libs/rt-thread-official
libs
/
rt-thread-official
mirror of https://github.com/RT-Thread/rt-thread.git
4
0
Fork 0
Code Issues Releases Wiki Activity

This commit is contained in:
toasun 2015-05-12 15:44:57 +08:00
parent bd59276640
commit a58078d18a
9 changed files with 8945 additions and 8758 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

111
bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h
View File

@ -1,12 +1,12 @@
/****************************************************************************************************//**
* @file CMEM7.h
* @file cmem7.h
*
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
* CMEM7 from <unknown Vendor>.
* cmem7 from <unknown Vendor>.
*
* @version V1.0
* @date 5. June 2014
* @date 5. January 2015
*
* @note Generated with SVDConv V2.75
* from CMSIS SVD File 'SVDConv_CME_M7.svd' Version 1.0,
@ -18,7 +18,7 @@
* @{
*/
/** @addtogroup CMEM7
/** @addtogroup cmem7
* @{
*/
@ -46,7 +46,7 @@ typedef enum {
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
/* ---------------------- CMEM7 Specific Interrupt Numbers ---------------------- */
/* ---------------------- cmem7 Specific Interrupt Numbers ---------------------- */
ETH_INT_IRQn = 0, /*!< 0 ETH_INT */
USB_INT_IRQn = 1, /*!< 1 USB_INT */
DMA_INT_IRQn = 2, /*!< 2 DMA_INT */
@ -105,7 +105,7 @@ typedef enum {
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
#include "system_cmem7.h" /*!< CMEM7 System */
#include "system_cmem7.h" /*!< cmem7 System */
/* ================================================================================ */
@ -789,17 +789,17 @@ typedef struct { /*!< RTC Structure
struct {
__IO uint32_t SECOND : 1; /*!< 1s interrupt, write 1 clear 0 */
__IO uint32_t MICROSECOND: 1; /*!< 1ms interrupt, write 1 clear 0 */
__IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt, write 1 clear 0 */
} INT_STATUS_b; /*!< BitSize */
};
__IO uint32_t SECOND; /*!< current seconds of system time */
union {
__IO uint16_t MICROSECOND; /*!< current micro seconds of system time */
__IO uint16_t MILLSECOND; /*!< current millseconds of system time */
struct {
__IO uint16_t MS : 10; /*!< micro seconds */
} MICROSECOND_b; /*!< BitSize */
} MILLSECOND_b; /*!< BitSize */
};
} RTC_Type;
@ -2884,9 +2884,35 @@ typedef struct { /*!< ETH Structure
are used to index the content */
} VLAN_TAG_b; /*!< BitSize */
};
__I uint32_t RESERVED0[8];
__I uint32_t RESERVED0[2];
__IO uint32_t RWUFFR; /*!< Remote Wake-Up Frame Filter Register */
union {
__IO uint32_t PMTCSR; /*!< PMT Control and Status Register */
struct {
__IO uint32_t PWRDWN : 1; /*!< Power Down */
__IO uint32_t MGKPKTEN : 1; /*!< Magic Packet Enable */
__IO uint32_t RWKPKTEN : 1; /*!< Remote Wake-Up Frame Enable */
uint32_t : 2;
__IO uint32_t MGKPRCVD : 1; /*!< the power management event is generated because of the reception
of a magic packet */
__IO uint32_t RWKPRCVD : 1; /*!< When set, this bit indicates the power management event is generated
because of the reception of a remote wake-up frame */
uint32_t : 2;
__IO uint32_t GLBLUCAST : 1; /*!< When set, enables any unicast packet filtered by the MAC (DAF)address
recognition to be a remote wake-up frame. */
uint32_t : 14;
__IO uint32_t RWKPTR : 3; /*!< Remote Wake-up FIFO Pointer */
uint32_t : 4;
__IO uint32_t RWKFILTRST : 1; /*!< Remote Wake-Up Frame Filter Register Pointer Reset. */
} PMTCSR_b; /*!< BitSize */
};
__I uint32_t RESERVED1[2];
__IO uint32_t MACISR; /*!< Interrupt Status Register */
__IO uint32_t MACIMR; /*!< Interrupt Mask Register */
__IO uint16_t ADDR0_HIGH; /*!< MAC Address0 High Register */
__I uint16_t RESERVED1;
__I uint16_t RESERVED2;
__IO uint32_t ADDR0_LOW; /*!< MAC Address0 LOW Register */
union {
@ -2901,10 +2927,51 @@ typedef struct { /*!< ETH Structure
} ADDR1_HIGH_b; /*!< BitSize */
};
__IO uint32_t ADDR1_LOW; /*!< MAC Address1 LOW Register */
__I uint32_t RESERVED2[47];
__IO uint32_t MMC_RX_MASK; /*!< MMC Receive interrupt mask */
__IO uint32_t MMC_TX_MASK; /*!< MMC Transmit Interrupt Mask */
__I uint32_t RESERVED3[955];
__I uint32_t RESERVED3[44];
union {
__IO uint32_t MMCCR; /*!< MMC Control Register */
struct {
__IO uint32_t CNTRST : 1; /*!< Counters Reset */
__IO uint32_t CNTSTOPRO : 1; /*!< Counter Stop Rollover */
__IO uint32_t RSTONRD : 1; /*!< Reset on Read */
__IO uint32_t CNTFREEZ : 1; /*!< MMC Counter Freeze */
__IO uint32_t CNTPRST : 1; /*!< Counters Preset */
__IO uint32_t CNTPRSTLVL : 1; /*!< Counters Preset */
uint32_t : 2;
__IO uint32_t UCDBC : 1; /*!< Update MMC Counters for Dropped Broadcast Frames */
} MMCCR_b; /*!< BitSize */
};
__IO uint32_t MMCRIR; /*!< MMC Receive Interrupt Register */
__IO uint32_t MMCTIR; /*!< MMC Transmit Interrupt Register */
__IO uint32_t MMCRIMR; /*!< MMC Receive interrupt mask */
__IO uint32_t MMCTIMR; /*!< MMC Transmit Interrupt Mask */
__I uint32_t RESERVED4[59];
__IO uint32_t MMCIRCOIM; /*!< MMC IPC Receive Checksum Offload Interrupt Mask */
__I uint32_t RESERVED5[319];
union {
__IO uint32_t PTPTSCR; /*!< Timestamp Control Register */
struct {
__IO uint32_t TSENA : 1; /*!< Timestamp Enable */
__IO uint32_t TSCFUPDT : 1; /*!< Timestamp Fine or Coarse Update */
__IO uint32_t TSINIT : 1; /*!< Timestamp Initialize */
__IO uint32_t TSUPDT : 1; /*!< Timestamp Update */
__IO uint32_t TSTRIG : 1; /*!< Timestamp Interrupt Trigger Enable */
__IO uint32_t TSADDREG : 1; /*!< Addend Reg Update */
} PTPTSCR_b; /*!< BitSize */
};
__IO uint32_t PTPSSIR; /*!< Sub-Second Increment Register */
__IO uint32_t PTPTSHR; /*!< System Time Seconds Register */
__IO uint32_t PTPTSLR; /*!< System Time Nanoseconds Register */
__IO uint32_t PTPTSHUR; /*!< System Time Seconds Update Register */
__IO uint32_t PTPTSLUR; /*!< System Time Nanoseconds Update Register */
__IO uint32_t PTPTSAR; /*!< Timestamp Addend Register */
__IO uint32_t PTPTTHR; /*!< Target Time Seconds Register */
__IO uint32_t PTPTTLR; /*!< Target Time Nanoseconds Register */
__I uint32_t RESERVED6[567];
union {
__IO uint32_t BUS_MODE; /*!< Flow Control Register */
@ -3019,7 +3086,7 @@ typedef struct { /*!< ETH Structure
__IO uint32_t NIE : 1; /*!< Normal Interrupt Summary Enable */
} INT_EN_b; /*!< BitSize */
};
__I uint32_t RESERVED4[3];
__I uint32_t RESERVED7[3];
union {
__IO uint32_t AHB_STATUS; /*!< AHB Status Register */
@ -3029,7 +3096,7 @@ typedef struct { /*!< ETH Structure
in the non-idle state */
} AHB_STATUS_b; /*!< BitSize */
};
__I uint32_t RESERVED5[6];
__I uint32_t RESERVED8[6];
__I uint32_t CURTDESAPTR; /*!< Current Host Transmit Descriptor Register */
__I uint32_t CURRDESAPTR; /*!< Current Host Receive Descriptor Register */
__I uint32_t CURTBUFAPTR; /*!< Current Host Transmit Buffer Address Register */
@ -7227,7 +7294,7 @@ typedef struct { /*!< GLOBAL_CTRL Structure
struct {
__IO uint32_t SECOND : 1; /*!< 1s interrupt enable */
__IO uint32_t MICROSECOND: 1; /*!< 1ms interrupt enable */
__IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt enable */
} RTC_INT_EN_b; /*!< BitSize */
};
__I uint32_t RESERVED1;
@ -7315,7 +7382,9 @@ typedef struct { /*!< DDRC Structure
__IO uint32_t MODE : 6; /*!< DDRC Mode */
uint32_t : 2;
__IO uint32_t LANE : 1; /*!< LANE synchronization logic bypass */
uint32_t : 7;
uint32_t : 3;
__IO uint32_t ADEC : 1; /*!< address decoder mapping */
uint32_t : 3;
__IO uint32_t B16 : 2; /*!< Active 16 bit DQ position when the unmber of DQ IO is 16 */
uint32_t : 6;
__IO uint32_t CLKPOL : 2; /*!< DQS clkpol set by user on the PHY */
@ -7933,7 +8002,7 @@ typedef struct { /*!< SOFT_RESET Structure
/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group CMEM7 */
/** @} */ /* End of group cmem7 */
/** @} */ /* End of group (null) */
#ifdef __cplusplus
@ -7941,5 +8010,5 @@ typedef struct { /*!< SOFT_RESET Structure
#endif
#endif /* CMEM7_H */
#endif /* cmem7_H */

9
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h
View File

@ -45,6 +45,11 @@
#define _USB
#define _WDG
//#define _MARVELL
//#define _IP1826D
#define _M7NORFLASH
#define _ME_6095_F
#define USE_FULL_ASSERT 1
#ifdef USE_FULL_ASSERT
@ -71,7 +76,9 @@ typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL;
/**
* System clock frequency, unit is Hz.
*/
#define SYSTEM_CLOCK_FREQ 200000000
#define SYSTEM_CLOCK_FREQ 300000000
//250000000
//300000000
/**
* @brief usecond delay

65
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h
View File

@ -86,7 +86,6 @@
/**
* @}
*/
/**
* @brief EFUSE receive filter structure
*/
@ -105,15 +104,15 @@ typedef struct
*/
typedef struct
{
BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */
BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */
uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */
uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */
uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */
BOOL ETH_RxEn; /*!< Rx enable */
BOOL ETH_TxEn; /*!< Tx enable */
BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */
BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */
uint8_t ETH_MacAddr[6]; /*!< MAC address */
ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */
ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */
} ETH_InitTypeDef;
/**
@ -173,14 +172,14 @@ typedef struct {
uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */
uint32_t : 5;
uint32_t TTSE : 1; /*!< timestamp available while last segment */
uint32_t LS : 1; /*!< last segment flag */
uint32_t FS : 1; /*!< first segment flag */
uint32_t LS : 1; /*!< [OUT] last segment flag */
uint32_t FS : 1; /*!< [OUT] first segment flag */
uint32_t : 1;
uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */
uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */
uint32_t : 2;
uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */
uint32_t FL : 14; /*!< frame length while last segment */
uint32_t FL : 14; /*!< [OUT] frame length while last segment */
uint32_t : 2;
} RX0_b;
} RX_0;
@ -216,7 +215,13 @@ uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
* @retval None
*/
void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data);
/**
* @brief Fills each ETH_InitStruct member with its default value.
* @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void ETH_StructInit(ETH_InitTypeDef* init);
/**
* @brief Ethernet initialization
* @note This function should be called at first before any other interfaces.
@ -231,21 +236,21 @@ BOOL ETH_Init(ETH_InitTypeDef *init);
* @param[in] Enable The bit indicates if specific interrupts are enable or not
* @retval None
*/
void ETH_EnableInt(uint32_t Int, BOOL enable);
void ETH_ITConfig(uint32_t Int, BOOL enable);
/**
* @brief Check specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @retval BOOL The bit indicates if specific interrupts are set or not
*/
BOOL ETH_GetIntStatus(uint32_t Int);
BOOL ETH_GetITStatus(uint32_t Int);
/**
* @brief Clear specific interrupts
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @retval None
*/
void ETH_ClearInt(uint32_t Int);
void ETH_ClearITPendingBit(uint32_t Int);
/**
* @brief Get ethernte MAC address
@ -299,7 +304,7 @@ ETH_TX_DESC *ETH_AcquireFreeTxDesc(void);
/**
* @brief Check if a transmission descriptor is free or not
* @param desc A pointer of a transmission descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval BOOL True if the transmission descriptor is free, or flase.
*/
BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
@ -309,11 +314,26 @@ BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
* After users prepared data in the buffer of a free descriptor,
* They must call this function to change ownership of the
* descriptor to hardware.
* @param desc A pointer of a transmission descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval None
*/
void ETH_ReleaseTxDesc(ETH_TX_DESC *desc);
/**
* @brief Set buffer address of the specific TX descriptor
* @param[in] desc A pointer of a transmission descriptor
* @param[in] bufAddr buffer address to be sent
* @retval None
*/
void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr);
/**
* @brief Get buffer address of the specific TX descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval uint32_t buffer address to be gotten
*/
uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc);
/**
* @brief Set ethernet receive descriptor ring
* @note Make sure that memory occupied by descriptors should be in physical
@ -359,7 +379,7 @@ ETH_RX_DESC *ETH_AcquireFreeRxDesc(void);
/**
* @brief Check if a receive descriptor is free or not
* @param desc A pointer of a receive descriptor
* @param[in] desc A pointer of a receive descriptor
* @retval BOOL True if the receive descriptor is free, or flase.
*/
BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
@ -369,11 +389,26 @@ BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
* After users handled data in the buffer of a free descriptor,
* They must call this function to change ownership of the
* descriptor to hardware.
* @param desc A pointer of a transmission descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval None
*/
void ETH_ReleaseRxDesc(ETH_RX_DESC *desc);
/**
* @brief Set buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @param[in] bufAddr buffer address to be received
* @retval None
*/
void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr);
/**
* @brief Get buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @retval uint32_t buffer address to be gotten
*/
uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc);
#ifdef __cplusplus
}
#endif

8
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h
View File

@ -202,6 +202,14 @@ void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data);
*/
void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data);
void flash_WaitInWritting(void) ;
void flash_WaitReadFifoNotEmpty(void);
uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) ;
#ifdef __cplusplus
}
#endif

11
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h
View File

@ -140,6 +140,17 @@ void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLev
*/
void GPIO_EnablePwm(uint8_t Channel, BOOL Enable);
/**
xjf 20150324
**/
void GPIO_SetBits(uint32_t mask);
void GPIO_clrBits(uint32_t mask);
uint32_t GPIO_getBits(uint32_t mask);
#ifdef __cplusplus
}
#endif

10
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h
View File

@ -102,6 +102,16 @@
#include "cmem7_wdg.h"
#endif
#ifdef _MARVELL
#include <marvel_98dx242.h>
#include <s24g_i2c.h>
#endif
#ifdef _IP1826D
#include <ip1826d_v00.h>
#endif
#ifdef __cplusplus
}
#endif

42
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h
View File

@ -87,9 +87,11 @@ typedef struct
* @{
*/
#define NVIC_VectTab_CME_CODE ((uint32_t)0x00000000)
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \
((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
@ -197,6 +199,20 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
*/
void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
/**
* @brief Convert the mapping destination address to source address
* @param[in] to address to be mapped to
* @retval uint32_t address to be mapped from
*/
uint32_t GLB_ConvertToMappingFromAddr(uint32_t to);
/**
* @brief Convert the mapping source address to destination address
* @param[in] from address to be mapped from
* @retval uint32_t address to be mapped to
*/
uint32_t GLB_ConvertToMappingToAddr(uint32_t from);
/**
* @brief Set NMI irq number, it should be one of @ref IRQn_Type.
* @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI
@ -228,6 +244,30 @@ void GLB_SetNmiIrqNum(uint32_t irq);
*/
void GLB_SelectSysClkSource(uint8_t source);
/**
* @brief Simulate instruction 'STRB' or 'STRH' with 'BFI'
* @Note In M7, you have to write a register in 32-bit alignment,
* not in 8-bit or 16-bit.
* @param[in] addr register address to be written
* @param[in] value value to be written
* @param[in] lsb LSB in register to be written
* @param[in] len bit length to be written
* @retval None
*/
//#define aaaa(len) __asm("LDR len, 11")
#define CMEM7_BFI(addr, value, lsb, len) \
do { \
unsigned long tmp; \
unsigned long tmp1 = (unsigned long)addr; \
\
__asm("LDR tmp, [tmp1]\n" \
"BFI tmp, "#value", "#lsb", "#len" \n" \
"STR tmp, [tmp1]\n"); \
} while (0)
#ifdef __cplusplus
}
#endif

14
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h
View File

@ -38,7 +38,7 @@
* @{
*/
#define RTC_Int_Second ((uint32_t)0x00000001)
#define RTC_Int_Microsecond ((uint32_t)0x00000002)
#define RTC_Int_Millsecond ((uint32_t)0x00000002)
#define RTC_Int_All ((uint32_t)0x00000003)
#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0))
/**
@ -51,21 +51,21 @@
* @param[in] Enable The bit indicates if specific interrupts are enable or not
* @retval None
*/
void RTC_EnableInt(uint32_t Int, BOOL Enable);
void RTC_ITConfig(uint32_t Int, BOOL Enable);
/**
* @brief Check specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval BOOL The bit indicates if specific interrupts are set or not
*/
BOOL RTC_GetIntStatus(uint32_t Int);
BOOL RTC_GetITStatus(uint32_t Int);
/**
* @brief Clear specific interrupts
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval None
*/
void RTC_ClearInt(uint32_t Int);
void RTC_ClearITPendingBit(uint32_t Int);
/**
* @brief Get seconds since power up
@ -75,11 +75,11 @@ void RTC_ClearInt(uint32_t Int);
uint32_t RTC_GetSecond(void);
/**
* @brief Get current micro-seconds
* @brief Get current millseconds
* @param None
* @retval uint32_t Current micro-seconds
* @retval uint32_t Current millseconds
*/
uint16_t RTC_GetMicroSecond(void);
uint16_t RTC_GetMillSecond(void);
#ifdef __cplusplus
}

19
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h
View File

@ -56,14 +56,21 @@
* @}
*/
/**
* @brief Deinitializes the Watchdog peripheral registers to their default reset values.
* @param[in] None
* @retval None
*/
void WDG_DeInit(void);
/**
* @brief Watchdog initialization
* @note This function should be called at first before any other interfaces.
* @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
* @param[in] ResetMicroSecond MicroSeconds lasts before global reset
* @param[in] ResetMillSecond MillSeconds lasts before global reset
* @retval None
*/
void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond);
void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond);
/**
* @brief Enable or disable watchdog interrupt.
@ -71,28 +78,28 @@ void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond);
* @param[in] Enable The bit indicates if the specific interrupt are enable or not
* @retval None
*/
void WDG_EnableInt(uint8_t Int, BOOL Enable);
void WDG_ITConfig(uint8_t Int, BOOL Enable);
/**
* @brief Check the specific interrupt are set or not
* @param None
* @retval BOOL The bit indicates if the specific interrupt are set or not
*/
BOOL WDG_GetIntStatus(void);
BOOL WDG_GetITStatus(void);
/**
* @brief Clear the specific interrupt
* @param None
* @retval None
*/
void WDG_ClearInt(void);
void WDG_ClearITPendingBit(void);
/**
* @brief Enable or disable watchdog.
* @param[in] Enable The bit indicates if watchdog is enable or not
* @retval None
*/
void WDG_Enable(BOOL Enable);
void WDG_Cmd(BOOL Enable);
#ifdef __cplusplus