From a4a59532567766a250ae6c51ce5e1a465a05027a Mon Sep 17 00:00:00 2001 From: Yaochenger <1516081466@qq.com> Date: Thu, 25 Jul 2024 17:40:56 +0800 Subject: [PATCH] [bsp][ch32] add eth driver --- .../risc-v/Libraries/ch32_drivers/SConscript | 3 + .../risc-v/Libraries/ch32_drivers/drv_eth.c | 775 ++++++++++++++++++ .../risc-v/Libraries/ch32_drivers/drv_eth.h | 50 ++ bsp/wch/risc-v/ch32v307v-r1/.config | 163 +++- bsp/wch/risc-v/ch32v307v-r1/board/Kconfig | 7 + bsp/wch/risc-v/ch32v307v-r1/rtconfig.h | 89 +- bsp/wch/risc-v/ch32v307v-r1/rtconfig.py | 2 +- libcpu/risc-v/common/context_gcc.S | 3 + 8 files changed, 1055 insertions(+), 37 deletions(-) create mode 100644 bsp/wch/risc-v/Libraries/ch32_drivers/drv_eth.c create mode 100644 bsp/wch/risc-v/Libraries/ch32_drivers/drv_eth.h diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript b/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript index 7d462d7f4a..3b8e88aa83 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript @@ -36,6 +36,9 @@ if GetDepend('SOC_RISCV_FAMILY_CH32'): if GetDepend('BSP_USING_USBD'): src += ['drv_usbd.c'] + if GetDepend('BSP_USING_ETH'): + src += ['drv_eth.c'] + if GetDepend('BSP_USING_IWDT'): src += ['drv_iwdt.c'] diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_eth.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_eth.c new file mode 100644 index 0000000000..b46dbe1da4 --- /dev/null +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_eth.c @@ -0,0 +1,775 @@ +/* + * File : drv_usart.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2024, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WCH the first version + */ + +#include "board.h" +#include + + +#ifdef BSP_USING_ETH +#include +#include "lwipopts.h" +#include + +//#define DRV_DEBUG +#define LOG_TAG "drv.eth" +#include + +#define MAX_ADDR_LEN 6 +#define ETH_DMARxDesc_FrameLengthShift 16 + +#define define_O(a,b) \ +GPIO_InitStructure.GPIO_Pin = b;\ +GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\ +GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\ +GPIO_Init(a, &GPIO_InitStructure) + +#define define_I(a,b) \ +GPIO_InitStructure.GPIO_Pin = b;\ +GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\ +GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;\ +GPIO_Init(a, &GPIO_InitStructure) + + +/* globe variable */ +extern ETH_DMADESCTypeDef *DMATxDescToSet; //set tx Desc then send it +extern ETH_DMADESCTypeDef *DMARxDescToGet; //current rx Desc + + +/* rt-thread eth */ +struct rt_ch32_eth +{ + /* inherit from ethernet device */ + struct eth_device parent; +#ifndef PHY_USING_INTERRUPT_MODE + rt_timer_t poll_link_timer; +#endif + /* interface address info, hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + /* ETH_Speed */ + uint32_t ETH_Speed; + /* ETH_Duplex_Mode */ + uint32_t ETH_Mode; +}; + +static ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB]; +static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE],Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE]; +struct rt_ch32_eth ch32v30x_eth_device; + + +//#define ETH_RX_DUMP +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%02X ", buf[i + j]); + else + rt_kprintf(" "); + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + rt_kprintf("\r\n"); + } +} +#endif + + +/* received data */ +FrameTypeDef ETH_RxPkt_ChainMode(void) +{ + u32 framelength = 0; + FrameTypeDef frame = {0,0,NULL}; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET) + { + frame.length = ETH_ERROR; + if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + LOG_E("Error:ETH_DMARxDesc_OWN.\r\n"); + /* Return error: OWN bit set */ + return frame; + } + + if( + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (u32)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (u32)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (u32)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + + /* Get the addrees of the actual buffer */ + frame.buffer = DMARxDescToGet->Buffer1Addr; + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + rt_kprintf("Error:recv error frame,status:0x%08x.\r\n",DMARxDescToGet->Status); + } + DMARxDescToGet->Status|=ETH_DMARxDesc_OWN; + frame.length = framelength; + frame.descriptor = DMARxDescToGet; + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + /* Return Frame */ + return (frame); +} + + + +/******************************************************************************* +* Function Name : GETH_pin_init +* Description : PHY RGMII interface GPIO initialization. +* Input : None. +* Return : None. +*******************************************************************************/ +void GETH_pin_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* PB12/13 set AF_PP_OUT */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC, ENABLE); + GPIOB->CFGHR&=~(0xff<<16); + GPIOB->CFGHR|= (0xbb<<16); + GPIOB->CFGLR&=~(0xff<<4); + + define_O(GPIOA,GPIO_Pin_2); + define_O(GPIOA,GPIO_Pin_3); + define_O(GPIOA,GPIO_Pin_7); + define_O(GPIOC,GPIO_Pin_4); + define_O(GPIOC,GPIO_Pin_5); + define_O(GPIOB,GPIO_Pin_0); + + define_I(GPIOC,GPIO_Pin_0); + define_I(GPIOC,GPIO_Pin_1); + define_I(GPIOC,GPIO_Pin_2); + define_I(GPIOC,GPIO_Pin_3); + define_I(GPIOA,GPIO_Pin_0); + define_I(GPIOA,GPIO_Pin_1); + + define_I(GPIOB,GPIO_Pin_1);/* 125m in */ +} + + +/******************************************************************************* +* Function Name : GETH_pin_init +* Description : PHY MII/RMII interface GPIO initialization. +* Input : None. +* Return : None. +*******************************************************************************/ +void FETH_pin_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + +#ifdef USE_RMII + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC|RCC_APB2Periph_AFIO, ENABLE); + GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII); + define_O(GPIOA,GPIO_Pin_2);/* MDC */ + define_O(GPIOC,GPIO_Pin_1);/* MDIO */ + + define_O(GPIOB,GPIO_Pin_11);//txen + define_O(GPIOB,GPIO_Pin_12);//txd0 + define_O(GPIOB,GPIO_Pin_13);//txd1 + + define_I(GPIOA,GPIO_Pin_1);/* PA1 REFCLK */ + define_I(GPIOA,GPIO_Pin_7);/* PA7 CRSDV */ + define_I(GPIOC,GPIO_Pin_4);/* RXD0 */ + define_I(GPIOC,GPIO_Pin_5);/* RXD1 */ + +#else + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC, ENABLE); + /* tx */ + define_O(GPIOA,GPIO_Pin_2);/* MDC */ + define_O(GPIOC,GPIO_Pin_1);/* MDIO */ + + define_I(GPIOC,GPIO_Pin_3);//txclk + define_O(GPIOB,GPIO_Pin_11);//txen + define_O(GPIOB,GPIO_Pin_12);//txd0 + define_O(GPIOB,GPIO_Pin_13);//txd1 + define_O(GPIOC,GPIO_Pin_2); //txd2 + define_O(GPIOB,GPIO_Pin_8);//txd3 + /* tx */ + define_I(GPIOA,GPIO_Pin_1);/* PA1 RXC */ + define_I(GPIOA,GPIO_Pin_7);/* PA7 RXDV */ + define_I(GPIOC,GPIO_Pin_4);/* RXD0 */ + define_I(GPIOC,GPIO_Pin_5);/* RXD1 */ + define_I(GPIOB,GPIO_Pin_0);/* RXD2 */ + define_I(GPIOB,GPIO_Pin_1);/* RXD3 */ + define_I(GPIOB,GPIO_Pin_10);/* RXER */ + + define_O(GPIOA,GPIO_Pin_0);/* PA0 */ + define_O(GPIOA,GPIO_Pin_3);/* PA3 */ +#endif +} + +/******************************************************************************* +* Function Name : ETH_Init +* Description : ETH initialization. +* Input : ETH_InitStruct:initialization struct. +* PHYAddress:PHY address. +* Return : Initialization status. +*******************************************************************************/ +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) +{ + uint32_t tmpreg = 0; + uint16_t RegValue = 0; + uint32_t tickstart=0; + /* config phy */ + tmpreg = ETH->MACMIIAR; + tmpreg &= MACMIIAR_CR_MASK; + /* set SMI clock */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + ETH->MACMIIAR = (uint32_t)tmpreg; + /* reset phy */ + ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset); + tickstart= rt_tick_get_millisecond(); + do{ + asm("nop"); /* waiting for finish */ + }while((rt_tick_get_millisecond()-tickstart)<1000); + + + tickstart= rt_tick_get_millisecond(); + RegValue = 0; + while( (RegValue&(PHY_Reset)) ) + { + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + if((rt_tick_get_millisecond()-tickstart)>10000) + { + LOG_E("Error:Wait phy reset timeout!\r\n"); + while(1); + } + } + + /* waiting for link up */ + tickstart= rt_tick_get_millisecond(); + RegValue = 0; + while((RegValue&(PHY_Linked_Status)) == 0) + { + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BSR); + if((rt_tick_get_millisecond()-tickstart)>10000) + { + LOG_E("Error:Wait phy linking timeout!\r\n"); + while(1); + } + } + + /* waiting for auto-negotiation */ + tickstart= rt_tick_get_millisecond(); + RegValue = 0; + while((RegValue&PHY_AutoNego_Complete) == 0) + { + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BSR); + if((rt_tick_get_millisecond()-tickstart)>10000) + { + LOG_E("Error:Wait phy auto-negotiation complete timeout!\r\n"); + while(1); + } + } + +#ifdef USE10BASE_T + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BMCR); + LOG_D("PHY_BMCR:%d,value:%04x.\n",PHY_BMCR,RegValue); + if((RegValue & (1<<8)) != (uint32_t)RESET) + { + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + ch32v30x_eth_device.ETH_Mode=ETH_Mode_FullDuplex; + LOG_D("Full-Duplex.\n"); + } + else + { + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ch32v30x_eth_device.ETH_Mode=ETH_Mode_HalfDuplex; + LOG_D("Half-Duplex.\n"); + } + if(RegValue & (1<<13)) + { + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + ch32v30x_eth_device.ETH_Speed=ETH_Speed_100M; + /* send link up. */ + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:100M.\n"); + } + else + { + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ch32v30x_eth_device.ETH_Speed=ETH_Speed_10M; + /* send link up. */ + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:10M.\n"); + } +#endif + +#ifdef USE_FAST_MAC + /* 100M MAC,RMII */ + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BMCR); + LOG_D("PHY_BMCR:%d,value:%04x.\n",PHY_BMCR,RegValue); + if((RegValue & (1<<8)) != (uint32_t)RESET) + { + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + ch32v30x_eth_device.ETH_Mode = ETH_Mode_FullDuplex; + LOG_D("Full-Duplex.\n"); + } + else + { + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ch32v30x_eth_device.ETH_Mode = ETH_Mode_HalfDuplex; + LOG_D("Half-Duplex.\n"); + } + if(RegValue & (1<<13)) + { + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + ch32v30x_eth_device.ETH_Speed=ETH_Speed_100M; + /* send link up. */ + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:100M.\n"); + } + else + { + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ch32v30x_eth_device.ETH_Speed=ETH_Speed_10M; + /* send link up. */ + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:10M.\n"); + } +#endif + +#ifdef USE_GIGA_MAC + /* GMAC,RGMI */ + ETH_WritePHYRegister(PHYAddress, 31,0x0a43 ); + RegValue = ETH_ReadPHYRegister(PHYAddress, 26); + if( RegValue & 0x0008 ) + { + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + ch32v30x_eth_device.ETH_Mode = ETH_Mode_FullDuplex; + LOG_D("full duplex.\n"); + } + else + { + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ch32v30x_eth_device.ETH_Mode = ETH_Mode_HalfDuplex; + LOG_D("half duplex!\n"); + } + if(( RegValue & 0x0030 ) == 0x0000) + { + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ch32v30x_eth_device.ETH_Speed= ETH_Speed_10M; + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:10Mbps.\n"); + } + else if(( RegValue & 0x0030 ) == 0x0010) + { + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + ch32v30x_eth_device.ETH_Speed= ETH_Speed_100M; + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:100Mbps.\n"); + } + else if(( RegValue & 0x0030 ) == 0x0020) + { + ETH_InitStruct->ETH_Speed = ETH_Speed_1000M; + ch32v30x_eth_device.ETH_Speed= ETH_Speed_1000M; + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:1000Mbps.\n"); + } +#endif + + tickstart= rt_tick_get_millisecond(); + do{ + asm("nop"); + }while((rt_tick_get_millisecond()-tickstart)<1000); + + + /* MAC config */ + /* if use RGMII,should config RGMII clock delay register */ + tmpreg = ETH->MACCR; + tmpreg &= MACCR_CLEAR_MASK; + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_CarrierSense | + ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_ReceiveOwn | + ETH_InitStruct->ETH_LoopbackMode | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_DeferralCheck); + ETH->MACCR = (uint32_t)tmpreg; +#ifdef USE10BASE_T + /* enable internal pull up resistance,50Ω */ + ETH->MACCR|=ETH_Internal_Pull_Up_Res_Enable; +#endif + ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); + /* Write to ETHERNET MACHTHR */ + ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; + /* Write to ETHERNET MACHTLR */ + ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; + /* Get the ETHERNET MACFCR value */ + tmpreg = ETH->MACFCR; + /* Clear xx bits */ + tmpreg &= MACFCR_CLEAR_MASK; + + tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | + ETH_InitStruct->ETH_ZeroQuantaPause | + ETH_InitStruct->ETH_PauseLowThreshold | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); + ETH->MACFCR = (uint32_t)tmpreg; + + ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + + tmpreg = ETH->DMAOMR; + /* Clear xx bits */ + tmpreg &= DMAOMR_CLEAR_MASK; + + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + ETH_InitStruct->ETH_ReceiveStoreForward | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitThresholdControl | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); + ETH->DMAOMR = (uint32_t)tmpreg; + + ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | + ETH_InitStruct->ETH_FixedBurst | + ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->ETH_TxDMABurstLength | + (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | + ETH_InitStruct->ETH_DMAArbitration | + ETH_DMABMR_USP); + + return ETH_SUCCESS; +} + +/* eth initialization function */ +static rt_err_t rt_ch32_eth_init(rt_device_t dev) +{ + ETH_InitTypeDef ETH_InitStructure={0}; + RCC_PLL3Cmd(DISABLE); + RCC_PREDIV2Config(RCC_PREDIV2_Div2); + RCC_PLL3Config(RCC_PLL3Mul_15); + RCC_PLL3Cmd(ENABLE); + while(RESET == RCC_GetFlagStatus(RCC_FLAG_PLL3RDY)); + LOG_D("PLL3 Init Finish\r\n"); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC|RCC_AHBPeriph_ETH_MAC_Tx|RCC_AHBPeriph_ETH_MAC_Rx,ENABLE); +#ifdef USE10BASE_T + /* Enable internal 10BASE-T PHY*/ + EXTEN->EXTEN_CTR |=EXTEN_ETH_10M_EN; +#endif +#ifdef USE_GIGA_MAC + /* Enable 1G MAC*/ + EXTEN->EXTEN_CTR |= EXTEN_ETH_RGMII_SEL; + /* mac clock use external 125MHz,input from PB1 */ + RCC_ETH1GCLKConfig(RCC_ETH1GCLKSource_PB1_IN); + RCC_ETH1G_125Mcmd(ENABLE); + /* Enable RGMII GPIO */ + GETH_pin_init(); +#endif + +#ifdef USE_FAST_MAC + /* Enable MII or RMII GPIO */ + FETH_pin_init(); +#endif + /* Reset ETHERNET on AHB Bus */ + ETH_DeInit(); + /* Software reset */ + ETH_SoftwareReset(); + /* Wait for software reset */ + while(ETH->DMABMR & ETH_DMABMR_SR); + LOG_D("ETH RST Finish\r\n"); + + ETH_StructInit(Ð_InitStructure); + ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; + ETH_InitStructure.ETH_Speed = ETH_Speed_1000M; + ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable ; + ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; + ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; + ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable; + ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Enable; + ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; +#ifdef CHECKSUM_BY_HARDWARE + ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; +#endif + /*------------------------ DMA -----------------------------------*/ + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: + the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, + if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ + ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; + ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable; + ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable; + ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; + ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; + ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; + ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1; + /* Configure Ethernet */ + ETH_Init(Ð_InitStructure, PHY_ADDRESS); + /* Enable the Ethernet Rx Interrupt */ + ETH_DMAITConfig(ETH_DMA_IT_NIS + | ETH_DMA_IT_R + | ETH_DMA_IT_T + ,ENABLE); + NVIC_SetPriority(ETH_IRQn,1<<4); + NVIC_EnableIRQ(ETH_IRQn); + ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); + ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); +#ifdef USE_GIGA_MAC + RGMII_TXC_Delay(0,2); +#endif + ETH_Start(); + return RT_EOK; +} + +static rt_err_t rt_ch32_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + LOG_D("eth open\r\n"); + return RT_EOK; +} + +static rt_err_t rt_ch32_eth_close(rt_device_t dev) +{ + LOG_D("eth close\r\n"); + return RT_EOK; +} + +static rt_ssize_t rt_ch32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + LOG_D("eth read\r\n"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_ssize_t rt_ch32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + LOG_D("eth write\r\n"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + + +static rt_err_t rt_ch32_eth_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, ch32v30x_eth_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +rt_err_t rt_ch32_eth_tx(rt_device_t dev, struct pbuf *p) +{ + rt_err_t ret = RT_ERROR; + struct pbuf *q; + uint8_t *buffer = (uint8_t *)(DMATxDescToSet->Buffer1Addr); + uint8_t *pdata; + uint32_t framelength = 0,len=0; + /* copy frame from pbufs to driver buffers */ + for (q = p; q != NULL; q = q->next) + { + /* Is this buffer available? If not, goto error */ + if ((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + LOG_E("buffer not valid\r\n"); + ret = ERR_USE; + goto Tx_error; + } + + pdata = q->payload; + len = q->len; + framelength += len; + rt_memcpy(buffer,pdata,len); + buffer += len; + } + +#ifdef ETH_TX_DUMP + dump_hex(buffer, p->tot_len); +#endif + + DMATxDescToSet->ControlBufferSize = (framelength & ETH_DMATxDesc_TBS1); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + ret = ERR_OK; + + Tx_error: + /* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + return ret; +} + + +volatile FrameTypeDef frame; +struct pbuf *rt_ch32_eth_rx(rt_device_t dev) +{ + struct pbuf *p = NULL; + struct pbuf *q = NULL; + uint16_t len = 0; + uint8_t *buffer; + uint8_t *pdata; + + if(!frame.length) + { + return NULL; + } + len=frame.length; + frame.length=0; + buffer=(uint8_t *)frame.buffer; + if (len > 0) + { + /* We allocate a pbuf chain of pbufs from the Lwip buffer pool */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + } +#ifdef ETH_RX_DUMP + dump_hex(buffer, p->tot_len); +#endif + if (p != NULL) + { + for (q = p; q != NULL; q = q->next) + { + pdata = q->payload; + rt_memcpy(pdata,buffer,q->len); + pdata += (q->len); + buffer += (q->len); + } + } + else + { + LOG_E("p=null\r\n"); + } + return p; + } + +/* interrupt service routine */ +void ETH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void ETH_IRQHandler(void) +{ + GET_INT_SP(); + /* enter interrupt */ + rt_err_t result; + rt_interrupt_enter(); + if(ETH->DMASRÐ_DMA_IT_R) + { + ETH_DMAClearITPendingBit(ETH_DMA_IT_R); + frame = ETH_RxPkt_ChainMode(); + result = eth_device_ready(&(ch32v30x_eth_device.parent)); + if (result != RT_EOK) + rt_kprintf("RxCpltCallback err = %d\r\n", result); + } + if(ETH->DMASRÐ_DMA_IT_T) + { + ETH_DMAClearITPendingBit(ETH_DMA_IT_T); + } + ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS); + /* leave interrupt */ + rt_interrupt_leave(); + FREE_INT_SP(); +} + + +/* Register the EMAC device */ +static int rt_hw_ch32_eth_init(void) +{ + rt_err_t state = RT_EOK; + /* 84-c2-e4 WCH. */ + ch32v30x_eth_device.dev_addr[0] = 0x84; + ch32v30x_eth_device.dev_addr[1] = 0xc2; + ch32v30x_eth_device.dev_addr[2] = 0xe4; + /* generate MAC (only for test). */ + ch32v30x_eth_device.dev_addr[3] = 0x1; + ch32v30x_eth_device.dev_addr[4] = 0x2; + ch32v30x_eth_device.dev_addr[5] = 0x3; + + ch32v30x_eth_device.parent.parent.init = rt_ch32_eth_init; + ch32v30x_eth_device.parent.parent.open = rt_ch32_eth_open; + ch32v30x_eth_device.parent.parent.close = rt_ch32_eth_close; + ch32v30x_eth_device.parent.parent.read = rt_ch32_eth_read; + ch32v30x_eth_device.parent.parent.write = rt_ch32_eth_write; + ch32v30x_eth_device.parent.parent.control = rt_ch32_eth_control; + ch32v30x_eth_device.parent.parent.user_data = RT_NULL; + + ch32v30x_eth_device.parent.eth_rx = rt_ch32_eth_rx; + ch32v30x_eth_device.parent.eth_tx = rt_ch32_eth_tx; + + /* register eth device */ + state = eth_device_init(&(ch32v30x_eth_device.parent), "e0"); + if (RT_EOK == state) + { + LOG_D("emac device init success"); + } + else + { + LOG_E("emac device init faild: %d\r\n", state); + state = -RT_ERROR; + } + + return state; +} +INIT_DEVICE_EXPORT(rt_hw_ch32_eth_init); + +#endif /* BSP_USING_ETH */ diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_eth.h b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_eth.h new file mode 100644 index 0000000000..40c9e5214e --- /dev/null +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_eth.h @@ -0,0 +1,50 @@ +/* + * File : usart.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WCH the first version + */ +#ifndef __DRV_ETH_H__ +#define __DRV_ETH_H__ +#include "rthw.h" +#include "rtthread.h" +#include "ch32v30x_eth.h" + + +/* MII/MDI interface select */ +#define PHY_ADDRESS 0x01 +#define USE10BASE_T + +#ifndef USE10BASE_T + #define USE_GIGA_MAC + #ifndef USE_GIGA_MAC + #define USE_FAST_MAC + //#define USE_RMII + #endif +#endif + +#define ETH_RXBUFNB 6 +#define ETH_TXBUFNB 6 + +#if 0 +#define USE_LOOP_STRUCT 1 +#else +#define USE_CHAIN_STRUCT 1 +#endif + + +typedef struct +{ + u32 length; + u32 buffer; + ETH_DMADESCTypeDef *descriptor; +}FrameTypeDef; + +#endif diff --git a/bsp/wch/risc-v/ch32v307v-r1/.config b/bsp/wch/risc-v/ch32v307v-r1/.config index 060fc9bc4c..24714bde0d 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/.config +++ b/bsp/wch/risc-v/ch32v307v-r1/.config @@ -1,7 +1,3 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# # # RT-Thread Kernel @@ -18,7 +14,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -# CONFIG_RT_USING_OVERFLOW_CHECK is not set CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -28,18 +23,29 @@ CONFIG_IDLE_THREAD_STACK_SIZE=256 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization # -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# end of kservice optimization + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# end of klibc optimization + CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_OVERFLOW_CHECK is not set # # Inter-Thread communication @@ -51,6 +57,7 @@ CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication # # Memory Management @@ -67,6 +74,8 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMTRACE is not set # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y +# end of Memory Management + CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set @@ -75,14 +84,12 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x50100 +CONFIG_RT_VER_NUM=0x50200 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 -# CONFIG_RT_USING_CACHE is not set +# end of RT-Thread Kernel + CONFIG_RT_USING_HW_ATOMIC=y -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set CONFIG_ARCH_RISCV=y # @@ -97,8 +104,8 @@ CONFIG_RT_USING_MSH=y CONFIG_RT_USING_FINSH=y CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=1024 +CONFIG_FINSH_THREAD_PRIORITY=11 +CONFIG_FINSH_THREAD_STACK_SIZE=2048 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y @@ -114,12 +121,15 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # DFS: device virtual file system # # CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + # CONFIG_RT_USING_FAL is not set # # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set @@ -138,6 +148,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -150,21 +162,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers # # C/C++ and POSIX layer @@ -182,6 +186,8 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer # # POSIX (Portable Operating System Interface) layer @@ -203,7 +209,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # Socket is in the 'Network' category # +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + # CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer # # Network @@ -212,12 +222,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_NETDEV is not set # CONFIG_RT_USING_LWIP is not set # CONFIG_RT_USING_AT is not set +# end of Network # # Memory protection # # CONFIG_RT_USING_MEM_PROTECTION is not set # CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection # # Utilities @@ -229,12 +241,25 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + # CONFIG_RT_USING_VBUS is not set +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + # # RT-Thread Utestcases # # CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases # # RT-Thread online packages @@ -243,7 +268,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # IoT - internet of things # -# CONFIG_PKG_USING_LWIP is not set # CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_UMQTT is not set @@ -256,6 +280,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -265,27 +290,35 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # Marvell WiFi # # CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi # # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + # CONFIG_PKG_USING_RW007 is not set # # CYW43012 WiFi # # CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi # # BL808 WiFi # # CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi # # CYW43439 WiFi # # CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set @@ -308,6 +341,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set @@ -350,6 +385,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things # # security packages @@ -360,6 +397,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set # CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages # # language packages @@ -375,18 +413,22 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format # # XML: Extensible Markup Language # # CONFIG_PKG_USING_SIMPLE_XML is not set # CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + # CONFIG_PKG_USING_LUATOS_SOC is not set # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set # CONFIG_PKG_USING_PIKASCRIPT is not set # CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages # # multimedia packages @@ -398,12 +440,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library # # u8g2: a monochrome graphic library # # CONFIG_PKG_USING_U8G2_OFFICIAL is not set # CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -423,6 +468,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages # # tools packages @@ -471,6 +517,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set # CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages # # system packages @@ -482,6 +529,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set # # acceleration: Assembly language or algorithmic acceleration packages @@ -489,6 +539,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages # # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard @@ -499,6 +550,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # Micrium: Micrium software products porting for RT-Thread @@ -509,6 +561,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_LITEOS_SDK is not set # CONFIG_PKG_USING_TZ_DATABASE is not set @@ -556,6 +610,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RTP is not set # CONFIG_PKG_USING_REB is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages # # peripheral libraries and drivers @@ -568,9 +623,27 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -580,10 +653,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_K210_SDK is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers # # sensors drivers @@ -653,6 +729,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers # # touch drivers @@ -667,6 +744,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_XPT2046_TOUCH is not set # CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -739,6 +818,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_BT_MX01 is not set # CONFIG_PKG_USING_RGPOWER is not set # CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers # # AI packages @@ -753,15 +833,18 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages # # miscellaneous packages @@ -770,6 +853,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # project laboratory # +# end of project laboratory # # samples: kernel and components samples @@ -778,6 +862,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples # # entertainment: terminal games and other interesting software packages @@ -793,6 +878,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set @@ -826,6 +913,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages # # Arduino libraries @@ -841,6 +929,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos # # Sensors @@ -980,6 +1069,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors # # Display @@ -991,6 +1082,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display # # Timing @@ -999,6 +1091,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set # CONFIG_PKG_USING_ARDUINO_TICKER is not set # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing # # Data Processing @@ -1006,6 +1099,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set # CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing # # Data Storage @@ -1016,6 +1111,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication # # Device Control @@ -1027,12 +1123,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control # # Other # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO @@ -1045,10 +1143,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO # # Uncategorized # +# end of Arduino libraries +# end of RT-Thread online packages + CONFIG_SOC_RISCV_FAMILY_CH32=y CONFIG_SOC_RISCV_SERIES_CH32V3=y @@ -1061,6 +1163,7 @@ CONFIG_SOC_CH32V307VC=y # Onboard Peripheral Drivers # # CONFIG_BSP_USING_ARDUINO is not set +# end of Onboard Peripheral Drivers # # On-chip Peripheral Drivers @@ -1077,6 +1180,10 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART8 is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_USBH is not set +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_SOFT_I2C is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_SOFT_SPI is not set @@ -1085,7 +1192,9 @@ CONFIG_LSI_VALUE=40000 # CONFIG_BSP_USING_IWDT is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_TIM is not set +# end of On-chip Peripheral Drivers # # Board extended module Drivers # +# end of Hardware Drivers Config diff --git a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig index 4b7e8923a5..23c3f1eb3d 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig +++ b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig @@ -121,6 +121,13 @@ menu "On-chip Peripheral Drivers" default n endif + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + select RT_USING_NETDEV + select RT_USING_SAL + config BSP_USING_USBH bool "Enable USB Host" select RT_USING_USB_HOST diff --git a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h index 6714eb10cc..89181a1331 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h +++ b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h @@ -1,9 +1,6 @@ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - /* RT-Thread Kernel */ #define RT_NAME_MAX 8 @@ -23,7 +20,13 @@ /* kservice optimization */ +/* end of kservice optimization */ + +/* klibc optimization */ + +/* end of klibc optimization */ #define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT @@ -34,18 +37,21 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ /* Memory Management */ #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP +/* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x50100 +#define RT_VER_NUM 0x50200 #define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC #define ARCH_RISCV @@ -59,8 +65,8 @@ #define RT_USING_FINSH #define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 1024 +#define FINSH_THREAD_PRIORITY 11 +#define FINSH_THREAD_STACK_SIZE 2048 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB @@ -72,6 +78,7 @@ /* DFS: device virtual file system */ +/* end of DFS: device virtual file system */ /* Device Drivers */ @@ -81,9 +88,7 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN - -/* Using USB */ - +/* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -95,6 +100,8 @@ #define RT_LIBC_TZ_DEFAULT_HOUR 8 #define RT_LIBC_TZ_DEFAULT_MIN 0 #define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ @@ -104,18 +111,30 @@ /* Socket is in the 'Network' category */ +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ /* Network */ +/* end of Network */ /* Memory protection */ +/* end of Memory protection */ /* Utilities */ +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ /* RT-Thread Utestcases */ +/* end of RT-Thread Utestcases */ /* RT-Thread online packages */ @@ -126,57 +145,78 @@ /* Marvell WiFi */ +/* end of Marvell WiFi */ /* Wiced WiFi */ +/* end of Wiced WiFi */ /* CYW43012 WiFi */ +/* end of CYW43012 WiFi */ /* BL808 WiFi */ +/* end of BL808 WiFi */ /* CYW43439 WiFi */ +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ /* IoT Cloud */ +/* end of IoT Cloud */ +/* end of IoT - internet of things */ /* security packages */ +/* end of security packages */ /* language packages */ /* JSON: JavaScript Object Notation, a lightweight data-interchange format */ +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ /* XML: Extensible Markup Language */ +/* end of XML: Extensible Markup Language */ +/* end of language packages */ /* multimedia packages */ /* LVGL: powerful and easy-to-use embedded GUI library */ +/* end of LVGL: powerful and easy-to-use embedded GUI library */ /* u8g2: a monochrome graphic library */ +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ /* tools packages */ +/* end of tools packages */ /* system packages */ /* enhanced kernel services */ +/* end of enhanced kernel services */ /* acceleration: Assembly language or algorithmic acceleration packages */ +/* end of acceleration: Assembly language or algorithmic acceleration packages */ /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ /* Micrium: Micrium software products porting for RT-Thread */ +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ /* peripheral libraries and drivers */ @@ -184,66 +224,94 @@ /* STM32 HAL & SDK Drivers */ +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ /* Kendryte SDK */ +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ /* sensors drivers */ +/* end of sensors drivers */ /* touch drivers */ +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ /* AI packages */ +/* end of AI packages */ /* Signal Processing and Control Algorithm Packages */ +/* end of Signal Processing and Control Algorithm Packages */ /* miscellaneous packages */ /* project laboratory */ +/* end of project laboratory */ + /* samples: kernel and components samples */ +/* end of samples: kernel and components samples */ /* entertainment: terminal games and other interesting software packages */ +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ /* Arduino libraries */ /* Projects and Demos */ +/* end of Projects and Demos */ /* Sensors */ +/* end of Sensors */ /* Display */ +/* end of Display */ /* Timing */ +/* end of Timing */ /* Data Processing */ +/* end of Data Processing */ /* Data Storage */ /* Communication */ +/* end of Communication */ /* Device Control */ +/* end of Device Control */ /* Other */ +/* end of Other */ /* Signal IO */ +/* end of Signal IO */ /* Uncategorized */ +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ #define SOC_RISCV_FAMILY_CH32 #define SOC_RISCV_SERIES_CH32V3 @@ -253,6 +321,7 @@ /* Onboard Peripheral Drivers */ +/* end of Onboard Peripheral Drivers */ /* On-chip Peripheral Drivers */ @@ -260,8 +329,10 @@ #define BSP_USING_UART #define BSP_USING_UART1 #define LSI_VALUE 40000 +/* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ +/* end of Hardware Drivers Config */ #endif diff --git a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.py b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.py index a6df5fe22d..dacd230426 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.py +++ b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.py @@ -52,7 +52,7 @@ if PLATFORM == 'gcc': LPATH = '' if BUILD == 'debug': - CFLAGS += ' -O0 -g3' + CFLAGS += ' -Os -g3' AFLAGS += ' -g3' else: CFLAGS += ' -O2' diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index 2e4651391a..b0dc0aa16a 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -48,6 +48,9 @@ rt_hw_interrupt_enable: .globl rt_hw_context_switch_to rt_hw_context_switch_to: la t0, __rt_rvstack +#ifdef SOC_RISCV_FAMILY_CH32 + addi t0, t0, -512 // for ch32 +#endif /* SOC_RISCV_FAMILY_CH32 */ csrw mscratch,t0 LOAD sp, (a0)