2011.08.07 Magicoe Added PK40X256VLQ100
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1666 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
magicoe@163.com
parent
d561771cc0
commit
a39d7f73ad
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@ -0,0 +1,98 @@
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/*
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* File : app.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-08-06 Magicoe first release
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*
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*/
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/**
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* @addtogroup PK40X256LVQ100
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*/
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/*@{*/
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#include <rtthread.h>
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#include "tc_comm.h"
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#include "SLCD_Driver.h"
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/*
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* This is an example for delay thread
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*/
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static struct rt_thread thread;
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static char thread_stack[THREAD_STACK_SIZE];
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static void thread_entry(void* parameter)
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{
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rt_tick_t tick;
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rt_uint8_t *dispchar[4] = {"INITED",
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"TICK10",
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"TICK15",
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" EXIT "};
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rt_kprintf("thread inited ok\n");
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SLCD_PrintString(dispchar[0], 0);
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tick = rt_tick_get();
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rt_kprintf("thread tick %d\n", tick);
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rt_kprintf("thread delay 10 tick\n");
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rt_thread_delay(1000);
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if (rt_tick_get() - tick > 1000)
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{
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tc_done(TC_STAT_FAILED);
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return;
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}
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SLCD_PrintString(dispchar[1], 0);
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tick = rt_tick_get();
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rt_kprintf("thread delay 15 tick\n");
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rt_thread_delay(1500);
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if (rt_tick_get() - tick > 1500)
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{
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tc_done(TC_STAT_FAILED);
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return;
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}
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SLCD_PrintString(dispchar[2], 0);
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rt_thread_delay(1000);
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rt_kprintf("thread exit\n");
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SLCD_PrintString(dispchar[3], 0);
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tc_done(TC_STAT_PASSED);
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}
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rt_err_t thread_delay_init()
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{
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rt_err_t result;
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result = rt_thread_init(&thread,
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"test",
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thread_entry, RT_NULL,
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&thread_stack[0], sizeof(thread_stack),
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THREAD_PRIORITY, 10);
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if (result == RT_EOK)
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rt_thread_startup(&thread);
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else
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tc_stat(TC_STAT_END | TC_STAT_FAILED);
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return result;
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}
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int rt_application_init()
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{
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thread_delay_init();
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return 0;
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}
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/*@}*/
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@ -0,0 +1,73 @@
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-01-25 Bernard first version
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* 2011-08-06 Magicoe PK40X256VLQ100 version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "board.h"
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#include "uart.h"
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#include "PK40X256VLQ100.h"
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#include "core_cm4.h"
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#include "SLCD_Driver.h"
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/**
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* @addtogroup PK40X256VLQ100
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*/
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/*@{*/
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/**
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* This is the timer interrupt service routine.
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*/
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void rt_hw_timer_handler()
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/**
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* This function will initial sam7s64 board.
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*/
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void rt_hw_board_init()
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{
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rt_uint8_t *dispchar = {"RTINIT"};
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/* Get Core Clock Frequency */
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SystemCoreClockUpdate(); /* Get Core Clock Frequency */
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/* init systick */
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SysTick_Config( SystemCoreClock/1000 ); /* Generate interrupt each 1 ms */
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SLCD_Configuration();
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SLCD_SegmentsAllOff ();
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SLCD_PrintString(dispchar, 0);
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/* set pend exception priority */
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// NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
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#ifdef RT_USING_UART
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/* init hardware UART device */
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rt_hw_uart_init();
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#endif
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device("uart0");
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#endif
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SLCD_PrintString(dispchar, 0);
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}
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/*@}*/
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@ -0,0 +1,20 @@
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/*
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* File : board.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-01-25 Bernard first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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void rt_hw_board_init(void);
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#endif
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@ -0,0 +1,475 @@
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const int8_t Font_35x8[] = {
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/* Space ' ' */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '!' */
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0,0,1,0,0,
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0,0,1,0,0,
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0,0,1,0,0,
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0,0,1,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,1,0,0,
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/* '"' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '#' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '$' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '%' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '&' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* ''' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '(' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* ')' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '*' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '+' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* ',' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '-' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '.' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '/' not defined */
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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0,0,0,0,0,
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/* '0' */
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0,1,1,1,0,
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1,0,0,0,1,
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1,0,0,1,1,
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1,0,1,0,1,
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1,1,0,0,1,
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1,0,0,0,1,
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0,1,1,1,0,
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/* '1' */
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0,0,1,0,0,
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0,1,1,0,0,
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0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
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0,1,1,1,0,
|
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/* '2' */
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0,1,1,1,0,
|
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1,0,0,0,1,
|
||||
0,0,0,0,1,
|
||||
0,0,0,1,0,
|
||||
0,0,1,0,0,
|
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0,1,0,0,0,
|
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1,1,1,1,1,
|
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/* '3' */
|
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1,1,1,1,1,
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0,0,0,1,0,
|
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0,0,1,0,0,
|
||||
0,0,0,1,0,
|
||||
0,0,0,0,1,
|
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1,0,0,0,1,
|
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0,1,1,1,0,
|
||||
/* '4' */
|
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0,0,0,1,0,
|
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0,0,1,1,0,
|
||||
0,1,0,1,0,
|
||||
1,0,0,1,0,
|
||||
1,1,1,1,1,
|
||||
0,0,0,1,0,
|
||||
0,0,0,1,0,
|
||||
/* '5' */
|
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1,1,1,1,1,
|
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1,0,0,0,0,
|
||||
1,1,1,1,0,
|
||||
0,0,0,0,1,
|
||||
0,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,1,1,0,
|
||||
/* '6' */
|
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0,0,1,1,0,
|
||||
0,1,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,1,1,0,
|
||||
/* '7' */
|
||||
1,1,1,1,1,
|
||||
0,0,0,0,1,
|
||||
0,0,0,1,0,
|
||||
0,0,1,0,0,
|
||||
0,1,0,0,0,
|
||||
0,1,0,0,0,
|
||||
0,1,0,0,0,
|
||||
/* '8' */
|
||||
0,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,1,1,0,
|
||||
/* '9' */
|
||||
0,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,1,1,1,
|
||||
0,0,0,0,1,
|
||||
0,0,0,1,0,
|
||||
0,1,1,0,0,
|
||||
/* ':' */
|
||||
0,0,0,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,0,0,0,
|
||||
/* ';' not defined */
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
/* '<' */
|
||||
0,0,0,0,1,
|
||||
0,0,0,1,0,
|
||||
0,0,1,0,0,
|
||||
0,1,0,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,0,1,0,
|
||||
0,0,0,0,1,
|
||||
/* '=' not defined */
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,1,1,1,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
/* '>' */
|
||||
0,1,0,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,0,1,0,
|
||||
0,0,0,0,1,
|
||||
0,0,0,1,0,
|
||||
0,0,1,0,0,
|
||||
0,1,0,0,0,
|
||||
/* '?'not defined */
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
/* '@' not defined */
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
0,0,0,0,0,
|
||||
/* 'A' */
|
||||
0,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,1,1,1,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
/* 'B' */
|
||||
1,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,1,1,1,0,
|
||||
/* 'C' */
|
||||
0,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,1,
|
||||
0,1,1,1,0,
|
||||
/* 'D' */
|
||||
1,1,1,0,0,
|
||||
1,0,0,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,1,0,
|
||||
1,1,1,0,0,
|
||||
/* 'E' */
|
||||
1,1,1,1,1,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,1,1,1,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,1,1,1,1,
|
||||
/* 'F' */
|
||||
1,1,1,1,1,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,1,1,1,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
/* 'G' */
|
||||
0,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,0,
|
||||
1,0,1,1,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,1,1,1,
|
||||
/* 'H' */
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,1,1,1,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
/* 'I' */
|
||||
0,1,1,1,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,1,1,1,0,
|
||||
/* 'J' */
|
||||
0,0,1,1,1,
|
||||
0,0,0,1,0,
|
||||
0,0,0,1,0,
|
||||
0,0,0,1,0,
|
||||
0,0,0,1,0,
|
||||
1,0,0,1,0,
|
||||
0,1,1,0,0,
|
||||
/* 'K' */
|
||||
1,0,0,0,1,
|
||||
1,0,0,1,0,
|
||||
1,0,1,0,0,
|
||||
1,1,0,0,0,
|
||||
1,0,1,0,0,
|
||||
1,0,0,1,0,
|
||||
1,0,0,0,1,
|
||||
/* 'L' */
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,1,1,1,1,
|
||||
/* 'M' */
|
||||
1,0,0,0,1,
|
||||
1,1,0,1,1,
|
||||
1,0,1,0,1,
|
||||
1,0,1,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
/* 'N' */
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,1,0,0,1,
|
||||
1,0,1,0,1,
|
||||
1,0,0,1,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
/* 'O' */
|
||||
0,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,1,1,0,
|
||||
/* 'P' */
|
||||
1,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,1,1,1,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
/* 'Q' */
|
||||
0,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,1,0,1,
|
||||
1,0,0,1,0,
|
||||
0,1,1,0,1,
|
||||
/* 'R' */
|
||||
1,1,1,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,1,1,1,0,
|
||||
1,0,1,0,0,
|
||||
1,0,0,1,0,
|
||||
1,0,0,0,1,
|
||||
/* 'S' */
|
||||
0,1,1,1,1,
|
||||
1,0,0,0,0,
|
||||
1,0,0,0,0,
|
||||
0,1,1,1,0,
|
||||
0,0,0,0,1,
|
||||
0,0,0,0,1,
|
||||
1,1,1,1,0,
|
||||
/* 'T' */
|
||||
1,1,1,1,1,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
/* 'U' */
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,1,1,0,
|
||||
/* 'V' */
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,0,1,0,
|
||||
0,0,1,0,0,
|
||||
/* 'W' */
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,1,0,1,
|
||||
1,0,1,0,1,
|
||||
1,0,1,0,1,
|
||||
0,1,0,1,0,
|
||||
/* 'X' */
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,0,1,0,
|
||||
0,0,1,0,0,
|
||||
0,1,0,1,0,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
/* 'Y' */
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
1,0,0,0,1,
|
||||
0,1,0,1,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
0,0,1,0,0,
|
||||
/* 'Z' */
|
||||
1,1,1,1,1,
|
||||
0,0,0,0,1,
|
||||
0,0,0,1,0,
|
||||
0,0,1,0,0,
|
||||
0,1,0,0,0,
|
||||
1,0,0,0,0,
|
||||
1,1,1,1,1,
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,367 @@
|
|||
/**************************************************************************//**
|
||||
* @file SLCD_Driver.c
|
||||
* @brief MK40X256VMD100 Segment LCD Low Level Driver (306 Segments)
|
||||
* @version V0.01
|
||||
* @date 13. May 2011
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <PK40X256VLQ100.H>
|
||||
#include <string.h>
|
||||
#include "rtdef.h"
|
||||
#include "Font_35x8.h"
|
||||
#include "SLCD_Driver.h"
|
||||
|
||||
const uint8_t WFShiftTable[] = /*Front Plane 0 - 38*/
|
||||
{
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
24,
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
24,
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
24,
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
24,
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
24,
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
24,
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
24,
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
24,
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
24,
|
||||
0,
|
||||
8,
|
||||
16,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* SLCD controller Initialization *
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
void SLCD_Configuration (void)
|
||||
{
|
||||
MCG->C1 |= MCG_C1_IRCLKEN_MASK; /* Enable IRCLK */
|
||||
|
||||
SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK /* Enable Port B,C,D Clock */
|
||||
| SIM_SCGC5_PORTC_MASK
|
||||
| SIM_SCGC5_PORTD_MASK );
|
||||
|
||||
SIM->SCGC3 |= SIM_SCGC3_SLCD_MASK; /* Enable SLCD Clock */
|
||||
|
||||
LCD->GCR = 0; /* Disable SLCD module */
|
||||
|
||||
LCD->PEN[0] = 0xFFFFFFFE; /* Enable SLCD pins 1-31 */
|
||||
LCD->PEN[1] = 0x0000FFFF; /* Enable SLCD pins 32-47 */
|
||||
|
||||
|
||||
LCD->BPEN[1] = 0x0000FF00; /* SLCD Backplane Assignment: Pin 38 - 46 */
|
||||
LCD->BPEN[0] = 0;
|
||||
|
||||
LCD->WF[0] = 0; /* Clear SLCD */
|
||||
LCD->WF[1] = 0;
|
||||
LCD->WF[2] = 0;
|
||||
LCD->WF[3] = 0;
|
||||
LCD->WF[4] = 0;
|
||||
LCD->WF[5] = 0;
|
||||
LCD->WF[6] = 0;
|
||||
LCD->WF[7] = 0;
|
||||
LCD->WF[8] = 0;
|
||||
LCD->WF[9] = 0;
|
||||
|
||||
LCD->WF[10] = 0x08040201; /* SLCD Backplane Phase Assignment */
|
||||
LCD->WF[11] = 0x80402010;
|
||||
|
||||
LCD->GCR |= LCD_GCR_VSUPPLY(1); /* Drive VLL3 from VDD */
|
||||
LCD->GCR |= LCD_GCR_CPSEL_MASK; /* LCD charge pump is selected */
|
||||
LCD->GCR |= LCD_GCR_DUTY(7); /* Use 8 BP */
|
||||
LCD->GCR |= LCD_GCR_SOURCE_MASK; /* LCD clock source : alternate clock */
|
||||
LCD->GCR |= LCD_GCR_LCLK(4); /* LCD clock prescaler: 4 */
|
||||
|
||||
LCD->GCR |= LCD_GCR_LCDEN_MASK; /* Enable LCD module */
|
||||
}
|
||||
/*******************************************************************************
|
||||
* SLCD All Segments Off
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_SegmentsAllOff (void)
|
||||
{
|
||||
LCD->WF[0] = 0;
|
||||
LCD->WF[1] = 0;
|
||||
LCD->WF[2] = 0;
|
||||
LCD->WF[3] = 0;
|
||||
LCD->WF[4] = 0;
|
||||
LCD->WF[5] = 0;
|
||||
LCD->WF[6] = 0;
|
||||
LCD->WF[7] = 0;
|
||||
LCD->WF[8] = 0;
|
||||
LCD->WF[9] = 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* SLCD All Segments On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_SegmentsAllOn(void)
|
||||
{
|
||||
LCD->WF[0] = 0xFFFFFF00;
|
||||
LCD->WF[1] = 0xFFFFFFFF;
|
||||
LCD->WF[2] = 0xFFFFFFFF;
|
||||
LCD->WF[3] = 0xFFFFFFFF;
|
||||
LCD->WF[4] = 0xFFFFFFFF;
|
||||
LCD->WF[5] = 0xFFFFFFFF;
|
||||
LCD->WF[6] = 0xFFFFFFFF;
|
||||
LCD->WF[7] = 0xFFFFFFFF;
|
||||
LCD->WF[8] = 0xFFFFFFFF;
|
||||
LCD->WF[9] = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* SLCD Draw One ASCII character
|
||||
* Parameter: in (ASCII character), fploc (Front Plane Location)
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_DrawChar(uint8_t in, uint8_t fploc)
|
||||
{
|
||||
int nCol, nRow;
|
||||
uint8_t bploc = 0;
|
||||
uint8_t value = 0;
|
||||
|
||||
in -= 0x20;
|
||||
|
||||
for (nRow = 0; nRow < (CHAR_SIZE_ROW); nRow++) {
|
||||
for (nCol = 0; nCol < CHAR_SIZE_COLUMN; nCol++) {
|
||||
value = Font_35x8[in*CHAR_SIZE + nRow*CHAR_SIZE_COLUMN + nCol];
|
||||
if (value == 0) {
|
||||
LCD->WF[(fploc + 2)/4] &= ~(1 << (bploc + WFShiftTable[fploc + 2]));
|
||||
}
|
||||
else {
|
||||
LCD->WF[(fploc + 2)/4] |= (1 << (bploc + WFShiftTable[fploc + 2]));
|
||||
}
|
||||
fploc++;
|
||||
}
|
||||
bploc++;
|
||||
fploc -= CHAR_SIZE_COLUMN;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* SLCD Print String
|
||||
* Parameter: srcStr (Source String) , sPos (Front Plane Location)
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_PrintString (uint8_t * srcStr, uint8_t sPos)
|
||||
{
|
||||
uint8_t offset = sPos;
|
||||
|
||||
while (*srcStr)
|
||||
{
|
||||
SLCD_DrawChar(*srcStr++,offset);
|
||||
offset += CHAR_SIZE_SEGMENT;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* SLCD Print String2
|
||||
* Parameter: srcStr (Source String) , sPos (Front Plane Location)
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_PrintString2 (uint8_t * srcStr, uint8_t sPos)
|
||||
{
|
||||
uint8_t offset = sPos;
|
||||
|
||||
while (*srcStr)
|
||||
{
|
||||
SLCD_DrawChar(*srcStr++,offset);
|
||||
offset += CHAR_SIZE_SEGMENT;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_RadioSighOn (void)
|
||||
{
|
||||
LCD->WF[0] |= (1 << (BP_0 + 8)); /*FrontPlane: LCD_P1. BackPlane: 0*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_USBSighOn (void)
|
||||
{
|
||||
LCD->WF[0] |= (1 << (BP_1 + 8)); /*FrontPlane: LCD_P1. BackPlane: 1*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_ClockSighOn (void)
|
||||
{
|
||||
LCD->WF[0] |= (1 << (BP_3 + 8)); /*FrontPlane: LCD_P1. BackPlane: 3*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Freescale Logo Segment On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_FreescaleLogoOn (void)
|
||||
{
|
||||
LCD->WF[0] |= (1 << (BP_4 + 8)); /*FrontPlane: LCD_P1. BackPlane: 4*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_JLinkSignOn (void)
|
||||
{
|
||||
LCD->WF[0] |= (1 << (BP_5 + 8)); /*FrontPlane: LCD_P1. BackPlane: 5*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_BatterySignOn (int level)
|
||||
{
|
||||
LCD->WF[0] |= (1 << (BP_6 + 8)); /*FrontPlane: LCD_P1. BackPlane: 6*/
|
||||
if(level == 0)
|
||||
{
|
||||
LCD->WF[0] &= ~(1 << (BP_7 + 8 )); /*FrontPlane: LCD_P1. BackPlane: 0*/
|
||||
LCD->WF[9] &= ~(1 << (BP_6 + 24)); /*BackPlane:*/
|
||||
LCD->WF[9] &= ~(1 << (BP_7 + 24));/*BackPlane:*/
|
||||
}
|
||||
if(level == 1)
|
||||
{
|
||||
LCD->WF[0] &= ~(1 << (BP_7 + 8)); /*FrontPlane: LCD_P1. BackPlane: 0*/
|
||||
LCD->WF[9] &= ~(1 << (BP_6 + 24)); /*BackPlane:*/
|
||||
LCD->WF[9] |= (1 << (BP_7 + 24)); /*BackPlane:*/
|
||||
}
|
||||
if(level == 2)
|
||||
{
|
||||
LCD->WF[0] &= ~(1 << (BP_7 + 8)); /*FrontPlane: LCD_P1. BackPlane: 0*/
|
||||
LCD->WF[9] |= (1 << (BP_6 + 24)); /*BackPlane:*/
|
||||
LCD->WF[9] |= (1 << (BP_7 + 24)); /*BackPlane:*/
|
||||
}
|
||||
if(level == 3)
|
||||
{
|
||||
LCD->WF[0] |= (1 << (BP_7 + 8)); /*FrontPlane: LCD_P1. BackPlane: 6*/
|
||||
LCD->WF[9] |= (1 << (BP_6 + 24)); /*BackPlane:*/
|
||||
LCD->WF[9] |= (1 << (BP_7 + 24)); /*BackPlane:*/
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_RadioSighOff (void)
|
||||
{
|
||||
LCD->WF[0] &= ~(1 << (BP_0 + 8)); /*FrontPlane: LCD_P1. BackPlane: 0*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_USBSighOff (void)
|
||||
{
|
||||
LCD->WF[0] &= ~(1 << (BP_1 + 8)); /*FrontPlane: LCD_P1. BackPlane: 1*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment On
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_ClockSighOff (void)
|
||||
{
|
||||
LCD->WF[0] &= ~(1 << (BP_3 + 8)); /*FrontPlane: LCD_P1. BackPlane: 3*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Freescale Logo Segment Off
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_FreescaleLogoOff (void)
|
||||
{
|
||||
LCD->WF[0] &= ~(1 << (BP_4 + 8)); /*FrontPlane: LCD_P1. BackPlane: 4*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment Off
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_JLinkSignOff (void)
|
||||
{
|
||||
LCD->WF[0] &= ~(1 << (BP_5 + 8)); /*FrontPlane: LCD_P1. BackPlane: 5*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* JLink Sign Segment Off
|
||||
* Parameter: None
|
||||
* Return: *
|
||||
*******************************************************************************/
|
||||
void SLCD_BatterySignOff (void)
|
||||
{
|
||||
LCD->WF[0] &= ~(1 << (BP_6 + 8)); /*FrontPlane: LCD_P1. BackPlane: 5*/
|
||||
LCD->WF[0] &= ~(1 << (BP_7 + 8)); /*FrontPlane: LCD_P1. BackPlane: 7*/
|
||||
LCD->WF[9] &= ~(1 << (BP_6 + 24)); /*BackPlane:*/
|
||||
LCD->WF[9] &= ~(1 << (BP_7 + 24)); /*BackPlane:*/
|
||||
}
|
||||
|
||||
// end file ----------------------------------------------------------------------------
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/**************************************************************************//**
|
||||
* @file SLCD_Driver.h
|
||||
* @brief SLCD Low Level Driver function prototypes and defines
|
||||
* @version V0.01
|
||||
* @date 13. May 2011
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _SLCD_DRIVER_H
|
||||
#define _SLCD_DRIVER_H
|
||||
|
||||
|
||||
#define CHAR_SIZE_COLUMN 5
|
||||
#define CHAR_SIZE_ROW 7
|
||||
#define CHAR_SIZE_SEGMENT 6
|
||||
|
||||
#define CHAR_SIZE 35
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BP_0 = 0,
|
||||
BP_1,
|
||||
BP_2,
|
||||
BP_3,
|
||||
BP_4,
|
||||
BP_5,
|
||||
BP_6,
|
||||
BP_7
|
||||
} BackPlaneNumber;
|
||||
|
||||
|
||||
extern void SLCD_Configuration (void);
|
||||
extern void SLCD_SegmentsAllOff(void);
|
||||
extern void SLCD_SegmentsAllOn(void);
|
||||
extern void SLCD_DrawChar(rt_uint8_t in, rt_uint8_t fploc);
|
||||
extern void SLCD_PrintString (rt_uint8_t * srcStr, rt_uint8_t sPos);
|
||||
|
||||
extern void SLCD_RadioSighOn(void);
|
||||
extern void SLCD_USBSighOn(void);
|
||||
extern void SLCD_FreescaleLogoOn(void);
|
||||
extern void SLCD_JLinkSignOn(void);
|
||||
extern void SLCD_ClockSighOn(void);
|
||||
extern void SLCD_BatterySignOn(int level);
|
||||
|
||||
extern void SLCD_RadioSighOff(void);
|
||||
extern void SLCD_USBSighOff(void);
|
||||
extern void SLCD_FreescaleLogoOff(void);
|
||||
extern void SLCD_JLinkSignOff(void);
|
||||
extern void SLCD_ClockSighOff(void);
|
||||
extern void SLCD_BatterySignOff(void);
|
||||
|
||||
#endif /* _SLCD_DRIVER_H */
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/* RT-Thread config file */
|
||||
#ifndef __RTTHREAD_CFG_H__
|
||||
#define __RTTHREAD_CFG_H__
|
||||
|
||||
/* RT_NAME_MAX*/
|
||||
#define RT_NAME_MAX 4
|
||||
|
||||
/* RT_ALIGN_SIZE*/
|
||||
#define RT_ALIGN_SIZE 4
|
||||
|
||||
/* PRIORITY_MAX*/
|
||||
#define RT_THREAD_PRIORITY_MAX 8
|
||||
|
||||
/* Tick per Second*/
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
|
||||
/* SECTION: RT_DEBUG */
|
||||
/* Thread Debug*/
|
||||
/* #define RT_THREAD_DEBUG */
|
||||
|
||||
/* Using Hook*/
|
||||
/* #define RT_USING_HOOK */
|
||||
|
||||
/* SECTION: IPC */
|
||||
/* Using Semaphore*/
|
||||
#define RT_USING_SEMAPHORE
|
||||
|
||||
/* Using Mutex*/
|
||||
/* #define RT_USING_MUTEX */
|
||||
|
||||
/* Using Event*/
|
||||
/* #define RT_USING_EVENT */
|
||||
|
||||
/* Using MailBox*/
|
||||
#define RT_USING_MAILBOX
|
||||
|
||||
/* Using Message Queue*/
|
||||
/* #define RT_USING_MESSAGEQUEUE */
|
||||
|
||||
/* SECTION: Memory Management */
|
||||
/* Using Memory Pool Management*/
|
||||
/* #define RT_USING_MEMPOOL */
|
||||
|
||||
/* Using Dynamic Heap Management*/
|
||||
/* #define RT_USING_HEAP */
|
||||
|
||||
/* Using Small MM*/
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_TINY_SIZE
|
||||
|
||||
/* SECTION: Device System */
|
||||
/* Using Device System */
|
||||
//#define RT_USING_DEVICE
|
||||
|
||||
/* buffer size for UART reception */
|
||||
//#define RT_UART_RX_BUFFER_SIZE 64
|
||||
|
||||
/* Using UART */
|
||||
//#define RT_USING_UART
|
||||
|
||||
/* SECTION: Console options */
|
||||
/* use console for rt_kprintf */
|
||||
//#define RT_USING_CONSOLE
|
||||
/* the buffer size of console */
|
||||
//#define RT_CONSOLEBUF_SIZE 80
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* File : startup.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-01-25 Bernard first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "board.h"
|
||||
#ifdef RT_USING_UART
|
||||
#include "uart.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @addtogroup sam7s
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#endif
|
||||
|
||||
#ifdef __GNUC__
|
||||
extern unsigned char __bss_start;
|
||||
extern unsigned char __bss_end;
|
||||
#endif
|
||||
|
||||
extern void rt_hw_interrupt_init(void);
|
||||
extern int rt_application_init(void);
|
||||
#ifdef RT_USING_DEVICE
|
||||
extern rt_err_t rt_hw_serial_init(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* This function will startup RT-Thread RTOS.
|
||||
*/
|
||||
void rtthread_startup(void)
|
||||
{
|
||||
/* init kernel object */
|
||||
rt_system_object_init();
|
||||
|
||||
/* init board */
|
||||
rt_hw_board_init();
|
||||
rt_show_version();
|
||||
|
||||
/* init tick */
|
||||
rt_system_tick_init();
|
||||
|
||||
/* init timer system */
|
||||
rt_system_timer_init();
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
#ifdef __CC_ARM
|
||||
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
|
||||
#elif __ICCARM__
|
||||
rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
|
||||
#else
|
||||
rt_system_heap_init((void*)&__bss_end, (void*)0x204000);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* init scheduler system */
|
||||
rt_system_scheduler_init();
|
||||
|
||||
#ifdef RT_USING_HOOK /* if the hook is used */
|
||||
/* set idle thread hook */
|
||||
rt_thread_idle_sethook(rt_hw_led_flash);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_DEVICE
|
||||
/* init all device */
|
||||
rt_device_init_all();
|
||||
#endif
|
||||
|
||||
/* init application */
|
||||
rt_application_init();
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
/* init finsh */
|
||||
finsh_system_init();
|
||||
finsh_set_device("uart1");
|
||||
#endif
|
||||
|
||||
/* init idle thread */
|
||||
rt_thread_idle_init();
|
||||
|
||||
/* start scheduler */
|
||||
rt_system_scheduler_start();
|
||||
|
||||
/* never reach here */
|
||||
return ;
|
||||
}
|
||||
|
||||
int main (void)
|
||||
{
|
||||
rt_uint32_t UNUSED level;
|
||||
|
||||
/* disable interrupt first */
|
||||
level = rt_hw_interrupt_disable();
|
||||
|
||||
/* invoke rtthread_startup */
|
||||
rtthread_startup();
|
||||
while(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,295 @@
|
|||
/****************************************************************************
|
||||
* $Id:: uart.c 3736 2010-06-24 02:07:03Z usb00423 $
|
||||
* Project: NXP LPC122x UART example
|
||||
*
|
||||
* Description:
|
||||
* This file contains UART code example which include UART
|
||||
* initialization, UART interrupt handler, and related APIs for
|
||||
* UART access.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <CMSIS/LPC122x.h>
|
||||
|
||||
#include "uart.h"
|
||||
|
||||
#define IER_RBR 0x01
|
||||
#define IER_THRE 0x02
|
||||
#define IER_RLS 0x04
|
||||
|
||||
#define IIR_PEND 0x01
|
||||
#define IIR_RLS 0x03
|
||||
#define IIR_RDA 0x02
|
||||
#define IIR_CTI 0x06
|
||||
#define IIR_THRE 0x01
|
||||
|
||||
#define LSR_RDR 0x01
|
||||
#define LSR_OE 0x02
|
||||
#define LSR_PE 0x04
|
||||
#define LSR_FE 0x08
|
||||
#define LSR_BI 0x10
|
||||
#define LSR_THRE 0x20
|
||||
#define LSR_TEMT 0x40
|
||||
#define LSR_RXFE 0x80
|
||||
|
||||
/**
|
||||
* @addtogroup LPC11xx
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
|
||||
|
||||
#define UART_BAUDRATE 115200
|
||||
|
||||
struct rt_uart_lpc
|
||||
{
|
||||
struct rt_device parent;
|
||||
|
||||
/* buffer for reception */
|
||||
rt_uint8_t read_index, save_index;
|
||||
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
|
||||
}uart_device;
|
||||
|
||||
void UART0_IRQHandler(void)
|
||||
{
|
||||
rt_ubase_t level, iir;
|
||||
struct rt_uart_lpc* uart = &uart_device;
|
||||
|
||||
/* read IIR and clear it */
|
||||
iir = LPC_UART0->IIR;
|
||||
|
||||
iir >>= 0x01; /* skip pending bit in IIR */
|
||||
iir &= 0x07; /* check bit 1~3, interrupt identification */
|
||||
|
||||
if (iir == IIR_RDA) /* Receive Line Status */
|
||||
{
|
||||
/* If no error on RLS, normal ready, save into the data buffer. */
|
||||
/* Note: read RBR will clear the interrupt */
|
||||
uart->rx_buffer[uart->save_index] = LPC_UART0->RBR;
|
||||
level = rt_hw_interrupt_disable();
|
||||
uart->save_index ++;
|
||||
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
uart->save_index = 0;
|
||||
rt_hw_interrupt_enable(level);
|
||||
/* invoke callback */
|
||||
if(uart->parent.rx_indicate != RT_NULL)
|
||||
{
|
||||
rt_size_t length;
|
||||
if (uart->read_index > uart->save_index)
|
||||
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
|
||||
else
|
||||
length = uart->save_index - uart->read_index;
|
||||
|
||||
uart->parent.rx_indicate(&uart->parent, length);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: rt_uart_init
|
||||
** Descriptions:
|
||||
** parameters: dev
|
||||
** Returned value: None
|
||||
*****************************************************************************/
|
||||
static rt_err_t rt_uart_init(rt_device_t dev)
|
||||
{
|
||||
rt_uint32_t Fdiv;
|
||||
rt_uint32_t regVal;
|
||||
|
||||
NVIC_DisableIRQ(UART0_IRQn);
|
||||
|
||||
/* Init UART Hardware */
|
||||
LPC_IOCON->PIO0_1 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_1 |= 0x02; /* UART RXD */
|
||||
LPC_IOCON->PIO0_2 &= ~0x07;
|
||||
LPC_IOCON->PIO0_2 |= 0x02; /* UART TXD */
|
||||
|
||||
/* Enable UART clock */
|
||||
LPC_SYSCON->PRESETCTRL |= (0x1<<2);
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<12);
|
||||
LPC_SYSCON->UART0CLKDIV = 0x1; /* divided by 1 */
|
||||
|
||||
LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
||||
regVal = LPC_SYSCON->UART0CLKDIV;
|
||||
Fdiv = ((SystemAHBFrequency/regVal)/16)/UART_BAUDRATE ; /*baud rate */
|
||||
|
||||
LPC_UART0->DLM = Fdiv / 256;
|
||||
LPC_UART0->DLL = Fdiv % 256;
|
||||
LPC_UART0->LCR = 0x03; /* DLAB = 0 */
|
||||
LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
||||
|
||||
/* Read to clear the line status. */
|
||||
regVal = LPC_UART0->LSR;
|
||||
|
||||
/* Ensure a clean start, no data in either TX or RX FIFO. */
|
||||
while ( LPC_UART0->LSR & (LSR_THRE|LSR_TEMT) != (LSR_THRE|LSR_TEMT) );
|
||||
while ( LPC_UART0->LSR & LSR_RDR )
|
||||
{
|
||||
regVal = LPC_UART0->RBR; /* Dump data from RX FIFO */
|
||||
}
|
||||
|
||||
/* Enable the UART Interrupt */
|
||||
NVIC_EnableIRQ(UART0_IRQn);
|
||||
|
||||
LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
if(dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* Enable the UART Interrupt */
|
||||
NVIC_EnableIRQ(UART0_IRQn);
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_close(rt_device_t dev)
|
||||
{
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* Disable the UART Interrupt */
|
||||
NVIC_DisableIRQ(UART0_IRQn);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
{
|
||||
rt_uint8_t* ptr;
|
||||
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
/* point to buffer */
|
||||
ptr = (rt_uint8_t*) buffer;
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
/* interrupt receive */
|
||||
rt_base_t level;
|
||||
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
if (uart->read_index != uart->save_index)
|
||||
{
|
||||
*ptr = uart->rx_buffer[uart->read_index];
|
||||
|
||||
uart->read_index ++;
|
||||
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
uart->read_index = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* no data in rx buffer */
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
break;
|
||||
}
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
|
||||
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
char *ptr;
|
||||
ptr = (char*)buffer;
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
||||
{
|
||||
/* stream mode */
|
||||
while (size)
|
||||
{
|
||||
if (*ptr == '\n')
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
while ( !(LPC_UART0->LSR & LSR_THRE) );
|
||||
/* write data */
|
||||
LPC_UART0->THR = '\r';
|
||||
}
|
||||
|
||||
/* THRE status, contain valid data */
|
||||
while ( !(LPC_UART0->LSR & LSR_THRE) );
|
||||
/* write data */
|
||||
LPC_UART0->THR = *ptr;
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while ( size != 0 )
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
while ( !(LPC_UART0->LSR & LSR_THRE) );
|
||||
|
||||
/* write data */
|
||||
LPC_UART0->THR = *ptr;
|
||||
|
||||
ptr++;
|
||||
size--;
|
||||
}
|
||||
}
|
||||
|
||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||
}
|
||||
|
||||
void rt_hw_uart_init(void)
|
||||
{
|
||||
struct rt_uart_lpc* uart;
|
||||
|
||||
/* get uart device */
|
||||
uart = &uart_device;
|
||||
|
||||
/* device initialization */
|
||||
uart->parent.type = RT_Device_Class_Char;
|
||||
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
|
||||
uart->read_index = uart->save_index = 0;
|
||||
|
||||
/* device interface */
|
||||
uart->parent.init = rt_uart_init;
|
||||
uart->parent.open = rt_uart_open;
|
||||
uart->parent.close = rt_uart_close;
|
||||
uart->parent.read = rt_uart_read;
|
||||
uart->parent.write = rt_uart_write;
|
||||
uart->parent.control = RT_NULL;
|
||||
uart->parent.user_data = RT_NULL;
|
||||
|
||||
rt_device_register(&uart->parent,
|
||||
"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
void rt_hw_uart_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,176 @@
|
|||
;/*
|
||||
; * File : context_rvds.S
|
||||
; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
; *
|
||||
; * The license and distribution terms for this file may be
|
||||
; * found in the file LICENSE in this distribution or at
|
||||
; * http://www.rt-thread.org/license/LICENSE
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2009-01-17 Bernard first version
|
||||
; * 2010-02-04 Magicoe Edit for LPC17xx Series
|
||||
; * 2010-08-06 Magicoe Amended for PK40X256VLQ100
|
||||
; */
|
||||
|
||||
;/**
|
||||
; * @addtogroup PK40X256VLQ100
|
||||
; */
|
||||
;/*@{*/
|
||||
|
||||
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
|
||||
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (3)
|
||||
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
|
||||
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
|
||||
|
||||
AREA |.text|, CODE, READONLY, ALIGN=2
|
||||
THUMB
|
||||
REQUIRE8
|
||||
PRESERVE8
|
||||
|
||||
IMPORT rt_thread_switch_interrput_flag
|
||||
IMPORT rt_interrupt_from_thread
|
||||
IMPORT rt_interrupt_to_thread
|
||||
|
||||
;/*
|
||||
; * rt_base_t rt_hw_interrupt_disable();
|
||||
; */
|
||||
rt_hw_interrupt_disable PROC
|
||||
EXPORT rt_hw_interrupt_disable
|
||||
MRS r0, PRIMASK
|
||||
CPSID I
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
;/*
|
||||
; * void rt_hw_interrupt_enable(rt_base_t level);
|
||||
; */
|
||||
rt_hw_interrupt_enable PROC
|
||||
EXPORT rt_hw_interrupt_enable
|
||||
MSR PRIMASK, r0
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
;/*
|
||||
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||
; * r0 --> from
|
||||
; * r1 --> to
|
||||
; */
|
||||
rt_hw_context_switch_interrupt
|
||||
EXPORT rt_hw_context_switch_interrupt
|
||||
rt_hw_context_switch PROC
|
||||
EXPORT rt_hw_context_switch
|
||||
|
||||
; set rt_thread_switch_interrput_flag to 1
|
||||
LDR r2, =rt_thread_switch_interrput_flag
|
||||
LDR r3, [r2]
|
||||
CMP r3, #1
|
||||
BEQ _reswitch
|
||||
MOV r3, #1
|
||||
STR r3, [r2]
|
||||
|
||||
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
|
||||
STR r0, [r2]
|
||||
|
||||
_reswitch
|
||||
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
|
||||
STR r1, [r2]
|
||||
|
||||
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
|
||||
LDR r1, =NVIC_PENDSVSET
|
||||
STR r1, [r0]
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
; r0 --> swith from thread stack
|
||||
; r1 --> swith to thread stack
|
||||
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
|
||||
rt_hw_pend_sv PROC
|
||||
EXPORT rt_hw_pend_sv
|
||||
|
||||
; disable interrupt to protect context switch
|
||||
MRS r2, PRIMASK
|
||||
CPSID I
|
||||
|
||||
; get rt_thread_switch_interrupt_flag
|
||||
LDR r0, =rt_thread_switch_interrput_flag
|
||||
LDR r1, [r0]
|
||||
CBZ r1, pendsv_exit ; pendsv already handled
|
||||
|
||||
; clear rt_thread_switch_interrput_flag to 0
|
||||
MOV r1, #0x00
|
||||
STR r1, [r0]
|
||||
|
||||
LDR r0, =rt_interrupt_from_thread
|
||||
LDR r1, [r0]
|
||||
CBZ r1, swtich_to_thread ; skip register save at the first time
|
||||
|
||||
MRS r1, psp ; get from thread stack pointer
|
||||
STMFD r1!, {r4 - r11} ; push r4 - r11 register
|
||||
LDR r0, [r0]
|
||||
STR r1, [r0] ; update from thread stack pointer
|
||||
|
||||
swtich_to_thread
|
||||
LDR r1, =rt_interrupt_to_thread
|
||||
LDR r1, [r1]
|
||||
LDR r1, [r1] ; load thread stack pointer
|
||||
|
||||
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
|
||||
MSR psp, r1 ; update stack pointer
|
||||
|
||||
pendsv_exit
|
||||
; restore interrupt
|
||||
MSR PRIMASK, r2
|
||||
|
||||
ORR lr, lr, #0x04
|
||||
BX lr
|
||||
ENDP
|
||||
|
||||
;/*
|
||||
; * void rt_hw_context_switch_to(rt_uint32 to);
|
||||
; * r0 --> to
|
||||
; * this fucntion is used to perform the first thread switch
|
||||
; */
|
||||
rt_hw_context_switch_to PROC
|
||||
EXPORT rt_hw_context_switch_to
|
||||
; set to thread
|
||||
LDR r1, =rt_interrupt_to_thread
|
||||
STR r0, [r1]
|
||||
|
||||
; set from thread to 0
|
||||
LDR r1, =rt_interrupt_from_thread
|
||||
MOV r0, #0x0
|
||||
STR r0, [r1]
|
||||
|
||||
; set interrupt flag to 1
|
||||
LDR r1, =rt_thread_switch_interrput_flag
|
||||
MOV r0, #1
|
||||
STR r0, [r1]
|
||||
|
||||
; set the PendSV exception priority
|
||||
LDR r0, =NVIC_SYSPRI2
|
||||
LDR r1, =NVIC_PENDSV_PRI
|
||||
LDR.W R2, [r0,#0x00] ; read
|
||||
ORR r1,r1,r2 ; modify
|
||||
STR r1, [r0] ; write-bak
|
||||
|
||||
; trigger the PendSV exception (causes context switch)
|
||||
LDR r0, =NVIC_INT_CTRL
|
||||
LDR r1, =NVIC_PENDSVSET
|
||||
STR r1, [r0]
|
||||
|
||||
; enable interrupts at processor level
|
||||
CPSIE I
|
||||
|
||||
; never reach here!
|
||||
ENDP
|
||||
|
||||
; compatible with old version
|
||||
rt_hw_interrupt_thread_switch PROC
|
||||
EXPORT rt_hw_interrupt_thread_switch
|
||||
BX lr
|
||||
NOP
|
||||
ENDP
|
||||
|
||||
END
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,706 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm4_simd.h
|
||||
* @brief CMSIS Cortex-M4 SIMD Header File
|
||||
* @version V2.01
|
||||
* @date 06. December 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CM4_SIMD_H__
|
||||
#define __CORE_CM4_SIMD_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <intrinsics.h> /* IAR Intrinsics */
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
|
||||
/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
|
||||
/* intrinsic __SADD8 see intrinsics.h */
|
||||
/* intrinsic __QADD8 see intrinsics.h */
|
||||
/* intrinsic __SHADD8 see intrinsics.h */
|
||||
/* intrinsic __UADD8 see intrinsics.h */
|
||||
/* intrinsic __UQADD8 see intrinsics.h */
|
||||
/* intrinsic __UHADD8 see intrinsics.h */
|
||||
/* intrinsic __SSUB8 see intrinsics.h */
|
||||
/* intrinsic __QSUB8 see intrinsics.h */
|
||||
/* intrinsic __SHSUB8 see intrinsics.h */
|
||||
/* intrinsic __USUB8 see intrinsics.h */
|
||||
/* intrinsic __UQSUB8 see intrinsics.h */
|
||||
/* intrinsic __UHSUB8 see intrinsics.h */
|
||||
/* intrinsic __SADD16 see intrinsics.h */
|
||||
/* intrinsic __QADD16 see intrinsics.h */
|
||||
/* intrinsic __SHADD16 see intrinsics.h */
|
||||
/* intrinsic __UADD16 see intrinsics.h */
|
||||
/* intrinsic __UQADD16 see intrinsics.h */
|
||||
/* intrinsic __UHADD16 see intrinsics.h */
|
||||
/* intrinsic __SSUB16 see intrinsics.h */
|
||||
/* intrinsic __QSUB16 see intrinsics.h */
|
||||
/* intrinsic __SHSUB16 see intrinsics.h */
|
||||
/* intrinsic __USUB16 see intrinsics.h */
|
||||
/* intrinsic __UQSUB16 see intrinsics.h */
|
||||
/* intrinsic __UHSUB16 see intrinsics.h */
|
||||
/* intrinsic __SASX see intrinsics.h */
|
||||
/* intrinsic __QASX see intrinsics.h */
|
||||
/* intrinsic __SHASX see intrinsics.h */
|
||||
/* intrinsic __UASX see intrinsics.h */
|
||||
/* intrinsic __UQASX see intrinsics.h */
|
||||
/* intrinsic __UHASX see intrinsics.h */
|
||||
/* intrinsic __SSAX see intrinsics.h */
|
||||
/* intrinsic __QSAX see intrinsics.h */
|
||||
/* intrinsic __SHSAX see intrinsics.h */
|
||||
/* intrinsic __USAX see intrinsics.h */
|
||||
/* intrinsic __UQSAX see intrinsics.h */
|
||||
/* intrinsic __UHSAX see intrinsics.h */
|
||||
/* intrinsic __USAD8 see intrinsics.h */
|
||||
/* intrinsic __USADA8 see intrinsics.h */
|
||||
/* intrinsic __SSAT16 see intrinsics.h */
|
||||
/* intrinsic __USAT16 see intrinsics.h */
|
||||
/* intrinsic __UXTB16 see intrinsics.h */
|
||||
/* intrinsic __SXTB16 see intrinsics.h */
|
||||
/* intrinsic __UXTAB16 see intrinsics.h */
|
||||
/* intrinsic __SXTAB16 see intrinsics.h */
|
||||
/* intrinsic __SMUAD see intrinsics.h */
|
||||
/* intrinsic __SMUADX see intrinsics.h */
|
||||
/* intrinsic __SMLAD see intrinsics.h */
|
||||
/* intrinsic __SMLADX see intrinsics.h */
|
||||
/* intrinsic __SMLALD see intrinsics.h */
|
||||
/* intrinsic __SMLALDX see intrinsics.h */
|
||||
/* intrinsic __SMUSD see intrinsics.h */
|
||||
/* intrinsic __SMUSDX see intrinsics.h */
|
||||
/* intrinsic __SMLSD see intrinsics.h */
|
||||
/* intrinsic __SMLSDX see intrinsics.h */
|
||||
/* intrinsic __SMLSLD see intrinsics.h */
|
||||
/* intrinsic __SMLSLDX see intrinsics.h */
|
||||
/* intrinsic __SEL see intrinsics.h */
|
||||
/* intrinsic __QADD see intrinsics.h */
|
||||
/* intrinsic __QSUB see intrinsics.h */
|
||||
/* intrinsic __PKHBT see intrinsics.h */
|
||||
/* intrinsic __PKHTB see intrinsics.h */
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SSAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SMLALD(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
#define __SMLALDX(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SMLSLD(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
#define __SMLSLDX(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
/* not yet supported */
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM4_SIMD_H__ */
|
||||
|
|
@ -0,0 +1,664 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V2.03
|
||||
* @date 07. April 2011
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMFUNC_H__
|
||||
#define __CORE_CMFUNC_H__
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_CONTROL(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_CONTROL(uint32_t control);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_IPSR(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_APSR(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_xPSR(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_PSP(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_PSP(uint32_t topOfProcStack);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_MSP(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_MSP(uint32_t topOfMainStack);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_PRIMASK(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_PRIMASK(uint32_t priMask);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_BASEPRI(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_BASEPRI(uint32_t basePri);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_FAULTMASK(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_FAULTMASK(uint32_t faultMask);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & 1);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
#endif /* __CORE_CMFUNC_H__ */
|
||||
|
|
@ -0,0 +1,592 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V2.03
|
||||
* @date 07. April 2011
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMINSTR_H__
|
||||
#define __CORE_CMINSTR_H__
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
extern uint32_t __REV16(uint32_t value);
|
||||
#else /* (__ARMCC_VERSION >= 400677) */
|
||||
static __INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
extern int32_t __REVSH(int32_t value);
|
||||
#else /* (__ARMCC_VERSION >= 400677) */
|
||||
static __INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __CLREX(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
#define __CLREX __clrex
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint16_t result;
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H__ */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* File : cpu.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-01-05 Bernard first version
|
||||
* 2010-02-04 Magicoe Edit for LPC17xx Series
|
||||
* 2011-08-06 Magicoe Manded for PK40X256VLQ100
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @addtogroup PK40X256VLQ100
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* reset cpu by dog's time-out
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_reset()
|
||||
{
|
||||
/*NOTREACHED*/
|
||||
}
|
||||
|
||||
/**
|
||||
* shutdown CPU
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_shutdown()
|
||||
{
|
||||
rt_kprintf("shutdown...\n");
|
||||
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* File : fault.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-01-05 Bernard first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
|
||||
struct stack_contex
|
||||
{
|
||||
rt_uint32_t r0;
|
||||
rt_uint32_t r1;
|
||||
rt_uint32_t r2;
|
||||
rt_uint32_t r3;
|
||||
rt_uint32_t r12;
|
||||
rt_uint32_t lr;
|
||||
rt_uint32_t pc;
|
||||
rt_uint32_t psr;
|
||||
};
|
||||
|
||||
extern void rt_hw_interrupt_thread_switch(void);
|
||||
extern void list_thread(void);
|
||||
extern rt_thread_t rt_current_thread;
|
||||
void rt_hw_hard_fault_exception(struct stack_contex* contex)
|
||||
{
|
||||
rt_kprintf("psr: 0x%08x\n", contex->psr);
|
||||
rt_kprintf(" pc: 0x%08x\n", contex->pc);
|
||||
rt_kprintf(" lr: 0x%08x\n", contex->lr);
|
||||
rt_kprintf("r12: 0x%08x\n", contex->r12);
|
||||
rt_kprintf("r03: 0x%08x\n", contex->r3);
|
||||
rt_kprintf("r02: 0x%08x\n", contex->r2);
|
||||
rt_kprintf("r01: 0x%08x\n", contex->r1);
|
||||
rt_kprintf("r00: 0x%08x\n", contex->r0);
|
||||
|
||||
rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
while (1);
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
;/*
|
||||
; * File : fault_rvds.S
|
||||
; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
; *
|
||||
; * The license and distribution terms for this file may be
|
||||
; * found in the file LICENSE in this distribution or at
|
||||
; * http://www.rt-thread.org/license/LICENSE
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2009-01-17 Bernard first version
|
||||
; */
|
||||
|
||||
AREA |.text|, CODE, READONLY, ALIGN=2
|
||||
THUMB
|
||||
REQUIRE8
|
||||
PRESERVE8
|
||||
|
||||
IMPORT rt_hw_hard_fault_exception
|
||||
|
||||
rt_hw_hard_fault PROC
|
||||
EXPORT rt_hw_hard_fault
|
||||
|
||||
; get current context
|
||||
MRS r0, psp ; get fault thread stack pointer
|
||||
PUSH {lr}
|
||||
BL rt_hw_hard_fault_exception
|
||||
POP {lr}
|
||||
|
||||
ORR lr, lr, #0x04
|
||||
BX lr
|
||||
ENDP
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* File : interrupt.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-01-05 Bernard first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrput_flag;
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2006-08-23 Bernard the first version
|
||||
* 2010-02-04 Magicoe Edit for LPC17xx Series
|
||||
* 2011-08-06 Magicoe Manded for PK40X256VLQ100
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @addtogroup PK40X256VLQ100
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
unsigned long *stk;
|
||||
|
||||
stk = (unsigned long *)stack_addr;
|
||||
*(stk) = 0x01000000L; /* PSR */
|
||||
*(--stk) = (unsigned long)tentry; /* entry point, pc */
|
||||
*(--stk) = (unsigned long)texit; /* lr */
|
||||
*(--stk) = 0; /* r12 */
|
||||
*(--stk) = 0; /* r3 */
|
||||
*(--stk) = 0; /* r2 */
|
||||
*(--stk) = 0; /* r1 */
|
||||
*(--stk) = (unsigned long)parameter; /* r0 : argument */
|
||||
|
||||
*(--stk) = 0; /* r11 */
|
||||
*(--stk) = 0; /* r10 */
|
||||
*(--stk) = 0; /* r9 */
|
||||
*(--stk) = 0; /* r8 */
|
||||
*(--stk) = 0; /* r7 */
|
||||
*(--stk) = 0; /* r6 */
|
||||
*(--stk) = 0; /* r5 */
|
||||
*(--stk) = 0; /* r4 */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,652 @@
|
|||
; /*
|
||||
; * File : start_rvds.s
|
||||
; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
; *
|
||||
; * The license and distribution terms for this file may be
|
||||
; * found in the file LICENSE in this distribution or at
|
||||
; * http://www.rt-thread.org/license/LICENSE
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2009-09-23 Bernard first implementation
|
||||
; * 2010-02-04 Magicoe Edit for LPC17xx Series
|
||||
; * 2011-08-06 Magicoe Edit for PK40X256VLQ100
|
||||
; */
|
||||
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_MK40N512MD100.s
|
||||
; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
|
||||
; * MK40N512MD100
|
||||
; * @version: 1.6
|
||||
; * @date: 2011-1-14
|
||||
; *
|
||||
; * Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
;*
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00001000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00001000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
IMPORT rt_hw_hard_fault
|
||||
IMPORT rt_hw_pend_sv
|
||||
IMPORT rt_hw_timer_handler
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD rt_hw_hard_fault ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD rt_hw_pend_sv ; PendSV Handler
|
||||
DCD rt_hw_timer_handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
|
||||
DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
|
||||
DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
|
||||
DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
|
||||
DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
|
||||
DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
|
||||
DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
|
||||
DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
|
||||
DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
|
||||
DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
|
||||
DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
|
||||
DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
|
||||
DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
|
||||
DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
|
||||
DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
|
||||
DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
|
||||
DCD DMA_Error_IRQHandler ; DMA Error Interrupt
|
||||
DCD MCM_IRQHandler ; Normal Interrupt
|
||||
DCD FTFL_IRQHandler ; FTFL Interrupt
|
||||
DCD Read_Collision_IRQHandler ; Read Collision Interrupt
|
||||
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLW_IRQHandler ; Low Leakage Wakeup
|
||||
DCD Watchdog_IRQHandler ; WDOG Interrupt
|
||||
DCD Reserved39_IRQHandler ; Reserved interrupt 39
|
||||
DCD I2C0_IRQHandler ; I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; I2C1 interrupt
|
||||
DCD SPI0_IRQHandler ; SPI0 Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd Message Buffers Interrupt
|
||||
DCD CAN0_Bus_Off_IRQHandler ; CAN0 Bus Off Interrupt
|
||||
DCD CAN0_Error_IRQHandler ; CAN0 Error Interrupt
|
||||
DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx Warning Interrupt
|
||||
DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx Warning Interrupt
|
||||
DCD CAN0_Wake_Up_IRQHandler ; CAN0 Wake Up Interrupt
|
||||
DCD Reserved51_IRQHandler ; Reserved interrupt 51
|
||||
DCD Reserved52_IRQHandler ; Reserved interrupt 52
|
||||
DCD CAN1_ORed_Message_buffer_IRQHandler ; CAN1 OR'd Message Buffers Interrupt
|
||||
DCD CAN1_Bus_Off_IRQHandler ; CAN1 Bus Off Interrupt
|
||||
DCD CAN1_Error_IRQHandler ; CAN1 Error Interrupt
|
||||
DCD CAN1_Tx_Warning_IRQHandler ; CAN1 Tx Warning Interrupt
|
||||
DCD CAN1_Rx_Warning_IRQHandler ; CAN1 Rx Warning Interrupt
|
||||
DCD CAN1_Wake_Up_IRQHandler ; CAN1 Wake Up Interrupt
|
||||
DCD Reserved59_IRQHandler ; Reserved interrupt 59
|
||||
DCD Reserved60_IRQHandler ; Reserved interrupt 60
|
||||
DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
|
||||
DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
|
||||
DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
|
||||
DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
|
||||
DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
|
||||
DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
|
||||
DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
|
||||
DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
|
||||
DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
|
||||
DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
|
||||
DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
|
||||
DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
|
||||
DCD ADC0_IRQHandler ; ADC0 interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 interrupt
|
||||
DCD CMP0_IRQHandler ; CMP0 interrupt
|
||||
DCD CMP1_IRQHandler ; CMP1 interrupt
|
||||
DCD CMP2_IRQHandler ; CMP2 interrupt
|
||||
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
|
||||
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
|
||||
DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
|
||||
DCD CMT_IRQHandler ; CMT interrupt
|
||||
DCD RTC_IRQHandler ; RTC interrupt
|
||||
DCD Reserved83_IRQHandler ; Reserved interrupt 83
|
||||
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
|
||||
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
|
||||
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
|
||||
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
|
||||
DCD PDB0_IRQHandler ; PDB0 Interrupt
|
||||
DCD USB0_IRQHandler ; USB0 interrupt
|
||||
DCD USBDCD_IRQHandler ; USBDCD Interrupt
|
||||
DCD Reserved91_IRQHandler ; Reserved interrupt 91
|
||||
DCD Reserved92_IRQHandler ; Reserved interrupt 92
|
||||
DCD Reserved93_IRQHandler ; Reserved interrupt 93
|
||||
DCD Reserved94_IRQHandler ; Reserved interrupt 94
|
||||
DCD I2S0_IRQHandler ; I2S0 Interrupt
|
||||
DCD SDHC_IRQHandler ; SDHC Interrupt
|
||||
DCD DAC0_IRQHandler ; DAC0 interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 interrupt
|
||||
DCD TSI0_IRQHandler ; TSI0 Interrupt
|
||||
DCD MCG_IRQHandler ; MCG Interrupt
|
||||
DCD LPTimer_IRQHandler ; LPTimer interrupt
|
||||
DCD LCD_IRQHandler ; Segment LCD Interrupt
|
||||
DCD PORTA_IRQHandler ; Port A interrupt
|
||||
DCD PORTB_IRQHandler ; Port B interrupt
|
||||
DCD PORTC_IRQHandler ; Port C interrupt
|
||||
DCD PORTD_IRQHandler ; Port D interrupt
|
||||
DCD PORTE_IRQHandler ; Port E interrupt
|
||||
DCD Reserved108_IRQHandler ; Reserved interrupt 108
|
||||
DCD Reserved109_IRQHandler ; Reserved interrupt 109
|
||||
DCD Reserved110_IRQHandler ; Reserved interrupt 110
|
||||
DCD Reserved111_IRQHandler ; Reserved interrupt 111
|
||||
DCD Reserved112_IRQHandler ; Reserved interrupt 112
|
||||
DCD Reserved113_IRQHandler ; Reserved interrupt 113
|
||||
DCD Reserved114_IRQHandler ; Reserved interrupt 114
|
||||
DCD Reserved115_IRQHandler ; Reserved interrupt 115
|
||||
DCD Reserved116_IRQHandler ; Reserved interrupt 116
|
||||
DCD Reserved117_IRQHandler ; Reserved interrupt 117
|
||||
DCD Reserved118_IRQHandler ; Reserved interrupt 118
|
||||
DCD Reserved119_IRQHandler ; Reserved interrupt 119
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
; <h> Flash Configuration
|
||||
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
; <h> Backdoor Comparison Key
|
||||
; <o0> Backdoor Key 0 <0x0-0xFF:2>
|
||||
; <o1> Backdoor Key 1 <0x0-0xFF:2>
|
||||
; <o2> Backdoor Key 2 <0x0-0xFF:2>
|
||||
; <o3> Backdoor Key 3 <0x0-0xFF:2>
|
||||
; <o4> Backdoor Key 4 <0x0-0xFF:2>
|
||||
; <o5> Backdoor Key 5 <0x0-0xFF:2>
|
||||
; <o6> Backdoor Key 6 <0x0-0xFF:2>
|
||||
; <o7> Backdoor Key 7 <0x0-0xFF:2>
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
; </h>
|
||||
; <h> Program flash protection bytes (FPROT)
|
||||
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
|
||||
; <i> Each bit protects a 1/32 region of the program flash memory.
|
||||
; <h> FPROT0
|
||||
; <i> Program flash protection bytes
|
||||
; <i> 1/32 - 8/32 region
|
||||
; <o.0> FPROT0.0
|
||||
; <o.1> FPROT0.1
|
||||
; <o.2> FPROT0.2
|
||||
; <o.3> FPROT0.3
|
||||
; <o.4> FPROT0.4
|
||||
; <o.5> FPROT0.5
|
||||
; <o.6> FPROT0.6
|
||||
; <o.7> FPROT0.7
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT1
|
||||
; <i> Program Flash Region Protect Register 1
|
||||
; <i> 9/32 - 16/32 region
|
||||
; <o.0> FPROT1.0
|
||||
; <o.1> FPROT1.1
|
||||
; <o.2> FPROT1.2
|
||||
; <o.3> FPROT1.3
|
||||
; <o.4> FPROT1.4
|
||||
; <o.5> FPROT1.5
|
||||
; <o.6> FPROT1.6
|
||||
; <o.7> FPROT1.7
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT2
|
||||
; <i> Program Flash Region Protect Register 2
|
||||
; <i> 17/32 - 24/32 region
|
||||
; <o.0> FPROT2.0
|
||||
; <o.1> FPROT2.1
|
||||
; <o.2> FPROT2.2
|
||||
; <o.3> FPROT2.3
|
||||
; <o.4> FPROT2.4
|
||||
; <o.5> FPROT2.5
|
||||
; <o.6> FPROT2.6
|
||||
; <o.7> FPROT2.7
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT3
|
||||
; <i> Program Flash Region Protect Register 3
|
||||
; <i> 25/32 - 32/32 region
|
||||
; <o.0> FPROT3.0
|
||||
; <o.1> FPROT3.1
|
||||
; <o.2> FPROT3.2
|
||||
; <o.3> FPROT3.3
|
||||
; <o.4> FPROT3.4
|
||||
; <o.5> FPROT3.5
|
||||
; <o.6> FPROT3.6
|
||||
; <o.7> FPROT3.7
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3:EOR:0xFF
|
||||
; </h>
|
||||
; </h>
|
||||
; <h> Data flash protection byte (FDPROT)
|
||||
; <i> Each bit protects a 1/8 region of the data flash memory.
|
||||
; <i> (Program flash only devices: Reserved)
|
||||
; <o.0> FDPROT.0
|
||||
; <o.1> FDPROT.1
|
||||
; <o.2> FDPROT.2
|
||||
; <o.3> FDPROT.3
|
||||
; <o.4> FDPROT.4
|
||||
; <o.5> FDPROT.5
|
||||
; <o.6> FDPROT.6
|
||||
; <o.7> FDPROT.7
|
||||
nFDPROT EQU 0x00
|
||||
FDPROT EQU nFDPROT:EOR:0xFF
|
||||
; </h>
|
||||
; <h> EEPROM protection byte (FEPROT)
|
||||
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
|
||||
; <i> (Program flash only devices: Reserved)
|
||||
; <o.0> FEPROT.0
|
||||
; <o.1> FEPROT.1
|
||||
; <o.2> FEPROT.2
|
||||
; <o.3> FEPROT.3
|
||||
; <o.4> FEPROT.4
|
||||
; <o.5> FEPROT.5
|
||||
; <o.6> FEPROT.6
|
||||
; <o.7> FEPROT.7
|
||||
nFEPROT EQU 0x00
|
||||
FEPROT EQU nFEPROT:EOR:0xFF
|
||||
; </h>
|
||||
; <h> Flash nonvolatile option byte (FOPT)
|
||||
; <i> Allows the user to customize the operation of the MCU at boot time.
|
||||
; <o.0> LPBOOT
|
||||
; <0=> Low-power boot
|
||||
; <1=> normal boot
|
||||
; <o.1> EZPORT_DIS
|
||||
; <0=> EzPort operation is enabled
|
||||
; <1=> EzPort operation is disabled
|
||||
FOPT EQU 0xFF
|
||||
; </h>
|
||||
; <h> Flash security byte (FSEC)
|
||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
||||
; <o.0..1> SEC
|
||||
; <2=> MCU security status is unsecure
|
||||
; <3=> MCU security status is secure
|
||||
; <i> Flash Security
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.2..3> FSLACC
|
||||
; <2=> Freescale factory access denied
|
||||
; <3=> Freescale factory access granted
|
||||
; <i> Freescale Failure Analysis Access Code
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.4..5> MEEN
|
||||
; <2=> Mass erase is disabled
|
||||
; <3=> Mass erase is enabled
|
||||
; <i> Mass Erase Enable Bits
|
||||
; <i> Enables and disables mass erase capability of the FTFL module
|
||||
; <o.6..7> KEYEN
|
||||
; <2=> Backdoor key access enabled
|
||||
; <3=> Backdoor key access disabled
|
||||
; <i> Backdoor key Security Enable
|
||||
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
||||
FSEC EQU 0xFE
|
||||
; </h>
|
||||
; </h>
|
||||
IF :LNOT::DEF:RAM_TARGET
|
||||
AREA |.ARM.__at_0x400|, CODE, READONLY
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, FEPROT, FDPROT
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT DMA0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_IRQHandler [WEAK]
|
||||
EXPORT DMA3_IRQHandler [WEAK]
|
||||
EXPORT DMA4_IRQHandler [WEAK]
|
||||
EXPORT DMA5_IRQHandler [WEAK]
|
||||
EXPORT DMA6_IRQHandler [WEAK]
|
||||
EXPORT DMA7_IRQHandler [WEAK]
|
||||
EXPORT DMA8_IRQHandler [WEAK]
|
||||
EXPORT DMA9_IRQHandler [WEAK]
|
||||
EXPORT DMA10_IRQHandler [WEAK]
|
||||
EXPORT DMA11_IRQHandler [WEAK]
|
||||
EXPORT DMA12_IRQHandler [WEAK]
|
||||
EXPORT DMA13_IRQHandler [WEAK]
|
||||
EXPORT DMA14_IRQHandler [WEAK]
|
||||
EXPORT DMA15_IRQHandler [WEAK]
|
||||
EXPORT DMA_Error_IRQHandler [WEAK]
|
||||
EXPORT MCM_IRQHandler [WEAK]
|
||||
EXPORT FTFL_IRQHandler [WEAK]
|
||||
EXPORT Read_Collision_IRQHandler [WEAK]
|
||||
EXPORT LVD_LVW_IRQHandler [WEAK]
|
||||
EXPORT LLW_IRQHandler [WEAK]
|
||||
EXPORT Watchdog_IRQHandler [WEAK]
|
||||
EXPORT Reserved39_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Error_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
|
||||
EXPORT Reserved51_IRQHandler [WEAK]
|
||||
EXPORT Reserved52_IRQHandler [WEAK]
|
||||
EXPORT CAN1_ORed_Message_buffer_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Bus_Off_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Error_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Tx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Rx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Wake_Up_IRQHandler [WEAK]
|
||||
EXPORT Reserved59_IRQHandler [WEAK]
|
||||
EXPORT Reserved60_IRQHandler [WEAK]
|
||||
EXPORT UART0_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART0_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART1_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART1_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART2_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART2_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART3_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART3_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART4_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART4_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART5_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART5_ERR_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT CMP0_IRQHandler [WEAK]
|
||||
EXPORT CMP1_IRQHandler [WEAK]
|
||||
EXPORT CMP2_IRQHandler [WEAK]
|
||||
EXPORT FTM0_IRQHandler [WEAK]
|
||||
EXPORT FTM1_IRQHandler [WEAK]
|
||||
EXPORT FTM2_IRQHandler [WEAK]
|
||||
EXPORT CMT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT Reserved83_IRQHandler [WEAK]
|
||||
EXPORT PIT0_IRQHandler [WEAK]
|
||||
EXPORT PIT1_IRQHandler [WEAK]
|
||||
EXPORT PIT2_IRQHandler [WEAK]
|
||||
EXPORT PIT3_IRQHandler [WEAK]
|
||||
EXPORT PDB0_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USBDCD_IRQHandler [WEAK]
|
||||
EXPORT Reserved91_IRQHandler [WEAK]
|
||||
EXPORT Reserved92_IRQHandler [WEAK]
|
||||
EXPORT Reserved93_IRQHandler [WEAK]
|
||||
EXPORT Reserved94_IRQHandler [WEAK]
|
||||
EXPORT I2S0_IRQHandler [WEAK]
|
||||
EXPORT SDHC_IRQHandler [WEAK]
|
||||
EXPORT DAC0_IRQHandler [WEAK]
|
||||
EXPORT DAC1_IRQHandler [WEAK]
|
||||
EXPORT TSI0_IRQHandler [WEAK]
|
||||
EXPORT MCG_IRQHandler [WEAK]
|
||||
EXPORT LPTimer_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT PORTA_IRQHandler [WEAK]
|
||||
EXPORT PORTB_IRQHandler [WEAK]
|
||||
EXPORT PORTC_IRQHandler [WEAK]
|
||||
EXPORT PORTD_IRQHandler [WEAK]
|
||||
EXPORT PORTE_IRQHandler [WEAK]
|
||||
EXPORT Reserved108_IRQHandler [WEAK]
|
||||
EXPORT Reserved109_IRQHandler [WEAK]
|
||||
EXPORT Reserved110_IRQHandler [WEAK]
|
||||
EXPORT Reserved111_IRQHandler [WEAK]
|
||||
EXPORT Reserved112_IRQHandler [WEAK]
|
||||
EXPORT Reserved113_IRQHandler [WEAK]
|
||||
EXPORT Reserved114_IRQHandler [WEAK]
|
||||
EXPORT Reserved115_IRQHandler [WEAK]
|
||||
EXPORT Reserved116_IRQHandler [WEAK]
|
||||
EXPORT Reserved117_IRQHandler [WEAK]
|
||||
EXPORT Reserved118_IRQHandler [WEAK]
|
||||
EXPORT Reserved119_IRQHandler [WEAK]
|
||||
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
DMA4_IRQHandler
|
||||
DMA5_IRQHandler
|
||||
DMA6_IRQHandler
|
||||
DMA7_IRQHandler
|
||||
DMA8_IRQHandler
|
||||
DMA9_IRQHandler
|
||||
DMA10_IRQHandler
|
||||
DMA11_IRQHandler
|
||||
DMA12_IRQHandler
|
||||
DMA13_IRQHandler
|
||||
DMA14_IRQHandler
|
||||
DMA15_IRQHandler
|
||||
DMA_Error_IRQHandler
|
||||
MCM_IRQHandler
|
||||
FTFL_IRQHandler
|
||||
Read_Collision_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
Watchdog_IRQHandler
|
||||
Reserved39_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
CAN0_ORed_Message_buffer_IRQHandler
|
||||
CAN0_Bus_Off_IRQHandler
|
||||
CAN0_Error_IRQHandler
|
||||
CAN0_Tx_Warning_IRQHandler
|
||||
CAN0_Rx_Warning_IRQHandler
|
||||
CAN0_Wake_Up_IRQHandler
|
||||
Reserved51_IRQHandler
|
||||
Reserved52_IRQHandler
|
||||
CAN1_ORed_Message_buffer_IRQHandler
|
||||
CAN1_Bus_Off_IRQHandler
|
||||
CAN1_Error_IRQHandler
|
||||
CAN1_Tx_Warning_IRQHandler
|
||||
CAN1_Rx_Warning_IRQHandler
|
||||
CAN1_Wake_Up_IRQHandler
|
||||
Reserved59_IRQHandler
|
||||
Reserved60_IRQHandler
|
||||
UART0_RX_TX_IRQHandler
|
||||
UART0_ERR_IRQHandler
|
||||
UART1_RX_TX_IRQHandler
|
||||
UART1_ERR_IRQHandler
|
||||
UART2_RX_TX_IRQHandler
|
||||
UART2_ERR_IRQHandler
|
||||
UART3_RX_TX_IRQHandler
|
||||
UART3_ERR_IRQHandler
|
||||
UART4_RX_TX_IRQHandler
|
||||
UART4_ERR_IRQHandler
|
||||
UART5_RX_TX_IRQHandler
|
||||
UART5_ERR_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
CMP1_IRQHandler
|
||||
CMP2_IRQHandler
|
||||
FTM0_IRQHandler
|
||||
FTM1_IRQHandler
|
||||
FTM2_IRQHandler
|
||||
CMT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
Reserved83_IRQHandler
|
||||
PIT0_IRQHandler
|
||||
PIT1_IRQHandler
|
||||
PIT2_IRQHandler
|
||||
PIT3_IRQHandler
|
||||
PDB0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USBDCD_IRQHandler
|
||||
Reserved91_IRQHandler
|
||||
Reserved92_IRQHandler
|
||||
Reserved93_IRQHandler
|
||||
Reserved94_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
SDHC_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
LCD_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
PORTC_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
PORTE_IRQHandler
|
||||
Reserved108_IRQHandler
|
||||
Reserved109_IRQHandler
|
||||
Reserved110_IRQHandler
|
||||
Reserved111_IRQHandler
|
||||
Reserved112_IRQHandler
|
||||
Reserved113_IRQHandler
|
||||
Reserved114_IRQHandler
|
||||
Reserved115_IRQHandler
|
||||
Reserved116_IRQHandler
|
||||
Reserved117_IRQHandler
|
||||
Reserved118_IRQHandler
|
||||
Reserved119_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
|
||||
|
|
@ -0,0 +1,309 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processor: PK40X256VLQ100
|
||||
** Compilers: ARM Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU ARM C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: K40P144M100SF2RM, Rev. 3, 4 Nov 2010
|
||||
** Version: rev. 1.6, 2011-01-14
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that contains the system frequency.
|
||||
** It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2010-09-29)
|
||||
** Initial version
|
||||
** - rev. 1.0 (2010-10-15)
|
||||
** First public version
|
||||
** - rev. 1.1 (2010-10-27)
|
||||
** Registers updated according to the new reference manual revision - Rev. 2, 15 Oct 2010
|
||||
** ADC - Peripheral register PGA bit definition has been fixed, bits PGALP, PGACHP removed.
|
||||
** CAN - Peripheral register MCR bit definition has been fixed, bit WAKSRC removed.
|
||||
** CRC - Peripheral register layout structure has been extended with 8/16-bit access to shadow registers.
|
||||
** CMP - Peripheral base address macro renamed from HSCMPx_BASE to CMPx_BASE.
|
||||
** CMP - Peripheral base pointer macro renamed from HSCMPx to CMPx.
|
||||
** DMA - Peripheral base address macro renamed from eDMA_BASE to DMA_BASE.
|
||||
** DMA - Peripheral base pointer macro renamed from eDMA to DMA.
|
||||
** GPIO - Port Output Enable Register (POER) has been renamed to Port Data Direction Register (PDDR), all POER related macros fixed to PDDR.
|
||||
** LCD - Peripheral base address macro renamed from SLCD_BASE to LCD_BASE.
|
||||
** LCD - Peripheral base pointer macro renamed from SLCD to LCD.
|
||||
** PDB - Peripheral register layout structure has been extended for Channel n and DAC n register array access (#MTWX44115).
|
||||
** RFSYS - System regfile registers have been added (#MTWX43999)
|
||||
** RFVBAT - VBAT regfile registers have been added (#MTWX43999)
|
||||
** RTC - Peripheral register CR bit definition has been fixed, bit OTE removed.
|
||||
** TSI - Peripheral registers STATUS, SCANC bit definition have been fixed, bit groups CAPTRM, DELVOL and AMCLKDIV added.
|
||||
** USB - Peripheral base address macro renamed from USBOTG0_BASE to USB0_BASE.
|
||||
** USB - Peripheral base pointer macro renamed from USBOTG0 to USB0.
|
||||
** VREF - Peripheral register TRM removed.
|
||||
** - rev. 1.2 (2010-11-11)
|
||||
** Registers updated according to the new reference manual revision - Rev. 3, 4 Nov 2010
|
||||
** CAN - Individual Matching Element Update (IMEU) feature has been removed.
|
||||
** CAN - Peripheral register layout structure has been fixed, registers IMEUR, LRFR have been removed.
|
||||
** CAN - Peripheral register CTRL2 bit definition has been fixed, bits IMEUMASK, LOSTRMMSK, LOSTRLMSK, IMEUEN have been removed.
|
||||
** CAN - Peripheral register ESR2 bit definition has been fixed, bits IMEUF, LOSTRMF, LOSTRLF have been removed.
|
||||
** NV - Fixed offset address of BACKKEYx, FPROTx registers.
|
||||
** TSI - Peripheral register layout structure has been fixed, register WUCNTR has been removed.
|
||||
** - rev. 1.3 (2010-11-19)
|
||||
** CAN - Support for CAN0_IMEU_IRQn, CAN0_Lost_Rx_IRQn interrupts has been removed.
|
||||
** CAN - Support for CAN1_IMEU_IRQn, CAN1_Lost_Rx_IRQn interrupts has been removed.
|
||||
** - rev. 1.4 (2010-11-30)
|
||||
** EWM - Peripheral base address EWM_BASE definition has been fixed from 0x4005F000u to 0x40061000u (#MTWX44776).
|
||||
** - rev. 1.5 (2010-12-17)
|
||||
** AIPS0, AIPS1 - Fixed offset of PACRE-PACRP registers (#MTWX45259).
|
||||
** - rev. 1.6 (2011-01-14)
|
||||
** Added BITBAND_REG() macro to provide access to register bits using bit band region.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*! \file MK40N512MD100 */
|
||||
/*! \version 1.6 */
|
||||
/*! \date 2011-01-14 */
|
||||
/*! \brief Device specific configuration file for MK40N512MD100 (implementation file) */
|
||||
/*! \detailed Provides a system configuration function and a global variable that contains the system frequency.
|
||||
It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include "PK40X256VLQ100.h"
|
||||
|
||||
#define DISABLE_WDOG 1
|
||||
|
||||
#define CLOCK_SETUP 1
|
||||
/* Predefined clock setups
|
||||
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
|
||||
Core clock/Bus clock derived from an internal clock source 32.768kHz
|
||||
Core clock = 47.97MHz, BusClock = 47.97MHz
|
||||
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE} mode
|
||||
Clock derived from and external crystal 8MHz
|
||||
Core clock = 24MHz, BusClock = 24MHz
|
||||
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
|
||||
Core clock/Bus clock derived directly from external crystal with no multiplication
|
||||
Core clock = 4MHz, BusClock = 4MHz
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clock source values
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if (CLOCK_SETUP == 0)
|
||||
#define CPU_XTAL_CLK_HZ 4000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
|
||||
#elif (CLOCK_SETUP == 1)
|
||||
#define CPU_XTAL_CLK_HZ 4000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 24000000u /* Default System clock value */
|
||||
#elif (CLOCK_SETUP == 2)
|
||||
#define CPU_XTAL_CLK_HZ 4000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||
#endif /* (CLOCK_SETUP == 2) */
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit (void) {
|
||||
#if (DISABLE_WDOG)
|
||||
/* Disable the WDOG module */
|
||||
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
|
||||
WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
|
||||
/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
|
||||
WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
|
||||
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
|
||||
WDOG->STCTRLH = (uint16_t)0x01D2u;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
|
||||
/* System clock initialization */
|
||||
#if (CLOCK_SETUP == 0)
|
||||
/* Switch to FEI Mode */
|
||||
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x06u;
|
||||
/* MCG->C2: ??=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x00u;
|
||||
/* MCG_C4: DMX32=1,DRST_DRS=1 */
|
||||
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0x40u) | (uint8_t)0xA0u);
|
||||
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
|
||||
MCG->C5 = (uint8_t)0x00u;
|
||||
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
|
||||
MCG->C6 = (uint8_t)0x00u;
|
||||
while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
|
||||
}
|
||||
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
|
||||
#elif (CLOCK_SETUP == 1)
|
||||
/* Switch to FBE Mode */
|
||||
/* OSC->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC->CR = (uint8_t)0x00u;
|
||||
/* SIM->SOPT2: MCGCLKSEL=0 */
|
||||
SIM->SOPT2 &= (uint8_t)~(uint8_t)0x01u;
|
||||
/* MCG->C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x24u;
|
||||
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x9Au;
|
||||
/* MCG->C4: DMX32=0,DRST_DRS=0 */
|
||||
MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
|
||||
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=3 */
|
||||
MCG->C5 = (uint8_t)0x03u;
|
||||
/* MCG->C5: PLLCLKEN=1 */
|
||||
MCG->C5 |= (uint8_t)0x40u; /* Enable the PLL */
|
||||
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
|
||||
MCG->C6 = (uint8_t)0x00u;
|
||||
while((MCG->S & MCG_S_OSCINIT_MASK) == 0u) { /* Check that the oscillator is running */
|
||||
}
|
||||
while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
/* Switch to PBE Mode */
|
||||
/* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x82u;
|
||||
/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV=0 */
|
||||
MCG->C6 = (uint8_t)0x40u;
|
||||
/* Switch to PEE Mode */
|
||||
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x02u;
|
||||
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=3 */
|
||||
MCG->C5 = (uint8_t)0x03u;
|
||||
/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV=0 */
|
||||
MCG->C6 = (uint8_t)0x40u;
|
||||
while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
|
||||
}
|
||||
while((MCG->S & MCG_S_LOCK_MASK) == 0u) { /* Wait until locked */
|
||||
}
|
||||
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
|
||||
#elif (CLOCK_SETUP == 2)
|
||||
/* Switch to FBE Mode */
|
||||
/* OSC->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC->CR = (uint8_t)0x00u;
|
||||
/* SIM->SOPT2: MCGCLKSEL=0 */
|
||||
SIM->SOPT2 &= (uint8_t)~(uint8_t)0x01u;
|
||||
/* MCG->C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x24u;
|
||||
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x9Au;
|
||||
/* MCG->C4: DMX32=0,DRST_DRS=0 */
|
||||
MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
|
||||
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
|
||||
MCG->C5 = (uint8_t)0x00u;
|
||||
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
|
||||
MCG->C6 = (uint8_t)0x00u;
|
||||
while((MCG->S & MCG_S_OSCINIT_MASK) == 0u) { /* Check that the oscillator is running */
|
||||
}
|
||||
while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
/* Switch to BLPE Mode */
|
||||
/* MCG->C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x24u;
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
|
||||
#endif /* (CLOCK_SETUP == 2) */
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
|
||||
uint8_t Divider;
|
||||
|
||||
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
|
||||
/* Output of FLL or PLL is selected */
|
||||
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
|
||||
/* FLL is selected */
|
||||
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
|
||||
/* External reference clock is selected */
|
||||
if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) {
|
||||
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||||
} else { /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
||||
} /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
|
||||
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
||||
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
|
||||
if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) {
|
||||
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
|
||||
} /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) */
|
||||
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
|
||||
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
||||
/* Select correct multiplier to calculate the MCG output clock */
|
||||
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
|
||||
case 0x0u:
|
||||
MCGOUTClock *= 640u;
|
||||
break;
|
||||
case 0x20u:
|
||||
MCGOUTClock *= 1280u;
|
||||
break;
|
||||
case 0x40u:
|
||||
MCGOUTClock *= 1920u;
|
||||
break;
|
||||
case 0x60u:
|
||||
MCGOUTClock *= 2560u;
|
||||
break;
|
||||
case 0x80u:
|
||||
MCGOUTClock *= 732u;
|
||||
break;
|
||||
case 0xA0u:
|
||||
MCGOUTClock *= 1464u;
|
||||
break;
|
||||
case 0xC0u:
|
||||
MCGOUTClock *= 2197u;
|
||||
break;
|
||||
case 0xE0u:
|
||||
MCGOUTClock *= 2929u;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
||||
/* PLL is selected */
|
||||
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV_MASK));
|
||||
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
|
||||
Divider = ((MCG->C6 & MCG_C6_VDIV_MASK) + 24u);
|
||||
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
|
||||
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
|
||||
/* Internal reference clock is selected */
|
||||
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
|
||||
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
|
||||
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
|
||||
/* External reference clock is selected */
|
||||
if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) {
|
||||
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||||
} else { /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
||||
} /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
|
||||
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
||||
/* Reserved value */
|
||||
return;
|
||||
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
||||
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
||||
}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processor: PK40X256VLQ100
|
||||
** Compilers: ARM Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU ARM C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: K40P144M100SF2RM, Rev. 3, 4 Nov 2010
|
||||
** Version: rev. 1.6, 2011-01-14
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that contains the system frequency.
|
||||
** It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2010-09-29)
|
||||
** Initial version
|
||||
** - rev. 1.0 (2010-10-15)
|
||||
** First public version
|
||||
** - rev. 1.1 (2010-10-27)
|
||||
** Registers updated according to the new reference manual revision - Rev. 2, 15 Oct 2010
|
||||
** ADC - Peripheral register PGA bit definition has been fixed, bits PGALP, PGACHP removed.
|
||||
** CAN - Peripheral register MCR bit definition has been fixed, bit WAKSRC removed.
|
||||
** CRC - Peripheral register layout structure has been extended with 8/16-bit access to shadow registers.
|
||||
** CMP - Peripheral base address macro renamed from HSCMPx_BASE to CMPx_BASE.
|
||||
** CMP - Peripheral base pointer macro renamed from HSCMPx to CMPx.
|
||||
** DMA - Peripheral base address macro renamed from eDMA_BASE to DMA_BASE.
|
||||
** DMA - Peripheral base pointer macro renamed from eDMA to DMA.
|
||||
** GPIO - Port Output Enable Register (POER) has been renamed to Port Data Direction Register (PDDR), all POER related macros fixed to PDDR.
|
||||
** LCD - Peripheral base address macro renamed from SLCD_BASE to LCD_BASE.
|
||||
** LCD - Peripheral base pointer macro renamed from SLCD to LCD.
|
||||
** PDB - Peripheral register layout structure has been extended for Channel n and DAC n register array access (#MTWX44115).
|
||||
** RFSYS - System regfile registers have been added (#MTWX43999)
|
||||
** RFVBAT - VBAT regfile registers have been added (#MTWX43999)
|
||||
** RTC - Peripheral register CR bit definition has been fixed, bit OTE removed.
|
||||
** TSI - Peripheral registers STATUS, SCANC bit definition have been fixed, bit groups CAPTRM, DELVOL and AMCLKDIV added.
|
||||
** USB - Peripheral base address macro renamed from USBOTG0_BASE to USB0_BASE.
|
||||
** USB - Peripheral base pointer macro renamed from USBOTG0 to USB0.
|
||||
** VREF - Peripheral register TRM removed.
|
||||
** - rev. 1.2 (2010-11-11)
|
||||
** Registers updated according to the new reference manual revision - Rev. 3, 4 Nov 2010
|
||||
** CAN - Individual Matching Element Update (IMEU) feature has been removed.
|
||||
** CAN - Peripheral register layout structure has been fixed, registers IMEUR, LRFR have been removed.
|
||||
** CAN - Peripheral register CTRL2 bit definition has been fixed, bits IMEUMASK, LOSTRMMSK, LOSTRLMSK, IMEUEN have been removed.
|
||||
** CAN - Peripheral register ESR2 bit definition has been fixed, bits IMEUF, LOSTRMF, LOSTRLF have been removed.
|
||||
** NV - Fixed offset address of BACKKEYx, FPROTx registers.
|
||||
** TSI - Peripheral register layout structure has been fixed, register WUCNTR has been removed.
|
||||
** - rev. 1.3 (2010-11-19)
|
||||
** CAN - Support for CAN0_IMEU_IRQn, CAN0_Lost_Rx_IRQn interrupts has been removed.
|
||||
** CAN - Support for CAN1_IMEU_IRQn, CAN1_Lost_Rx_IRQn interrupts has been removed.
|
||||
** - rev. 1.4 (2010-11-30)
|
||||
** EWM - Peripheral base address EWM_BASE definition has been fixed from 0x4005F000u to 0x40061000u (#MTWX44776).
|
||||
** - rev. 1.5 (2010-12-17)
|
||||
** AIPS0, AIPS1 - Fixed offset of PACRE-PACRP registers (#MTWX45259).
|
||||
** - rev. 1.6 (2011-01-14)
|
||||
** Added BITBAND_REG() macro to provide access to register bits using bit band region.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*! \file PK40X256VLQ100 */
|
||||
/*! \version 1.6 */
|
||||
/*! \date 2011-01-14 */
|
||||
/*! \brief Device specific configuration file for PK40X256VLQ100 (header file) */
|
||||
/*! \detailed Provides a system configuration function and a global variable that contains the system frequency.
|
||||
It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device. */
|
||||
|
||||
#ifndef SYSTEM_PK40X256VLQ100_H_
|
||||
#define SYSTEM_PK40X256VLQ100_H_ /*!< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*! \brief System clock frequency (core clock)
|
||||
\detailed The system clock frequency supplied to the SysTick timer and the processor core clock.
|
||||
This variable can be used by the user application to setup the SysTick timer or configure other parameters.
|
||||
It may also be used by debugger to query the frequency of the debug timer or configure the trace clock speed.
|
||||
SystemCoreClock is initialized with a correct predefined value. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*! \brief Setup the microcontroller system.
|
||||
\detailed Typically this function configures the oscillator (PLL) that is part of the microcontroller device.
|
||||
For systems with variable clock speed it also updates the variable SystemCoreClock.
|
||||
SystemInit is called from startup_device file. */
|
||||
void SystemInit (void);
|
||||
|
||||
/*! \brief Updates the SystemCoreClock variable.
|
||||
\detailed It must be called whenever the core clock is changed during program execution.
|
||||
SystemCoreClockUpdate() evaluates the clock register settings and calculates the current core clock. */
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* #if !defined(SYSTEM_PK40X256VLQ100_H_) */
|
||||
Loading…
Reference in New Issue