libs/rt-thread-official
libs
/
rt-thread-official
mirror of https://github.com/RT-Thread/rt-thread.git
4
0
Fork 0
Code Issues Releases Wiki Activity

support GNUC cross compiler(GNUM16CM32Cv1101-ELF) for renesas M16C porting 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2047 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
dzzxzz@gmail.com 2012-04-14 07:04:27 +00:00
parent 87195cf84e
commit a321f3da64
14 changed files with 3358 additions and 131 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
bsp/m16c62p/SConscript
View File

@ -3,6 +3,11 @@ Import('RTT_ROOT')
from building import *
src_c = ['application.c', 'startup.c', 'board.c', 'bsp.c', 'uart.c']
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src_asm = ['start.S', 'vects.S', 'interrupts.S']
elif rtconfig.CROSS_TOOL == 'iar':
src_asm = ['cstartup.asm', 'interrupts.asm', 'vectors.asm']
src = File(src_c + src_asm)

2
bsp/m16c62p/board.c
View File

@ -24,7 +24,7 @@
/**
* This function will initial m16c board.
*/
void rt_hw_board_init()
void rt_hw_board_init(void)
{
#ifdef RT_USING_UART0
rt_hw_uart_init();

3
bsp/m16c62p/board.h
View File

@ -16,6 +16,9 @@
#ifndef __BOARD_H__
#define __BOARD_H__
#define M16C62P_SRAM_SIZE 31L
#define M16C62P_SRAM_END (0x400 + M16C62P_SRAM_SIZE * 1024 - 1)
void rt_hw_board_init(void);
#endif

40
bsp/m16c62p/bsp.c
View File

@ -21,49 +21,49 @@
void led_init(void)
{
pu37 = 1;
pd11_0 = 1;
PUR3.BIT.PU37 = 1;
PD11.BIT.PD11_0 = 1;
led_off();
}
void led_on(void)
{
p11_0 = 0;
P11.BIT.P11_0 = 0;
}
void led_off(void)
{
p11_0 = 1;
P11.BIT.P11_0 = 1;
}
static void mcu_init(void)
{
volatile rt_uint32_t count;
/* Configure clock for divide by 1 mode */
prcr |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */
cm1 = 0x20; /* Set CM16, CM17 divide ratio to 1: */
PRCR.BYTE |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */
CM1.BYTE = 0x20; /* Set CM16, CM17 divide ratio to 1: */
/* ... main clock on in high drive no PLL */
cm0 &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */
CM0.BYTE &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */
/* Configure main PLL */
prcr |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */
pm2 |= 0x01; /* Set SFR access to 2 wait, which is required for */
PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */
PM2.BYTE |= 0x01; /* Set SFR access to 2 wait, which is required for */
/* ... operation greater than 16 MHz PM2.PM20 = 1 */
prcr &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */
plc0 = 0x91; /* Enable and turn on PLL */
PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */
PLC0.BYTE = 0x91; /* Enable and turn on PLL */
count = 20000; /* Delay while PLL stabilizes */
while (count > 0) {
count--;
}
cm1 |= 0x02; /* Switch to PLL CM1.CM11 = 1 */
prcr &= ~0x01; /* Protect clock control register PRCR.PRC0 = 0 */
CM1.BYTE |= 0x02; /* Switch to PLL CM1.CM11 = 1 */
PRCR.BYTE &= ~0x01; /* Protect clock control register PRCR.PRC0 = 0 */
prcr |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */
pm1 |= 0x01; /* Enable data flash area PM1.PM10 = 1 */
prcr &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */
PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */
PM1.BYTE |= 0x01; /* Enable data flash area PM1.PM10 = 1 */
PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */
}
/*
@ -91,13 +91,13 @@ static void timer_tick_init(void)
{
/* Set timer to timer mode */
/* Set count source as PLL clock / 8 (f8) */
tb0mr = 0x40;
TB0MR.BYTE = 0x40;
/* Assign timer value and reload value */
tb0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND;
TB0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND;
/* Set timer B channel 0 interrupt level = 7 */
/* Clear interrupt request */
tb0ic = 0x07;
tabsr |= 0x20; /* Start timer */
TB0IC.BYTE = 0x07;
TABSR.BYTE |= 0x20; /* Start timer */
}
void system_init(void)

61
bsp/m16c62p/interrupts.S Normal file
View File

@ -0,0 +1,61 @@
/*
* File : interrupt.s34
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-04-20 fify the first version
*
* For : Renesas M16C
* Toolchain : IAR's EW for M16C v3.401
*/
.text
.globl _rt_hw_context_switch_interrupt_do
.type _rt_hw_context_switch_interrupt_do, #function
_rt_hw_context_switch_interrupt_do:
MOV.B #0, _rt_thread_switch_interrupt_flag
MOV.W _rt_interrupt_from_thread, A0
STC ISP, [A0]
MOV.W _rt_interrupt_to_thread, A0
LDC [A0], ISP
POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore all processor registers from the new task's stack
REIT
.text
.globl _rt_hw_timer_handler
.type _rt_hw_timer_handler, #function
_rt_hw_timer_handler:
PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers
jsr.a _rt_interrupt_enter
jsr.a _rt_tick_increase
jsr.a _rt_interrupt_leave
CMP.B #1, _rt_thread_switch_interrupt_flag
JEQ _rt_hw_context_switch_interrupt_do
POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore current task's registers
REIT ; Return from interrup
.text
.globl _rt_hw_uart0_receive_handler
.type _rt_hw_uart0_receive_handler, #function
_rt_hw_uart0_receive_handler:
PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers
jsr.a _rt_interrupt_enter
jsr.a _u0rec_handler
jsr.a _rt_interrupt_leave
CMP.B #1, _rt_thread_switch_interrupt_flag
JEQ _rt_hw_context_switch_interrupt_do
POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore current task's registers
REIT ; Return from interrup

2757
bsp/m16c62p/iom16c62p.h Normal file
View File

File diff suppressed because it is too large Load Diff

167
bsp/m16c62p/m16c62p.ld Normal file
View File

@ -0,0 +1,167 @@
MEMORY
{
ram (rw) : o = 0x0000400, l = 31k
rom (rx) : o = 0x00A0000, l = 384k
nrom(rx) : o = 0x0000F000, l = 4k
xram(rw) : o = 0x00028000, l = 4k
}
_system_stack_size = 0x800;
SECTIONS
{
/* Variable Vector Section */
.var_vects 0x000FA000 :
{
KEEP(*( .var_vects))
} > rom
.text 0x000DD000 :
{
*(.text)
*(.text.*)
/* section information for finsh shell */
. = ALIGN(4);
___fsymtab_start = .;
KEEP(*(FSymTab))
___fsymtab_end = .;
. = ALIGN(4);
___vsymtab_start = .;
KEEP(*(VSymTab))
___vsymtab_end = .;
. = ALIGN(4);
etext = .;
} > rom
.rodata :
{
_rodata = .;
*(.rodata)
*(.rodata.*)
*(.frodata)
_erodata = .;
} > rom
.init :
{
*(.init)
} > rom
.fini :
{
*(.fini)
} > rom
.got :
{
*(.got)
*(.got.plt)
} > rom
.eh_frame_hdr :
{
*(.eh_frame_hdr)
} > rom
.eh_frame :
{
*(.eh_frame)
} > rom
.jcr :
{
*(.jcr)
} > rom
.tors :
{
__CTOR_LIST__ = .;
___ctors = .;
*(.ctors)
___ctors_end = .;
__CTOR_END__ = .;
__DTOR_LIST__ = .;
___dtors = .;
*(.dtors)
___dtors_end = .;
__DTOR_END__ = .;
_mdata = .;
} > rom
.data 0x00000400 : AT (_mdata)
{
_data = .;
*(.data)
*(.data.*)
*(.ndata)
*(.ndata.*)
*(.plt)
_edata = .;
} > ram
.bss :
{
_bss = .;
*(.bss)
*(COMMON)
*(.nbss)
_ebss = .;
_end = .;
} > ram
.gcc_exc :
{
*(.gcc_exc)
} > ram
/* User Stack Pointer */
/*
.ustack 0x00003000 :
{
_ustack = .;
} > ram
*/
/* Interrupt Stack Pointer */
.istack :
{
. = . + _system_stack_size;
. = ALIGN(4);
_istack = .;
} > ram
. = ALIGN(4);
_user_ram_end = .;
.nrodata 0x0000F000 :
{
_nrodata = .;
*(.nrodata)
*(.nrodata.*)
_enrodata = .;
} > nrom
.fdata 0x00028000 : AT (_mdata + SIZEOF(.data))
{
_fdata = .;
*(.fdata)
*(.fdata.*)
_efdata = .;
} > xram
.fbss :
{
_fbss = .;
*(.fbss)
*(.fbss.*)
_efbss = .;
} > xram
/* Fixed Vector Section */
.vects 0x000FFFDC :
{
KEEP(*( .vects))
} > rom
}

74
bsp/m16c62p/rtconfig.h
View File

@ -75,78 +75,6 @@
///#define FINSH_USING_SYMTAB
///#define FINSH_USING_DESCRIPTION
/* SECTION: device filesystem support */
/* #define RT_USING_DFS */
///#define RT_USING_DFS_ELMFAT
/* the max number of mounted filesystem */
///#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
///#define DFS_FD_MAX 4
/* the max number of cached sector */
///#define DFS_CACHE_MAX_NUM 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
//#define RT_USING_LWIP
/* Enable ICMP protocol*/
///#define RT_LWIP_ICMP
/* Enable UDP protocol*/
///#define RT_LWIP_UDP
/* Enable TCP protocol*/
///#define RT_LWIP_TCP
/* Enable DNS */
///#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
///#define RT_LWIP_TCP_PCB_NUM 5
/* ip address of target*/
///#define RT_LWIP_IPADDR0 192
///#define RT_LWIP_IPADDR1 168
///#define RT_LWIP_IPADDR2 1
///#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
/* SECTION: RT-Thread/GUI */
/* #define RT_USING_RTGUI */
/* name length of RTGUI object */
#define RTGUI_NAME_MAX 12
/* support 16 weight font */
#define RTGUI_USING_FONT16
/* support Chinese font */
#define RTGUI_USING_FONTHZ
/* use DFS as file interface */
#define RTGUI_USING_DFS_FILERW
/* use font file as Chinese font */
#define RTGUI_USING_HZ_FILE
/* use small size in RTGUI */
#define RTGUI_USING_SMALL_SIZE
/* use mouse cursor */
/* #define RTGUI_USING_MOUSE_CURSOR */
/* default font size in RTGUI */
#define RTGUI_DEFAULT_FONT_SIZE 16
//#define RT_USING_NEWLIB
#endif

164
bsp/m16c62p/start.S Normal file
View File

@ -0,0 +1,164 @@
/****************************************************************
KPIT Cummins Infosystems Ltd, Pune, India.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*****************************************************************/
/* Start-up code for M16C targets only */
.text
.global _start
.type _start, @function
_start:
ldc #_istack, isp /* set interrupt stack pointer */
#ifndef EXT_RAM
mov.b #0x02,0x0a /* write enable in protect register */
mov.b #0x00,0x04 /* set processer mode :single chip mode */
/* 0x04 is the address of processor mode register 0 */
mov.b #0x00,0x0a /* write disable in protect register */
#endif
#if EXT_RAM
mov.w #0x000a,a0 /* Write enable in protect register */
mov.b #0xff,[a0]
mov.w #0x04,a0 /* Memory expansion mode, WRH/WRL/RD signals */
mov.b #0x05,[a0]
mov.w #0x05,a0 /* Insert wait, no limit in on-chip memory */
mov.b #0x88,[a0]
mov.w #0x08,a0 /* Enable all the CS signals with wait */
mov.b #0x0F,[a0]
mov.w #0x0a,a0 /* write disable in protect register */
mov.b #0x00,[a0]
#endif
; ldc #0x0080,flg /* select USER STACK POINTER (BIT7=1,USP) (BIT7=0,ISP) */
; ldc #_ustack,sp /* set user stack pointer */
/* INTERRUPT VECTOR ADDRESS definition */
ldc #0xF, intbh /* load upper 4 bits of variable vector address in intbh */
ldc #0xA000, intbl /* load lower 16 bits of variable vector address in intbl */
fset I /* ADD THIS TO ENABLE INTERRUPTS */
/* call the hardware initialiser */
; jsr.a _hw_initialise
/* load data section from ROM to RAM */
mov.b #%hi8(_mdata),r1h /* move upper 4 bits of the 20 bit address (_mdata) to, r1h */
mov.w #%lo16(_mdata),a0 /* move lower 16 bits of the 20 bit address (_mdata) to,a0 */
mov.w #_data,a1 /* store the start address of data section in, A1 */
mov.w #_edata,r3 /* store the end address of data section in R3 */
sub.w a1,r3 /* R3=R3-A1. Store size of data section in R3 */
mov.w r3,r2 /* Store size of data section in R2 */
smovf.b
/* bss initialisation : zero out bss */
mov.b #0x00,R0L /* load R0L reg with 0x0 (value at which bss section will be initialised) */
mov.w #_bss, a1 /* store the start address of bss in A1 */
mov.w #_ebss, a0 /* store the end address of bss in A0 */
sub.w a1,a0 /* (A0 = A0-A1) */
mov.w a0,r3 /* Store size of bss section in reg R3 */
sstr.b
#if EXT_RAM
/* load fdata section from ROM to External RAM only if EXT_RAM is defined */
pushc sp /*store stack pointer in stack */
popc fb /*copy the stack pointer in frame base register */
push.w #%hi16(_mdata) /* offset of -2 from fb: store higher 16 bits of _mdata */
push.w #%lo16(_mdata) /* offset of -4 from fb: store lower 16 bits of _mdata */
mov.w #_edata,r0 /* end address of data section */
mov.w #_data,r1 /* start address of data section */
sub.w r1,r0 /* size of data section in r0 */
add.w r0,-4[fb] /* store the lower 16 bits of source address on stack */
adc.w #0,-2[fb] /* store the higher 4 bits of source address on stack */
push.w #%hi16(_fdata) /* offset -6 from fp: store the higher 4 bits of destination address on stack */
push.w #%lo16(_fdata) /* offset -8 from fp: store the lower 16 bits of destination address on stack */
push.w #%hi16(_efdata) /* offset -10 from fp: higher 16 bits of _efdata */
push.w #%lo16(_efdata) /* offset -12 from fp: lower 16 bits of _efdata */
label1:
cmp.w -6[fb],-10[fb] /* Compare higher 16 bits of _fdata and _efdata */
jnz label2
cmp.w -8[fb],-12[fb] /* Compare lower 16 bits of _fdata and _efdata */
jeq init_fdata_end
label2:
mov.w -2[fb],a1 /* Copy higher 16 bits of source in A1 */
mov.w -4[fb],a0 /* Copy lower 16 bits of source in A1 */
lde.b [a1a0],r0l /* Copy contents of a1a0 in r0l */
mov.w -6[fb],a1 /* Copy higher 16 bits of destination in A1 */
mov.w -8[fb],a0 /* Copy lower 16 bits of destination in A0 */
ste.b r0l,[a1a0] /* store r0l contents at [a1a0] */
add.w #0x01,-4[fb] /* increment lower 16 bits of source */
adcf.w -2[fb] /* add carry to higher 16 bits of source */
add.w #0x01,-8[fb] /* increment lower 16 bits of destination */
adcf.w -6[fb] /* add carry to higher 16 bits of destination */
jmp.b label1
init_fdata_end:
pop.w r0 /* clean stack */
pop.w r0
pop.w r0
pop.w r0
pop.w r0
pop.w r0
/* Zero out fbss section */
push.w #%hi16(_fbss) /* offset of -2 from fb: higher 16 bits of _fbss */
push.w #%lo16(_fbss) /* offset of -4 from fb: lower 16 bits of _fbss */
push.w #%hi16(_efbss) /* offset of -6 from fb: higer 16 bits of _efbss */
push.w #%lo16(_efbss) /* offset of -8 from fb: lower 16 bits of _efbss */
mov.b #0x00,r0l
label3:
cmp.w -2[fb],-6[fb] /* Compare higher 16 bits of _fdata and _efdata */
jnz label4
cmp.w -4[fb],-8[fb] /* Compare lower 16 bits of _fdata and _efdata */
jeq init_fbss_end
label4:
mov.w -2[fb],a1 /* Copy higher 16 bits of source in A1 */
mov.w -4[fb],a0 /* Copy lower 16 bits of source in A1 */
ste.b r0l,[a1a0] /* store r0l contents at [a1a0] */
add.w #0x01,-4[fb] /* increment lower 16 bits of _fbss */
adcf.w -2[fb] /* add carry to higher 16 bits of _fbss */
jmp.b label3
init_fbss_end:
pop.w r0 /* clean stack */
pop.w r0
pop.w r0
pop.w r0
#endif
/* start user program */
jsr.a _main
.end

6
bsp/m16c62p/startup.c
View File

@ -28,8 +28,10 @@ extern void finsh_set_device(const char* device);
#endif
#ifdef RT_USING_HEAP
#ifdef __ICCM16C__
#if (defined (__ICCM16C__))
#pragma section="DATA16_HEAP"
#elif (defined (__GNUC__))
extern unsigned char user_ram_end;
#endif
#endif
@ -59,6 +61,8 @@ void rtthread_startup(void)
#ifdef RT_USING_HEAP
#ifdef __ICCM16C__
rt_system_heap_init(__segment_begin("DATA16_HEAP"), __segment_end("DATA16_HEAP"));
#elif (defined (__GNUC__))
rt_system_heap_init((void*)&user_ram_end, (void*)M16C62P_SRAM_END);
#endif
#endif

34
bsp/m16c62p/uart.c
View File

@ -37,9 +37,9 @@ void u0rec_handler(void)
struct rt_uart_m16c *uart = &uart_device;
while(ri_u0c1 == 0)
while (U0C1.BIT.RI == 0)
;
c = (char) u0rb;
c = U0RB.BYTE.U0RBL;
/* Receive Data Available */
uart->rx_buffer[uart->save_index] = c;
@ -70,10 +70,10 @@ static rt_err_t rt_uart_init (rt_device_t dev)
bit rate = ((BRG count source / 16)/baud rate) - 1
Baud rate is based on main crystal or PLL not CPU core clock */
//pclk1 = 1; /// seleck F1SIO
u0brg = (unsigned char)(((CPU_CLK_FREQ/16)/BAUD_RATE)-1); //(N+1)
U0BRG = (unsigned char)(((CPU_CLK_FREQ/16)/BAUD_RATE)-1); //(N+1)
/* UART Transmit/Receive Control Register 2 */
ucon = 0x00;
UCON.BYTE = 0x00;
/* 00000000
b0 U0IRS UART0 transmit irq cause select bit, 0 = transmit buffer empty
b1 U1IRS UART1 transmit irq cause select bit, 0 = transmit buffer empty
@ -86,7 +86,7 @@ static rt_err_t rt_uart_init (rt_device_t dev)
/* UART0 transmit/receive control register 0 */
/* f1 count source, CTS/RTS disabled, CMOS output */
u0c0 = 0x10;
U0C0.BYTE = 0x10;
/* 00010000
b1:b0 CLK01:CLK0 BRG count source select bits //01 F8SIO
b2 CRS CTS/RTS function select bit
@ -98,7 +98,7 @@ static rt_err_t rt_uart_init (rt_device_t dev)
/* UART0 transmit/receive control register 1 */
/* disable transmit and receive, no error output pin, data not inverted */
u0c1 = 0x00;
U0C1.BYTE = 0x00;
/* 00000000
b0 TE Transmit enable bit
b1 TI Transmit buffer empty flag
@ -110,7 +110,7 @@ static rt_err_t rt_uart_init (rt_device_t dev)
/* UART0 transmit/receive mode register */
/* 8-bit data,asynch mode, internal clock, 1 stop bit, no parity */
u0mr = 0x05;
U0MR.BYTE = 0x05;
/* 00000101
b2:b0 SMD12:SMD1 Serial I/O Mode select bits
b3 CKDIR Internal/External clock select bit, CKDIR
@ -120,20 +120,20 @@ static rt_err_t rt_uart_init (rt_device_t dev)
b7 IOPOL TxD, RxD I/O polarity reverse bit */
/* clear UART0 receive buffer by reading */
u0tb = u0rb;
U0TB.WORD = U0RB.WORD;
/* clear UART0 transmit buffer */
u0tb = 0;
U0TB.WORD = 0;
/* disable irqs before setting irq registers */
level = rt_hw_interrupt_disable();
/* Enable UART0 receive interrupt, priority level 4 */
s0ric = 0x04;
S0RIC.BYTE = 0x04;
/* Enable all interrupts */
rt_hw_interrupt_enable(level);
/* UART0 transmit/receive control register 1 */
/* enable transmit and receive */
u0c1 = 0x05;
U0C1.BYTE = 0x05;
/* 00000101 enable transmit and receive
b0 TE Transmit enable bit
b1 TI Transmit buffer empty flag
@ -227,15 +227,15 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer
{
if (*ptr == '\n')
{
while(ti_u0c1 == 0)
while (U0C1.BIT.TI == 0)
;
u0tb = '\r';
U0TB.BYTE.U0TBL = '\r';
}
/* THRE status, contain valid data */
while(ti_u0c1 == 0)
while (U0C1.BIT.TI == 0)
;
u0tb = *ptr;
U0TB.BYTE.U0TBL = *ptr;
ptr ++;
size --;
@ -246,9 +246,9 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer
while (size != 0)
{
/* THRE status, contain valid data */
while(ti_u0c1 == 0)
while (U0C1.BIT.TI == 0)
;
u0tb = *ptr;
U0TB.BYTE.U0TBL = *ptr;
ptr ++;
size --;

71
bsp/m16c62p/vects.S Normal file
View File

@ -0,0 +1,71 @@
;/****************************************************************
;KPIT Cummins Infosystems Ltd, Pune, India. 17-June-2005.
;
;This program is distributed in the hope that it will be useful,
;but WITHOUT ANY WARRANTY; without even the implied warranty of
;MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
;
;*****************************************************************/
; Fixed Vector Table
.section .vects,"a",@progbits
.type _HardwareVectors, @object
.size _HardwareVectors, 36
_HardwareVectors:
.long 0 ;(Undefined Instruction) Interrupt on UND instruction
.long 0 ;(Overflow) Interrupt on INTO instruction
.long 0 ;(BRK) If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table
.long 0 ;(Address match)There is an address-matching interrupt enable bit
.long 0 ;Single step (debugger)
.long 0 ;Watchdog timer
.long 0 ;DBC (debugger)
.long 0 ;(NMI)External interrupt by input to NMI pin
.long (_start + 0xFF000000) ; Reset
; Variable Vector Table
; .global _rt_hw_uart0_receive_handler
; .global _rt_hw_timer_handler
.global _VariableVectors
.section .var_vects,"a",@progbits
.type _VariableVectors, @object
.size _VariableVectors, 128
_VariableVectors:
.long _os_context_switch ; Vector 0: BRK
.long 0 ; Vector 1: Reserved
.long 0 ; Vector 2: Reserved
.long 0 ; Vector 3: Reserved
.long 0 ; Vector 4: INT3
.long 0 ; Vector 5: Timer B5
.long 0 ; Vector 6: Timer B4, UART1 Bus Collision Detect
.long 0 ; Vector 7: Timer B3, UART0 Bus Collision Detect
.long 0 ; Vector 8: SI/O4, INT5
.long 0 ; Vector 9: SI/O3, INT4
.long 0 ; Vector 10: UART2 Bus Collision Detect
.long 0 ; Vector 11: DMA0
.long 0 ; Vector 12: DMA1
.long 0 ; Vector 13: Key Input Interrupt
.long 0 ; Vector 14: A/D
.long 0 ; Vector 15: UART2 Transmit, NACK2
.long 0 ; Vector 16: UART2 Receive, ACK2
.long 0 ; Vector 17: UART0 Transmit, NACK0
.long _rt_hw_uart0_receive_handler ; Vector 18: UART0 Receive, ACK0
.long 0 ; Vector 19: UART1 Transmit, NACK1
.long 0 ; Vector 20: UART1 Receive, ACK1
.long 0 ; Vector 21: Timer A0
.long 0 ; Vector 22: Timer A1
.long 0 ; Vector 23: Timer A2
.long 0 ; Vector 24: Timer A3
.long 0 ; Vector 25: Timer A4
.long _rt_hw_timer_handler ; Vector 26: Timer B0
.long 0 ; Vector 27: Timer B1
.long 0 ; Vector 28: Timer B2
.long 0 ; Vector 29:
.long 0 ; Vector 30:
.long 0 ; Vector 31:
.end

47
libcpu/m16c/m16c62p/context_gcc.S Normal file
View File

@ -0,0 +1,47 @@
/*
* File : context.asm
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-04-09 fify the first version
* 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
* 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
*/
.section .text
.globl _rt_interrupt_from_thread
.globl _rt_interrupt_to_thread
.global _os_context_switch
.type _os_context_switch, @function
_os_context_switch:
PUSHM R0,R1,R2,R3,A0,A1,SB,FB
MOV.W _rt_interrupt_from_thread, A0
STC ISP, [A0]
MOV.W _rt_interrupt_to_thread, A0
LDC [A0], ISP
POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
REIT ; Return from interrup
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* this fucntion is used to perform the first thread switch
*/
.global _rt_hw_context_switch_to
.type _rt_hw_context_switch_to, @function
_rt_hw_context_switch_to:
ENTER #0x0
MOV.W 0x5[FB], A0
LDC [A0], ISP
POPM R0,R1,R2,R3,A0,A1,SB,FB
REIT
.end

20
libcpu/m16c/m16c62p/cpuport.c
View File

@ -88,3 +88,23 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to)
}
rt_interrupt_to_thread = to;
}
#if defined(__GNUC__)
rt_base_t rt_hw_interrupt_disable(void)
{
register rt_uint16_t temp;
asm("STC FLG, %0":"=r" (temp));
asm("FCLR I");
return (rt_base_t)temp;
}
void rt_hw_interrupt_enable(rt_base_t level)
{
register rt_uint16_t temp;
temp = level & 0xffff;
asm("LDC %0, FLG": :"r" (temp));
}
#endif