diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S
index af6c9934d4..5985d54fb3 100644
--- a/libcpu/arm/cortex-m4/context_gcc.S
+++ b/libcpu/arm/cortex-m4/context_gcc.S
@@ -145,16 +145,16 @@ switch_to_thread:
 
     MSR psp, r1                 /* update stack pointer */
 
-pendsv_exit:
-    /* restore interrupt */
-    MSR PRIMASK, r2
-
 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     ORR     lr, lr, #0x10       /* lr |=  (1 << 4), clean FPCA. */
     CMP     r3,  #0             /* if(flag_r3 != 0) */
     BICNE   lr, lr, #0x10       /* lr &= ~(1 << 4), set FPCA. */
 #endif
 
+pendsv_exit:
+    /* restore interrupt */
+    MSR PRIMASK, r2
+
     ORR lr, lr, #0x04
     BX  lr
 
diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S
index 4cc9539112..c34600ea4c 100644
--- a/libcpu/arm/cortex-m4/context_iar.S
+++ b/libcpu/arm/cortex-m4/context_iar.S
@@ -149,10 +149,6 @@ skip_pop_fpu
 
     MSR     psp, r1                 ; update stack pointer
 
-pendsv_exit
-    ; restore interrupt
-    MSR     PRIMASK, r2
-
 #if defined ( __ARMVFP__ )
     ORR     lr, lr, #0x10           ; lr |=  (1 << 4), clean FPCA.
     CBZ     r3, return_without_fpu  ; if(flag_r3 != 0)
@@ -160,6 +156,10 @@ pendsv_exit
 return_without_fpu
 #endif
 
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
     ORR     lr, lr, #0x04
     BX      lr
 
diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S
index ea894ed000..5cae619287 100644
--- a/libcpu/arm/cortex-m4/context_rvds.S
+++ b/libcpu/arm/cortex-m4/context_rvds.S
@@ -147,16 +147,16 @@ switch_to_thread
 
     MSR     psp, r1                 ; update stack pointer
 
-pendsv_exit
-    ; restore interrupt
-    MSR     PRIMASK, r2
-
     IF      {FPU} != "SoftVFP"
     ORR     lr, lr, #0x10           ; lr |=  (1 << 4), clean FPCA.
     CMP     r3,  #0                 ; if(flag_r3 != 0)
     BICNE   lr, lr, #0x10           ; lr &= ~(1 << 4), set FPCA.
     ENDIF
 
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
     ORR     lr, lr, #0x04
     BX      lr
     ENDP
diff --git a/libcpu/arm/cortex-m7/context_gcc.S b/libcpu/arm/cortex-m7/context_gcc.S
index af6c9934d4..5985d54fb3 100644
--- a/libcpu/arm/cortex-m7/context_gcc.S
+++ b/libcpu/arm/cortex-m7/context_gcc.S
@@ -145,16 +145,16 @@ switch_to_thread:
 
     MSR psp, r1                 /* update stack pointer */
 
-pendsv_exit:
-    /* restore interrupt */
-    MSR PRIMASK, r2
-
 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     ORR     lr, lr, #0x10       /* lr |=  (1 << 4), clean FPCA. */
     CMP     r3,  #0             /* if(flag_r3 != 0) */
     BICNE   lr, lr, #0x10       /* lr &= ~(1 << 4), set FPCA. */
 #endif
 
+pendsv_exit:
+    /* restore interrupt */
+    MSR PRIMASK, r2
+
     ORR lr, lr, #0x04
     BX  lr
 
diff --git a/libcpu/arm/cortex-m7/context_iar.S b/libcpu/arm/cortex-m7/context_iar.S
index 4cc9539112..c34600ea4c 100644
--- a/libcpu/arm/cortex-m7/context_iar.S
+++ b/libcpu/arm/cortex-m7/context_iar.S
@@ -149,10 +149,6 @@ skip_pop_fpu
 
     MSR     psp, r1                 ; update stack pointer
 
-pendsv_exit
-    ; restore interrupt
-    MSR     PRIMASK, r2
-
 #if defined ( __ARMVFP__ )
     ORR     lr, lr, #0x10           ; lr |=  (1 << 4), clean FPCA.
     CBZ     r3, return_without_fpu  ; if(flag_r3 != 0)
@@ -160,6 +156,10 @@ pendsv_exit
 return_without_fpu
 #endif
 
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
     ORR     lr, lr, #0x04
     BX      lr
 
diff --git a/libcpu/arm/cortex-m7/context_rvds.S b/libcpu/arm/cortex-m7/context_rvds.S
index 38410c8a3b..dc9a958646 100644
--- a/libcpu/arm/cortex-m7/context_rvds.S
+++ b/libcpu/arm/cortex-m7/context_rvds.S
@@ -147,16 +147,16 @@ switch_to_thread
 
     MSR     psp, r1                 ; update stack pointer
 
-pendsv_exit
-    ; restore interrupt
-    MSR     PRIMASK, r2
-
     IF      {FPU} != "SoftVFP"
     ORR     lr, lr, #0x10           ; lr |=  (1 << 4), clean FPCA.
     CMP     r3,  #0                 ; if(flag_r3 != 0)
     BICNE   lr, lr, #0x10           ; lr &= ~(1 << 4), set FPCA.
     ENDIF
 
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
     ORR     lr, lr, #0x04
     BX      lr
     ENDP