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[imxrt 1170]add flexspi support (#6429) 

* [imxrt 1170]add flexspi support

* format file

* format file

* update flexspi serial root clk to 80MHz

* format file
This commit is contained in:
xiao xie 2022-09-15 17:08:26 +08:00 committed by GitHub
parent 09e29c4d93
commit a0ca06b499
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 245 additions and 1 deletions
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14
bsp/imxrt/imxrt1170-nxp-evk/board/Kconfig
View File

@ -32,7 +32,7 @@ menu "On-chip Peripheral Drivers"
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
default n
menuconfig BSP_USING_LPUART
bool "Enable UART"
@ -106,6 +106,18 @@ menu "On-chip Peripheral Drivers"
bool "Enable FLEXCAN3"
default n
endif
menuconfig BSP_USING_FLEXSPI
bool "Enable FLEXSPI"
default n
if BSP_USING_FLEXSPI
config BSP_USING_FLEXSPI1
bool "Enable FLEXCAN1"
default n
config BSP_USING_FLEXSPI2
bool "Enable FLEXCAN2"
default n
endif
endmenu
menu "Onboard Peripheral Drivers"

49
bsp/imxrt/imxrt1170-nxp-evk/board/board.c
View File

@ -10,6 +10,7 @@
* 2022-08-17 xjy198903 add rgmii pins
* 2022-09-01 xjy198903 add can pins
* 2022-09-07 xjy198903 add sdio pins
* 2022-09-14 xjy198903 add flexspi pins
*/
#include <rthw.h>
@ -1273,6 +1274,50 @@ void imxrt_can_pins_init(void)
}
#endif
#ifdef BSP_USING_FLEXSPI
void imxrt_flexspi_pins_init(void)
{
#ifdef BSP_USING_FLEXSPI1
CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03, /* GPIO_SD_B2_00 is configured as FLEXSPI1_B_DATA03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02, /* GPIO_SD_B2_01 is configured as FLEXSPI1_B_DATA02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01, /* GPIO_SD_B2_02 is configured as FLEXSPI1_B_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00, /* GPIO_SD_B2_03 is configured as FLEXSPI1_B_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS, /* GPIO_SD_B2_05 is configured as FLEXSPI1_A_DQS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B, /* GPIO_SD_B2_06 is configured as FLEXSPI1_A_SS0_B */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK, /* GPIO_SD_B2_07 is configured as FLEXSPI1_A_SCLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00, /* GPIO_SD_B2_08 is configured as FLEXSPI1_A_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01, /* GPIO_SD_B2_09 is configured as FLEXSPI1_A_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02, /* GPIO_SD_B2_10 is configured as FLEXSPI1_A_DATA02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03, /* GPIO_SD_B2_11 is configured as FLEXSPI1_A_DATA03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
#endif
}
#endif
void rt_hw_board_init()
{
BOARD_ConfigMPU();
@ -1313,5 +1358,9 @@ void rt_hw_board_init()
#ifdef BSP_USING_CAN
imxrt_can_pins_init();
#endif
#ifdef BSP_USING_FLEXSPI
imxrt_flexspi_pins_init();
#endif
}

32
bsp/imxrt/imxrt1170-nxp-evk/board/ports/flexspi_port.h Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-08-15 xjy198903 The first version for rt1170
*/
#ifndef FLEXSPI_PORT_H__
#define FLEXSPI_PORT_H__
/* parameters for flexpsi peripheral */
#define FLEXSPI1_CONTROL_BASE FLEXSPI1
#define FLEXSPI2_CONTROL_BASE FLEXSPI2
#define FLEXSPI_ROOT_CLK (80000000U) /* serial root clk: 80MHz*/
#define FLASH_SIZE (32 * 1024) /* device size 32*1024(KB) = 32MB */
#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */
#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */
#define AWR_SEQ_NUMBER 1 /* Sequence number for AHB write command */
#define AWR_SEQ_INDEX 1 /* Sequence ID for AHB write command */
#define ARD_SEQ_CMD 0xBB /* cmd for read */
#define AWR_SEQ_CMD 0xAA /* cmd for write */
#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkExternalInputFromDqsPad
#define FLASH_PORT kFLEXSPI_PortA1
#define CLOCK_SRC kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M
#define CLOCK_DIV 5U
#define CUSTOM_LUT_LENGTH 64U
#define FLEXSPI1_AHB_DATA_ADDRESS (0x30000000U)
#define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U)
#endif /* FLEXSPI_PORT_H__ */

3
bsp/imxrt/libraries/MIMXRT1170/SConscript
View File

@ -49,6 +49,9 @@ if GetDepend(['BSP_USING_ETH']):
if GetDepend(['RT_USING_CAN']):
src += ['MIMXRT1176/drivers/fsl_flexcan.c']
if GetDepend(['BSP_USING_FLEXSPI']):
src += ['MIMXRT1176/drivers/fsl_flexspi.c']
if rtconfig.PLATFORM in ['gcc']:
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, ASFLAGS = '$ASFLAGS -D __STARTUP_CLEAR_BSS')
else:

3
bsp/imxrt/libraries/drivers/SConscript
View File

@ -76,6 +76,9 @@ if GetDepend('RT_USING_USB_HOST'):
if GetDepend('BSP_USING_PULSE_ENCODER'):
src += ['drv_pulse_encoder.c']
if GetDepend('BSP_USING_FLEXSPI'):
src += ['drv_flexspi.c']
src += ['drv_common.c']
path = [cwd]

145
bsp/imxrt/libraries/drivers/drv_flexspi.c Normal file
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@ -0,0 +1,145 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-09-14 xjy198903 the first version for 1170
*/
#include <rtthread.h>
#ifdef BSP_USING_FLEXSPI
#include "board.h"
#include <rtdevice.h>
#ifdef RT_USING_FINSH
#include <finsh.h>
#endif
#include "flexspi_port.h"
#include "fsl_flexspi.h"
#define COMBINATION_MODE 1U
#define FREE_RUNNING_MODE 1U
#define FLEXSPI_DEBUG
#define LOG_TAG "drv.flexspi"
#include <drv_log.h>
static flexspi_device_config_t deviceconfig = {
.flexspiRootClk = 12000000,
.flashSize = FLASH_SIZE,
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
.CSInterval = 2,
.CSHoldTime = 3,
.CSSetupTime = 3,
.dataValidTime = 0,
.columnspace = 0,
.enableWordAddress = 0,
.AWRSeqIndex = AWR_SEQ_INDEX,
.AWRSeqNumber = AWR_SEQ_NUMBER,
.ARDSeqIndex = ARD_SEQ_INDEX,
.ARDSeqNumber = ARD_SEQ_NUMBER,
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
.AHBWriteWaitInterval = 0,
};
const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
/* 8bit mode */
[4 * ARD_SEQ_INDEX] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
};
static void flexspi_clock_init(clock_root_t root, uint8_t src, uint8_t div)
{
/*Clock setting for flexspi1*/
CLOCK_SetRootClockDiv(root, div);
CLOCK_SetRootClockMux(root, src);
}
static int rt_hw_imxrt_flexspi_init(void)
{
flexspi_config_t config;
FLEXSPI_Type *base;
#ifdef BSP_USING_FLEXSPI1
base = FLEXSPI1_CONTROL_BASE;
#else
base = FLEXSPI2_CONTROL_BASE;
#endif
//Set root clk 80MHz
flexspi_clock_init(kCLOCK_Root_Flexspi1, CLOCK_SRC, CLOCK_DIV);
/*Get FLEXSPI default settings and configure the flexspi. */
FLEXSPI_GetDefaultConfig(&config);
/*Set AHB buffer size for reading data through AHB bus. */
config.ahbConfig.enableAHBPrefetch = true;
config.ahbConfig.enableAHBBufferable = true;
config.ahbConfig.enableReadAddressOpt = true;
config.ahbConfig.enableAHBCachable = true;
config.ahbConfig.enableClearAHBBufferOpt = true;
config.rxSampleClock = FLEXSPI_RX_SAMPLE_CLOCK;
if(COMBINATION_MODE)
{
config.enableCombination = true;
}
if(FREE_RUNNING_MODE)
{
config.enableSckFreeRunning = true;
}
FLEXSPI_Init(base, &config);
/* Configure flash settings according to serial flash feature. */
FLEXSPI_SetFlashConfig(base, &deviceconfig, FLASH_PORT);
/* Update LUT table. */
FLEXSPI_UpdateLUT(base, 0, customLUT, CUSTOM_LUT_LENGTH);
/* Do software reset. */
FLEXSPI_SoftwareReset(base);
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_imxrt_flexspi_init);
#ifdef FLEXSPI_DEBUG
#ifdef FINSH_USING_MSH
#define FLEXSPI_DATALEN 4U
static rt_uint32_t send_buf[FLEXSPI_DATALEN] = {0x11223344, 0x55667788, 0x12345678, 0x9900aabb};
static uint32_t recv_buf[FLEXSPI_DATALEN];
/* read write 32bit test */
static void flexspi_test(void)
{
volatile rt_uint32_t *flexspi = (rt_uint32_t *)FLEXSPI1_AHB_DATA_ADDRESS; /* FLEXSPI1 start address. */
LOG_D("FLEXSPI Memory 32 bit Write Start\n");
*(flexspi + 15) = send_buf[3];
*(flexspi + 8) = send_buf[1];
*(flexspi + 11) = send_buf[2];
*(flexspi + 3) = send_buf[0];
LOG_D("FLEXSPI Memory 32 bit Write End\n");
memset(recv_buf, 0, sizeof(recv_buf));
LOG_D("FLEXSPI Memory 32 bit Read Start\n");
recv_buf[2] = *(flexspi + 11);
recv_buf[3] = *(flexspi + 15);
recv_buf[1] = *(flexspi + 8);
recv_buf[0] = *(flexspi + 3);
LOG_D("FLEXSPI Memory 32 bit Read End\n");
LOG_D("addr12 is 0x%x\n", recv_buf[0]);
LOG_D("addr32 is 0x%x\n", recv_buf[1]);
LOG_D("addr44 is 0x%x\n", recv_buf[2]);
LOG_D("addr60 is 0x%x\n", recv_buf[3]);
}
MSH_CMD_EXPORT(flexspi_test, flexspi test)
#endif /* FLEXSPI_DEBUG */
#endif /* FINSH_USING_MSH */
#endif /* BSP_USING_FLEXSPI */