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[efm32] auto formatted

This commit is contained in:
Meco Man 2021-03-27 15:16:57 +08:00
parent 1ba020f3c8
commit 9f2192a03d
74 changed files with 4406 additions and 4406 deletions
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4
bsp/efm32/EFM32GG_DK3750/dvk.h
View File

@ -164,7 +164,7 @@ int DVK_BRD3600A_usbVBUSGetOCFlagState(void);
/* For "backward compatibility" with DVK */
/** DVK_enablePeripheral() backward compatibility */
#define DVK_enablePeripheral(X) DVK_peripheralAccess(X, true)
#define DVK_enablePeripheral(X) DVK_peripheralAccess(X, true)
/** DVK_disablePeripheral() backward compatibility */
#define DVK_disablePeripheral(X) DVK_peripheralAccess(X, false)
@ -193,7 +193,7 @@ __STATIC_INLINE uint16_t DVK_EBI_readRegister(volatile uint16_t *addr)
/**************************************************************************//**
* @brief Read data from 16-bit board control register
* @param addr Register to read
* @return Value of board controller register
* @return Value of board controller register
*****************************************************************************/
__STATIC_INLINE uint16_t DVK_readRegister(volatile uint16_t *addr)
{

4
bsp/efm32/EFM32GG_DK3750/trace.c
View File

@ -125,7 +125,7 @@ void TRACE_SWOSetup(void)
/**************************************************************************//**
* @brief Profiler configuration for EFM32GG990F11024/EFM32GG-DK3750
* @return true if energyAware Profiler/SWO is enabled, false if not
* @note If first word of the user page is zero, this will not
* @note If first word of the user page is zero, this will not
* enable SWO profiler output
*****************************************************************************/
bool TRACE_ProfilerSetup(void)
@ -141,7 +141,7 @@ bool TRACE_ProfilerSetup(void)
{
TRACE_SWOSetup();
return true;
}
}
}
/** @} (end group BSP) */

4
bsp/efm32/EFM32GG_DK3750/trace.h
View File

@ -58,7 +58,7 @@ bool TRACE_ProfilerSetup(void);
* for TRACE_ProfilerSetup. If TRACE_ProfilerEnable(false) has been run,
* no example project will enable SWO trace.
* @param[in] enable
* @note Add "em_msc.c" to build to use this function.
* @note Add "em_msc.c" to build to use this function.
*****************************************************************************/
__STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
{
@ -69,7 +69,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
data = *userpage;
if(enable)
{
if(data == 0xFFFFFFFF)
if(data == 0xFFFFFFFF)
{
return;
}

2
bsp/efm32/EFM32_Gxxx_DK/dvk.c
View File

@ -52,7 +52,7 @@ bool DVK_init(void)
#endif
#ifdef DVK_SPI_CONTROL
ret = DVK_SPI_init();
#endif
#endif
if ( ret == false )
{
/* Board is configured in wrong mode, please restart KIT! */

2
bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h
View File

@ -73,7 +73,7 @@
#define BC_HW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x14)) /**< HW version */
#define BC_FW_BUILDNO ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x15)) /**< FW build number */
#define BC_FW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x16)) /**< FW version */
#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17)) /**< Scratch common */
#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17)) /**< Scratch common */
#define BC_SCRATCH_EFM0 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x18)) /**< Scratch EFM0 */
#define BC_SCRATCH_EFM1 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x19)) /**< Scratch EFM1 */
#define BC_SCRATCH_EFM2 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1A)) /**< Scratch EFM2 */

4
bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c
View File

@ -155,7 +155,7 @@ uint16_t DVK_getPushButtons(void)
/* Check state */
aemState = DVK_readRegister(BC_AEMSTATE);
/* Read pushbutton status */
if ( aemState == BC_AEMSTATE_EFM )
if ( aemState == BC_AEMSTATE_EFM )
{
pb = (~(DVK_readRegister(BC_PUSHBUTTON))) & 0x000f;
}
@ -174,7 +174,7 @@ uint16_t DVK_getJoystick(void)
/* Check state */
aemState = DVK_readRegister(BC_AEMSTATE);
/* Read pushbutton status */
if ( aemState == BC_AEMSTATE_EFM )
if ( aemState == BC_AEMSTATE_EFM )
{
joyStick = (~(DVK_readRegister(BC_JOYSTICK))) & 0x001f;
}

6
bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c
View File

@ -163,7 +163,7 @@ bool DVK_EBI_init(void)
* be configured for EBI access */
ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
while ((ebiMagic != BC_MAGIC_VALUE) && retry)
{
{
DVK_EBI_disable();
/* Enable SPI interface */
DVK_SPI_init();
@ -172,13 +172,13 @@ bool DVK_EBI_init(void)
DVK_SPI_writeRegister(BC_CFG, BC_CFG_EBI);
/* Disable SPI */
DVK_SPI_disable();
/* Now setup EBI again */
DVK_EBI_configure();
/* Wait until ready */
ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
if (ebiMagic == BC_MAGIC_VALUE) break;
retry--;
}
if ( ! retry ) return false;

8
bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c
View File

@ -106,7 +106,7 @@ static void spiInit(void)
/* Configure SPI bus connect pins, DOUT set to 0, disable EBI */
GPIO_PinModeSet(PORT_SPIBUS_CONNECT, PIN_SPIBUS_CONNECT, gpioModePushPull, 0);
GPIO_PinModeSet(PORT_EBIBUS_CONNECT, PIN_EBIBUS_CONNECT, gpioModePushPull, 1);
/* Configure SPI pins */
GPIO_PinModeSet(PORT_SPI_TX, PIN_SPI_TX, gpioModePushPull, 0);
GPIO_PinModeSet(PORT_SPI_RX, PIN_SPI_RX, gpioModePushPull, 0);
@ -164,11 +164,11 @@ static uint16_t spiAccess(uint8_t spiaddr, uint8_t rw, uint16_t spidata)
/* Just ignore data read back */
USART_Rx(USART_USED);
/* SPI data LSB */
/* SPI data LSB */
USART_Tx(USART_USED, spidata & 0xFF);
tmp = (uint16_t)USART_Rx(USART_USED);
/* SPI data MSB */
/* SPI data MSB */
USART_Tx(USART_USED, spidata >> 8);
tmp |= (uint16_t)USART_Rx(USART_USED) << 8;
@ -213,7 +213,7 @@ bool DVK_SPI_init(void)
if(spiMagic != BC_MAGIC_VALUE)
{
return false;
}
}
else
{
return true;

4
bsp/efm32/EFM32_Gxxx_DK/trace.c
View File

@ -89,7 +89,7 @@ void TRACE_SWOSetup(void)
/**************************************************************************//**
* @brief Profiler configuration
* @return true if energyAware Profiler/SWO is enabled, false if not
* @note If first word of the user page is zero, this will not
* @note If first word of the user page is zero, this will not
* enable SWO profiler output, see trace.h
*****************************************************************************/
bool TRACE_ProfilerSetup(void)
@ -105,7 +105,7 @@ bool TRACE_ProfilerSetup(void)
{
TRACE_SWOSetup();
return true;
}
}
}
/** @} (end group BSP) */

6
bsp/efm32/EFM32_Gxxx_DK/trace.h
View File

@ -58,7 +58,7 @@ bool TRACE_ProfilerSetup(void);
* in TRACE_ProfilerSetup. If TRACE_ProfilerEnable(false) has been run,
* no example project will enable SWO trace.
* @param[in] enable
* @note Add "em_msc.c" to build to use this function.
* @note Add "em_msc.c" to build to use this function.
*****************************************************************************/
__STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
{
@ -69,7 +69,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
data = *userpage;
if(enable)
{
if(data == 0xFFFFFFFF)
if(data == 0xFFFFFFFF)
{
return;
}
@ -81,7 +81,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
return;
}
}
/* Initialize MSC */
MSC_Init();

40
bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h
View File

@ -1,24 +1,24 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 11. November 2010
* $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 11. November 2010
* $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H

660
bsp/efm32/Libraries/CMSIS/Include/arm_math.h
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File diff suppressed because it is too large Load Diff

6
bsp/efm32/Libraries/CMSIS/Include/core_cm3.h
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@ -636,14 +636,14 @@ typedef struct
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
uint32_t RESERVED3[29];
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
uint32_t RESERVED4[43];
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6];
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */

6
bsp/efm32/Libraries/CMSIS/Include/core_cm4.h
View File

@ -669,14 +669,14 @@ typedef struct
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
uint32_t RESERVED3[29];
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
uint32_t RESERVED4[43];
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6];
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */

6
bsp/efm32/Libraries/CMSIS/Include/core_sc300.h
View File

@ -607,14 +607,14 @@ typedef struct
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
uint32_t RESERVED3[29];
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
uint32_t RESERVED4[43];
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6];
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */

110
bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h
View File

@ -1,20 +1,20 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
/* ----------------------------------------------------------------------
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
* $Date: 5. March 2012
* $Revision: V0.03
*
*
* Project: CMSIS-RTOS API
* Title: cmsis_os.h template header file
*
*
* Version 0.02
* Initial Proposal Phase
* Initial Proposal Phase
* Version 0.03
* osKernelStart added, optional feature: main started as thread
* osSemaphores have standard behaviour
* osTimerCreate does not start the timer, added osTimerStart
* osThreadPass is renamed to osThreadYield
* -------------------------------------------------------------------- */
* osThreadPass is renamed to osThreadYield
* -------------------------------------------------------------------- */
/**
\page cmsis_os_h Header File Template: cmsis_os.h
@ -35,8 +35,8 @@ The file cmsis_os.h contains:
All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
These definitions can be specific to the underlying RTOS kernel.
Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
@ -52,7 +52,7 @@ The following CMSIS-RTOS functions can be called from threads and interrupt serv
- \ref osMessagePut, \ref osMessageGet
- \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
@ -73,11 +73,11 @@ extern void thread_sample (void const *argument); // function protot
osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
// Pool definition
osPoolDef(MyPool, 10, long);
osPoolDef(MyPool, 10, long);
\endcode
This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
used throughout the whole project.
@ -92,7 +92,7 @@ used throughout the whole project.
\endcode
*/
#ifndef _CMSIS_OS_H
#define _CMSIS_OS_H
@ -100,7 +100,7 @@ used throughout the whole project.
#define osCMSIS 0x00003 ///< API version (main [31:16] .sub [15:0])
/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number.
#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string
@ -113,7 +113,7 @@ used throughout the whole project.
#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread
#define osFeature_Semaphore 30 ///< maximum count for SemaphoreInit function
#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available
#include <stdint.h>
#include <stddef.h>
@ -133,7 +133,7 @@ typedef enum {
osPriorityBelowNormal = -1, ///< priority: below normal
osPriorityNormal = 0, ///< priority: normal (default)
osPriorityAboveNormal = +1, ///< priority: above normal
osPriorityHigh = +2, ///< priority: high
osPriorityHigh = +2, ///< priority: high
osPriorityRealtime = +3, ///< priority: realtime (highest)
osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority
} osPriority;
@ -160,23 +160,23 @@ typedef enum {
osErrorValue = 0x86, ///< value of a parameter is out of range.
osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits.
os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
} osStatus;
} osStatus;
/// Timer type value for the timer definition
/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
typedef enum {
osTimerOnce = 0, ///< one-shot timer
osTimerPeriodic = 1 ///< repeating timer
} os_timer_type;
osTimerOnce = 0, ///< one-shot timer
osTimerPeriodic = 1 ///< repeating timer
} os_timer_type;
/// Entry point of a thread.
/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
typedef void (*os_pthread) (void const *argument);
typedef void (*os_pthread) (void const *argument);
/// Entry point of a timer call back function.
/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
typedef void (*os_ptimer) (void const *argument);
typedef void (*os_ptimer) (void const *argument);
// >>> the following data type definitions may shall adapted towards a specific RTOS
@ -240,7 +240,7 @@ typedef const struct os_semaphore_def {
/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
typedef const struct os_pool_def {
uint32_t pool_sz; ///< number of items (elements) in the pool
uint32_t item_sz; ///< size of an item
uint32_t item_sz; ///< size of an item
void *pool; ///< pointer to memory for pool
} osPoolDef_t;
@ -248,7 +248,7 @@ typedef const struct os_pool_def {
/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
typedef const struct os_messageQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
uint32_t item_sz; ///< size of an item
void *pool; ///< memory array for messages
} osMessageQDef_t;
@ -256,23 +256,23 @@ typedef const struct os_messageQ_def {
/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
typedef const struct os_mailQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
uint32_t item_sz; ///< size of an item
void *pool; ///< memory array for mail
} osMailQDef_t;
/// Event structure contains detailed information about an event.
/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
/// Event structure contains detailed information about an event.
/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
/// However the struct may be extended at the end.
typedef struct {
osStatus status; ///< status code: event or error information
union {
uint32_t v; ///< message as 32-bit value
uint32_t v; ///< message as 32-bit value
void *p; ///< message or mail as void pointer
int32_t signals; ///< signal flags
int32_t signals; ///< signal flags
} value; ///< event value
union {
osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
} def; ///< event definition
} osEvent;
@ -283,11 +283,11 @@ typedef struct {
/// \param[in] thread_def thread definition referenced with \ref osThread.
/// \param[in] argument pointer that is passed to the thread function as start argument.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
osStatus osKernelStart (osThreadDef_t *thread_def, void *argument);
/// Check if the RTOS kernel is already started.
/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
/// \return 0 RTOS is not started, 1 RTOS is started.
int32_t osKernelRunning(void);
@ -299,7 +299,7 @@ int32_t osKernelRunning(void);
/// \param priority initial priority of the thread function.
/// \param instances number of possible thread instances.
/// \param stacksz stack size (in bytes) requirements for the thread function.
/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osThreadDef(name, priority, instances, stacksz) \
@ -312,7 +312,7 @@ osThreadDef_t os_thread_def_##name = \
/// Access a Thread defintion.
/// \param name name of the thread definition object.
/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osThread(name) \
&os_thread_def_##name
@ -341,7 +341,7 @@ osStatus osThreadTerminate (osThreadId thread_id);
/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
osStatus osThreadYield (void);
/// Change priority of an active thread.
/// Change priority of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] priority new priority value for the thread function.
/// \return status code that indicates the execution status of the function.
@ -359,7 +359,7 @@ osPriority osThreadGetPriority (osThreadId thread_id);
// ==== Generic Wait Functions ====
/// Wait for Timeout (Time Delay)
/// \param[in] millisec time delay value
/// \param[in] millisec time delay value
/// \return status code that indicates the execution status of the function.
osStatus osDelay (uint32_t millisec);
@ -378,7 +378,7 @@ osEvent osWait (uint32_t millisec);
/// Define a Timer object.
/// \param name name of the timer object.
/// \param function name of the timer call back function.
/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osTimerDef(name, function) \
@ -391,7 +391,7 @@ osTimerDef_t os_timer_def_##name = \
/// Access a Timer definition.
/// \param name name of the timer object.
/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osTimer(name) \
&os_timer_def_##name
@ -452,7 +452,7 @@ osEvent osSignalWait (int32_t signals, uint32_t millisec);
/// Define a Mutex.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMutexDef(name) \
@ -464,7 +464,7 @@ osMutexDef_t os_mutex_def_##name = { 0 }
/// Access a Mutex defintion.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMutex(name) \
&os_mutex_def_##name
@ -495,7 +495,7 @@ osStatus osMutexRelease (osMutexId mutex_id);
/// Define a Semaphore object.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osSemaphoreDef(name) \
@ -507,7 +507,7 @@ osSemaphoreDef_t os_semaphore_def_##name = { 0 }
/// Access a Semaphore definition.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osSemaphore(name) \
&os_semaphore_def_##name
@ -533,7 +533,7 @@ int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
#endif // Semaphore available
// ==== Memory Pool Management Functions ====
#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available
@ -542,7 +542,7 @@ osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
/// \param name name of the memory pool.
/// \param no maximum number of objects (elements) in the memory pool.
/// \param type data type of a single object (element).
/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osPoolDef(name, no, type) \
@ -555,7 +555,7 @@ osPoolDef_t os_pool_def_##name = \
/// \brief Access a Memory Pool definition.
/// \param name name of the memory pool
/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osPool(name) \
&os_pool_def_##name
@ -572,7 +572,7 @@ osPoolId osPoolCreate (osPoolDef_t *pool_def);
/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
void *osPoolAlloc (osPoolId pool_id);
/// Allocate a memory block from a memory pool and set memory block to zero
/// Allocate a memory block from a memory pool and set memory block to zero
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
@ -596,7 +596,7 @@ osStatus osPoolFree (osPoolId pool_id, void *block);
/// \param name name of the queue.
/// \param queue_sz maximum number of messages in the queue.
/// \param type data type of a single message element (for debugger).
/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMessageQDef(name, queue_sz, type) \
@ -609,7 +609,7 @@ osMessageQDef_t os_messageQ_def_##name = \
/// \brief Access a Message Queue Definition.
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMessageQ(name) \
&os_messageQ_def_##name
@ -647,7 +647,7 @@ osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
/// \param name name of the queue
/// \param queue_sz maximum number of messages in queue
/// \param type data type of a single message element
/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMailQDef(name, queue_sz, type) \
@ -657,10 +657,10 @@ extern osMailQDef_t os_mailQ_def_##name
osMailQDef_t os_mailQ_def_##name = \
{ (queue_sz), sizeof (type) }
#endif
/// \brief Access a Mail Queue Definition
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMailQ(name) \
&os_mailQ_def_##name
@ -706,7 +706,7 @@ osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
osStatus osMailFree (osMailQId queue_id, void *mail);
#endif // Mail Queues available

2
bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c
View File

@ -39,7 +39,7 @@ extern void __iar_program_start(void);
extern void SystemInit(void);
/* Auto defined by linker */
extern unsigned char CSTACK$$Limit;
extern unsigned char CSTACK$$Limit;
__weak void Reset_Handler(void)
{

18
bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c
View File

@ -64,18 +64,18 @@
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
#ifndef EFM32_LFXO_FREQ
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
@ -118,13 +118,13 @@ uint32_t SystemCoreClock;
uint32_t SystemCoreClockGet(void)
{
uint32_t ret;
ret = SystemHFClockGet();
#if defined (_EFM32_GIANT_FAMILY)
/* Leopard/Giant Gecko has an additional divider */
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
#endif
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
/* Keep CMSIS variable up-to-date just in case */
@ -147,7 +147,7 @@ uint32_t SystemCoreClockGet(void)
uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
{
@ -160,11 +160,11 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
case CMU_STATUS_LFRCOSEL:
ret = EFM32_LFRCO_FREQ;
break;
case CMU_STATUS_HFXOSEL:
#if (EFM32_HFXO_FREQ > 0)
ret = SystemHFXOClock;
@ -174,7 +174,7 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
default: /* CMU_STATUS_HFRCOSEL */
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
{

2
bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c
View File

@ -39,7 +39,7 @@ extern void __iar_program_start(void);
extern void SystemInit(void);
/* Auto defined by linker */
extern unsigned char CSTACK$$Limit;
extern unsigned char CSTACK$$Limit;
__weak void Reset_Handler(void)
{

18
bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c
View File

@ -64,18 +64,18 @@
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
#ifndef EFM32_LFXO_FREQ
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
@ -118,13 +118,13 @@ uint32_t SystemCoreClock;
uint32_t SystemCoreClockGet(void)
{
uint32_t ret;
ret = SystemHFClockGet();
#if defined (_EFM32_GIANT_FAMILY)
/* Leopard/Giant Gecko has an additional divider */
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
#endif
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
/* Keep CMSIS variable up-to-date just in case */
@ -147,7 +147,7 @@ uint32_t SystemCoreClockGet(void)
uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
{
@ -160,11 +160,11 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
case CMU_STATUS_LFRCOSEL:
ret = EFM32_LFRCO_FREQ;
break;
case CMU_STATUS_HFXOSEL:
#if (EFM32_HFXO_FREQ > 0)
ret = SystemHFXOClock;
@ -174,7 +174,7 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
default: /* CMU_STATUS_HFRCOSEL */
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
{

4
bsp/efm32/Libraries/emlib/inc/em_acmp.h
View File

@ -173,7 +173,7 @@ typedef struct
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;
@ -229,7 +229,7 @@ typedef struct
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;

4
bsp/efm32/Libraries/emlib/inc/em_burtc.h
View File

@ -289,8 +289,8 @@ __STATIC_INLINE void BURTC_Enable(bool enable)
if( enable )
{
BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
}
else
}
else
{
BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
}

4
bsp/efm32/Libraries/emlib/inc/em_cmu.h
View File

@ -432,7 +432,7 @@ typedef enum
#endif
#if defined(USB_PRESENT)
cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
(_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) |
@ -441,7 +441,7 @@ typedef enum
#endif
#if defined(USB_PRESENT)
cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
(_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) |

8
bsp/efm32/Libraries/emlib/inc/em_dma.h
View File

@ -251,7 +251,7 @@ typedef struct
/** Enable repeated loop */
bool enable;
/** Width of transfer, reload value for nMinus1 */
uint16_t nMinus1;
uint16_t nMinus1;
} DMA_CfgLoop_TypeDef;
@ -335,20 +335,20 @@ typedef struct
* Pointer to the controlblock in memory holding descriptors (channel
* control data structures). This memory must be properly aligned
* according to requirements.
*
*
* Alignment requirements are
* a) 5 bits base requirement, bits [4:0]
* b) Add the number of bits needed to represent the wanted number
* of channels
* c) Align structure with this number of bits set to zero
*
*
* Examples: 4 channels, 5 + 2 (channels 0 to 3) = 7 bits
* 7 bit alignment, 64 byte address alignment
* 8 channels, 5 + 3 (channels 0 to 7) = 8 bits
* 8 bit alignment, 256 byte address alignment
* 12 channels, 5 + 4 (channels 0 to 11) = 9 bits
* 9 bit alignment, 512 byte address alignment
*
*
* Please refer to the reference manual, DMA chapter for more details.
*
* It is possible to provide a smaller memory block, only covering

10
bsp/efm32/Libraries/emlib/inc/em_ebi.h
View File

@ -157,7 +157,7 @@ typedef enum
} EBI_ALow_TypeDef;
/** Adress Pin Enable, high limit - higher limit of pins to enable */
typedef enum
typedef enum
{
/** All EBI_A pins are disabled */
ebiAHighA0 = EBI_ROUTE_APEN_A0,
@ -218,9 +218,9 @@ typedef enum {
/** EBI PIN I/O Location 1 */
ebiLocation1 = EBI_ROUTE_LOCATION_LOC1,
/** EBI PIN I/O Location 2 */
ebiLocation2 = EBI_ROUTE_LOCATION_LOC2,
ebiLocation2 = EBI_ROUTE_LOCATION_LOC2,
/** EBI PIN I/O Location 3 */
// ebiLocation3 = EBI_ROUTE_LOCATION_LOC3,
// ebiLocation3 = EBI_ROUTE_LOCATION_LOC3,
} EBI_Location_TypeDef;
#endif
@ -626,7 +626,7 @@ __STATIC_INLINE void EBI_TFTPixelSet(int pixel, uint32_t color)
******************************************************************************/
__STATIC_INLINE void EBI_TFTMaskBlendMode(EBI_TFTMaskBlend_TypeDef maskBlend)
{
EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend;
EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend;
}
@ -676,7 +676,7 @@ __STATIC_INLINE uint32_t EBI_TFTHCount(void)
/***************************************************************************//**
* @brief Set Frame Buffer Trigger
* @brief Set Frame Buffer Trigger
* Frame buffer pointer will be updated either on each horizontal line (hsync)
* or vertical update (vsync)(
******************************************************************************/

14
bsp/efm32/Libraries/emlib/inc/em_emu.h
View File

@ -62,8 +62,8 @@ typedef enum
/** Select ULFRCO as duty oscillator in EM4 */
emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
/** Select LFXO as duty oscillator in EM4 */
emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
/** Select LFRCO as duty oscillator in EM4 */
emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
/** Select LFRCO as duty oscillator in EM4 */
emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
} EMU_EM4Osc_TypeDef;
@ -124,15 +124,15 @@ typedef enum
#if defined(_EFM32_GIANT_FAMILY)
/** Energy Mode 4 initialization structure */
typedef struct
typedef struct
{
/** Lock configuration of regulator, BOD and oscillator */
bool lockConfig;
/** EM4 duty oscillator */
EMU_EM4Osc_TypeDef osc;
EMU_EM4Osc_TypeDef osc;
/** Wake up on EM4 BURTC interrupt */
bool buRtcWakeup;
/** Enable EM4 voltage regulator */
/** Enable EM4 voltage regulator */
bool vreg;
} EMU_EM4Init_TypeDef;
@ -145,7 +145,7 @@ typedef struct
}
/** Backup Power Domain Initialization structure */
typedef struct
typedef struct
{
/* Backup Power Domain power configuration */
@ -153,7 +153,7 @@ typedef struct
EMU_Probe_TypeDef probe;
/** Enable BOD calibration mode */
bool bodCal;
/** Enable BU_STAT status pin for active BU mode */
/** Enable BU_STAT status pin for active BU mode */
bool statusPinEnable;
/* Backup Power Domain connection configuration */

2
bsp/efm32/Libraries/emlib/inc/em_msc.h
View File

@ -88,7 +88,7 @@ typedef enum
#if defined (_EFM32_GIANT_FAMILY)
/** Strategy for prioritized bus access */
typedef enum {
typedef enum {
mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */
mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */
mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */

4
bsp/efm32/Libraries/emlib/inc/em_rmu.h
View File

@ -59,10 +59,10 @@ typedef enum
{
#if defined(_EFM32_GIANT_FAMILY)
/** Reset control over Backup Power Domain */
rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT,
rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT,
#endif
/** Allow Cortex-M3 lock up signal */
rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT
rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT
} RMU_Reset_TypeDef;
/*******************************************************************************

2
bsp/efm32/Libraries/emlib/inc/em_usart.h
View File

@ -276,7 +276,7 @@ typedef struct
#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
/** USART PRS trigger enable */
typedef struct
typedef struct
{
#if defined(_EFM32_GIANT_FAMILY)
/** Enable AUTOTX */

6
bsp/efm32/Libraries/emlib/src/em_burtc.c
View File

@ -87,7 +87,7 @@ __STATIC_INLINE uint32_t BURTC_DivToLog2(uint32_t div)
* Configures the BURTC peripheral.
*
* @note
* Before initialization, BURTC module must first be enabled by clearing the
* Before initialization, BURTC module must first be enabled by clearing the
* reset bit in the RMU, i.e.
* @verbatim
* RMU_ResetControl(rmuResetBU, false);
@ -123,7 +123,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
presc = BURTC_DivToLog2(burtcInit->clkDiv);
/* Make sure all registers are updated simultaneously */
if (burtcInit->enable)
if (burtcInit->enable)
{
BURTC_FreezeEnable(true);
}
@ -132,7 +132,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
BURTC->LPMODE = (uint32_t)(burtcInit->lowPowerMode);
/* New configuration */
ctrl = ((BURTC_CTRL_RSTEN) |
ctrl = ((BURTC_CTRL_RSTEN) |
(burtcInit->mode) |
(burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) |
(burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) |

8
bsp/efm32/Libraries/emlib/src/em_cmu.c
View File

@ -1377,14 +1377,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
/* frequencies above 32MHz */
if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE)
{
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ |
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ |
/* Must have HFLE enabled to access some LE peripherals >=32MHz */
CMU_CTRL_HFLE;
} else {
/* This can happen if the user configures the EFM32_HFXO_FREQ to */
/* use another oscillator frequency */
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
}
#endif
@ -1475,7 +1475,7 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);
/* Enable DIV4 factor for peripheral clock */
BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
}
#endif

16
bsp/efm32/Libraries/emlib/src/em_ebi.c
View File

@ -105,7 +105,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
ctrl |= EBI_CTRL_BANK0EN;
}
@ -117,13 +117,13 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
_EBI_CTRL_ARDY1EN_MASK|
_EBI_CTRL_ARDYTO1DIS_MASK|
_EBI_CTRL_NOIDLE1_MASK|
_EBI_CTRL_BANK1EN_MASK);
_EBI_CTRL_BANK1EN_MASK);
ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
ctrl |= EBI_CTRL_BANK1EN;
}
@ -141,7 +141,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
ctrl |= EBI_CTRL_BANK2EN;
}
@ -153,13 +153,13 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
_EBI_CTRL_ARDY3EN_MASK|
_EBI_CTRL_ARDYTO3DIS_MASK|
_EBI_CTRL_NOIDLE3_MASK|
_EBI_CTRL_BANK3EN_MASK);
_EBI_CTRL_BANK3EN_MASK);
ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
ctrl |= EBI_CTRL_BANK3EN;
}
@ -172,7 +172,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
_EBI_CTRL_BANK1EN_MASK|
_EBI_CTRL_BANK2EN_MASK|
_EBI_CTRL_BANK3EN_MASK);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
if ( ebiInit->banks & EBI_BANK0 )
{
@ -265,7 +265,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
EBI_ChipSelectEnable(ebiInit->csLines, true);
/* Activate new configuration */
EBI->CTRL = ctrl;
EBI->CTRL = ctrl;
}

26
bsp/efm32/Libraries/emlib/src/em_emu.c
View File

@ -402,16 +402,16 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4init)
_EMU_EM4CONF_OSC_MASK|
_EMU_EM4CONF_BURTCWU_MASK|
_EMU_EM4CONF_VREGEN_MASK);
/* Configure new settings */
em4conf |= (
(em4init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)|
(em4init->osc)|
(em4init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)|
(em4init->vreg << _EMU_EM4CONF_VREGEN_SHIFT));
/* Apply configuration. Note that lock can be set after this stage. */
EMU->EM4CONF = em4conf;
EMU->EM4CONF = em4conf;
}
@ -432,15 +432,15 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
_EMU_PWRCONF_VOUTSTRONG_MASK|
_EMU_PWRCONF_VOUTMED_MASK|
_EMU_PWRCONF_VOUTWEAK_MASK);
reg |= (bupdInit->resistor|
(bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)|
(bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT)|
(bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT));
(bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT));
EMU->PWRCONF = reg;
/* Set backup domain inactive mode configuration */
/* Set backup domain inactive mode configuration */
reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK);
reg |= (bupdInit->inactivePower);
EMU->BUINACT = reg;
@ -456,14 +456,14 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
_EMU_BUCTRL_BODCAL_MASK|
_EMU_BUCTRL_STATEN_MASK|
_EMU_BUCTRL_EN_MASK);
/* Note use of ->enable to both enable BUPD, use BU_VIN pin input and
/* Note use of ->enable to both enable BUPD, use BU_VIN pin input and
release reset */
reg |= (bupdInit->probe|
(bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT)|
(bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)|
(bupdInit->enable << _EMU_BUCTRL_EN_SHIFT));
/* Enable configuration */
EMU->BUCTRL = reg;
@ -479,14 +479,14 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
* @brief
* Configure Backup Power Domain BOD Threshold value
* @note
* These values are precalibrated
* These values are precalibrated
* @param[in] mode Active or Inactive mode
* @param[in] value
******************************************************************************/
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
{
EFM_ASSERT(value<4);
switch(mode)
{
case emuBODMode_Active:
@ -503,7 +503,7 @@ void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
* @brief
* Configure Backup Power Domain BOD Threshold Range
* @note
* These values are precalibrated
* These values are precalibrated
* @param[in] mode Active or Inactive mode
* @param[in] value
******************************************************************************/

2
bsp/efm32/Libraries/emlib/src/em_lesense.c
View File

@ -533,7 +533,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh,
/* Channel specific configuration of clocks, sample mode, excitation pin mode
* alternate excitation usage and interrupt mode on scan channel chIdx in
* LESENSE_CHchIdx_INTERACT. */
LESENSE->CH[chIdx].INTERACT = ((uint32_t)confCh->exClk <<
LESENSE->CH[chIdx].INTERACT = ((uint32_t)confCh->exClk <<
_LESENSE_CH_INTERACT_EXCLK_SHIFT) |
((uint32_t)confCh->sampleClk <<
_LESENSE_CH_INTERACT_SAMPLECLK_SHIFT) |

2
bsp/efm32/Libraries/emlib/src/em_msc.c
View File

@ -55,7 +55,7 @@
* @brief
* Enables the flash controller for writing.
* @note
* IMPORTANT: This function must be called before flash operations when
* IMPORTANT: This function must be called before flash operations when
* AUXHFRCO clock has been changed from default 14MHz band.
******************************************************************************/
void MSC_Init(void)

22
bsp/efm32/Libraries/emlib/src/em_opamp.c
View File

@ -243,7 +243,7 @@ void OPAMP_Disable( DAC_TypeDef *dac, OPAMP_TypeDef opa )
void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init )
{
uint32_t offset;
EFM_ASSERT( DAC_REF_VALID( dac ) );
EFM_ASSERT( DAC_OPA_VALID( opa ) );
EFM_ASSERT( init->bias <= ( _DAC_BIASPROG_BIASPROG_MASK >>
@ -267,13 +267,13 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef
}
else
{
EFM_ASSERT( init->offset <= ( _DAC_CAL_CH0OFFSET_MASK >>
EFM_ASSERT( init->offset <= ( _DAC_CAL_CH0OFFSET_MASK >>
_DAC_CAL_CH0OFFSET_SHIFT ) );
dac->CAL = ( dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK ) |
( init->offset << _DAC_CAL_CH0OFFSET_SHIFT );
( init->offset << _DAC_CAL_CH0OFFSET_SHIFT );
}
dac->OPA0MUX = (uint32_t)init->resSel |
(uint32_t)init->outMode |
init->outPen |
@ -315,11 +315,11 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef
}
else
{
EFM_ASSERT( init->offset <= ( _DAC_CAL_CH1OFFSET_MASK >>
EFM_ASSERT( init->offset <= ( _DAC_CAL_CH1OFFSET_MASK >>
_DAC_CAL_CH1OFFSET_SHIFT ) );
dac->CAL = ( dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK ) |
( init->offset << _DAC_CAL_CH1OFFSET_SHIFT );
( init->offset << _DAC_CAL_CH1OFFSET_SHIFT );
}
dac->OPA1MUX = (uint32_t)init->resSel |
@ -370,11 +370,11 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef
}
else
{
EFM_ASSERT( init->offset <= ( _DAC_OPAOFFSET_OPA2OFFSET_MASK >>
EFM_ASSERT( init->offset <= ( _DAC_OPAOFFSET_OPA2OFFSET_MASK >>
_DAC_OPAOFFSET_OPA2OFFSET_SHIFT ) );
dac->CAL = ( dac->CAL & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK ) |
( init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT );
( init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT );
}
dac->OPA2MUX = (uint32_t)init->resSel |

2
bsp/efm32/Libraries/emlib/src/em_rmu.c
View File

@ -1,7 +1,7 @@
/***************************************************************************//**
* @file
* @brief Reset Management Unit (RMU) peripheral module peripheral API
*
*
* @author Energy Micro AS
* @version 3.0.0
*******************************************************************************

2
bsp/efm32/Libraries/emlib/src/em_timer.c
View File

@ -136,7 +136,7 @@ void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init)
{
timer->CMD = TIMER_CMD_STOP;
}
/* Reset counter */
timer->CNT = _TIMER_CNT_RESETVALUE;

6
bsp/efm32/Libraries/emlib/src/em_usart.c
View File

@ -82,7 +82,7 @@
#endif
#if (UART_COUNT == 1)
#define UART_REF_VALID(ref) ((ref)==UART0)
#define UART_REF_VALID(ref) ((ref)==UART0)
#elif (UART_COUNT == 2)
#define UART_REF_VALID(ref) (((ref)==UART0) || ((ref)==UART1))
#else
@ -733,8 +733,8 @@ void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init)
* @brief
* Initialize automatic transmissions using PRS channel as trigger
* @note
* Initialize USART with USART_Init() before setting up PRS configuration
*
* Initialize USART with USART_Init() before setting up PRS configuration
*
* @param[in] usart Pointer to USART to configure
* @param[in] init Pointer to initialization structure
******************************************************************************/

2
bsp/efm32/Libraries/emlib/src/em_vcmp.c
View File

@ -133,7 +133,7 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit)
while(!VCMP_Ready());
VCMP_LowPowerRefSet(vcmpInit->lowPowerRef);
}
/* Clear edge interrupt */
VCMP_IntClear(VCMP_IF_EDGE);
}

146
bsp/efm32/board.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file board.c
* @brief Board support of RT-Thread RTOS for EFM32
* @file board.c
* @brief Board support of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,12 +10,12 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add SWO output enable function
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add SWO output enable function
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* 2011-12-09 onelife Add LEUART module support
* 2011-12-14 onelife Add LFXO enabling routine in driver initialization
* function
@ -37,19 +37,19 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \
((VECTTAB) == FLASH_MEM_BASE))
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \
((VECTTAB) == FLASH_MEM_BASE))
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/***************************************************************************//**
* @addtogroup SysTick_clock_source
* @{
******************************************************************************/
#define SysTick_CLKSource_MASK ((rt_uint32_t)0x00000004)
#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000)
#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \
((SOURCE) == SysTick_CLKSource_HFCORECLK))
#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000)
#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \
((SOURCE) == SysTick_CLKSource_HFCORECLK))
/***************************************************************************//**
* @}
******************************************************************************/
@ -67,20 +67,20 @@
* @note
*
* @param[in] NVIC_VectTab
* Indicate the vector table is allocated in RAM or ROM
* Indicate the vector table is allocated in RAM or ROM
*
* @param[in] Offset
* The vector table offset
******************************************************************************/
static void NVIC_SetVectorTable(
rt_uint32_t NVIC_VectTab,
rt_uint32_t Offset)
rt_uint32_t NVIC_VectTab,
rt_uint32_t Offset)
{
/* Check the parameters */
RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
RT_ASSERT(IS_NVIC_OFFSET(Offset));
/* Check the parameters */
RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
RT_ASSERT(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
}
/***************************************************************************//**
@ -95,19 +95,19 @@ static void NVIC_SetVectorTable(
static void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
/* Set the vector table allocated at 0x20000000 */
NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
/* Set the vector table allocated at 0x20000000 */
NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
#else /* VECT_TAB_FLASH */
/* Set the vector table allocated at 0x00000000 */
NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
/* Set the vector table allocated at 0x00000000 */
NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
#endif
/* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
subpriority */
NVIC_SetPriorityGrouping(0x7UL);
/* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
subpriority */
NVIC_SetPriorityGrouping(0x7UL);
/* Set Base Priority Mask Register */
__set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
/* Set Base Priority Mask Register */
__set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
}
/***************************************************************************//**
@ -119,13 +119,13 @@ static void NVIC_Configuration(void)
* @note
*
* @param[in] SysTick_CLKSource
* Specifies the SysTick clock source.
* Specifies the SysTick clock source.
*
* @arg SysTick_CLKSource_HCLK_Div8
* AHB clock divided by 8 selected as SysTick clock source.
* AHB clock divided by 8 selected as SysTick clock source.
*
* @arg SysTick_CLKSource_HCLK
* AHB clock selected as SysTick clock source.
* AHB clock selected as SysTick clock source.
******************************************************************************/
static void SysTick_CLKSourceConfig(rt_uint32_t SysTick_CLKSource)
{
@ -184,14 +184,14 @@ static void SysTick_Configuration(void)
/* Start LETIMER0 */
LETIMER_Init(LETIMER0, &letimerInit);
#else
rt_uint32_t coreClk;
rt_uint32_t cnts;
rt_uint32_t coreClk;
rt_uint32_t cnts;
coreClk = SystemCoreClockGet();
cnts = coreClk / RT_TICK_PER_SECOND;
coreClk = SystemCoreClockGet();
cnts = coreClk / RT_TICK_PER_SECOND;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
#endif
}
@ -206,9 +206,9 @@ static void SysTick_Configuration(void)
******************************************************************************/
void Swo_Configuration(void)
{
rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
/* Enable Serial wire output pin */
@ -258,12 +258,12 @@ void Swo_Configuration(void)
******************************************************************************/
void rt_hw_board_init(void)
{
/* Chip errata */
CHIP_Init();
/* Chip errata */
CHIP_Init();
/* Initialize DVK board register access */
#if defined(EFM32_GXXX_DK)
DVK_init();
DVK_init();
#elif defined(EFM32GG_DK3750)
DVK_init(DVK_Init_EBI);
@ -272,12 +272,12 @@ void rt_hw_board_init(void)
DVK_clearInterruptFlags(BC_INTFLAG_MASK);
#endif
/* config NVIC Configuration */
NVIC_Configuration();
/* config NVIC Configuration */
NVIC_Configuration();
#if defined(EFM32_USING_HFXO)
/* Configure external oscillator */
SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
/* Configure external oscillator */
SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
/* Switching the CPU clock source to HFXO */
CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
@ -293,15 +293,15 @@ void rt_hw_board_init(void)
#if defined(EFM32_SWO_ENABLE)
/* Enable SWO */
Swo_Configuration();
Swo_Configuration();
#endif
/* Enable high frequency peripheral clock */
CMU_ClockEnable(cmuClock_HFPER, true);
/* Enabling clock to the interface of the low energy modules */
CMU_ClockEnable(cmuClock_CORELE, true);
/* Enable high frequency peripheral clock */
CMU_ClockEnable(cmuClock_HFPER, true);
/* Enabling clock to the interface of the low energy modules */
CMU_ClockEnable(cmuClock_CORELE, true);
/* Enable GPIO clock */
CMU_ClockEnable(cmuClock_GPIO, true);
CMU_ClockEnable(cmuClock_GPIO, true);
/* Configure the SysTick */
SysTick_Configuration();
@ -318,8 +318,8 @@ void rt_hw_board_init(void)
******************************************************************************/
void rt_hw_driver_init(void)
{
/* Initialize DMA */
rt_hw_dma_init();
/* Initialize DMA */
rt_hw_dma_init();
/* Select LFXO for specified module (and wait for it to stabilize) */
#if (!defined(EFM32_USING_LFXO) && defined(RT_USING_RTC))
@ -331,11 +331,11 @@ void rt_hw_driver_init(void)
#error "Low frequency clock source is needed for using LEUART"
#endif
/* Initialize USART */
/* Initialize USART */
#if (defined(RT_USING_USART0) || defined(RT_USING_USART1) || \
defined(RT_USING_USART2) || defined(RT_USING_UART0) || \
defined(RT_USING_UART1))
rt_hw_usart_init();
rt_hw_usart_init();
#endif
/* Initialize LEUART */
@ -343,7 +343,7 @@ void rt_hw_driver_init(void)
rt_hw_leuart_init();
#endif
/* Setup Console */
/* Setup Console */
#if defined(EFM32_GXXX_DK)
DVK_enablePeripheral(DVK_RS232A);
DVK_enablePeripheral(DVK_SPI);
@ -354,31 +354,31 @@ void rt_hw_driver_init(void)
DVK_enablePeripheral(DVK_RS232_LEUART);
#endif
#endif
rt_console_set_device(CONSOLE_DEVICE);
rt_console_set_device(CONSOLE_DEVICE);
/* Initialize Timer */
/* Initialize Timer */
#if (defined(RT_USING_TIMER0) || defined(RT_USING_TIMER1) || defined(RT_USING_TIMER2))
rt_hw_timer_init();
rt_hw_timer_init();
#endif
/* Initialize ADC */
/* Initialize ADC */
#if defined(RT_USING_ADC0)
rt_hw_adc_init();
rt_hw_adc_init();
#endif
/* Initialize ACMP */
/* Initialize ACMP */
#if (defined(RT_USING_ACMP0) || defined(RT_USING_ACMP1))
rt_hw_acmp_init();
rt_hw_acmp_init();
#endif
/* Initialize IIC */
/* Initialize IIC */
#if (defined(RT_USING_IIC0) || defined(RT_USING_IIC1))
rt_hw_iic_init();
rt_hw_iic_init();
#endif
/* Initialize RTC */
/* Initialize RTC */
#if defined(RT_USING_RTC)
rt_hw_rtc_init();
rt_hw_rtc_init();
#endif
/* Enable SPI access to MicroSD card */

126
bsp/efm32/board.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file board.h
* @brief Board support of RT-Thread RTOS for EFM32
* @file board.h
* @brief Board support of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,18 +10,18 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add prototype for SWO output enable and interrupt
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add prototype for SWO output enable and interrupt
* context check functions
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* 2011-12-09 onelife Add LEUART module support
* 2011-12-14 onelife Add LFXO enabling routine in driver initialization
* function
* 2011-12-20 onelife Move SPI Auto-CS setting to "rtconfig.h"
* 2012-05-15 onelife Modified to compatible with CMSIS v3
* 2012-05-15 onelife Modified to compatible with CMSIS v3
******************************************************************************/
#ifndef __BOARD_H__
#define __BOARD_H__
@ -72,15 +72,15 @@ extern volatile rt_uint32_t rt_system_status;
#define EFM32_SWO_ENABLE
#endif
#define EFM32_NO_DATA (0)
#define EFM32_NO_POINTER (RT_NULL)
#define EFM32_NO_OFFSET (-1)
#define EFM32_NO_DMA (-1)
#define EFM32_NO_DATA (0)
#define EFM32_NO_POINTER (RT_NULL)
#define EFM32_NO_OFFSET (-1)
#define EFM32_NO_DMA (-1)
/* SECTION: SPI Flash */
#if defined(EFM32_USING_SFLASH)
#define SFLASH_CS_PORT (gpioPortC)
#define SFLASH_CS_PIN (8)
#define SFLASH_CS_PORT (gpioPortC)
#define SFLASH_CS_PIN (8)
#endif
/* SECTION: Micro SD */
@ -114,9 +114,9 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SECTION: SYSTEM */
#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE)
#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5)
#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5)
#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE)
#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5)
#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5)
/* SECTION: CLOCK */
#define EFM32_USING_HFXO
@ -125,9 +125,9 @@ extern volatile rt_uint32_t rt_system_status;
#if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK))
#define EFM32_HFXO_FREQUENCY (32000000)
#elif defined(EFM32GG_DK3750)
#define EFM32_HFXO_FREQUENCY (48000000)
#define EFM32_HFXO_FREQUENCY (48000000)
#else
#define EFM32_HFXO_FREQUENCY (00000000)
#define EFM32_HFXO_FREQUENCY (00000000)
#endif
#endif
#if defined(EFM32_USING_LFXO)
@ -141,8 +141,8 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SECTION: USART */
#define USART_RX_BUFFER_SIZE (64)
#define LEUART_RX_BUFFER_SIZE (64)
#define USART_RX_BUFFER_SIZE (64)
#define LEUART_RX_BUFFER_SIZE (64)
/* Location count (start from 0) */
#if defined(_EFM32_GECKO_FAMILY)
#define EFM32_USART_LOCATION_COUNT (3)
@ -155,14 +155,14 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SUBSECTION: UART */
#define UART_BAUDRATE (115200)
#define UART_BAUDRATE (115200)
/* SUBSECTION: SPI */
/* Max SPI clock: HFPERCLK/2 for master, HFPERCLK/8 for slave */
#define SPI_BAUDRATE (4000000)
#define SPI_BAUDRATE (4000000)
/* SECTION: I2C */
#define IIC_RX_BUFFER_SIZE (32)
#define IIC_RX_BUFFER_SIZE (32)
#if defined(_EFM32_GECKO_FAMILY)
#define EFM32_IIC_LOCATION_COUNT (4)
#elif defined(_EFM32_GIANT_FAMILY)
@ -170,61 +170,61 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SECTION: ADC */
#define ADC_CALI_REF (adcRef2V5)
#define ADC_CALI_CH (adcSingleInpCh5)
#define ADC_CONVERT_FREQUENCY (7000000)
#define ADC_CALI_REF (adcRef2V5)
#define ADC_CALI_CH (adcSingleInpCh5)
#define ADC_CONVERT_FREQUENCY (7000000)
#if (RT_CONSOLE_DEVICE == EFM_USART0)
#define CONSOLE_DEVICE RT_USART0_NAME
#define CONSOLE_DEVICE RT_USART0_NAME
#elif (RT_CONSOLE_DEVICE == EFM_USART1)
#define CONSOLE_DEVICE RT_USART1_NAME
#define CONSOLE_DEVICE RT_USART1_NAME
#elif (RT_CONSOLE_DEVICE == EFM_USART2)
#define CONSOLE_DEVICE RT_USART2_NAME
#define CONSOLE_DEVICE RT_USART2_NAME
#elif (RT_CONSOLE_DEVICE == EFM_UART0)
#define CONSOLE_DEVICE RT_UART0_NAME
#define CONSOLE_DEVICE RT_UART0_NAME
#elif (RT_CONSOLE_DEVICE == EFM_UART1)
#define CONSOLE_DEVICE RT_UART1_NAME
#define CONSOLE_DEVICE RT_UART1_NAME
#elif (RT_CONSOLE_DEVICE == EFM_LEUART0)
#define CONSOLE_DEVICE RT_LEUART0_NAME
#define CONSOLE_DEVICE RT_LEUART0_NAME
#elif (RT_CONSOLE_DEVICE == EFM_LEUART1)
#define CONSOLE_DEVICE RT_LEUART1_NAME
#define CONSOLE_DEVICE RT_LEUART1_NAME
#else
#define CONSOLE_DEVICE "NONE"
#define CONSOLE_DEVICE "NONE"
#endif
/* The following defines should be consistent with those in diskio.h */
#define CTRL_SYNC 0
#define GET_SECTOR_COUNT 1
#define GET_SECTOR_SIZE 2
#define GET_BLOCK_SIZE 3
#define MMC_GET_TYPE 10
#define MMC_GET_CSD 11
#define MMC_GET_CID 12
#define MMC_GET_OCR 13
#define MMC_GET_SDSTAT 14
#define CTRL_SYNC 0
#define GET_SECTOR_COUNT 1
#define GET_SECTOR_SIZE 2
#define GET_BLOCK_SIZE 3
#define MMC_GET_TYPE 10
#define MMC_GET_CSD 11
#define MMC_GET_CID 12
#define MMC_GET_OCR 13
#define MMC_GET_SDSTAT 14
/* The above defines should be consistent with those in diskio.h */
/* I/O control options */
#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC
#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT
#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE
#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE
#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE
#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD
#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID
#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR
#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT
#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC
#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT
#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE
#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE
#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE
#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD
#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID
#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR
#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT
/*! fixme: move the following define to Rtdef.h */
#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */
#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */
#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */
#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */
#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */
#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */
#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */
#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */
#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */
#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */
#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */
#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */
#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */
#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */
#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */
#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */
/* Exported functions ------------------------------------------------------- */
void rt_hw_board_init(void);

1256
bsp/efm32/dev_accel.c
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File diff suppressed because it is too large Load Diff

146
bsp/efm32/dev_accel.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_accel.h
* @brief Accelerometer driver of RT-Thread RTOS for EFM32
* @file dev_accel.h
* @brief Accelerometer driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,10 +10,10 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-07-13 onelife Initial creation for using EFM32 ADC module to
* Date Author Notes
* 2011-07-13 onelife Initial creation for using EFM32 ADC module to
* interface the Freescale MMA7361L
* 2011-08-02 onelife Add digital interface support of using EFM32 IIC
* 2011-08-02 onelife Add digital interface support of using EFM32 IIC
* module for the Freescale MMA7455L
******************************************************************************/
#ifndef __DEV_ACCEL_H__
@ -27,95 +27,95 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_accel_result_t
{
rt_int32_t x;
rt_int32_t y;
rt_int32_t z;
rt_int32_t x;
rt_int32_t y;
rt_int32_t z;
};
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* MMA7361LC
g-Select g-Range Sensitivity
0 1.5 g 800 mV/g
1 6 g 206 mV/g
/* MMA7361LC
g-Select g-Range Sensitivity
0 1.5 g 800 mV/g
1 6 g 206 mV/g
MMA7455L
g-Select g-Range Sensitivity
0 2 g 64 LSB/g
1 4 g 32 LSB/g
2 8 g 16 LSB/g
MMA7455L
g-Select g-Range Sensitivity
0 2 g 64 LSB/g
1 4 g 32 LSB/g
2 8 g 16 LSB/g
*/
#define ACCEL_G_SELECT (0)
#define ACCEL_G_SELECT (0)
#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */
#define ACCEL_CAL_ROUND (50)
#define ACCEL_CAL_SIMPLE (0)
#define ACCEL_CAL_INTERACT (1)
#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */
#define ACCEL_CAL_ROUND (50)
#define ACCEL_CAL_SIMPLE (0)
#define ACCEL_CAL_INTERACT (1)
#if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
/* Reading_at_1g = Sensitivity * Max_reading / Refference_voltage */
#define ACCEL_CAL_1G_VALUE {993, 256}
#define ACCEL_CAL_1G_VALUE {993, 256}
#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2
#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3
#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4
#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2
#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3
#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4
#elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f}
#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f}
#define ACCEL_IIC_SLAVE_ADDRESS (0x1d)
#define ACCEL_INT1_PORT (gpioPortD)
#define ACCEL_INT1_PIN (13)
#define ACCEL_INT2_PORT (gpioPortD)
#define ACCEL_INT2_PIN (12)
#define ACCEL_INT1_PORT (gpioPortD)
#define ACCEL_INT1_PIN (13)
#define ACCEL_INT2_PORT (gpioPortD)
#define ACCEL_INT2_PIN (12)
#define ACCEL_MODE_STANDBY (1 << 0)
#define ACCEL_MODE_MEASUREMENT (1 << 1)
#define ACCEL_MODE_LEVEL (1 << 2)
#define ACCEL_MODE_PULSE (1 << 3)
#define ACCEL_RANGE_8G (1 << 4)
#define ACCEL_RANGE_4G (1 << 5)
#define ACCEL_RANGE_2G (1 << 6)
#define ACCEL_INTPIN_INVERSE (1 << 7)
#define ACCEL_INT_LEVEL_PULSE (1 << 8)
#define ACCEL_INT_PULSE_LEVEL (1 << 9)
#define ACCEL_INT_SINGLE_DOUBLE (1 << 10)
#define ACCEL_DISABLE_X (1 << 11)
#define ACCEL_DISABLE_Y (1 << 12)
#define ACCEL_DISABLE_Z (1 << 13)
#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */
#define ACCEL_BANDWIDTH_125HZ (1 << 15)
#define ACCEL_LEVEL_AND (1 << 16)
#define ACCEL_PULSE_AND (1 << 17)
#define ACCEL_DRIVE_STRONG (1 << 18)
#define ACCEL_SOURCE_LEVEL_X (1 << 19)
#define ACCEL_SOURCE_LEVEL_Y (1 << 20)
#define ACCEL_SOURCE_LEVEL_Z (1 << 21)
#define ACCEL_SOURCE_PULSE_X (1 << 22)
#define ACCEL_SOURCE_PULSE_Y (1 << 23)
#define ACCEL_SOURCE_PULSE_Z (1 << 24)
#define ACCEL_MODE_STANDBY (1 << 0)
#define ACCEL_MODE_MEASUREMENT (1 << 1)
#define ACCEL_MODE_LEVEL (1 << 2)
#define ACCEL_MODE_PULSE (1 << 3)
#define ACCEL_RANGE_8G (1 << 4)
#define ACCEL_RANGE_4G (1 << 5)
#define ACCEL_RANGE_2G (1 << 6)
#define ACCEL_INTPIN_INVERSE (1 << 7)
#define ACCEL_INT_LEVEL_PULSE (1 << 8)
#define ACCEL_INT_PULSE_LEVEL (1 << 9)
#define ACCEL_INT_SINGLE_DOUBLE (1 << 10)
#define ACCEL_DISABLE_X (1 << 11)
#define ACCEL_DISABLE_Y (1 << 12)
#define ACCEL_DISABLE_Z (1 << 13)
#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */
#define ACCEL_BANDWIDTH_125HZ (1 << 15)
#define ACCEL_LEVEL_AND (1 << 16)
#define ACCEL_PULSE_AND (1 << 17)
#define ACCEL_DRIVE_STRONG (1 << 18)
#define ACCEL_SOURCE_LEVEL_X (1 << 19)
#define ACCEL_SOURCE_LEVEL_Y (1 << 20)
#define ACCEL_SOURCE_LEVEL_Z (1 << 21)
#define ACCEL_SOURCE_PULSE_X (1 << 22)
#define ACCEL_SOURCE_PULSE_Y (1 << 23)
#define ACCEL_SOURCE_PULSE_Z (1 << 24)
#define ACCEL_SHIFT_MODE (0)
#define ACCEL_SHIFT_RANGE (4)
#define ACCEL_SHIFT_INT (8)
#define ACCEL_SHIFT_DISABLE (11)
#define ACCEL_SHIFT_SOURCE (19)
#define ACCEL_SHIFT_MODE (0)
#define ACCEL_SHIFT_RANGE (4)
#define ACCEL_SHIFT_INT (8)
#define ACCEL_SHIFT_DISABLE (11)
#define ACCEL_SHIFT_SOURCE (19)
#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE)
#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE)
#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT)
#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE)
#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE)
#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE)
#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE)
#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT)
#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE)
#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE)
#endif
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data,
rt_bool_t lowResolution);
rt_bool_t lowResolution);
rt_err_t efm_accel_config(rt_uint32_t config,
rt_uint8_t level_threshold,
rt_uint8_t pulse_threshold,
rt_uint8_t pulse_duration,
rt_uint8_t pulse_latency,
rt_uint8_t pulse_duration2);
rt_uint8_t level_threshold,
rt_uint8_t pulse_threshold,
rt_uint8_t pulse_duration,
rt_uint8_t pulse_latency,
rt_uint8_t pulse_duration2);
rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period);
rt_err_t efm_accel_init(void);

40
bsp/efm32/dev_keys.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_keys.c
* @brief Keys driver of RT-Thread RTOS for EFM32
* @file dev_keys.c
* @brief Keys driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board
******************************************************************************/
@ -48,14 +48,14 @@ static rt_bool_t click;
/* Private functions ---------------------------------------------------------*/
/***************************************************************************//**
* @brief
* Keys interrupt handler
* Keys interrupt handler
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
******************************************************************************/
static void efm32_keys_isr(rt_device_t dev)
{
@ -158,18 +158,18 @@ static void efm32_keys_isr(rt_device_t dev)
/***************************************************************************//**
* @brief
* Keys timeout handler
* Keys timeout handler
*
* @details
*
* @note
*
* @param[in] param
* Parameter
* Parameter
******************************************************************************/
static void efm32_keys_timer_isr(void *param)
{
rt_uint16_t joystick;
rt_uint16_t joystick;
joystick = DVK_getJoystick();
@ -277,11 +277,11 @@ void efm32_hw_keys_init(void)
GPIO_IntConfig(KEYS_INT_PORT, KEYS_INT_PIN, true, true, true);
efm32_irq_hook_init_t hook;
hook.type = efm32_irq_type_gpio;
hook.unit = KEYS_INT_PIN;
hook.cbFunc = efm32_keys_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
hook.type = efm32_irq_type_gpio;
hook.unit = KEYS_INT_PIN;
hook.cbFunc = efm32_keys_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
if ((rt_uint8_t)KEYS_INT_PIN % 2)
{
@ -299,12 +299,12 @@ void efm32_hw_keys_init(void)
/* Enable DVK joystick interrupt */
DVK_enableInterrupt(BC_INTEN_JOYSTICK);
rt_timer_init(&joy.timer,
"joy_tmr",
efm32_keys_timer_isr,
RT_NULL,
KEYS_POLL_TIME,
RT_TIMER_FLAG_PERIODIC);
rt_timer_init(&joy.timer,
"joy_tmr",
efm32_keys_timer_isr,
RT_NULL,
KEYS_POLL_TIME,
RT_TIMER_FLAG_PERIODIC);
joy_dev.init = efm32_keys_init;
joy_dev.open = RT_NULL;

8
bsp/efm32/dev_keys.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_keys.h
* @brief Keys driver of RT-Thread RTOS for EFM32
* @file dev_keys.h
* @brief Keys driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board
******************************************************************************/
#ifndef __DEV_KEYS_H__

76
bsp/efm32/dev_lcd.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_lcd.c
* @brief LCD driver of RT-Thread RTOS for EFM32
* @file dev_lcd.c
* @brief LCD driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-16 onelife Initial creation of address mapped method (pixel
* drive) for EFM32GG_DK3750 board
* 2011-12-29 onelife Add direct drive method (frame buffer) support
@ -451,48 +451,48 @@ rt_err_t efm32_spiLcd_writeRegister(rt_uint8_t reg, rt_uint16_t data)
/***************************************************************************//**
* @brief
* Register LCD device
* Register LCD device
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] name
* Device name
* Device name
*
* @param[in] flag
* Configuration flags
* Configuration flags
*
* @param[in] iic
* Pointer to IIC device descriptor
* Pointer to IIC device descriptor
*
* @return
* Error code
* Error code
******************************************************************************/
rt_err_t efm32_spiLcd_register(
rt_device_t device,
const char *name,
rt_uint32_t flag,
void *data)
rt_device_t device,
const char *name,
rt_uint32_t flag,
void *data)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device != RT_NULL);
device->type = RT_Device_Class_Graphic;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = efm32_spiLcd_control;
device->user_data = data;
device->type = RT_Device_Class_Graphic;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = efm32_spiLcd_control;
device->user_data = data;
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
}
/***************************************************************************//**
@ -511,18 +511,18 @@ void efm32_spiLcd_init(void)
DMD_DisplayGeometry *geometry;
rt_uint32_t ret;
do
{
do
{
USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT;
/* Find SPI device */
lcd = rt_device_find(LCD_USING_DEVICE_NAME);
if (lcd == RT_NULL)
{
lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME);
break;
}
lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME);
/* Find SPI device */
lcd = rt_device_find(LCD_USING_DEVICE_NAME);
if (lcd == RT_NULL)
{
lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME);
break;
}
lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME);
/* Config CS pin */
usart = (struct efm32_usart_device_t *)(lcd->user_data);
@ -647,7 +647,7 @@ void efm32_spiLcd_init(void)
}
/* Init LCD info */
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX;
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX;
lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
lcd_info.bits_per_pixel = 16;
lcd_info.width = geometry->xSize;

8
bsp/efm32/dev_lcd.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_lcd.h
* @brief LCD driver of RT-Thread RTOS for EFM32
* @file dev_lcd.h
* @brief LCD driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-16 onelife Initial creation of address mapped method (pixel
* drive) for EFM32GG_DK3750 board
******************************************************************************/

138
bsp/efm32/dev_sflash.h
View File

@ -20,85 +20,85 @@
/* Exported types ------------------------------------------------------------*/
enum sflash_inst_type_t
{
/* Instruction only */
sflash_inst_wren = 0x00,
sflash_inst_wrdi,
sflash_inst_rdid_l,
sflash_inst_rdid_s,
sflash_inst_rdsr,
sflash_inst_wrsr,
sflash_inst_be,
sflash_inst_dp,
sflash_inst_rdp,
/* Instruction and address */
sflash_inst_wrlr,
sflash_inst_rdlr,
sflash_inst_read,
sflash_inst_potp,
sflash_inst_pp,
sflash_inst_difp,
sflash_inst_sse,
sflash_inst_se,
/* Instruction, address and dummy read */
sflash_inst_read_f,
sflash_inst_dofr,
sflash_inst_rotp
/* Instruction only */
sflash_inst_wren = 0x00,
sflash_inst_wrdi,
sflash_inst_rdid_l,
sflash_inst_rdid_s,
sflash_inst_rdsr,
sflash_inst_wrsr,
sflash_inst_be,
sflash_inst_dp,
sflash_inst_rdp,
/* Instruction and address */
sflash_inst_wrlr,
sflash_inst_rdlr,
sflash_inst_read,
sflash_inst_potp,
sflash_inst_pp,
sflash_inst_difp,
sflash_inst_sse,
sflash_inst_se,
/* Instruction, address and dummy read */
sflash_inst_read_f,
sflash_inst_dofr,
sflash_inst_rotp
};
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#define SFLASH_SPI_COMMAND_SKIP (1)
#define SFLASH_SPI_READ_SKIP (2)
#define SFLASH_SPI_COMMAND_SKIP (1)
#define SFLASH_SPI_READ_SKIP (2)
#define SFLASH_INST_CODE_WREN (0x06)
#define SFLASH_INST_CODE_WRDI (0x04)
#define SFLASH_INST_CODE_RDID_L (0x9F)
#define SFLASH_INST_CODE_RDID_S (0x9E)
#define SFLASH_INST_CODE_RDSR (0x05)
#define SFLASH_INST_CODE_WRSR (0x01)
#define SFLASH_INST_CODE_WRLR (0xE5)
#define SFLASH_INST_CODE_RDLR (0xE8)
#define SFLASH_INST_CODE_READ (0x03)
#define SFLASH_INST_CODE_READ_F (0x0B)
#define SFLASH_INST_CODE_DOFR (0x3B)
#define SFLASH_INST_CODE_ROTP (0x4B)
#define SFLASH_INST_CODE_POTP (0x42)
#define SFLASH_INST_CODE_PP (0x02)
#define SFLASH_INST_CODE_DIFP (0xA2)
#define SFLASH_INST_CODE_SSE (0x20)
#define SFLASH_INST_CODE_SE (0xD8)
#define SFLASH_INST_CODE_BE (0xC7)
#define SFLASH_INST_CODE_DP (0xB9)
#define SFLASH_INST_CODE_RDP (0xAB)
#define SFLASH_INST_CODE_WREN (0x06)
#define SFLASH_INST_CODE_WRDI (0x04)
#define SFLASH_INST_CODE_RDID_L (0x9F)
#define SFLASH_INST_CODE_RDID_S (0x9E)
#define SFLASH_INST_CODE_RDSR (0x05)
#define SFLASH_INST_CODE_WRSR (0x01)
#define SFLASH_INST_CODE_WRLR (0xE5)
#define SFLASH_INST_CODE_RDLR (0xE8)
#define SFLASH_INST_CODE_READ (0x03)
#define SFLASH_INST_CODE_READ_F (0x0B)
#define SFLASH_INST_CODE_DOFR (0x3B)
#define SFLASH_INST_CODE_ROTP (0x4B)
#define SFLASH_INST_CODE_POTP (0x42)
#define SFLASH_INST_CODE_PP (0x02)
#define SFLASH_INST_CODE_DIFP (0xA2)
#define SFLASH_INST_CODE_SSE (0x20)
#define SFLASH_INST_CODE_SE (0xD8)
#define SFLASH_INST_CODE_BE (0xC7)
#define SFLASH_INST_CODE_DP (0xB9)
#define SFLASH_INST_CODE_RDP (0xAB)
#define SFLASH_REPLY_LEN_WREN (0)
#define SFLASH_REPLY_LEN_WRDI (0)
#define SFLASH_REPLY_LEN_RDID_L (20)
#define SFLASH_REPLY_LEN_RDID_S (3)
#define SFLASH_REPLY_LEN_RDSR (1)
#define SFLASH_REPLY_LEN_WRSR (1)
#define SFLASH_REPLY_LEN_WRLR (1)
#define SFLASH_REPLY_LEN_RDLR (1)
#define SFLASH_REPLY_LEN_READ (-1)
#define SFLASH_REPLY_LEN_READ_F (-1)
#define SFLASH_REPLY_LEN_DOFR (-1)
#define SFLASH_REPLY_LEN_ROTP (65)
#define SFLASH_REPLY_LEN_POTP (65)
#define SFLASH_REPLY_LEN_PP (256)
#define SFLASH_REPLY_LEN_DIFP (256)
#define SFLASH_REPLY_LEN_SSE (0)
#define SFLASH_REPLY_LEN_SE (0)
#define SFLASH_REPLY_LEN_BE (0)
#define SFLASH_REPLY_LEN_DP (0)
#define SFLASH_REPLY_LEN_RDP (0)
#define SFLASH_REPLY_LEN_WREN (0)
#define SFLASH_REPLY_LEN_WRDI (0)
#define SFLASH_REPLY_LEN_RDID_L (20)
#define SFLASH_REPLY_LEN_RDID_S (3)
#define SFLASH_REPLY_LEN_RDSR (1)
#define SFLASH_REPLY_LEN_WRSR (1)
#define SFLASH_REPLY_LEN_WRLR (1)
#define SFLASH_REPLY_LEN_RDLR (1)
#define SFLASH_REPLY_LEN_READ (-1)
#define SFLASH_REPLY_LEN_READ_F (-1)
#define SFLASH_REPLY_LEN_DOFR (-1)
#define SFLASH_REPLY_LEN_ROTP (65)
#define SFLASH_REPLY_LEN_POTP (65)
#define SFLASH_REPLY_LEN_PP (256)
#define SFLASH_REPLY_LEN_DIFP (256)
#define SFLASH_REPLY_LEN_SSE (0)
#define SFLASH_REPLY_LEN_SE (0)
#define SFLASH_REPLY_LEN_BE (0)
#define SFLASH_REPLY_LEN_DP (0)
#define SFLASH_REPLY_LEN_RDP (0)
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_spiFlash_init(void);
rt_err_t efm_spiFlash_deinit(void);
rt_uint32_t efm_spiFlash_cmd(
enum sflash_inst_type_t command,
rt_uint32_t address,
rt_uint8_t *buffer,
rt_uint32_t size);
enum sflash_inst_type_t command,
rt_uint32_t address,
rt_uint8_t *buffer,
rt_uint32_t size);
#endif /* __DEV_SFLASH_H__ */

432
bsp/efm32/drv_acmp.c
View File

@ -30,18 +30,18 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
#ifdef RT_ACMP_DEBUG
#define acmp_debug(format,args...) rt_kprintf(format, ##args)
#define acmp_debug(format,args...) rt_kprintf(format, ##args)
#else
#define acmp_debug(format,args...)
#endif
/* Private variables ---------------------------------------------------------*/
#ifdef RT_USING_ACMP0
static struct rt_device acmp0_device;
static struct rt_device acmp0_device;
#endif
#ifdef RT_USING_ACMP1
static struct rt_device acmp1_device;
static struct rt_device acmp1_device;
#endif
/* Private function prototypes -----------------------------------------------*/
@ -64,169 +64,169 @@ ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq);
******************************************************************************/
static rt_err_t rt_acmp_init(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev != RT_NULL);
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp->hook.cbFunc = RT_NULL;
acmp->hook.userPtr = RT_NULL;
acmp->hook.cbFunc = RT_NULL;
acmp->hook.userPtr = RT_NULL;
return RT_EOK;
return RT_EOK;
}
/***************************************************************************//**
* @brief
* Configure ACMP device
* Configure ACMP device
*
* @details
*
* @note
*
* @param[in] dev
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] cmd
* ACMP control command
* ACMP control command
*
* @param[in] args
* Arguments
* Arguments
*
* @return
* Error code
* Error code
******************************************************************************/
static rt_err_t rt_acmp_control(
rt_device_t dev,
rt_uint8_t cmd,
void *args)
rt_device_t dev,
rt_uint8_t cmd,
void *args)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev != RT_NULL);
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* Suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
ACMP_Disable(acmp->acmp_device);
break;
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* Suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
ACMP_Disable(acmp->acmp_device);
break;
case RT_DEVICE_CTRL_RESUME:
/* Resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
ACMP_Enable(acmp->acmp_device);
break;
case RT_DEVICE_CTRL_RESUME:
/* Resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
ACMP_Enable(acmp->acmp_device);
break;
case RT_DEVICE_CTRL_ACMP_INIT:
{
rt_bool_t int_en = false;
struct efm32_acmp_control_t *control;
case RT_DEVICE_CTRL_ACMP_INIT:
{
rt_bool_t int_en = false;
struct efm32_acmp_control_t *control;
control = (struct efm32_acmp_control_t *)args;
acmp_debug("ACMP: control -> init start\n");
control = (struct efm32_acmp_control_t *)args;
acmp_debug("ACMP: control -> init start\n");
/* Configure ACMPn */
if (control->init == RT_NULL)
{
return -RT_ERROR;
}
ACMP_Init(acmp->acmp_device, control->init);
ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput);
if (control->output != RT_NULL)
{
ACMP_GPIOSetup(
acmp->acmp_device,
control->output->location,
control->output->enable,
control->output->invert);
int_en = true;
}
if (control->hook.cbFunc != RT_NULL)
{
acmp->hook.cbFunc = control->hook.cbFunc;
acmp->hook.userPtr = control->hook.userPtr;
int_en = true;
}
/* Configure ACMPn */
if (control->init == RT_NULL)
{
return -RT_ERROR;
}
ACMP_Init(acmp->acmp_device, control->init);
ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput);
if (control->output != RT_NULL)
{
ACMP_GPIOSetup(
acmp->acmp_device,
control->output->location,
control->output->enable,
control->output->invert);
int_en = true;
}
if (control->hook.cbFunc != RT_NULL)
{
acmp->hook.cbFunc = control->hook.cbFunc;
acmp->hook.userPtr = control->hook.userPtr;
int_en = true;
}
if (int_en)
{
/* Enable edge interrupt */
ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE);
ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE);
if (int_en)
{
/* Enable edge interrupt */
ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE);
ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE);
/* Enable ACMP0/1 interrupt vector in NVIC */
NVIC_ClearPendingIRQ(ACMP0_IRQn);
NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(ACMP0_IRQn);
}
}
break;
/* Enable ACMP0/1 interrupt vector in NVIC */
NVIC_ClearPendingIRQ(ACMP0_IRQn);
NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(ACMP0_IRQn);
}
}
break;
case RT_DEVICE_CTRL_ACMP_OUTPUT:
*((rt_bool_t *)args) = \
(acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false;
break;
case RT_DEVICE_CTRL_ACMP_OUTPUT:
*((rt_bool_t *)args) = \
(acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false;
break;
default:
return -RT_ERROR;
}
default:
return -RT_ERROR;
}
return RT_EOK;
return RT_EOK;
}
/***************************************************************************//**
* @brief
* Register ACMP device
* Register ACMP device
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] name
* Device name
* Device name
*
* @param[in] flag
* Configuration flags
* Configuration flags
*
* @param[in] acmp
* Pointer to ACMP device descriptor
* Pointer to ACMP device descriptor
*
* @return
* Error code
* Error code
******************************************************************************/
rt_err_t rt_hw_acmp_register(
rt_device_t device,
const char *name,
rt_uint32_t flag,
struct efm32_acmp_device_t *acmp)
rt_device_t device,
const char *name,
rt_uint32_t flag,
struct efm32_acmp_device_t *acmp)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device != RT_NULL);
device->type = RT_Device_Class_Char; /* fixme: should be acmp type */
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_acmp_init;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_acmp_control;
device->user_data = acmp;
device->type = RT_Device_Class_Char; /* fixme: should be acmp type */
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_acmp_init;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_acmp_control;
device->user_data = acmp;
/* register a character device */
return rt_device_register(device, name, flag);
/* register a character device */
return rt_device_register(device, name, flag);
}
/***************************************************************************//**
* @brief
* ACMP edge trigger interrupt handler
* ACMP edge trigger interrupt handler
*
* @details
*
@ -234,96 +234,96 @@ rt_err_t rt_hw_acmp_register(
******************************************************************************/
void rt_hw_acmp_isr(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev != RT_NULL);
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
if (acmp->hook.cbFunc != RT_NULL)
{
(acmp->hook.cbFunc)(acmp->hook.userPtr);
}
if (acmp->hook.cbFunc != RT_NULL)
{
(acmp->hook.cbFunc)(acmp->hook.userPtr);
}
}
/***************************************************************************//**
* @brief
* Initialize the specified ACMP unit
* Initialize the specified ACMP unit
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] unitNumber
* Unit number
* Unit number
*
* @return
* Pointer to ACMP device
* Pointer to ACMP device
******************************************************************************/
static struct efm32_acmp_device_t *rt_hw_acmp_unit_init(
rt_device_t device,
rt_uint8_t unitNumber)
rt_device_t device,
rt_uint8_t unitNumber)
{
struct efm32_acmp_device_t *acmp;
efm32_irq_hook_init_t hook;
CMU_Clock_TypeDef acmpClock;
struct efm32_acmp_device_t *acmp;
efm32_irq_hook_init_t hook;
CMU_Clock_TypeDef acmpClock;
do
{
/* Allocate device */
acmp = rt_malloc(sizeof(struct efm32_acmp_device_t));
if (acmp == RT_NULL)
{
acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber);
break;
}
do
{
/* Allocate device */
acmp = rt_malloc(sizeof(struct efm32_acmp_device_t));
if (acmp == RT_NULL)
{
acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber);
break;
}
/* Initialization */
if (unitNumber >= ACMP_COUNT)
{
break;
}
switch (unitNumber)
{
case 0:
acmp->acmp_device = ACMP0;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0;
break;
/* Initialization */
if (unitNumber >= ACMP_COUNT)
{
break;
}
switch (unitNumber)
{
case 0:
acmp->acmp_device = ACMP0;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0;
break;
case 1:
acmp->acmp_device = ACMP1;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1;
break;
case 1:
acmp->acmp_device = ACMP1;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1;
break;
default:
break;
}
default:
break;
}
/* Enable ACMP clock */
CMU_ClockEnable(acmpClock, true);
/* Enable ACMP clock */
CMU_ClockEnable(acmpClock, true);
/* Reset */
ACMP_Reset(acmp->acmp_device);
/* Reset */
ACMP_Reset(acmp->acmp_device);
/* Config interrupt and NVIC */
hook.type = efm32_irq_type_acmp;
hook.unit = unitNumber;
hook.cbFunc = rt_hw_acmp_isr;
hook.userPtr = device;
efm32_irq_hook_register(&hook);
/* Config interrupt and NVIC */
hook.type = efm32_irq_type_acmp;
hook.unit = unitNumber;
hook.cbFunc = rt_hw_acmp_isr;
hook.userPtr = device;
efm32_irq_hook_register(&hook);
return acmp;
} while(0);
return acmp;
} while(0);
if (acmp)
{
rt_free(acmp);
}
rt_kprintf("ACMP: Init failed!\n");
return RT_NULL;
if (acmp)
{
rt_free(acmp);
}
rt_kprintf("ACMP: Init failed!\n");
return RT_NULL;
}
/***************************************************************************//**
@ -338,20 +338,20 @@ static struct efm32_acmp_device_t *rt_hw_acmp_unit_init(
******************************************************************************/
void rt_hw_acmp_init(void)
{
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
#ifdef RT_USING_ACMP0
if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL)
{
rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp);
}
if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL)
{
rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp);
}
#endif
#ifdef RT_USING_ACMP1
if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL)
{
rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp);
}
if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL)
{
rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp);
}
#endif
}
@ -369,50 +369,50 @@ void rt_hw_acmp_init(void)
******************************************************************************/
ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq)
{
if (!hfperFreq)
{
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
if (!hfperFreq)
{
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
/* Just in case, make sure we get non-zero freq for below calculation */
if (!hfperFreq)
{
hfperFreq = 1;
}
}
/* Just in case, make sure we get non-zero freq for below calculation */
if (!hfperFreq)
{
hfperFreq = 1;
}
}
/* Determine number of HFPERCLK cycle >= 10us */
if (4 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime4;
}
else if (8 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime8;
}
else if (16 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime16;
}
else if (32 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime32;
}
else if (64 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime64;
}
else if (128 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime128;
}
else if (256 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime256;
}
else if (512 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime512;
}
/* Determine number of HFPERCLK cycle >= 10us */
if (4 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime4;
}
else if (8 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime8;
}
else if (16 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime16;
}
else if (32 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime32;
}
else if (64 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime64;
}
else if (128 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime128;
}
else if (256 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime256;
}
else if (512 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime512;
}
}
#endif

20
bsp/efm32/drv_acmp.h
View File

@ -23,24 +23,24 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_acmp_device_t
{
ACMP_TypeDef *acmp_device;
efm32_irq_hook_t hook;
ACMP_TypeDef *acmp_device;
efm32_irq_hook_t hook;
};
struct efm32_acmp_output_t
{
rt_uint32_t location;
rt_bool_t enable;
rt_bool_t invert;
rt_uint32_t location;
rt_bool_t enable;
rt_bool_t invert;
};
struct efm32_acmp_control_t
{
ACMP_Init_TypeDef *init;
ACMP_Channel_TypeDef posInput;
ACMP_Channel_TypeDef negInput;
struct efm32_acmp_output_t *output;
efm32_irq_hook_t hook;
ACMP_Init_TypeDef *init;
ACMP_Channel_TypeDef posInput;
ACMP_Channel_TypeDef negInput;
struct efm32_acmp_output_t *output;
efm32_irq_hook_t hook;
};
/* Exported constants --------------------------------------------------------*/

1114
bsp/efm32/drv_adc.c
View File

File diff suppressed because it is too large Load Diff

60
bsp/efm32/drv_adc.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file drv_adc.h
* @brief ADC driver of RT-Thread RTOS for EFM32
* @file drv_adc.h
* @brief ADC driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,9 +10,9 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-02-21 onelife Initial creation for EFM32
* 2011-07-14 onelife Add multiple channels support for scan mode
* Date Author Notes
* 2011-02-21 onelife Initial creation for EFM32
* 2011-07-14 onelife Add multiple channels support for scan mode
******************************************************************************/
#ifndef __DRV_ADC_H__
#define __DRV_ADC_H__
@ -21,50 +21,50 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_adc_device_t
{
ADC_TypeDef *adc_device;
rt_uint8_t mode;
rt_uint8_t singleCount;
rt_uint8_t singleDmaChannel;
rt_uint8_t scanCount;
rt_uint8_t scanDmaChannel;
ADC_TypeDef *adc_device;
rt_uint8_t mode;
rt_uint8_t singleCount;
rt_uint8_t singleDmaChannel;
rt_uint8_t scanCount;
rt_uint8_t scanDmaChannel;
};
struct efm32_adc_control_single_t
{
rt_uint8_t count;
rt_uint8_t dmaChannel;
ADC_InitSingle_TypeDef *init;
rt_uint8_t count;
rt_uint8_t dmaChannel;
ADC_InitSingle_TypeDef *init;
};
struct efm32_adc_control_scan_t
{
rt_uint8_t count;
rt_uint8_t dmaChannel;
ADC_InitScan_TypeDef *init;
rt_uint8_t count;
rt_uint8_t dmaChannel;
ADC_InitScan_TypeDef *init;
};
struct efm32_adc_control_t
{
rt_uint8_t mode;
struct efm32_adc_control_scan_t scan;
struct efm32_adc_control_single_t single;
rt_uint8_t mode;
struct efm32_adc_control_scan_t scan;
struct efm32_adc_control_single_t single;
};
struct efm32_adc_result_t
{
rt_uint8_t mode;
void *buffer;
rt_uint8_t mode;
void *buffer;
};
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#define ADC_MODE_SINGLE (0x01)
#define ADC_MODE_SCAN (0x02)
#define ADC_MODE_TAILGATE (0x04)
#define ADC_OP_SINGLE_REPEAT (0x10)
#define ADC_OP_SCAN_REPEAT (0x20)
#define ADC_MASK_MODE (0x0f)
#define ADC_MASK_OP (0xf0)
#define ADC_MODE_SINGLE (0x01)
#define ADC_MODE_SCAN (0x02)
#define ADC_MODE_TAILGATE (0x04)
#define ADC_OP_SINGLE_REPEAT (0x10)
#define ADC_OP_SCAN_REPEAT (0x20)
#define ADC_MASK_MODE (0x0f)
#define ADC_MASK_OP (0xf0)
/* Exported functions ------------------------------------------------------- */
void rt_hw_adc_init(void);

28
bsp/efm32/drv_emu.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file drv_emu.c
* @brief EMU driver of RT-Thread RTOS for EFM32
* @file drv_emu.c
* @brief EMU driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,8 +10,8 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2012-02-21 onelife Initial creation for EFM32
* Date Author Notes
* 2012-02-21 onelife Initial creation for EFM32
******************************************************************************/
/***************************************************************************//**
@ -27,7 +27,7 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
#ifdef EFM32_EMU_DEBUG
#define emu_debug(format,args...) rt_kprintf(format, ##args)
#define emu_debug(format,args...) rt_kprintf(format, ##args)
#else
#define emu_debug(format,args...)
#endif
@ -176,7 +176,7 @@ void emu_em4_enable(void)
/***************************************************************************//**
* @brief
* Initialize EMU module related hardware
* Initialize EMU module related hardware
*
* @details
*
@ -213,22 +213,22 @@ void efm32_emu_init(void)
break;
}
/* init thread */
/* init thread */
if (rt_thread_init(
&emu_task.thread,
"EMU",
emu_task_main_loop, (void *)&emu_task,
emu_task_main_loop, (void *)&emu_task,
(void *)&emu_task.stack, sizeof(emu_task.stack),
RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK)
RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK)
{
break;
}
/* startup */
if (rt_thread_startup(&emu_task.thread) != RT_EOK)
{
/* startup */
if (rt_thread_startup(&emu_task.thread) != RT_EOK)
{
break;
}
}
} while (0);
rt_kprintf("EMU err: init failed!\n");

12
bsp/efm32/drv_emu.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file drv_emu.h
* @brief EMU driver of RT-Thread RTOS for EFM32
* @file drv_emu.h
* @brief EMU driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,9 +10,9 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-02-21 onelife Initial creation for EFM32
* 2011-07-14 onelife Add multiple channels support for scan mode
* Date Author Notes
* 2011-02-21 onelife Initial creation for EFM32
* 2011-07-14 onelife Add multiple channels support for scan mode
******************************************************************************/
#ifndef __DRV_EMU_H__
#define __DRV_EMU_H__

1514
bsp/efm32/drv_ethernet.c
View File

File diff suppressed because it is too large Load Diff

30
bsp/efm32/drv_ethernet.h
View File

@ -1,11 +1,11 @@
/***************************************************************************//**
* @file drv_ethernet.h
* @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART
* @file drv_ethernet.h
* @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART
* module
* This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet
* This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet
* controller with SPI interface.
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -13,8 +13,8 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-06-22 onelife Initial creation for using EFM32 USART module
* Date Author Notes
* 2011-06-22 onelife Initial creation for using EFM32 USART module
******************************************************************************/
#ifndef __DEV_ETHERNET_H__
#define __DEV_ETHERNET_H__
@ -25,18 +25,18 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#define ETH_ADDR_LEN (6)
#define ETH_CLK_MAX (10000000) /* Should be more than 8 Mz (Errata 1) */
#define ETH_ADDR_LEN (6)
#define ETH_CLK_MAX (10000000) /* Should be more than 8 Mz (Errata 1) */
//#define ETH_HALF_DUPLEX
#define ETH_PERIOD_WAIT_INIT (RT_TICK_PER_SECOND/100)
#define ETH_PERIOD_WAIT_TX (RT_TICK_PER_SECOND/100)
#define ETH_SPI_RX_SKIP (1)
#define ETH_PERIOD_WAIT_INIT (RT_TICK_PER_SECOND/100)
#define ETH_PERIOD_WAIT_TX (RT_TICK_PER_SECOND/100)
#define ETH_SPI_RX_SKIP (1)
#define ETH_RESET_PORT (gpioPortB)
#define ETH_RESET_PIN (9)
#define ETH_INT_PORT (gpioPortB)
#define ETH_INT_PIN (10)
#define ETH_RESET_PORT (gpioPortB)
#define ETH_RESET_PIN (9)
#define ETH_INT_PORT (gpioPortB)
#define ETH_INT_PIN (10)
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_hw_eth_init(void);

1228
bsp/efm32/drv_leuart.c
View File

File diff suppressed because it is too large Load Diff

54
bsp/efm32/drv_leuart.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file drv_leuart.h
* @brief LEUART driver of RT-Thread RTOS for EFM32
* @file drv_leuart.h
* @brief LEUART driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,8 +10,8 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-12-09 onelife Initial creation for EFM32
* Date Author Notes
* 2011-12-09 onelife Initial creation for EFM32
******************************************************************************/
#ifndef __DRV_LEUSART_H__
#define __DRV_LEUSART_H__
@ -20,37 +20,37 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_leuart_int_mode_t
{
rt_uint8_t *data_ptr;
rt_uint8_t data_size;
rt_uint32_t read_index, save_index;
rt_uint8_t *data_ptr;
rt_uint8_t data_size;
rt_uint32_t read_index, save_index;
};
struct efm32_leuart_dma_mode_t
{
/* DMA Channel */
rt_uint32_t dma_channel;
/* DMA Channel */
rt_uint32_t dma_channel;
/* buffer info */
rt_uint32_t *data_ptr;
rt_uint8_t data_size;
/* buffer info */
rt_uint32_t *data_ptr;
rt_uint8_t data_size;
};
struct efm32_leuart_device_t
{
/* Counter */
rt_uint32_t counter;
/* Lock */
struct rt_semaphore *lock;
/* Unit number */
rt_uint8_t unit;
/* State */
volatile rt_uint8_t state;
/* Pointer to LEUART device structure */
LEUART_TypeDef *leuart_device;
/* Pointer to RX structure */
void *rx_mode;
/* Pointer to TX structure */
void *tx_mode;
/* Counter */
rt_uint32_t counter;
/* Lock */
struct rt_semaphore *lock;
/* Unit number */
rt_uint8_t unit;
/* State */
volatile rt_uint8_t state;
/* Pointer to LEUART device structure */
LEUART_TypeDef *leuart_device;
/* Pointer to RX structure */
void *rx_mode;
/* Pointer to TX structure */
void *tx_mode;
};
/* Exported constants --------------------------------------------------------*/

114
bsp/efm32/drv_rtc.c
View File

@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2010-12-27 onelife Modify for EFM32
* 2011-06-16 onelife Modify init function for efm32lib v2 upgrading
@ -33,7 +33,7 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
#ifdef RT_RTC_DEBUG
#define rtc_debug(format,args...) rt_kprintf(format, ##args)
#define rtc_debug(format,args...) rt_kprintf(format, ##args)
#else
#define rtc_debug(format,args...)
#endif
@ -55,10 +55,10 @@ static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag)
}
static rt_size_t rt_rtc_read(
rt_device_t dev,
rt_off_t pos,
void* buffer,
rt_size_t size)
rt_device_t dev,
rt_off_t pos,
void* buffer,
rt_size_t size)
{
return 0;
}
@ -91,16 +91,16 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
*(rt_uint32_t *)args = rtc_time + RTC_CounterGet();
rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet());
rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet());
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
{
rtc_time = *(rt_uint32_t *)args;
rtc_debug("RTC: set rtc_time %x\n", rtc_time);
rtc_debug("RTC: set rtc_time %x\n", rtc_time);
/* Reset counter */
RTC_CounterReset();
/* Reset counter */
RTC_CounterReset();
}
break;
}
@ -118,12 +118,12 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
******************************************************************************/
void rt_hw_rtc_isr(rt_device_t device)
{
if (RTC->IF & RTC_IFC_OF)
{
rtc_time += _RTC_CNT_MASK;
}
if (RTC->IF & RTC_IFC_OF)
{
rtc_time += _RTC_CNT_MASK;
}
RTC->IFC = _RTC_IFC_MASK;
RTC->IFC = _RTC_IFC_MASK;
}
/***************************************************************************//**
@ -147,25 +147,25 @@ void rt_hw_rtc_isr(rt_device_t device)
* Error code
******************************************************************************/
rt_err_t rt_hw_rtc_register(
rt_device_t device,
const char *name,
rt_uint32_t flag)
rt_device_t device,
const char *name,
rt_uint32_t flag)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device != RT_NULL);
device->type = RT_Device_Class_RTC;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = rt_rtc_open;
device->close = RT_NULL;
device->read = rt_rtc_read;
device->write = RT_NULL;
device->control = rt_rtc_control;
device->user_data = RT_NULL; /* no private */
device->type = RT_Device_Class_RTC;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = rt_rtc_open;
device->close = RT_NULL;
device->read = rt_rtc_read;
device->write = RT_NULL;
device->control = rt_rtc_control;
device->user_data = RT_NULL; /* no private */
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
}
@ -179,50 +179,50 @@ rt_err_t rt_hw_rtc_register(
******************************************************************************/
void rt_hw_rtc_init(void)
{
rt_uint32_t reset;
rt_uint32_t reset;
reset = RMU_ResetCauseGet();
reset = RMU_ResetCauseGet();
// TODO: What is the current reset mode?
if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST)
// TODO: What is the current reset mode?
if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST)
{
RTC_Init_TypeDef rtcInit;
efm32_irq_hook_init_t hook;
RTC_Init_TypeDef rtcInit;
efm32_irq_hook_init_t hook;
rtcInit.enable = true;
rtcInit.debugRun = false;
rtcInit.comp0Top = false;
rtcInit.enable = true;
rtcInit.debugRun = false;
rtcInit.comp0Top = false;
rtc_time = 0UL;
rtc_time = 0UL;
rt_kprintf("rtc is not configured\n");
rt_kprintf("please configure with set_date and set_time\n");
/* Configuring clock */
/* Configuring clock */
CMU_ClockDivSet(cmuClock_RTC,cmuClkDiv_32768);
CMU_ClockEnable(cmuClock_RTC, true);
/* Initialize and enable RTC */
RTC_Reset();
RTC_Init(&rtcInit);
/* Initialize and enable RTC */
RTC_Reset();
RTC_Init(&rtcInit);
hook.type = efm32_irq_type_rtc;
hook.unit = 0;
hook.cbFunc = rt_hw_rtc_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
hook.type = efm32_irq_type_rtc;
hook.unit = 0;
hook.cbFunc = rt_hw_rtc_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
/* Enabling Interrupt from RTC */
RTC_IntEnable(RTC_IFC_OF);
RTC_IntClear(RTC_IFC_OF);
/* Enabling Interrupt from RTC */
RTC_IntEnable(RTC_IFC_OF);
RTC_IntClear(RTC_IFC_OF);
NVIC_ClearPendingIRQ(RTC_IRQn);
NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(RTC_IRQn);
NVIC_ClearPendingIRQ(RTC_IRQn);
NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(RTC_IRQn);
}
/* register rtc device */
rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA);
rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA);
}
#endif

2
bsp/efm32/drv_rtc.h
View File

@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2010-12-27 onelife Modification for EFM32
*********************************************************************/

76
bsp/efm32/drv_sdcard.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file drv_sdcard.h
* @brief Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32
* @file drv_sdcard.h
* @brief Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32
* USART module
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -11,9 +11,9 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-05-13 onelife Initial creation for using EFM32 USART module
* 2011-07-07 onelife Modify initialization function to return error code
* Date Author Notes
* 2011-05-13 onelife Initial creation for using EFM32 USART module
* 2011-07-07 onelife Modify initialization function to return error code
******************************************************************************/
#ifndef __DEV_SDCARD_H__
#define __DEV_SDCARD_H__
@ -33,43 +33,43 @@
#error "EFM32 SPI clock should not be more than (EFM32_HFXO_FREQUENCY/2)"
#endif
#define SD_SPEED_LOW (0)
#define SD_SPEED_HIGH (1)
#define SD_WAIT_PERIOD (RT_TICK_PER_SECOND)
#define SD_SPEED_LOW (0)
#define SD_SPEED_HIGH (1)
#define SD_WAIT_PERIOD (RT_TICK_PER_SECOND)
#define SD_SECTOR_SIZE_SHIFT (9)
#define SD_SECTOR_SIZE (1 << SD_SECTOR_SIZE_SHIFT)
#define SD_BLOCK_SIZE_CSD (16)
#define SD_BLOCK_SIZE_CID (16)
#define SD_BLOCK_SIZE_OCR (4)
#define SD_BLOCK_SIZE_SDSTAT (64)
#define SD_SECTOR_SIZE_SHIFT (9)
#define SD_SECTOR_SIZE (1 << SD_SECTOR_SIZE_SHIFT)
#define SD_BLOCK_SIZE_CSD (16)
#define SD_BLOCK_SIZE_CID (16)
#define SD_BLOCK_SIZE_OCR (4)
#define SD_BLOCK_SIZE_SDSTAT (64)
/* Card type definitions (CardType) */
#define CT_MMC (0x01)
#define CT_SD1 (0x02)
#define CT_SD2 (0x04)
#define CT_SDC (CT_SD1|CT_SD2)
#define CT_BLOCK (0x08)
#define CT_MMC (0x01)
#define CT_SD1 (0x02)
#define CT_SD2 (0x04)
#define CT_SDC (CT_SD1|CT_SD2)
#define CT_BLOCK (0x08)
/* Definitions for MMC/SDC command */
#define CMD0 (0) /* GO_IDLE_STATE */
#define CMD1 (1) /* SEND_OP_COND */
#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */
#define CMD8 (8) /* SEND_IF_COND */
#define CMD9 (9) /* SEND_CSD */
#define CMD10 (10) /* SEND_CID */
#define CMD12 (12) /* STOP_TRANSMISSION */
#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */
#define CMD16 (16) /* SET_BLOCKLEN */
#define CMD17 (17) /* READ_SINGLE_BLOCK */
#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
#define CMD23 (23) /* SET_BLOCK_COUNT */
#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */
#define CMD24 (24) /* WRITE_BLOCK */
#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
#define CMD41 (41) /* SEND_OP_COND (ACMD) */
#define CMD55 (55) /* APP_CMD */
#define CMD58 (58) /* READ_OCR */
#define CMD0 (0) /* GO_IDLE_STATE */
#define CMD1 (1) /* SEND_OP_COND */
#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */
#define CMD8 (8) /* SEND_IF_COND */
#define CMD9 (9) /* SEND_CSD */
#define CMD10 (10) /* SEND_CID */
#define CMD12 (12) /* STOP_TRANSMISSION */
#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */
#define CMD16 (16) /* SET_BLOCKLEN */
#define CMD17 (17) /* READ_SINGLE_BLOCK */
#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
#define CMD23 (23) /* SET_BLOCK_COUNT */
#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */
#define CMD24 (24) /* WRITE_BLOCK */
#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
#define CMD41 (41) /* SEND_OP_COND (ACMD) */
#define CMD55 (55) /* APP_CMD */
#define CMD58 (58) /* READ_OCR */
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_spiSd_init(void);

2
bsp/efm32/drv_timer.c
View File

@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-01-18 onelife Initial creation for EFM32
* 2011-06-17 onelife Modify init function for efm32lib v2 upgrading
******************************************************************************/

4
bsp/efm32/drv_usart.c
View File

@ -34,9 +34,9 @@
* 2011-12-20 onelife Add 9-bit SPI mode support
* 2011-12-20 onelife Change SPI write format (same as SPI read)
* 2011-12-20 onelife Change USART status format
* 2011-12-27 onelife Utilize "USART_PRESENT", "USART_COUNT",
* 2011-12-27 onelife Utilize "USART_PRESENT", "USART_COUNT",
* "UART_PRESENT" and "UART_COUNT"
* 2012-05-16 onelife Fix a bug in rt_hw_usart_init()
* 2012-05-16 onelife Fix a bug in rt_hw_usart_init()
******************************************************************************/
/***************************************************************************//**

42
bsp/efm32/enc28j60.h
View File

@ -197,9 +197,9 @@
#define MACON3_FRMLNEN 0x02
#define MACON3_FULDPX 0x01
// ENC28J60 MACON4 Register Bit Definitions
#define MACON4_DEFER (1<<6)
#define MACON4_BPEN (1<<5)
#define MACON4_NOBKOFF (1<<4)
#define MACON4_DEFER (1<<6)
#define MACON4_BPEN (1<<5)
#define MACON4_NOBKOFF (1<<4)
// ENC28J60 MICMD Register Bit Definitions
#define MICMD_MIISCAN 0x02
#define MICMD_MIIRD 0x01
@ -218,12 +218,12 @@
#define PHSTAT1_LLSTAT 0x0004
#define PHSTAT1_JBSTAT 0x0002
/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
#define PHSTAT2_TXSTAT (1 << 13)
#define PHSTAT2_RXSTAT (1 << 12)
#define PHSTAT2_COLSTAT (1 << 11)
#define PHSTAT2_LSTAT (1 << 10)
#define PHSTAT2_DPXSTAT (1 << 9)
#define PHSTAT2_PLRITY (1 << 5)
#define PHSTAT2_TXSTAT (1 << 13)
#define PHSTAT2_RXSTAT (1 << 12)
#define PHSTAT2_COLSTAT (1 << 11)
#define PHSTAT2_LSTAT (1 << 10)
#define PHSTAT2_DPXSTAT (1 << 9)
#define PHSTAT2_PLRITY (1 << 5)
// ENC28J60 PHY PHCON2 Register Bit Definitions
#define PHCON2_FRCLINK 0x4000
#define PHCON2_TXDIS 0x2000
@ -282,13 +282,13 @@
#define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
// SPI operation codes
#define ENC28J60_READ_CTRL_REG (0x00)
#define ENC28J60_READ_BUF_MEM (0x20 | 0x1A)
#define ENC28J60_WRITE_CTRL_REG (0x40)
#define ENC28J60_WRITE_BUF_MEM (0x60 | 0x1A)
#define ENC28J60_BIT_FIELD_SET (0x80)
#define ENC28J60_BIT_FIELD_CLR (0xA0)
#define ENC28J60_SOFT_RESET (0xE0 | 0x1F)
#define ENC28J60_READ_CTRL_REG (0x00)
#define ENC28J60_READ_BUF_MEM (0x20 | 0x1A)
#define ENC28J60_WRITE_CTRL_REG (0x40)
#define ENC28J60_WRITE_BUF_MEM (0x60 | 0x1A)
#define ENC28J60_BIT_FIELD_SET (0x80)
#define ENC28J60_BIT_FIELD_CLR (0xA0)
#define ENC28J60_SOFT_RESET (0xE0 | 0x1F)
// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
// buffer boundaries applied to internal 8K ram
@ -296,17 +296,17 @@
//
// start with recbuf at 0/
#define RXSTART_INIT 0x0
#define RXSTART_INIT 0x0
// receive buffer end
#define RXSTOP_INIT (0x1FFF - 0x0600 - 1)
#define RXSTOP_INIT (0x1FFF - 0x0600 - 1)
// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
#define TXSTART_INIT (0x1FFF - 0x0600)
#define TXSTART_INIT (0x1FFF - 0x0600)
// stp TX buffer at end of mem
#define TXSTOP_INIT 0x1FFF
#define TXSTOP_INIT 0x1FFF
// max frame length which the conroller will accept:
#define MAX_FRAMELEN 1518
#define MAX_FRAMELEN 1518
void rt_hw_enc28j60_init(void);

8
bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h
View File

@ -127,11 +127,11 @@ EMSTATUS DMD_setClippingArea(uint16_t xStart, uint16_t yStart,
uint16_t width, uint16_t height);
EMSTATUS DMD_writeData(uint16_t x, uint16_t y,
const uint8_t data[], uint32_t numPixels);
EMSTATUS DMD_writeDataRLE(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
EMSTATUS DMD_writeDataRLE(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
const uint8_t *data);
EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
const uint8_t *data,
int red, int green, int blue, int weight);
EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
const uint8_t *data,
int red, int green, int blue, int weight);
EMSTATUS DMD_readData(uint16_t x, uint16_t y,
uint8_t data[], uint32_t numPixels);
EMSTATUS DMD_writeColor(uint16_t x, uint16_t y, uint8_t red,

4
bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c
View File

@ -425,8 +425,8 @@ EMSTATUS DMD_writeData(uint16_t x, uint16_t y, const uint8_t data[],
* DMD_OK on success, otherwise error code
******************************************************************************/
EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
const uint8_t *data,
int red, int green, int blue, int weight)
const uint8_t *data,
int red, int green, int blue, int weight)
{
uint32_t color = 0;
int xpos, ypos;

8
bsp/efm32/graphics/tftspi.h
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@ -1,8 +1,8 @@
/***************************************************************************//**
* @file tftspi.h
* @brief Stub functions of EFM32 LCD driver
* @file tftspi.h
* @brief Stub functions of EFM32 LCD driver
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-20 onelife Initial creation for EFM32
******************************************************************************/
#ifndef __TFTSPI_H__

672
bsp/efm32/hdl_interrupt.c
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File diff suppressed because it is too large Load Diff

28
bsp/efm32/hdl_interrupt.h
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@ -21,31 +21,31 @@
/* Exported types ------------------------------------------------------------*/
enum efm32_irq_hook_type_t
{
efm32_irq_type_dma = 0,
efm32_irq_type_rtc,
efm32_irq_type_timer,
efm32_irq_type_dma = 0,
efm32_irq_type_rtc,
efm32_irq_type_timer,
efm32_irq_type_letimer,
efm32_irq_type_gpio,
efm32_irq_type_acmp,
efm32_irq_type_usart,
efm32_irq_type_leuart,
efm32_irq_type_iic
efm32_irq_type_gpio,
efm32_irq_type_acmp,
efm32_irq_type_usart,
efm32_irq_type_leuart,
efm32_irq_type_iic
};
typedef void (*efm32_irq_callback_t)(rt_device_t device);
typedef struct
{
enum efm32_irq_hook_type_t type;
rt_uint8_t unit;
efm32_irq_callback_t cbFunc;
void *userPtr;
enum efm32_irq_hook_type_t type;
rt_uint8_t unit;
efm32_irq_callback_t cbFunc;
void *userPtr;
} efm32_irq_hook_init_t;
typedef struct
{
efm32_irq_callback_t cbFunc;
void *userPtr;
efm32_irq_callback_t cbFunc;
void *userPtr;
} efm32_irq_hook_t;
/* Exported constants --------------------------------------------------------*/

56
bsp/efm32/httpd.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file httpd.c
* @brief Simple http server demo application
* @file httpd.c
* @brief Simple http server demo application
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,8 +10,8 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-07-04 onelife Derive from Energy Micro demo application
* Date Author Notes
* 2011-07-04 onelife Derive from Energy Micro demo application
******************************************************************************/
/**************************************************************************//**
@ -94,29 +94,29 @@
static int temp, vdd;
static char indexdata[700];
static const char indexdata1[] =
"HTTP/1.0 200 OK\r\n\
Content-type: text/html\r\n\
Pragma: no-cache\r\n\
Refresh: 5\r\n\
\r\n\
<html>\
<head><title>EFM32 HTTPD DEMO</title><head>\
<body>\
<h1>This is a simple http server</h1>\
<br><br><B>Ethernet controller: ENC28J60</B>\
<br><br><B>Refreshing timers: ";
"HTTP/1.0 200 OK\r\n\
Content-type: text/html\r\n\
Pragma: no-cache\r\n\
Refresh: 5\r\n\
\r\n\
<html>\
<head><title>EFM32 HTTPD DEMO</title><head>\
<body>\
<h1>This is a simple http server</h1>\
<br><br><B>Ethernet controller: ENC28J60</B>\
<br><br><B>Refreshing timers: ";
static const char indexdata2[] =
"<br><br><B>Current Vdd: ";
"<br><br><B>Current Vdd: ";
static const char indexdata3[] =
" V</B>\
<br><br><B>Current temperature: ";
" V</B>\
<br><br><B>Current temperature: ";
static const char indexdata4[] =
" C</B>\
</body>\
</html>";
" C</B>\
</body>\
</html>";
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@ -169,9 +169,9 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err
counter++;
}
vdd = rt_hw_get_vdd();
rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100);
counter += 4;
vdd = rt_hw_get_vdd();
rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100);
counter += 4;
for (i = 0; i < sizeof(indexdata3) - 1; i++)
{
@ -179,15 +179,15 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err
counter++;
}
temp = rt_hw_get_temp();
temp = rt_hw_get_temp();
/*Set temperature sign*/
if (temp < 0)
{
indexdata[counter] = '-';
counter++;
}
rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100);
counter += 5;
rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100);
counter += 5;
for (i = 0; i < sizeof(indexdata4); i++)
{

170
bsp/efm32/mma7455l.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file mma7455l.c
* @brief Header file of Freescale MMA7455L 3 axis Low-g digital output
* @file mma7455l.c
* @brief Header file of Freescale MMA7455L 3 axis Low-g digital output
* accelerometer
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -11,101 +11,101 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-08-02 onelife Initial creation
* Date Author Notes
* 2011-08-02 onelife Initial creation
******************************************************************************/
#ifndef __MMA7455L_H__
#define __MMA7455L_H__
#define XOUTL 0x00 //00 10 bits output value X LSB (Read only)
#define XOUTH 0x01 //01 10 bits output value X MSB (Read only)
#define YOUTL 0x02 //02 10 bits output value Y LSB (Read only)
#define YOUTH 0x03 //03 10 bits output value Y MSB (Read only)
#define ZOUTL 0x04 //04 10 bits output value Z LSB (Read only)
#define ZOUTH 0x05 //05 10 bits output value Z MSB (Read only)
#define XOUT8 0x06 //06 8 bits Output value X (Read only)
#define YOUT8 0x07 //07 8 bits Output value Y (Read only)
#define ZOUT8 0x08 //08 8 bits Output value Z (Read only)
#define STATUS 0x09 //09 Status registers (Read only)
#define DETSRC 0x0A //10 Detection source registers (Read only)
#define TOUT 0x0B //11 Temperature output value (Optional)
#define RESERVED1 0x0C //12 Reserved
#define I2CAD 0x0D //13 I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write)
#define USRINF 0x0E //14 User information (Optional, Read only)
#define WHOAMI 0x0F //15 Who am I value (Optional, Read only)
#define XOFFL 0x10 //16 Offset drift X value (LSB) (Read/Write)
#define XOFFH 0x11 //17 Offset drift X value (MSB) (Read/Write)
#define YOFFL 0x12 //18 Offset drift Y value (LSB) (Read/Write)
#define YOFFH 0x13 //19 Offset drift Y value (MSB) (Read/Write)
#define ZOFFL 0x14 //20 Offset drift Z value (LSB) (Read/Write)
#define ZOFFH 0x15 //21 Offset drift Z value (MSB) (Read/Write)
#define MCTL 0x16 //22 Mode control (Read/Write)
#define INTRST 0x17 //23 Interrupt latch reset (Read/Write)
#define CTL1 0x18 //24 Control 1 (Read/Write)
#define CTL2 0x19 //25 Control 2 (Read/Write)
#define LDTH 0x1A //26 Level detection threshold limit value (Read/Write)
#define PDTH 0x1B //27 Pulse detection threshold limit value (Read/Write)
#define PW 0x1C //28 Pulse duration value (Read/Write)
#define LT 0x1D //29 Latency time value (Read/Write)
#define TW 0x1E //30 Time window for second pulse value(Read/Write)
#define RESERVED2 0x1F //31 Reserved
#define XOUTL 0x00 //00 10 bits output value X LSB (Read only)
#define XOUTH 0x01 //01 10 bits output value X MSB (Read only)
#define YOUTL 0x02 //02 10 bits output value Y LSB (Read only)
#define YOUTH 0x03 //03 10 bits output value Y MSB (Read only)
#define ZOUTL 0x04 //04 10 bits output value Z LSB (Read only)
#define ZOUTH 0x05 //05 10 bits output value Z MSB (Read only)
#define XOUT8 0x06 //06 8 bits Output value X (Read only)
#define YOUT8 0x07 //07 8 bits Output value Y (Read only)
#define ZOUT8 0x08 //08 8 bits Output value Z (Read only)
#define STATUS 0x09 //09 Status registers (Read only)
#define DETSRC 0x0A //10 Detection source registers (Read only)
#define TOUT 0x0B //11 Temperature output value (Optional)
#define RESERVED1 0x0C //12 Reserved
#define I2CAD 0x0D //13 I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write)
#define USRINF 0x0E //14 User information (Optional, Read only)
#define WHOAMI 0x0F //15 Who am I value (Optional, Read only)
#define XOFFL 0x10 //16 Offset drift X value (LSB) (Read/Write)
#define XOFFH 0x11 //17 Offset drift X value (MSB) (Read/Write)
#define YOFFL 0x12 //18 Offset drift Y value (LSB) (Read/Write)
#define YOFFH 0x13 //19 Offset drift Y value (MSB) (Read/Write)
#define ZOFFL 0x14 //20 Offset drift Z value (LSB) (Read/Write)
#define ZOFFH 0x15 //21 Offset drift Z value (MSB) (Read/Write)
#define MCTL 0x16 //22 Mode control (Read/Write)
#define INTRST 0x17 //23 Interrupt latch reset (Read/Write)
#define CTL1 0x18 //24 Control 1 (Read/Write)
#define CTL2 0x19 //25 Control 2 (Read/Write)
#define LDTH 0x1A //26 Level detection threshold limit value (Read/Write)
#define PDTH 0x1B //27 Pulse detection threshold limit value (Read/Write)
#define PW 0x1C //28 Pulse duration value (Read/Write)
#define LT 0x1D //29 Latency time value (Read/Write)
#define TW 0x1E //30 Time window for second pulse value(Read/Write)
#define RESERVED2 0x1F //31 Reserved
/* For DETSRC */
#define DETSRC_INT_1 (0x01 << 0)
#define DETSRC_INT_2 (0x01 << 1)
#define DETSRC_PULSE_Z (0x01 << 2)
#define DETSRC_PULSE_Y (0x01 << 3)
#define DETSRC_PULSE_X (0x01 << 4)
#define DETSRC_LEVEL_Z (0x01 << 5)
#define DETSRC_LEVEL_Y (0x01 << 6)
#define DETSRC_LEVEL_X (0x01 << 7)
#define DETSRC_INT_1 (0x01 << 0)
#define DETSRC_INT_2 (0x01 << 1)
#define DETSRC_PULSE_Z (0x01 << 2)
#define DETSRC_PULSE_Y (0x01 << 3)
#define DETSRC_PULSE_X (0x01 << 4)
#define DETSRC_LEVEL_Z (0x01 << 5)
#define DETSRC_LEVEL_Y (0x01 << 6)
#define DETSRC_LEVEL_X (0x01 << 7)
/* For MCTL */
#define MCTL_SHIFT_MODE (0)
#define MCTL_SHIFT_G (2)
#define MCTL_MASK_MODE (0x03)
#define MCTL_MASK_G (0x0c)
#define MCTL_MODE_STANDBY (0x00 << MCTL_SHIFT_MODE)
#define MCTL_MODE_MEASUREMENT (0x01 << MCTL_SHIFT_MODE)
#define MCTL_MODE_LEVEL (0x02 << MCTL_SHIFT_MODE)
#define MCTL_MODE_PULSE (0x03 << MCTL_SHIFT_MODE)
#define MCTL_RANGE_8G (0x00 << MCTL_SHIFT_G)
#define MCTL_RANGE_4G (0x02 << MCTL_SHIFT_G)
#define MCTL_RANGE_2G (0x01 << MCTL_SHIFT_G)
#define MCTL_PIN_INT1 (0x01 << 6)
#define MCTL_SHIFT_MODE (0)
#define MCTL_SHIFT_G (2)
#define MCTL_MASK_MODE (0x03)
#define MCTL_MASK_G (0x0c)
#define MCTL_MODE_STANDBY (0x00 << MCTL_SHIFT_MODE)
#define MCTL_MODE_MEASUREMENT (0x01 << MCTL_SHIFT_MODE)
#define MCTL_MODE_LEVEL (0x02 << MCTL_SHIFT_MODE)
#define MCTL_MODE_PULSE (0x03 << MCTL_SHIFT_MODE)
#define MCTL_RANGE_8G (0x00 << MCTL_SHIFT_G)
#define MCTL_RANGE_4G (0x02 << MCTL_SHIFT_G)
#define MCTL_RANGE_2G (0x01 << MCTL_SHIFT_G)
#define MCTL_PIN_INT1 (0x01 << 6)
/* For INTRST */
#define INTRST_INT_1 (0x01 << 0)
#define INTRST_INT_2 (0x01 << 1)
#define INTRST_INT_1 (0x01 << 0)
#define INTRST_INT_2 (0x01 << 1)
/* For CTL1 */
#define CTL1_SHIFT_INTPIN (0)
#define CTL1_SHIFT_INT (1)
#define CTL1_SHIFT_AXES (3)
#define CTL1_SHIFT_THRESHOLD (6)
#define CTL1_SHIFT_BANDWIDTH (7)
#define CTL1_MASK_AXES (0x38)
#define CTL1_INTPIN_INVERSE (0x01 << CTL1_SHIFT_INTPIN)
#define CTL1_INT_LEVEL_PULSE (0x00 << CTL1_SHIFT_INT)
#define CTL1_INT_PULSE_LEVEL (0x01 << CTL1_SHIFT_INT)
#define CTL1_INT_SINGLE_DOUBLE (0x02 << CTL1_SHIFT_INT)
#define CTL1_X_DISABLE (0x01 << CTL1_SHIFT_AXES)
#define CTL1_Y_DISABLE (0x02 << CTL1_SHIFT_AXES)
#define CTL1_Z_DISABLE (0x04 << CTL1_SHIFT_AXES)
#define CTL1_THRESHOLD_ABSOLUTE (0x00 << CTL1_SHIFT_THRESHOLD)
#define CTL1_THRESHOLD_INTEGER (0x01 << CTL1_SHIFT_THRESHOLD)
#define CTL1_BANDWIDTH_62_5HZ (0x00 << CTL1_SHIFT_BANDWIDTH)
#define CTL1_BANDWIDTH_125HZ (0x01 << CTL1_SHIFT_BANDWIDTH)
#define CTL1_SHIFT_INTPIN (0)
#define CTL1_SHIFT_INT (1)
#define CTL1_SHIFT_AXES (3)
#define CTL1_SHIFT_THRESHOLD (6)
#define CTL1_SHIFT_BANDWIDTH (7)
#define CTL1_MASK_AXES (0x38)
#define CTL1_INTPIN_INVERSE (0x01 << CTL1_SHIFT_INTPIN)
#define CTL1_INT_LEVEL_PULSE (0x00 << CTL1_SHIFT_INT)
#define CTL1_INT_PULSE_LEVEL (0x01 << CTL1_SHIFT_INT)
#define CTL1_INT_SINGLE_DOUBLE (0x02 << CTL1_SHIFT_INT)
#define CTL1_X_DISABLE (0x01 << CTL1_SHIFT_AXES)
#define CTL1_Y_DISABLE (0x02 << CTL1_SHIFT_AXES)
#define CTL1_Z_DISABLE (0x04 << CTL1_SHIFT_AXES)
#define CTL1_THRESHOLD_ABSOLUTE (0x00 << CTL1_SHIFT_THRESHOLD)
#define CTL1_THRESHOLD_INTEGER (0x01 << CTL1_SHIFT_THRESHOLD)
#define CTL1_BANDWIDTH_62_5HZ (0x00 << CTL1_SHIFT_BANDWIDTH)
#define CTL1_BANDWIDTH_125HZ (0x01 << CTL1_SHIFT_BANDWIDTH)
/* For CTL2 */
#define CTL1_SHIFT_LEVEL (0)
#define CTL1_SHIFT_PULSE (1)
#define CTL1_SHIFT_DRIVE (2)
#define CTL2_LEVEL_OR (0x00 << CTL1_SHIFT_LEVEL)
#define CTL2_LEVEL_AND (0x01 << CTL1_SHIFT_LEVEL)
#define CTL2_PULSE_OR (0x00 << CTL1_SHIFT_PULSE)
#define CTL2_PULSE_AND (0x01 << CTL1_SHIFT_PULSE)
#define CTL2_DRIVE_STANDARD (0x00 << CTL1_SHIFT_DRIVE)
#define CTL2_DRIVE_STRONG (0x01 << CTL1_SHIFT_DRIVE)
#define CTL1_SHIFT_LEVEL (0)
#define CTL1_SHIFT_PULSE (1)
#define CTL1_SHIFT_DRIVE (2)
#define CTL2_LEVEL_OR (0x00 << CTL1_SHIFT_LEVEL)
#define CTL2_LEVEL_AND (0x01 << CTL1_SHIFT_LEVEL)
#define CTL2_PULSE_OR (0x00 << CTL1_SHIFT_PULSE)
#define CTL2_PULSE_AND (0x01 << CTL1_SHIFT_PULSE)
#define CTL2_DRIVE_STANDARD (0x00 << CTL1_SHIFT_DRIVE)
#define CTL2_DRIVE_STRONG (0x01 << CTL1_SHIFT_DRIVE)
#endif /* __MMA7455L_H__ */

128
bsp/efm32/rtconfig.h
View File

@ -1,7 +1,7 @@
/***************************************************************************//**
* @file rtconfig.h
* @brief RT-Thread config file
* COPYRIGHT (C) 2009, RT-Thread Development Team
* COPYRIGHT (C) 2009, RT-Thread Development Team
* @author
* @version 1.0
*******************************************************************************
@ -22,23 +22,23 @@
#define EFM32GG_DK3750
/* RT_NAME_MAX */
#define RT_NAME_MAX (8)
#define RT_NAME_MAX (8)
/* RT_ALIGN_SIZE */
#define RT_ALIGN_SIZE (4)
#define RT_ALIGN_SIZE (4)
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX (32)
#define RT_THREAD_PRIORITY_MAX (32)
/* Tick per Second */
#define RT_TICK_PER_SECOND (100)
#define RT_TICK_PER_SECOND (100)
/* SECTION: RT_DEBUG */
#define RT_DEBUG
#define RT_DEBUG_COLOR
//#define RT_DEBUG_MEM (1)
//#define RT_DEBUG_SCHEDULER (1)
//#define RT_DEBUG_IPC (1)
//#define RT_DEBUG_MEM (1)
//#define RT_DEBUG_SCHEDULER (1)
//#define RT_DEBUG_IPC (1)
//#define THREAD_DEBUG
//#define IRQ_DEBUG
#define RT_USING_OVERFLOW_CHECK
@ -69,9 +69,9 @@
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO (4)
#define RT_TIMER_THREAD_STACK_SIZE (512)
#define RT_TIMER_TICK_PER_SECOND (10)
#define RT_TIMER_THREAD_PRIO (4)
#define RT_TIMER_THREAD_STACK_SIZE (512)
#define RT_TIMER_TICK_PER_SECOND (10)
/* SECTION: IPC */
/* Using Semaphore*/
@ -134,10 +134,10 @@
#define EFM32_SPI_CLK_MODE(mode) (mode << 3) /* clock mode */
#if defined(EFM32_G8XX_STK)
//#define RT_USING_USART0 (0x0UL)
//#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER)
//#define RT_USART0_NAME "spi0"
//#define RT_USART0_USING_DMA (0x1UL)
//#define RT_USING_USART0 (0x0UL)
//#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER)
//#define RT_USART0_NAME "spi0"
//#define RT_USART0_USING_DMA (0x1UL)
#elif defined(EFM32_GXXX_DK)
#define RT_USING_USART0 (0x2UL)
#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER | EFM32_SPI_AUTOCS | \
@ -165,28 +165,28 @@
#endif
/* SECTION: IIC options */
//#define RT_USING_IIC0 0x3UL
#define RT_IIC0_NAME "iic0"
//#define RT_USING_IIC0 0x3UL
#define RT_IIC0_NAME "iic0"
/* SECTION: ACMP options */
//#define RT_USING_ACMP0
#define RT_ACMP0_NAME "acmp0"
#define RT_ACMP0_NAME "acmp0"
/* SECTION: ADC options */
#define RT_USING_ADC0
#define RT_ADC0_NAME "adc0"
#define RT_ADC0_NAME "adc0"
#if defined(RT_USING_ADC0)
#define RT_USING_MISC
#endif
/* SECTION: TIMER options */
//#define RT_USING_TIMER2 (0x00) /* Continuous mode */
#define RT_TIMER2_NAME "tmr2"
//#define RT_USING_TIMER2 (0x00) /* Continuous mode */
#define RT_TIMER2_NAME "tmr2"
/* SECTION: RTC options */
#if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750))
#define RT_USING_RTC
#define RT_RTC_NAME "rtc"
#define RT_RTC_NAME "rtc"
#endif
/* SECTION: Serial options */
@ -199,9 +199,9 @@
#define EFM_LEUART1 (0x21UL)
#if defined(EFM32_G8XX_STK)
#define RT_CONSOLE_DEVICE (EFM_USART1)
#define RT_CONSOLE_DEVICE (EFM_USART1)
#elif defined(EFM32_GXXX_DK)
#define RT_CONSOLE_DEVICE (EFM_USART1)
#define RT_CONSOLE_DEVICE (EFM_USART1)
#elif defined(EFM32GG_DK3750)
#if defined(EFM32GG_DK3750_USING_LEUART1)
#define RT_CONSOLE_DEVICE (EFM_LEUART1)
@ -217,7 +217,7 @@
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE (128)
#define RT_CONSOLEBUF_SIZE (128)
/* SECTION: finsh, a C-Express shell */
#define RT_USING_FINSH
@ -226,12 +226,12 @@
#define FINSH_USING_DESCRIPTION
/* SECTION: Peripheral devices */
#define EFM32_INTERFACE_ADC (0)
#define EFM32_INTERFACE_IIC (1)
#define EFM32_INTERFACE_SPI (2)
#define EFM32_INTERFACE_ADC (0)
#define EFM32_INTERFACE_IIC (1)
#define EFM32_INTERFACE_SPI (2)
#if (defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750))
//#define EFM32_USING_ACCEL EFM32_INTERFACE_IIC /* Three axis accelerometer */
//#define EFM32_USING_SFLASH /* SPI Flash */
//#define EFM32_USING_ACCEL EFM32_INTERFACE_IIC /* Three axis accelerometer */
//#define EFM32_USING_SFLASH /* SPI Flash */
#define EFM32_USING_SPISD /* MicroSD card */
//#define EFM32_USING_ETHERNET /* Ethernet controller */
//#define EFM32_USING_LCD /* TFT LCD */
@ -240,30 +240,30 @@
#if defined(EFM32_USING_ACCEL)
#if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
#define ACCEL_USING_DEVICE_NAME RT_ADC0_NAME
#define ACCEL_USING_DMA (0x3UL) /* For multiple channels scan mode */
#define ACCEL_USING_DEVICE_NAME RT_ADC0_NAME
#define ACCEL_USING_DMA (0x3UL) /* For multiple channels scan mode */
#elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
#define ACCEL_USING_DEVICE_NAME RT_IIC0_NAME
#define ACCEL_USING_DEVICE_NAME RT_IIC0_NAME
#endif
#endif
#if defined(EFM32_USING_SFLASH)
#define SFLASH_USING_DEVICE_NAME RT_USART0_NAME
#define SFLASH_USING_DEVICE_NAME RT_USART0_NAME
#endif
#if defined(EFM32_USING_SPISD)
#define SPISD_USING_DEVICE_NAME RT_USART0_NAME
#define SPISD_DEVICE_NAME "spiSd"
#define SPISD_USING_DEVICE_NAME RT_USART0_NAME
#define SPISD_DEVICE_NAME "spiSd"
#endif
#if defined(EFM32_USING_ETHERNET)
#if defined(EFM32_GXXX_DK)
#define ETH_USING_DEVICE_NAME RT_USART2_NAME
#define ETH_USING_DEVICE_NAME RT_USART2_NAME
#elif defined(EFM32GG_DK3750)
#define ETH_USING_DEVICE_NAME RT_USART1_NAME
#define ETH_USING_DEVICE_NAME RT_USART1_NAME
#endif
#define ETH_DEVICE_NAME "spiEth"
#define ETH_ADDR_DEFAULT {0x00, 0x01, 0x02, 0x03, 0x04, 0x05}
#define ETH_DEVICE_NAME "spiEth"
#define ETH_ADDR_DEFAULT {0x00, 0x01, 0x02, 0x03, 0x04, 0x05}
#endif
/* SECTION: device filesystem */
@ -271,9 +271,9 @@
#define RT_USING_DFS
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX (2)
/* the max number of opened files */
/* the max number of opened files */
#define DFS_FD_MAX (4)
/* the max number of cached sector */
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM (4)
#endif /* defined(RT_USING_NEWLIB) || defined(EFM32_USING_SPISD) */
#if defined(EFM32_USING_SPISD)
@ -288,8 +288,8 @@
#if defined(EFM32_USING_ETHERNET)
#define EFM32_USING_ETH_HTTPD
//#define EFM32_USING_ETH_UTILS
//#define hostName "onelife.dyndns.org"
//#define userPwdB64 "dXNlcjpwYXNzd2Q="
//#define hostName "onelife.dyndns.org"
//#define userPwdB64 "dXNlcjpwYXNzd2Q="
//#define RT_USING_LWIP
//#define RT_USING_NETUTILS
@ -308,37 +308,37 @@
//#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM (2)
#define RT_LWIP_TCP_PCB_NUM (2)
/* ip address of target*/
#define RT_LWIP_IPADDR0 (192)
#define RT_LWIP_IPADDR1 (168)
#define RT_LWIP_IPADDR2 (1)
#define RT_LWIP_IPADDR3 (118)
#define RT_LWIP_IPADDR0 (192)
#define RT_LWIP_IPADDR1 (168)
#define RT_LWIP_IPADDR2 (1)
#define RT_LWIP_IPADDR3 (118)
/* gateway address of target*/
#define RT_LWIP_GWADDR0 (192)
#define RT_LWIP_GWADDR1 (168)
#define RT_LWIP_GWADDR2 (1)
#define RT_LWIP_GWADDR3 (1)
#define RT_LWIP_GWADDR0 (192)
#define RT_LWIP_GWADDR1 (168)
#define RT_LWIP_GWADDR2 (1)
#define RT_LWIP_GWADDR3 (1)
/* mask address of target*/
#define RT_LWIP_MSKADDR0 (255)
#define RT_LWIP_MSKADDR1 (255)
#define RT_LWIP_MSKADDR2 (255)
#define RT_LWIP_MSKADDR3 (0)
#define RT_LWIP_MSKADDR0 (255)
#define RT_LWIP_MSKADDR1 (255)
#define RT_LWIP_MSKADDR2 (255)
#define RT_LWIP_MSKADDR3 (0)
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY (12)
#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4)
#define RT_LWIP_TCPTHREAD_STACKSIZE (1024)
#define RT_LWIP_TCPTHREAD_PRIORITY (12)
#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4)
#define RT_LWIP_TCPTHREAD_STACKSIZE (1024)
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY (15)
#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4)
#define RT_LWIP_ETHTHREAD_STACKSIZE (512)
#define RT_LWIP_ETHTHREAD_PRIORITY (15)
#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4)
#define RT_LWIP_ETHTHREAD_STACKSIZE (512)
#endif /* defined(EFM32_USING_ETHERNET) */
/* SECTION: RTGUI support */
#if defined(EFM32_USING_LCD)
#define LCD_USING_DEVICE_NAME RT_USART1_NAME
#define LCD_USING_DEVICE_NAME RT_USART1_NAME
#define LCD_DEVICE_NAME "lcd"
/* using RTGUI support */
// #define RT_USING_RTGUI

4
bsp/efm32/startup.c
View File

@ -10,12 +10,12 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2006-08-31 Bernard first implementation
* 2010-12-29 onelife Modify for EFM32
* 2011-12-20 onelife Add RTGUI initialization routine
* 2012-02-21 onelife Add energy management initialization routine
* 2012-05-15 onelife Modified to compatible with CMSIS v3
* 2012-05-15 onelife Modified to compatible with CMSIS v3
******************************************************************************/
/***************************************************************************//**