diff --git a/bsp/CME_M7/CME_M7.ld b/bsp/CME_M7/CME_M7.ld
new file mode 100644
index 0000000000..b157040dd5
--- /dev/null
+++ b/bsp/CME_M7/CME_M7.ld
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
+ * nuc472_flash.ld - Linker configuration file for project.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-08-24 aozima first implementation
+ *
+ *****************************************************************************/
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+SECTIONS
+{
+ .text :
+ {
+ _text = .;
+ KEEP(*(.isr_vector))
+ *(.text*)
+ *(.rodata*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for components init. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ } > FLASH
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > FLASH
+ __exidx_end = .;
+
+ /* end of all text. */
+ _etext = .;
+
+ .data : AT(_etext)
+ {
+ _data = .;
+ *(vtable)
+ *(.data*)
+ _edata = .;
+ } > SRAM
+
+ .bss :
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ _ebss = .;
+ } > SRAM
+ __bss_end = .;
+
+}
diff --git a/bsp/CME_M7/CME_M7.sct b/bsp/CME_M7/CME_M7.sct
new file mode 100644
index 0000000000..f125e284a2
--- /dev/null
+++ b/bsp/CME_M7/CME_M7.sct
@@ -0,0 +1,22 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+; load region size_region
+LR_IROM1 (0) (1024 * 128)
+{
+ ; load address = execution address
+ ER_IROM1 (0) (1024 * 128)
+ {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; RW data
+ RW_IRAM1 0x20000000 (1024 * 64)
+ {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/CME_M7/CMSIS/CME_M7/cmem7_it.c b/bsp/CME_M7/CMSIS/CME_M7/cmem7_it.c
new file mode 100644
index 0000000000..bb4c590c7b
--- /dev/null
+++ b/bsp/CME_M7/CMSIS/CME_M7/cmem7_it.c
@@ -0,0 +1,93 @@
+/**
+ *****************************************************************************
+ * @file cmem7_it.c
+ *
+ * @brief CMEM7 system exception file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_it.h"
+
+void NMI_Handler(void)
+{
+ while (1);
+}
+
+void HardFault_Handler(void)
+{
+ if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
+ __breakpoint (0); // halt program execution here
+ }
+ /* Go to infinite loop when Hard Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+void MemManage_Handler(void)
+{
+ if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
+ __breakpoint (0); // halt program execution here
+ }
+ /* Go to infinite loop when Memory Manage exception occurs */
+ while (1)
+ {
+ }
+}
+
+void BusFault_Handler(void)
+{
+ if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
+ __breakpoint (0); // halt program execution here
+ }
+ /* Go to infinite loop when Bus Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+void UsageFault_Handler(void)
+{
+ if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
+ __breakpoint (0); // halt program execution here
+ }
+ /* Go to infinite loop when Usage Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+void SVC_Handler(void)
+{
+}
+
+void DebugMon_Handler(void)
+{
+}
+
+void PendSV_Handler(void)
+{
+}
+
+void SysTick_Handler(void)
+{
+}
+
diff --git a/bsp/CME_M7/CMSIS/CME_M7/cmem7_it.h b/bsp/CME_M7/CMSIS/CME_M7/cmem7_it.h
new file mode 100644
index 0000000000..65260dd0cf
--- /dev/null
+++ b/bsp/CME_M7/CMSIS/CME_M7/cmem7_it.h
@@ -0,0 +1,401 @@
+/**
+ *****************************************************************************
+ * @file cmem7_it.h
+ *
+ * @brief CMEM7 system exception interrupt header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note Actually, you don't have to implement below involved function
+ * whick were defined as weak dummy functions in startup file.
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_IT_H
+#define __CMEM7_IT_H
+
+#include "cmem7.h"
+
+/**
+ * @brief This function handles NMI exception.
+ * @param None
+ * @retval None
+ */
+void NMI_Handler(void);
+
+/**
+ * @brief This function handles Hard Fault exception.
+ * @param None
+ * @retval None
+ */
+void HardFault_Handler(void);
+
+/**
+ * @brief This function handles Memory Manage exception.
+ * @param None
+ * @retval None
+ */
+void MemManage_Handler(void);
+
+/**
+ * @brief This function handles Bus Fault exception.
+ * @param None
+ * @retval None
+ */
+void BusFault_Handler(void);
+
+/**
+ * @brief This function handles Usage Fault exception.
+ * @param None
+ * @retval None
+ */
+void UsageFault_Handler(void);
+
+/**
+ * @brief This function handles SVCall exception.
+ * @param None
+ * @retval None
+ */
+void SVC_Handler(void);
+
+/**
+ * @brief This function handles Debug Monitor exception.
+ * @param None
+ * @retval None
+ */
+void DebugMon_Handler(void);
+
+/**
+ * @brief This function handles PendSV_Handler exception.
+ * @param None
+ * @retval None
+ */
+void PendSV_Handler(void);
+
+/**
+ * @brief This function handles SysTick Handler.
+ * @param None
+ * @retval None
+ */
+void SysTick_Handler(void);
+
+/**
+ * @brief This function handles ethernet interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void ETH_IRQHandler(void);
+
+/**
+ * @brief This function handles USB interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void USB_IRQHandler(void);
+
+/**
+ * @brief This function handles DMA interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void DMAC_IRQHandler(void);
+
+/**
+ * @brief This function handles CAN0 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void CAN0_IRQHandler(void);
+
+/**
+ * @brief This function handles CAN1 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void CAN1_IRQHandler(void);
+
+/**
+ * @brief This function handles FP0 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP0_IRQHandler(void);
+
+/**
+ * @brief This function handles FP1 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP1_IRQHandler(void);
+
+/**
+ * @brief This function handles FP2 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP2_IRQHandler(void);
+
+/**
+ * @brief This function handles FP3 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP3_IRQHandler(void);
+
+/**
+ * @brief This function handles FP4 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP4_IRQHandler(void);
+
+/**
+ * @brief This function handles FP5 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP5_IRQHandler(void);
+
+/**
+ * @brief This function handles FP6 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP6_IRQHandler(void);
+
+/**
+ * @brief This function handles FP7 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP7_IRQHandler(void);
+
+/**
+ * @brief This function handles FP8 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP8_IRQHandler(void);
+
+/**
+ * @brief This function handles FP9 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP9_IRQHandler(void);
+
+/**
+ * @brief This function handles FP10 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP10_IRQHandler(void);
+
+/**
+ * @brief This function handles FP11 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP11_IRQHandler(void);
+
+/**
+ * @brief This function handles FP12 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP12_IRQHandler(void);
+
+/**
+ * @brief This function handles FP13 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP13_IRQHandler(void);
+
+/**
+ * @brief This function handles FP14 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP14_IRQHandler(void);
+
+/**
+ * @brief This function handles FP15 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void FP15_IRQHandler(void);
+
+/**
+ * @brief This function handles UART0 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void UART0_IRQHandler(void);
+
+/**
+ * @brief This function handles UART1 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void UART1_IRQHandler(void);
+
+/**
+ * @brief This function handles ADC interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void ADC_IRQHandler(void);
+
+/**
+ * @brief This function handles GPIO interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void GPIO_IRQHandler(void);
+
+/**
+ * @brief This function handles SPI1 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void SPI1_IRQHandler(void);
+
+/**
+ * @brief This function handles I2C1 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void I2C1_IRQHandler(void);
+
+/**
+ * @brief This function handles SPI0 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void SPI0_IRQHandler(void);
+
+/**
+ * @brief This function handles I2C0 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void I2C0_IRQHandler(void);
+
+/**
+ * @brief This function handles RTC second interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void RTC_1S_IRQHandler(void);
+
+/**
+ * @brief This function handles RTC microsecond interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void RTC_1MS_IRQHandler(void);
+
+/**
+ * @brief This function handles watchdog interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void WDG_IRQHandler(void);
+
+/**
+ * @brief This function handles timer interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void TIMER_IRQHandler(void);
+
+/**
+ * @brief This function handles DDR interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void DDRC_SW_PROC_IRQHandler(void);
+
+/**
+ * @brief This function handles ethernet pmt interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void ETH_PMT_IRQHandler(void);
+
+/**
+ * @brief This function handles pad interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void PAD_IRQHandler(void);
+
+/**
+ * @brief This function handles DDR interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void DDRC_LANE_SYNC_IRQHandler(void);
+
+/**
+ * @brief This function handles UART2 interrupt.
+ * @param None
+ * @retval None
+ * @note Implement it in your interrupt handler
+ */
+void UART2_IRQHandler(void);
+
+#endif /* __CMEM7_IT_H */
+
diff --git a/bsp/CME_M7/CMSIS/CME_M7/startup/arm/startup_cmem7.s b/bsp/CME_M7/CMSIS/CME_M7/startup/arm/startup_cmem7.s
new file mode 100644
index 0000000000..175ec85647
--- /dev/null
+++ b/bsp/CME_M7/CMSIS/CME_M7/startup/arm/startup_cmem7.s
@@ -0,0 +1,288 @@
+;*****************************************************************************
+;* @file start_cmem7.h
+;*
+;* @brief CMEM7 startup file
+;*
+;*
+;* @version V1.0
+;* @date 3. September 2013
+;*
+;* @note
+;*
+;*****************************************************************************
+;* @attention
+;*
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+;* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+;* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+;* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*
+;* © COPYRIGHT 2013 Capital-micro
+;*****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD ETH_IRQHandler ; ETH
+ DCD USB_IRQHandler ; USB
+ DCD DMAC_IRQHandler ; DMAC
+ DCD CAN0_IRQHandler ; CAN0
+ DCD CAN1_IRQHandler ; CAN1
+ DCD FP0_IRQHandler ; FP[0:15]
+ DCD FP1_IRQHandler
+ DCD FP2_IRQHandler
+ DCD FP3_IRQHandler
+ DCD FP4_IRQHandler
+ DCD FP5_IRQHandler
+ DCD FP6_IRQHandler
+ DCD FP7_IRQHandler
+ DCD FP8_IRQHandler
+ DCD FP9_IRQHandler
+ DCD FP10_IRQHandler
+ DCD FP11_IRQHandler
+ DCD FP12_IRQHandler
+ DCD FP13_IRQHandler
+ DCD FP14_IRQHandler
+ DCD FP15_IRQHandler ; 21
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD ADC_IRQHandler ; ADC
+ DCD GPIO_IRQHandler ; GPIO
+ DCD SPI1_IRQHandler ; SPI1
+ DCD I2C1_IRQHandler ; I2C1
+ DCD SPI0_IRQHandler ; SPI0
+ DCD I2C0_IRQHandler ; I2C0
+ DCD RTC_1S_IRQHandler ; RTC 1S
+ DCD RTC_1MS_IRQHandler ; RTC 1MS
+ DCD WDG_IRQHandler ; Watchdog
+ DCD TIMER_IRQHandler ; Timer 0 || 1 || 2 || 3
+ DCD DDRC_SW_PROC_IRQHandler ; DDRC sw proc
+ DCD ETH_PMT_IRQHandler ; ETH pmt
+ DCD PAD_IRQHandler ; PAD
+ DCD DDRC_LANE_SYNC_IRQHandler ; DDRC lane sync
+ DCD UART2_IRQHandler ; UART2
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT DMAC_IRQHandler [WEAK]
+ EXPORT CAN0_IRQHandler [WEAK]
+ EXPORT CAN1_IRQHandler [WEAK]
+ EXPORT FP0_IRQHandler [WEAK]
+ EXPORT FP1_IRQHandler [WEAK]
+ EXPORT FP2_IRQHandler [WEAK]
+ EXPORT FP3_IRQHandler [WEAK]
+ EXPORT FP4_IRQHandler [WEAK]
+ EXPORT FP5_IRQHandler [WEAK]
+ EXPORT FP6_IRQHandler [WEAK]
+ EXPORT FP7_IRQHandler [WEAK]
+ EXPORT FP8_IRQHandler [WEAK]
+ EXPORT FP9_IRQHandler [WEAK]
+ EXPORT FP10_IRQHandler [WEAK]
+ EXPORT FP11_IRQHandler [WEAK]
+ EXPORT FP12_IRQHandler [WEAK]
+ EXPORT FP13_IRQHandler [WEAK]
+ EXPORT FP14_IRQHandler [WEAK]
+ EXPORT FP15_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT GPIO_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT RTC_1S_IRQHandler [WEAK]
+ EXPORT RTC_1MS_IRQHandler [WEAK]
+ EXPORT WDG_IRQHandler [WEAK]
+ EXPORT TIMER_IRQHandler [WEAK]
+ EXPORT DDRC_SW_PROC_IRQHandler [WEAK]
+ EXPORT ETH_PMT_IRQHandler [WEAK]
+ EXPORT PAD_IRQHandler [WEAK]
+ EXPORT DDRC_LANE_SYNC_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ETH_IRQHandler
+USB_IRQHandler
+DMAC_IRQHandler
+CAN0_IRQHandler
+CAN1_IRQHandler
+FP0_IRQHandler
+FP1_IRQHandler
+FP2_IRQHandler
+FP3_IRQHandler
+FP4_IRQHandler
+FP5_IRQHandler
+FP6_IRQHandler
+FP7_IRQHandler
+FP8_IRQHandler
+FP9_IRQHandler
+FP10_IRQHandler
+FP11_IRQHandler
+FP12_IRQHandler
+FP13_IRQHandler
+FP14_IRQHandler
+FP15_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+ADC_IRQHandler
+GPIO_IRQHandler
+SPI1_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+I2C0_IRQHandler
+RTC_1S_IRQHandler
+RTC_1MS_IRQHandler
+WDG_IRQHandler
+TIMER_IRQHandler
+DDRC_SW_PROC_IRQHandler
+ETH_PMT_IRQHandler
+PAD_IRQHandler
+DDRC_LANE_SYNC_IRQHandler
+UART2_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* (C) COPYRIGHT 2011 Capital Micro *****END OF FILE*****
diff --git a/bsp/CME_M7/CMSIS/CME_M7/system_cmem7.c b/bsp/CME_M7/CMSIS/CME_M7/system_cmem7.c
new file mode 100644
index 0000000000..4022916ba3
--- /dev/null
+++ b/bsp/CME_M7/CMSIS/CME_M7/system_cmem7.c
@@ -0,0 +1,39 @@
+/**
+ *****************************************************************************
+ * @file system_cmem7.c
+ *
+ * @brief CMEM7 system initial file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7.h"
+#include "cmem7_includes.h"
+
+void SystemInit (void) {
+ // Generally, we use DLL clock as system clock, not default oscillator
+ GLB_SelectSysClkSource(SYS_CLK_SEL_DLL);
+
+ // change NMI to PAD IRQ
+ GLB_SetNmiIrqNum(PAD_INT_IRQn);
+
+ return ;
+}
+
diff --git a/bsp/CME_M7/CMSIS/SConscript b/bsp/CME_M7/CMSIS/SConscript
new file mode 100644
index 0000000000..b850fc90bf
--- /dev/null
+++ b/bsp/CME_M7/CMSIS/SConscript
@@ -0,0 +1,31 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+CME_M7/system_cmem7.c
+""")
+
+# add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += ['Device/Nuvoton/NUC472_442/Source/GCC/startup_NUC472_442.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += ['CME_M7/startup/arm/startup_cmem7.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += ['Device/Nuvoton/NUC472_442/Source/IAR/startup_NUC472_442.S']
+
+path = [cwd + '/CME_M7']
+#ath += [cwd + '/StdDriver/inc']
+
+# if GetDepend(['RT_USING_BSP_CMSIS']):
+ # path += [cwd + '/CMSIS/Include']
+# elif GetDepend(['RT_USING_RTT_CMSIS']):
+ # path += [RTT_ROOT + '/components/CMSIS/Include']
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/CME_M7/SConscript b/bsp/CME_M7/SConscript
new file mode 100644
index 0000000000..0992612410
--- /dev/null
+++ b/bsp/CME_M7/SConscript
@@ -0,0 +1,12 @@
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/CME_M7/SConstruct b/bsp/CME_M7/SConstruct
new file mode 100644
index 0000000000..4d5dfc1d4d
--- /dev/null
+++ b/bsp/CME_M7/SConstruct
@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/CME_M7/StdPeriph_Driver/SConscript b/bsp/CME_M7/StdPeriph_Driver/SConscript
new file mode 100644
index 0000000000..bcc08ad28e
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/SConscript
@@ -0,0 +1,14 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Glob('src/*.c')
+
+path = [cwd + '/inc']
+
+group = DefineGroup('StdPeriph_Driver', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/CMEM7.h b/bsp/CME_M7/StdPeriph_Driver/inc/CMEM7.h
new file mode 100644
index 0000000000..c7905ed6f4
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/CMEM7.h
@@ -0,0 +1,7945 @@
+
+/****************************************************************************************************//**
+ * @file CMEM7.h
+ *
+ * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
+ * CMEM7 from .
+ *
+ * @version V1.0
+ * @date 5. June 2014
+ *
+ * @note Generated with SVDConv V2.75
+ * from CMSIS SVD File 'SVDConv_CME_M7.svd' Version 1.0,
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+ * @{
+ */
+
+/** @addtogroup CMEM7
+ * @{
+ */
+
+#ifndef CMEM7_H
+#define CMEM7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* ---------------------- CMEM7 Specific Interrupt Numbers ---------------------- */
+ ETH_INT_IRQn = 0, /*!< 0 ETH_INT */
+ USB_INT_IRQn = 1, /*!< 1 USB_INT */
+ DMA_INT_IRQn = 2, /*!< 2 DMA_INT */
+ CAN0_INT_IRQn = 3, /*!< 3 CAN0_INT */
+ CAN1_INT_IRQn = 4, /*!< 4 CAN1_INT */
+ FP0_INT_IRQn = 5, /*!< 5 FP0_INT */
+ FP1_INT_IRQn = 6, /*!< 6 FP1_INT */
+ FP2_INT_IRQn = 7, /*!< 7 FP2_INT */
+ FP3_INT_IRQn = 8, /*!< 8 FP3_INT */
+ FP4_INT_IRQn = 9, /*!< 9 FP4_INT */
+ FP5_INT_IRQn = 10, /*!< 10 FP5_INT */
+ FP6_INT_IRQn = 11, /*!< 11 FP6_INT */
+ FP7_INT_IRQn = 12, /*!< 12 FP7_INT */
+ FP8_INT_IRQn = 13, /*!< 13 FP8_INT */
+ FP9_INT_IRQn = 14, /*!< 14 FP9_INT */
+ FP10_INT_IRQn = 15, /*!< 15 FP10_INT */
+ FP11_INT_IRQn = 16, /*!< 16 FP11_INT */
+ FP12_INT_IRQn = 17, /*!< 17 FP12_INT */
+ FP13_INT_IRQn = 18, /*!< 18 FP13_INT */
+ FP14_INT_IRQn = 19, /*!< 19 FP14_INT */
+ FP15_INT_IRQn = 20, /*!< 20 FP15_INT */
+ UART0_INT_IRQn = 21, /*!< 21 UART0_INT */
+ UART1_INT_IRQn = 22, /*!< 22 UART1_INT */
+ ADC_INT_IRQn = 23, /*!< 23 ADC_INT */
+ GPIO_INT_IRQn = 24, /*!< 24 GPIO_INT */
+ SPI1_INT_IRQn = 25, /*!< 25 SPI1_INT */
+ I2C1_INT_IRQn = 26, /*!< 26 I2C1_INT */
+ SPI0_INT_IRQn = 27, /*!< 27 SPI0_INT */
+ I2C0_INT_IRQn = 28, /*!< 28 I2C0_INT */
+ RTC_1S_INT_IRQn = 29, /*!< 29 RTC_1S_INT */
+ RTC_1MS_INT_IRQn = 30, /*!< 30 RTC_1MS_INT */
+ WDG_INT_IRQn = 31, /*!< 31 WDG_INT */
+ TIMER_INT_IRQn = 32, /*!< 32 TIMER_INT */
+ DDRC_SW_PROC_IRQn = 33, /*!< 33 DDRC_SW_PROC */
+ ETH_PMT_INT_IRQn = 34, /*!< 34 ETH_PMT_INT */
+ PAD_INT_IRQn = 35, /*!< 35 PAD_INT */
+ DDRC_LANE_SYNC_IRQn = 36, /*!< 36 DDRC_LANE_SYNC */
+ UART2_INT_IRQn = 37 /*!< 37 UART2_INT */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
+#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 0 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include /*!< Cortex-M3 processor and core peripherals */
+#include "system_CMEM7.h" /*!< CMEM7 System */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ UART0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief asynchronous serial controller 0 (UART0)
+ */
+
+typedef struct { /*!< UART0 Structure */
+ __IO uint16_t BAUDRATE; /*!< baudrate Register */
+ __I uint16_t RESERVED0;
+ __IO uint16_t TX_BUF; /*!< transmit buffer Register */
+ __I uint16_t RESERVED1;
+ __I uint16_t RX_BUF; /*!< receive buffer Register */
+ __I uint16_t RESERVED2;
+
+ union {
+ __IO uint32_t CTRL; /*!< control Register */
+
+ struct {
+ __IO uint32_t MODE : 3; /*!< asc mode control */
+ __IO uint32_t STOP : 2; /*!< number of stop bits selection */
+ __IO uint32_t PARITY : 1; /*!< parity selection */
+ __IO uint32_t LOOPBACK : 1; /*!< loopback mode enable bit */
+ uint32_t : 1;
+ __IO uint32_t RX_EN : 1; /*!< receive enable bit */
+ uint32_t : 1;
+ __IO uint32_t FIFO_EN : 1; /*!< FIFO enable bit */
+ __IO uint32_t CTS : 1; /*!< Clear to send, enable signal to send */
+ __IO uint32_t BAUD_MODE : 1; /*!< baudrate generation mode */
+ __IO uint32_t RX_THRESHOLD: 5; /*!< receive threshold */
+ __IO uint32_t RX_HALF_FULL: 5; /*!< receive fifi half full level */
+ } CTRL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_MASK; /*!< interrupt mask register */
+
+ struct {
+ __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */
+ __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */
+ __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */
+ __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */
+ __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */
+ __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */
+ __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */
+ __IO uint32_t PE : 1; /*!< parity error interrupt */
+ __IO uint32_t FE : 1; /*!< frame error interrupt */
+ __IO uint32_t OE : 1; /*!< overrun error interrupt */
+ __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */
+ } INT_MASK_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t STATUS; /*!< status register */
+
+ struct {
+ __IO uint32_t RNE : 1; /*!< receiver FIFO not empty */
+ __IO uint32_t TE : 1; /*!< Transmitter FIFO empty */
+ __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */
+ __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty */
+ __IO uint32_t TOE : 1; /*!< time out when the receiver FIFO is empty */
+ __IO uint32_t RHF : 1; /*!< receiver FIFO is half full */
+ __IO uint32_t TF : 1; /*!< transmitter FIFO is full */
+ } STATUS_b; /*!< BitSize */
+ };
+ __IO uint8_t TIMEOUT; /*!< timeout Register */
+ __I uint8_t RESERVED3[3];
+
+ union {
+ __IO uint32_t TX_RESET; /*!< transmit reset Register */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< enable */
+ } TX_RESET_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RX_RESET; /*!< receive reset Register */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< enable */
+ } RX_RESET_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RUN; /*!< uart enable register */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< enable */
+ } RUN_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_RAW; /*!< raw interrupt before mask register */
+
+ struct {
+ __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */
+ __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */
+ __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */
+ __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */
+ __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */
+ __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */
+ __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */
+ __IO uint32_t PE : 1; /*!< parity error interrupt */
+ __IO uint32_t FE : 1; /*!< frame error interrupt */
+ __IO uint32_t OE : 1; /*!< overrun error interrupt */
+ __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */
+ } INT_RAW_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_SEEN; /*!< interrupt after mask register */
+
+ struct {
+ __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */
+ __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */
+ __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */
+ __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */
+ __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */
+ __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */
+ __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */
+ __IO uint32_t PE : 1; /*!< parity error interrupt */
+ __IO uint32_t FE : 1; /*!< frame error interrupt */
+ __IO uint32_t OE : 1; /*!< overrun error interrupt */
+ __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */
+ } INT_SEEN_b; /*!< BitSize */
+ };
+} UART0_Type;
+
+
+/* ================================================================================ */
+/* ================ WDG ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief watchdog (WDG)
+ */
+
+typedef struct { /*!< WDG Structure */
+
+ union {
+ __IO uint32_t CTRL; /*!< control Register */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< flag indicates if watchdog is enabled or not */
+ __IO uint32_t INT_LEN : 1; /*!< watchdog report interrupt when COUNTER is 1/4 or 1/2 of LENGTH */
+ } CTRL_b; /*!< BitSize */
+ };
+ __IO uint32_t LEN; /*!< Ticks decrease down to 25% or 50% to trigger an interrupt */
+
+ union {
+ __IO uint32_t INT_CTRL; /*!< interrupt control */
+
+ struct {
+ __IO uint32_t MASK : 1; /*!< mask register */
+ __IO uint32_t TRIGGER_MODE: 1; /*!< trigger mode */
+ } INT_CTRL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_STA; /*!< interrupt status register */
+
+ struct {
+ __IO uint32_t STA : 1; /*!< interrupt status */
+ } INT_STA_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_RAW; /*!< interrupt raw register */
+
+ struct {
+ __IO uint32_t STA : 1; /*!< interrupt status */
+ } INT_RAW_b; /*!< BitSize */
+ };
+ __I uint32_t CNT; /*!< counter register */
+} WDG_Type;
+
+
+/* ================================================================================ */
+/* ================ TIMER0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief timer 0 (TIMER0)
+ */
+
+typedef struct { /*!< TIMER0 Structure */
+
+ union {
+ __IO uint32_t CTRL; /*!< control Register */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< flag indicates if timer is enabled or not */
+ } CTRL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t TYPE; /*!< type Register */
+
+ struct {
+ __IO uint32_t SIGNLE_SHOT: 1; /*!< indicate timer generate only one interrupt if not reload */
+ } TYPE_b; /*!< BitSize */
+ };
+ __IO uint32_t LEN; /*!< length */
+
+ union {
+ __IO uint32_t INT_EN; /*!< interrupt enable */
+
+ struct {
+ __IO uint32_t EN_REVERSE : 1; /*!< flag indicates if timer is disable or not */
+ } INT_EN_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_STA; /*!< interrupt status */
+
+ struct {
+ __IO uint32_t STA : 1; /*!< interrupt status */
+ } INT_STA_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_RAW; /*!< interrupt raw register */
+
+ struct {
+ __IO uint32_t STA : 1; /*!< interrupt status */
+ } INT_RAW_b; /*!< BitSize */
+ };
+ __I uint32_t CNT; /*!< counter register */
+} TIMER0_Type;
+
+
+/* ================================================================================ */
+/* ================ SPI0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI 0 (SPI0)
+ */
+
+typedef struct { /*!< SPI0 Structure */
+
+ union {
+ __I uint32_t STATUS; /*!< status Register */
+
+ struct {
+ __I uint32_t RFIFO_EMPTY: 1; /*!< receive fifo is empty */
+ __I uint32_t RFIFO_FULL : 1; /*!< receive fifo is full */
+ __I uint32_t RFIFO_ALMOST_EMPTY: 1; /*!< receive fifo is almost empty */
+ __I uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full */
+ __I uint32_t TFIFO_EMPTY: 1; /*!< transmit fifo is empty */
+ __I uint32_t TFIFO_FULL : 1; /*!< transmit fifo is full */
+ __I uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo is almost empty */
+ __I uint32_t TFIFO_ALMOST_FULL: 1; /*!< transmit fifo almost full */
+ __I uint32_t BUSY : 1; /*!< indecates if SPI is idle or busy */
+ } STATUS_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTRL; /*!< control Register */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< indicates if SPI is enabled or not */
+ __IO uint32_t RX_EN : 1; /*!< indicates if SPI receiver is enabled or not */
+ __IO uint32_t CLK_HIGH : 1; /*!< indicats if idle clock polarity is high level */
+ __IO uint32_t NEG_EDGE : 1; /*!< 1, indicates SPI takes sample at the rise edge and transmit
+ data at the trailing edge. 0, conversely. */
+ __IO uint32_t TX_BIT_SEQUENCE: 1; /*!< transmit bit sequence. 0 : MSB is sent first */
+ __IO uint32_t RX_BIT_SEQUENCE: 1; /*!< receive bit sequence. 0: MSB is received first */
+ } CTRL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_MASK; /*!< interrupt mask Register */
+
+ struct {
+ __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */
+ __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */
+ __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */
+ __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */
+ __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */
+ __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */
+ __IO uint32_t DONE : 1; /*!< transmit done interrupt */
+ } INT_MASK_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_STATUS; /*!< interrupt Register */
+
+ struct {
+ __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */
+ __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */
+ __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */
+ __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */
+ __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */
+ __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */
+ __IO uint32_t DONE : 1; /*!< transmit done interrupt */
+ } INT_STATUS_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_RAW; /*!< interrupt raw Register */
+
+ struct {
+ __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */
+ __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */
+ __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */
+ __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */
+ __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */
+ __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */
+ __IO uint32_t DONE : 1; /*!< transmit done interrupt */
+ } INT_RAW_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t BCNT; /*!< bit length while transmitting and receiving */
+
+ struct {
+ __IO uint32_t CNT : 5; /*!< bit length while transmitting and receiving, BCNT + 1 */
+ } BCNT_b; /*!< BitSize */
+ };
+ __IO uint8_t GAP; /*!< half cycle number between continuous data frame */
+ __I uint8_t RESERVED0[3];
+ __IO uint16_t DIV; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */
+ __I uint16_t RESERVED1;
+ __IO uint32_t TRANS_CNT; /*!< transmit data length, data number = TRANS_CNT + 1 */
+
+ union {
+ __O uint32_t TRANS_START; /*!< transmit startup register, write 1 to trigger transmision once */
+
+ struct {
+ __O uint32_t TX_TRIGGER : 1; /*!< write 1 to trigger transmision once */
+ } TRANS_START_b; /*!< BitSize */
+ };
+ __IO uint32_t RW_DATA; /*!< raw data register */
+} SPI0_Type;
+
+
+/* ================================================================================ */
+/* ================ I2C0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I2C 0 (I2C0)
+ */
+
+typedef struct { /*!< I2C0 Structure */
+
+ union {
+ __IO uint32_t CTRL; /*!< control Register */
+
+ struct {
+ __IO uint32_t MODE : 1; /*!< master or slave mode */
+ __IO uint32_t MASTER_ADDR_WIDTH: 1; /*!< 7- or 10-bits address as a master */
+ __IO uint32_t SLAVE_ADDR_WIDTH: 1; /*!< 7- or 10-bits address width as a slave */
+ } CTRL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint16_t TAR; /*!< target address Register */
+
+ struct {
+ __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */
+ __IO uint16_t START_BYTE : 1; /*!< Enable start Byte for each transfer */
+ } TAR_b; /*!< BitSize */
+ };
+ __I uint16_t RESERVED0;
+
+ union {
+ __IO uint16_t SAR; /*!< slave address Register */
+
+ struct {
+ __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */
+ } SAR_b; /*!< BitSize */
+ };
+ __I uint16_t RESERVED1;
+
+ union {
+ __IO uint32_t DATA_CMD; /*!< I2C transfer data/command entry */
+
+ struct {
+ __IO uint32_t DATA : 8; /*!< 8-bits data */
+ __O uint32_t RD_CMD : 1; /*!< read command for master mode only, write 0 if slave mode */
+ __O uint32_t WR_CMD : 1; /*!< write command for master mode only */
+ __O uint32_t WR_RD_CMD : 1; /*!< write and read command for master mode only */
+ } DATA_CMD_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t WRITE_READ_CNT; /*!< I2C write and read data byte counter Register */
+
+ struct {
+ __IO uint32_t RD_BYTE_CNT: 9; /*!< Decide the number of bytes read back as a master-receiver */
+ uint32_t : 7;
+ __IO uint32_t WR_BYTE_CNT: 9; /*!< Decide the number of byte to send as a master-transmitter */
+ } WRITE_READ_CNT_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t SCL_CNT; /*!< I2C clk pulse counter */
+
+ struct {
+ __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< the SCL clock high-period count */
+ __IO uint32_t LOW_LEVEL_TICK: 16; /*!< the SCL clock low-period count */
+ } SCL_CNT_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED2;
+
+ union {
+ __I uint32_t INT_STATUS; /*!< I2C interrupt sources */
+
+ struct {
+ __I uint32_t RX_UNDER : 1; /*!< receiver underflow */
+ __I uint32_t RX_OVER : 1; /*!< receiver overflow */
+ __I uint32_t RX_FULL : 1; /*!< receiver is full */
+ __I uint32_t TX_OVER : 1; /*!< transmit overflow */
+ __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */
+ __I uint32_t RD_REQ : 1; /*!< read request */
+ __I uint32_t TX_ABRT : 1; /*!< transmit abortion */
+ __I uint32_t RX_DONE : 1; /*!< receive done */
+ __I uint32_t TX_DONE : 1; /*!< transmit done */
+ __I uint32_t WR_REQ : 1; /*!< write request */
+ } INT_STATUS_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_MASK; /*!< I2C interrupt mask register */
+
+ struct {
+ __I uint32_t RX_UNDER : 1; /*!< receiver underflow */
+ __I uint32_t RX_OVER : 1; /*!< receiver overflow */
+ __I uint32_t RX_FULL : 1; /*!< receiver is full */
+ __I uint32_t TX_OVER : 1; /*!< transmit overflow */
+ __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */
+ __I uint32_t RD_REQ : 1; /*!< read request */
+ __I uint32_t TX_ABRT : 1; /*!< transmit abortion */
+ __I uint32_t RX_DONE : 1; /*!< receive done */
+ __I uint32_t TX_DONE : 1; /*!< transmit done */
+ __I uint32_t WR_REQ : 1; /*!< write request */
+ } INT_MASK_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED3;
+
+ union {
+ __IO uint32_t RX_TL; /*!< I2C receive FIFO threshold */
+
+ struct {
+ __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */
+ } RX_TL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t TX_TL; /*!< I2C transmit FIFO threshold */
+
+ struct {
+ __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */
+ } TX_TL_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t CLR_ALL_INT; /*!< I2C clear all interrupt register */
+
+ struct {
+ __I uint32_t CLEAR : 1; /*!< Read this register to clear all individual interrupts */
+ } CLR_ALL_INT_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t CLR_RX_UNDER; /*!< I2C clear RX_UNDER interrupt */
+
+ struct {
+ __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_UNDER interrupt (bit 19)
+ of the I2C_STATUS register */
+ } CLR_RX_UNDER_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t CLR_RX_OVER; /*!< I2C clear RX_OVER interrupt */
+
+ struct {
+ __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_OVER interrupt (bit 20) of
+ the I2C_STATUS register */
+ } CLR_RX_OVER_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t CLR_TX_OVER; /*!< I2C clear TX_OVER interrupt */
+
+ struct {
+ __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_OVER interrupt (bit 22) of
+ the I2C_STATUS register */
+ } CLR_TX_OVER_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t CLR_RD_REQ; /*!< I2C clear RD_REQ interrupt */
+
+ struct {
+ __I uint32_t CLEAR : 1; /*!< Read this register to clear the RD_REQ interrupt (bit 24) of
+ the I2C_STATUS register */
+ } CLR_RD_REQ_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t CLR_TX_ABRT; /*!< I2C clear TX_ABRT interrupt */
+
+ struct {
+ __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_ABRT interrupts (bit 25 ,
+ bit 18, bit 17, bit 16 and bit 15) of the I2C_STATUS register. */
+ } CLR_TX_ABRT_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t CLR_RX_DONE; /*!< I2C clear RX_DONE interrupt */
+
+ struct {
+ __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_DONE interrupt (bit 26) of
+ the I2C_STATUS register */
+ } CLR_RX_DONE_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ENABLE; /*!< I2C enable register */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< enable device */
+ uint32_t : 30;
+ __IO uint32_t RESET : 1; /*!< TX and RX FIFO are held in an erased state( flushed) and all
+ interrupts deserted */
+ } ENABLE_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t STATUS; /*!< I2C status register */
+
+ struct {
+ __I uint32_t BUSY : 1; /*!< I2C busy Status */
+ __I uint32_t TX_FIFO_NOT_FULL: 1; /*!< transmit FIFO is not full */
+ __I uint32_t TX_FIFO_EMPTY: 1; /*!< transmit FIFO is empty */
+ __I uint32_t RX_FIFO_NOT_EMPTY: 1; /*!< receive FIFO is not empty */
+ __I uint32_t RX_FIFO_FULL: 1; /*!< receive FIFO is full */
+ __I uint32_t EN : 1; /*!< I2C is enabled */
+ __I uint32_t TX_BYTE_W_ACK: 9; /*!< Number of bytes sent to slave with acknowledge during the last
+ write transaction as a master-transmitter only */
+ __I uint32_t ABRT_ADDR_NOACK: 1; /*!< the address sent was not acknowledged by any slave as a master */
+ __I uint32_t ABRT_TX_DATA_NOACK: 1; /*!< the data sent was not acknowledged by any slave as a master */
+ __I uint32_t ABRT_SLAVE_FLUSH_TX_FIFO: 1; /*!< Slave has received a read command and some data exists in the
+ TX FIFO so the slave issues a TX_ABRT interrupt to flush old
+ data in TX FIFO */
+ __I uint32_t ABRT_SLAVE_RD_IN_TX: 1; /*!< When the processor side responds to a slave mode request for
+ data to be transmitted to a remote master and user writes a
+ 1 in CMD (bit 8) of I2C_DATA_CMD register */
+ __I uint32_t RX_UNDER : 1; /*!< receiver is underflow */
+ __I uint32_t RX_OVER : 1; /*!< receiver is overflow */
+ __I uint32_t RX_FULL : 1; /*!< receiver is full */
+ __I uint32_t TX_OVER : 1; /*!< transmit is overflow */
+ __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */
+ __I uint32_t RD_REQ : 1; /*!< read request is received */
+ __I uint32_t TX_ABRT : 1; /*!< transmit is abort */
+ __I uint32_t RX_DONE : 1; /*!< receive is done */
+ __I uint32_t TX_DONE : 1; /*!< transmit is done */
+ __I uint32_t WR_REQ : 1; /*!< write request is received */
+ __I uint32_t MST_RD_FLAG: 1; /*!< Master is executing read command */
+ __I uint32_t MST_WR_FLAG: 1; /*!< Master is executing read command */
+ __I uint32_t MST_WR_RD_FLAG: 1; /*!< Master is executing write-read command */
+ } STATUS_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t TX_FIFO_LEVEL; /*!< I2C transmit FIFO level */
+
+ struct {
+ __I uint32_t LEVEL : 5; /*!< FIFO level */
+ } TX_FIFO_LEVEL_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t RX_FIFO_LEVEL; /*!< I2C receive FIFO level */
+
+ struct {
+ __I uint32_t LEVEL : 5; /*!< FIFO level */
+ } RX_FIFO_LEVEL_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED4;
+
+ union {
+ __O uint32_t SLAVE_NACK; /*!< I2C slave send a data NACK */
+
+ struct {
+ __O uint32_t NACK : 1; /*!< data NACK */
+ } SLAVE_NACK_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED5;
+
+ union {
+ __IO uint32_t SDA_SETUP; /*!< I2C SDA setup timer */
+
+ struct {
+ __IO uint32_t TSETUP : 10; /*!< This counter defines the max value of the following constrains:THD:STA
+ TSU:STO,TSETUP: T / INPUT_CLK_PERIOD */
+ __IO uint32_t TSU_DAT : 8; /*!< This counter defines the constrain of TSU:DAT: 250ns (or 100ns)
+ / INPUT_CLK_PERIOD */
+ } SDA_SETUP_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t TSU_STA_SETUP; /*!< I2C Tsu_sta and Tbuf_free timer */
+
+ struct {
+ __IO uint32_t TBUF : 10; /*!< This counter defines the constrain of bus free interval: Tbuf,
+ Tbuf : Tbus_free / INPUT_CLK_PERIOD */
+ __IO uint32_t TSU_STA : 10; /*!< This counter defines the constrain of Tsu:sta, Tsu:sta : Tsu:sta
+ / INPUT_CLK_PERIOD */
+ __IO uint32_t SDA_FILTER_CNT: 4; /*!< SDA filter count */
+ __IO uint32_t SDA_FILTER_EN: 1; /*!< SDA filter enable bit */
+ __IO uint32_t SCL_FILTER_CNT: 4; /*!< SCL filter count */
+ __IO uint32_t SCL_FILTER_EN: 1; /*!< SCL filter enable bit */
+ } TSU_STA_SETUP_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t CLR_TX_DONE; /*!< I2C clear TX_DONE interrupt */
+
+ struct {
+ __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_DONE interrupt (bit 27) of
+ the I2C_STATUS register */
+ } CLR_TX_DONE_b; /*!< BitSize */
+ };
+} I2C0_Type;
+
+
+/* ================================================================================ */
+/* ================ RTC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief RTC (RTC)
+ */
+
+typedef struct { /*!< RTC Structure */
+
+ union {
+ __IO uint32_t INT_STATUS; /*!< interrupt Register */
+
+ struct {
+ __IO uint32_t SECOND : 1; /*!< 1s interrupt, write 1 clear 0 */
+ __IO uint32_t MICROSECOND: 1; /*!< 1ms interrupt, write 1 clear 0 */
+ } INT_STATUS_b; /*!< BitSize */
+ };
+ __IO uint32_t SECOND; /*!< current seconds of system time */
+
+ union {
+ __IO uint16_t MICROSECOND; /*!< current micro seconds of system time */
+
+ struct {
+ __IO uint16_t MS : 10; /*!< micro seconds */
+ } MICROSECOND_b; /*!< BitSize */
+ };
+} RTC_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIO ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief GPIO (GPIO)
+ */
+
+typedef struct { /*!< GPIO Structure */
+ __I uint32_t GPIO_IN; /*!< GPIO input data */
+ __IO uint32_t GPIO_OUT_UNMASK; /*!< GPIO output mask Register */
+ __IO uint32_t GPIO_OUT_DATA; /*!< GPIO output data register */
+ __IO uint32_t GPIO_OE; /*!< GPIO output driver enable */
+ __IO uint32_t GPIO_INT_MASK; /*!< GPIO input interrupt mask */
+ __IO uint32_t GPIO_INT_STATUS; /*!< GPIO input interrupt status */
+ __IO uint32_t GPIO_INT_RAW; /*!< GPIO input interrupt raw */
+ __IO uint32_t GPIO_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */
+
+ union {
+ __IO uint32_t PWM_OUT_SEL; /*!< Select gpio output from PWM */
+
+ struct {
+ __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */
+ __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */
+ __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */
+ __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */
+ } PWM_OUT_SEL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t PWM_OUT0_LEN; /*!< Pwm channel 0 paramters */
+
+ struct {
+ __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */
+ __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */
+ } PWM_OUT0_LEN_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t PWM_OUT1_LEN; /*!< Pwm channel 1 paramters */
+
+ struct {
+ __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */
+ __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */
+ } PWM_OUT1_LEN_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t PWM_OUT2_LEN; /*!< Pwm channel 2 paramters */
+
+ struct {
+ __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */
+ __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */
+ } PWM_OUT2_LEN_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t PWM_OUT3_LEN; /*!< Pwm channel 3 paramters */
+
+ struct {
+ __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */
+ __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */
+ } PWM_OUT3_LEN_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t PWM_OUT_EN; /*!< Pwm enable */
+
+ struct {
+ __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */
+ __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */
+ __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */
+ __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */
+ } PWM_OUT_EN_b; /*!< BitSize */
+ };
+ __I uint32_t GPIO_H_IN; /*!< GPIO_H input data */
+ __IO uint32_t GPIO_H_OUT_UNMASK; /*!< GPIO_H output unmask Register */
+ __IO uint32_t GPIO_H_OUT_DATA; /*!< GPIO_H output data register */
+ __IO uint32_t GPIO_H_OE; /*!< GPIO_H output driver enable */
+ __IO uint32_t GPIO_H_INT_MASK; /*!< GPIO_H interrupt mask */
+ __IO uint32_t GPIO_H_INT_STATUS; /*!< GPIO_H interrupt status */
+ __IO uint32_t GPIO_H_INT_RAW; /*!< GPIO_H interrupt raw */
+ __IO uint32_t GPIO_H_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */
+ __I uint32_t GPIO_N_IN; /*!< GPIO_N input data */
+ __IO uint32_t GPIO_N_OUT_UNMASK; /*!< GPIO_N output unmask Register */
+ __IO uint32_t GPIO_N_OUT_DATA; /*!< GPIO_N output data register */
+ __IO uint32_t GPIO_N_OE; /*!< GPIO_N output driver enable */
+ __IO uint32_t GPIO_N_INT_MASK; /*!< GPIO_N interrupt mask */
+ __IO uint32_t GPIO_N_INT_STATUS; /*!< GPIO_N interrupt status */
+ __IO uint32_t GPIO_N_INT_RAW; /*!< GPIO_N interrupt raw */
+ __IO uint32_t GPIO_N_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */
+} GPIO_Type;
+
+
+/* ================================================================================ */
+/* ================ NOR_FLASH ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief NOR_FLASH (NOR_FLASH)
+ */
+
+typedef struct { /*!< NOR_FLASH Structure */
+
+ union {
+ __IO uint32_t CTRL0; /*!< control Register 0 */
+
+ struct {
+ __IO uint32_t DIV : 8; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */
+ __IO uint32_t CS_REVALID_INTERVAL: 8; /*!< interval from CS invalid to valid, number of half cycle of SCK */
+ __IO uint32_t RW_BYTE_CNT: 16; /*!< RW byte count (eliminate CMD, ADDRESS, DUMMY in normal state,
+ contains all in transparent state. 0 is unlimited */
+ } CTRL0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTRL1; /*!< control Register 1 */
+
+ struct {
+ __IO uint32_t CMD : 8; /*!< operated command */
+ __IO uint32_t ADDRESS : 24; /*!< RW address */
+ } CTRL1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t TRIGGER; /*!< trigger register */
+
+ struct {
+ __O uint32_t OP_START : 1; /*!< operation start. */
+ __IO uint32_t OP_CLEAN : 1; /*!< operation clean, stop current opration and clean FIFO */
+ __IO uint32_t TRSP_RD_EN : 1; /*!< if a read operation after transparent operation */
+ __IO uint32_t TRSP_EN : 1; /*!< enable transparent operation */
+ } TRIGGER_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t STATUS; /*!< status register */
+
+ struct {
+ __I uint32_t BUSY : 1; /*!< reading or writting */
+ __I uint32_t RD_FIFO_ALMOST_FULL: 1; /*!< read FIFO is almost full */
+ __I uint32_t RD_FIFO_EMPTY: 1; /*!< read FIFO is empty */
+ __I uint32_t RD_FIFO_FULL: 1; /*!< read FIFO is full */
+ __I uint32_t WR_FIFO_ALMOST_EMPTY: 1; /*!< write FIFO is almost empty */
+ __I uint32_t WR_FIFO_FULL: 1; /*!< write FIFO is full */
+ __I uint32_t WR_FIFO_EMPTY: 1; /*!< write FIFO is empty */
+ } STATUS_b; /*!< BitSize */
+ };
+ __IO uint32_t DATA; /*!< data register. lower bits are significant in read and higher
+ bits are significant in writting */
+
+ union {
+ __IO uint32_t BYPASS; /*!< bypass Register, is used for JTAG connecting FLASH directly */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< enable bypass */
+ } BYPASS_b; /*!< BitSize */
+ };
+} NOR_FLASH_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief ADC (ADC)
+ */
+
+typedef struct { /*!< ADC Structure */
+
+ union {
+ __IO uint32_t POWERDOWN_RESET; /*!< power down and reset Register */
+
+ struct {
+ __IO uint32_t RESET_ADC2 : 1; /*!< ADC2, reset, active high */
+ __IO uint32_t RESET_ADC1 : 1; /*!< ADC1, reset, active high */
+ __IO uint32_t POWERDOWN_ADC2: 1; /*!< ADC2, power down, active high */
+ __IO uint32_t POWERDOWN_ADC1: 1; /*!< ADC1, power down, active high */
+ } POWERDOWN_RESET_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG0; /*!< config Register */
+
+ struct {
+ __IO uint32_t VSEN : 3; /*!< ADC-1 VSEN Selection */
+ __IO uint32_t PHASE_CTRL : 2; /*!< ADC-1 and ADC-2 CLK Phase Control */
+ } CFG0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_ADC1; /*!< config ADC1 register */
+
+ struct {
+ __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */
+ __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */
+ __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */
+ __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */
+ } CFG_ADC1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_ADC2; /*!< config ADC1 register */
+
+ struct {
+ __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */
+ __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */
+ __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */
+ __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */
+ } CFG_ADC2_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ADC1_FIFO_CLEAR; /*!< clear adc1 fifo data */
+
+ struct {
+ __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */
+ } ADC1_FIFO_CLEAR_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ADC2_FIFO_CLEAR; /*!< clear adc2 fifo data */
+
+ struct {
+ __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */
+ } ADC2_FIFO_CLEAR_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ALL_ADC_FIFO_CLEAR; /*!< clear adc1 and adc2 fifo data */
+
+ struct {
+ __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */
+ } ALL_ADC_FIFO_CLEAR_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_MASK; /*!< interrupt mask register */
+
+ struct {
+ __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */
+ __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */
+ __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */
+ __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */
+ __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */
+ __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */
+ } INT_MASK_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_RAW; /*!< interrupt raw register */
+
+ struct {
+ __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */
+ __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */
+ __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */
+ __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */
+ __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */
+ __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */
+ } INT_RAW_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_STATUS; /*!< interrupt status register */
+
+ struct {
+ __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */
+ __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */
+ __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */
+ __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */
+ __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */
+ __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */
+ } INT_STATUS_b; /*!< BitSize */
+ };
+ __I uint32_t ADC1_OUT; /*!< ADC-1 Output data (Signed-Magnitude Format) */
+ __I uint32_t ADC2_OUT; /*!< ADC-2 Output data (Signed-Magnitude Format) */
+ __I uint32_t ADC1_OUT_OFFSET_CALIBRATION; /*!< ADC-1 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */
+ __I uint32_t ADC2_OUT_OFFSET_CALIBRATION; /*!< ADC-2 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */
+ __I uint32_t ADC1_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-1 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */
+ __I uint32_t ADC2_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-2 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */
+ __I uint32_t ADC1_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-1 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */
+ __I uint32_t ADC2_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-2 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */
+
+ union {
+ __I uint32_t EOC; /*!< Conversion End Indicator */
+
+ struct {
+ __I uint32_t ADC2_EOC_GAIN: 1; /*!< ADC2 EOC_GAIN signal, conversion is done */
+ __I uint32_t ADC2_EOC_OFF: 1; /*!< ADC2 EOC_OFF signal, conversion is done */
+ __I uint32_t ADC2_EOC : 1; /*!< ADC2 EOC signal, conversion is done */
+ __I uint32_t ADC1_EOC_GAIN: 1; /*!< ADC1 EOC_GAIN signal, conversion is done */
+ __I uint32_t ADC1_EOC_OFF: 1; /*!< ADC1 EOC_OFF signal, conversion is done */
+ __I uint32_t ADC1_EOC : 1; /*!< ADC1 EOC signal, conversion is done */
+ } EOC_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t BUSY; /*!< ADC is busy */
+
+ struct {
+ __I uint32_t ADC1_BUSY : 1; /*!< ADC1 is busy */
+ __I uint32_t ADC2_BUSY : 1; /*!< ADC2 is busy */
+ } BUSY_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint32_t ADC1_START; /*!< ADC1 startup enable */
+
+ struct {
+ __O uint32_t EN : 1; /*!< start */
+ } ADC1_START_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint32_t ADC1_STOP; /*!< ADC1 stop enable */
+
+ struct {
+ __O uint32_t EN : 1; /*!< start */
+ } ADC1_STOP_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint16_t ADC1_FIFO_READ; /*!< ADC1 FIFO read data */
+
+ struct {
+ __O uint16_t DATA : 12; /*!< data */
+ __O uint16_t CHANNEL : 4; /*!< channel number */
+ } ADC1_FIFO_READ_b; /*!< BitSize */
+ };
+ __I uint16_t RESERVED0;
+
+ union {
+ __O uint32_t ADC2_START; /*!< ADC2 startup enable, only for single-conversion */
+
+ struct {
+ __O uint32_t EN : 1; /*!< start */
+ } ADC2_START_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint32_t ADC2_STOP; /*!< ADC1 stop enable, only for single-conversion */
+
+ struct {
+ __O uint32_t EN : 1; /*!< start */
+ } ADC2_STOP_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint16_t ADC2_FIFO_READ; /*!< ADC2 FIFO read data */
+
+ struct {
+ __O uint16_t DATA : 12; /*!< data */
+ __O uint16_t CHANNEL : 4; /*!< channel number */
+ } ADC2_FIFO_READ_b; /*!< BitSize */
+ };
+ __I uint16_t RESERVED1;
+
+ union {
+ __O uint32_t ALL_ADC_START; /*!< all ADCs start */
+
+ struct {
+ __O uint32_t EN : 1; /*!< start */
+ } ALL_ADC_START_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint32_t ALL_ADC_STOP; /*!< all ADCs stop */
+
+ struct {
+ __O uint32_t EN : 1; /*!< start */
+ } ALL_ADC_STOP_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t ALL_ADC_FIFO_READ; /*!< all ADCs FIFO read data */
+
+ struct {
+ __I uint32_t ADC1_DATA : 12; /*!< ADC1 data */
+ __I uint32_t ADC1_CHANNEL: 4; /*!< ADC1 channel number */
+ __I uint32_t ADC2_DATA : 12; /*!< ADC2 data */
+ __I uint32_t ADC2_CHANNEL: 4; /*!< ADC2 channel number */
+ } ALL_ADC_FIFO_READ_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t STATUS; /*!< status register */
+
+ struct {
+ __I uint32_t ADC1_READ_EMPTY: 1; /*!< ADC1 read empty */
+ __I uint32_t ADC2_READ_EMPTY: 1; /*!< ADC2 read empty */
+ __I uint32_t ADC1_READ_ALMOST_EMPTY: 1; /*!< ADC1 read almost empty */
+ __I uint32_t ADC2_READ_ALMOST_EMPTY: 1; /*!< ADC2 read almost empty */
+ __I uint32_t ADC1_WRITE_FULL: 1; /*!< ADC1 write full */
+ __I uint32_t ADC2_WRITE_FULL: 1; /*!< ADC2 write full */
+ __I uint32_t ADC1_WRITE_ALMOST_FULL: 1; /*!< ADC1 write almost full */
+ __I uint32_t ADC2_WRITE_ALMOST_FULL: 1; /*!< ADC2 write almost full */
+ } STATUS_b; /*!< BitSize */
+ };
+} ADC_Type;
+
+
+/* ================================================================================ */
+/* ================ EFUSE ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief EFUSE (EFUSE)
+ */
+
+typedef struct { /*!< EFUSE Structure */
+
+ union {
+ __IO uint32_t USER_CTRL_LOW; /*!< low user region control */
+
+ struct {
+ __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */
+ __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */
+ __I uint32_t BUSY : 1; /*!< reading or writting */
+ __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */
+ __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */
+ __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */
+ __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */
+ __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */
+ } USER_CTRL_LOW_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t TIMING_0; /*!< timing 0 */
+
+ struct {
+ __IO uint32_t TPRS : 7; /*!< TPRS */
+ __IO uint32_t TESR : 2; /*!< TESR */
+ __IO uint32_t TRC : 4; /*!< TRC */
+ __IO uint32_t TRPW : 3; /*!< TRPW */
+ __IO uint32_t TRAH : 2; /*!< TRAH */
+ __IO uint32_t TRAC : 3; /*!< TRAC */
+ uint32_t : 6;
+ __IO uint32_t TPWPH : 5; /*!< TPWPH[6:2] */
+ } TIMING_0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t TIMING_1; /*!< timing 1 */
+
+ struct {
+ __IO uint32_t TPWPS : 7; /*!< TPWPS */
+ __IO uint32_t TEPS : 4; /*!< TEPS */
+ __IO uint32_t TPP : 11; /*!< TPP */
+ __IO uint32_t TPIT : 8; /*!< TPIT */
+ __IO uint32_t TPWPH : 2; /*!< TPWPS[1:0] */
+ } TIMING_1_b; /*!< BitSize */
+ };
+ __IO uint32_t USER_DATA0_LOW; /*!< user data [31:0] */
+ __IO uint32_t USER_DATA1_LOW; /*!< user data [63:32] */
+ __IO uint32_t USER_DATA2_LOW; /*!< user data [95:64] */
+ __IO uint32_t USER_DATA3_LOW; /*!< user data [127:96] */
+
+ union {
+ __IO uint32_t USER_DATA4_LOW; /*!< crc and lock bit */
+
+ struct {
+ __IO uint32_t LOCK : 1; /*!< write protection if true */
+ uint32_t : 23;
+ __IO uint32_t CRC : 8; /*!< CRC */
+ } USER_DATA4_LOW_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED0[3];
+
+ union {
+ __IO uint32_t USER_CTRL_HI; /*!< high user region control */
+
+ struct {
+ __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */
+ __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */
+ __I uint32_t BUSY : 1; /*!< reading or writting */
+ __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */
+ __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */
+ __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */
+ __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */
+ __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */
+ } USER_CTRL_HI_b; /*!< BitSize */
+ };
+ __IO uint32_t USER_DATA0_HI; /*!< user data [159:128] */
+ __IO uint32_t USER_DATA1_HI; /*!< user data [191:160] */
+ __IO uint32_t USER_DATA2_HI; /*!< user data [223:192] */
+ __IO uint32_t USER_DATA3_HI; /*!< user data [255:224] */
+
+ union {
+ __IO uint32_t USER_DATA4_HI; /*!< crc and lock bit */
+
+ struct {
+ __IO uint32_t LOCK : 1; /*!< write protection if true */
+ uint32_t : 23;
+ __IO uint32_t CRC : 8; /*!< CRC */
+ } USER_DATA4_HI_b; /*!< BitSize */
+ };
+} EFUSE_Type;
+
+
+/* ================================================================================ */
+/* ================ CAN0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief CAN 0 (CAN0)
+ */
+
+typedef struct { /*!< CAN0 Structure */
+
+ union {
+ __IO uint8_t MODE; /*!< mode Register */
+
+ struct {
+ __IO uint8_t RM : 1; /*!< reset mode if 1 or operation mode */
+ __IO uint8_t LOM : 1; /*!< Listen only mode */
+ __IO uint8_t STM : 1; /*!< self test mode */
+ __IO uint8_t AFM : 1; /*!< acceptance filter mode. Single filter if 1, dual filter if 0 */
+ __IO uint8_t SM : 1; /*!< sleep mode */
+ } MODE_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED0[3];
+
+ union {
+ __O uint8_t CMD; /*!< command Register */
+
+ struct {
+ __O uint8_t TR : 1; /*!< Set to 1 when a message is to be transmitted */
+ __O uint8_t AT : 1; /*!< Set to 1 to cancel the next transmission request */
+ __O uint8_t RRB : 1; /*!< Set to 1 to release the Receive Buffer */
+ __O uint8_t CDO : 1; /*!< Set to 1 to clear the data overrun condition signaled by the
+ Data Overrun Status bit (SR.1). */
+ __O uint8_t SSR : 1; /*!< Set to 1 when a message is to be transmitted and received simultaneously */
+ } CMD_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED1[3];
+
+ union {
+ __I uint8_t STATUS; /*!< status Register */
+
+ struct {
+ __I uint8_t RBNE : 1; /*!< Receive Buffer not empty */
+ __I uint8_t DO : 1; /*!< Data Overrun Status */
+ __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */
+ __I uint8_t TC : 1; /*!< Transmission complete */
+ __I uint8_t RXING : 1; /*!< receiving the data */
+ __I uint8_t TXING : 1; /*!< transmitting the data */
+ __I uint8_t ERR : 1; /*!< At least one of the error counters is more than Error Warning
+ Limit Register */
+ __I uint8_t BUS_OFF : 1; /*!< in 'Bus Off' state */
+ } STATUS_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED2[3];
+
+ union {
+ __I uint8_t INT; /*!< interrupt Register */
+
+ struct {
+ __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */
+ __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */
+ __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status
+ or Error Status bits (SR.7,SR.6) */
+ __I uint8_t DO : 1; /*!< Data Overrun Status */
+ __I uint8_t WAKEUP : 1; /*!< wake-up */
+ __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being
+ in error passive state or when at least one error counter exceeds
+ the protocol-defined level of 127 */
+ __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */
+ __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */
+ } INT_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED3[3];
+
+ union {
+ __IO uint8_t INT_EN; /*!< interrupt enabled Register */
+
+ struct {
+ __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */
+ __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */
+ __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status
+ or Error Status bits (SR.7,SR.6) */
+ __I uint8_t DO : 1; /*!< Data Overrun Status */
+ __I uint8_t WAKEUP : 1; /*!< wake-up */
+ __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being
+ in error passive state or when at least one error counter exceeds
+ the protocol-defined level of 127 */
+ __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */
+ __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */
+ } INT_EN_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED4[7];
+
+ union {
+ __IO uint8_t BTR0; /*!< Bus Timing 0 */
+
+ struct {
+ __IO uint8_t BRP : 6; /*!< TQ =2 x Txtal1 x (32 x BRP.5 + 16 x BRP.4 + 8 x BRP.3 + 4 x
+ BRP.2 + 2 x BRP.1 + BRP.0 + 1) */
+ __IO uint8_t SJW : 2; /*!< the maximum number of time quanta of sync segment */
+ } BTR0_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED5[3];
+
+ union {
+ __IO uint8_t BTR1; /*!< Bus Timing 1 */
+
+ struct {
+ __IO uint8_t TSEG1 : 4; /*!< the maximum number of time quanta of propagation and 1st phase
+ segment */
+ __IO uint8_t TSEG2 : 3; /*!< the maximum number of time quanta of 2nd phase segment */
+ __IO uint8_t SAM : 1; /*!< sample times. Sample 3 times if 1, once if 0 */
+ } BTR1_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED6[3];
+
+ union {
+ __IO uint8_t OCR; /*!< Output Control Register */
+
+ struct {
+ __IO uint8_t MODE : 2; /*!< output control mode */
+ } OCR_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED7[11];
+
+ union {
+ __I uint8_t ALC; /*!< Arbitration Lost Capture */
+
+ struct {
+ __I uint8_t BIT : 5; /*!< the current position of the Bit Processor when bus arbitration
+ lost, 1st bit (ID.28) if 0 */
+ } ALC_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED8[3];
+
+ union {
+ __I uint8_t ECC; /*!< Error Code Capture */
+
+ struct {
+ __I uint8_t SEGMENT : 5; /*!< segment code */
+ __I uint8_t DIRECTION : 1; /*!< If 1, the error occurred during reception. If 0, the error occurred
+ during transmission */
+ __I uint8_t ERR : 2; /*!< error code */
+ } ECC_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED9[3];
+ __IO uint8_t EWLR; /*!< Error Warning Limit */
+ __I uint8_t RESERVED10[3];
+ __IO uint8_t RXERR; /*!< Receive Error Counter */
+ __I uint8_t RESERVED11[3];
+ __IO uint8_t TXERR; /*!< Transmit Error Counter */
+ __I uint8_t RESERVED12[3];
+
+ union {
+ __IO uint8_t FI_OR_ACR0; /*!< Transmit Frame Information if writting or Receive Frame Information
+ if reading, ACR[0] if reset mode */
+
+ struct {
+ __IO uint8_t DLC : 4; /*!< byte number in the data */
+ uint8_t : 2;
+ __IO uint8_t RTR : 1; /*!< 1 indicates a remote frame; 0 indicates a data frame */
+ __IO uint8_t FF : 1; /*!< 1 selects Extended Frame Format (EFF); 0 selects Standard Frame
+ Format (SFF) */
+ } FI_OR_ACR0_b; /*!< BitSize */
+ };
+ __I uint8_t RESERVED13[3];
+ __IO uint8_t DI0_OR_ACR1; /*!< Transmit data Information if writting or Receive data Information
+ if reading, ACR[1] if reset mode */
+ __I uint8_t RESERVED14[3];
+ __IO uint8_t DI1_OR_ACR2; /*!< Transmit data Information if writting or Receive data Information
+ if reading, ACR[2] if reset mode */
+ __I uint8_t RESERVED15[3];
+ __IO uint8_t DI2_OR_ACR3; /*!< Transmit data Information if writting or Receive data Information
+ if reading, ACR[3] if reset mode */
+ __I uint8_t RESERVED16[3];
+ __IO uint8_t DI3_OR_AMR0; /*!< Transmit data Information if writting or Receive data Information
+ if reading, AMR[0] if reset mode */
+ __I uint8_t RESERVED17[3];
+ __IO uint8_t DI4_OR_AMR1; /*!< Transmit data Information if writting or Receive data Information
+ if reading, AMR[1] if reset mode */
+ __I uint8_t RESERVED18[3];
+ __IO uint8_t DI5_OR_AMR2; /*!< Transmit data Information if writting or Receive data Information
+ if reading, AMR[2] if reset mode */
+ __I uint8_t RESERVED19[3];
+ __IO uint8_t DI6_OR_AMR3; /*!< Transmit data Information if writting or Receive data Information
+ if reading, AMR[3] if reset mode */
+ __I uint8_t RESERVED20[3];
+ __IO uint8_t DI7; /*!< Transmit data Information if writting or Receive data Information
+ if reading */
+ __I uint8_t RESERVED21[3];
+ __IO uint8_t DI8; /*!< Transmit data Information if writting or Receive data Information
+ if reading */
+ __I uint8_t RESERVED22[3];
+ __IO uint8_t DI9; /*!< Transmit data Information if writting or Receive data Information
+ if reading */
+ __I uint8_t RESERVED23[3];
+ __IO uint8_t DI10; /*!< Transmit data Information if writting or Receive data Information
+ if reading */
+ __I uint8_t RESERVED24[3];
+ __IO uint8_t DI11; /*!< Transmit data Information if writting or Receive data Information
+ if reading */
+ __I uint8_t RESERVED25[3];
+ __IO uint8_t RMC; /*!< Receive Message Counter */
+ __I uint8_t RESERVED26[7];
+
+ union {
+ __IO uint8_t CDR; /*!< Clock Divider Register */
+
+ struct {
+ __IO uint8_t DIVIDER : 3; /*!< divider of XTAL1 */
+ __IO uint8_t OFF : 1; /*!< disable XTAL1 */
+ } CDR_b; /*!< BitSize */
+ };
+} CAN0_Type;
+
+
+/* ================================================================================ */
+/* ================ DMA ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief DMA (DMA)
+ */
+
+typedef struct { /*!< DMA Structure */
+ __IO uint32_t SAR0; /*!< Current Source Address of DMA transfer */
+ __I uint32_t RESERVED0;
+ __IO uint32_t DAR0; /*!< Current Destination Address of DMA transfer */
+ __I uint32_t RESERVED1;
+
+ union {
+ __IO uint32_t LLP0; /*!< Linked List Pointer Register for Channel */
+
+ struct {
+ __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that
+ stores the next linked list item resides. */
+ __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is
+ enabled */
+ } LLP0_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED2;
+
+ union {
+ __IO uint32_t CTL_LOW0; /*!< Lower 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */
+ __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */
+ __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */
+ __IO uint32_t DINC : 2; /*!< Destination Address Increment */
+ __IO uint32_t SINC : 2; /*!< Source Address Increment */
+ __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */
+ __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */
+ __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */
+ __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */
+ uint32_t : 1;
+ __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */
+ __IO uint32_t DMS : 2; /*!< Destination Master Select */
+ __IO uint32_t SMS : 2; /*!< Source Master Select */
+ __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */
+ __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */
+ } CTL_LOW0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTL_HI0; /*!< Higher 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform
+ for every block transfer */
+ __IO uint32_t DONE : 1; /*!< a block transfer is complete */
+ } CTL_HI0_b; /*!< BitSize */
+ };
+ __IO uint32_t SSTAT0; /*!< Source Status Register for Channel */
+ __I uint32_t RESERVED3;
+ __IO uint32_t DSTAT0; /*!< Destination Status Register for Channel */
+ __I uint32_t RESERVED4;
+ __IO uint32_t SSTATAR0; /*!< Source Status Address Register for Channel */
+ __I uint32_t RESERVED5;
+ __IO uint32_t DSTATAR0; /*!< Destination Status Address Register for Channel */
+ __I uint32_t RESERVED6;
+
+ union {
+ __IO uint32_t CFG_LOW0; /*!< Lower 32-bit Configuration Register for Channel */
+
+ struct {
+ uint32_t : 5;
+ __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */
+ __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit
+ is cleared. */
+ __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */
+ __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */
+ __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */
+ __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */
+ __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */
+ __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */
+ __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */
+ __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */
+ __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */
+ __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */
+ } CFG_LOW0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_HI0; /*!< Higher 32-bit Configuration Register for Channel */
+
+ struct {
+ __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination
+ Peripheral is the flow controller. */
+ __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before
+ a burst transaction request is serviced. */
+ __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the
+ HPROT[3:1] master interface signals */
+ __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ } CFG_HI0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t SGR0; /*!< Source Gather Register for Channel */
+
+ struct {
+ __IO uint32_t SGI : 20; /*!< Source gather interval */
+ __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */
+ } SGR0_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED7;
+
+ union {
+ __IO uint32_t DSR0; /*!< Destination Scatter Register for Channel */
+
+ struct {
+ __IO uint32_t DSI : 20; /*!< Destination scatter interval */
+ __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of
+ CTLx.DST_TR_WIDTH */
+ } DSR0_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED8;
+ __IO uint32_t SAR1; /*!< Current Source Address of DMA transfer */
+ __I uint32_t RESERVED9;
+ __IO uint32_t DAR1; /*!< Current Destination Address of DMA transfer */
+ __I uint32_t RESERVED10;
+
+ union {
+ __IO uint32_t LLP1; /*!< Linked List Pointer Register for Channel */
+
+ struct {
+ __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that
+ stores the next linked list item resides. */
+ __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is
+ enabled */
+ } LLP1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED11;
+
+ union {
+ __IO uint32_t CTL_LOW1; /*!< Lower 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */
+ __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */
+ __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */
+ __IO uint32_t DINC : 2; /*!< Destination Address Increment */
+ __IO uint32_t SINC : 2; /*!< Source Address Increment */
+ __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */
+ __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */
+ __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */
+ __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */
+ uint32_t : 1;
+ __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */
+ __IO uint32_t DMS : 2; /*!< Destination Master Select */
+ __IO uint32_t SMS : 2; /*!< Source Master Select */
+ __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */
+ __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */
+ } CTL_LOW1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTL_HI1; /*!< Higher 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform
+ for every block transfer */
+ __IO uint32_t DONE : 1; /*!< a block transfer is complete */
+ } CTL_HI1_b; /*!< BitSize */
+ };
+ __IO uint32_t SSTAT1; /*!< Source Status Register for Channel */
+ __I uint32_t RESERVED12;
+ __IO uint32_t DSTAT1; /*!< Destination Status Register for Channel */
+ __I uint32_t RESERVED13;
+ __IO uint32_t SSTATAR1; /*!< Source Status Address Register for Channel */
+ __I uint32_t RESERVED14;
+ __IO uint32_t DSTATAR1; /*!< Destination Status Address Register for Channel */
+ __I uint32_t RESERVED15;
+
+ union {
+ __IO uint32_t CFG_LOW1; /*!< Lower 32-bit Configuration Register for Channel */
+
+ struct {
+ uint32_t : 5;
+ __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */
+ __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit
+ is cleared. */
+ __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */
+ __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */
+ __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */
+ __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */
+ __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */
+ __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */
+ __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */
+ __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */
+ __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */
+ __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */
+ } CFG_LOW1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_HI1; /*!< Higher 32-bit Configuration Register for Channel */
+
+ struct {
+ __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination
+ Peripheral is the flow controller. */
+ __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before
+ a burst transaction request is serviced. */
+ __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the
+ HPROT[3:1] master interface signals */
+ __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ } CFG_HI1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t SGR1; /*!< Source Gather Register for Channel */
+
+ struct {
+ __IO uint32_t SGI : 20; /*!< Source gather interval */
+ __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */
+ } SGR1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED16;
+
+ union {
+ __IO uint32_t DSR1; /*!< Destination Scatter Register for Channel */
+
+ struct {
+ __IO uint32_t DSI : 20; /*!< Destination scatter interval */
+ __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of
+ CTLx.DST_TR_WIDTH */
+ } DSR1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED17;
+ __IO uint32_t SAR2; /*!< Current Source Address of DMA transfer */
+ __I uint32_t RESERVED18;
+ __IO uint32_t DAR2; /*!< Current Destination Address of DMA transfer */
+ __I uint32_t RESERVED19;
+
+ union {
+ __IO uint32_t LLP2; /*!< Linked List Pointer Register for Channel */
+
+ struct {
+ __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that
+ stores the next linked list item resides. */
+ __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is
+ enabled */
+ } LLP2_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED20;
+
+ union {
+ __IO uint32_t CTL_LOW2; /*!< Lower 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */
+ __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */
+ __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */
+ __IO uint32_t DINC : 2; /*!< Destination Address Increment */
+ __IO uint32_t SINC : 2; /*!< Source Address Increment */
+ __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */
+ __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */
+ __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */
+ __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */
+ uint32_t : 1;
+ __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */
+ __IO uint32_t DMS : 2; /*!< Destination Master Select */
+ __IO uint32_t SMS : 2; /*!< Source Master Select */
+ __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */
+ __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */
+ } CTL_LOW2_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTL_HI2; /*!< Higher 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform
+ for every block transfer */
+ __IO uint32_t DONE : 1; /*!< a block transfer is complete */
+ } CTL_HI2_b; /*!< BitSize */
+ };
+ __IO uint32_t SSTAT2; /*!< Source Status Register for Channel */
+ __I uint32_t RESERVED21;
+ __IO uint32_t DSTAT2; /*!< Destination Status Register for Channel */
+ __I uint32_t RESERVED22;
+ __IO uint32_t SSTATAR2; /*!< Source Status Address Register for Channel */
+ __I uint32_t RESERVED23;
+ __IO uint32_t DSTATAR2; /*!< Destination Status Address Register for Channel */
+ __I uint32_t RESERVED24;
+
+ union {
+ __IO uint32_t CFG_LOW2; /*!< Lower 32-bit Configuration Register for Channel */
+
+ struct {
+ uint32_t : 5;
+ __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */
+ __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit
+ is cleared. */
+ __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */
+ __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */
+ __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */
+ __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */
+ __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */
+ __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */
+ __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */
+ __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */
+ __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */
+ __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */
+ } CFG_LOW2_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_HI2; /*!< Higher 32-bit Configuration Register for Channel */
+
+ struct {
+ __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination
+ Peripheral is the flow controller. */
+ __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before
+ a burst transaction request is serviced. */
+ __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the
+ HPROT[3:1] master interface signals */
+ __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ } CFG_HI2_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t SGR2; /*!< Source Gather Register for Channel */
+
+ struct {
+ __IO uint32_t SGI : 20; /*!< Source gather interval */
+ __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */
+ } SGR2_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED25;
+
+ union {
+ __IO uint32_t DSR2; /*!< Destination Scatter Register for Channel */
+
+ struct {
+ __IO uint32_t DSI : 20; /*!< Destination scatter interval */
+ __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of
+ CTLx.DST_TR_WIDTH */
+ } DSR2_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED26;
+ __IO uint32_t SAR3; /*!< Current Source Address of DMA transfer */
+ __I uint32_t RESERVED27;
+ __IO uint32_t DAR3; /*!< Current Destination Address of DMA transfer */
+ __I uint32_t RESERVED28;
+
+ union {
+ __IO uint32_t LLP3; /*!< Linked List Pointer Register for Channel */
+
+ struct {
+ __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that
+ stores the next linked list item resides. */
+ __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is
+ enabled */
+ } LLP3_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED29;
+
+ union {
+ __IO uint32_t CTL_LOW3; /*!< Lower 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */
+ __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */
+ __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */
+ __IO uint32_t DINC : 2; /*!< Destination Address Increment */
+ __IO uint32_t SINC : 2; /*!< Source Address Increment */
+ __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */
+ __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */
+ __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */
+ __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */
+ uint32_t : 1;
+ __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */
+ __IO uint32_t DMS : 2; /*!< Destination Master Select */
+ __IO uint32_t SMS : 2; /*!< Source Master Select */
+ __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */
+ __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */
+ } CTL_LOW3_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTL_HI3; /*!< Higher 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform
+ for every block transfer */
+ __IO uint32_t DONE : 1; /*!< a block transfer is complete */
+ } CTL_HI3_b; /*!< BitSize */
+ };
+ __IO uint32_t SSTAT3; /*!< Source Status Register for Channel */
+ __I uint32_t RESERVED30;
+ __IO uint32_t DSTAT3; /*!< Destination Status Register for Channel */
+ __I uint32_t RESERVED31;
+ __IO uint32_t SSTATAR3; /*!< Source Status Address Register for Channel */
+ __I uint32_t RESERVED32;
+ __IO uint32_t DSTATAR3; /*!< Destination Status Address Register for Channel */
+ __I uint32_t RESERVED33;
+
+ union {
+ __IO uint32_t CFG_LOW3; /*!< Lower 32-bit Configuration Register for Channel */
+
+ struct {
+ uint32_t : 5;
+ __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */
+ __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit
+ is cleared. */
+ __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */
+ __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */
+ __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */
+ __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */
+ __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */
+ __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */
+ __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */
+ __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */
+ __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */
+ __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */
+ } CFG_LOW3_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_HI3; /*!< Higher 32-bit Configuration Register for Channel */
+
+ struct {
+ __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination
+ Peripheral is the flow controller. */
+ __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before
+ a burst transaction request is serviced. */
+ __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the
+ HPROT[3:1] master interface signals */
+ __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ } CFG_HI3_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t SGR3; /*!< Source Gather Register for Channel */
+
+ struct {
+ __IO uint32_t SGI : 20; /*!< Source gather interval */
+ __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */
+ } SGR3_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED34;
+
+ union {
+ __IO uint32_t DSR3; /*!< Destination Scatter Register for Channel */
+
+ struct {
+ __IO uint32_t DSI : 20; /*!< Destination scatter interval */
+ __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of
+ CTLx.DST_TR_WIDTH */
+ } DSR3_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED35;
+ __IO uint32_t SAR4; /*!< Current Source Address of DMA transfer */
+ __I uint32_t RESERVED36;
+ __IO uint32_t DAR4; /*!< Current Destination Address of DMA transfer */
+ __I uint32_t RESERVED37;
+
+ union {
+ __IO uint32_t LLP4; /*!< Linked List Pointer Register for Channel */
+
+ struct {
+ __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that
+ stores the next linked list item resides. */
+ __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is
+ enabled */
+ } LLP4_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED38;
+
+ union {
+ __IO uint32_t CTL_LOW4; /*!< Lower 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */
+ __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */
+ __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */
+ __IO uint32_t DINC : 2; /*!< Destination Address Increment */
+ __IO uint32_t SINC : 2; /*!< Source Address Increment */
+ __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */
+ __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */
+ __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */
+ __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */
+ uint32_t : 1;
+ __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */
+ __IO uint32_t DMS : 2; /*!< Destination Master Select */
+ __IO uint32_t SMS : 2; /*!< Source Master Select */
+ __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */
+ __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */
+ } CTL_LOW4_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTL_HI4; /*!< Higher 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform
+ for every block transfer */
+ __IO uint32_t DONE : 1; /*!< a block transfer is complete */
+ } CTL_HI4_b; /*!< BitSize */
+ };
+ __IO uint32_t SSTAT4; /*!< Source Status Register for Channel */
+ __I uint32_t RESERVED39;
+ __IO uint32_t DSTAT4; /*!< Destination Status Register for Channel */
+ __I uint32_t RESERVED40;
+ __IO uint32_t SSTATAR4; /*!< Source Status Address Register for Channel */
+ __I uint32_t RESERVED41;
+ __IO uint32_t DSTATAR4; /*!< Destination Status Address Register for Channel */
+ __I uint32_t RESERVED42;
+
+ union {
+ __IO uint32_t CFG_LOW4; /*!< Lower 32-bit Configuration Register for Channel */
+
+ struct {
+ uint32_t : 5;
+ __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */
+ __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit
+ is cleared. */
+ __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */
+ __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */
+ __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */
+ __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */
+ __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */
+ __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */
+ __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */
+ __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */
+ __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */
+ __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */
+ } CFG_LOW4_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_HI4; /*!< Higher 32-bit Configuration Register for Channel */
+
+ struct {
+ __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination
+ Peripheral is the flow controller. */
+ __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before
+ a burst transaction request is serviced. */
+ __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the
+ HPROT[3:1] master interface signals */
+ __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ } CFG_HI4_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t SGR4; /*!< Source Gather Register for Channel */
+
+ struct {
+ __IO uint32_t SGI : 20; /*!< Source gather interval */
+ __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */
+ } SGR4_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED43;
+
+ union {
+ __IO uint32_t DSR4; /*!< Destination Scatter Register for Channel */
+
+ struct {
+ __IO uint32_t DSI : 20; /*!< Destination scatter interval */
+ __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of
+ CTLx.DST_TR_WIDTH */
+ } DSR4_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED44;
+ __IO uint32_t SAR5; /*!< Current Source Address of DMA transfer */
+ __I uint32_t RESERVED45;
+ __IO uint32_t DAR5; /*!< Current Destination Address of DMA transfer */
+ __I uint32_t RESERVED46;
+
+ union {
+ __IO uint32_t LLP5; /*!< Linked List Pointer Register for Channel */
+
+ struct {
+ __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that
+ stores the next linked list item resides. */
+ __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is
+ enabled */
+ } LLP5_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED47;
+
+ union {
+ __IO uint32_t CTL_LOW5; /*!< Lower 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */
+ __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */
+ __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */
+ __IO uint32_t DINC : 2; /*!< Destination Address Increment */
+ __IO uint32_t SINC : 2; /*!< Source Address Increment */
+ __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */
+ __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */
+ __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */
+ __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */
+ uint32_t : 1;
+ __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */
+ __IO uint32_t DMS : 2; /*!< Destination Master Select */
+ __IO uint32_t SMS : 2; /*!< Source Master Select */
+ __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */
+ __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */
+ } CTL_LOW5_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTL_HI5; /*!< Higher 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform
+ for every block transfer */
+ __IO uint32_t DONE : 1; /*!< a block transfer is complete */
+ } CTL_HI5_b; /*!< BitSize */
+ };
+ __IO uint32_t SSTAT5; /*!< Source Status Register for Channel */
+ __I uint32_t RESERVED48;
+ __IO uint32_t DSTAT5; /*!< Destination Status Register for Channel */
+ __I uint32_t RESERVED49;
+ __IO uint32_t SSTATAR5; /*!< Source Status Address Register for Channel */
+ __I uint32_t RESERVED50;
+ __IO uint32_t DSTATAR5; /*!< Destination Status Address Register for Channel */
+ __I uint32_t RESERVED51;
+
+ union {
+ __IO uint32_t CFG_LOW5; /*!< Lower 32-bit Configuration Register for Channel */
+
+ struct {
+ uint32_t : 5;
+ __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */
+ __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit
+ is cleared. */
+ __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */
+ __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */
+ __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */
+ __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */
+ __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */
+ __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */
+ __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */
+ __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */
+ __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */
+ __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */
+ } CFG_LOW5_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_HI5; /*!< Higher 32-bit Configuration Register for Channel */
+
+ struct {
+ __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination
+ Peripheral is the flow controller. */
+ __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before
+ a burst transaction request is serviced. */
+ __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the
+ HPROT[3:1] master interface signals */
+ __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ } CFG_HI5_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t SGR5; /*!< Source Gather Register for Channel */
+
+ struct {
+ __IO uint32_t SGI : 20; /*!< Source gather interval */
+ __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */
+ } SGR5_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED52;
+
+ union {
+ __IO uint32_t DSR5; /*!< Destination Scatter Register for Channel */
+
+ struct {
+ __IO uint32_t DSI : 20; /*!< Destination scatter interval */
+ __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of
+ CTLx.DST_TR_WIDTH */
+ } DSR5_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED53;
+ __IO uint32_t SAR6; /*!< Current Source Address of DMA transfer */
+ __I uint32_t RESERVED54;
+ __IO uint32_t DAR6; /*!< Current Destination Address of DMA transfer */
+ __I uint32_t RESERVED55;
+
+ union {
+ __IO uint32_t LLP6; /*!< Linked List Pointer Register for Channel */
+
+ struct {
+ __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that
+ stores the next linked list item resides. */
+ __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is
+ enabled */
+ } LLP6_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED56;
+
+ union {
+ __IO uint32_t CTL_LOW6; /*!< Lower 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */
+ __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */
+ __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */
+ __IO uint32_t DINC : 2; /*!< Destination Address Increment */
+ __IO uint32_t SINC : 2; /*!< Source Address Increment */
+ __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */
+ __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */
+ __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */
+ __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */
+ uint32_t : 1;
+ __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */
+ __IO uint32_t DMS : 2; /*!< Destination Master Select */
+ __IO uint32_t SMS : 2; /*!< Source Master Select */
+ __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */
+ __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */
+ } CTL_LOW6_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTL_HI6; /*!< Higher 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform
+ for every block transfer */
+ __IO uint32_t DONE : 1; /*!< a block transfer is complete */
+ } CTL_HI6_b; /*!< BitSize */
+ };
+ __IO uint32_t SSTAT6; /*!< Source Status Register for Channel */
+ __I uint32_t RESERVED57;
+ __IO uint32_t DSTAT6; /*!< Destination Status Register for Channel */
+ __I uint32_t RESERVED58;
+ __IO uint32_t SSTATAR6; /*!< Source Status Address Register for Channel */
+ __I uint32_t RESERVED59;
+ __IO uint32_t DSTATAR6; /*!< Destination Status Address Register for Channel */
+ __I uint32_t RESERVED60;
+
+ union {
+ __IO uint32_t CFG_LOW6; /*!< Lower 32-bit Configuration Register for Channel */
+
+ struct {
+ uint32_t : 5;
+ __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */
+ __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit
+ is cleared. */
+ __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */
+ __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */
+ __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */
+ __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */
+ __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */
+ __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */
+ __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */
+ __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */
+ __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */
+ __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */
+ } CFG_LOW6_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_HI6; /*!< Higher 32-bit Configuration Register for Channel */
+
+ struct {
+ __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination
+ Peripheral is the flow controller. */
+ __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before
+ a burst transaction request is serviced. */
+ __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the
+ HPROT[3:1] master interface signals */
+ __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ } CFG_HI6_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t SGR6; /*!< Source Gather Register for Channel */
+
+ struct {
+ __IO uint32_t SGI : 20; /*!< Source gather interval */
+ __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */
+ } SGR6_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED61;
+
+ union {
+ __IO uint32_t DSR6; /*!< Destination Scatter Register for Channel */
+
+ struct {
+ __IO uint32_t DSI : 20; /*!< Destination scatter interval */
+ __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of
+ CTLx.DST_TR_WIDTH */
+ } DSR6_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED62;
+ __IO uint32_t SAR7; /*!< Current Source Address of DMA transfer */
+ __I uint32_t RESERVED63;
+ __IO uint32_t DAR7; /*!< Current Destination Address of DMA transfer */
+ __I uint32_t RESERVED64;
+
+ union {
+ __IO uint32_t LLP7; /*!< Linked List Pointer Register for Channel */
+
+ struct {
+ __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that
+ stores the next linked list item resides. */
+ __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is
+ enabled */
+ } LLP7_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED65;
+
+ union {
+ __IO uint32_t CTL_LOW7; /*!< Lower 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */
+ __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */
+ __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */
+ __IO uint32_t DINC : 2; /*!< Destination Address Increment */
+ __IO uint32_t SINC : 2; /*!< Source Address Increment */
+ __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */
+ __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */
+ __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */
+ __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */
+ uint32_t : 1;
+ __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */
+ __IO uint32_t DMS : 2; /*!< Destination Master Select */
+ __IO uint32_t SMS : 2; /*!< Source Master Select */
+ __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */
+ __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */
+ } CTL_LOW7_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CTL_HI7; /*!< Higher 32-bits Control Register for Channel */
+
+ struct {
+ __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform
+ for every block transfer */
+ __IO uint32_t DONE : 1; /*!< a block transfer is complete */
+ } CTL_HI7_b; /*!< BitSize */
+ };
+ __IO uint32_t SSTAT7; /*!< Source Status Register for Channel */
+ __I uint32_t RESERVED66;
+ __IO uint32_t DSTAT7; /*!< Destination Status Register for Channel */
+ __I uint32_t RESERVED67;
+ __IO uint32_t SSTATAR7; /*!< Source Status Address Register for Channel */
+ __I uint32_t RESERVED68;
+ __IO uint32_t DSTATAR7; /*!< Destination Status Address Register for Channel */
+ __I uint32_t RESERVED69;
+
+ union {
+ __IO uint32_t CFG_LOW7; /*!< Lower 32-bit Configuration Register for Channel */
+
+ struct {
+ uint32_t : 5;
+ __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */
+ __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit
+ is cleared. */
+ __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */
+ __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */
+ __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */
+ __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */
+ __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */
+ __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */
+ __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */
+ __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */
+ __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */
+ __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */
+ __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */
+ } CFG_LOW7_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CFG_HI7; /*!< Higher 32-bit Configuration Register for Channel */
+
+ struct {
+ __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination
+ Peripheral is the flow controller. */
+ __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before
+ a burst transaction request is serviced. */
+ __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the
+ HPROT[3:1] master interface signals */
+ __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */
+ } CFG_HI7_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t SGR7; /*!< Source Gather Register for Channel */
+
+ struct {
+ __IO uint32_t SGI : 20; /*!< Source gather interval */
+ __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */
+ } SGR7_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED70;
+
+ union {
+ __IO uint32_t DSR7; /*!< Destination Scatter Register for Channel */
+
+ struct {
+ __IO uint32_t DSI : 20; /*!< Destination scatter interval */
+ __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of
+ CTLx.DST_TR_WIDTH */
+ } DSR7_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED71[11];
+ __I uint8_t INT_TFR; /*!< DMA Transfer Complete */
+ __I uint8_t RESERVED72[7];
+ __I uint8_t INT_BLOCK; /*!< Block Transfer Complete */
+ __I uint8_t RESERVED73[7];
+ __I uint8_t INT_SRC_TRAN; /*!< Source Transaction Complete */
+ __I uint8_t RESERVED74[7];
+ __I uint8_t INT_DST_TRAN; /*!< Destination Transaction Complete */
+ __I uint8_t RESERVED75[7];
+ __I uint8_t INT_ERR; /*!< Error */
+ __I uint8_t RESERVED76[7];
+
+ union {
+ __IO uint16_t INT_EN_TFR; /*!< DMA Transfer Complete */
+
+ struct {
+ __IO uint16_t EN : 8; /*!< interrupt enable */
+ __IO uint16_t WE : 8; /*!< interrupt enable write enable */
+ } INT_EN_TFR_b; /*!< BitSize */
+ };
+ __I uint16_t RESERVED77[3];
+
+ union {
+ __IO uint16_t INT_EN_BLOCK; /*!< Block Transfer Complete */
+
+ struct {
+ __IO uint16_t EN : 8; /*!< interrupt enable */
+ __IO uint16_t WE : 8; /*!< interrupt enable write enable */
+ } INT_EN_BLOCK_b; /*!< BitSize */
+ };
+ __I uint16_t RESERVED78[3];
+
+ union {
+ __IO uint16_t INT_EN_SRC_TRAN; /*!< Source Transaction Complete */
+
+ struct {
+ __IO uint16_t EN : 8; /*!< interrupt enable */
+ __IO uint16_t WE : 8; /*!< interrupt enable write enable */
+ } INT_EN_SRC_TRAN_b; /*!< BitSize */
+ };
+ __I uint16_t RESERVED79[3];
+
+ union {
+ __IO uint16_t INT_EN_DST_TRAN; /*!< Destination Transaction Complete */
+
+ struct {
+ __IO uint16_t EN : 8; /*!< interrupt enable */
+ __IO uint16_t WE : 8; /*!< interrupt enable write enable */
+ } INT_EN_DST_TRAN_b; /*!< BitSize */
+ };
+ __I uint16_t RESERVED80[3];
+
+ union {
+ __IO uint16_t INT_EN_ERR; /*!< Error */
+
+ struct {
+ __IO uint16_t EN : 8; /*!< interrupt enable */
+ __IO uint16_t WE : 8; /*!< interrupt enable write enable */
+ } INT_EN_ERR_b; /*!< BitSize */
+ };
+ __I uint16_t RESERVED81[3];
+ __O uint8_t INT_CLEAR_TFR; /*!< DMA Transfer Complete */
+ __I uint8_t RESERVED82[7];
+ __O uint8_t INT_CLEAR_BLOCK; /*!< Block Transfer Complete */
+ __I uint8_t RESERVED83[7];
+ __O uint8_t INT_CLEAR_SRC_TRAN; /*!< Source Transaction Complete */
+ __I uint8_t RESERVED84[7];
+ __O uint8_t INT_CLEAR_DST_TRAN; /*!< Destination Transaction Complete */
+ __I uint8_t RESERVED85[7];
+ __O uint8_t INT_CLEAR_ERR; /*!< Error */
+ __I uint8_t RESERVED86[63];
+
+ union {
+ __IO uint32_t DMA_EN; /*!< DW_ahb_dmac Configuration Register */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< enable */
+ } DMA_EN_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED87;
+
+ union {
+ __IO uint32_t CH_EN; /*!< DW_ahb_dmac Channel Enable Register */
+
+ struct {
+ __IO uint32_t EN : 8; /*!< enable */
+ __IO uint32_t WE : 8; /*!< enable write enable */
+ } CH_EN_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED88[10];
+
+ union {
+ __I uint32_t DMA_COMP_PARAMS_6_HI; /*!< Component Parameters for channel 7 */
+
+ struct {
+ __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination
+ transfer width. */
+ __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source
+ transfer width. */
+ __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */
+ __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */
+ __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */
+ __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */
+ __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */
+ __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */
+ __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is
+ on */
+ __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */
+ uint32_t : 2;
+ __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */
+ __I uint32_t DMS : 3; /*!< Destination AHB dma interface */
+ __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */
+ __I uint32_t SMS : 3; /*!< source AHB dma interface */
+ __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */
+ } DMA_COMP_PARAMS_6_HI_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t DMA_COMP_PARAMS_5_LOW; /*!< Component Parameters for channel 6 */
+
+ struct {
+ __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination
+ transfer width. */
+ __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source
+ transfer width. */
+ __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */
+ __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */
+ __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */
+ __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */
+ __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */
+ __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */
+ __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is
+ on */
+ __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */
+ uint32_t : 2;
+ __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */
+ __I uint32_t DMS : 3; /*!< Destination AHB dma interface */
+ __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */
+ __I uint32_t SMS : 3; /*!< source AHB dma interface */
+ __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */
+ } DMA_COMP_PARAMS_5_LOW_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t DMA_COMP_PARAMS_5_HI; /*!< Component Parameters for channel 5 */
+
+ struct {
+ __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination
+ transfer width. */
+ __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source
+ transfer width. */
+ __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */
+ __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */
+ __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */
+ __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */
+ __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */
+ __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */
+ __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is
+ on */
+ __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */
+ uint32_t : 2;
+ __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */
+ __I uint32_t DMS : 3; /*!< Destination AHB dma interface */
+ __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */
+ __I uint32_t SMS : 3; /*!< source AHB dma interface */
+ __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */
+ } DMA_COMP_PARAMS_5_HI_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t DMA_COMP_PARAMS_4_LOW; /*!< Component Parameters for channel 4 */
+
+ struct {
+ __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination
+ transfer width. */
+ __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source
+ transfer width. */
+ __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */
+ __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */
+ __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */
+ __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */
+ __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */
+ __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */
+ __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is
+ on */
+ __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */
+ uint32_t : 2;
+ __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */
+ __I uint32_t DMS : 3; /*!< Destination AHB dma interface */
+ __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */
+ __I uint32_t SMS : 3; /*!< source AHB dma interface */
+ __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */
+ } DMA_COMP_PARAMS_4_LOW_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t DMA_COMP_PARAMS_4_HI; /*!< Component Parameters for channel 3 */
+
+ struct {
+ __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination
+ transfer width. */
+ __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source
+ transfer width. */
+ __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */
+ __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */
+ __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */
+ __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */
+ __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */
+ __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */
+ __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is
+ on */
+ __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */
+ uint32_t : 2;
+ __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */
+ __I uint32_t DMS : 3; /*!< Destination AHB dma interface */
+ __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */
+ __I uint32_t SMS : 3; /*!< source AHB dma interface */
+ __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */
+ } DMA_COMP_PARAMS_4_HI_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t DMA_COMP_PARAMS_3_LOW; /*!< Component Parameters for channel 2 */
+
+ struct {
+ __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination
+ transfer width. */
+ __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source
+ transfer width. */
+ __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */
+ __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */
+ __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */
+ __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */
+ __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */
+ __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */
+ __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is
+ on */
+ __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */
+ uint32_t : 2;
+ __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */
+ __I uint32_t DMS : 3; /*!< Destination AHB dma interface */
+ __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */
+ __I uint32_t SMS : 3; /*!< source AHB dma interface */
+ __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */
+ } DMA_COMP_PARAMS_3_LOW_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t DMA_COMP_PARAMS_3_HI; /*!< Component Parameters for channel 1 */
+
+ struct {
+ __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination
+ transfer width. */
+ __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source
+ transfer width. */
+ __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */
+ __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */
+ __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */
+ __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */
+ __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */
+ __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */
+ __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is
+ on */
+ __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */
+ uint32_t : 2;
+ __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */
+ __I uint32_t DMS : 3; /*!< Destination AHB dma interface */
+ __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */
+ __I uint32_t SMS : 3; /*!< source AHB dma interface */
+ __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */
+ } DMA_COMP_PARAMS_3_HI_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t DMA_COMP_PARAMS_2_LOW; /*!< Component Parameters for channel 0 */
+
+ struct {
+ __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination
+ transfer width. */
+ __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source
+ transfer width. */
+ __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */
+ __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */
+ __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */
+ __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */
+ __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */
+ __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */
+ __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is
+ on */
+ __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */
+ uint32_t : 2;
+ __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */
+ __I uint32_t DMS : 3; /*!< Destination AHB dma interface */
+ __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */
+ __I uint32_t SMS : 3; /*!< source AHB dma interface */
+ __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */
+ } DMA_COMP_PARAMS_2_LOW_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED89;
+
+ union {
+ __I uint32_t DMA_COMP_PARAMS_1_LOW; /*!< Maximum block size for channel */
+
+ struct {
+ __I uint32_t CH0_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 0. */
+ __I uint32_t CH1_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 1 */
+ __I uint32_t CH2_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 2 */
+ __I uint32_t CH3_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 3 */
+ __I uint32_t CH4_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 4 */
+ __I uint32_t CH5_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 5 */
+ __I uint32_t CH6_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 6 */
+ __I uint32_t CH7_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 7 */
+ } DMA_COMP_PARAMS_1_LOW_b; /*!< BitSize */
+ };
+} DMA_Type;
+
+
+/* ================================================================================ */
+/* ================ ETH ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief ETH (ETH)
+ */
+
+typedef struct { /*!< ETH Structure */
+
+ union {
+ __IO uint32_t CONFIG; /*!< MAC Configuration Register */
+
+ struct {
+ __IO uint32_t PRELEN : 2; /*!< Preamble Length for Transmit frames */
+ __IO uint32_t RX_EN : 1; /*!< Receiver Enable */
+ __IO uint32_t TX_EN : 1; /*!< Transmitter Enable */
+ __IO uint32_t DC_EN : 1; /*!< Deferral Check Enable */
+ uint32_t : 2;
+ __IO uint32_t ACS : 1; /*!< Automatic Pad or CRC Stripping */
+ __IO uint32_t LUD : 1; /*!< Link Up or Down */
+ uint32_t : 1;
+ __IO uint32_t IPC : 1; /*!< Checksum Offload */
+ __IO uint32_t DM : 1; /*!< Duplex Mode */
+ __IO uint32_t LM : 1; /*!< Loopback Mode */
+ uint32_t : 1;
+ __IO uint32_t FES : 1; /*!< Speed in XMII interface */
+ __IO uint32_t PS : 1; /*!< the Ethernet line speed */
+ uint32_t : 4;
+ __IO uint32_t JE : 1; /*!< Jumbo enable */
+ uint32_t : 1;
+ __IO uint32_t JD : 1; /*!< if 0, the MAC cuts off the transmitter if more than 2,048 bytes
+ of data (10,240 if JE is set high) */
+ __IO uint32_t WD : 1; /*!< Watchdog Disable */
+ __IO uint32_t TC : 1; /*!< If 1, this bit enables the transmission of duplex mode, link
+ speed, and link up or down information to the PHY */
+ __IO uint32_t CST : 1; /*!< CRC Stripping for Type Frames */
+ uint32_t : 1;
+ __IO uint32_t TWOKPE : 1; /*!< If 0, 1518 bytes is considered as a giant frame, 1 is 2000 bytes. */
+ __IO uint32_t SARC : 3; /*!< Source Address Insertion or Replacement Control */
+ } CONFIG_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t FF; /*!< MAC Frame Filter */
+
+ struct {
+ __IO uint32_t PR : 1; /*!< Receive all frames in spite of source and destination address */
+ __IO uint32_t HUC : 1; /*!< if 1, don't compare DA field in destination address filtering
+ of unicast frames with DA register */
+ __IO uint32_t HMC : 1; /*!< if 1, don't compare DA field in destination address filtering
+ of multicast frames with DA register */
+ __IO uint32_t DAIF : 1; /*!< if set, the Address Check block operates in inverse filtering
+ mode for the DA address comparison */
+ __IO uint32_t PM : 1; /*!< Pass All Multicast */
+ __IO uint32_t DBF : 1; /*!< Disable Broadcast Frames */
+ __IO uint32_t PCF : 2; /*!< Pass Control Frames */
+ __IO uint32_t SAIF : 1; /*!< If set, the frames whose SA matches the SA registers are marked
+ as failing the SA Address filter */
+ __IO uint32_t SAF : 1; /*!< Source Address Filter Enable */
+ __IO uint32_t HPF : 1; /*!< Hash or Perfect Filter */
+ uint32_t : 5;
+ __IO uint32_t VTFE : 1; /*!< VLAN Tag Filter Enable */
+ uint32_t : 3;
+ __IO uint32_t IPFE : 1; /*!< Layer 3 and Layer 4 Filter Enable */
+ __IO uint32_t DNTU : 1; /*!< Drop non-TCP/UDP over IP Frames */
+ uint32_t : 9;
+ __IO uint32_t RA : 1; /*!< Receive all */
+ } FF_b; /*!< BitSize */
+ };
+ __IO uint32_t HTH; /*!< Hash Table High Register */
+ __IO uint32_t HTL; /*!< Hash Table Low Register */
+
+ union {
+ __IO uint32_t GMII_ADDR; /*!< GMII Address Register */
+
+ struct {
+ __IO uint32_t BUSY : 1; /*!< GMII Busy */
+ __IO uint32_t GW : 1; /*!< GMII write or read */
+ __IO uint32_t CR : 4; /*!< CSR Clock Range */
+ __IO uint32_t GR : 5; /*!< These bits select the desired GMII register in the selected
+ PHY device */
+ __IO uint32_t PA : 5; /*!< This field indicates which of the 32 possible PHY devices are
+ being accessed */
+ } GMII_ADDR_b; /*!< BitSize */
+ };
+ __IO uint32_t GMII_DATA; /*!< GMII Data Register */
+
+ union {
+ __IO uint32_t FC; /*!< Flow Control Register */
+
+ struct {
+ __IO uint32_t FCB : 1; /*!< This bit initiates a Pause frame in the full-duplex mode */
+ __IO uint32_t TFE : 1; /*!< MAC enables the flow control operation to transmit Pause frames */
+ __IO uint32_t RFE : 1; /*!< MAC enables the flow control operation to receive Pause frames */
+ __IO uint32_t UP : 1; /*!< MAC can detect Pause frames with unicast address of the station */
+ } FC_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t VLAN_TAG; /*!< VLAN Tag Register */
+
+ struct {
+ __IO uint32_t VL : 16; /*!< VLAN Tag Identifier for Receive Frames */
+ __IO uint32_t ETV : 1; /*!< Enable 12-Bit VLAN Tag Comparison */
+ __IO uint32_t VTIM : 1; /*!< If set, The frames that do not have matching VLAN Tag are marked
+ as matched */
+ __IO uint32_t ESVL : 1; /*!< If set, consider the S-VLAN (Type = 0x88A8) frames as valid
+ VLAN tagged frames */
+ __IO uint32_t VTHM : 1; /*!< When set, the most significant four bits of the VLAN tag's CRC
+ are used to index the content */
+ } VLAN_TAG_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED0[8];
+ __IO uint16_t ADDR0_HIGH; /*!< MAC Address0 High Register */
+ __I uint16_t RESERVED1;
+ __IO uint32_t ADDR0_LOW; /*!< MAC Address0 LOW Register */
+
+ union {
+ __IO uint32_t ADDR1_HIGH; /*!< MAC Address0 High Register */
+
+ struct {
+ __IO uint32_t ADDR : 16; /*!< MAC Address1 [47:32] */
+ uint32_t : 14;
+ __IO uint32_t SA : 1; /*!< MAC address1 is source or destination address compared with
+ received frame */
+ __IO uint32_t AE : 1; /*!< the address filter module uses the MAC address1 for filtering */
+ } ADDR1_HIGH_b; /*!< BitSize */
+ };
+ __IO uint32_t ADDR1_LOW; /*!< MAC Address1 LOW Register */
+ __I uint32_t RESERVED2[47];
+ __IO uint32_t MMC_RX_MASK; /*!< MMC Receive interrupt mask */
+ __IO uint32_t MMC_TX_MASK; /*!< MMC Transmit Interrupt Mask */
+ __I uint32_t RESERVED3[955];
+
+ union {
+ __IO uint32_t BUS_MODE; /*!< Flow Control Register */
+
+ struct {
+ __IO uint32_t SWR : 1; /*!< Software Reset */
+ __IO uint32_t DA : 1; /*!< This bit specifies the arbitration scheme between the transmit
+ and receive paths of Channel */
+ __IO uint32_t DSL : 5; /*!< the byte number of bus width to skip between two unchained descriptors */
+ __IO uint32_t ATDS : 1; /*!< When set, the size of the alternate descriptor increases to
+ 32 bytes */
+ __IO uint32_t PBL : 6; /*!< These bits indicate the maximum number of beats to be transferred
+ in one DMA transaction */
+ __IO uint32_t PR : 2; /*!< The Priority Ratio is (PR + 1) : 1 */
+ __IO uint32_t FB : 1; /*!< performs fixed burst transfers or not */
+ __IO uint32_t RPBL : 6; /*!< This field indicates the maximum number of beats to be transferred
+ in one Rx DMA transaction */
+ __IO uint32_t USP : 1; /*!< If set, RPBL is same as RPBL definition */
+ __IO uint32_t PBLx8 : 1; /*!< If set, all PBLs multiplies 8 */
+ __IO uint32_t AAL : 1; /*!< If set, all bursts aligned to the start address LS bits */
+ __IO uint32_t MB : 1; /*!< When this bit is set high and the FB bit is low, the AHB master
+ interface starts all bursts of length more than 16 with INCR */
+ __IO uint32_t TXPR : 1; /*!< When set, the transmit DMA has higher priority than the receive
+ DMA */
+ __IO uint32_t PRWG : 2; /*!< The Priority weight is (PRWG + 1) : 1 */
+ uint32_t : 1;
+ __IO uint32_t RIB : 1; /*!< If set, rebuilds the pending beats of any burst transfer initiated
+ with INCRx */
+ } BUS_MODE_b; /*!< BitSize */
+ };
+ __IO uint32_t TPD; /*!< Transmit Poll Demand */
+ __IO uint32_t RPD; /*!< Receive Poll Demand */
+ __IO uint32_t RDESLA; /*!< Receive Descriptor List Address */
+ __IO uint32_t TDESLA; /*!< Transmit Descriptor List Address */
+
+ union {
+ __IO uint32_t STATUS; /*!< Status Register */
+
+ struct {
+ __IO uint32_t TI : 1; /*!< This bit indicates that the frame transmission is complete */
+ __IO uint32_t TPS : 1; /*!< Transmit Process Stopped */
+ __IO uint32_t TU : 1; /*!< the host owns the Next Descriptor in the Transmit List and the
+ DMA cannot acquire it. */
+ __IO uint32_t TJT : 1; /*!< Transmit Jabber Timeout */
+ __IO uint32_t OVF : 1; /*!< Receive Overflow */
+ __IO uint32_t UNF : 1; /*!< Transmit Underflow */
+ __IO uint32_t RI : 1; /*!< the frame reception is complete */
+ __IO uint32_t RU : 1; /*!< Receive Buffer Unavailable */
+ __IO uint32_t RPS : 1; /*!< Receive Process Stopped */
+ __IO uint32_t RWT : 1; /*!< Receive Watchdog Timeout */
+ __IO uint32_t ETI : 1; /*!< the frame to be transmitted is fully transferred to the MTL
+ Transmit FIFO */
+ uint32_t : 2;
+ __IO uint32_t FBI : 1; /*!< a bus error occurred, as described in EB. */
+ __IO uint32_t ERI : 1; /*!< the DMA filled the first data buffer of the packet */
+ __IO uint32_t AIS : 1; /*!< Abnormal Interrupt Summary, must be cleared by writting */
+ __IO uint32_t NIS : 1; /*!< Normal Interrupt Summary, must be cleared by writting */
+ __I uint32_t RS : 3; /*!< Receive DMA FSM state */
+ __I uint32_t TS : 3; /*!< Transmit DMA FSM state */
+ __I uint32_t EB : 3; /*!< Error bit */
+ __I uint32_t GLI : 1; /*!< GMAC Line Interface Interrupt */
+ __I uint32_t GMI : 1; /*!< GMAC MMC Interrupt */
+ __I uint32_t GPI : 1; /*!< GMAC PMT Interrupt */
+ __I uint32_t TTI : 1; /*!< Timestamp Trigger Interrupt */
+ } STATUS_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t OPERATION; /*!< Operation Mode Register */
+
+ struct {
+ uint32_t : 1;
+ __IO uint32_t SR : 1; /*!< Start or Stop Receive */
+ __IO uint32_t OSF : 1; /*!< Operate on Second Frame */
+ __IO uint32_t RT : 2; /*!< Receive Threshold Control */
+ __IO uint32_t DGF : 1; /*!< Drop Giant Frames */
+ __IO uint32_t FUF : 1; /*!< Forward Undersized Good Frames */
+ __IO uint32_t FEF : 1; /*!< Forward Error Frames */
+ uint32_t : 5;
+ __IO uint32_t ST : 1; /*!< Start or Stop Transmission Command */
+ __IO uint32_t TT : 3; /*!< Transmit Threshold Control */
+ uint32_t : 3;
+ __IO uint32_t FTF : 1; /*!< Flush Transmit FIFO */
+ __IO uint32_t TSF : 1; /*!< If set, transmission starts when a full frame resides in Transmit
+ FIFO */
+ uint32_t : 2;
+ __IO uint32_t DFF : 1; /*!< Disable Flushing of Received Frames */
+ __IO uint32_t RSF : 1; /*!< If set, the MTL reads a frame from the Rx FIFO while the complete
+ frame has been written to it, */
+ } OPERATION_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INT_EN; /*!< Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TIE : 1; /*!< Transmit Interrupt Enable */
+ __IO uint32_t TSE : 1; /*!< Transmit Stopped Enable */
+ __IO uint32_t TUE : 1; /*!< Transmit Buffer Unavailable Enable */
+ __IO uint32_t TJE : 1; /*!< Transmit Jabber Timeout Enable */
+ __IO uint32_t OVE : 1; /*!< Overflow Interrupt Enable */
+ __IO uint32_t UNE : 1; /*!< Underflow Interrupt Enable */
+ __IO uint32_t RIE : 1; /*!< Receive Interrupt Enable */
+ __IO uint32_t RUE : 1; /*!< Receive Buffer Unavailable Enable */
+ __IO uint32_t RSE : 1; /*!< Receive Stopped Enable */
+ __IO uint32_t RWE : 1; /*!< Receive Watchdog Timeout Enable */
+ __IO uint32_t ETE : 1; /*!< Early Transmit Interrupt Enable */
+ uint32_t : 2;
+ __IO uint32_t FBE : 1; /*!< Fatal Bus Error Enable */
+ __IO uint32_t ERE : 1; /*!< Early Receive Interrupt Enable */
+ __IO uint32_t AIE : 1; /*!< Abnormal Interrupt Summary Enable */
+ __IO uint32_t NIE : 1; /*!< Normal Interrupt Summary Enable */
+ } INT_EN_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED4[3];
+
+ union {
+ __IO uint32_t AHB_STATUS; /*!< AHB Status Register */
+
+ struct {
+ __IO uint32_t BUSY : 1; /*!< If set, it indicates that the AHB master interface FSMs are
+ in the non-idle state */
+ } AHB_STATUS_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED5[6];
+ __I uint32_t CURTDESAPTR; /*!< Current Host Transmit Descriptor Register */
+ __I uint32_t CURRDESAPTR; /*!< Current Host Receive Descriptor Register */
+ __I uint32_t CURTBUFAPTR; /*!< Current Host Transmit Buffer Address Register */
+ __I uint32_t CURRBUFAPTR; /*!< Current Host Receive Buffer Address Register */
+} ETH_Type;
+
+
+/* ================================================================================ */
+/* ================ USB ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USB (USB)
+ */
+
+typedef struct { /*!< USB Structure */
+
+ union {
+ __IO uint32_t GOTGCTL; /*!< Control and Status register */
+
+ struct {
+ __I uint32_t SES_REQ_SCS: 1; /*!< set when a session request initiation is successful as a device */
+ __IO uint32_t SES_SEQ : 1; /*!< set to initiate a session request on the USB as a device */
+ __IO uint32_t VB_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using
+ the GOTGCTL.VbvalidOvVal as a host */
+ __IO uint32_t VB_VALID_OV_VAL: 1; /*!< set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn
+ is set as a host */
+ __IO uint32_t A_VALID_OV_EN: 1; /*!< enable/disable the software to override the Avalid signal using
+ the GOTGCTL.AvalidOvVal as a host */
+ __IO uint32_t A_VALID_OV_VAL: 1; /*!< set Override value for Avalid signal when GOTGCTL.AvalidOvEn
+ is set as a host */
+ __IO uint32_t B_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using
+ the GOTGCTL.BvalidOvVal as a device. */
+ __IO uint32_t B_VALID_OV_VAL: 1; /*!< set Override value for Bvalid signal when GOTGCTL.BvalidOvEn
+ is set as a device. */
+ __I uint32_t HST_NEG_SCS: 1; /*!< sets when host negotiation is successful as a device. */
+ __IO uint32_t HNP_REQ : 1; /*!< sets this bit to initiate an HNP request to the connected USB
+ host as a device */
+ __IO uint32_t HST_SET_HNP_EN: 1; /*!< Host Set HNP Enable as a host */
+ __IO uint32_t DEV_HNP_EN : 1; /*!< Device HNP Enabled as a device */
+ uint32_t : 4;
+ __I uint32_t CON_ID_STS : 1; /*!< Connector ID Status */
+ __I uint32_t DBNC_TIME : 1; /*!< the debounce time of a detected connection as a host */
+ __I uint32_t A_SES_VLD : 1; /*!< A-Session Valid as a host */
+ __I uint32_t B_SES_VLD : 1; /*!< B-Session Valid as a host */
+ __IO uint32_t OTG_VER : 1; /*!< If 0, OTG Version 1.3. If 1, OTG Version 2.0. */
+ } GOTGCTL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t GOTGINT; /*!< OTG interrupt Register */
+
+ struct {
+ uint32_t : 2;
+ __IO uint32_t SES_END_DET: 1; /*!< Set when the utmiotg_bvalid signal is deasserted */
+ uint32_t : 5;
+ __IO uint32_t SES_REQ_SUC_STS_CHNG: 1; /*!< Session Request Success Status Change */
+ __IO uint32_t HST_NEG_SUC_STS_CHNG: 1; /*!< Host Negotiation Success Status Change */
+ uint32_t : 7;
+ __IO uint32_t HST_NEG_DET: 1; /*!< if set, detects a host negotiation request on the USB */
+ __IO uint32_t A_DEV_TOUT_CHG: 1; /*!< A-device has timed out while waiting for the B-device to connect */
+ __IO uint32_t DBNCE_DONE : 1; /*!< debounce is completed after the device connect as a host */
+ } GOTGINT_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t GAHBCFG; /*!< AHB Configuration Register */
+
+ struct {
+ __IO uint32_t GLBL_INTR_EN: 1; /*!< Global Interrupt Enable */
+ __IO uint32_t BST_LEN : 4; /*!< Burst Length/Type */
+ __IO uint32_t DMA_EN : 1; /*!< DMA enable */
+ uint32_t : 15;
+ __IO uint32_t REMOTE_MEM_SUPP: 1; /*!< enable the functionality to wait for the system DMA Done Signal
+ for the DMA Write Transfers */
+ __IO uint32_t NOTIFY_ALL_DMA_WRITE: 1; /*!< enable the System DMA Done functionality for all the DMA write
+ Transactions corresponding to the Channel/Endpoint */
+ __IO uint32_t AHB_SINGLE : 1; /*!< supports Single transfers for the remaining data in a transfer */
+ } GAHBCFG_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t GUSBCFG; /*!< USB Configuration Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t PHY_IF : 1; /*!< PHY Interface */
+ __IO uint32_t ULPI_UTMI_SEL: 1; /*!< 1, ULPI. 0, UTMI+ */
+ __IO uint32_t FS_IF : 1; /*!< 1, 3-pin bidirectional. 0, 6-pin unidirectional */
+ __IO uint32_t PHY_SEL : 1; /*!< 0, USB 2.0 High-Speed PHY. 1, USB 1.1 full-speed serial transceiver */
+ __IO uint32_t DDR_SEL : 1; /*!< 0, Single Data Rate ULPI Interface, with 8-bit-wide data bus.
+ 1, Double Data Rate ULPI Interface, with 4-bit-wide data bus */
+ __IO uint32_t SRP_CAP : 1; /*!< SRP-Capable */
+ __IO uint32_t HNP_CAP : 1; /*!< HNP-Capable */
+ __IO uint32_t USB_TRD_TIM: 4; /*!< Specifies the response time for a MAC request to the Packet
+ FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM) as
+ a device. */
+ uint32_t : 1;
+ __IO uint32_t PHY_LPWR_CLK_SEL: 1; /*!< 0, 480-MHz Internal PLL clock. 1, 48-MHz External Clock */
+ uint32_t : 12;
+ __IO uint32_t TX_END_DELAY: 1; /*!< Tx End Delay as a device */
+ __IO uint32_t FORCE_HOST_MODE: 1; /*!< Force Host Mode */
+ __IO uint32_t FORCE_DEVICE_MODE: 1; /*!< Force Device Mode */
+ } GUSBCFG_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t GRSTCTL; /*!< Reset Register */
+
+ struct {
+ __IO uint32_t CORE_SOFT_RST: 1; /*!< Core Soft Reset */
+ uint32_t : 1;
+ __IO uint32_t FRM_CNT_RST: 1; /*!< Host Frame Counter Reset */
+ uint32_t : 1;
+ __IO uint32_t RX_FIFO_FLUSH: 1; /*!< RxFIFO Flush */
+ __IO uint32_t TX_FIFO_FLUSH: 1; /*!< TxFIFO Flush */
+ __IO uint32_t TX_FIFO_FLUSH_NUM: 4; /*!< This field indicates which of the 32 possible PHY devices are
+ being accessed */
+ __IO uint32_t TX_FIFO_ALL: 1; /*!< TxFIFO flush all FIFOs */
+ uint32_t : 19;
+ __I uint32_t DMA_REQ : 1; /*!< Indicates that the DMA request is in progress */
+ __I uint32_t AHB_IDLE : 1; /*!< Indicates that the AHB Master State Machine is in the IDLE condition */
+ } GRSTCTL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t GINTSTS; /*!< Interrupt Register */
+
+ struct {
+ __I uint32_t CUR_MOD : 1; /*!< Current Mode of Operation */
+ __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch Interrupt */
+ __I uint32_t OTG_INT : 1; /*!< OTG Interrupt */
+ __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */
+ __I uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */
+ __I uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */
+ __I uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */
+ __I uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */
+ uint32_t : 2;
+ __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */
+ __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */
+ __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */
+ __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */
+ __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a
+ device */
+ __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */
+ uint32_t : 1;
+ __I uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */
+ __I uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */
+ __I uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */
+ __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */
+ __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous
+ OUT Transfer as a device */
+ __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */
+ __IO uint32_t RST_DET : 1; /*!< reset detect as a device */
+ __I uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as
+ a host */
+ __I uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as
+ a host */
+ __I uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */
+ __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */
+ __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */
+ __IO uint32_t DD : 1; /*!< A change in connector ID status */
+ __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */
+ __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */
+ } GINTSTS_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t GINTEN; /*!< Interrupt enable Register */
+
+ struct {
+ uint32_t : 1;
+ __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch */
+ __IO uint32_t OTG_INT : 1; /*!< OTG */
+ __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */
+ __IO uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */
+ __IO uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */
+ __IO uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */
+ __IO uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */
+ uint32_t : 2;
+ __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */
+ __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */
+ __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */
+ __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */
+ __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a
+ device */
+ __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */
+ uint32_t : 1;
+ __IO uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */
+ __IO uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */
+ __IO uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */
+ __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */
+ __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous
+ OUT Transfer as a device */
+ __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */
+ __IO uint32_t RST_DET : 1; /*!< reset detect as a device */
+ __IO uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as
+ a host */
+ __IO uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as
+ a host */
+ __IO uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */
+ __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */
+ __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */
+ __IO uint32_t DD : 1; /*!< A change in connector ID status */
+ __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */
+ __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */
+ } GINTEN_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t GRXSTSR; /*!< Returns the contents of the top of the Receive FIFO */
+
+ struct {
+ __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */
+ __I uint32_t BCNT : 11; /*!< byte count of the received packet */
+ __I uint32_t DPID : 2; /*!< Data PID of the received packet */
+ __I uint32_t PS : 4; /*!< the status of the received packet */
+ __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which
+ the packet is received on the USB */
+ } GRXSTSR_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t GRXSTSP; /*!< Pop the contents of the top of the Receive FIFO */
+
+ struct {
+ __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */
+ __I uint32_t BCNT : 11; /*!< byte count of the received packet */
+ __I uint32_t DPID : 2; /*!< Data PID of the received packet */
+ __I uint32_t PS : 4; /*!< the status of the received packet */
+ __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which
+ the packet is received on the USB */
+ } GRXSTSP_b; /*!< BitSize */
+ };
+ __IO uint16_t GRXFSIZ; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768
+ is max */
+ __I uint16_t RESERVED0;
+
+ union {
+ __IO uint32_t GNPTXFSIZ; /*!< Non-Periodic Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t NTRSA_INEF0TRSA: 16; /*!< start address for Non-periodic Transmit FIFO RAM as a host or
+ IN Endpoint FIFO0 Transmit RAM as a device */
+ __IO uint32_t NTD_INEF0TD: 16; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768
+ is max. Non-periodic TxFIFO Depth as a host or IN Endpoint TxFIFO
+ 0 Depth as a device */
+ } GNPTXFSIZ_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t GNPTXSTS; /*!< Non-Periodic Transmit FIFO/Queue Status Register */
+
+ struct {
+ __I uint32_t NTSA : 16; /*!< the amount of free space available in the Non-periodic TxFIFO,
+ max is 32768. */
+ __I uint32_t NTRQSA : 8; /*!< the amount of free space available in the Non-periodic Transmit
+ Request Queue, max is 8. */
+ __I uint32_t TNTRQ_LAST : 1; /*!< last Entry in the Non-periodic Tx Request Queue that is currently
+ being processed by the MAC */
+ __I uint32_t TNTRQ_TYPE : 2; /*!< type in the Non-periodic Tx Request Queue that is currently
+ being processed by the MAC */
+ __I uint32_t TNTRQ_CH : 4; /*!< Channel of top of the Non-periodic Transmit Request Queue */
+ } GNPTXSTS_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED1[5];
+
+ union {
+ __I uint32_t GHWCFG1; /*!< User HW Config1 Register */
+
+ struct {
+ __I uint32_t EP0_DIR : 2; /*!< Endpoint 0 direction, always Bidirection */
+ __I uint32_t EP1_DIR : 2; /*!< Endpoint 1 direction */
+ __I uint32_t EP2_DIR : 2; /*!< Endpoint 2 direction */
+ __I uint32_t EP3_DIR : 2; /*!< Endpoint 3 direction */
+ __I uint32_t EP4_DIR : 2; /*!< Endpoint 4 direction */
+ __I uint32_t EP5_DIR : 2; /*!< Endpoint 5 direction */
+ __I uint32_t EP6_DIR : 2; /*!< Endpoint 6 direction */
+ __I uint32_t EP7_DIR : 2; /*!< Endpoint 7 direction */
+ __I uint32_t EP8_DIR : 2; /*!< Endpoint 8 direction */
+ __I uint32_t EP9_DIR : 2; /*!< Endpoint 9 direction */
+ __I uint32_t EP10_DIR : 2; /*!< Endpoint 10 direction */
+ __I uint32_t EP11_DIR : 2; /*!< Endpoint 11 direction */
+ __I uint32_t EP12_DIR : 2; /*!< Endpoint 12 direction */
+ __I uint32_t EP13_DIR : 2; /*!< Endpoint 13 direction */
+ __I uint32_t EP14_DIR : 2; /*!< Endpoint 14 direction */
+ __I uint32_t EP15_DIR : 2; /*!< Endpoint 15 direction */
+ } GHWCFG1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED2[3];
+
+ union {
+ __IO uint32_t GLPMCFG; /*!< Core LPM Configuration Register */
+
+ struct {
+ __IO uint32_t EP0_DIR : 1; /*!< LPM capability is enabled */
+ } GLPMCFG_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t GPWRDN; /*!< Global Power Down Register */
+
+ struct {
+ uint32_t : 1;
+ __IO uint32_t PMU_ACTIVE : 1; /*!< PMU Active is enabled */
+ uint32_t : 1;
+ __IO uint32_t PDC : 1; /*!< Power Down Clamp is enabled */
+ __IO uint32_t PDR : 1; /*!< If clear, Reset DWC_otg */
+ __IO uint32_t PDS : 1; /*!< If 0, DWC_otg is in ON state, or OFF state */
+ __IO uint32_t DIS_VBUS : 1; /*!< Disable VBUS */
+ uint32_t : 8;
+ __IO uint32_t SRP_DETECT_INT: 1; /*!< SRP has been detected by the PMU as a host */
+ __IO uint32_t SRP_DETECT_INT_EN: 1; /*!< Enable For SRPDetect Interrupt as a host */
+ __IO uint32_t STATE_CHN_INT: 1; /*!< a status change in either the IDDIG or BSessVld signal */
+ __IO uint32_t STATE_CHN_INT_EN: 1; /*!< Enable For Status Change Interrupt */
+ __I uint32_t LINE_STATE : 2; /*!< the current linestate on USB as seen by the PMU module */
+ __I uint32_t IDDIG : 1; /*!< the status of the IDDIG signal. If 0, host mode. if 1, device
+ mode */
+ __I uint32_t B_SESS_VLD : 1; /*!< B session valid status signal from the PHY */
+ __IO uint32_t ADP_INT : 1; /*!< set whenever there is a ADP event */
+ } GPWRDN_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t GDFIFOCFG; /*!< Global DFIFO Software Config Register */
+
+ struct {
+ __IO uint32_t GDFIFOCFG : 16; /*!< This field is for dynamic programming of the DFIFO Size. */
+ __IO uint32_t EPIBA : 16; /*!< This field provides the start address of the EP info controller */
+ } GDFIFOCFG_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED3[40];
+
+ union {
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t HPTSA : 16; /*!< start address of the Periodic TxFIFO */
+ __IO uint32_t EPIBA : 16; /*!< the size of the Periodic TxFIFO */
+ } HPTXFSIZ_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF1; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF2; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF2_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF3; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF3_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF4; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF4_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF5; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF5_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF6; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF6_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF7; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF7_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF8; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF8_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF9; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF9_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF10; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF10_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF11; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF11_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF12; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF12_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF13; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF13_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF14; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF14_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DIEPTXF15; /*!< Device In Endpoint Transmit FIFO Size Register */
+
+ struct {
+ __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */
+ } DIEPTXF15_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED4[176];
+
+ union {
+ __IO uint32_t HCFG; /*!< Host Configuration Register */
+
+ struct {
+ __IO uint32_t FS_LS_PCS : 2; /*!< FS/LS PHY Clock Select as a host */
+ __IO uint32_t FS_LS_SUPPORT: 1; /*!< If set, FS/LS-only, even If the connected device can support
+ HS */
+ uint32_t : 4;
+ __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */
+ __IO uint32_t RVP : 8; /*!< ResValid number of clock cycles to detect a valid resume */
+ uint32_t : 7;
+ __IO uint32_t EN_SG_DMA : 1; /*!< Enable Scatter/gather DMA in Host mode */
+ __IO uint32_t FLE : 2; /*!< the number of entries in the Frame list. 8 times of FLE */
+ __IO uint32_t EPS : 1; /*!< Enables periodic scheduling */
+ uint32_t : 4;
+ __IO uint32_t MCRTE : 1; /*!< enable/disable the Host core to wait 200 PHY clock cycles at
+ the end of Resume to change the opmode signal to the PHY to
+ 00 after Suspend or LPM. */
+ } HCFG_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register */
+
+ struct {
+ __IO uint32_t FI : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */
+ __IO uint32_t RC : 1; /*!< The HFIR can be dynamically reloaded during runtime if set */
+ } HFIR_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t HFNUM; /*!< Host Frame Number/Frame Time Remaining Register */
+
+ struct {
+ __I uint32_t FN : 16; /*!< This field increments when a new SOF is transmitted on the USB */
+ __I uint32_t FTR : 16; /*!< amount of time remaining in the current microframe (HS) or Frame
+ (FS/LS), in terms of PHY clocks */
+ } HFNUM_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED5;
+
+ union {
+ __I uint32_t HPTXSTS; /*!< Host Periodic Transmit FIFO/Queue Status Register */
+
+ struct {
+ __I uint32_t PTDFSA : 16; /*!< Indicates the number of free locations available to be written
+ to in the Periodic TxFIFO, max is 32768 */
+ __I uint32_t PTRQSA : 8; /*!< Indicates the number of free locations available to be written
+ in the Periodic Transmit Request Queue, max is 16 */
+ __I uint32_t TPTRQ_LAST : 1; /*!< last Entry in the periodic Tx Request Queue that is currently
+ being processed by the MAC */
+ __I uint32_t TPTRQ_TYPE : 2; /*!< type in the periodic Tx Request Queue that is currently being
+ processed by the MAC */
+ __I uint32_t TPTRQ_CH : 4; /*!< Channel of top of the periodic Transmit Request Queue */
+ __I uint32_t TPTRQ_ODD_FRAME: 1; /*!< If set, send in odd (micro)Frame */
+ } HPTXSTS_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t HAINT; /*!< Host All Channels Interrupt Register */
+
+ struct {
+ __I uint32_t INT : 16; /*!< Channel Interrupts, from 0 to 15. */
+ } HAINT_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HAINT_EN; /*!< Host All Channels Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t EN : 16; /*!< Channel Interrupts Enable, from 0 to 15. */
+ } HAINT_EN_b; /*!< BitSize */
+ };
+ __IO uint32_t HFLBA; /*!< The starting address of the Frame list */
+ __I uint32_t RESERVED6[8];
+
+ union {
+ __IO uint32_t __HPRT; /*!< Host Port Control and Status Register */
+
+ struct {
+ __I uint32_t PCS : 1; /*!< If a device is attached to the port */
+ __IO uint32_t PCD : 1; /*!< A device connection is detected */
+ __IO uint32_t PE : 1; /*!< Port Enable */
+ __IO uint32_t PEDC : 1; /*!< Set if when the status of the Port Enable (bit 2) of this register
+ changes */
+ __I uint32_t POA : 1; /*!< Indicates the overcurrent condition of the port */
+ __IO uint32_t POC : 1; /*!< Set if when the status of the Port Overcurrent Active bit (bit
+ 4) in this register changes */
+ __IO uint32_t PR : 1; /*!< Application and Core all can perform resume by setting, then
+ clear it whatever resume is success or not */
+ __IO uint32_t PS : 1; /*!< Sets this bit to put this port in Suspend mode */
+ __IO uint32_t PRESET : 1; /*!< sets this bit, a reset sequence is started on this port */
+ uint32_t : 1;
+ __IO uint32_t PLSDP : 1; /*!< Logic level of D+ */
+ __IO uint32_t PLSDN : 1; /*!< Logic level of D- */
+ __IO uint32_t PP : 1; /*!< this field to control power to this port. 1, power on */
+ __IO uint32_t PTC : 4; /*!< The application writes a nonzero value to this field to put
+ the port into a Test mode */
+ __I uint32_t SPEED : 2; /*!< Indicates the speed of the device attached to this port */
+ } __HPRT_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED7[47];
+
+ union {
+ __IO uint32_t HCC0; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC0_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED8;
+
+ union {
+ __IO uint32_t HCINT0; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN0; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ0; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA0; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA0_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED9;
+ __IO uint32_t HCDMAB0; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC1; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED10;
+
+ union {
+ __IO uint32_t HCINT1; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN1; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ1; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA1; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED11;
+ __IO uint32_t HCDMAB1; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC2; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC2_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED12;
+
+ union {
+ __IO uint32_t HCINT2; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT2_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN2; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN2_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ2; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ2_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA2; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA2_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED13;
+ __IO uint32_t HCDMAB2; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC3; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC3_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED14;
+
+ union {
+ __IO uint32_t HCINT3; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT3_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN3; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN3_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ3; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ3_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA3; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA3_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED15;
+ __IO uint32_t HCDMAB3; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC4; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC4_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED16;
+
+ union {
+ __IO uint32_t HCINT4; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT4_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN4; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN4_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ4; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ4_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA4; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA4_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED17;
+ __IO uint32_t HCDMAB4; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC5; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC5_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED18;
+
+ union {
+ __IO uint32_t HCINT5; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT5_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN5; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN5_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ5; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ5_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA5; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA5_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED19;
+ __IO uint32_t HCDMAB5; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC6; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC6_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED20;
+
+ union {
+ __IO uint32_t HCINT6; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT6_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN6; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN6_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ6; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ6_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA6; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA6_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED21;
+ __IO uint32_t HCDMAB6; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC7; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC7_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED22;
+
+ union {
+ __IO uint32_t HCINT7; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT7_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN7; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN7_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ7; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ7_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA7; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA7_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED23;
+ __IO uint32_t HCDMAB7; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC8; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC8_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED24;
+
+ union {
+ __IO uint32_t HCINT8; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT8_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN8; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN8_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ8; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ8_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA8; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA8_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED25;
+ __IO uint32_t HCDMAB8; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC9; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC9_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED26;
+
+ union {
+ __IO uint32_t HCINT9; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT9_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN9; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN9_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ9; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ9_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA9; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA9_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED27;
+ __IO uint32_t HCDMAB9; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC10; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC10_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED28;
+
+ union {
+ __IO uint32_t HCINT10; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT10_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN10; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN10_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ10; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ10_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA10; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA10_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED29;
+ __IO uint32_t HCDMAB10; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC11; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC11_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED30;
+
+ union {
+ __IO uint32_t HCINT11; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT11_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN11; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN11_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ11; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ11_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA11; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA11_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED31;
+ __IO uint32_t HCDMAB11; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC12; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC12_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED32;
+
+ union {
+ __IO uint32_t HCINT12; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT12_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN12; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN12_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ12; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ12_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA12; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA12_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED33;
+ __IO uint32_t HCDMAB12; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC13; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC13_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED34;
+
+ union {
+ __IO uint32_t HCINT13; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT13_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN13; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN13_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ13; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ13_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA13; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA13_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED35;
+ __IO uint32_t HCDMAB13; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC14; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC14_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED36;
+
+ union {
+ __IO uint32_t HCINT14; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT14_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN14; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN14_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ14; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ14_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA14; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA14_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED37;
+ __IO uint32_t HCDMAB14; /*!< Host Channel-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t HCC15; /*!< Host Channel Characteristics Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */
+ uint32_t : 1;
+ __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */
+ __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source
+ or sink. */
+ __IO uint32_t OF : 1; /*!< The frame is odd or even. */
+ __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */
+ __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not
+ yet. */
+ } HCC15_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED38;
+
+ union {
+ __IO uint32_t HCINT15; /*!< Host Channel Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT15_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCINT_EN15; /*!< Host Channel Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data
+ source or sink. */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ uint32_t : 8;
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */
+ __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */
+ } HCINT_EN15_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCTSIZ15; /*!< Host Channel Transfer Size Register */
+
+ struct {
+ __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that
+ microframe.Bit N indicates scheduling for Nth microframe scheduling
+ for 8th microframe in that frame. */
+ __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */
+ uint32_t : 13;
+ __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */
+ __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */
+ } HCTSIZ15_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t HCDMA15; /*!< Host Channel-n DMA Address Register */
+
+ struct {
+ uint32_t : 3;
+ __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */
+ __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */
+ } HCDMA15_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED39;
+ __IO uint32_t HCDMAB15; /*!< Host Channel-n DMA Buffer Address Register */
+ __I uint32_t RESERVED40[64];
+
+ union {
+ __IO uint32_t DCFG; /*!< Device Configuration Register */
+
+ struct {
+ __IO uint32_t DSPEED : 2; /*!< the maximum speed the application can support */
+ __IO uint32_t NZLSOH : 1; /*!< select the handshake the core sends on receiving a non zero-length
+ data packet during the OUT transaction of a control transfer's
+ Status stage */
+ __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */
+ __IO uint32_t DEVICE_ADDR: 7; /*!< The application must program this field after every SetAddress
+ control command */
+ __IO uint32_t PFI : 2; /*!< Indicates the time within a (micro)frame at which the application
+ must be notified using the End Of Periodic Frame Interrupt */
+ __IO uint32_t EDON : 1; /*!< If set the core sets NAK after Bulk OUT transfer complete */
+ uint32_t : 9;
+ __IO uint32_t EN_SG_DMA : 1; /*!< enable the Scatter/Gather DMA operation */
+ __IO uint32_t PSI : 2; /*!< Periodic Scheduling Interval */
+ __IO uint32_t RVP : 6; /*!< It controls the resume period when the core resumes from suspend */
+ } DCFG_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DCTL; /*!< Device Control Register */
+
+ struct {
+ __IO uint32_t RWS : 1; /*!< If set, the core initiates remote signaling to wake the USB
+ hosts */
+ __IO uint32_t SD : 1; /*!< If set, generates a device disconnect event to the USB host */
+ __I uint32_t GNPINS : 1; /*!< A NAK handshake is sent out on all non-periodic IN endpoints,
+ irrespective of the data availability in the transmit FIFO. */
+ __I uint32_t GONS : 1; /*!< No data is written to the RxFIFO, irrespective of space availability.. */
+ __IO uint32_t TC : 3; /*!< Test Control */
+ __O uint32_t SGNPIN : 1; /*!< A write to this field sets the Global Non-periodic IN NAK */
+ __O uint32_t CGNPIN : 1; /*!< A write to this field clears the Global Non-periodic IN NAK */
+ __O uint32_t SGON : 1; /*!< A write to this field sets the Global OUT NAK */
+ __O uint32_t CGON : 1; /*!< A write to this field sets the Global OUT NAK. */
+ __IO uint32_t POPD : 1; /*!< Power-On Programming Done */
+ __IO uint32_t GMC : 2; /*!< GMC must be programmed only once after initialization. the number
+ of packets to be serviced for that end point before moving to
+ the next end point */
+ uint32_t : 1;
+ __IO uint32_t IFNIE : 1; /*!< Ignore frame number for isochronous endpoints */
+ __IO uint32_t NBE : 1; /*!< Set NAK automatically on babble */
+ __IO uint32_t ECBNA : 1; /*!< After receiving BNA interrupt, the core disables the endpoint */
+ } DCTL_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t DSTS; /*!< Device Status Register */
+
+ struct {
+ __I uint32_t SUSPEND : 1; /*!< this bit is set as long as a Suspend condition is detected on
+ the USB */
+ __I uint32_t SPEED : 2; /*!< Indicates the speed at which the DWC_otg core has come up after
+ speed detection through a chirp sequence */
+ __I uint32_t EE : 1; /*!< reason of suspend state */
+ uint32_t : 4;
+ __I uint32_t SOFFN : 14; /*!< Frame or Microframe Number of the Received SOF */
+ __I uint32_t DLSDP : 1; /*!< Logic level of D+ */
+ __I uint32_t DLSDN : 1; /*!< Logic level of D- */
+ } DSTS_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED41;
+
+ union {
+ __IO uint32_t DIEPEN; /*!< Device IN Endpoint Common Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */
+ __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */
+ __IO uint32_t TIMEOUT : 1; /*!< Timeout Condition(Non-isochronous endpoints) */
+ __IO uint32_t ITRWTFE : 1; /*!< IN Token Received When TxFIFO Empty */
+ __IO uint32_t ITRWEPM : 1; /*!< IN Token received with EP Mismatch */
+ __IO uint32_t IENE : 1; /*!< IN Endpoint NAK Effective */
+ uint32_t : 1;
+ __IO uint32_t FU : 1; /*!< Fifo Underrun */
+ __IO uint32_t BNA : 1; /*!< BNA Interrupt */
+ uint32_t : 3;
+ __IO uint32_t NAK : 1; /*!< NAK interrupt */
+ } DIEPEN_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DOEPEN; /*!< Device OUT Endpoint Common Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */
+ __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */
+ __IO uint32_t SPD : 1; /*!< SETUP Phase Done, Applies to control endpoints only */
+ __IO uint32_t OTRWED : 1; /*!< OUT Token Received when Endpoint Disabled, Applies to control
+ OUT endpoints only */
+ __IO uint32_t SPR : 1; /*!< Status Phase Received */
+ __IO uint32_t BTBSPR : 1; /*!< Back-to-Back SETUP Packets Received, Applies to control OUT
+ endpoints only */
+ uint32_t : 1;
+ __IO uint32_t OPE : 1; /*!< OUT Packet Error */
+ __IO uint32_t BNA : 1; /*!< BNA Interrupt */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error interrupt */
+ __IO uint32_t NAK : 1; /*!< NAK interrupt */
+ __IO uint32_t NYET : 1; /*!< NYET interrupt */
+ } DOEPEN_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t DAINT; /*!< Device All Channels Interrupt Register */
+
+ struct {
+ __I uint32_t INT : 16; /*!< IN Endpoint Interrupt Bits, from 0 to 15. */
+ __I uint32_t OUT_INT : 16; /*!< OUT Endpoint Interrupt Bits, from 0 to 15. */
+ } DAINT_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DAINT_EN; /*!< Device All Channels Interrupt Enable Register */
+
+ struct {
+ __IO uint32_t IN_EN : 16; /*!< IN EP Interrupt Enable, from 0 to 15. */
+ __IO uint32_t OUT_EN : 16; /*!< OUT EP Interrupt Enable, from 0 to 15. */
+ } DAINT_EN_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED42[4];
+
+ union {
+ __IO uint32_t DTHRCTL; /*!< Device Threshold Control Register */
+
+ struct {
+ __IO uint32_t NISOINETE : 1; /*!< Non-ISO IN Endpoints Threshold Enable */
+ __IO uint32_t ISOINETE : 1; /*!< ISO IN Endpoints Threshold Enable */
+ __IO uint32_t TTL : 9; /*!< This field specifies Transmit thresholding size in DWORDS */
+ __IO uint32_t ATR : 2; /*!< These bits define the ratio between the AHB threshold and the
+ MAC threshold for the transmit path only. */
+ uint32_t : 3;
+ __IO uint32_t RTE : 1; /*!< If set, the core enables thresholding in the receive direction */
+ __IO uint32_t RTL : 9; /*!< This field specifies Receive thresholding size in DWORDS */
+ uint32_t : 1;
+ __IO uint32_t APE : 1; /*!< This bit controls internal DMA arbiter parking for IN endpoints */
+ } DTHRCTL_b; /*!< BitSize */
+ };
+ __IO uint16_t DIEPEMPEN; /*!< Device IN Endpoint FIFO Empty Interrupt Enable Register */
+ __I uint16_t RESERVED43[101];
+
+ union {
+ __IO uint32_t DIEPCTL0; /*!< Device Control IN Endpoint 0 Control Register */
+
+ struct {
+ __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint,
+ applies to IN and OUT endpoints */
+ uint32_t : 13;
+ __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active
+ in all configurations and interfaces */
+ uint32_t : 1;
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */
+ __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a
+ SETUP token is received for this endpoint */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ uint32_t : 2;
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL0_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED44;
+
+ union {
+ __IO uint32_t DIEPINT0; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT0_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED45;
+
+ union {
+ __IO uint32_t DIEPTSIZ0; /*!< Device IN Endpoint 0 Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ uint32_t : 12;
+ __IO uint32_t PACKET_CNT : 2; /*!< the total number of USB packets */
+ } DIEPTSIZ0_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA0; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA0; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED46;
+ __I uint32_t DIEPDMAB0; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL1; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED47;
+
+ union {
+ __IO uint32_t DIEPINT1; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED48;
+
+ union {
+ __IO uint32_t DIEPTSIZ1; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ1_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA1; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA1; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED49;
+ __I uint32_t DIEPDMAB1; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL2; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL2_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED50;
+
+ union {
+ __IO uint32_t DIEPINT2; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT2_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED51;
+
+ union {
+ __IO uint32_t DIEPTSIZ2; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ2_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA2; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA2; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED52;
+ __I uint32_t DIEPDMAB2; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL3; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL3_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED53;
+
+ union {
+ __IO uint32_t DIEPINT3; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT3_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED54;
+
+ union {
+ __IO uint32_t DIEPTSIZ3; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ3_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA3; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA3; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED55;
+ __I uint32_t DIEPDMAB3; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL4; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL4_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED56;
+
+ union {
+ __IO uint32_t DIEPINT4; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT4_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED57;
+
+ union {
+ __IO uint32_t DIEPTSIZ4; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ4_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA4; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA4; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED58;
+ __I uint32_t DIEPDMAB4; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL5; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL5_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED59;
+
+ union {
+ __IO uint32_t DIEPINT5; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT5_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED60;
+
+ union {
+ __IO uint32_t DIEPTSIZ5; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ5_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA5; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA5; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED61;
+ __I uint32_t DIEPDMAB5; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL6; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL6_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED62;
+
+ union {
+ __IO uint32_t DIEPINT6; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT6_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED63;
+
+ union {
+ __IO uint32_t DIEPTSIZ6; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ6_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA6; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA6; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED64;
+ __I uint32_t DIEPDMAB6; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL7; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL7_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED65;
+
+ union {
+ __IO uint32_t DIEPINT7; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT7_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED66;
+
+ union {
+ __IO uint32_t DIEPTSIZ7; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ7_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA7; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA7; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED67;
+ __I uint32_t DIEPDMAB7; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL8; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL8_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED68;
+
+ union {
+ __IO uint32_t DIEPINT8; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT8_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED69;
+
+ union {
+ __IO uint32_t DIEPTSIZ8; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ8_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA8; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA8; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED70;
+ __I uint32_t DIEPDMAB8; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL9; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL9_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED71;
+
+ union {
+ __IO uint32_t DIEPINT9; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT9_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED72;
+
+ union {
+ __IO uint32_t DIEPTSIZ9; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ9_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA9; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA9; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED73;
+ __I uint32_t DIEPDMAB9; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL10; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL10_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED74;
+
+ union {
+ __IO uint32_t DIEPINT10; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT10_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED75;
+
+ union {
+ __IO uint32_t DIEPTSIZ10; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ10_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA10; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA10; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED76;
+ __I uint32_t DIEPDMAB10; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL11; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL11_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED77;
+
+ union {
+ __IO uint32_t DIEPINT11; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT11_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED78;
+
+ union {
+ __IO uint32_t DIEPTSIZ11; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ11_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA11; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA11; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED79;
+ __I uint32_t DIEPDMAB11; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL12; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL12_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED80;
+
+ union {
+ __IO uint32_t DIEPINT12; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT12_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED81;
+
+ union {
+ __IO uint32_t DIEPTSIZ12; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ12_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA12; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA12; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED82;
+ __I uint32_t DIEPDMAB12; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL13; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL13_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED83;
+
+ union {
+ __IO uint32_t DIEPINT13; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT13_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED84;
+
+ union {
+ __IO uint32_t DIEPTSIZ13; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ13_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA13; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA13; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED85;
+ __I uint32_t DIEPDMAB13; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL14; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL14_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED86;
+
+ union {
+ __IO uint32_t DIEPINT14; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT14_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED87;
+
+ union {
+ __IO uint32_t DIEPTSIZ14; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ14_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA14; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA14; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED88;
+ __I uint32_t DIEPDMAB14; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DIEPCTL15; /*!< Device IN Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ uint32_t : 1;
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an
+ endpoint even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ transmit is setup */
+ } DIEPCTL15_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED89;
+
+ union {
+ __IO uint32_t DIEPINT15; /*!< Device IN Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this
+ endpoint */
+ __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */
+ __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */
+ __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DIEPINT15_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED90;
+
+ union {
+ __IO uint32_t DIEPTSIZ15; /*!< Device IN Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints.
+ The number of packets must be fetched per non-periodic IN endpoints */
+ } DIEPTSIZ15_b; /*!< BitSize */
+ };
+ __IO uint32_t DIEPDMA15; /*!< Device IN Endpoint-n DMA Address Register */
+ __IO uint16_t DTXFSA15; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */
+ __I uint16_t RESERVED91;
+ __I uint32_t DIEPDMAB15; /*!< Device IN Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL0; /*!< Device Control OUT Endpoint 0 Control Register */
+
+ struct {
+ __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint,
+ applies to IN and OUT endpoints */
+ uint32_t : 13;
+ __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active
+ in all configurations and interfaces */
+ uint32_t : 1;
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */
+ __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */
+ __IO uint32_t SNOOP : 1; /*!< does not check if the OUT packets are correct before transferring */
+ __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a
+ SETUP token is received for this endpoint */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ uint32_t : 2;
+ __I uint32_t EPD : 1; /*!< The application cannot disable control OUT endpoint 0 */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL0_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED92;
+
+ union {
+ __IO uint32_t DOEPINT0; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT0_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED93;
+
+ union {
+ __IO uint32_t DOEPTSIZ0; /*!< Device OUT Endpoint 0 Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ uint32_t : 12;
+ __IO uint32_t PACKET_CNT : 1; /*!< This field is decremented to zero after a packet is written
+ into the RxFIFO */
+ uint32_t : 9;
+ __IO uint32_t SETUP_CNT : 2; /*!< the number of back-to-back SETUP data packets the endpoint can
+ receive */
+ } DOEPTSIZ0_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA0; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED94;
+ __I uint32_t DOEPDMAB0; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL1; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED95;
+
+ union {
+ __IO uint32_t DOEPINT1; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT1_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED96;
+
+ union {
+ __IO uint32_t DOEPTSIZ1; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ1_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA1; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED97;
+ __I uint32_t DOEPDMAB1; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL2; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL2_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED98;
+
+ union {
+ __IO uint32_t DOEPINT2; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT2_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED99;
+
+ union {
+ __IO uint32_t DOEPTSIZ2; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ2_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA2; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED100;
+ __I uint32_t DOEPDMAB2; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL3; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL3_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED101;
+
+ union {
+ __IO uint32_t DOEPINT3; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT3_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED102;
+
+ union {
+ __IO uint32_t DOEPTSIZ3; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ3_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA3; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED103;
+ __I uint32_t DOEPDMAB3; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL4; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL4_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED104;
+
+ union {
+ __IO uint32_t DOEPINT4; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT4_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED105;
+
+ union {
+ __IO uint32_t DOEPTSIZ4; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ4_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA4; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED106;
+ __I uint32_t DOEPDMAB4; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL5; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL5_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED107;
+
+ union {
+ __IO uint32_t DOEPINT5; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT5_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED108;
+
+ union {
+ __IO uint32_t DOEPTSIZ5; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ5_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA5; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED109;
+ __I uint32_t DOEPDMAB5; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL6; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL6_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED110;
+
+ union {
+ __IO uint32_t DOEPINT6; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT6_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED111;
+
+ union {
+ __IO uint32_t DOEPTSIZ6; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ6_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA6; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED112;
+ __I uint32_t DOEPDMAB6; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL7; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL7_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED113;
+
+ union {
+ __IO uint32_t DOEPINT7; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT7_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED114;
+
+ union {
+ __IO uint32_t DOEPTSIZ7; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ7_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA7; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED115;
+ __I uint32_t DOEPDMAB7; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL8; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL8_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED116;
+
+ union {
+ __IO uint32_t DOEPINT8; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT8_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED117;
+
+ union {
+ __IO uint32_t DOEPTSIZ8; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ8_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA8; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED118;
+ __I uint32_t DOEPDMAB8; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL9; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL9_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED119;
+
+ union {
+ __IO uint32_t DOEPINT9; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT9_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED120;
+
+ union {
+ __IO uint32_t DOEPTSIZ9; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ9_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA9; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED121;
+ __I uint32_t DOEPDMAB9; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL10; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL10_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED122;
+
+ union {
+ __IO uint32_t DOEPINT10; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT10_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED123;
+
+ union {
+ __IO uint32_t DOEPTSIZ10; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ10_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA10; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED124;
+ __I uint32_t DOEPDMAB10; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL11; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL11_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED125;
+
+ union {
+ __IO uint32_t DOEPINT11; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT11_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED126;
+
+ union {
+ __IO uint32_t DOEPTSIZ11; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ11_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA11; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED127;
+ __I uint32_t DOEPDMAB11; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL12; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL12_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED128;
+
+ union {
+ __IO uint32_t DOEPINT12; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT12_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED129;
+
+ union {
+ __IO uint32_t DOEPTSIZ12; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ12_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA12; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED130;
+ __I uint32_t DOEPDMAB12; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL13; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL13_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED131;
+
+ union {
+ __IO uint32_t DOEPINT13; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT13_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED132;
+
+ union {
+ __IO uint32_t DOEPTSIZ13; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ13_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA13; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED133;
+ __I uint32_t DOEPDMAB13; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL14; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL14_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED134;
+
+ union {
+ __IO uint32_t DOEPINT14; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT14_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED135;
+
+ union {
+ __IO uint32_t DOEPTSIZ14; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ14_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA14; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED136;
+ __I uint32_t DOEPDMAB14; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+
+ union {
+ __IO uint32_t DOEPCTL15; /*!< Device OUT Endpoint N Control Register */
+
+ struct {
+ __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */
+ uint32_t : 4;
+ __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */
+ __I uint32_t DPID : 1; /*!< Endpoint Data PID */
+ __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if
+ set */
+ __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */
+ __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */
+ __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens.
+ To control endpoints, response an ACK */
+ uint32_t : 4;
+ __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */
+ __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */
+ __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */
+ __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */
+ __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint
+ even before the transfer for that endpoint is complete */
+ __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to
+ receive data is setup */
+ } DOEPCTL15_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED137;
+
+ union {
+ __IO uint32_t DOEPINT15; /*!< Device OUT Endpoint-n Interrupt Register */
+
+ struct {
+ __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */
+ __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */
+ __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */
+ __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control
+ endpoint is complete */
+ __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */
+ __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data
+ phase to the status phase of a Control Write transfer */
+ __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back
+ SETUP packets for this particular endpoint */
+ __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */
+ __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */
+ __IO uint32_t BNA : 1; /*!< Buffer Not Available */
+ uint32_t : 2;
+ __IO uint32_t BE : 1; /*!< Babble Error */
+ __IO uint32_t NAK : 1; /*!< a NAK is transmitted */
+ __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */
+ } DOEPINT15_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED138;
+
+ union {
+ __IO uint32_t DOEPTSIZ15; /*!< Device OUT Endpoint-n Transfer Size Register */
+
+ struct {
+ __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */
+ __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */
+ __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets.
+ To isochronous OUT endpoints, data PID received in the last
+ packet */
+ } DOEPTSIZ15_b; /*!< BitSize */
+ };
+ __IO uint32_t DOEPDMA15; /*!< Device OUT Endpoint-n DMA Address Register */
+ __I uint32_t RESERVED139;
+ __I uint32_t DOEPDMAB15; /*!< Device OUT Endpoint-n DMA Buffer Address Register */
+} USB_Type;
+
+
+/* ================================================================================ */
+/* ================ GLOBAL_CTRL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief GLOBAL_CTRL (GLOBAL_CTRL)
+ */
+
+typedef struct { /*!< GLOBAL_CTRL Structure */
+
+ union {
+ __I uint32_t AES_STATUS; /*!< AES status */
+
+ struct {
+ __I uint32_t RD_ALMOST_EMPTY: 1; /*!< FIFO read almost empty */
+ __I uint32_t RD_EMPTY : 1; /*!< FIFO read empty */
+ __I uint32_t WR_FULL_ALMOST: 1; /*!< FIFO write almost full */
+ __I uint32_t WR_FULL : 1; /*!< FIFO write full */
+ __I uint32_t IDLE : 1; /*!< decryption finish */
+ } AES_STATUS_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED0[253];
+
+ union {
+ __IO uint32_t CLK_SEL_0; /*!< clock select 0 */
+
+ struct {
+ __IO uint32_t CAN1_CLK : 2; /*!< CAN1 clock frequency dividor based on system clock, which should
+ be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t CAN0_CLK : 2; /*!< CAN0 clock frequency dividor based on system clock, which should
+ be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t I2C1_CLK : 2; /*!< I2C1 clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t I2C0_CLK : 2; /*!< I2C0 clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t SPI1_CLK : 2; /*!< SPI1 clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t SPI0_CLK : 2; /*!< SPI0 clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t UART1_CLK : 2; /*!< UART1 clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t UART0_CLK : 2; /*!< UART0 clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t RTC_CLK : 2; /*!< RTC clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t GPIO_CLK : 2; /*!< GPIO clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t TIMER_CLK : 2; /*!< TIMER clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t WDG_CLK : 2; /*!< watchdog clock frequency dividor based on system clock, which
+ should be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ uint32_t : 2;
+ __IO uint32_t FLASH_CLK : 2; /*!< FLASH clock frequency dividor based on system clock, which should
+ be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */
+ __IO uint32_t DMA_AHB_CLK: 2; /*!< DMA AHB bus clock frequency dividor based on system clock, which
+ should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */
+ __IO uint32_t USB_AHB_CLK: 2; /*!< USB AHB bus clock frequency dividor based on system clock, which
+ should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */
+ } CLK_SEL_0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CLK_SEL_1; /*!< clock select 1 */
+
+ struct {
+ __IO uint32_t ETH_AHB_CLK: 2; /*!< ETH_AHB clock frequency dividor based on system clock, which
+ should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */
+ __IO uint32_t DDR_CLK : 2; /*!< DDR clock frequency dividor based on system clock, which should
+ be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */
+ uint32_t : 4;
+ __IO uint32_t ADC_CLK : 2; /*!< ADC clock frequency dividor based on system clock, which should
+ be 1/8, 1/16, 1/32, external from 0 to 3 */
+ __IO uint32_t EFUSE_CLK : 2; /*!< EFUSE clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t SYS_CLK : 4; /*!< system clock clock frequency dividor based on system clock,
+ which should be oscillator(0), DLL(1), crystal(2), external(3),
+ JTAG(4), PS(8) */
+ __IO uint32_t UART2_CLK : 2; /*!< UART2 clock frequency dividor based on system clock, which should
+ be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */
+ __IO uint32_t UTMI_CLK : 1; /*!< UTMI clock came from on-chip usb phy(0) or off-chip usb phy(1) */
+ } CLK_SEL_1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t USB_PHY_CTRL; /*!< USB Phy Control Register */
+
+ struct {
+ __IO uint32_t BITSTUFF : 1; /*!< 0: No bit stuff */
+ __IO uint32_t XTLSEL : 1; /*!< 0: 12MHz */
+ __IO uint32_t PLL : 1; /*!< PLL mode */
+ __IO uint32_t VOLDET : 1; /*!< Voltage Detector Enable, 0: Disable */
+ __IO uint32_t IDUP : 1; /*!< 0: ID is uplled up through 33k Ohm resister */
+ __IO uint32_t CKISEL : 1; /*!< Clock selection, 0: Crystal, 1: Internal Clock */
+ __IO uint32_t FMOD : 1; /*!< 1: Normal */
+ __IO uint32_t SQUELCH : 3; /*!< Squelch Reference Voltage, 000: 27.5mV, 001: 137.5mV, 111: 220mV */
+ __IO uint32_t HDISCDT : 3; /*!< Host Disconnect Detection Reference Voltage, 000: 500mV, 100:
+ 588mV, 111: 654mV */
+ __IO uint32_t PRTSEL : 1; /*!< 0: Internal OTG PHY, 1: UTMI to External PHY */
+ __IO uint32_t RSTPRT : 1; /*!< 0: The reverse of usb_rst_n will reset, 1: Reset OTG PHY */
+ } USB_PHY_CTRL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RTC_INT_EN; /*!< RTC interrupt enable Register */
+
+ struct {
+ __IO uint32_t SECOND : 1; /*!< 1s interrupt enable */
+ __IO uint32_t MICROSECOND: 1; /*!< 1ms interrupt enable */
+ } RTC_INT_EN_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED1;
+
+ union {
+ __IO uint32_t NMI_SEL; /*!< nmi interrupt selection */
+
+ struct {
+ __IO uint32_t NMI : 7; /*!< NMI interrupt ID */
+ } NMI_SEL_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED2;
+ __IO uint32_t AES_TARGET_ADDR; /*!< AES target address, default is frame decoder address(0x41800000) */
+
+ union {
+ __IO uint32_t AES_BURST_TYPE; /*!< AES burst type */
+
+ struct {
+ __IO uint32_t TYPE : 2; /*!< burst type, fixed(0), incr(1) */
+ } AES_BURST_TYPE_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED3[3];
+
+ union {
+ __IO uint32_t ICACHE; /*!< ICACHE Enable */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< ICACHE Enable */
+ } ICACHE_b; /*!< BitSize */
+ };
+ __IO uint32_t IBUSOFF; /*!< Code Bus Offset */
+ __IO uint32_t DBUSOFF; /*!< Data Bus Offset */
+ __IO uint32_t EXTADDR; /*!< Bus Ext Addr */
+} GLOBAL_CTRL_Type;
+
+
+/* ================================================================================ */
+/* ================ AES ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief AES (AES)
+ */
+
+typedef struct { /*!< AES Structure */
+ __IO uint32_t FIFO; /*!< data FIFO to be decoded */
+
+ union {
+ __O uint32_t FIFO_CLEAR; /*!< clear data FIFO */
+
+ struct {
+ __O uint32_t CLEAR : 1; /*!< clear after write 1 and write 0 */
+ } FIFO_CLEAR_b; /*!< BitSize */
+ };
+} AES_Type;
+
+
+/* ================================================================================ */
+/* ================ DDRC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief DDR_CFG (DDRC)
+ */
+
+typedef struct { /*!< DDRC Structure */
+ __IO uint32_t CMD; /*!< DDR commands to program */
+
+ union {
+ __IO uint32_t CTRL; /*!< DDR Control */
+
+ struct {
+ __IO uint32_t TO : 1; /*!< Take over DDRC siggen */
+ __IO uint32_t CLR : 1; /*!< Clear commands in FIFO */
+ __O uint32_t STR : 1; /*!< Start to execute the commands in FIFO */
+ } CTRL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t MODE; /*!< DDR mode */
+
+ struct {
+ __IO uint32_t MODE : 6; /*!< DDRC Mode */
+ uint32_t : 2;
+ __IO uint32_t LANE : 1; /*!< LANE synchronization logic bypass */
+ uint32_t : 7;
+ __IO uint32_t B16 : 2; /*!< Active 16 bit DQ position when the unmber of DQ IO is 16 */
+ uint32_t : 6;
+ __IO uint32_t CLKPOL : 2; /*!< DQS clkpol set by user on the PHY */
+ } MODE_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t QUE; /*!< DDRC queue depth */
+
+ struct {
+ __IO uint32_t DEPTH : 1; /*!< DDRC queue depth */
+ } QUE_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t REF; /*!< Refresh control */
+
+ struct {
+ __IO uint32_t THRD : 5; /*!< Number of refresh requests which can be postponed */
+ uint32_t : 3;
+ __IO uint32_t TRIG : 4; /*!< Number of refresh requests every dl_refi */
+ uint32_t : 4;
+ __IO uint32_t TIME : 16; /*!< Refresh interval time */
+ } REF_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint32_t REF_TRIG; /*!< Refresh trigger */
+
+ struct {
+ __O uint32_t GO : 1; /*!< Write 1 to trigger one refresh request by cbus */
+ } REF_TRIG_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint32_t ZQ_TRIG; /*!< ZQCTL trigger */
+
+ struct {
+ __O uint32_t CS : 1; /*!< Write 1 to trigger one ZQCS request by cbus */
+ __O uint32_t CL : 1; /*!< Write 1 to trigger one ZQCL request by cbus */
+ } ZQ_TRIG_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ZQCSR; /*!< ZQCSR */
+
+ struct {
+ __IO uint32_t EN : 1; /*!< Enable ZQCS request */
+ __IO uint32_t PRI : 1; /*!< 0: DMA access prior to ZQCS, 1: ZQCS prior to DMA access */
+ } ZQCSR_b; /*!< BitSize */
+ };
+ __IO uint32_t ZQCSI; /*!< ZQCS interval time */
+
+ union {
+ __IO uint32_t RCD; /*!< t(RCD) */
+
+ struct {
+ __IO uint32_t DI : 5; /*!< t(RCD), delay from ACT command to RW command of same bank */
+ } RCD_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RAS; /*!< t(RAS) */
+
+ struct {
+ __IO uint32_t DI : 6; /*!< t(RAS), delay from ACT command to PRE command of same bank */
+ } RAS_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RP; /*!< t(RP) */
+
+ struct {
+ __IO uint32_t DI : 5; /*!< t(RP), delay from PRE command to ACT/REF/ZQ command */
+ uint32_t : 3;
+ __IO uint32_t RPA : 1; /*!< 0: t(RP) delay for PREA command; 1: t(RP)+1 delay for PREA command */
+ } RP_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RC; /*!< t(RC) */
+
+ struct {
+ __IO uint32_t DI : 7; /*!< t(RC), delay from ACT command to ACT command of same bank */
+ } RC_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RRD; /*!< t(RRD) */
+
+ struct {
+ __IO uint32_t DI : 4; /*!< t(RRD), delay from ACT command to ACT command */
+ } RRD_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t CCD; /*!< t(CCD) */
+
+ struct {
+ __IO uint32_t DI : 3; /*!< t(CCD), delay from RW command to RW command */
+ } CCD_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RTW; /*!< t(RTW) */
+
+ struct {
+ __IO uint32_t DI : 5; /*!< t(RTW), delay from RD command to WR command */
+ } RTW_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t WTR; /*!< t(WTR) */
+
+ struct {
+ __IO uint32_t DI : 5; /*!< t(WTR), delay from WR command to RD command */
+ } WTR_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RTP; /*!< t(RTP) */
+
+ struct {
+ __IO uint32_t DI : 3; /*!< t(RTP), delay from RD command to PRE command of same bank */
+ } RTP_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t WTP; /*!< t(WTP) */
+
+ struct {
+ __IO uint32_t DI : 6; /*!< t(WTP), delay from WR command to PRE command of same bank */
+ } WTP_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RFC; /*!< t(RFC) */
+
+ struct {
+ __IO uint32_t DI : 8; /*!< t(WTP), delay from WR command to PRE command of same bank */
+ } RFC_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ZQCL; /*!< t(ZQoper) */
+
+ struct {
+ __IO uint32_t DI : 9; /*!< t(ZQoper), delay from ZQCL command to REF/ZQ/ACT command */
+ } ZQCL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ZQCS; /*!< t(ZQCS) */
+
+ struct {
+ __IO uint32_t DI : 7; /*!< t(ZQCS), delay from ZQCS command to REF/ZQ/ACT command */
+ } ZQCS_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t FAW; /*!< t(FAW) */
+
+ struct {
+ __IO uint32_t DI : 6; /*!< t(FAW), 4 act command window time */
+ } FAW_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t BURST; /*!< BURST */
+
+ struct {
+ __IO uint32_t LEN : 1; /*!< 0: length 8, 1: length 4 */
+ } BURST_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t PHUNG; /*!< PHUNG */
+
+ struct {
+ __IO uint32_t MODE : 1; /*!< 0: normal mode, 1: prevent read hang mode */
+ __IO uint32_t LPM : 1; /*!< 1: stop the IO clk */
+ } PHUNG_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RL; /*!< READ Latency */
+
+ struct {
+ __IO uint32_t VAL : 5; /*!< READ Latency */
+ } RL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t WL; /*!< WRITE Latency */
+
+ struct {
+ __IO uint32_t VAL : 5; /*!< WRITE Latency */
+ } WL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t TRAIN; /*!< TRAIN */
+
+ struct {
+ __IO uint32_t EN : 4; /*!< Enable lane N training mode */
+ } TRAIN_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DQSEN0; /*!< Delay cycles of dqsen of byte lane 0 */
+
+ struct {
+ __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 0 */
+ } DQSEN0_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DQSEN1; /*!< Delay cycles of dqsen of byte lane 1 */
+
+ struct {
+ __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 1 */
+ } DQSEN1_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DQSEN2; /*!< Delay cycles of dqsen of byte lane 2 */
+
+ struct {
+ __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 2 */
+ } DQSEN2_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t DQSEN3; /*!< Delay cycles of dqsen of byte lane 0 */
+
+ struct {
+ __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 3 */
+ } DQSEN3_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ODTH; /*!< Delay from WR command to odt high transition */
+
+ struct {
+ __IO uint32_t DL : 5; /*!< Delay from WR command to odt high transition */
+ } ODTH_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ODTL; /*!< Delay from WR command to odt low transition */
+
+ struct {
+ __IO uint32_t DL : 5; /*!< Delay from WR command to odt low transition */
+ } ODTL_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint32_t ODT; /*!< Used in write leveling mode */
+
+ struct {
+ __O uint32_t TRIG : 1; /*!< 0: trigger odt low, 1: trigger odt high */
+ } ODT_b; /*!< BitSize */
+ };
+
+ union {
+ __O uint32_t DQS; /*!< Used in write leveling mode */
+
+ struct {
+ __O uint32_t TRIG : 1; /*!< Writing 1 to this register triggers a dqs pulse */
+ } DQS_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t STA; /*!< Commands FIFO */
+
+ struct {
+ __I uint32_t MODE : 1; /*!< DDRC in sw_proc mode */
+ __I uint32_t EMPTY : 1; /*!< Sw_proc command fifo empty */
+ __I uint32_t FULL : 1; /*!< Sw_proc command fifo full */
+ } STA_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INTCTL; /*!< Interrupt Control */
+
+ struct {
+ __IO uint32_t DONE : 1; /*!< 0: the sw_proc_done int will not be masked, 1: the sw_proc_done
+ int will be masked */
+ __IO uint32_t ERR : 1; /*!< mask of the lane_sync_error interrupt */
+ uint32_t : 14;
+ __IO uint32_t MODE : 1; /*!< Interrupt mode: 0: int level active, write 1 to clear; 1: int
+ edge active */
+ } INTCTL_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INTRAW; /*!< Interrupt RAW */
+
+ struct {
+ __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done before mask */
+ __IO uint32_t ERR : 1; /*!< int reg of the lane sync error before masked */
+ } INTRAW_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t INTSTA; /*!< Interrupt STA */
+
+ struct {
+ __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done after mask */
+ __IO uint32_t ERR : 1; /*!< int register of lane sync error after masked */
+ } INTSTA_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t PHY; /*!< PHY */
+
+ struct {
+ __IO uint32_t RST : 1; /*!< FPGA version, reset read dq fifo. Low active */
+ } PHY_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RDQ; /*!< FPGA version, read dq delay of byte lane N */
+
+ struct {
+ __IO uint32_t L3 : 6; /*!< FPGA version, read dq delay of byte lane3 */
+ uint32_t : 2;
+ __IO uint32_t L2 : 6; /*!< FPGA version, read dq delay of byte lane2 */
+ uint32_t : 2;
+ __IO uint32_t L1 : 6; /*!< FPGA version, read dq delay of byte lane3 */
+ uint32_t : 2;
+ __IO uint32_t L0 : 7; /*!< FPGA version, read dq delay of byte lane0 */
+ } RDQ_b; /*!< BitSize */
+ };
+
+ union {
+ __I uint32_t CALIB; /*!< calibration */
+
+ struct {
+ __I uint32_t TPU : 8; /*!< calibration result values, if fail then 0x40 */
+ __I uint32_t TPD : 8; /*!< calibration result values, if fail then 0x40 */
+ __I uint32_t PDR : 5; /*!< calibration result values, if fail then 0x40 */
+ __I uint32_t NDR : 5; /*!< calibration result values, if fail then 0x40 */
+ uint32_t : 5;
+ __IO uint32_t EN : 1; /*!< trigger the calibration processing which is sensitive to the
+ positive edge */
+ } CALIB_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t ITMDLY; /*!< "itmdly" is the fine delay trim to the read path "dq", "itmsdly"
+ is to the read path of "dqs". From 000 to 111 increasingly,
+ each step is about 40ps */
+
+ struct {
+ __IO uint32_t I0 : 4; /*!< itmdly0 */
+ __IO uint32_t IS0 : 4; /*!< itmsdly0 */
+ __IO uint32_t I1 : 4; /*!< itmdly1 */
+ __IO uint32_t IS1 : 4; /*!< itmsdly1 */
+ __IO uint32_t I2 : 4; /*!< itmdly2 */
+ __IO uint32_t IS2 : 4; /*!< itmsdly2 */
+ __IO uint32_t I3 : 4; /*!< itmdly3 */
+ __IO uint32_t IS3 : 4; /*!< itmsdly3 */
+ } ITMDLY_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t TUNE; /*!< CALIB_TUNE */
+
+ struct {
+ __IO uint32_t TPU : 4; /*!< tpu_tune, finial val = tune[3] ? val - tune : val + tune */
+ __IO uint32_t TPD : 4; /*!< tpd_tune, tune[3:0] for TPD/TPU, [2:0] is the tune val */
+ __IO uint32_t PDR : 4; /*!< pdr_tune, inial val = tune[2] ? val - tune : val + tune */
+ __IO uint32_t NDR : 4; /*!< ndr_tune, tune[2:0] for NDR/PDR, [1:0] is the tune val */
+ } TUNE_b; /*!< BitSize */
+ };
+
+ union {
+ __IO uint32_t RD_SEL; /*!< RD_WINDOWS_SEL */
+
+ struct {
+ __IO uint32_t PHY_SEL : 3; /*!< To fix the phy read valid issue, this is to adjust the read
+ data valid window to match the phy read valid by cycle level */
+ } RD_SEL_b; /*!< BitSize */
+ };
+} DDRC_Type;
+
+
+/* ================================================================================ */
+/* ================ PDLOCK ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief PLL DLL LOCK (PDLOCK)
+ */
+
+typedef struct { /*!< PDLOCK Structure */
+
+ union {
+ __I uint32_t GCLK; /*!< GCLK */
+
+ struct {
+ __I uint32_t C1R2P : 1; /*!< gclk_c1r2_pll_lock */
+ __I uint32_t C1R1P : 1; /*!< gclk_c1r1_pll_lock */
+ __I uint32_t C2R1P : 1; /*!< gclk_c2r1_pll_lock */
+ __I uint32_t C2R2P : 1; /*!< gclk_c2r2_pll_lock */
+ __I uint32_t C1R2D : 1; /*!< gclk_c1r2_dll_lock */
+ __I uint32_t C1R1D : 1; /*!< gclk_c1r1_dll_lock */
+ __I uint32_t C2R1D : 1; /*!< gclk_c2r1_dll_lock */
+ __I uint32_t C2R2D : 1; /*!< gclk_c2r2_dll_lock */
+ } GCLK_b; /*!< BitSize */
+ };
+} PDLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================ PDPROT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief PLL DLL PROTECT (PDPROT)
+ */
+
+typedef struct { /*!< PDPROT Structure */
+
+ union {
+ __O uint32_t LOCK; /*!< LOCK */
+
+ struct {
+ __O uint32_t EN : 1; /*!< Enable the PLL DLL Lock to Protect it */
+ } LOCK_b; /*!< BitSize */
+ };
+} PDPROT_Type;
+
+
+/* ================================================================================ */
+/* ================ CFG_CTRL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief CFG_CTRL (CFG_CTRL)
+ */
+
+typedef struct { /*!< CFG_CTRL Structure */
+ __I uint32_t RESERVED0[3];
+
+ union {
+ __IO uint32_t DONE; /*!< DONE CFG */
+
+ struct {
+ __IO uint32_t CMD : 1; /*!< Write 1 indicate all chain data write over */
+ __IO uint32_t STA : 1; /*!< 1= all chain config process over, chip is in user mode */
+ } DONE_b; /*!< BitSize */
+ };
+ __I uint32_t RESERVED1[34];
+
+ union {
+ __IO uint32_t PDLLSTR; /*!< PLL DLL RESET */
+
+ struct {
+ __IO uint32_t C1R1P : 1; /*!< C1r1_rstpll_n, low active */
+ __IO uint32_t C1R2P : 1; /*!< C1r2_rstpll_n, low active */
+ __IO uint32_t C2R1P : 1; /*!< C2r1_rstpll_n, low active */
+ __IO uint32_t C2R2P : 1; /*!< C2r2_rstpll_n, low active */
+ __IO uint32_t C1R1D : 1; /*!< C1r1_rstdll_n, low active */
+ __IO uint32_t C1R2D : 1; /*!< C1r2_rstdll_n, low active */
+ __IO uint32_t C2R1D : 1; /*!< C2r1_rstdll_n, low active */
+ __IO uint32_t C2R2D : 1; /*!< C2r2_rstdll_n, low active */
+ } PDLLSTR_b; /*!< BitSize */
+ };
+} CFG_CTRL_Type;
+
+
+/* ================================================================================ */
+/* ================ SOFT_RESET ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SUB SOFT RESET (SOFT_RESET)
+ */
+
+typedef struct { /*!< SOFT_RESET Structure */
+
+ union {
+ __IO uint32_t SOFTRST; /*!< SOFTRST */
+
+ struct {
+ __IO uint32_t CAN1_n : 1; /*!< soft_rst_can1_n */
+ __IO uint32_t CAN0_n : 1; /*!< soft_rst_can0_n */
+ __IO uint32_t I2C1_n : 1; /*!< soft_rst_i2c1_n */
+ __IO uint32_t I2C0_n : 1; /*!< soft_rst_i2c0_n */
+ __IO uint32_t SPI1_n : 1; /*!< soft_rst_spi1_n */
+ __IO uint32_t SPI0_n : 1; /*!< soft_rst_spi0_n */
+ __IO uint32_t UART1_n : 1; /*!< soft_rst_uart1_n */
+ __IO uint32_t UART0_n : 1; /*!< soft_rst_uart0_n */
+ __IO uint32_t RTC_n : 1; /*!< soft_rst_rtc_n */
+ __IO uint32_t GPIO_n : 1; /*!< soft_rst_gpio_n */
+ __IO uint32_t TIMER_n : 1; /*!< soft_rst_timer_n */
+ __IO uint32_t WDT_n : 1; /*!< soft_rst_wdt_n */
+ __IO uint32_t LVDS_n : 1; /*!< soft_rst_lvds_n */
+ __IO uint32_t FLS_n : 1; /*!< soft_rst_fls_n */
+ __IO uint32_t DMAC_AHB_n : 1; /*!< soft_rst_dmac_ahb_n */
+ __IO uint32_t USB_AHB_n : 1; /*!< soft_rst_usb_ahb_n */
+ __IO uint32_t ETH_AHB_n : 1; /*!< soft_rst_eth_ahb_n */
+ __IO uint32_t DDRC_n : 1; /*!< soft_rst_ddrc_n */
+ __IO uint32_t ARM_HCLK_n : 1; /*!< soft_rst_arm_HCLK_n */
+ __IO uint32_t _48_n : 1; /*!< soft_rst_48_n */
+ __IO uint32_t UTM_n : 1; /*!< soft_rst_utmi_n */
+ __IO uint32_t CACHE_n : 1; /*!< soft_rst_cache_n */
+ __IO uint32_t USB_n : 1; /*!< soft_rst_cache_n */
+ __IO uint32_t ETH_RX_n : 1; /*!< soft_rst_eth_rx_i_n */
+ __IO uint32_t ETH_TX_n : 1; /*!< soft_rst_eth_tx_i_n */
+ __IO uint32_t ADC_n : 1; /*!< soft_rst_adc_n */
+ __IO uint32_t EFUSE_n : 1; /*!< soft_rst_efuse_n */
+ __IO uint32_t Reserved1_n: 1; /*!< Reserved11 */
+ __IO uint32_t AES_n : 1; /*!< soft_rst_aes_n */
+ __IO uint32_t UART2_n : 1; /*!< soft_rst_uart2_n */
+ __IO uint32_t AS_n : 1; /*!< soft_rst_as_n */
+ __IO uint32_t FDCD_n : 1; /*!< soft_rst_fdcd_n */
+ } SOFTRST_b; /*!< BitSize */
+ };
+} SOFT_RESET_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define UART0_BASE 0x41005000UL
+#define UART1_BASE 0x4100C000UL
+#define UART2_BASE 0x4100E000UL
+#define WDG_BASE 0x41001000UL
+#define TIMER0_BASE 0x41000000UL
+#define TIMER1_BASE 0x41000020UL
+#define TIMER2_BASE 0x41000040UL
+#define TIMER3_BASE 0x41000060UL
+#define SPI0_BASE 0x41004000UL
+#define SPI1_BASE 0x4100B000UL
+#define I2C0_BASE 0x41003000UL
+#define I2C1_BASE 0x4100A000UL
+#define RTC_BASE 0x41007004UL
+#define GPIO_BASE 0x41002000UL
+#define NOR_FLASH_BASE 0x40800000UL
+#define ADC_BASE 0x41006000UL
+#define EFUSE_BASE 0x41008000UL
+#define CAN0_BASE 0x41009000UL
+#define CAN1_BASE 0x4100D000UL
+#define DMA_BASE 0x41500000UL
+#define ETH_BASE 0x41200000UL
+#define USB_BASE 0x41300000UL
+#define GLOBAL_CTRL_BASE 0x41007010UL
+#define AES_BASE 0x41600000UL
+#define DDRC_BASE 0x41400000UL
+#define PDLOCK_BASE 0x41007000UL
+#define PDPROT_BASE 0x41007C00UL
+#define CFG_CTRL_BASE 0x41700000UL
+#define SOFT_RESET_BASE 0x41007400UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define UART0 ((UART0_Type *) UART0_BASE)
+#define UART1 ((UART0_Type *) UART1_BASE)
+#define UART2 ((UART0_Type *) UART2_BASE)
+#define WDG ((WDG_Type *) WDG_BASE)
+#define TIMER0 ((TIMER0_Type *) TIMER0_BASE)
+#define TIMER1 ((TIMER0_Type *) TIMER1_BASE)
+#define TIMER2 ((TIMER0_Type *) TIMER2_BASE)
+#define TIMER3 ((TIMER0_Type *) TIMER3_BASE)
+#define SPI0 ((SPI0_Type *) SPI0_BASE)
+#define SPI1 ((SPI0_Type *) SPI1_BASE)
+#define I2C0 ((I2C0_Type *) I2C0_BASE)
+#define I2C1 ((I2C0_Type *) I2C1_BASE)
+#define RTC ((RTC_Type *) RTC_BASE)
+#define GPIO ((GPIO_Type *) GPIO_BASE)
+#define NOR_FLASH ((NOR_FLASH_Type *) NOR_FLASH_BASE)
+#define ADC ((ADC_Type *) ADC_BASE)
+#define EFUSE ((EFUSE_Type *) EFUSE_BASE)
+#define CAN0 ((CAN0_Type *) CAN0_BASE)
+#define CAN1 ((CAN0_Type *) CAN1_BASE)
+#define DMA ((DMA_Type *) DMA_BASE)
+#define ETH ((ETH_Type *) ETH_BASE)
+#define USB ((USB_Type *) USB_BASE)
+#define GLOBAL_CTRL ((GLOBAL_CTRL_Type *) GLOBAL_CTRL_BASE)
+#define AES ((AES_Type *) AES_BASE)
+#define DDRC ((DDRC_Type *) DDRC_BASE)
+#define PDLOCK ((PDLOCK_Type *) PDLOCK_BASE)
+#define PDPROT ((PDPROT_Type *) PDPROT_BASE)
+#define CFG_CTRL ((CFG_CTRL_Type *) CFG_CTRL_BASE)
+#define SOFT_RESET ((SOFT_RESET_Type *) SOFT_RESET_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group CMEM7 */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* CMEM7_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_adc.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_adc.h
new file mode 100644
index 0000000000..7059c3c7ee
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_adc.h
@@ -0,0 +1,269 @@
+/**
+ *****************************************************************************
+ * @file cmem7_adc.h
+ *
+ * @brief CMEM7 ADC header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_ADC_H
+#define __CMEM7_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup ADC_PERIPH
+ * @{
+ */
+typedef enum {
+ ADC_PERIPH_1,
+ ADC_PERIPH_2,
+} ADC_PERIPH;
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC_PERIPH_1) || \
+ ((PERIPH) == ADC_PERIPH_2))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_VSEN
+ * @{
+ */
+#define ADC_VSEN_VDDCORE 1
+#define ADC_VSEN_VDDIO 2
+#define ADC_VSEN_VDDIO2 4
+
+#define IS_ADC_VSEN(VSEN) (((VSEN) == ADC_VSEN_VDDCORE) || \
+ ((VSEN) == ADC_VSEN_VDDIO) || \
+ ((VSEN) == ADC_VSEN_VDDIO2))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_PHASE_CTRL
+ * @{
+ */
+#define ADC_PHASE_CTRL_0DEG_RISE_EDGE 0 /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(Rising Edge) */
+#define ADC_PHASE_CTRL_90DEG_AHEAD 1 /* ADC-1 90DEG ahead of ADC-2 */
+#define ADC_PHASE_CTRL_90DEG_LAG 2 /* ADC-1 90DEG lag of ADC-2 */
+#define ADC_PHASE_CTRL_0DEG_FALL_EDGE 3 /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(falling Edge) */
+
+#define IS_ADC_PHASE_CTRL(CTRL) (((CTRL) == ADC_PHASE_CTRL_0DEG_RISE_EDGE) || \
+ ((CTRL) == ADC_PHASE_CTRL_90DEG_AHEAD) || \
+ ((CTRL) == ADC_PHASE_CTRL_90DEG_LAG) || \
+ ((CTRL) == ADC_PHASE_CTRL_0DEG_FALL_EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CONVERSION
+ * @{
+ */
+#define ADC_SYSTEM_MODE_SINGLE_CONV 1
+#define ADC_SYSTEM_MODE_CONTINUOUS_CONV 2
+
+#define IS_ADC_CONVERSION(CONV) (((CONV) == ADC_SYSTEM_MODE_SINGLE_CONV) || \
+ ((CONV) == ADC_SYSTEM_MODE_CONTINUOUS_CONV))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CALIBRATION
+ * @{
+ */
+#define ADC_CALIBRATION_OFFSET 3
+#define ADC_CALIBRATION_NEGTIVE_GAIN 4
+#define ADC_CALIBRATION_POSTIVE_GAIN 5
+
+#define IS_ADC_CALIBRATION(CALIB) (((CALIB) == ADC_CALIBRATION_OFFSET) || \
+ ((CALIB) == ADC_CALIBRATION_NEGTIVE_GAIN) || \
+ ((CALIB) == ADC_CALIBRATION_POSTIVE_GAIN))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CHANNEL
+ * @{
+ */
+#define ADC_CHANNEL_CALIBRATION 0x0
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC1_CHANNEL
+ * @{
+ */
+#define ADC1_CHANNEL_VIP 0x1
+#define ADC1_CHANNEL_VSEN 0x2
+#define ADC1_CHANNEL_VADIO_0 0x4
+#define ADC1_CHANNEL_VADIO_1 0x8
+#define ADC1_CHANNEL_VADIO_2 0x10
+#define ADC1_CHANNEL_VADIO_3 0x20
+#define ADC1_CHANNEL_VADIO_4 0x40
+#define ADC1_CHANNEL_VADIO_5 0x80
+#define ADC1_CHANNEL_ALL 0xFF
+
+#define IS_ADC1_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) & ~ADC1_CHANNEL_ALL) == 0)
+/**
+ * @}
+ */
+
+/** @defgroup ADC2_CHANNEL
+ * @{
+ */
+#define ADC2_CHANNEL_VIN 0x1
+#define ADC2_CHANNEL_VTMP 0x2
+#define ADC2_CHANNEL_VADIO_6 0x4
+#define ADC2_CHANNEL_VADIO_7 0x8
+#define ADC2_CHANNEL_VADIO_8 0x10
+#define ADC2_CHANNEL_VADIO_9 0x20
+#define ADC2_CHANNEL_VADIO_10 0x40
+#define ADC2_CHANNEL_VADIO_11 0x80
+#define ADC2_CHANNEL_ALL 0xFF
+
+#define IS_ADC2_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) & ~ADC2_CHANNEL_ALL) == 0)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_INT
+ * @{
+ */
+#define ADC1_INT_ALMOST_FULL 0x1
+#define ADC2_INT_ALMOST_FULL 0x8
+#define ADC_INT_ALL 0x9
+
+#define IS_ADC_INT(INT) (((INT) != 0) && (((INT) & ~ADC_INT_ALL) == 0))
+/**
+ * @}
+ */
+
+/**
+ * @brief ADC collection data structure
+ */
+typedef struct {
+ uint8_t channel; /*!< The channel of collected data, is a value of
+ @ref ADC_CHANNEL, @ref ADC1_CHANNEL or @ref ADC2_CHANNEL */
+ uint16_t data; /*!< collected data */
+} ADC_Data;
+
+/**
+ * @brief ADC initialization structure
+ */
+typedef struct
+{
+ uint8_t ADC_PhaseCtrl; /*!< Phase between ADC1 and ADC2, is a value of @ref ADC_PHASE_CTRL */
+ uint8_t ADC_VsenSelection; /*!< ADC1 VSEN selection, is a value of @ref ADC_VSEN */
+} ADC_InitTypeDef;
+
+/**
+ * @brief ADC initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] init A pointer to structure ADC_InitTypeDef
+ * @retval None
+ */
+void ADC_Init(ADC_InitTypeDef* init);
+
+/**
+ * @brief Enable or disable ADC.
+ * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+ * @param[in] Enable The bit indicates if the specific ADC is enable or not
+ * @retval None
+ */
+void ADC_Enable(uint8_t adc, BOOL enable);
+
+/**
+ * @brief Enable or disable ADC interrupt.
+ * @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
+ * @param[in] Enable The bit indicates if specific interrupts are enable or not
+ * @retval None
+ */
+void ADC_EnableInt(uint32_t Int, BOOL enable);
+
+/**
+ * @brief Check specific interrupts are set or not
+ * @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
+ * @retval BOOL The bit indicates if the specific interrupts are set or not
+ */
+BOOL ADC_GetIntStatus(uint32_t Int);
+
+/**
+ * @brief Clear specific interrupts
+ * @param[in] Int interrupt mask bits, which can be a value of @ref ADC_INT
+ * @retval None
+ */
+void ADC_ClearInt(uint32_t Int);
+
+/**
+ * @brief ADC starts to convert data
+ * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+ * @param[in] convMode It should be a value of @ref ADC_CONVERSION
+ * @param[in] channel It should be the value of @ref ADC1_CHANNEL
+ * or @ref ADC2_CHANNEL according to parameter 'adc'
+ * @retval BOOL The bit indicates if the specific ADC starts to convert data
+ */
+BOOL ADC_StartConversion(uint8_t adc, uint8_t convMode, uint32_t channel);
+
+/**
+ * @brief ADC starts to calibrate and produces one sample
+ * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+ * @param[in] convMode It should be a value of @ref ADC_CALIBRATION
+ * @retval BOOL The bit indicates if the specific ADC starts to convert data
+ */
+BOOL ADC_StartCalibration(uint8_t adc, uint8_t calibration);
+
+/**
+ * @brief ADC stops conversion or calibration
+ * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+ * @retval NULL
+ */
+void ADC_Stop(uint8_t adc);
+
+/**
+ * @brief Check if ADC is busy or not
+ * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+ * @retval BOOL The bit indicates if the specific ADC is busy or not
+ */
+BOOL ADC_IsBusy(uint8_t adc);
+
+/**
+ * @brief Read data from ADC
+ * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+ * @param[in] Size Expected data size to be read
+ * @param[out] data A user-allocated buffer to fetch data to be read
+ * @retval uint8_t Actual read data size
+ */
+uint8_t ADC_Read(uint8_t adc, uint8_t size, ADC_Data* data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CMEM7_ADC_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_aes.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_aes.h
new file mode 100644
index 0000000000..66a45de5fb
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_aes.h
@@ -0,0 +1,52 @@
+/**
+ *****************************************************************************
+ * @file cmem7_aes.h
+ *
+ * @brief CMEM7 AES header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_AES_H
+#define __CMEM7_AES_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/**
+ * @brief AES decryption
+ * @param[in] src A pointer to data to be decrypted
+ * @param[out] dst A user-allocated buffer to fetch decrypted data
+ * @param[in] len Expected data size to be decrypted, which should
+ * be multiply times of 16
+ * @retval BOOL True if succeed, or flase
+ */
+BOOL AES_Decrypt(const void *src, void *dst, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_AES_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_can.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_can.h
new file mode 100644
index 0000000000..d22a0f6518
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_can.h
@@ -0,0 +1,237 @@
+/**
+ *****************************************************************************
+ * @file cmem7_can.h
+ *
+ * @brief CMEM7 CAN header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_CAN_H
+#define __CMEM7_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN0) || \
+ ((PERIPH) == CAN1))
+
+/** @defgroup CAN_FLT
+ * @{
+ */
+#define CAN_FLT_STANDARD_SINGLE 0x00000000
+#define CAN_FLT_STANDARD_DUAL 0x00000001
+#define CAN_FLT_EXTENDED_SINGLE 0x00000002
+#define CAN_FLT_EXTENDED_DUAL 0x00000003
+
+#define IS_CAN_FLT_TYPE(FILTER) (((FILTER) == CAN_FLT_STANDARD_SINGLE) || \
+ ((FILTER) == CAN_FLT_STANDARD_DUAL) || \
+ ((FILTER) == CAN_FLT_EXTENDED_SINGLE) || \
+ ((FILTER) == CAN_FLT_EXTENDED_DUAL))
+
+#define IS_CAN_FLT_SINGLE(FILTER) (((FILTER) == CAN_FLT_STANDARD_SINGLE) || \
+ ((FILTER) == CAN_FLT_EXTENDED_SINGLE))
+
+#define IS_CAN_FLT_DUAL(FILTER) (IS_CAN_FLT_TYPE(FILTER) && \
+ !IS_CAN_FLT_SINGLE(FILTER))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_CDR_DIV
+ * @{
+ */
+#define CAN_CDR_DIV_1_2 0x0
+#define CAN_CDR_DIV_1_4 0x1
+#define CAN_CDR_DIV_1_6 0x2
+#define CAN_CDR_DIV_1_8 0x3
+#define CAN_CDR_DIV_1_10 0x4
+#define CAN_CDR_DIV_1_12 0x5
+#define CAN_CDR_DIV_1_14 0x6
+#define CAN_CDR_DIV_1_1 0x7
+
+#define IS_CAN_CDR_DIV(DIV) (((DIV) == CAN_CDR_DIV_1_2) || \
+ ((DIV) == CAN_CDR_DIV_1_4) || \
+ ((DIV) == CAN_CDR_DIV_1_6) || \
+ ((DIV) == CAN_CDR_DIV_1_8) || \
+ ((DIV) == CAN_CDR_DIV_1_10) || \
+ ((DIV) == CAN_CDR_DIV_1_12) || \
+ ((DIV) == CAN_CDR_DIV_1_14) || \
+ ((DIV) == CAN_CDR_DIV_1_1))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_INT
+ * @{
+ */
+#define CAN_INT_RBNF 0x01
+#define CAN_INT_TB_UNLOCK 0x02
+#define CAN_INT_ERR 0x04
+#define CAN_INT_DATA_OVERRUN 0x08
+#define CAN_INT_WAKEUP 0x10
+#define CAN_INT_ERR_PASSIVE 0x20
+#define CAN_INT_ARBITRATION_LOST 0x40
+#define CAN_INT_BUS_ERR 0x80
+#define CAN_INT_All 0xFF
+
+#define IS_CAN_INT(INT) (((INT) != 0) && (((INT) & ~CAN_INT_All) == 0))
+/**
+ * @}
+ */
+
+/**
+ * @brief CAN standard filter structure
+ */
+typedef struct {
+ uint16_t ID28_18; /*!< 11 bits */
+ BOOL RTR; /*!< if remote frame */
+ uint8_t data1; /*!< data byte 1, if not 2nd CAN_FLT_STANDARD_DUAL*/
+ uint8_t data2; /*!< data byte 2, if CAN_FLT_STANDARD_SINGLE */
+} CAN_STANDARD_FILTER;
+
+/**
+ * @brief CAN extended filter structure
+ */
+typedef struct {
+ uint16_t ID28_13; /*!< 16 bits */
+ uint16_t ID12_0; /*!< 13 bits, if CAN_FLT_EXTENDED_SINGLE */
+ BOOL RTR; /*!< if remote frame, if CAN_FLT_EXTENDED_SINGLE */
+} CAN_EXTENDED_FILTER;
+
+/**
+ * @brief CAN filter structure
+ */
+typedef struct {
+ uint8_t type; /*!< Filter type, which is a value of @ref CAN_FLT */
+
+ /**
+ * @brief accepted filter
+ */
+ union {
+ CAN_STANDARD_FILTER sf;
+ CAN_EXTENDED_FILTER ef;
+ } ACCEPT;
+
+ /**
+ * @brief filter mask
+ */
+ union {
+ CAN_STANDARD_FILTER sf;
+ CAN_EXTENDED_FILTER ef;
+ } MASK;
+} CAN_FILTER;
+
+/**
+ * @brief CAN initialization structure
+ */
+typedef struct {
+ BOOL CAN_TxEn; /*!< if transmission is enable */
+ BOOL CAN_Loopback; /*!< loop back mode without phy */
+ uint8_t CAN_ClockDiv; /*!< input clock divider, ref as @ref CAN_CDR_DIV */
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
+ Time quantum = (CAN_Prescaler + 1) * 2 * input clock */
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization. */
+ uint8_t CAN_TSEG1; /*!< the maximum number of time quanta of
+ propagation and 1st phase segment */
+ uint8_t CAN_TSEG2; /*!< the maximum number of time quanta of 2nd
+ phase segment */
+ BOOL CAN_HighSpeed; /*!< if CAN is running on high speed bus (class C) */
+} CAN_InitTypeDef;
+
+/**
+ * @brief CAN frame structure
+ */
+typedef struct
+{
+ BOOL SFF; /*!< If standard or extended frame format */
+ uint32_t Id; /*!< Specifies the identifier.This parameter can
+ be a value between 0 to 0x1FFFFFFF. */
+ BOOL RTR; /*!< Specifies if the frame is a remote frame */
+ uint8_t DLC; /*!< Specifies the length of the frame, which is
+ a value between 0 to 8 */
+ uint8_t Data[8]; /*!< Frame data */
+} CAN_Frame;
+
+/**
+ * @brief CAN initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+ * @param[in] Init A pointer to structure CAN_InitTypeDef
+ * @param[in] f1 A pointer to structure CAN_FILTER
+ * @param[in] f2 NULL if single filter, or a pointer to second filter while dual filters
+ * @retval BOOL The bit indicates if specific CAN is initialized or not
+ */
+BOOL CAN_Init(CAN0_Type* CANx, CAN_InitTypeDef* Init,
+ CAN_FILTER *f1, CAN_FILTER *f2);
+
+/**
+ * @brief CAN is set to sleep or wake up
+ * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+ * @param[in] Enable The bit indicates if sleep mode is enable or not
+ * @retval None
+ */
+void CAN_SetSleepMode(CAN0_Type* CANx, BOOL enable);
+
+/**
+ * @brief Enable or disable UART interrupt.
+ * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref CAN_INT
+ * @param[in] Enable The bit indicates if specific interrupts are enable or not
+ * @retval None
+ */
+void CAN_EnableInt(CAN0_Type* CANx, uint32_t Int, BOOL enable);
+
+/**
+ * @brief Check specific interrupts are set or not
+ * @note All interrupts except for receive int are cleared after call this func.
+ * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+ * @retval uint8_t CAN interrupt bits, which can be the combination of @ref CAN_INT
+ */
+uint8_t CAN_GetIntStatus(CAN0_Type* CANx);
+
+/**
+ * @brief CAN perform to transmit data
+ * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+ * @param[in] frame A pointer to the CAN_Frame to be transmitted
+ * @retval BOOL The bit indicates if data is transmitted or not
+ */
+BOOL CAN_Transmit(CAN0_Type* CANx, CAN_Frame* frame);
+
+/**
+ * @brief CAN perform to receive data
+ * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+ * @param[out] frame A user-allocated buffer to fetch received frame
+ * @retval BOOL The bit indicates if data is recieved or not
+ */
+BOOL CAN_Receive(CAN0_Type* CANx, CAN_Frame* frame);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_CAN_H */
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h
new file mode 100644
index 0000000000..db3b45c0a2
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h
@@ -0,0 +1,108 @@
+/**
+ *****************************************************************************
+ * @file cmem7_conf.h
+ *
+ * @brief CMEM7 config file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_CONF_H
+#define __CMEM7_CONF_H
+
+#define _ADC
+#define _AES
+#define _CAN
+#define _DDR
+#define _DMA
+#define _EFUSE
+#define _ETH
+#define _FLASH
+#define _GPIO
+#define _I2C
+#define _MISC
+#define _RTC
+#define _SPI
+#define _TIM
+#define _UART
+#define _USB
+#define _WDG
+
+#define USE_FULL_ASSERT 1
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function which reports
+ * the name of the source file and the source line number of the call
+ * that failed. If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((unsigned char *)__FILE__, __LINE__))
+
+ static void assert_failed(unsigned char* file, unsigned long line) {
+ while (1) {
+ ;
+ }
+ }
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL;
+
+/**
+ * System clock frequency, unit is Hz.
+ */
+#define SYSTEM_CLOCK_FREQ 200000000
+
+/**
+ * @brief usecond delay
+ * @note It can't delay in an accurate time
+ * @param[in] usec usecond to be delay
+ * @retval None
+ */
+static void udelay(unsigned long usec) {
+ unsigned long count = 0;
+ unsigned long utime = SYSTEM_CLOCK_FREQ / 1000000 * usec;
+
+ while(++count < utime) ;
+}
+
+/**
+ * UART definition for print
+ */
+#define PRINT_UART UART2
+
+/**
+ * DDR type definition
+ */
+#define DDR_TYPE 3 // 2 for DDR2, 3 for DDR3
+
+#if (DDR_TYPE == 3)
+# define DDR_SIZE (256 << 20)
+#elif (DDR_TYPE == 2)
+# define DDR_SIZE (128 << 20)
+#else
+# error
+#endif
+
+#endif /* __CMEM7_CONF_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_ddr.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_ddr.h
new file mode 100644
index 0000000000..98dfef13c2
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_ddr.h
@@ -0,0 +1,185 @@
+/**
+ *****************************************************************************
+ * @file cmem7_ddr.h
+ *
+ * @brief CMEM7 AES header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_DDR_H
+#define __CMEM7_DDR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+/** @defgroup _MEM_TYPE
+ * @{
+ */
+enum _MEM_TYPE
+{
+ MEM_DDR2=1,
+ MEM_DDR3
+} ;
+/**
+ * @}
+ */
+
+/** @defgroup _BUS_WIDTH
+ * @{
+ */
+enum _BUS_WIDTH
+{
+ BUS_WIDTH_8,
+ BUS_WIDTH_16,
+ BUS_WIDTH_MAX
+};
+/**
+ * @}
+ */
+/** @defgroup _CHIP_TYPE
+ * @{
+ */
+enum _CHIP_TYPE
+{
+ _32Mbx8,
+ _64Mbx8,
+ _128Mbx8,
+ _256Mbx8,
+ _512Mbx8,
+ _16Mbx16,
+ _32Mbx16,
+ _64Mbx16,
+ _128Mbx16,
+ _256Mbx16,
+ _512Mbx16,
+ CHIP_TYPE_MAX
+};
+/**
+ * @}
+ */
+
+/** @defgroup _CHIP_NUM
+ * @{
+ */
+enum _CHIP_NUM
+{
+ CHIP_NUM_x1,
+ CHIP_NUM_x2,
+ CHIP_NUM_MAX
+};
+/**
+ * @}
+ */
+
+/** @defgroup MEM_CHIP_INFO
+ * @{
+ */
+typedef struct {
+ uint8_t mem_type; /*!< ddr type @ref _MEM_TYPE*/
+ uint8_t Bus_width; /*!< ddr qs bus width @ref _BUS_WIDTH*/
+ uint8_t Chip_type; /*!< chip type @ref _CHIP_TYPE*/
+ uint8_t Chip_num; /*!< chip number @ref _CHIP_NUM*/
+ uint8_t Chip_bank; /*!< chip bank number*/
+} MEM_CHIP_INFO;
+/**
+ * @}
+ */
+
+
+/** @defgroup DDR2MEM
+ * @{
+ */
+typedef struct {
+ uint32_t tCK; /*!< Period of clock(ps), not data period */
+ uint32_t tCL; /*!< tCL */
+ uint32_t tRCD; /*!< tRCD */
+ uint32_t tRP; /*!< tRP */
+ uint32_t tRC; /*!< tRC */
+ uint32_t tRAS; /*!< tRAS */
+ uint32_t tWR; /*!< tWR */
+ uint32_t tRRD; /*!< tRRD */
+ uint32_t tWTR; /*!< tWTR */
+ uint32_t tRTP; /*!< tRTP */
+ uint32_t tFAW; /*!< tFAW */
+} DDR2MEM; /*!< DDR2ʱÐò¶¨Òå */
+/**
+ * @}
+ */
+
+/** @defgroup DDR3MEM
+ * @{
+ */
+typedef struct {
+ uint32_t tCK; /*!< Period of clock(ps), not data period */
+ uint32_t tCL; /*!< tCL */
+ uint32_t tWCL; /*!< tWCL */
+ uint32_t tRCD; /*!< tRCD */
+ uint32_t tRAS; /*!< tRAS */
+ uint32_t tRP; /*!< tRP */
+ uint32_t tRC; /*!< tRC */
+ uint32_t tRRD; /*!< tRRD */
+ uint32_t tFAW; /*!< tFAW */
+ uint32_t tWR; /*!< tWR */
+ uint32_t tRTP; /*!< tRTP */
+ uint32_t tZQoper; /*!< tZQCL */
+ uint32_t tZQCS; /*!< tZQCS */
+} DDR3MEM; /*!< DDR3ʱÐò¶¨Òå */
+/**
+ * @}
+ */
+
+/** @defgroup DDR2PREDEF
+ * @{
+ */
+extern const DDR2MEM DDR2PREDEF[]; /*!< Pre-defined DDR2 Timing in library */
+#define DDR2_400C 0 /*!< sg5E: DDR2-400C CL=4, tCK=5000ps */
+
+/**
+ * @}
+ */
+
+/** @defgroup DDR3PREDEF
+ * @{
+ */
+extern const DDR3MEM DDR3PREDEF[]; /*!< Pre-defined DDR3 Timing in library */
+#define DDR3_400 0
+#define DDR3_667 1
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DDR Timing Configuration
+ * @param[in] chip information ,A pointer to struct @ref MEM_CHIP_INFO
+ * @param[in] ddr A pointer to struct @ref DDR2MEM or @ref DDR3MEM that specified DDR Timing. Some typital DDR2/3 Timings are defined in arrays @ref DDR2PREDEF and @ref DDR3PREDEF.
+ * @retval void
+ */
+BOOL DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_DDR_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_dma.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_dma.h
new file mode 100644
index 0000000000..5e63902448
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_dma.h
@@ -0,0 +1,116 @@
+/**
+ *****************************************************************************
+ * @file cmem7_dma.h
+ *
+ * @brief CMEM7 DMA header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_DMA_H
+#define __CMEM7_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup DMA_Int
+ * @{
+ */
+#define DMA_Int_TfrComplete 0x00000001
+#define DMA_Int_Err 0x00000002
+#define DMA_Int_All 0x00000003
+
+#define IS_DMA_INT(INT) (((INT) != 0) && (((INT) & ~DMA_Int_All) == 0))
+/**
+ * @}
+ */
+
+/**
+ * @brief Descriptor structure
+ * @note DMA requires users provides a list of descriptors to operation.
+ * Meanwhile, memory occupied by descriptors should be in physical
+ * memory and keep valid during DMA transfer.
+ */
+typedef struct {
+ uint32_t srcAddr; /*!< source address */
+ uint32_t dstAddr; /*!< destination address */
+ uint32_t number; /*!< block byte number, no more than 2K Bytes */
+ uint32_t nextBlock; /*!< next block descriptor */
+ uint32_t padding; /*!< Nonsense, only used to fill */
+} BLOCK_DESC;
+
+/**
+ * @brief DMA initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param None
+ * @retval None
+ */
+void DMA_Init(void);
+
+/**
+ * @brief Enable or disable DMA interrupt.
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
+ * @param[in] Enable The bit indicates if specific interrupts are enable or not
+ * @retval None
+ */
+void DMA_EnableInt(uint32_t Int, BOOL enable);
+
+/**
+ * @brief Check specific interrupts are set or not
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
+ * @retval BOOL The bit indicates if specific interrupts are set or not
+ */
+BOOL DMA_GetIntStatus(uint32_t Int);
+
+/**
+ * @brief Clear specific interrupts
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
+ * @retval None
+ */
+void DMA_ClearInt(uint32_t Int);
+
+/**
+ * @brief DMA transfer
+ * @note Make sure that memory occupied by descriptors should be in physical
+ * memory and keep valid before DMA transfer is finished (Return false by
+ * calling DMA_IsBusy after DMA transfer started).
+ * @param[in] blockList A pointer to header of list of BLOCK_DESC
+ * @retval BOOL The bit indicates if DMA begins to transfer
+ * @see DMA_IsBusy
+ */
+BOOL DMA_Transfer(BLOCK_DESC *blockList);
+
+/**
+ * @brief DMA is busy or not
+ * @param None
+ * @retval BOOL The bit indicates if DMA is busy or not
+ */
+BOOL DMA_IsBusy(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_DMA_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_efuse.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_efuse.h
new file mode 100644
index 0000000000..e8c19b3196
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_efuse.h
@@ -0,0 +1,114 @@
+/**
+ *****************************************************************************
+ * @file cmem7_efuse.h
+ *
+ * @brief CMEM7 EFUSE header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_EFUSE_H
+#define __CMEM7_EFUSE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup EFUSE_TMRF_R
+ * @{
+ */
+#define EFUSE_TMRF_R_3000 0
+#define EFUSE_TMRF_R_1200 1
+#define EFUSE_TMRF_R_750 2
+
+#define IS_EFUSE_TMRF(R) (((R) == EFUSE_TMRF_R_3000) || \
+ ((R) == EFUSE_TMRF_R_1200) || \
+ ((R) == EFUSE_TMRF_R_750))
+/**
+ * @}
+ */
+
+/**
+ * @brief EFUSE timing structure
+ */
+typedef struct
+{
+ uint32_t EFUSE_Tpwph; /*!< Nano second */
+ uint32_t EFUSE_Trac; /*!< Nano second */
+ uint32_t EFUSE_Trah; /*!< Nano second */
+ uint32_t EFUSE_Trpw; /*!< Nano second */
+ uint32_t EFUSE_Trc; /*!< Nano second */
+ uint32_t EFUSE_Tesr; /*!< Nano second */
+ uint32_t EFUSE_Tprs; /*!< Nano second */
+ uint32_t EFUSE_Tpi; /*!< Nano second */
+ uint32_t EFUSE_Tpp; /*!< Nano second */
+ uint32_t EFUSE_Teps; /*!< Nano second */
+ uint32_t EFUSE_Tpwps; /*!< Nano second */
+} EFUSE_Timing;
+
+/**
+ * @brief EFUSE initialization structure
+ */
+typedef struct
+{
+ uint8_t EFUSE_ClockDividor; /*!< EFUSE clock dividor, 2 in n times */
+ uint8_t EFUSE_TMRF; /*!< EFUSE reference resistor select, @ref EFUSE_TMRF_R */
+ EFUSE_Timing* timing; /*!< Timing configuration, null if default */
+} EFUSE_InitTypeDef;
+
+/**
+ * @brief EFUSE key structure
+ */
+typedef struct
+{
+ uint32_t key0; /*!< EFUSE AES key [31:0] */
+ uint32_t key1; /*!< EFUSE AES key [63:32] */
+ uint32_t key2; /*!< EFUSE AES key [95:64] */
+ uint32_t key3; /*!< EFUSE AES key [127:96] */
+ uint32_t key4; /*!< EFUSE AES key [159:128] */
+ uint32_t key5; /*!< EFUSE AES key [191:160] */
+ uint32_t key6; /*!< EFUSE AES key [223:192] */
+ uint32_t key7; /*!< EFUSE AES key [255:224] */
+} EFUSE_AesKey;
+
+/**
+ * @brief EFUSE initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] init A pointer to structure EFUSE_InitTypeDef
+ * @retval None
+ */
+void EFUSE_Init(EFUSE_InitTypeDef* init);
+
+/**
+ * @brief EFUSE initialization
+ * @param[in] key A pointer to EFUSE_AesKey to be compared
+ * @retval BOOL True if equal, or false if different
+ */
+BOOL EFUSE_Compare(EFUSE_AesKey* key);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_EFUSE_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h
new file mode 100644
index 0000000000..4d8a46527a
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h
@@ -0,0 +1,382 @@
+/**
+ *****************************************************************************
+ * @file cmem7_eth.h
+ *
+ * @brief CMEM7 ethernet header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_ETH_H
+#define __CMEM7_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup ETH_SPEED
+ * @{
+ */
+#define ETH_SPEED_10M 0x0
+#define ETH_SPEED_100M 0x1
+#define ETH_SPEED_1000M 0x2
+
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
+ ((SPEED) == ETH_SPEED_100M) || \
+ ((SPEED) == ETH_SPEED_1000M))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DUPLEX
+ * @{
+ */
+#define ETH_DUPLEX_HALF 0x0
+#define ETH_DUPLEX_FULL 0x1
+
+#define IS_ETH_DUPLEX(DUPLEX) (((DUPLEX) == ETH_DUPLEX_HALF) || \
+ ((DUPLEX) == ETH_DUPLEX_FULL))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_INT
+ * @{
+ */
+#define ETH_INT_TX_COMPLETE_FRAME 0x0001
+#define ETH_INT_TX_STOP 0x0002
+#define ETH_INT_TX_BUF_UNAVAI 0x0004
+#define ETH_INT_RX_OVERFLOW 0x0010
+#define ETH_INT_TX_UNDERFLOW 0x0020
+#define ETH_INT_RX_COMPLETE_FRAME 0x0040
+#define ETH_INT_RX_BUF_UNAVAI 0x0080
+#define ETH_INT_RX_STOP 0x0100
+#define ETH_INT_BUS_FATAL_ERROR 0x2000
+#define ETH_INT_ALL (ETH_INT_TX_COMPLETE_FRAME | \
+ ETH_INT_TX_STOP | \
+ ETH_INT_TX_BUF_UNAVAI | \
+ ETH_INT_RX_OVERFLOW | \
+ ETH_INT_TX_UNDERFLOW | \
+ ETH_INT_RX_COMPLETE_FRAME | \
+ ETH_INT_RX_BUF_UNAVAI | \
+ ETH_INT_RX_STOP | \
+ ETH_INT_BUS_FATAL_ERROR)
+
+#define IS_ETH_INT(INT) (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0))
+/**
+ * @}
+ */
+
+/**
+ * @brief EFUSE receive filter structure
+ */
+typedef struct
+{
+ BOOL ETH_BroadcastFilterEnable; /*!< Broadcast is dropped or passed */
+ BOOL ETH_OwnFilterEnable; /*!< source address filter is on or off */
+ BOOL ETH_SelfDrop; /*!< Only own address is dropped or passed */
+ BOOL ETH_SourceFilterEnable; /*!< source address filter is on or off */
+ BOOL ETH_SourceDrop; /*!< Only specific source address is dropped or passed */
+ uint8_t ETH_SourceMacAddr[6]; /*!< Source MAC address */
+} ETH_FrameFilter;
+
+/**
+ * @brief Ethernet initialization structure
+ */
+typedef struct
+{
+ BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */
+ uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */
+ uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */
+ BOOL ETH_RxEn; /*!< Rx enable */
+ BOOL ETH_TxEn; /*!< Tx enable */
+ BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */
+ BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */
+ uint8_t ETH_MacAddr[6]; /*!< MAC address */
+ ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */
+} ETH_InitTypeDef;
+
+/**
+ * @brief Ethernet Tx descriptor structure
+ */
+typedef struct {
+ union {
+ uint32_t TX0;
+
+ struct {
+ uint32_t : 1;
+ uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */
+ uint32_t : 1;
+ uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */
+ uint32_t : 1;
+ uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */
+ uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */
+ uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */
+ uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */
+ uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */
+ uint32_t : 2;
+ uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */
+ uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */
+ uint32_t : 8;
+ uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */
+ uint32_t : 2;
+ uint32_t FS : 1; /*!< first segment flag */
+ uint32_t LS : 1; /*!< last segment flag */
+ uint32_t : 2;
+ } TX0_b;
+ } TX_0;
+
+ union {
+ uint32_t TX1;
+
+ struct {
+ uint32_t SIZE : 13; /*!< buffer size */
+ uint32_t : 19;
+ } TX1_b;
+ } TX_1;
+
+ uint32_t bufAddr; /*!< address of buffer */
+ uint32_t nextDescAddr; /*!< address of next descriptor */
+ uint64_t reserved;
+ uint64_t timeStamp; /*!< time stamp while last segment */
+} ETH_TX_DESC;
+
+/**
+ * @brief Ethernet Rx descriptor structure
+ */
+typedef struct {
+ union {
+ uint32_t RX0;
+
+ struct {
+ uint32_t : 1;
+ uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */
+ uint32_t : 5;
+ uint32_t TTSE : 1; /*!< timestamp available while last segment */
+ uint32_t LS : 1; /*!< last segment flag */
+ uint32_t FS : 1; /*!< first segment flag */
+ uint32_t : 1;
+ uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */
+ uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */
+ uint32_t : 2;
+ uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */
+ uint32_t FL : 14; /*!< frame length while last segment */
+ uint32_t : 2;
+ } RX0_b;
+ } RX_0;
+
+ union {
+ uint32_t RX1;
+
+ struct {
+ uint32_t SIZE : 13; /*!< buffer size */
+ uint32_t : 19;
+ } RX1_b;
+ } RX_1;
+
+ uint32_t bufAddr; /*!< buffer address */
+ uint32_t nextDescAddr; /*!< address of next descriptor */
+ uint64_t reserved;
+ uint64_t timeStamp; /*!< time stamp while the last segment */
+} ETH_RX_DESC;
+
+/**
+ * @brief Read data from phy chip
+ * @param[in] phyAddr Address of phy chip
+ * @param[in] phyReg Address of phy's register to be read
+ * @retval uint32_t value of phy's register
+ */
+uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
+
+/**
+ * @brief Write data to phy chip
+ * @param[in] phyAddr Address of phy chip
+ * @param[in] phyReg Address of phy's register to be written
+ * @param[in] data Data to be written
+ * @retval None
+ */
+void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+
+/**
+ * @brief Ethernet initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] init A pointer to structure ETH_InitTypeDef
+ * @retval BOOL The bit indicates if ethernet is initialized successfully
+ */
+BOOL ETH_Init(ETH_InitTypeDef *init);
+
+/**
+ * @brief Enable or disable ethernet interrupt.
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
+ * @param[in] Enable The bit indicates if specific interrupts are enable or not
+ * @retval None
+ */
+void ETH_EnableInt(uint32_t Int, BOOL enable);
+
+/**
+ * @brief Check specific interrupts are set or not
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
+ * @retval BOOL The bit indicates if specific interrupts are set or not
+ */
+BOOL ETH_GetIntStatus(uint32_t Int);
+
+/**
+ * @brief Clear specific interrupts
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
+ * @retval None
+ */
+void ETH_ClearInt(uint32_t Int);
+
+/**
+ * @brief Get ethernte MAC address
+ * @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes.
+ * @retval None
+ */
+void ETH_GetMacAddr(uint8_t *mac);
+
+/**
+ * @brief Set ethernet transmission descriptor ring
+ * @note Make sure that memory occupied by descriptors should be in physical
+ * memory and keep valid before ethernet transmission is finished.
+ * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
+ * has a 'nextDescAddr' pointed to first node.
+ * @retval BOOL The bit indicates if valid ring is set
+ */
+BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring);
+
+/**
+ * @brief Start ethernet transmission
+ * @param None
+ * @retval None
+ */
+void ETH_StartTx(void);
+
+/**
+ * @brief Stop ethernet transmission
+ * @param None
+ * @retval None
+ */
+void ETH_StopTx(void);
+
+/**
+ * @brief Resume ethernet transmission\n
+ * While ethernet doesn't have enough buffer to transmit data, it will
+ * pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users
+ * must call this function to start ethernet again after new buffer
+ * prepared.
+ * @param None
+ * @retval None
+ */
+void ETH_ResumeTx(void);
+
+/**
+ * @brief Get free transmission descriptor\n
+ * @param None
+ * @retval ETH_TX_DESC* A pointer of free transmission descriptor,
+ * NULL if no free descriptor
+ */
+ETH_TX_DESC *ETH_AcquireFreeTxDesc(void);
+
+/**
+ * @brief Check if a transmission descriptor is free or not
+ * @param desc A pointer of a transmission descriptor
+ * @retval BOOL True if the transmission descriptor is free, or flase.
+ */
+BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
+
+/**
+ * @brief Release a transmission descriptor to ethernet\n
+ * After users prepared data in the buffer of a free descriptor,
+ * They must call this function to change ownership of the
+ * descriptor to hardware.
+ * @param desc A pointer of a transmission descriptor
+ * @retval None
+ */
+void ETH_ReleaseTxDesc(ETH_TX_DESC *desc);
+
+/**
+ * @brief Set ethernet receive descriptor ring
+ * @note Make sure that memory occupied by descriptors should be in physical
+ * memory and keep valid before ethernet receive is finished.
+ * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
+ * has a 'nextDescAddr' pointed to first node.
+ * @retval BOOL The bit indicates if valid ring is set
+ */
+BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring);
+
+/**
+ * @brief Start ethernet receive
+ * @param None
+ * @retval None
+ */
+void ETH_StartRx(void);
+
+/**
+ * @brief Stop ethernet receive
+ * @param None
+ * @retval None
+ */
+void ETH_StopRx(void);
+
+/**
+ * @brief Resume ethernet receive\n
+ * While ethernet doesn't have enough buffer to receive data, it will
+ * pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users
+ * must call this function to start ethernet again after new buffer
+ * prepared.
+ * @param None
+ * @retval None
+ */
+void ETH_ResumeRx(void);
+
+/**
+ * @brief Get the free descriptor which contains received data\n
+ * @param None
+ * @retval ETH_RX_DESC* A pointer of free receive descriptor,
+ * NULL if no free descriptor
+ */
+ETH_RX_DESC *ETH_AcquireFreeRxDesc(void);
+
+/**
+ * @brief Check if a receive descriptor is free or not
+ * @param desc A pointer of a receive descriptor
+ * @retval BOOL True if the receive descriptor is free, or flase.
+ */
+BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
+
+/**
+ * @brief Release a receive descriptor to ethernet\n
+ * After users handled data in the buffer of a free descriptor,
+ * They must call this function to change ownership of the
+ * descriptor to hardware.
+ * @param desc A pointer of a transmission descriptor
+ * @retval None
+ */
+void ETH_ReleaseRxDesc(ETH_RX_DESC *desc);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_ETH_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h
new file mode 100644
index 0000000000..477cc59212
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h
@@ -0,0 +1,210 @@
+/**
+ *****************************************************************************
+ * @file cmem7_flash.h
+ *
+ * @brief CMEM7 flash controller source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_FLASH_H
+#define __CMEM7_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup FLASH_PROTECT_MODE
+ * @{
+ */
+#define FLASH_PROTECT_MODE_SW 0 /*!< The Status Register can be written to after a Write
+ Enable command.(Default) */
+#define FLASH_PROTECT_MODE_HW 1 /*!< WP pin decides if the Status Register can be written
+ WP#=0, the Status Register locked
+ WP#=1, the Status Register is unlocked and can be written to
+ after a Write Enable command */
+#define FLASH_PROTECT_MODE_POWERDOWN 2 /*!< Status Register is protected and can not be written to again
+ until the next Power-Down, Power-Up cycle */
+#define FLASH_PROTECT_MODE_OTP 3 /*!< Status Register is permanently protected */
+
+#define IS_FLASH_PROTECT_MODE(MODE) (((MODE) == FLASH_PROTECT_MODE_SW) || \
+ ((MODE) == FLASH_PROTECT_MODE_HW) || \
+ ((MODE) == FLASH_PROTECT_MODE_POWERDOWN) || \
+ ((MODE) == FLASH_PROTECT_MODE_OTP))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_PROTECT_REGION
+ * @{
+ */
+#define FLASH_PROTECT_REGION_NONE 0x00 /*!< no region is protected */
+#define FLASH_PROTECT_REGION_UP_64K 0x01 /*!< region(0F0000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_128K 0x02 /*!< region(0E0000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_256K 0x03 /*!< region(0C0000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_512K 0x04 /*!< region(080000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_64K 0x09 /*!< region(000000H-00FFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_128K 0x0A /*!< region(000000H-01FFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_256K 0x0B /*!< region(000000H-03FFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_512K 0x0C /*!< region(000000H-07FFFFH) is protected */
+#define FLASH_PROTECT_REGION_ALL 0x0D /*!< region(000000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_4K 0x11 /*!< region(0FF000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_8K 0x12 /*!< region(0FE000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_16K 0x13 /*!< region(0FC000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_UP_32K 0x14 /*!< region(0F8000H-0FFFFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_4K 0x19 /*!< region(000000H-000FFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_8K 0x1A /*!< region(000000H-001FFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_16K 0x1B /*!< region(000000H-003FFFH) is protected */
+#define FLASH_PROTECT_REGION_LOW_32K 0x1C /*!< region(000000H-007FFFH) is protected */
+
+#define IS_FLASH_PROTECT_REGION(REGION) (((REGION) == FLASH_PROTECT_REGION_NONE) || \
+ ((REGION) == FLASH_PROTECT_REGION_UP_64K) || \
+ ((REGION) == FLASH_PROTECT_REGION_UP_128K) || \
+ ((REGION) == FLASH_PROTECT_REGION_UP_256K) || \
+ ((REGION) == FLASH_PROTECT_REGION_UP_512K) || \
+ ((REGION) == FLASH_PROTECT_REGION_LOW_64K) || \
+ ((REGION) == FLASH_PROTECT_REGION_LOW_128K) || \
+ ((REGION) == FLASH_PROTECT_REGION_LOW_256K) || \
+ ((REGION) == FLASH_PROTECT_REGION_LOW_512K) || \
+ ((REGION) == FLASH_PROTECT_REGION_ALL) || \
+ ((REGION) == FLASH_PROTECT_REGION_UP_4K) || \
+ ((REGION) == FLASH_PROTECT_REGION_UP_8K) || \
+ ((REGION) == FLASH_PROTECT_REGION_UP_16K) || \
+ ((REGION) == FLASH_PROTECT_REGION_UP_32K) || \
+ ((REGION) == FLASH_PROTECT_REGION_LOW_4K) || \
+ ((REGION) == FLASH_PROTECT_REGION_LOW_8K) || \
+ ((REGION) == FLASH_PROTECT_REGION_LOW_16K) || \
+ ((REGION) == FLASH_PROTECT_REGION_LOW_32K))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_READ_MODE
+ * @{
+ */
+#define FLASH_READ_MODE_NORMAL 0 /*!< normal read, 1 bitwidth, highest freqency is 90MHz */
+#define FLASH_READ_MODE_FAST 1 /*!< fast read, 1 bitwidth, highest freqency is 120MHz */
+#define FLASH_READ_MODE_FAST_DUAL 2 /*!< fast read, 2 bitwidth, highest freqency is 120MHz */
+#define FLASH_READ_MODE_FAST_QUAD 3 /*!< fast read, 4 bitwidth, highest freqency is 90MHz */
+
+#define IS_FLASH_READ_MODE(MODE) (((MODE) == FLASH_READ_MODE_NORMAL) || \
+ ((MODE) == FLASH_READ_MODE_FAST) || \
+ ((MODE) == FLASH_READ_MODE_FAST_DUAL) || \
+ ((MODE) == FLASH_READ_MODE_FAST_QUAD))
+/**
+ * @}
+ */
+
+/**
+ * @brief UART initialization structure
+ */
+typedef struct
+{
+ uint8_t FLASH_ClockDividor; /*!< flash clock dividor, 2 in n times */
+ uint8_t FLASH_ProtectMode; /*!< Status Register protection mode */
+ uint8_t FLASH_ProtectRegion; /*!< flash protection region */
+ BOOL FLASH_QuadEnable; /*!< if allows Quad operation */
+ void (*FLASH_Wait)(void); /*!< When the former read or write operation is excuting,
+ Flash has to call a callback to wait it finish.
+ If null, Flash will wait forever until finish */
+} FLASH_InitTypeDef;
+
+/**
+ * @brief flash initialization
+ * @note This function should be called at first before any other interfaces.
+ * Users should make sure that doesn't erase or write data in a
+ * write-protected region.
+ * @param[in] init A pointer to structure FLASH_InitTypeDef
+ * @retval None
+ */
+void FLASH_Init(FLASH_InitTypeDef* init);
+
+/**
+ * @brief Get flash status
+ * @param[out] ProtectMode flash protect mode, ref as @ref FLASH_PROTECT_MODE
+ * @param[out] ProtectRegion flash protect region, ref as @ref FLASH_PROTECT_REGION
+ * @param[out] QuadEnable quad speed mode enable bit
+ * @retval None
+ */
+void FLASH_GetStatus(uint8_t* ProtectMode, uint8_t* ProtectRegion, BOOL* QuadEnable);
+
+/**
+ * @brief Erase a sector, which is 4K bytes large.
+ * @param[in] addr Start address of a sector
+ * @retval None
+ */
+void FLASH_EraseSector(uint32_t addr);
+
+/**
+ * @brief Erase a block, which is 32K bytes large.
+ * @param[in] addr Start address of a block
+ * @retval None
+ */
+void FLASH_Erase32kBlock(uint32_t addr);
+
+/**
+ * @brief Erase a block, which is 64K bytes large.
+ * @param[in] addr Start address of a block
+ * @retval None
+ */
+void FLASH_Erase64kBlock(uint32_t addr);
+
+/**
+ * @brief Erase all chip
+ * @param None
+ * @retval None
+ */
+void FLASH_EraseChip(void);
+
+/**
+ * @brief Enable flash power down mode or not
+ * @param[in] enable The bit indicates if flash power down mode is enable or not
+ * @retval None
+ */
+void FLASH_EnableDeepPowerDown(BOOL enable);
+
+/**
+ * @brief Read data from flash
+ * @param[in] ReadMode Normal or fast read, ref as @ref FLASH_READ_MODE
+ * @param[in] addr Start address to be read
+ * @param[in] size Expected data size to be read
+ * @param[out] data A user-allocated buffer to fetch data to be read
+ * @retval None
+ */
+void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data);
+
+/**
+ * @brief Write data to flash
+ * @param[in] addr Start address to be read
+ * @param[in] size Expected data size to be read
+ * @param[out] data A pointer to the data to be written
+ * @retval None
+ */
+void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_FLASH_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h
new file mode 100644
index 0000000000..836bc2f7b6
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h
@@ -0,0 +1,148 @@
+/**
+ *****************************************************************************
+ * @file cmem7_gpio.h
+ *
+ * @brief CMEM7 GPIO header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_GPIO_H
+#define __CMEM7_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup GPIO_GROUP
+ * @{
+ */
+typedef enum {
+ GPIO_GROUP_GPIO,
+} GPIO_GROUP;
+
+#define IS_GPIO_GROUP(GROUP) (((GROUP) == GPIO_GROUP_GPIO))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_PWM_CHANNEL
+ * @{
+ */
+typedef enum {
+ GPIO_PWM_CHANNEL_GPIO_31,
+} GPIO_PWM_CHANNEL;
+
+#define IS_GPIO_PWM_CHANNEL(CHANNEL) (((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_31))
+/**
+ * @}
+ */
+
+/**
+ * @brief GPIO initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+ * @param[in] PositiveTrigger Positive edge interrupt trigger if true, or negative edge
+ * @retval None
+ */
+void GPIO_Init(uint8_t Group, uint32_t PositiveTrigger);
+
+/**
+ * @brief Enable or disable GPIO output in the specific group.
+ * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+ * @param[in] Enable each bit indicates if the corresponding GPIO pin
+ * in the specific GPIO group is enable or not
+ * @retval None
+ */
+void GPIO_EnableOutput(uint8_t Group, uint32_t Enable);
+
+/**
+ * @brief Enable or disable GPIO interrupt in the specific group.
+ * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+ * @param[in] Enable each bit indicates if the corresponding GPIO pin interrupt
+ * in the specific GPIO group is enable or not
+ * @retval None
+ */
+void GPIO_EnableInt(uint8_t Group, uint32_t Enable);
+
+/**
+ * @brief Check specific interrupts are set or not
+ * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+ * @retval uint32_t each bit indicates if the corresponding GPIO pin interrupt
+ * in the specific GPIO group is set or not
+ */
+uint32_t GPIO_GetIntStatus(uint8_t Group);
+
+/**
+ * @brief Clear GPIO interrupt in the specific group.
+ * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+ * @param[in] Clear each bit indicates if the corresponding GPIO pin interrupt
+ * in the specific GPIO group is clear or not
+ * @retval None
+ */
+void GPIO_ClearInt(uint8_t Group, uint32_t Clear);
+
+/**
+ * @brief Get value of each GPIO pin in the specific group
+ * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+ * @retval uint32_t each bit indicates value of the corresponding GPIO pin
+ * in the specific GPIO group
+ */
+uint32_t GPIO_Read(uint8_t Group);
+
+/**
+ * @brief Set value of each GPIO pin in the specific group
+ * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+ * @param[in] Unmask each bit indicates value of the corresponding GPIO pin
+ * in the specific GPIO group is set or not
+ * @param[in] data each bit indicates value of the corresponding GPIO pin
+ * in the specific GPIO group to be set
+ * @retval None
+ */
+void GPIO_Write(uint8_t Group, uint32_t Unmask, uint32_t data);
+
+/**
+ * @brief Initialize PWM for the specific GPIO pin
+ * @note It can work before call GPIO_EnableOutput for the specific GPIO pin
+ * @param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
+ * @param[in] HighLevelNanoSecond Nanosecond which high level lasts
+ * @param[in] LowLevelNanoSecond Nanosecond which low level lasts
+ * @retval None
+ * @see GPIO_EnableOutput
+ */
+void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLevelNanoSecond);
+
+/**
+ * @brief Enable or disable GPIO PWM in the specific channel.
+ * @param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
+ * @param[in] Enable The bit indicates if the specific channel is enable or not
+ * @retval None
+ */
+void GPIO_EnablePwm(uint8_t Channel, BOOL Enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_GPIO_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_i2c.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_i2c.h
new file mode 100644
index 0000000000..388983838b
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_i2c.h
@@ -0,0 +1,247 @@
+/**
+ *****************************************************************************
+ * @file cmem7_i2c.h
+ *
+ * @brief CMEM7 I2C header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_I2C_H
+#define __CMEM7_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C0) || \
+ ((PERIPH) == I2C1))
+
+/** @defgroup I2C_Mode
+ * @{
+ */
+#define I2C_Mode_Slave 0
+#define I2C_Mode_Master 1
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_Slave) || \
+ ((MODE) == I2C_Mode_Master))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_ADDR_WIDTH
+ * @{
+ */
+#define I2C_ADDR_WIDTH_7BIT 0
+#define I2C_ADDR_WIDTH_10BIT 1
+#define IS_I2C_ADDR_WIDTH(WIDTH) (((WIDTH) == I2C_ADDR_WIDTH_7BIT) || \
+ ((WIDTH) == I2C_ADDR_WIDTH_10BIT))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_INT
+ * @{
+ */
+#define I2C_INT_RX_FIFO_NOT_EMPTY 0x00000004 /*!< Can't be clear but read FIFO */
+#define I2C_INT_RD_REQUEST 0x00000020 /*!< Slave was requested to send data */
+#define I2C_INT_TX_ABORT 0x00000040 /*!< Error while sending data */
+#define I2C_INT_RX_DONE 0x00000080 /*!< Slave sent all requested data */
+#define I2C_INT_TX_DONE 0x00000100 /*!< Master accomplish to send all data */
+
+#define I2C_INT_ALL (I2C_INT_RX_FIFO_NOT_EMPTY | \
+ I2C_INT_RD_REQUEST | \
+ I2C_INT_TX_ABORT | \
+ I2C_INT_RX_DONE | \
+ I2C_INT_TX_DONE)
+
+#define IS_I2C_INT(INT) (((INT) != 0) && (((INT) & ~I2C_INT_ALL) == 0))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_STATUS
+ * @{
+ */
+#define I2C_STATUS_RX_FIFO_NOT_EMPTY 0x00200000 /*!< Can't be clear but read FIFO */
+#define I2C_STATUS_RD_REQUEST 0x01000000 /*!< Slave was requested to send data */
+#define I2C_STATUS_TX_ABORT 0x02000000 /*!< Error while sending data */
+#define I2C_STATUS_RX_DONE 0x04000000 /*!< Slave sent all requested data */
+#define I2C_STATUS_TX_DONE 0x08000000 /*!< Master accomplish to send all data */
+
+#define I2C_STATUS_ALL (I2C_STATUS_RX_FIFO_NOT_EMPTY | \
+ I2C_STATUS_RD_REQUEST | \
+ I2C_STATUS_TX_ABORT | \
+ I2C_STATUS_RX_DONE | \
+ I2C_STATUS_TX_DONE)
+
+#define IS_I2C_STATUS(STATUS) (((STATUS) != 0) && (((STATUS) & ~I2C_STATUS_ALL) == 0))
+/**
+ * @}
+ */
+
+/**
+ * @brief I2C timing structure
+ */
+typedef struct
+{
+ uint32_t I2C_Freq; /*!< I2C frquency */
+
+ uint16_t I2C_TsuDat; /*!< nano second of TSU:DAT */
+ uint16_t I2C_Tsetup; /*!< nano second of THD:STA and TSU:STO */
+ uint16_t I2C_Tbuf; /*!< nano second of TBUF */
+ uint16_t I2C_TsuSta; /*!< nano second of TSU:STA */
+
+ BOOL I2C_SdaFilterEn; /*!< enabled flag of SDA filter */
+ uint8_t I2C_SdaFilterSpike; /*!< spikes of SDA filter */
+ BOOL I2C_SclFilterEn; /*!< enabled flag of SCL filter */
+ uint8_t I2C_SclFilterSpike; /*!< spikes of SCL filter */
+
+} I2C_InitTimingDef;
+
+/**
+ * @brief I2C initialization structure
+ */
+typedef struct
+{
+ uint8_t I2C_Mode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_mode */
+ uint8_t I2C_AddressWidth; /*!< 7- or 10-bits width address, ref as @ref I2C_ADDR_WIDTH */
+ uint8_t I2C_Address; /*!< 7- or 10-bits address */
+ I2C_InitTimingDef* timing; /*!< timing structure, null if don't set */
+} I2C_InitTypeDef;
+
+/**
+ * @brief I2C initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] init A pointer to structure I2C_InitTypeDef
+ * @retval None
+ */
+void I2C_Init(I2C0_Type* I2Cx, I2C_InitTypeDef* I2C_Init);
+
+/**
+ * @brief Enable or disable I2C.
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] Enable The bit indicates if the specific I2C is enable or not
+ * @retval None
+ */
+void I2C_Enable(I2C0_Type* I2Cx, BOOL enable);
+
+/**
+ * @brief Enable or disable I2C interrupt.
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
+ * @param[in] Enable The bit indicates if specific interrupts are enable or not
+ * @retval None
+ */
+void I2C_EnableInt(I2C0_Type* I2Cx, uint32_t Int, BOOL enable);
+
+/**
+ * @brief Check specific interrupts are set or not
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
+ * @retval BOOL The bit indicates if specific interrupts are enable or not
+ */
+BOOL I2C_GetIntStatus(I2C0_Type* I2Cx, uint32_t Int);
+
+/**
+ * @brief Clear specific interrupts
+ * @note Specific interrupt clear will clear correspective status as well
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
+ * @retval None
+ */
+void I2C_ClearInt(I2C0_Type* I2Cx, uint32_t Int);
+
+/**
+ * @brief Check specific status are set or not
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
+ * @retval BOOL The bit indicates if specific status are set or not
+ */
+BOOL I2C_GetStatus(I2C0_Type* I2Cx, uint32_t Status);
+
+/**
+ * @brief Clear specific status
+ * @note Specific status clear will clear correspective interrupt as well
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
+ * @retval None
+ */
+void I2C_ClearStatus(I2C0_Type* I2Cx, uint32_t Status);
+
+/**
+ * @brief I2C send read request in master mode
+ * @note Users must call I2C_StopReq between 2 requests
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] size Expected data size to be read
+ * @retval BOOL The bit indicates if read request to be sent is valid
+ * @see I2C_StopReq
+ */
+BOOL I2C_MasterReadReq(I2C0_Type* I2Cx, uint8_t size);
+
+/**
+ * @brief Read data from I2C
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] size Expected data size to be read
+ * @param[out] Data A user-allocated buffer to fetch data to be read
+ * @retval uint8_t Actual read data size
+ */
+uint8_t I2C_ReadFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
+
+/**
+ * @brief I2C send write request in master or slave mode
+ * @note Users must call I2C_StopReq between 2 requests
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] size Expected data size to be written, includes the first data
+ * @param[in] firstData The first data to be written
+ * @retval BOOL The bit indicates if write request to be sent is valid
+ * @see I2C_StopReq
+ */
+BOOL I2C_WriteReq(I2C0_Type* I2Cx, uint8_t size, uint8_t firstData);
+
+/**
+ * @brief Write data to I2C
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @param[in] size Expected data size to be written
+ * @param[in] Data A pointer to the data to be written
+ * @retval uint8_t Actual written data size
+ */
+uint8_t I2C_WriteFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
+
+/**
+ * @brief I2C stop request
+ * @note Users must call I2C_StopReq between 2 requests
+ * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+ * @retval BOOL The bit indicates if request is stopped.
+ * @see I2C_MasterReadReq I2C_WriteReq
+ */
+BOOL I2C_StopReq(I2C0_Type* I2Cx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CMEM7_I2C_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h
new file mode 100644
index 0000000000..a7e6cc2cc4
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h
@@ -0,0 +1,110 @@
+/**
+ *****************************************************************************
+ * @file cmem7_includes.h
+ *
+ * @brief CMEM7 includes file, easy to use CMEM7 library
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_INCLUDES_H
+#define __CMEM7_INCLUDES_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7_conf.h"
+#include "cmem7_it.h"
+
+#ifdef _ADC
+ #include "cmem7_adc.h"
+#endif
+
+#ifdef _AES
+ #include "cmem7_aes.h"
+#endif
+
+#ifdef _CAN
+ #include "cmem7_can.h"
+#endif
+
+#ifdef _DDR
+ #include "cmem7_ddr.h"
+#endif
+
+#ifdef _DMA
+ #include "cmem7_dma.h"
+#endif
+
+#ifdef _EFUSE
+ #include "cmem7_efuse.h"
+#endif
+
+#ifdef _ETH
+ #include "cmem7_eth.h"
+#endif
+
+#ifdef _FLASH
+ #include "cmem7_flash.h"
+#endif
+
+#ifdef _GPIO
+ #include "cmem7_gpio.h"
+#endif
+
+#ifdef _I2C
+ #include "cmem7_i2c.h"
+#endif
+
+#ifdef _MISC
+ #include "cmem7_misc.h"
+#endif
+
+#ifdef _RTC
+ #include "cmem7_rtc.h"
+#endif
+
+#ifdef _SPI
+ #include "cmem7_spi.h"
+#endif
+
+#ifdef _TIM
+ #include "cmem7_tim.h"
+#endif
+
+#ifdef _UART
+ #include "cmem7_uart.h"
+#endif
+
+#ifdef _USB
+ #include "cmem7_usb.h"
+#endif
+
+#ifdef _WDG
+ #include "cmem7_wdg.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_INCLUDES_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h
new file mode 100644
index 0000000000..d0b980aa72
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h
@@ -0,0 +1,236 @@
+/**
+ *****************************************************************************
+ * @file cmem7_misc.h
+ *
+ * @brief CMEM7 miscellaneous header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_MISC_H
+#define __CMEM7_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/**
+ * @brief NVIC initialization structure
+ */
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ============================================================================================================================
+@endcode
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete Capital-micro Devices IRQ Channels list, please
+ refer to cmem7.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+
+/** @defgroup NVIC_VectTab
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @defgroup NVIC_LP
+ * @{
+ */
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @defgroup NVIC_PriorityGroup
+ * @{
+ */
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+ ((GROUP) == NVIC_PriorityGroup_1) || \
+ ((GROUP) == NVIC_PriorityGroup_2) || \
+ ((GROUP) == NVIC_PriorityGroup_3) || \
+ ((GROUP) == NVIC_PriorityGroup_4))
+/**
+ * @}
+ */
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
+ * This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup:
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @retval None
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ * @retval None
+ */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values, ref as @ref NVIC_VectTab:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset: Vector Table base offset field. This value must be a multiple
+ * of 0x200.
+ * @retval None
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values, ref as @ref NVIC_LP:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
+
+/**
+ * @brief Memory map from address 'from' to 'address 'to' and open icache or not
+ * @param[in] from address to be mapped from
+ * @param[in] to address to be mapped to
+ * @param[in] isIcacheOn icache is on or off
+ * @retval None
+ */
+void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
+
+/**
+ * @brief Set NMI irq number, it should be one of @ref IRQn_Type.
+ * @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI
+ * interrupt routine if the specific 'irq' occurs. By default, NMI irq number
+ * is 0, same as ETH_INT_IRQn
+ * @param[in] irq irq number
+ * @retval None
+ */
+void GLB_SetNmiIrqNum(uint32_t irq);
+
+/** @defgroup SYS_CLK_SEL
+ * @{
+ */
+#define SYS_CLK_SEL_OSC 0x0
+#define SYS_CLK_SEL_DLL 0x1
+#define SYS_CLK_SEL_CRYSTAL 0x2
+#define SYS_CLK_SEL_EXTERNAL 0x3
+/**
+ * @}
+ */
+
+/**
+ * @brief Select system clock source, it should be one of @ref SYS_CLK_SEL.
+ * @Note You MUST make sure externel clock has been stabled if clock
+ * source is external before call this function.
+ * Default value is SYS_CLK_SEL_OSC
+ * @param[in] irq irq number
+ * @retval None
+ */
+void GLB_SelectSysClkSource(uint8_t source);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_MISC_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_retarget.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_retarget.h
new file mode 100644
index 0000000000..579ba63ec0
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_retarget.h
@@ -0,0 +1,87 @@
+/**
+ *****************************************************************************
+ * @file cmem7_retarget.h
+ *
+ * @brief CMEM7 retarget header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_RETARGET_H
+#define __CMEM7_RETARGET_H
+
+#include
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+#pragma import(__use_no_semihosting_swi)
+
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+FILE __stdin;
+FILE __stderr;
+
+
+int fputc(int c, FILE *f) {
+ uint8_t ch = c;
+ if (c == '\n') {
+ ch = '\r';
+ while (0 == UART_Write(PRINT_UART, 1, &ch));
+ ch = '\n';
+ }
+
+ while (0 == UART_Write(PRINT_UART, 1, &ch)) ;
+ return ch;
+}
+
+
+int fgetc(FILE *f) {
+ uint8_t ch;
+
+ while (0 == UART_Read(PRINT_UART, 1, &ch)) ;
+ return ch;
+}
+
+int ferror(FILE *f) {
+ /* Your implementation of ferror */
+ return EOF;
+}
+
+
+void _ttywrch(int c) {
+ while (0 == UART_Write(PRINT_UART, 1, (uint8_t *)&c));
+}
+
+
+void _sys_exit(int return_code) {
+label: goto label; /* endless loop */
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_RETARGET_H */
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h
new file mode 100644
index 0000000000..bb04de5d83
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h
@@ -0,0 +1,89 @@
+/**
+ *****************************************************************************
+ * @file cmem7_rtc.h
+ *
+ * @brief CMEM7 RTC header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_RTC_H
+#define __CMEM7_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup RTC_Int
+ * @{
+ */
+#define RTC_Int_Second ((uint32_t)0x00000001)
+#define RTC_Int_Microsecond ((uint32_t)0x00000002)
+#define RTC_Int_All ((uint32_t)0x00000003)
+#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0))
+/**
+ * @}
+ */
+
+/**
+ * @brief Enable or disable RTC interrupt.
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
+ * @param[in] Enable The bit indicates if specific interrupts are enable or not
+ * @retval None
+ */
+void RTC_EnableInt(uint32_t Int, BOOL Enable);
+
+/**
+ * @brief Check specific interrupts are set or not
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
+ * @retval BOOL The bit indicates if specific interrupts are set or not
+ */
+BOOL RTC_GetIntStatus(uint32_t Int);
+
+/**
+ * @brief Clear specific interrupts
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
+ * @retval None
+ */
+void RTC_ClearInt(uint32_t Int);
+
+/**
+ * @brief Get seconds since power up
+ * @param None
+ * @retval uint32_t Seconds since power up
+ */
+uint32_t RTC_GetSecond(void);
+
+/**
+ * @brief Get current micro-seconds
+ * @param None
+ * @retval uint32_t Current micro-seconds
+ */
+uint16_t RTC_GetMicroSecond(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_RTC_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_spi.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_spi.h
new file mode 100644
index 0000000000..d770005679
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_spi.h
@@ -0,0 +1,167 @@
+/**
+ *****************************************************************************
+ * @file cmem7_spi.h
+ *
+ * @brief CMEM7 SPI header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_SPI_H
+#define __CMEM7_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI0) || \
+ ((PERIPH) == SPI1))
+
+
+/** @defgroup SPI_MODE
+ * @{
+ */
+#define SPI_MODE_CPOL_0_CPHA_0 0 /*!< CPOL : Idle clock level is low level.
+ CPHA : Capture data at the first edge */
+#define SPI_MODE_CPOL_0_CPHA_1 1 /*!< CPOL : Idle clock level is low level.
+ CPHA : Capture data at the second edge */
+#define SPI_MODE_CPOL_1_CPHA_0 2 /*!< CPOL : Idle clock level is high level.
+ CPHA : Capture data at the first edge */
+#define SPI_MODE_CPOL_1_CPHA_1 3 /*!< CPOL : Idle clock level is high level.
+ CPHA : Capture data at the first edge */
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_CPOL_0_CPHA_0) || \
+ ((MODE) == SPI_MODE_CPOL_0_CPHA_1) || \
+ ((MODE) == SPI_MODE_CPOL_1_CPHA_0) || \
+ ((MODE) == SPI_MODE_CPOL_1_CPHA_1))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_INT
+ * @{
+ */
+#define SPI_INT_RX_FIFO_UNDERFLOW 0x00000001
+#define SPI_INT_RX_FIFO_OVERFLOW 0x00000002
+#define SPI_INT_RX_FIFO_ALMOST_FULL 0x00000004
+#define SPI_INT_TX_FIFO_UNDERFLOW 0x00000008
+#define SPI_INT_TX_FIFO_OVERFLOW 0x00000010
+#define SPI_INT_TX_FIFO_ALMOST_FULL 0x00000020
+#define SPI_INT_DONE 0x00000040
+#define SPI_INT_ALL 0x0000007F
+
+#define IS_SPI_INT(INT) (((INT) != 0) && (((INT) & ~SPI_INT_ALL) == 0))
+/**
+ * @}
+ */
+
+/**
+ * @brief SPI initialization structure
+ */
+typedef struct
+{
+ uint8_t SPI_Mode; /*!< indicates SPI's CPOL and CPHA, ref as @ref SPI_MODE */
+ BOOL SPI_RxEn; /*!< indicates if SPI receiver is enabled or not */
+ uint8_t SPI_BitLength; /*!< bit length while transmitting and receiving */
+ uint8_t SPI_Gap; /*!< cycle number between continuous data frame */
+ uint8_t SPI_ClockDividor; /*!< SPI clock dividor, 1 / ((1 + DIV) * 2) */
+} SPI_InitTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @brief SPI initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+ * @param[in] init A pointer to structure SPI_InitTypeDef
+ * @retval None
+ */
+void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init);
+
+/**
+ * @brief Enable or disable SPI.
+ * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+ * @param[in] Enable The bit indicates if the specific SPI is enable or not
+ * @retval None
+ */
+void SPI_Enable(SPI0_Type* SPIx, BOOL enable);
+
+/**
+ * @brief Enable or disable SPI interrupt.
+ * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
+ * @param[in] Enable The bit indicates if specific interrupts are enable or not
+ * @retval None
+ */
+void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable);
+
+/**
+ * @brief Check specific interrupts are set or not
+ * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
+ * @retval BOOL The bit indicates if specific interrupts are set or not
+ */
+BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int);
+
+/**
+ * @brief Clear specific interrupts
+ * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
+ * @retval None
+ */
+void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int);
+
+/**
+ * @brief Read data from SPI FIFO
+ * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+ * @param[in] size Expected data size to be read
+ * @param[out] data A user-allocated buffer to fetch data to be read
+ * @retval uint8_t Actual read data size
+ */
+uint8_t SPI_ReadFifo(SPI0_Type* SPIx, uint8_t size, uint32_t* data);
+
+/**
+ * @brief Write data to SPI FIFO
+ * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+ * @param[in] size Expected data size to be written
+ * @param[in] data A pointer to the data to be written
+ * @retval uint8_t Actual written data size
+ */
+uint8_t SPI_WriteFifo(SPI0_Type* SPIx, uint8_t Size, uint32_t* data);
+
+/**
+ * @brief send a SPI transcation request
+ * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+ * @param[in] size Expected data size to be written and read
+ * @retval BOOL The bit indicates if the request is sent
+ */
+BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CMEM7_SPI_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_tim.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_tim.h
new file mode 100644
index 0000000000..99a2d68fd5
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_tim.h
@@ -0,0 +1,101 @@
+/**
+ *****************************************************************************
+ * @file cmem7_tim.h
+ *
+ * @brief CMEM7 timer header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_TIM_H
+#define __CMEM7_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIMER0) || \
+ ((PERIPH) == TIMER1) || \
+ ((PERIPH) == TIMER2) || \
+ ((PERIPH) == TIMER3))
+
+/**
+ * @brief Timer initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+ * @param[in] Ms overflow micro-seconds of the specific timer
+ * @retval None
+ */
+void TIM_Init(TIMER0_Type* Timx, uint16_t Ms);
+
+/**
+ * @brief Enable or disable timer interrupt.
+ * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+ * @param[in] Enable The bit indicates if the specific interrupt is enable or not
+ * @retval None
+ */
+void TIM_EnableInt(TIMER0_Type* Timx, BOOL Enable);
+
+/**
+ * @brief Check the specific interrupt is set or not
+ * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+ * @retval BOOL The bit indicates if the specific interrupt is set or not
+ */
+BOOL TIM_GetIntStatus(TIMER0_Type* Timx);
+
+/**
+ * @brief Clear specific interrupts
+ * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+ * @retval None
+ */
+void TIM_ClearInt(TIMER0_Type* Timx);
+
+/**
+ * @brief Enable or disable timer.
+ * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+ * @param[in] Enable The bit indicates if the specific timer is enable or not
+ * @retval None
+ */
+void TIM_Enable(TIMER0_Type* Timx, BOOL Enable);
+
+/**
+ * @brief Check the specific timer is overflow or not
+ * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+ * @retval BOOL The bit indicates if the specific timer is overflow or not
+ */
+BOOL TIM_IsOverflow(TIMER0_Type* Timx);
+
+/**
+ * @brief Get current counter of timer
+ * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+ * @retval uint32_t current counter
+ */
+uint32_t TIM_GetCounter(TIMER0_Type* Timx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CMEM7_TIM_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_uart.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_uart.h
new file mode 100644
index 0000000000..1a0d7e6139
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_uart.h
@@ -0,0 +1,172 @@
+/**
+ *****************************************************************************
+ * @file cmem7_uart.h
+ *
+ * @brief CMEM7 uart header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_UART_H
+#define __CMEM7_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+#define IS_UART_ALL_PERIPH(PERIPH) (((PERIPH) == UART0) || \
+ ((PERIPH) == UART1) || \
+ ((PERIPH) == UART2))
+
+/** @defgroup UART_StopBits
+ * @{
+ */
+#define UART_StopBits_0_5 0
+#define UART_StopBits_1 1
+#define UART_StopBits_1_5 2
+#define UART_StopBits_2 3
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
+ ((STOPBITS) == UART_StopBits_0_5) || \
+ ((STOPBITS) == UART_StopBits_2) || \
+ ((STOPBITS) == UART_StopBits_1_5))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity
+ * @{
+ */
+#define UART_Parity_Even 0
+#define UART_Parity_Odd 1
+#define UART_Parity_None 2
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_Even) || \
+ ((PARITY) == UART_Parity_Odd) || \
+ ((PARITY) == UART_Parity_None))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Int
+ * @{
+ */
+#define UART_Int_RxNotEmpty 0x00000001
+#define UART_Int_TxEmpty 0x00000002
+#define UART_Int_TxHalfEmpty 0x00000004
+#define UART_Int_TxTimeoutNotEmpty 0x00000008
+#define UART_Int_TxTimeoutEmpty 0x00000010
+#define UART_Int_RxHalfFull 0x00000020
+#define UART_Int_TxFull 0x00000040
+#define UART_Int_ParityError 0x00000080
+#define UART_Int_FrameError 0x00000100
+#define UART_Int_OverrunError 0x00000200
+#define UART_Int_RxThresholdReach 0x00000400
+#define UART_Int_All 0x000007FF
+
+#define IS_UART_INT(INT) (((INT) != 0) && (((INT) & ~UART_Int_All) == 0))
+
+/**
+ * @}
+ */
+
+/**
+ * @brief UART initialization structure
+ */
+typedef struct
+{
+ uint32_t UART_BaudRate; /*!< Baudrate */
+ uint8_t UART_StopBits; /*!< Specifies the number of stop bits transmitted,
+ It's a value of @ref UART_StopBits */
+ uint8_t UART_Parity; /*!< Specifies the parity mode.
+ It's a value of @ref UART_Parity */
+ BOOL UART_LoopBack; /*!< loop back mode */
+ BOOL UART_RxEn; /*!< Receive enable bit */
+ BOOL UART_CtsEn; /*!< Clear to set */
+} UART_InitTypeDef;
+
+/**
+ * @brief UART initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+ * @param[in] init A pointer to structure UART_InitTypeDef
+ * @retval None
+ */
+void UART_Init(UART0_Type* UARTx, UART_InitTypeDef *init);
+
+/**
+ * @brief Enable or disable UART interrupt.
+ * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
+ * @param[in] Enable The bit indicates if specific interrupts are enable or not
+ * @retval None
+ */
+void UART_EnableInt(UART0_Type* UARTx, uint32_t Int, BOOL Enable);
+
+/**
+ * @brief Enable or disable UART.
+ * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+ * @param[in] Enable The bit indicates if the specific UART is enable or not
+ * @retval None
+ */
+void UART_Enable(UART0_Type* UARTx, BOOL enable);
+
+/**
+ * @brief Check specific interrupts are set or not
+ * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
+ * @retval BOOL The bit indicates if specific interrupts are set or not
+ */
+BOOL UART_GetIntStatus(UART0_Type* UARTx, uint32_t Int);
+
+/**
+ * @brief Clear specific interrupts
+ * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+ * @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
+ * @retval None
+ */
+void UART_ClearInt(UART0_Type* UARTx, uint32_t Int);
+
+/**
+ * @brief Write data to UART
+ * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+ * @param[in] Size Expected data size to be written
+ * @param[in] Data A pointer to the data to be written
+ * @retval uint8_t Actual written data size
+ */
+uint8_t UART_Write(UART0_Type* UARTx, uint8_t Size, uint8_t* Data);
+
+/**
+ * @brief Read data from UART
+ * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+ * @param[in] Size Expected data size to be read
+ * @param[out] Data A user-allocated buffer to fetch data to be read
+ * @retval uint8_t Actual read data size
+ */
+uint8_t UART_Read(UART0_Type* UARTx, uint8_t Size, uint8_t* Data);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_UART_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_usb.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_usb.h
new file mode 100644
index 0000000000..13bbaea600
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_usb.h
@@ -0,0 +1,588 @@
+/**
+ *****************************************************************************
+ * @file cmem7_usb.h
+ *
+ * @brief CMEM7 USB header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_USB_H
+#define __CMEM7_USB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+#include "string.h"
+
+/**
+ *
+ */
+#define SET_HCDMA_DESC_ADDR(a) (((uint32_t)(a)) >> 9)
+#define MIN(a, b) (((a) <= (b)) ? (a) : (b))
+#define MAX(a, b) (((a) >= (b)) ? (a) : (b))
+#define BIT(b) (0x1u << (b))
+
+/** @defgroup USB_HOST_PID
+ * @{
+ */
+#define USB_HOST_PID_DATA0 0x0 /*!< Indicates the Data PID is DATA0 */
+#define USB_HOST_PID_DATA2 0x1 /*!< Indicates the Data PID is DATA2 */
+#define USB_HOST_PID_DATA1 0x2 /*!< Indicates the Data PID is DATA1 */
+#define USB_HOST_PID_MDATA 0x3 /*!< Indicates the Data PID is MDATA (non-control) */
+#define USB_HOST_PID_SETUP 0x3 /*!< Indicates the Data PID is SETUP (control) */
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP_TYPE
+ * @{
+ */
+typedef enum {
+ USB_EP_TYPE_CONTROL = 0x0, /*!< Control */
+ USB_EP_TYPE_ISO = 0x1, /*!< Isochronous */
+ USB_EP_TYPE_BULK = 0x2, /*!< Bulk */
+ USB_EP_TYPE_INT = 0x3, /*!< Interrupt */
+} USB_EP_TYPE;
+/**
+ * @}
+ */
+
+/** @defgroup USB_ENUM_SPEED
+ * @{
+ */
+typedef enum {
+ USB_ENUM_SPEED_HS = 0x0, /*!< Enumerated Speed is High Speed */
+ USB_ENUM_SPEED_FS = 0x1, /*!< Enumerated Speed is Full Speed */
+ USB_ENUM_SPEED_LS = 0x2, /*!< Enumerated Speed is Low Speed */
+ USB_ENUM_SPEED_FS_48M = 0x3, /*!< Enumerated Speed is Full Speed (PHY clock is running at 48MHz) */
+} USB_ENUM_SPEED;
+/**
+ * @}
+ */
+
+/** @defgroup USB_INT_GP
+ * @{
+ */
+typedef enum {
+ USB_INT_GP_HOST_DISC, /*!< Device disconnection interrupt (Only for HOST Mode) */
+ USB_INT_GP_DEV_RESET, /*!< USB Port Reset Interrupt (Only for DEVICE Mode) */
+ USB_INT_GP_DEV_ENUMDONE, /*!< Enumeration Done Interrupt (Only for DEVICE Mode) */
+ USB_INT_GP_DEV_SUSP, /*!< USB Suspend Interrupt (Only for DEVICE Mode) */
+ USB_INT_GP_DEV_EARLY, /*!< USB Idle Interrupt (Only for DEVICE Mode) */
+ USB_INT_GP_SOF, /*!< SOF Interrupt */
+ USB_INT_GP_MIS, /*!< USB access overstep the boundary Interrupt */
+ USB_INT_GP_IDCHG, /*!< OTG Connector ID Status Change Interrupt */
+ USB_INT_GP_SESSREQ, /*!< Session Request / Create Interrupt */
+} USB_INT_GP;
+/**
+ * @}
+ */
+
+/** @defgroup USB_INT_OTG
+ * @{
+ */
+typedef enum {
+ USB_INT_OTG_SESEND, /*!< Session End Interrupt */
+ USB_INT_OTG_STANDAUP, /*!< B Device timeout to connect Interrupt */
+ USB_INT_OTG_HNDETECT, /*!< Host Negotiation Detected Interrupt */
+ USB_INT_OTG_HNSUCCHG, /*!< Host Negotiation Success Status Change Interrupt */
+ USB_INT_OTG_KEEPAPP, /*!< Debounce Done Interrupt (Only for HOST Mode) */
+} USB_INT_OTG;
+/**
+ * @}
+ */
+
+/** @defgroup USB_OTG_CTL
+ * @{
+ */
+typedef enum {
+ USB_OTG_DEV_HNSUCC = 8, /*!< Host Negotiation Success (Only for DEVICE Mode, Read Only) */
+ USB_OTG_DEV_HNPREQ = 9, /*!< HNP Request (Only for DEVICE Mode) */
+ USB_OTG_HST_HNPENABLE = 10, /*!< Host Set HNP Enable (Only for HOST Mode) */
+ USB_OTG_DEV_HNPENABLE = 11, /*!< Device HNP Enabled (Only for DEVICE Mode) */
+} USB_OTG_CTL;
+
+/**
+ * @}
+ */
+
+typedef union {
+ __IO uint32_t HPRT; /*!< Host Port Control and Status Register */
+
+ struct {
+ __I uint32_t PCS : 1; /*!< If a device is attached to the port */
+ __IO uint32_t PCD : 1; /*!< A device connection is detected */
+ __IO uint32_t PE : 1; /*!< Port Enable */
+ __IO uint32_t PEDC : 1; /*!< Set if when the status of the Port Enable (bit 2) of this register
+ changes */
+ __I uint32_t POA : 1; /*!< Indicates the overcurrent condition of the port */
+ __IO uint32_t POC : 1; /*!< Set if when the status of the Port Overcurrent Active bit (bit
+ 4) in this register changes */
+ __IO uint32_t PR : 1; /*!< Application and Core all can perform resume by setting, then
+ clear it whatever resume is success or not */
+ __IO uint32_t PS : 1; /*!< Sets this bit to put this port in Suspend mode */
+ __IO uint32_t PRESET : 1; /*!< sets this bit, a reset sequence is started on this port */
+ uint32_t : 1;
+ __IO uint32_t PLSDP : 1; /*!< Logic level of D+ */
+ __IO uint32_t PLSDN : 1; /*!< Logic level of D- */
+ __IO uint32_t PP : 1; /*!< this field to control power to this port. 1, power on */
+ __IO uint32_t PTC : 4; /*!< The application writes a nonzero value to this field to put
+ the port into a Test mode */
+ __I uint32_t SPEED : 2; /*!< Indicates the speed of the device attached to this port */
+ } HPRT_b; /*!< BitSize */
+} USB_REG_HPRT;
+
+typedef struct {
+ union {
+ uint32_t VALUE; /*!< provide the status of the buffer */
+ struct {
+ __IO uint32_t SIZE : 17; /*!< Total bytes to transfer for OUT; the expected transfer size for IN */
+ __IO uint32_t AQTD : 6; /*!< IN Only, Alternated Queue Transfer Descriptor Valid */
+ __IO uint32_t AQTD_VLD : 1; /*!< IN Only, Alternated Queue Transfer Descriptor Valid */
+ __IO uint32_t SUP : 1; /*!< OUT Only, it indicates that the buffer data pointed by this descriptor
+ is a setup packet of 8 bytes */
+ __IO uint32_t IOC : 1; /*!< It indicates that that the core must generate a XferCompl interrupt */
+ __IO uint32_t EOL : 1; /*!< It indicates that this is the last descriptor in the list */
+ uint32_t : 1;
+ __IO uint32_t STS : 2; /*!< The status of the rx/tx data:
+ 00=Success; 01=PKTERR; 10=Reserved; 11=Reserved */
+ uint32_t : 1;
+ __IO uint32_t A : 1; /*!< Active: 0=descriptor is not ready; 1=descriptor is ready */
+ } HOST_NISO_b; /*!< BitSize */
+ struct {
+ __IO uint32_t SIZE : 16; /*!< Total bytes to transfer for OUT; the expected transfer size for IN */
+ uint32_t : 7;
+ __IO uint32_t MTRF : 1; /*!< IN Only, Alternated Queue Transfer Descriptor Valid */
+ __IO uint32_t SR : 1; /*!< IN Only, Alternated Queue Transfer Descriptor Valid */
+ __IO uint32_t IOC : 1; /*!< It indicates that that the core must generate a XferCompl interrupt */
+ __IO uint32_t SP : 1; /*!< It indicates that this is the last descriptor in the list */
+ __IO uint32_t L : 1; /*!< It indicates that this is the last descriptor in the list */
+ __IO uint32_t STS : 2; /*!< The status of the rx/tx data:
+ 00=Success; 01=PKTERR; 10=Reserved; 11=Reserved */
+ __IO uint32_t BS : 2; /*!< Active: 0=descriptor is not ready; 1=descriptor is ready */
+ } DEV_NISO_OUT_b; /*!< BitSize */
+ struct {
+ __IO uint32_t SIZE : 16; /*!< Total bytes to transfer for OUT; the expected transfer size for IN */
+ uint32_t : 7;
+ __IO uint32_t PID : 2; /*!< IN Only, Alternated Queue Transfer Descriptor Valid */
+ __IO uint32_t IOC : 1; /*!< It indicates that that the core must generate a XferCompl interrupt */
+ __IO uint32_t SP : 1; /*!< It indicates that this is the last descriptor in the list */
+ __IO uint32_t L : 1; /*!< It indicates that this is the last descriptor in the list */
+ __IO uint32_t STS : 2; /*!< The status of the rx/tx data:
+ 00=Success; 01=PKTERR; 10=Reserved; 11=Reserved */
+ __IO uint32_t BS : 2; /*!< Active: 0=descriptor is not ready; 1=descriptor is ready */
+ } DEV_NISO_IN_b; /*!< BitSize */
+ } QUADLET;
+ uint32_t BUIFFER; /*!< points to a data buffer */
+} OTG_DESCRIPTOR;
+
+/**
+ * @brief Get OTG Connector ID Status (Is B-Device)
+ * @retval BOOL TRUE: High; FALSE: Low
+ */
+BOOL USB_ogtIsBdevID(void);
+
+/**
+ * @brief Set USB Global Interrupt Enable
+ * @param[in] enable TRUE: Enable; FALSE: Disable
+ * @retval void
+ */
+void USB_EnableInt(BOOL enable);
+
+/**
+ * @brief Flush TX/RX FIFO
+ * @param[in] num Flush FIFO£¬0: non-periodic TX FIFO (HOST Mode) or FIFO 0 (DEVICE Mode); 1: Periodic TX FIFO (HOST Mode) or FIFO 1 (DEVICE Mode); 2-15: FIFO n in DEVICE Mode; 16: Flush All TX FIFO; otherwise: Flush RX FIFO
+ * @retval void
+ */
+void USB_FlushFIFO(uint32_t num);
+
+/**
+ * @brief Initialize USB
+ * @param[in] type USB Mode, Bit0: Force HOST Mode; Bit1: Force DEVICE Mode; Bit4: Enable SRP; Bit5: Enable HNP
+ * @retval void
+ */
+void USB_coreInit(uint32_t type);
+
+/**
+ * @brief Get USB Mode (Is Host Mode?)
+ * @retval BOOL TRUE: HOST Mode; FALSE: DEVICE Mode
+ */
+BOOL USB_roleIsHost(void);
+
+/**
+ * @brief Control and get VBus Status (Only for HOST Mode)
+ * @param[in] opt Bit1: Set VBus using Bit0; Bit0: Turn VBus On or Off
+ * @retval BOOL TRUE: VBus is on; FALSE£ºVBus is off
+ * @note It cannot control VBus actually due to HW problem
+ */
+BOOL USB_hostVBus(uint32_t opt);
+
+/**
+ * @brief Initialize USB HOST Module (Only for HOST Mode)
+ * @retval void
+ */
+void USB_hostInit(void);
+
+/**
+ * @brief Set USB Port Reset Status (Only for HOST Mode)
+ * @param[in] rst TRUE: Port is reseting; FALSE: Port stop reseting
+ * @retval void
+ */
+void USB_HostResetPort(BOOL rst);
+
+/**
+ * @brief Frame Number of the next SOF (Only for HOST Mode)
+ * @retval uint16_t Frame Number of the next SOF will be send
+ */
+uint16_t USB_HostGetCurFrame(void);
+
+/**
+ * @brief Suspend USP Port (Only for HOST Mode)
+ * @retval void
+ */
+void USB_HostSuspendPort(void);
+
+/**
+ * @brief Get the device enumerated speed (Only for HOST Mode)
+ * @retval USB_ENUM_SPEED A value of @ref USB_ENUM_SPEED defined
+ */
+USB_ENUM_SPEED USB_hostGetEnumSpd(void);
+
+/**
+ * @brief Get USB Port Connection Status (Only for HOST Mode)
+ * @retval BOOL TRUE: A device is attached; FALSE: No device is attached
+ */
+BOOL USB_hostPrtConn(void);
+
+/**
+ * @brief Channel 0 Transaction (Only for HOST Mode)
+ * @param[in] devaddr USB Device Address
+ * @param[in] desc A pointer to DMA Descriptor (512-byte alignment)
+ * @param[in] ctd In terms of number of DMA descriptors (0 means start from 1st DMA descriptor)
+ * @param[in] ntd Number of Transfer Descriptors (from 0 to 63 which means from 1 to 64 descriptors)
+ * @param[in] ping TRUE: Do PING protocol (Only for OUT Transfer); Must be 0 for IN Transfer
+ * @param[in] pid PID: A value of @ref USB_HOST_PID defined: USB_HOST_PID_DATA0, USB_HOST_PID_DATA2, USB_HOST_PID_DATA1, USB_HOST_PID_MDATA or USB_HOST_PID_SETUP
+ * @param[in] mps Maximum Packet Size (in bytes)
+ * @param[in] epnum Endpoint Address
+ * @param[in] in Is IN Transfer, TRUE: IN Transfer; FALSE: OUT Transfer
+ * @param[in] eptype Endpoint Type, A value of @ref USB_EP_TYPE defined
+ * @param[in] speed Device Speed, A value of @ref USB_ENUM_SPEED defined
+ */
+void USB_hostCH0(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed);
+
+/**
+ * @brief Channel 1 Transaction (Only for HOST Mode)
+ * @see USB_hostCH0
+ */
+void USB_hostCH1(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed);
+
+/**
+ * @brief Channel 2 Transaction (Only for HOST Mode)
+ * @see USB_hostCH0
+ */
+void USB_hostCH2(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed);
+
+/**
+ * @brief Channel n Transaction (Only for HOST Mode)
+ * @param[in] ch Channel number will be used
+ * @param[in] devaddr USB Device Address
+ * @param[in] desc A pointer to DMA Descriptor (512-byte alignment)
+ * @param[in] ctd In terms of number of DMA descriptors (0 means start from 1st DMA descriptor)
+ * @param[in] ntd Number of Transfer Descriptors (from 0 to 63 which means from 1 to 64 descriptors)
+ * @param[in] ping TRUE: Do PING protocol (Only for OUT Transfer); Must be 0 for IN Transfer
+ * @param[in] pid PID: A value of @ref USB_HOST_PID defined: USB_HOST_PID_DATA0, USB_HOST_PID_DATA2, USB_HOST_PID_DATA1, USB_HOST_PID_MDATA or USB_HOST_PID_SETUP
+ * @param[in] mps Maximum Packet Size (in bytes)
+ * @param[in] epnum Endpoint Address
+ * @param[in] in Is IN Transfer, TRUE: IN Transfer; FALSE: OUT Transfer
+ * @param[in] eptype Endpoint Type, A value of @ref USB_EP_TYPE defined
+ * @param[in] speed Device Speed, A value of @ref USB_ENUM_SPEED defined
+ * @retval int returns 0 if success, otherwise returns a negative value
+ */
+int USB_hostCHn(uint32_t ch, uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed);
+
+/**
+ * @brief Halt Channel n (Only for HOST Mode)
+ * @param[in] ch Channel number will be halted
+ * @retval int returns 0 if success, otherwise returns a negative value
+ */
+int USB_hostCHnHalt(uint32_t ch);
+
+/**
+ * @brief Disable USB Port (Only for HOST Mode)
+ * @param[in] dis TRUE: Disable USB Port; FALSE: Do NOT Disable USB Port
+ * @retval BOOL If USB Port is disabled, TRUE: USB Port Disabled; FALSE: USB Port Enabled
+ * @note It CANNOT Enable USB Port; Port will be enabled automatically after the port was reset successfully.
+ */
+BOOL USB_hostPortDisable(BOOL dis);
+
+/**
+ * @brief Enable Connection Interrupt (Only for HOST Mode)
+ * @param[in] en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
+ * @retval void
+ */
+void USB_hostINT_enConn(BOOL en);
+
+/**
+ * @brief Connection Interrupt Asserted (Only for HOST Mode)
+ * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
+ * @note PCD or PEDC asserted, please call USB_hostINT_clrPCD or USB_hostINT_clrPEDC function to clear it.
+ */
+BOOL USB_hostINT_isConn(void);
+
+/**
+ * @brief Port Connection Detected (PCD) Interrupt Asserted (Only for HOST Mode)
+ * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
+ */
+BOOL USB_hostINT_isPCD(void);
+
+/**
+ * @brief Clear Port Connection Detected (PCD) Interrupt Flag (Only for HOST Mode)
+ * @retval void
+ */
+void USB_hostINT_clrPCD(void);
+
+/**
+ * @brief Port Enable/Disable Change£¨PEDC£©Interrupt Asserted (Only for HOST Mode)
+ * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
+ */
+BOOL USB_hostINT_isPEDC(void);
+
+/**
+ * @brief Clear Port Enable/Disable Change£¨PEDC£©Interrupt Flag (Only for HOST Mode)
+ * @retval void
+ */
+void USB_hostINT_clrPEDC(void);
+
+/**
+ * @brief Enable Transaction Done Interrupt (Only for HOST Mode)
+ * @param[in] ch Channel to enable
+ * @para in en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
+ * @retval int returns 0 if success, otherwise returns a negative value
+ */
+int USB_hostINT_enDone(uint32_t ch, BOOL en);
+
+/**
+ * @brief Transaction Done Interrupt Asserted (Only for HOST Mode)
+ * @param[in] ch Channel to check
+ * @retval uint32_t result, Bit0: Done; Bit1: Buffer Not Available Error; Bit2: Channel Idle; Bit3: Transaction Error
+ */
+uint32_t USB_hostINT_isDone(uint32_t ch);
+
+/**
+ * @brief Transaction Done Interrupt Asserted (Only for HOST Mode)
+ * @param[in] ch Channel to check
+ * @retval uint32_t result, 0: No interrupt is pendding
+ */
+uint32_t USB_hostINT_isPend(uint32_t ch);
+
+/**
+ * @brief Initialize USB DEVICE Module (Only for DEVICE Mode)
+ * @retval void
+ */
+void USB_devInit(void);
+
+/**
+ * @brief Get the device enumerated speed (Only for DEVICE Mode)
+ * @retval USB_ENUM_SPEED A value of @ref USB_ENUM_SPEED defined
+ */
+USB_ENUM_SPEED USB_devGetEnumSpd(void);
+
+/**
+ * @brief Set Device Address (Only for DEVICE Mode)
+ * @param[in] Device Address
+ * @retval void
+ */
+void USB_devSetAddress(uint32_t addr);
+
+
+/**
+ * @brief Endpoint 0 OUT Transation (Only for DEVICE Mode)
+ * @param[in] size Transation length (in bytes)
+ * @param[in] pktcnt Packet Count
+ * @param[in] stpcnt The number of back-to-back SETUP data packets the endpoint can receive. (0 - 3)
+ * @param[in] desc A pointer to DMA descriptors
+ * @param[in] snoop Snoop Mode, TRUE: Enable Snoop Mode, which means it does not check if the OUT packets are correct before transferring them to application memory; FLASE: Disable Snoop Mode
+ * @retval void
+ */
+void USB_devEP0out(uint32_t size, uint32_t pktcnt, uint32_t stpcnt, void *desc, BOOL snoop);
+
+/**
+ * @brief Endpoint 0 IN Transation (Only for DEVICE Mode)
+ * @param[in] size Transation length (in bytes)
+ * @param[in] pktcnt Packet Count
+ * @param[in] desc A pointer to DMA descriptors
+ * @param[in] mps Maximum Packet Size (in bytes), only 8,, 32, 64 is valid
+ * @retval BOOL TRUE: Parameter mps is valid; FLASE: Parameter mps is invalid
+ */
+BOOL USB_devEP0in(uint32_t size, uint32_t pktcnt, void *desc, uint32_t mps/*8,16,32,64-byte*/);
+
+/**
+ * @brief Active Endpoint 1 (Only for DEVICE Mode)
+ * @param[in] in Endpoint direction, TRUE: IN; FALSE: OUT
+ * @param[in] mps Maximum Packet Size (in bytes), 0 means inactive the endpoint
+ * @param[in] type Endpoint type, A value of @ref USB_EP_TYPE defined
+ * @retval void
+ * @note All Endpoint but EP0 will be inactived after USB Port reseted
+ */
+void USB_devActEP1(const BOOL in, const uint32_t mps, USB_EP_TYPE type);
+
+/**
+ * @brief Active Endpoint 2 (Only for DEVICE Mode)
+ * @see USB_devActEP1
+ */
+void USB_devActEP2(const BOOL in, const uint32_t mps, USB_EP_TYPE type);
+
+/**
+ * @brief Endpoint 1 IN Transation (Only for DEVICE Mode)
+ * @param[in] size Maximum Packet Size (in bytes)
+ * @param[in] pktcnt Packet Count
+ * @param[in] pid PID (only for interrupt/bulk), 0x1 means DATA0; 0x2 means DATA1
+ * @param[in] desc A pointer to DMA descriptors
+ * @retval void
+ * @see
+ */
+void USB_devEP1in(uint32_t size, uint32_t pktcnt, uint32_t pid, void *desc);
+
+/**
+ * @brief Endpoint 1 OUT Transation (Only for DEVICE Mode)
+ * @param[in] size Data length (in bytes)
+ * @param[in] pktcnt Packet Count
+ * @param[in] PID (only for interrupt/bulk), 0x1 means DATA0; 0x2 means DATA1
+ * @param[in] stpcnt The number of back-to-back SETUP data packets the endpoint can receive. (0 - 3)
+ * @param[in] desc A pointer to DMA descriptors
+ * @param[in] snoop Snoop Mode, TRUE: Enable Snoop Mode, which means it does not check if the OUT packets are correct before transferring them to application memory; FLASE: Disable Snoop Mode
+ * @retval void
+ */
+void USB_devEP1out(uint32_t size, uint32_t pktcnt, uint32_t pid, uint32_t stpcnt, void *desc, BOOL snoop);
+
+/**
+ * @brief Endpoint 2 IN Transation (Only for DEVICE Mode)
+ * @see USB_devEP1in
+ */
+void USB_devEP2in(uint32_t size, uint32_t pktcnt, uint32_t pid, void *desc);
+
+/**
+ * @brief Endpoint 2 OUT Transation (Only for DEVICE Mode)
+ * @see USB_devEP1out
+ */
+void USB_devEP2out(uint32_t size, uint32_t pktcnt, uint32_t pid, uint32_t stpcnt, void *desc, BOOL snoop);
+
+/**
+ * @brief Set NAK handshake (Only for DEVICE Mode)
+ * @param[in] ep Endpoint
+ * @param[in] in Endpoint Direction, TRUE: IN; FALSE: OUT
+ * @param[in] en TRUE: Enable NAK handshake; FALSE: Disable NAK handshake
+ * @retval void
+ */
+void USB_devNAKhandshake(uint32_t ep, BOOL in, BOOL en);
+
+/**
+ * @brief Set STALL handshake (Only for DEVICE Mode)
+ * @param[in] ep Endpoint
+ * @param[in] in Endpoint Direction, TRUE: IN; FALSE: OUT
+ * @param[in] en TRUE: Enable STALL handshake; FALSE: Disable STALL handshake
+ * @retval BOOL Return the old status before en is set.
+ * @note Not for ISO Endpoint; For Endpoint 0 it clears itself when a SETUP token is received.
+ */
+BOOL USB_devSTALLhandshake(uint32_t ep, BOOL in, BOOL en);
+
+/**
+ * @brief Enable Transaction Done Interrupt (Only for DEVICE Mode)
+ * @param[in] ep Endpoint
+ * @param[in] in Endpoint Direction, TRUE: IN; FALSE: OUT
+ * @para in en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
+ * @retval void
+ */
+void USB_devINT_enDone(uint32_t ep, BOOL in, BOOL en);
+
+/**
+ * @brief Transaction Done Interrupt Asserted (Only for DEVICE Mode)
+ * @param[in] ep Endpoint
+ * @param[in] in Endpoint Direction, TRUE: IN; FALSE: OUT
+ * @retval uint32_t Result, Bit0: Done; Bit1£ºBuffer Not Available Error; Bit2: SETUP Phase Done
+ */
+uint32_t USB_devINT_isDone(uint32_t ep, BOOL in);
+
+/**
+ * @brief Enable OTG Interrupt (Only for DEVICE Mode)
+ * @para in en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
+ * @retval void
+ */
+void USB_INT_enOTG(BOOL en);
+
+/**
+ * @brief OTG Interrupt Asserted
+ * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
+ */
+BOOL USB_INT_isOTG(void);
+
+/**
+ * @brief OTG Function Interrupt Asserted
+ * @param[in] otg OTG Function Interrupt to check, A value of @ref USB_INT_OTG defined
+ * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
+ */
+BOOL USB_INT_isOTGon(USB_INT_OTG otg);
+
+/**
+ * @brief Clear OTG Function Interrupt Flag
+ * @param[in] otg OTG Function Interrupt to clear, A value of @ref USB_INT_OTG defined
+ * @retval void
+ */
+void USB_INT_clrOTGon(USB_INT_OTG otg);
+
+/**
+ * @brief Enable @ref USB_INT_GP Interrupt
+ * @para in name Interrupt to operate, A value of @ref USB_INT_GP defined
+ * @para in en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
+ * @retval void
+ */
+void USB_INT_enGP(USB_INT_GP name, BOOL en);
+
+/**
+ * @brief @ref USB_INT_GP Interrupt Asserted
+ * @para in name Interrupt to check, A value of @ref USB_INT_GP defined
+ * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
+ */
+BOOL USB_INT_isGP(USB_INT_GP name);
+
+/**
+ * @brief Clear @ref USB_INT_GP Interrupt Flag
+ * @para in name Interrupt to clear, A value of @ref USB_INT_GP defined
+ * @retval void
+ */
+void USB_INT_clrGP(USB_INT_GP name);
+
+/**
+ * @brief Enable OTG Function
+ * @param[in] ctl OTG Function to operate, A value of @ref USB_OTG_CTL defined
+ * @param[in] val TRUE: Enable the function; FALSE: Disable the function
+ * @retval BOOL The old value before it configure
+ */
+BOOL USB_otgControl(USB_OTG_CTL ctl, BOOL val);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_USB_H */
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h
new file mode 100644
index 0000000000..86fecbe8fa
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h
@@ -0,0 +1,103 @@
+/**
+ *****************************************************************************
+ * @file cmem7_wdg.h
+ *
+ * @brief CMEM7 watchdog header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __CMEM7_WDG_H
+#define __CMEM7_WDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "cmem7.h"
+#include "cmem7_conf.h"
+
+/** @defgroup WDG_INT
+ * @{
+ */
+#define WDG_INT_QUARTER 0
+#define WDG_INT_HALF 1
+#define IS_WDG_INT(INT) (((INT) == WDG_INT_QUARTER) || \
+ ((INT) == WDG_INT_HALF))
+/**
+ * @}
+ */
+
+/** @defgroup WDG_TRIGGER_MODE
+ * @{
+ */
+#define WDG_TRIGGER_MODE_EDGE 0
+#define WDG_TRIGGER_MODE_LEVEL 1
+#define IS_WDG_TRIGGER_MODE(TRI) (((TRI) == WDG_TRIGGER_MODE_EDGE) || \
+ ((TRI) == WDG_TRIGGER_MODE_LEVEL))
+/**
+ * @}
+ */
+
+/**
+ * @brief Watchdog initialization
+ * @note This function should be called at first before any other interfaces.
+ * @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
+ * @param[in] ResetMicroSecond MicroSeconds lasts before global reset
+ * @retval None
+ */
+void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond);
+
+/**
+ * @brief Enable or disable watchdog interrupt.
+ * @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT
+ * @param[in] Enable The bit indicates if the specific interrupt are enable or not
+ * @retval None
+ */
+void WDG_EnableInt(uint8_t Int, BOOL Enable);
+
+/**
+ * @brief Check the specific interrupt are set or not
+ * @param None
+ * @retval BOOL The bit indicates if the specific interrupt are set or not
+ */
+BOOL WDG_GetIntStatus(void);
+
+/**
+ * @brief Clear the specific interrupt
+ * @param None
+ * @retval None
+ */
+void WDG_ClearInt(void);
+
+/**
+ * @brief Enable or disable watchdog.
+ * @param[in] Enable The bit indicates if watchdog is enable or not
+ * @retval None
+ */
+void WDG_Enable(BOOL Enable);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMEM7_WDG_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/system_cmem7.h b/bsp/CME_M7/StdPeriph_Driver/inc/system_cmem7.h
new file mode 100644
index 0000000000..de593b9ae7
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/inc/system_cmem7.h
@@ -0,0 +1,47 @@
+/**
+ *****************************************************************************
+ * @file system_cmem7.h
+ *
+ * @brief CMEM7 system initial header file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#ifndef __SYSTEM_CMEM7_H
+#define __SYSTEM_CMEM7_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ * @brief Setup the microcontroller system.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_CMEM7_H */
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_adc.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_adc.c
new file mode 100644
index 0000000000..a2605f55ec
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_adc.c
@@ -0,0 +1,309 @@
+/**
+ *****************************************************************************
+ * @file cmem7_adc.c
+ *
+ * @brief CMEM7 ADC source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_adc.h"
+#include "cmem7.h"
+
+#define ADC_SYSTEM_MODE_IDLE 0
+
+static BOOL adc_IsMultiChannel(uint32_t channel) {
+ uint32_t i = 0;
+
+ for (i = 0; channel != 0; i++) {
+ channel &= (channel - 1);
+ }
+
+ return ((i > 1) ? TRUE : FALSE);
+}
+
+static uint8_t adc_GetChannel(uint32_t channel) {
+ uint32_t i = 0;
+
+ for (i = 0; channel > 1; i++) {
+ channel >>= 1;
+ }
+
+ return i;
+}
+
+static void adc_Reset(uint8_t adc, BOOL enable) {
+ if (adc == ADC_PERIPH_1) {
+ ADC->POWERDOWN_RESET_b.POWERDOWN_ADC1 = TRUE;
+ ADC->POWERDOWN_RESET_b.RESET_ADC1 = TRUE;
+ udelay(8000);
+ if (enable) {
+ ADC->POWERDOWN_RESET_b.POWERDOWN_ADC1 = FALSE;
+ ADC->POWERDOWN_RESET_b.RESET_ADC1 = FALSE;
+ udelay(8000);
+ }
+ } else {
+ ADC->POWERDOWN_RESET_b.POWERDOWN_ADC2 = TRUE;
+ ADC->POWERDOWN_RESET_b.RESET_ADC2 = TRUE;
+ udelay(8000);
+ if (enable) {
+ ADC->POWERDOWN_RESET_b.POWERDOWN_ADC2 = FALSE;
+ ADC->POWERDOWN_RESET_b.RESET_ADC2 = FALSE;
+ udelay(8000);
+ }
+ }
+}
+
+void ADC_Init(ADC_InitTypeDef* init) {
+ assert_param(init);
+ assert_param(IS_ADC_PHASE_CTRL(init->ADC_PhaseCtrl));
+ assert_param(IS_ADC_VSEN(init->ADC_VsenSelection));
+
+ SOFT_RESET->SOFTRST_b.ADC_n = 0;
+ SOFT_RESET->SOFTRST_b.ADC_n = 1;
+
+ ADC->CFG0_b.PHASE_CTRL = init->ADC_PhaseCtrl;
+ ADC->CFG0_b.VSEN = init->ADC_VsenSelection;
+}
+
+void ADC_Enable(uint8_t adc, BOOL enable) {
+ assert_param(IS_ADC_ALL_PERIPH(adc));
+
+ adc_Reset(adc, enable);
+}
+
+void ADC_EnableInt(uint32_t Int, BOOL enable) {
+ assert_param(IS_ADC_INT(Int));
+
+ if (enable) {
+ ADC->INT_MASK &= ~Int;
+ } else {
+ ADC->INT_MASK |= Int;
+ }
+}
+
+BOOL ADC_GetIntStatus(uint32_t Int) {
+ assert_param(IS_ADC_INT(Int));
+
+ if (0 != (ADC->INT_STATUS & Int)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+void ADC_ClearInt(uint32_t Int) {
+ assert_param(IS_ADC_INT(Int));
+
+ ADC->INT_STATUS = Int;
+}
+
+BOOL ADC_StartConversion(uint8_t adc, uint8_t convMode, uint32_t channel) {
+ assert_param(IS_ADC_ALL_PERIPH(adc));
+ assert_param(IS_ADC_CONVERSION(convMode));
+
+ if (adc == ADC_PERIPH_1) {
+ assert_param(IS_ADC1_CHANNEL(channel));
+ if (ADC->BUSY_b.ADC1_BUSY) {
+ return FALSE;
+ }
+
+ if (adc_IsMultiChannel(channel)) {
+ ADC->CFG_ADC1_b.SYSTEM_MODE = ADC_SYSTEM_MODE_SINGLE_CONV;
+ ADC->CFG_ADC1_b.MULTI_CHANNEL_BIT = channel;
+ ADC->CFG_ADC1_b.MULTI_CHANNEL_CONTINUE_SCAN =
+ (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) ? 1 : 0;
+ } else {
+ ADC->CFG_ADC1_b.SYSTEM_MODE = convMode;
+
+ if (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) {
+ ADC->CFG_ADC1_b.CHANNEL_SEL = adc_GetChannel(channel);
+ } else {
+ ADC->CFG_ADC1_b.MULTI_CHANNEL_BIT = channel;
+ ADC->CFG_ADC1_b.MULTI_CHANNEL_CONTINUE_SCAN = 0;
+ }
+ }
+
+ ADC->ADC1_START_b.EN = TRUE;
+ } else {
+ assert_param(IS_ADC2_CHANNEL(channel));
+ if (ADC->BUSY_b.ADC2_BUSY) {
+ return FALSE;
+ }
+
+ if (adc_IsMultiChannel(channel)) {
+ ADC->CFG_ADC2_b.SYSTEM_MODE = ADC_SYSTEM_MODE_SINGLE_CONV;
+ ADC->CFG_ADC2_b.MULTI_CHANNEL_BIT = channel;
+ ADC->CFG_ADC2_b.MULTI_CHANNEL_CONTINUE_SCAN =
+ (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) ? 1 : 0;
+ } else {
+ ADC->CFG_ADC2_b.SYSTEM_MODE = convMode;
+
+ if (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) {
+ ADC->CFG_ADC2_b.CHANNEL_SEL = adc_GetChannel(channel);
+ } else {
+ ADC->CFG_ADC2_b.MULTI_CHANNEL_BIT = channel;
+ ADC->CFG_ADC2_b.MULTI_CHANNEL_CONTINUE_SCAN = 0;
+ }
+ }
+
+ ADC->ADC2_START_b.EN = TRUE;
+ }
+
+ return TRUE;
+}
+
+BOOL ADC_StartCalibration(uint8_t adc, uint8_t calibration) {
+ assert_param(IS_ADC_ALL_PERIPH(adc));
+ assert_param(IS_ADC_CALIBRATION(calibration));
+
+ if (adc == ADC_PERIPH_1) {
+ if (ADC->BUSY_b.ADC1_BUSY) {
+ return FALSE;
+ }
+
+ ADC->CFG_ADC1_b.SYSTEM_MODE = calibration;
+ ADC->ADC1_START_b.EN = TRUE;
+ } else {
+ if (ADC->BUSY_b.ADC2_BUSY) {
+ return FALSE;
+ }
+
+ ADC->CFG_ADC2_b.SYSTEM_MODE = calibration;
+ ADC->ADC2_START_b.EN = TRUE;
+ }
+
+ return TRUE;
+}
+
+void ADC_Stop(uint8_t adc) {
+ assert_param(IS_ADC_ALL_PERIPH(adc));
+
+ if (adc == ADC_PERIPH_1) {
+ if (IS_ADC_CONVERSION(ADC->CFG_ADC1_b.SYSTEM_MODE)) {
+ ADC->ADC1_STOP_b.EN = TRUE;
+ }
+ while (ADC->BUSY_b.ADC1_BUSY) ;
+
+ ADC->ADC1_FIFO_CLEAR_b.CLEAR = TRUE;
+ //udelay(1000);
+ ADC->ADC1_FIFO_CLEAR_b.CLEAR = FALSE;
+ } else {
+ if (IS_ADC_CONVERSION(ADC->CFG_ADC2_b.SYSTEM_MODE)) {
+ ADC->ADC2_STOP_b.EN = TRUE;
+ }
+ while (ADC->BUSY_b.ADC2_BUSY) ;
+
+ ADC->ADC2_FIFO_CLEAR_b.CLEAR = TRUE;
+ //udelay(1000);
+ ADC->ADC2_FIFO_CLEAR_b.CLEAR = FALSE;
+ }
+}
+
+BOOL ADC_IsBusy(uint8_t adc) {
+ assert_param(IS_ADC_ALL_PERIPH(adc));
+
+ if (adc == ADC_PERIPH_1) {
+ if (ADC->BUSY_b.ADC1_BUSY) {
+ return TRUE;
+ }
+ } else {
+ if (ADC->BUSY_b.ADC2_BUSY) {
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
+
+/* return value is actual read data size */
+uint8_t ADC_Read(uint8_t adc, uint8_t size, ADC_Data* data) {
+ uint8_t count = 0;
+ uint8_t sysMode;
+ uint32_t tmp = 0;
+ assert_param(IS_ADC_ALL_PERIPH(adc));
+ assert_param(data);
+
+ if (adc == ADC_PERIPH_1) {
+ sysMode = ADC->CFG_ADC1_b.SYSTEM_MODE;
+ } else {
+ sysMode = ADC->CFG_ADC2_b.SYSTEM_MODE;
+ }
+
+ if ((sysMode == ADC_SYSTEM_MODE_SINGLE_CONV) ||
+ (sysMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV)) {
+ while (count < size) {
+ if (adc == ADC_PERIPH_1) {
+ if (ADC->STATUS_b.ADC1_READ_EMPTY) {
+ break;
+ }
+
+ tmp = ADC->ADC1_FIFO_READ;
+ (data + count)->channel = 1 << ((tmp&0xf000) >> 12);
+ (data + count++)->data = (tmp & 0xfff);
+ } else {
+ if (ADC->STATUS_b.ADC2_READ_EMPTY) {
+ break;
+ }
+ tmp = ADC->ADC2_FIFO_READ;
+ (data + count)->channel = 1 << ((tmp&0xf000) >> 12);
+ (data + count++)->data = (tmp & 0xfff);
+ }
+ }
+ } else if (sysMode == ADC_CALIBRATION_OFFSET) {
+ if (adc == ADC_PERIPH_1) {
+ if (!ADC->BUSY_b.ADC1_BUSY) {
+ (data + count)->channel = ADC_CHANNEL_CALIBRATION;
+ (data + count++)->data = ADC->ADC1_OUT_OFFSET_CALIBRATION;
+ }
+ } else {
+ if (!ADC->BUSY_b.ADC2_BUSY) {
+ (data + count)->channel = ADC_CHANNEL_CALIBRATION;
+ (data + count++)->data = ADC->ADC2_OUT_OFFSET_CALIBRATION;
+ }
+ }
+ } else if (sysMode == ADC_CALIBRATION_NEGTIVE_GAIN) {
+ if (adc == ADC_PERIPH_1) {
+ if (!ADC->BUSY_b.ADC1_BUSY) {
+ (data + count)->channel = ADC_CHANNEL_CALIBRATION;
+ (data + count++)->data = ADC->ADC1_OUT_NEGTIVE_GAIN_CALIBRATION;
+ }
+ } else {
+ if (!ADC->BUSY_b.ADC2_BUSY) {
+ (data + count)->channel = ADC_CHANNEL_CALIBRATION;
+ (data + count++)->data = ADC->ADC2_OUT_NEGTIVE_GAIN_CALIBRATION;
+ }
+ }
+ } else {
+ if (adc == ADC_PERIPH_1) {
+ if (!ADC->BUSY_b.ADC1_BUSY) {
+ (data + count)->channel = ADC_CHANNEL_CALIBRATION;
+ (data + count++)->data = ADC->ADC1_OUT_POSITIVE_GAIN_CALIBRATION;
+ }
+ } else {
+ if (!ADC->BUSY_b.ADC2_BUSY) {
+ (data + count)->channel = ADC_CHANNEL_CALIBRATION;
+ (data + count++)->data = ADC->ADC2_OUT_POSITIVE_GAIN_CALIBRATION;
+ }
+ }
+ }
+
+ return count;
+}
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_aes.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_aes.c
new file mode 100644
index 0000000000..ea958d719c
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_aes.c
@@ -0,0 +1,53 @@
+/**
+ *****************************************************************************
+ * @file cmem7_aes.c
+ *
+ * @brief CMEM7 AES source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_aes.h"
+
+BOOL AES_Decrypt(const void *src, void *dst, uint32_t len)
+{
+ uint32_t *po = dst;
+ const uint32_t *pi = src;
+
+ if (len & 0xF)
+ return FALSE;
+
+ AES->FIFO_CLEAR = 1;
+ AES->FIFO_CLEAR = 0;
+ GLOBAL_CTRL->AES_BURST_TYPE = 0x1; // Cannot be 0
+ while (len > 0) {
+ while (0 == GLOBAL_CTRL->AES_STATUS_b.IDLE); // 0x41007010
+ udelay(2);
+ GLOBAL_CTRL->AES_TARGET_ADDR = (uint32_t)po; // 0x41800000;
+ po += 4;
+ len -= 4 * sizeof(uint32_t);
+ while (0 == GLOBAL_CTRL->AES_STATUS_b.RD_EMPTY); // 0x41007010
+ AES->FIFO = *pi++;
+ AES->FIFO = *pi++;
+ AES->FIFO = *pi++;
+ AES->FIFO = *pi++;
+ }
+ return TRUE;
+}
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_can.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_can.c
new file mode 100644
index 0000000000..aa2766b4f2
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_can.c
@@ -0,0 +1,386 @@
+/**
+ *****************************************************************************
+ * @file cmem7_can.c
+ *
+ * @brief CMEM7 CAN source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_can.h"
+
+typedef struct {
+ union {
+ __IO uint8_t FI; /*!< Transmit Frame Information if writting or Receive Frame Information
+ if reading, ACR[0] if reset mode */
+
+ struct {
+ __IO uint8_t DLC : 4; /*!< byte number in the data */
+ uint8_t : 2;
+ __IO uint8_t RTR : 1; /*!< 1 indicates a remote frame; 0 indicates a data frame */
+ __IO uint8_t FF : 1; /*!< 1 selects Extended Frame Format (EFF); 0 selects Standard Frame
+ Format (SFF) */
+ } FI_b; /*!< BitSize */
+ } U;
+} CAN_FRAME_INFO;
+
+typedef struct {
+ union {
+ uint16_t ID; /*!< ID */
+
+ struct {
+ uint16_t ID28_21 : 8; /*!< ID28 to ID21 */
+ uint16_t : 4;
+ uint16_t RTR : 1; /*!< if remote frame */
+ uint16_t ID20_18 : 3; /*!< ID20 to ID18 */
+ } ID_b; /*!< BitSize */
+ } U;
+} CAN_STANDARD_ID;
+
+typedef struct {
+ union {
+ uint32_t ID; /*!< ID */
+
+ struct {
+ uint32_t ID28_21 : 8; /*!< ID28 to ID21 */
+ uint32_t ID20_13 : 8; /*!< ID20 to ID13 */
+ uint32_t ID12_5 : 8; /*!< ID12 to ID5 */
+ uint32_t : 2;
+ uint32_t RTR : 1; /*!< if remote frame */
+ uint32_t ID4_0 : 5; /*!< ID4 to ID0 */
+ } ID_b; /*!< BitSize */
+ } U;
+} CAN_EXTENDED_ID;
+
+#define CAN_MODE_NORMAL 0x00000000
+#define CAN_MODE_RESET 0x00000001
+#define CAN_MODE_LISTEN_ONLY 0x00000002
+#define CAN_MODE_SELF_TEST 0x00000004
+#define CAN_MODE_SINGLE_FILTER 0x00000008
+#define CAN_MODE_SLEEP 0x00000010
+
+#define CAN_OCR_NORMAL 0x02
+#define CAN_OCR_CLOCK 0x03
+
+static BOOL can_SetFilter(CAN0_Type* CANx, CAN_FILTER *f1, CAN_FILTER *f2) {
+ if (!f1) {
+ return FALSE;
+ }
+
+ if (!IS_CAN_FLT_TYPE(f1->type)) {
+ return FALSE;
+ }
+
+ if(IS_CAN_FLT_DUAL(f1->type)) {
+ if (!f2 || IS_CAN_FLT_SINGLE(f2->type)) {
+ return FALSE;
+ }
+ }
+
+ if (f1->type == CAN_FLT_STANDARD_SINGLE) {
+ CANx->FI_OR_ACR0 = f1->ACCEPT.sf.ID28_18 >> 3;
+ CANx->DI0_OR_ACR1 = (f1->ACCEPT.sf.ID28_18 & 0x07) << 5;
+ CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.RTR << 4;
+ CANx->DI1_OR_ACR2 = f1->ACCEPT.sf.data1;
+ CANx->DI2_OR_ACR3 = f1->ACCEPT.sf.data2;
+
+ CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3;
+ CANx->DI4_OR_AMR1 = (f1->MASK.sf.ID28_18 & 0x07) << 5;
+ CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4;
+ CANx->DI5_OR_AMR2 = f1->MASK.sf.data1;
+ CANx->DI6_OR_AMR3 = f1->MASK.sf.data2;
+ } else if (f1->type == CAN_FLT_STANDARD_DUAL) {
+ CANx->FI_OR_ACR0 = f1->ACCEPT.sf.ID28_18 >> 3;
+ CANx->DI0_OR_ACR1 = (f1->ACCEPT.sf.ID28_18 & 0x07) << 5;
+ CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.RTR << 4;
+ CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.data1 >> 4;
+ CANx->DI2_OR_ACR3 = f1->ACCEPT.sf.data1 & 0x0F;
+
+ CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3;
+ CANx->DI4_OR_AMR1 = (f1->MASK.sf.ID28_18 & 0x07) << 5;
+ CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4;
+ CANx->DI4_OR_AMR1 = f1->MASK.sf.data1 >> 4;
+ CANx->DI6_OR_AMR3 = f1->MASK.sf.data1 & 0x0F;
+ } else if (f1->type == CAN_FLT_EXTENDED_SINGLE) {
+ CANx->FI_OR_ACR0 = f1->ACCEPT.ef.ID28_13 >> 8;
+ CANx->DI0_OR_ACR1 = f1->ACCEPT.ef.ID28_13 & 0xFF;
+ CANx->DI1_OR_ACR2 = f1->ACCEPT.ef.ID12_0 >> 5;
+ CANx->DI2_OR_ACR3 = (f1->ACCEPT.ef.ID12_0 & 0x1F) << 3;
+ CANx->DI2_OR_ACR3 |= f1->ACCEPT.ef.RTR << 2;
+
+ CANx->DI3_OR_AMR0 = f1->MASK.ef.ID28_13 >> 8;
+ CANx->DI4_OR_AMR1 = f1->MASK.ef.ID28_13 & 0xFF;
+ CANx->DI5_OR_AMR2 = f1->MASK.ef.ID12_0 >> 5;
+ CANx->DI6_OR_AMR3 = (f1->MASK.ef.ID12_0 & 0x1F) << 3;
+ CANx->DI6_OR_AMR3 |= f1->MASK.ef.RTR << 2;
+ } else {
+ CANx->FI_OR_ACR0 = f1->ACCEPT.ef.ID28_13 >> 8;
+ CANx->DI0_OR_ACR1 = f1->ACCEPT.ef.ID28_13 & 0xFF;
+
+ CANx->DI3_OR_AMR0 = f1->MASK.ef.ID28_13 >> 8;
+ CANx->DI4_OR_AMR1 = f1->MASK.ef.ID28_13 & 0xFF;
+ }
+
+ if (IS_CAN_FLT_DUAL(f1->type)) {
+ if (f2->type == CAN_FLT_STANDARD_DUAL) {
+ CANx->DI1_OR_ACR2 = f2->ACCEPT.sf.ID28_18 >> 3;
+ CANx->DI2_OR_ACR3 |= (f2->ACCEPT.sf.ID28_18 & 0x07) << 5;
+ CANx->DI2_OR_ACR3 |= f2->ACCEPT.sf.RTR << 4;
+
+ CANx->DI5_OR_AMR2 = f2->MASK.sf.ID28_18 >> 3;
+ CANx->DI6_OR_AMR3 |= (f2->MASK.sf.ID28_18 & 0x07) << 5;
+ CANx->DI6_OR_AMR3 |= f2->MASK.sf.RTR << 4;
+ } else {
+ CANx->DI1_OR_ACR2 = f2->ACCEPT.ef.ID28_13 >> 8;
+ CANx->DI2_OR_ACR3 = f2->ACCEPT.ef.ID28_13 & 0xFF;
+
+ CANx->DI5_OR_AMR2 = f2->MASK.ef.ID28_13 >> 8;
+ CANx->DI6_OR_AMR3 = f2->MASK.ef.ID28_13 & 0xFF;
+ }
+ }
+
+ if (IS_CAN_FLT_SINGLE(f1->type)) {
+ CANx->MODE_b.AFM = 1;
+ } else {
+ CANx->MODE_b.AFM = 0;
+ }
+
+ return TRUE;
+}
+
+BOOL CAN_Init(CAN0_Type* CANx, CAN_InitTypeDef* Init,
+ CAN_FILTER *f1, CAN_FILTER *f2) {
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(Init);
+ assert_param(IS_CAN_CDR_DIV(Init->CAN_ClockDiv));
+
+ /* Quit to sleep mode in operation mode */
+ if (CANx->MODE_b.SM) {
+ CANx->MODE_b.RM = FALSE;
+ CANx->MODE_b.SM = FALSE;
+ }
+
+ /* switch to reset mode to set parameter */
+ CANx->MODE_b.RM = TRUE;
+
+ /* disable all interrupts and clear except receive interrupt */
+ {
+ uint8_t tmp;
+ CANx->INT_EN &= ~CAN_INT_All;
+ tmp = CANx->INT;
+ tmp = tmp;
+ }
+
+ CANx->MODE_b.LOM = (Init->CAN_TxEn) ? FALSE : TRUE;
+
+ CANx->MODE_b.STM = Init->CAN_Loopback;
+
+ CANx->CDR_b.OFF = FALSE;
+ CANx->CDR_b.DIVIDER = Init->CAN_ClockDiv;
+
+ CANx->BTR0_b.BRP = Init->CAN_Prescaler;
+ CANx->BTR0_b.SJW = Init->CAN_SJW;
+
+ CANx->BTR1_b.TSEG1 = Init->CAN_TSEG1;
+ CANx->BTR1_b.TSEG2 = Init->CAN_TSEG2;
+ CANx->BTR1_b.SAM = !Init->CAN_HighSpeed;
+
+ CANx->OCR_b.MODE = CAN_OCR_CLOCK;
+
+ if (!can_SetFilter(CANx, f1, f2)) {
+ return FALSE;
+ }
+
+ /* switch to operation mode */
+ CANx->MODE_b.RM = FALSE;
+
+ return TRUE;
+}
+
+void CAN_SetSleepMode(CAN0_Type* CANx, BOOL enable) {
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* switch to operation mode */
+ CANx->MODE_b.RM = FALSE;
+
+ CANx->MODE_b.SM = enable;
+}
+
+void CAN_EnableInt(CAN0_Type* CANx, uint32_t Int, BOOL enable) {
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_INT(Int));
+
+ if (enable) {
+ CANx->INT_EN |= CAN_INT_All;
+ } else {
+ CANx->INT_EN &= ~CAN_INT_All;
+ }
+}
+
+uint8_t CAN_GetIntStatus(CAN0_Type* CANx) {
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ return CANx->INT;
+}
+
+BOOL CAN_Transmit(CAN0_Type* CANx, CAN_Frame* frame) {
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ if (!frame) {
+ return FALSE;
+ }
+
+ if (CANx->MODE_b.LOM) {
+ return FALSE;
+ }
+
+ if (CANx->MODE_b.SM) {
+ CANx->MODE_b.RM = FALSE;
+ CANx->MODE_b.SM = FALSE;
+ }
+
+ {
+ CAN_FRAME_INFO fi;
+
+ fi.U.FI_b.FF = !frame->SFF;
+ fi.U.FI_b.RTR = frame->RTR;
+ fi.U.FI_b.DLC = frame->DLC;
+
+ CANx->FI_OR_ACR0 = fi.U.FI;
+ }
+
+ if (frame->SFF) {
+ CAN_STANDARD_ID id;
+
+ id.U.ID_b.ID28_21 = frame->Id >> 3;
+ id.U.ID_b.RTR = frame->RTR;
+ id.U.ID_b.ID20_18 = frame->Id & 0x07;
+
+ CANx->DI0_OR_ACR1 = id.U.ID & 0xFF;
+ CANx->DI1_OR_ACR2 = id.U.ID >> 8;
+
+ CANx->DI2_OR_ACR3 = frame->Data[0];
+ CANx->DI3_OR_AMR0 = frame->Data[1];
+ CANx->DI4_OR_AMR1 = frame->Data[2];
+ CANx->DI5_OR_AMR2 = frame->Data[3];
+ CANx->DI6_OR_AMR3 = frame->Data[4];
+ CANx->DI7 = frame->Data[5];
+ CANx->DI8 = frame->Data[6];
+ CANx->DI9 = frame->Data[7];
+ } else {
+ CAN_EXTENDED_ID id;
+
+ id.U.ID_b.ID28_21 = frame->Id >> 21;
+ id.U.ID_b.ID20_13 = (frame->Id >> 13) & 0xFF;
+ id.U.ID_b.ID12_5 = (frame->Id >> 5) & 0xFF;
+ id.U.ID_b.RTR = frame->RTR;
+ id.U.ID_b.ID4_0 = frame->Id & 0x1F;
+
+ CANx->DI0_OR_ACR1 = id.U.ID & 0xFF;
+ CANx->DI1_OR_ACR2 = (id.U.ID >> 8) & 0xFF;
+ CANx->DI2_OR_ACR3 = (id.U.ID >> 16) & 0xFF;
+ CANx->DI3_OR_AMR0 = (id.U.ID >> 24) & 0xFF;
+
+ CANx->DI4_OR_AMR1 = frame->Data[0];
+ CANx->DI5_OR_AMR2 = frame->Data[1];
+ CANx->DI6_OR_AMR3 = frame->Data[2];
+ CANx->DI7 = frame->Data[3];
+ CANx->DI8 = frame->Data[4];
+ CANx->DI9 = frame->Data[5];
+ CANx->DI10 = frame->Data[6];
+ CANx->DI11 = frame->Data[7];
+ }
+
+ if (CANx->MODE_b.STM) {
+ CANx->CMD_b.SSR = TRUE;
+ } else {
+ CANx->CMD_b.TR = TRUE;
+ }
+
+ return TRUE;
+}
+
+BOOL CAN_Receive(CAN0_Type* CANx, CAN_Frame* frame) {
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ if (!frame) {
+ return FALSE;
+ }
+
+ if (CANx->MODE_b.SM) {
+ CANx->MODE_b.RM = FALSE;
+ CANx->MODE_b.SM = FALSE;
+ }
+
+ {
+ CAN_FRAME_INFO fi;
+
+ fi.U.FI = CANx->FI_OR_ACR0;
+
+ frame->SFF = fi.U.FI_b.FF ? FALSE : TRUE;
+ frame->RTR = fi.U.FI_b.RTR ? TRUE : FALSE;
+ frame->DLC = fi.U.FI_b.DLC;
+ }
+
+ if (frame->SFF) {
+ CAN_STANDARD_ID id;
+
+ id.U.ID = CANx->DI0_OR_ACR1;
+ id.U.ID |= CANx->DI1_OR_ACR2 << 8;
+
+ frame->Id = id.U.ID_b.ID28_21 << 3;
+ frame->Id |= id.U.ID_b.ID20_18;
+
+ frame->Data[0] = CANx->DI2_OR_ACR3;
+ frame->Data[1] = CANx->DI3_OR_AMR0;
+ frame->Data[2] = CANx->DI4_OR_AMR1;
+ frame->Data[3] = CANx->DI5_OR_AMR2;
+ frame->Data[4] = CANx->DI6_OR_AMR3;
+ frame->Data[5] = CANx->DI7;
+ frame->Data[6] = CANx->DI8;
+ frame->Data[7] = CANx->DI9;
+ } else {
+ CAN_EXTENDED_ID id;
+
+ id.U.ID = CANx->DI0_OR_ACR1;
+ id.U.ID |= CANx->DI1_OR_ACR2 << 8;
+ id.U.ID |= CANx->DI2_OR_ACR3 << 16;
+ id.U.ID |= CANx->DI3_OR_AMR0 << 24;
+
+ frame->Id = id.U.ID_b.ID28_21 << 21;
+ frame->Id |= id.U.ID_b.ID20_13 << 13;
+ frame->Id |= id.U.ID_b.ID12_5 << 5;
+ frame->Id |= id.U.ID_b.ID4_0;
+
+ frame->Data[0] = CANx->DI4_OR_AMR1;
+ frame->Data[1] = CANx->DI5_OR_AMR2;
+ frame->Data[2] = CANx->DI6_OR_AMR3;
+ frame->Data[3] = CANx->DI7;
+ frame->Data[4] = CANx->DI8;
+ frame->Data[5] = CANx->DI9;
+ frame->Data[6] = CANx->DI10;
+ frame->Data[7] = CANx->DI11;
+ }
+
+ CANx->CMD_b.RRB = TRUE;
+
+ return TRUE;
+}
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_ddr.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_ddr.c
new file mode 100644
index 0000000000..a1556a39cd
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_ddr.c
@@ -0,0 +1,523 @@
+/**
+ *****************************************************************************
+ * @file cmem7_ddr.c
+ *
+ * @brief CMEM7 DDR source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_ddr.h"
+
+#define MAX(a, b) ((a >= b) ? (a) : (b))
+#define CAL_DDR3_CL(cl) ((cl>11)?(((cl-12)<Chip_type<_16Mbx16)?(chip_info->Chip_type):(chip_info->Chip_type-_16Mbx16);
+ capacity=(chip_info->Chip_type<_16Mbx16)?(CHIP_MIN_CAPACITY*(1<Chip_num+1)):(CHIP_MIN_CAPACITY*(1<Bus_width+1)/(BUS_WIDTH_16+1));
+ return capacity;
+
+
+}
+uint32_t Calc_DDR_RFC(const MEM_CHIP_INFO *chip_info)
+{
+ uint32_t capacity=0;
+ uint32_t tRFC=0;
+ assert_param(chip_info);
+
+
+ capacity=Get_DDR_Capacity(chip_info);
+ if (chip_info->mem_type==MEM_DDR2) {
+
+ switch(capacity){
+ case CHIP_CAPACITY_32MB:tRFC=75;break;
+ case CHIP_CAPACITY_64MB:tRFC=105;break;
+ case CHIP_CAPACITY_128MB:tRFC=128;break;
+ case CHIP_CAPACITY_256MB:tRFC=195;break;
+ case CHIP_CAPACITY_512MB:tRFC=328;break;
+ }
+ }
+ else{
+ switch(capacity){
+ case CHIP_CAPACITY_64MB:tRFC=90;break;
+ case CHIP_CAPACITY_128MB:tRFC=110;break;
+ case CHIP_CAPACITY_256MB:tRFC=160;break;
+ case CHIP_CAPACITY_512MB:tRFC=300;break;
+ case CHIP_CAPACITY_1024MB:tRFC=350;break;
+ }
+ }
+
+ return tRFC;
+
+
+}
+static void DDR_Cmd(const uint32_t cmd ,const uint32_t param)
+{
+ DDRC->CMD =((cmd)|(param));
+
+}
+static void DDR_Latency(const uint32_t cycle )
+{
+ DDR_Cmd(SW_CMD_NOP,cycle);
+}
+static void DDR2_conf(const MEM_CHIP_INFO *chip_info ,const void *ddr)
+{
+ uint32_t period=0;
+ const DDR2MEM *ptr = (const DDR2MEM *)ddr;
+ uint32_t tRFC=0;
+
+ assert_param(ddr);
+ tRFC=Calc_DDR_RFC(chip_info);
+ period = (1000 / (SYSTEM_CLOCK_FREQ / 1000000));
+ CFG_CTRL->DONE_b.CMD = 0x1;
+
+ DDRC->MODE_b.LANE = 1;
+ DDRC->MODE_b.B16 = 1;
+ DDRC->REF_b.TIME =( DDR_TREF/period);
+ DDRC->RP_b.RPA = 1;
+ DDRC->RFC_b.DI = (tRFC/period);
+ DDRC->PHUNG_b.MODE = 1;
+ DDRC->RD_SEL_b.PHY_SEL = 5;
+
+ DDRC->DQSEN0_b.DL = 2;
+ DDRC->DQSEN1_b.DL = 2;
+ DDRC->DQSEN2_b.DL = 2;
+ DDRC->DQSEN3_b.DL = 2;
+ DDRC->INTCTL_b.DONE = 1;
+ DDRC->INTCTL_b.ERR = 0;
+ DDRC->RDQ_b.L3 = DDRC->RDQ_b.L2 = DDRC->RDQ_b.L1 = DDRC->RDQ_b.L0 = 0x32;
+ DDRC->ITMDLY_b.I0 = DDRC->ITMDLY_b.IS0 = DDRC->ITMDLY_b.I1 = DDRC->ITMDLY_b.IS1 =
+ DDRC->ITMDLY_b.I2 = DDRC->ITMDLY_b.IS2 = DDRC->ITMDLY_b.I3 = DDRC->ITMDLY_b.IS3 = 3;
+
+
+ DDR_Latency((POWER_UP_NOP/period));
+ DDR_Cmd(SW_CMD_NOPCKE,(PRE_ALL_NOP/period));
+ DDR_Cmd(SW_CMD_PREA,NULL);
+ DDR_Latency(ptr->tRP);/*tRP*/
+ DDR_Cmd(SW_CMD_EMR2,NULL);
+ DDR_Latency(DDR2_TMRD);
+ DDR_Cmd(SW_CMD_EMR3,NULL);
+ DDR_Latency(DDR2_TMRD);
+ DDR_Cmd(SW_CMD_DLL_EN,NULL);
+ DDR_Latency(DDR2_TMRD);
+ DDR_Cmd(SW_CMD_DLL_RST,NULL);
+ DDR_Latency(DDR2_TMRD);
+ DDR_Cmd(SW_CMD_PREA,NULL);
+ DDR_Latency(ptr->tRP);
+ DDR_Cmd(SW_CMD_REF,NULL);
+ DDR_Latency((tRFC/period));/*tRFC*/
+ DDR_Cmd(SW_CMD_REF,NULL);
+ DDR_Latency((tRFC/period));
+ DDR_Cmd(SW_CMD_MR,(((ptr->tWR-1)<tCL<MODE_b.LANE = 0x1;
+ DDRC->QUE_b.DEPTH=1;
+ DDRC->REF_b.TIME = (DDR_TREF / period);////// //2Gb periodic refresh interval 7.8us 7.8us/5ns
+ DDRC->REF_b.TRIG = 1;
+ DDRC->REF_b.THRD = 8;
+ DDRC->ZQCSR_b.EN = 1;
+ DDRC->ZQCSI = 128 * 1000000 / period;
+ DDRC->RP_b.RPA = 1;
+ DDRC->RFC_b.DI = (tRFC / period);
+
+ if (ptr->tCK == 2500) { // 200MHz
+ DDRC->RD_SEL_b.PHY_SEL = 5;
+ } else if (ptr->tCK == 3000) { // 333MHz
+ DDRC->RD_SEL_b.PHY_SEL = 6;
+ }
+
+ DDRC->PHUNG_b.MODE = 1;
+ DDRC->DQSEN0_b.DL = 2;
+ DDRC->DQSEN1_b.DL = 2;
+ DDRC->DQSEN2_b.DL = 2;
+ DDRC->DQSEN3_b.DL = 2;
+
+ // config MR#
+ DDR_Latency((POWER_UP_NOP/period));//200us nop
+ DDR_Cmd(SW_CMD_RSTH,NULL);// RESET H
+ DDR_Latency((RSTH_NOP/period));// 500us nop
+ DDR_Cmd(SW_CMD_NOPCKE,((tRFC+10)/period));// cke high 170/tck tck txpr max(5nck, trfc(min) + 10ns) 2Gb refresh time 160ns
+ DDR_Cmd(SW_CMD_EMR2,((ptr->tWCL-5)<tWR-1)<tCL))));
+ // MR0
+ // A1 , A0 2'b0 fixed 8
+ // A2 CL 0
+ // A3 nibble sequential 0 Interleave 1
+ // A6,A5,A4 CL 101 CL =9
+ // A7 normal mode 0
+ // A8 DLL reset 1
+ // A11,A10,A9 wr=(twr/ck)=(15/3)=5 =001
+ // A12 DLL control for precharge PD fast exit 1
+ // MR0 =0xb50
+ DDR_Latency(MAX(DDR3_TMOD_CK,(DDR3_TMOD/period)));// tmod max (12nck,15ns)
+ DDR_Cmd(SW_CMD_ZQCL,NULL);// ZQCL starting ZQ calibration
+ DDR_Latency(MAX(DDR3_TZQINIT_CK,(DDR3_TZQINIT/period))); // tdllk 512nck (should be 500nck)
+ DDR_Latency(DDR3_TDLLK_CK); // tZQinit max(512nck,640ns)
+
+}
+
+BOOL DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr)
+{
+ uint32_t tCL, tWR, tWCL, tWTR, tCK,mode;
+
+ assert_param(chip_info);
+ assert_param(ddr);
+ if((chip_info->Bus_widthChip_numChip_type< CHIP_TYPE_MAX))
+ {
+ if(chip_info->mem_type==MEM_DDR2)
+ {
+ mode=DDR2_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
+ }
+ else
+ {
+ mode=DDR3_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
+ }
+ if(mode==0xff)
+ {
+ return FALSE;
+ }
+
+
+ }
+ else
+ {
+ return FALSE;
+ }
+
+
+ PDPROT->LOCK_b.EN = 0;
+ do {
+ CFG_CTRL->PDLLSTR_b.C2R1D = 0; // rst dll_c2r1
+ udelay(10);
+ CFG_CTRL->PDLLSTR_b.C2R1D = 1; // releset rst
+ udelay(10);
+ } while ((PDLOCK->GCLK & 0x40) != 0x40);
+ PDPROT->LOCK_b.EN = 1;
+
+ DDRC->MODE_b.MODE = mode;
+
+ if (chip_info->mem_type==MEM_DDR2) {
+ const DDR2MEM *ptr = (const DDR2MEM *)ddr;
+ DDRC->RL_b.VAL = ptr->tCL;
+ DDRC->RCD_b.DI = ptr->tRCD;
+ DDRC->RP_b.DI = ptr->tRP;
+ DDRC->RC_b.DI = ptr->tRC;
+ DDRC->RAS_b.DI = ptr->tRAS;
+ tWR = ptr->tWR;
+ tWTR = ptr->tWTR;
+ DDRC->RRD_b.DI = ptr->tRRD;
+ DDRC->RTP_b.DI = ptr->tRTP;
+ DDRC->FAW_b.DI = ptr->tFAW;
+ DDR2_conf(chip_info,ptr);
+ } else {
+ const DDR3MEM *ptr = (const DDR3MEM *)ddr;
+ DDRC->RL_b.VAL = ptr->tCL;
+ tWCL = ptr->tWCL;
+ DDRC->RCD_b.DI = ptr->tRCD;
+ DDRC->RAS_b.DI = ptr->tRAS;
+ DDRC->RP_b.DI = ptr->tRP;
+ DDRC->RC_b.DI = ptr->tRC;
+ DDRC->RRD_b.DI = ptr->tRRD;
+ DDRC->FAW_b.DI = ptr->tFAW;
+ tWR = ptr->tWR;
+ tCK = ptr->tCK;
+ DDRC->RTP_b.DI = ptr->tRTP;
+ DDRC->ZQCL_b.DI = ptr->tZQoper;
+ DDRC->ZQCS_b.DI = ptr->tZQCS;
+ DDR3_conf(chip_info,ptr);
+ }
+
+ tCL = DDRC->RL_b.VAL;
+
+ DDRC->WTR_b.DI = (DDRC->MODE_b.MODE & 0x20) ?
+ (tWCL + tWTR + (DDRC->BURST_b.LEN ? 2 : 4)) :
+ ((tCK * 4) > 7500) ? 18 : (tCK * 4 + 7500 - 1) / 7500; //4
+
+ DDRC->CCD_b.DI = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 2 : 4) : 4;
+ DDRC->RTW_b.DI = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 4 : 6) : (tCL + DDRC->CCD_b.DI - tWCL + (DDRC->BURST_b.LEN ? 0 : 2));
+ DDRC->WTP_b.DI = (DDRC->MODE_b.MODE & 0x20) ? (tCL + tWR + (DDRC->BURST_b.LEN ? 1 : 3)) : (tWCL + tWR + (DDRC->BURST_b.LEN ? 2 : 4));
+ DDRC->WL_b.VAL = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 3) - 3) : (tWCL - 2);
+ DDRC->ODTH_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 4) - 4) : 0;
+ if (tCK == 2500) { // 200MHz
+ DDRC->ODTL_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? (tCL - 1) : (tCL + 1)) : (DDRC->BURST_b.LEN ? 4 : 6);
+ } else if (tCK == 3000) { // 333MHz
+ DDRC->ODTL_b.DL = 0x1f;
+ }
+
+
+ // DEBUG INFO HERE
+ DDRC->CTRL_b.STR = 1;
+
+ while (0 == DDRC->STA_b.EMPTY);
+ while(0 == DDRC->INTRAW_b.DONE);
+ DDRC->CTRL_b.STR = DDRC->CTRL_b.TO = 0;
+
+ return TRUE;
+}
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_dma.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_dma.c
new file mode 100644
index 0000000000..c15957ab2f
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_dma.c
@@ -0,0 +1,262 @@
+/**
+ *****************************************************************************
+ * @file cmem7_dma.c
+ *
+ * @brief CMEM7 DMA source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_dma.h"
+
+typedef struct {
+ union {
+ uint32_t CTL_LOW;
+
+ struct {
+ uint32_t INT_EN : 1;
+ uint32_t DST_TR_WIDTH: 3;
+ uint32_t SRC_TR_WIDTH: 3;
+ uint32_t DINC : 2;
+ uint32_t SINC : 2;
+ uint32_t DEST_MSIZE : 3;
+ uint32_t SRC_MSIZE : 3;
+ uint32_t SRC_GATHER_EN: 1;
+ uint32_t DST_SCATTER_EN: 1;
+ uint32_t : 1;
+ uint32_t TT_FC : 3;
+ uint32_t DMS : 2;
+ uint32_t SMS : 2;
+ uint32_t LLP_DST_EN : 1;
+ uint32_t LLP_SRC_EN : 1;
+ } CTL_LOW_b;
+ } INNER;
+} INNER_CTL_LOW;
+
+typedef struct {
+ union {
+ uint32_t CTL_HI;
+
+ struct {
+ uint32_t BLOCK_TS : 12;
+ uint32_t DONE : 1;
+ } CTL_HI_b;
+ } INNER;
+} INNER_CTL_HIGH;
+
+typedef struct {
+ uint32_t srcAddr;
+ uint32_t dstAddr;
+ uint32_t nextBlock;
+ INNER_CTL_LOW low;
+ INNER_CTL_HIGH high;
+} INNER_BLOCK_DESC;
+
+
+#define DMA_MAX_CHANNEL_NUM 8
+
+#define DMA_TR_WIDTH_8_BIT 0
+#define DMA_TR_WIDTH_16_BIT 1
+#define DMA_TR_WIDTH_32_BIT 2
+#define DMA_TR_WIDTH_64_BIT 3
+#define DMA_TR_WIDTH_128_BIT 4
+#define DMA_TR_WIDTH_256_BIT 5
+
+#define DMA_INC_INCREMENT 0
+#define DMA_INC_DECREMENT 1
+#define DMA_INC_NO_CHANGE 2
+
+#define DMA_LOCK_DMA_TRANSFER 0
+#define DMA_LOCK_DMA_BLOCK_TRANSFER 1
+#define DMA_LOCK_DMA_BLOCK_TRANSACTION 2
+
+
+void DMA_Init() {
+ DMA->DMA_EN_b.EN = TRUE;
+
+ // only open channel 0
+ DMA->CH_EN = (0xFF << DMA_MAX_CHANNEL_NUM) | 0x0;
+
+ DMA_ClearInt(DMA_Int_All);
+ DMA_EnableInt(DMA_Int_All, FALSE);
+
+ DMA->SAR0 = 0x0;
+ DMA->DAR0 = 0x0;
+
+ DMA->CTL_HI0_b.BLOCK_TS = 0;
+ DMA->CTL_LOW0_b.INT_EN = FALSE;
+ DMA->CTL_LOW0_b.DST_TR_WIDTH = DMA_TR_WIDTH_32_BIT;
+ DMA->CTL_LOW0_b.SRC_TR_WIDTH = DMA_TR_WIDTH_32_BIT;
+ DMA->CTL_LOW0_b.DINC = DMA_INC_INCREMENT;
+ DMA->CTL_LOW0_b.SINC = DMA_INC_INCREMENT;
+ DMA->CTL_LOW0_b.DEST_MSIZE = 0;
+ DMA->CTL_LOW0_b.SRC_MSIZE = 0;
+ DMA->CTL_LOW0_b.SRC_GATHER_EN = FALSE;
+ DMA->CTL_LOW0_b.DST_SCATTER_EN = FALSE;
+ DMA->CTL_LOW0_b.TT_FC = 0;
+ DMA->CTL_LOW0_b.DMS = 0;
+ DMA->CTL_LOW0_b.SMS = 0;
+ DMA->CTL_LOW0_b.LLP_DST_EN = FALSE;
+ DMA->CTL_LOW0_b.LLP_SRC_EN = FALSE;
+
+ DMA->LLP0_b.LOC = 0;
+ DMA->LLP0_b.LMS = 0;
+
+ DMA->SGR0_b.SGC = 0x1;
+ DMA->SGR0_b.SGI = 0x0;
+
+ DMA->DSR0_b.DSC = 0x0;
+ DMA->DSR0_b.DSI = 0x0;
+
+ DMA->SSTATAR0 = 0x0;
+ DMA->DSTATAR0 = 0x0;
+
+ DMA->CFG_HI0 = 0x0;
+ DMA->CFG_LOW0_b.CH_PRIOR = 0;
+ DMA->CFG_LOW0_b.CH_SUSP = 0;
+ DMA->CFG_LOW0_b.HS_SEL_DST = 0;
+ DMA->CFG_LOW0_b.LOCK_B_L = 0;
+ DMA->CFG_LOW0_b.HS_SEL_SRC = 0;
+ DMA->CFG_LOW0_b.LOCK_CH_L = DMA_LOCK_DMA_TRANSFER;
+ DMA->CFG_LOW0_b.LOCK_B_L = DMA_LOCK_DMA_TRANSFER;
+ DMA->CFG_LOW0_b.LOCK_CH = TRUE;
+ DMA->CFG_LOW0_b.LOCK_B = TRUE;
+ DMA->CFG_LOW0_b.DST_HS_POL = 0;
+ DMA->CFG_LOW0_b.SRC_HS_POL = 0;
+ DMA->CFG_LOW0_b.RELOAD_SRC = FALSE;
+ DMA->CFG_LOW0_b.RELOAD_DST = FALSE;
+}
+
+void DMA_EnableInt(uint32_t Int, BOOL enable) {
+ assert_param(IS_DMA_INT(Int));
+
+ if (enable) {
+ if (Int & DMA_Int_TfrComplete) {
+ DMA->INT_EN_TFR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
+ }
+
+ if (Int & DMA_Int_Err) {
+ DMA->INT_EN_ERR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
+ }
+ } else {
+ if (Int & DMA_Int_TfrComplete) {
+ DMA->INT_EN_TFR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x0;
+ }
+
+ if (Int & DMA_Int_Err) {
+ DMA->INT_EN_ERR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x0;
+ }
+ }
+}
+
+BOOL DMA_GetIntStatus(uint32_t Int) {
+ assert_param(IS_DMA_INT(Int));
+
+ if (Int & DMA_Int_TfrComplete) {
+ if (DMA->INT_TFR) {
+ return TRUE;
+ }
+ }
+
+ if (Int & DMA_Int_Err) {
+ if (DMA->INT_ERR) {
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
+
+void DMA_ClearInt(uint32_t Int) {
+ assert_param(IS_DMA_INT(Int));
+
+ if (Int & DMA_Int_TfrComplete) {
+ DMA->INT_CLEAR_TFR = 0x1;
+ }
+
+ if (Int & DMA_Int_Err) {
+ DMA->INT_CLEAR_ERR = 0x1;
+ }
+}
+
+BOOL DMA_IsBusy() {
+ return (DMA->CH_EN_b.EN) ? TRUE : FALSE;
+}
+
+BOOL DMA_Transfer(BLOCK_DESC *blockList) {
+ BLOCK_DESC *p;
+ if (!blockList) {
+ return FALSE;
+ }
+
+ if (DMA_IsBusy()) {
+ return FALSE;
+ }
+
+ p = blockList;
+ while (p) {
+ BOOL llp = FALSE;
+ INNER_BLOCK_DESC *inner = (INNER_BLOCK_DESC *)p;
+ if (p->nextBlock) {
+ llp = TRUE;
+ }
+
+ inner->high.INNER.CTL_HI = 0;
+ inner->high.INNER.CTL_HI_b.BLOCK_TS = (p->number >> DMA_TR_WIDTH_32_BIT);
+ inner->high.INNER.CTL_HI_b.DONE = 0;
+
+ inner->nextBlock = p->nextBlock;
+
+ inner->low.INNER.CTL_LOW = 0;
+ inner->low.INNER.CTL_LOW_b.INT_EN = TRUE;
+ inner->low.INNER.CTL_LOW_b.DST_TR_WIDTH = DMA_TR_WIDTH_32_BIT;
+ inner->low.INNER.CTL_LOW_b.SRC_TR_WIDTH = DMA_TR_WIDTH_32_BIT;
+ inner->low.INNER.CTL_LOW_b.DINC = DMA_INC_INCREMENT;
+ inner->low.INNER.CTL_LOW_b.SINC = DMA_INC_INCREMENT;
+ inner->low.INNER.CTL_LOW_b.DEST_MSIZE = 0;
+ inner->low.INNER.CTL_LOW_b.SRC_MSIZE = 0;
+ inner->low.INNER.CTL_LOW_b.SRC_GATHER_EN = FALSE;
+ inner->low.INNER.CTL_LOW_b.DST_SCATTER_EN = FALSE;
+ inner->low.INNER.CTL_LOW_b.TT_FC = 0;
+ inner->low.INNER.CTL_LOW_b.DMS = 0;
+ inner->low.INNER.CTL_LOW_b.SMS = 0;
+ inner->low.INNER.CTL_LOW_b.LLP_DST_EN = llp;
+ inner->low.INNER.CTL_LOW_b.LLP_SRC_EN = llp;
+
+ if ((uint32_t)inner == (uint32_t)blockList) {
+ // copy to DMA
+ DMA->SAR0 = llp ? 0x0 : inner->srcAddr ;
+ DMA->DAR0 = llp ? 0x0 : inner->dstAddr ;
+
+ DMA->CTL_HI0 = llp ? 0x0 : inner->high.INNER.CTL_HI;
+ DMA->CTL_LOW0 = inner->low.INNER.CTL_LOW;
+
+ DMA->LLP0 = llp ? (uint32_t)inner : 0x0;
+ }
+
+ p = (BLOCK_DESC *)inner->nextBlock;
+ }
+
+ // open channel 0
+ DMA->CH_EN = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
+
+ return TRUE;
+}
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_efuse.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_efuse.c
new file mode 100644
index 0000000000..ad84a40fe9
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_efuse.c
@@ -0,0 +1,255 @@
+/**
+ *****************************************************************************
+ * @file cmem7_efuse.c
+ *
+ * @brief CMEM7 EFUSE source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_efuse.h"
+
+static void efuse_SetClock(uint8_t dividor) {
+ if (dividor <= 2) {
+ GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 0;
+ } else if (dividor <= 4) {
+ GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 1;
+ } else if (dividor <= 8) {
+ GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 2;
+ } else {
+ GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 3;
+ }
+}
+
+static uint32_t efuse_GetClock() {
+ return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK + 1));
+}
+
+// static uint8_t efuse_Crc8Bit(uint8_t data, uint8_t crc) {
+// uint8_t newCrc;
+// uint8_t d[8], c[8], i;
+//
+// for (i = 0; i < 8; i++) {
+// d[i] = (data >> i) & 0x01;
+// c[i] = (crc >> i) & 0x01;
+// }
+//
+// newCrc = d[7] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[7];
+// newCrc |= (d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6]) << 1;
+// newCrc |= (d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6]) << 2;
+// newCrc |= (d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7]) << 3;
+// newCrc |= (d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4]) << 4;
+// newCrc |= (d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5]) << 5;
+// newCrc |= (d[6] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[6]) << 6;
+// newCrc |= (d[7] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[7]) << 1;
+//
+// return newCrc;
+// }
+
+// static uint8_t efuse_Crc(EFUSE_AesKey* key, uint8_t lock, BOOL isLowRegion) {
+// uint8_t crc = 0;
+//
+// if (isLowRegion) {
+// crc = efuse_Crc8Bit(key->key0, crc);
+// crc = efuse_Crc8Bit(key->key0 >> 8, crc);
+// crc = efuse_Crc8Bit(key->key0 >> 16, crc);
+// crc = efuse_Crc8Bit(key->key0 >> 24, crc);
+// crc = efuse_Crc8Bit(key->key1, crc);
+// crc = efuse_Crc8Bit(key->key1 >> 8, crc);
+// crc = efuse_Crc8Bit(key->key1 >> 16, crc);
+// crc = efuse_Crc8Bit(key->key1 >> 24, crc);
+// crc = efuse_Crc8Bit(key->key2, crc);
+// crc = efuse_Crc8Bit(key->key2 >> 8, crc);
+// crc = efuse_Crc8Bit(key->key2 >> 16, crc);
+// crc = efuse_Crc8Bit(key->key2 >> 24, crc);
+// crc = efuse_Crc8Bit(key->key3, crc);
+// crc = efuse_Crc8Bit(key->key3 >> 8, crc);
+// crc = efuse_Crc8Bit(key->key3 >> 16, crc);
+// crc = efuse_Crc8Bit(key->key3 >> 24, crc);
+// crc = efuse_Crc8Bit(lock, crc);
+// crc = efuse_Crc8Bit(0x0, crc);
+// crc = efuse_Crc8Bit(0x0, crc);
+// } else {
+// crc = efuse_Crc8Bit(key->key4, crc);
+// crc = efuse_Crc8Bit(key->key4 >> 8, crc);
+// crc = efuse_Crc8Bit(key->key4 >> 16, crc);
+// crc = efuse_Crc8Bit(key->key4 >> 24, crc);
+// crc = efuse_Crc8Bit(key->key5, crc);
+// crc = efuse_Crc8Bit(key->key5 >> 8, crc);
+// crc = efuse_Crc8Bit(key->key5 >> 16, crc);
+// crc = efuse_Crc8Bit(key->key5 >> 24, crc);
+// crc = efuse_Crc8Bit(key->key6, crc);
+// crc = efuse_Crc8Bit(key->key6 >> 8, crc);
+// crc = efuse_Crc8Bit(key->key6 >> 16, crc);
+// crc = efuse_Crc8Bit(key->key6 >> 24, crc);
+// crc = efuse_Crc8Bit(key->key7, crc);
+// crc = efuse_Crc8Bit(key->key7 >> 8, crc);
+// crc = efuse_Crc8Bit(key->key7 >> 16, crc);
+// crc = efuse_Crc8Bit(key->key7 >> 24, crc);
+// crc = efuse_Crc8Bit(lock, crc);
+// crc = efuse_Crc8Bit(0x0, crc);
+// crc = efuse_Crc8Bit(0x0, crc);
+// }
+//
+// return crc;
+// }
+
+void EFUSE_Init(EFUSE_InitTypeDef* init) {
+ assert_param(init);
+ assert_param(IS_EFUSE_TMRF(init->EFUSE_TMRF));
+
+ efuse_SetClock(init->EFUSE_ClockDividor);
+ EFUSE->USER_CTRL_LOW_b.TMRF = init->EFUSE_TMRF;
+ EFUSE->USER_CTRL_HI_b.TMRF = init->EFUSE_TMRF;
+ if (init->timing) {
+ uint32_t value;
+
+ value = (init->timing->EFUSE_Tpwph * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_0_b.TPWPH = value >> 2;
+ EFUSE->TIMING_1_b.TPWPH = value & 0x00000003;
+
+ value = (init->timing->EFUSE_Trac * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_0_b.TRAC = value;
+
+ value = (init->timing->EFUSE_Trah * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_0_b.TRAH = value;
+
+ value = (init->timing->EFUSE_Trpw * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_0_b.TRPW = value;
+
+ value = (init->timing->EFUSE_Trc * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_0_b.TRC = value;
+
+ value = (init->timing->EFUSE_Tesr * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_0_b.TESR = value;
+
+ value = (init->timing->EFUSE_Tprs * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_0_b.TPRS = value;
+
+ value = (init->timing->EFUSE_Tpi * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_1_b.TPIT = value;
+
+ value = (init->timing->EFUSE_Tpp * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_1_b.TPP = value;
+
+ value = (init->timing->EFUSE_Teps * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_1_b.TEPS = value;
+
+ value = (init->timing->EFUSE_Teps * (efuse_GetClock() / 1000000) / 1000);
+ value = (value == 0) ? 1 : value;
+ EFUSE->TIMING_1_b.TPWPS = value;
+ }
+}
+
+/* It only can be written once */
+// BOOL EFUSE_Write(EFUSE_AesKey* key) {
+// assert_param(key);
+//
+// if ((EFUSE->USER_CTRL_LOW_b.LOCK || EFUSE->USER_CTRL_LOW_b.BUSY) ||
+// (EFUSE->USER_CTRL_HI_b.LOCK || EFUSE->USER_CTRL_HI_b.BUSY)) {
+// return FALSE;
+// }
+//
+// // write low region
+// EFUSE->USER_DATA0_LOW = key->key0;
+// EFUSE->USER_DATA1_LOW = key->key1;
+// EFUSE->USER_DATA2_LOW = key->key2;
+// EFUSE->USER_DATA3_LOW = key->key3;
+// EFUSE->USER_DATA4_LOW_b.CRC = efuse_Crc(key, 0x1, TRUE);
+// EFUSE->USER_DATA4_LOW_b.LOCK = 1;
+// EFUSE->USER_CTRL_LOW_b.WR_EN = FALSE;
+// EFUSE->USER_CTRL_LOW_b.WR_EN = TRUE;
+//
+// udelay(1000);
+// while (EFUSE->USER_CTRL_LOW_b.BUSY) ;
+//
+// if (EFUSE->USER_CTRL_LOW_b.WR_CRC_ERR) {
+// return FALSE;
+// }
+//
+// // write high region
+// EFUSE->USER_DATA0_HI = key->key4;
+// EFUSE->USER_DATA1_HI = key->key5;
+// EFUSE->USER_DATA2_HI = key->key6;
+// EFUSE->USER_DATA3_HI = key->key7;
+// EFUSE->USER_DATA4_HI_b.CRC = efuse_Crc(key, 0x1, FALSE);
+// EFUSE->USER_DATA4_HI_b.LOCK = 1;
+// EFUSE->USER_CTRL_HI_b.WR_EN = FALSE;
+// EFUSE->USER_CTRL_HI_b.WR_EN = TRUE;
+//
+// udelay(1000);
+// while (EFUSE->USER_CTRL_HI_b.BUSY) ;
+//
+// if (EFUSE->USER_CTRL_HI_b.WR_CRC_ERR) {
+// return FALSE;
+// }
+// return TRUE;
+// }
+
+BOOL EFUSE_Compare(EFUSE_AesKey* key) {
+ assert_param(key);
+
+ if (EFUSE->USER_CTRL_LOW_b.BUSY || EFUSE->USER_CTRL_HI_b.BUSY) {
+ return FALSE;
+ }
+
+ // compare low region
+ EFUSE->USER_DATA0_LOW = key->key0;
+ EFUSE->USER_DATA1_LOW = key->key1;
+ EFUSE->USER_DATA2_LOW = key->key2;
+ EFUSE->USER_DATA3_LOW = key->key3;
+ EFUSE->USER_CTRL_LOW_b.RD_EN = FALSE;
+ EFUSE->USER_CTRL_LOW_b.RD_EN = TRUE;
+
+ udelay(2);
+ while (EFUSE->USER_CTRL_LOW_b.BUSY) ;
+
+ if (EFUSE->USER_CTRL_LOW_b.COMPARE_FAIL) {
+ return FALSE;
+ }
+
+ // compare high region
+ EFUSE->USER_DATA0_HI = key->key4;
+ EFUSE->USER_DATA1_HI = key->key5;
+ EFUSE->USER_DATA2_HI = key->key6;
+ EFUSE->USER_DATA3_HI = key->key7;
+ EFUSE->USER_CTRL_HI_b.RD_EN = FALSE;
+ EFUSE->USER_CTRL_HI_b.RD_EN = TRUE;
+
+ udelay(2);
+ while (EFUSE->USER_CTRL_HI_b.BUSY) ;
+
+ if (EFUSE->USER_CTRL_HI_b.COMPARE_FAIL) {
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c
new file mode 100644
index 0000000000..c8eb45fba0
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c
@@ -0,0 +1,629 @@
+/**
+ *****************************************************************************
+ * @file cmem7_eth.c
+ *
+ * @brief CMEM7 ethernet source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_eth.h"
+
+
+typedef struct {
+ union {
+ uint32_t TX0;
+
+ struct {
+ uint32_t : 1;
+ uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */
+ uint32_t : 1;
+ uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */
+ uint32_t : 1;
+ uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */
+ uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */
+ uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */
+ uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */
+ uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */
+ uint32_t : 2;
+ uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */
+ uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */
+ uint32_t : 3;
+ uint32_t TCH : 1; /*!< Second Address Chained */
+ uint32_t : 4;
+ uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */
+ uint32_t : 2;
+ uint32_t FS : 1; /*!< first segment flag */
+ uint32_t LS : 1; /*!< last segment flag */
+ uint32_t IC : 1; /*!< Interrupt on Completion */
+ uint32_t OWN : 1; /*!< Descriptor is owned by self or hardware */
+ } TX0_b;
+ } TX_0;
+
+ union {
+ uint32_t TX1;
+
+ struct {
+ uint32_t SIZE : 13; /*!< buffer size */
+ uint32_t : 19;
+ } TX1_b;
+ } TX_1;
+
+ uint32_t bufAddr;
+ uint32_t nextDescAddr;
+ uint64_t reserved;
+ uint64_t timeStamp; /*!< time stamp in the last segment */
+} INNER_ETH_TX_DESC;
+
+typedef struct {
+ union {
+ uint32_t RX0;
+
+ struct {
+ uint32_t : 1;
+ uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */
+ uint32_t : 5;
+ uint32_t TTSE : 1; /*!< timestamp available while last segment */
+ uint32_t LS : 1; /*!< last segment flag */
+ uint32_t FS : 1; /*!< first segment flag */
+ uint32_t : 1;
+ uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */
+ uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */
+ uint32_t : 2;
+ uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */
+ uint32_t FL : 14; /*!< frame length while last segment */
+ uint32_t : 1;
+ uint32_t OWN : 1; /*!< Descriptor is owned by self or hardware */
+ } RX0_b;
+ } RX_0;
+
+ union {
+ uint32_t RX1;
+
+ struct {
+ uint32_t SIZE : 13; /*!< buffer size */
+ uint32_t : 1;
+ uint32_t RCH : 1; /*!< Second Address Chained */
+ uint32_t : 16;
+ uint32_t DIC : 1; /*!< Disable interrupt on Completion */
+ } RX1_b;
+ } RX_1;
+
+ uint32_t bufAddr;
+ uint32_t nextDescAddr;
+ uint64_t reserved;
+ uint64_t timeStamp; /*!< time stamp while the last segment */
+} INNER_ETH_RX_DESC;
+
+
+#define PHY_OP_READ 0x0
+#define PHY_OP_WRITE 0x1
+
+#define ETH_BURST_MODE_FIXED 0x0
+#define ETH_BURST_MODE_UNDERSIZE 0x1
+#define ETH_BURST_MODE_MIXED 0x2
+
+#define ETH_BURST_LENGTH_MIN 1
+#define ETH_BURST_LENGTH_MAX 256
+#define ETH_BURST_LENGTH_8X_SWITCH 32
+#define ETH_BURST_LENGTH_8X_MIN 8
+
+#define ETH_DMA_ARBITRATION_ROUND_ROBIN 0x0
+#define ETH_DMA_ARBITRATION_FIXED_PRIORITY 0x1
+
+#define ETH_RX_THRESHOLD_64 0x0
+#define ETH_RX_THRESHOLD_32 0x1
+#define ETH_RX_THRESHOLD_96 0x2
+#define ETH_RX_THRESHOLD_128 0x3
+
+#define ETH_TX_THRESHOLD_64 0x0
+#define ETH_TX_THRESHOLD_128 0x1
+#define ETH_TX_THRESHOLD_192 0x2
+#define ETH_TX_THRESHOLD_256 0x3
+#define ETH_TX_THRESHOLD_40 0x4
+#define ETH_TX_THRESHOLD_32 0x5
+#define ETH_TX_THRESHOLD_24 0x6
+#define ETH_TX_THRESHOLD_16 0x7
+
+#define ETH_INT_ABNORMAL_SUMMARY 0x8000
+#define ETH_INT_NORMAL_SUMMARY 0x10000
+
+#define IS_ETH_INT_NORMAL(INT) ((INT & ETH_INT_TX_COMPLETE_FRAME) || \
+ (INT & ETH_INT_TX_BUF_UNAVAI) || \
+ (INT & ETH_INT_RX_COMPLETE_FRAME))
+
+#define IS_ETH_INT_ABNORMAL(INT) ((INT & ETH_INT_TX_STOP) || \
+ (INT & ETH_INT_RX_OVERFLOW) || \
+ (INT & ETH_INT_TX_UNDERFLOW) || \
+ (INT & ETH_INT_RX_BUF_UNAVAI) || \
+ (INT & ETH_INT_RX_STOP) || \
+ (INT & ETH_INT_BUS_FATAL_ERROR))
+
+#define ETH_PREAMBLE_7_BYTE 0x0
+#define ETH_PREAMBLE_5_BYTE 0x1
+#define ETH_PREAMBLE_3_BYTE 0x2
+
+#define ETH_LINE_SPEED_1000M_BPS 0x0
+#define ETH_LINE_SPEED_10_100M_BPS 0x1
+
+#define ETH_EXACT_SPEED_10M_BPS 0x0
+#define ETH_EXACT_SPEED_100M_BPS 0x1
+
+#define ETH_SOURCE_ADDR_REPLACE 0x3
+
+#define ETH_PASS_CTRL_FRAME_ALL 0x0
+
+#define ETH_DESC_OWN_BY_SELF 0x0
+#define ETH_DESC_OWN_BY_HW 0x1
+
+
+static void mac_SwReset(void) {
+ ETH->BUS_MODE_b.SWR = 1;
+ while (ETH->BUS_MODE_b.SWR) ;
+ while (ETH->AHB_STATUS_b.BUSY) ;
+}
+
+static void mac_SetConfig(ETH_InitTypeDef *init) {
+ ETH->CONFIG_b.PRELEN = ETH_PREAMBLE_7_BYTE;
+ ETH->CONFIG_b.RX_EN = init->ETH_RxEn;
+ ETH->CONFIG_b.TX_EN = init->ETH_TxEn;
+ ETH->CONFIG_b.DC_EN = FALSE;
+ ETH->CONFIG_b.ACS = FALSE;
+ ETH->CONFIG_b.LUD = init->ETH_LinkUp;
+ ETH->CONFIG_b.IPC = init->ETH_ChecksumOffload;
+ ETH->CONFIG_b.DM = init->ETH_Duplex;
+ ETH->CONFIG_b.LM = FALSE;
+ ETH->MMC_RX_MASK = 0xFFFFFFFF;
+ ETH->MMC_TX_MASK = 0xFFFFFFFF;
+
+ if (init->ETH_Speed == ETH_SPEED_10M) {
+ ETH->CONFIG_b.FES = ETH_EXACT_SPEED_10M_BPS;
+ ETH->CONFIG_b.PS = ETH_LINE_SPEED_10_100M_BPS;
+ } else if (init->ETH_Speed == ETH_SPEED_100M) {
+ ETH->CONFIG_b.FES = ETH_EXACT_SPEED_100M_BPS;
+ ETH->CONFIG_b.PS = ETH_LINE_SPEED_10_100M_BPS;
+ } else {
+ ETH->CONFIG_b.FES = ETH_EXACT_SPEED_100M_BPS;
+ ETH->CONFIG_b.PS = ETH_LINE_SPEED_1000M_BPS;
+ }
+
+ ETH->CONFIG_b.JE = init->ETH_JumboFrame;
+
+ ETH->CONFIG_b.JD = TRUE;
+ ETH->CONFIG_b.WD = TRUE;
+ ETH->CONFIG_b.TC = FALSE;
+ ETH->CONFIG_b.CST = FALSE;
+ ETH->CONFIG_b.TWOKPE = FALSE;
+ ETH->CONFIG_b.SARC = ETH_SOURCE_ADDR_REPLACE;
+}
+
+static void mac_SetMacAddr(uint8_t *mac) {
+ ETH->ADDR0_HIGH = (mac[5] << 8) | mac[4];
+ ETH->ADDR0_LOW = (mac[3] << 24) | (mac[2] << 16) |
+ (mac[1] << 8) | mac[0];
+}
+
+static void mac_SetBurst(
+ uint8_t mode, uint32_t rxBurstLen, uint32_t txBurstLen) {
+ ETH->BUS_MODE_b.RIB = FALSE;
+ ETH->BUS_MODE_b.AAL = FALSE;
+
+ if (mode == ETH_BURST_MODE_FIXED) {
+ ETH->BUS_MODE_b.FB = TRUE;
+ ETH->BUS_MODE_b.MB = FALSE;
+ } else if (mode == ETH_BURST_MODE_UNDERSIZE) {
+ ETH->BUS_MODE_b.FB = FALSE;
+ ETH->BUS_MODE_b.MB = FALSE;
+ } else {
+ ETH->BUS_MODE_b.FB = TRUE;
+ ETH->BUS_MODE_b.MB = TRUE;
+ }
+
+ rxBurstLen = 1 << rxBurstLen;
+ rxBurstLen = (rxBurstLen > ETH_BURST_LENGTH_MAX) ?
+ ETH_BURST_LENGTH_MAX : rxBurstLen;
+
+ txBurstLen = 1 << txBurstLen;
+ txBurstLen = (txBurstLen > ETH_BURST_LENGTH_MAX) ?
+ ETH_BURST_LENGTH_MAX : txBurstLen;
+
+ // Regrading PBLx8 register, if one of PBL and RPBL is more than
+ // ETH_BURST_LENGTH_8X_SWITCH, another should be more than
+ // ETH_BURST_LENGTH_8X_MIN.
+ // If not, the greater level down to ETH_BURST_LENGTH_8X_SWITCH.
+ if ((txBurstLen < ETH_BURST_LENGTH_8X_MIN) ||
+ (rxBurstLen < ETH_BURST_LENGTH_8X_MIN)) {
+ if (rxBurstLen > ETH_BURST_LENGTH_8X_SWITCH) {
+ rxBurstLen = ETH_BURST_LENGTH_8X_SWITCH;
+ }
+
+ if (txBurstLen > ETH_BURST_LENGTH_8X_SWITCH) {
+ txBurstLen = ETH_BURST_LENGTH_8X_SWITCH;
+ }
+ }
+
+ ETH->BUS_MODE_b.USP = (rxBurstLen == txBurstLen) ? FALSE : TRUE;
+ if ((txBurstLen > ETH_BURST_LENGTH_8X_SWITCH) ||
+ (rxBurstLen > ETH_BURST_LENGTH_8X_SWITCH)) {
+ ETH->BUS_MODE_b.PBLx8 = TRUE;
+ } else {
+ ETH->BUS_MODE_b.PBLx8 = FALSE;
+ }
+
+ if (ETH->BUS_MODE_b.PBLx8) {
+ ETH->BUS_MODE_b.RPBL = rxBurstLen >> 3;
+ ETH->BUS_MODE_b.PBL = txBurstLen >> 3;
+ } else {
+ ETH->BUS_MODE_b.RPBL = rxBurstLen;
+ ETH->BUS_MODE_b.PBL = txBurstLen;
+ }
+}
+
+static void mac_SetPriority(BOOL isRxPrior, uint8_t priorityRate) {
+ ETH->BUS_MODE_b.PRWG = 0;
+ ETH->BUS_MODE_b.DA = ETH_DMA_ARBITRATION_ROUND_ROBIN;
+
+ ETH->BUS_MODE_b.TXPR = isRxPrior ? FALSE : TRUE;
+ ETH->BUS_MODE_b.PR = priorityRate;
+}
+
+static void mac_SetDescMode(BOOL isAlternate, uint8_t gap) {
+ ETH->BUS_MODE_b.ATDS = isAlternate;
+ ETH->BUS_MODE_b.DSL = gap;
+}
+
+static void mac_SetOpertionMode(void) {
+ ETH->OPERATION_b.OSF = FALSE;
+ ETH->OPERATION_b.RT = ETH_RX_THRESHOLD_32;
+ ETH->OPERATION_b.RSF = FALSE;
+
+ ETH->OPERATION_b.DGF = FALSE;
+ ETH->OPERATION_b.FUF = FALSE;
+ ETH->OPERATION_b.FEF = FALSE;
+ ETH->OPERATION_b.TT = ETH_TX_THRESHOLD_64;
+ ETH->OPERATION_b.TSF = FALSE;
+
+ ETH->OPERATION_b.FTF = TRUE;
+ ETH->OPERATION_b.DFF = TRUE;
+}
+
+static void mac_SetFrameFilter(ETH_FrameFilter *filter) {
+ ETH->FF_b.PR = FALSE;
+ ETH->FF_b.HUC = FALSE;
+ ETH->FF_b.HMC = FALSE;
+ ETH->FF_b.DAIF = FALSE;
+ ETH->FF_b.PM = FALSE;
+ ETH->FF_b.DBF = FALSE;
+ ETH->FF_b.PCF = ETH_PASS_CTRL_FRAME_ALL;
+ ETH->FF_b.SAIF = FALSE;
+ ETH->FF_b.SAF = FALSE;
+ ETH->FF_b.HPF = FALSE;
+ ETH->FF_b.VTFE = FALSE;
+ ETH->FF_b.IPFE = FALSE;
+ ETH->FF_b.DNTU = FALSE;
+ ETH->FF_b.RA = TRUE;
+
+ // receive all
+ if (!filter) {
+ return ;
+ }
+
+ // broadcast
+ if (filter->ETH_BroadcastFilterEnable) {
+ ETH->FF_b.RA = FALSE;
+ ETH->FF_b.DBF = TRUE;
+ }
+
+ // DA
+ if (filter->ETH_OwnFilterEnable) {
+ ETH->FF_b.RA = FALSE;
+ ETH->FF_b.DAIF = filter->ETH_SelfDrop;
+ }
+
+ // SA
+ if (filter->ETH_SourceFilterEnable) {
+ ETH->FF_b.RA = FALSE;
+ ETH->FF_b.SAF = TRUE;
+ ETH->FF_b.SAIF = filter->ETH_SourceDrop;
+ ETH->ADDR1_HIGH_b.AE = TRUE;
+ ETH->ADDR1_HIGH_b.SA = TRUE;
+ ETH->ADDR1_HIGH_b.ADDR =
+ (filter->ETH_SourceMacAddr[5] << 8) | filter->ETH_SourceMacAddr[4];
+ ETH->ADDR1_LOW = (filter->ETH_SourceMacAddr[3] << 24) |
+ (filter->ETH_SourceMacAddr[2] << 16) |
+ (filter->ETH_SourceMacAddr[1] << 8) |
+ filter->ETH_SourceMacAddr[0];
+ }
+}
+
+static void mac_setFlowControl(void) {
+ ETH->FC_b.FCB = FALSE;
+ ETH->FC_b.TFE = TRUE;
+ ETH->FC_b.RFE = TRUE;
+ ETH->FC_b.UP = TRUE;
+}
+
+uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg) {
+ ETH->GMII_ADDR_b.PA = phyAddr;
+ ETH->GMII_ADDR_b.GR = phyReg;
+ ETH->GMII_ADDR_b.GW = PHY_OP_READ;
+
+ ETH->GMII_ADDR_b.BUSY = TRUE;
+ while (ETH->GMII_ADDR_b.BUSY) ;
+
+ return ETH->GMII_DATA;
+}
+
+void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data) {
+ ETH->GMII_ADDR_b.PA = phyAddr;
+ ETH->GMII_ADDR_b.GR = phyReg;
+ ETH->GMII_ADDR_b.GW = PHY_OP_WRITE;
+ ETH->GMII_DATA = data;
+
+ ETH->GMII_ADDR_b.BUSY = TRUE;
+ while (ETH->GMII_ADDR_b.BUSY) ;
+}
+
+
+BOOL ETH_Init(ETH_InitTypeDef *init) {
+ assert_param(init);
+ assert_param(IS_ETH_SPEED(init->ETH_Speed));
+ assert_param(IS_ETH_DUPLEX(init->ETH_Duplex));
+
+ mac_SwReset();
+ mac_SetConfig(init);
+ mac_SetMacAddr(init->ETH_MacAddr);
+
+ mac_SetBurst(ETH_BURST_MODE_MIXED, 3, 4);
+ mac_SetPriority(TRUE, 0);
+ mac_SetDescMode(TRUE, 0);
+ mac_SetOpertionMode();
+ mac_SetFrameFilter(init->ETH_Filter);
+ mac_setFlowControl();
+
+ return TRUE;
+}
+
+void ETH_EnableInt(uint32_t Int, BOOL enable) {
+ assert_param(IS_ETH_INT(Int));
+
+ if (enable) {
+ if (IS_ETH_INT_NORMAL(Int)) {
+ ETH->INT_EN_b.NIE = TRUE;
+ }
+
+ if (IS_ETH_INT_ABNORMAL(Int)) {
+ ETH->INT_EN_b.AIE = TRUE;
+ }
+
+ ETH->INT_EN |= Int;
+ } else {
+ ETH->INT_EN &= ~Int;
+
+ if (!IS_ETH_INT_NORMAL(ETH->INT_EN)) {
+ ETH->INT_EN_b.NIE = FALSE;
+ }
+
+ if (!IS_ETH_INT_ABNORMAL(ETH->INT_EN)) {
+ ETH->INT_EN_b.AIE = FALSE;
+ }
+ }
+}
+BOOL ETH_GetIntStatus(uint32_t Int) {
+ assert_param(IS_ETH_INT(Int));
+
+ Int &= ETH->INT_EN;
+ if (0 != (ETH->STATUS & Int)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+void ETH_ClearInt(uint32_t Int) {
+ uint32_t sta;
+ assert_param(IS_ETH_INT(Int));
+
+ sta = ETH->STATUS;
+ sta &= ETH->INT_EN;
+ sta &= ~Int;
+
+ // write 1 clear
+ ETH->STATUS = Int;
+
+ if (IS_ETH_INT_NORMAL(Int)) {
+ if (!IS_ETH_INT_NORMAL(sta)) {
+ // write 1 clear
+ ETH->STATUS_b.NIS = 1;
+ }
+ }
+
+ if (IS_ETH_INT_ABNORMAL(Int)) {
+ if (!IS_ETH_INT_ABNORMAL(sta)) {
+ // write 1 clear
+ ETH->STATUS_b.AIS = 1;
+ }
+ }
+}
+
+void ETH_GetMacAddr(uint8_t *mac) {
+ uint32_t tmp;
+
+ if (!mac) {
+ return ;
+ }
+
+ tmp = ETH->ADDR0_LOW;
+ *(mac + 0) = (tmp >> 0) & 0xFF;
+ *(mac + 1) = (tmp >> 8) & 0xFF;
+ *(mac + 2) = (tmp >> 16) & 0xFF;
+ *(mac + 3) = (tmp >> 24) & 0xFF;
+ tmp = ETH->ADDR0_HIGH;
+ *(mac + 4) = (tmp >> 0) & 0xFF;
+ *(mac + 5) = (tmp >> 8) & 0xFF;
+}
+
+BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring) {
+ ETH_TX_DESC *buf = ring;
+
+ if (!ring) {
+ return FALSE;
+ }
+
+ if (ETH->OPERATION_b.ST) {
+ return FALSE;
+ }
+
+ do {
+ INNER_ETH_TX_DESC *desc = (INNER_ETH_TX_DESC *)buf;
+ desc->TX_0.TX0_b.TCH = TRUE;
+ desc->TX_0.TX0_b.IC = TRUE;
+ desc->TX_0.TX0_b.OWN = ETH_DESC_OWN_BY_SELF;
+
+ buf = (ETH_TX_DESC *)buf->nextDescAddr;
+ } while (buf != ring);
+
+ ETH->TDESLA = (uint32_t)ring;
+
+ return TRUE;
+}
+
+void ETH_StartTx() {
+ ETH->OPERATION_b.ST = TRUE;
+}
+
+void ETH_StopTx() {
+ ETH->OPERATION_b.ST = FALSE;
+}
+
+void ETH_ResumeTx() {
+ ETH->TPD = 0;
+}
+
+ETH_TX_DESC *ETH_AcquireFreeTxDesc(void) {
+ uint32_t cur = ETH->CURTDESAPTR;
+ INNER_ETH_TX_DESC *desc = (INNER_ETH_TX_DESC *)cur;
+
+ do {
+ if (desc->TX_0.TX0_b.OWN == ETH_DESC_OWN_BY_SELF) {
+ return (ETH_TX_DESC *)desc;
+ }
+ desc = (INNER_ETH_TX_DESC *)desc->nextDescAddr;
+ } while ((uint32_t)desc != cur);
+
+ return 0;
+}
+
+BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc) {
+ INNER_ETH_TX_DESC *inner;
+
+ if (!desc) {
+ return FALSE;
+ }
+
+ inner = (INNER_ETH_TX_DESC *)desc;
+ return (inner->TX_0.TX0_b.OWN == ETH_DESC_OWN_BY_SELF) ? TRUE : FALSE;
+}
+
+void ETH_ReleaseTxDesc(ETH_TX_DESC *desc) {
+ INNER_ETH_TX_DESC *inner;
+
+ if (!desc) {
+ return;
+ }
+
+ inner = (INNER_ETH_TX_DESC *)desc;
+ inner->TX_0.TX0_b.OWN = ETH_DESC_OWN_BY_HW;
+}
+
+BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring) {
+ ETH_RX_DESC *buf = ring;
+
+ if (!ring) {
+ return FALSE;
+ }
+
+ if (ETH->OPERATION_b.SR) {
+ return FALSE;
+ }
+
+ do {
+ INNER_ETH_RX_DESC *desc = (INNER_ETH_RX_DESC *)buf;
+ desc->RX_1.RX1_b.RCH = TRUE;
+ desc->RX_1.RX1_b.DIC = FALSE;
+ desc->RX_0.RX0_b.OWN = ETH_DESC_OWN_BY_HW;
+
+ buf = (ETH_RX_DESC *)buf->nextDescAddr;
+ } while (buf != ring);
+
+ ETH->RDESLA = (uint32_t)ring;
+
+ return TRUE;
+}
+
+void ETH_StartRx() {
+ ETH->OPERATION_b.SR = TRUE;
+}
+
+void ETH_StopRx() {
+ ETH->OPERATION_b.SR = FALSE;
+}
+
+void ETH_ResumeRx() {
+ ETH->RPD = 0;
+}
+
+ETH_RX_DESC *ETH_AcquireFreeRxDesc(void) {
+ uint32_t cur = ETH->CURRDESAPTR;
+ INNER_ETH_RX_DESC *desc = (INNER_ETH_RX_DESC *)cur;
+
+ do {
+ if (desc->RX_0.RX0_b.OWN == ETH_DESC_OWN_BY_SELF) {
+ return (ETH_RX_DESC *)desc;
+ }
+ desc = (INNER_ETH_RX_DESC *)desc->nextDescAddr;
+ } while ((uint32_t)desc != cur);
+
+ return 0;
+}
+
+BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc) {
+ INNER_ETH_RX_DESC *inner;
+
+ if (!desc) {
+ return FALSE;
+ }
+
+ inner = (INNER_ETH_RX_DESC *)desc;
+ return (inner->RX_0.RX0_b.OWN == ETH_DESC_OWN_BY_SELF) ? TRUE : FALSE;
+}
+
+void ETH_ReleaseRxDesc(ETH_RX_DESC *desc) {
+ INNER_ETH_RX_DESC *inner;
+
+ if (!desc) {
+ return;
+ }
+
+ inner = (INNER_ETH_RX_DESC *)desc;
+ inner->RX_0.RX0_b.OWN = ETH_DESC_OWN_BY_HW;
+}
+
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c
new file mode 100644
index 0000000000..db9adf0763
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c
@@ -0,0 +1,397 @@
+/**
+ *****************************************************************************
+ * @file cmem7_flash.c
+ *
+ * @brief CMEM7 flash controller source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_flash.h"
+
+typedef struct {
+ union {
+ uint16_t STATUS; /*!< status register */
+
+ struct {
+ uint16_t WIP: 1; /*!< in writting */
+ uint16_t WEL: 1; /*!< write enable */
+ uint16_t BP: 5; /*!< protection region */
+ uint16_t SRP: 2; /*!< protection mode */
+ uint16_t QE: 1; /*!< Quad mode */
+ } STATUS_b; /*!< BitSize */
+ } INNER;
+} FLASH_INNER_STATUS;
+
+
+#define NS_IN_A_SECOND (1000000000)
+
+#define FLASH_MAX_SIZE 0x800000
+#define FLASH_PAGE_SIZE 0x100
+#define FLASH_SECTOR_SIZE 0x001000
+#define FLASH_BLOCK_32K_SIZE 0x008000
+#define FLASH_BLOCK_64K_SIZE 0x010000
+
+#define FLASH_CMD_RD_INNER_STATUS_LOW 0x05
+#define FLASH_CMD_RD_INNER_STATUS_HIGH 0x35
+
+#define FLASH_CMD_WR_WRITE_ENABLE 0x06
+#define FLASH_CMD_WR_WRITE_DISABLE 0x04
+
+#define FLASH_CME_WR_STATUS_REG 0x01
+
+#define FLASH_CME_ERASE_SECTOR 0x20
+#define FLASH_CME_ERASE_BLOCK_32K 0x52
+#define FLASH_CME_ERASE_BLOCK_64K 0xD8
+#define FLASH_CME_ERASE_CHIP 0xC7
+
+#define FLASH_CME_WR_ENTER_DEEP_PD 0xB9
+#define FLASH_CME_WR_EXIT_DEEP_PD 0xAB
+
+#define FLASH_CME_RD_NORMAL 0x03
+#define FLASH_CME_RD_FAST 0x0B
+#define FLASH_CME_RD_FAST_DUAL 0x3B
+#define FLASH_CME_RD_FAST_QUAD 0x6B
+
+#define FLASH_CME_WR 0x02
+
+typedef void (*WAIT)(void);
+static WAIT wait;
+
+static void flash_setClock(uint8_t dividor) {
+ dividor = (dividor < 2) ? 2 : dividor;
+ NOR_FLASH->CTRL0_b.DIV = dividor / 2 - 1;
+}
+
+static void flash_cleanOperation() {
+ NOR_FLASH->TRIGGER_b.OP_CLEAN = TRUE;
+ while (NOR_FLASH->STATUS_b.BUSY);
+
+ NOR_FLASH->TRIGGER_b.OP_CLEAN = FALSE;
+ while (NOR_FLASH->STATUS_b.BUSY);
+}
+
+static uint8_t flash_ReadInnerStatusLow() {
+ NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
+ NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_LOW;
+ NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+
+ while (NOR_FLASH->STATUS_b.BUSY);
+
+ return (uint8_t)NOR_FLASH->DATA;
+}
+
+static uint8_t flash_ReadInnerStatusHigh() {
+ NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
+ NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_HIGH;
+ NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+
+ while (NOR_FLASH->STATUS_b.BUSY);
+
+ return (uint8_t)NOR_FLASH->DATA;
+}
+
+static void flash_WaitInWritting() {
+ FLASH_INNER_STATUS s;
+
+ while (NOR_FLASH->STATUS_b.BUSY);
+
+ do {
+ s.INNER.STATUS = flash_ReadInnerStatusLow();
+ if (!s.INNER.STATUS_b.WIP) {
+ break;
+ }
+
+ if (wait) {
+ (*wait)();
+ }
+ } while (1);
+}
+
+static void flash_WriteWriteEnable(BOOL enable) {
+ NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
+ NOR_FLASH->CTRL1_b.CMD =
+ enable ? FLASH_CMD_WR_WRITE_ENABLE : FLASH_CMD_WR_WRITE_DISABLE;
+
+ NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+
+ flash_WaitInWritting();
+}
+
+static void flash_WriteStatusReg(FLASH_INNER_STATUS *s) {
+ uint16_t tmp = s->INNER.STATUS;
+
+ NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 2;
+ NOR_FLASH->CTRL1_b.CMD = FLASH_CME_WR_STATUS_REG;
+ NOR_FLASH->DATA = ((tmp << 8) | (tmp >> 8)) << 16;
+ NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+
+ flash_WaitInWritting();
+}
+
+static void flash_Erase(uint8_t cmd, uint32_t addr) {
+ NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
+ NOR_FLASH->CTRL1_b.CMD = cmd;
+ NOR_FLASH->CTRL1_b.ADDRESS = addr;
+ NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+
+ flash_WaitInWritting();
+}
+
+static void flash_WriteDeepPowerDownEnable(BOOL enable) {
+ NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
+ NOR_FLASH->CTRL1_b.CMD =
+ enable ? FLASH_CME_WR_ENTER_DEEP_PD : FLASH_CME_WR_EXIT_DEEP_PD;
+
+ NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+
+ flash_WaitInWritting();
+}
+
+static void flash_RwReq(uint8_t cmd, uint32_t addr, uint16_t size) {
+ NOR_FLASH->CTRL0_b.RW_BYTE_CNT = size;
+ NOR_FLASH->CTRL1_b.CMD = cmd;
+ NOR_FLASH->CTRL1_b.ADDRESS = addr;
+
+ NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+}
+
+static void flash_WaitReadFifoNotEmpty() {
+ while (NOR_FLASH->STATUS_b.RD_FIFO_EMPTY) {
+ if (wait) {
+ (*wait)();
+ }
+ }
+}
+
+static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
+ uint16_t count = 0;
+
+ while (!NOR_FLASH->STATUS_b.RD_FIFO_EMPTY && size != 0) {
+ uint32_t d = NOR_FLASH->DATA;
+ if (size > 3) {
+ *(data + count++) = d >> 24;
+ *(data + count++) = (d & 0x00FF0000) >> 16;
+ *(data + count++) = (d & 0x0000FF00) >> 8;
+ *(data + count++) = (d & 0x000000FF);
+ size -= 4;
+ } else if (size == 3) {
+ *(data + count++) = (d & 0x00FF0000) >> 16;
+ *(data + count++) = (d & 0x0000FF00) >> 8;
+ *(data + count++) = (d & 0x000000FF);
+ size -= 3;
+ } else if (size == 2) {
+ *(data + count++) = (d & 0x0000FF00) >> 8;
+ *(data + count++) = (d & 0x000000FF);
+ size -= 2;
+ } else if (size == 1) {
+ *(data + count++) = (d & 0x000000FF);
+ size -= 1;
+ }
+ }
+
+ return count;
+}
+
+static uint16_t flash_WriteFifo(uint16_t size, uint8_t* data) {
+ uint16_t count = 0;
+
+ while (!NOR_FLASH->STATUS_b.WR_FIFO_FULL && size != 0) {
+ uint32_t d = 0;
+
+ if (size > 3) {
+ d = *(data + count++) << 24;
+ d |= *(data + count++) << 16;
+ d |= *(data + count++) << 8;
+ d |= *(data + count++);
+ size -= 4;
+ } else if (size == 3) {
+ d = *(data + count++) << 24;
+ d |= *(data + count++) << 16;
+ d |= *(data + count++) << 8;
+ size -= 3;
+ } else if (size == 2) {
+ d = *(data + count++) << 24;
+ d |= *(data + count++) << 16;
+ size -= 2;
+ } else if (size == 1) {
+ d = *(data + count++) << 24;
+ size -= 1;
+ }
+
+ NOR_FLASH->DATA = d;
+ }
+
+ return count;
+}
+
+static uint16_t flash_WritePage(uint32_t addr, uint16_t size, uint8_t* data) {
+ uint16_t actualSize, retSize;
+
+ flash_WriteWriteEnable(TRUE);
+
+ actualSize = FLASH_PAGE_SIZE - (addr & (FLASH_PAGE_SIZE - 1));
+ actualSize = (size > actualSize) ? actualSize : size;
+ retSize = actualSize;
+
+ flash_RwReq(FLASH_CME_WR, addr, actualSize);
+
+ while (actualSize != 0) {
+ uint8_t count = flash_WriteFifo(actualSize, data);
+
+ actualSize -= count;
+ data += count;
+ }
+
+ flash_WaitInWritting();
+
+ return retSize;
+}
+
+void FLASH_Init(FLASH_InitTypeDef* init) {
+ FLASH_INNER_STATUS s;
+
+ assert_param(init);
+ assert_param(IS_FLASH_PROTECT_MODE(init->FLASH_ProtectMode));
+ assert_param(IS_FLASH_PROTECT_REGION(init->FLASH_ProtectRegion));
+
+ wait = init->FLASH_Wait;
+ flash_setClock(init->FLASH_ClockDividor);
+
+ flash_cleanOperation();
+
+ flash_WaitInWritting();
+
+ s.INNER.STATUS = flash_ReadInnerStatusLow();
+ s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
+ s.INNER.STATUS_b.BP = init->FLASH_ProtectRegion;
+ s.INNER.STATUS_b.SRP = init->FLASH_ProtectMode;
+ s.INNER.STATUS_b.QE = init->FLASH_QuadEnable;
+
+ flash_WriteWriteEnable(TRUE);
+ flash_WriteStatusReg(&s);
+}
+
+void FLASH_GetStatus(uint8_t* ProtectMode, uint8_t* ProtectRegion, BOOL* QuadEnable) {
+ FLASH_INNER_STATUS s;
+
+ assert_param(ProtectMode);
+ assert_param(ProtectRegion);
+ assert_param(QuadEnable);
+
+ flash_WaitInWritting();
+
+ s.INNER.STATUS = flash_ReadInnerStatusLow();
+ s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
+ *ProtectRegion = s.INNER.STATUS_b.BP;
+ *ProtectMode = s.INNER.STATUS_b.SRP;
+ *QuadEnable = (s.INNER.STATUS_b.QE == 1) ? TRUE : FALSE;
+}
+
+void FLASH_EraseSector(uint32_t addr) {
+ flash_WaitInWritting();
+ flash_WriteWriteEnable(TRUE);
+
+ addr = (addr << 8) >> 8;
+ addr = addr / FLASH_SECTOR_SIZE * FLASH_SECTOR_SIZE;
+ flash_Erase(FLASH_CME_ERASE_SECTOR, addr);
+}
+
+void FLASH_Erase32kBlock(uint32_t addr) {
+ flash_WaitInWritting();
+ flash_WriteWriteEnable(TRUE);
+
+ addr = (addr << 8) >> 8;
+ addr = addr / FLASH_BLOCK_32K_SIZE * FLASH_BLOCK_32K_SIZE;
+ flash_Erase(FLASH_CME_ERASE_BLOCK_32K, addr);
+}
+
+void FLASH_Erase64kBlock(uint32_t addr) {
+ flash_WaitInWritting();
+ flash_WriteWriteEnable(TRUE);
+
+ addr = (addr << 8) >> 8;
+ addr = addr / FLASH_BLOCK_64K_SIZE * FLASH_BLOCK_64K_SIZE;
+ flash_Erase(FLASH_CME_ERASE_BLOCK_64K, addr);
+}
+
+void FLASH_EraseChip(void) {
+ flash_WaitInWritting();
+ flash_WriteWriteEnable(TRUE);
+ flash_Erase(FLASH_CME_ERASE_CHIP, 0x0);
+}
+
+void FLASH_EnableDeepPowerDown(BOOL enable) {
+ flash_WaitInWritting();
+ flash_WriteWriteEnable(TRUE);
+ flash_WriteDeepPowerDownEnable(enable);
+}
+
+void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data) {
+ uint8_t cmd;
+
+ assert_param(IS_FLASH_READ_MODE(ReadMode));
+ assert_param(addr + size <= FLASH_MAX_SIZE);
+ assert_param(data);
+
+ if (size == 0) {
+ return ;
+ }
+
+ flash_WaitInWritting();
+
+ if (ReadMode == FLASH_READ_MODE_NORMAL) {
+ cmd = FLASH_CME_RD_NORMAL;
+ } else if (ReadMode == FLASH_READ_MODE_FAST) {
+ cmd = FLASH_CME_RD_FAST;
+ } else if (ReadMode == FLASH_READ_MODE_FAST_DUAL) {
+ cmd = FLASH_CME_RD_FAST_DUAL;
+ } else {
+ cmd = FLASH_CME_RD_FAST_QUAD;
+ }
+
+ flash_RwReq(cmd, addr, size);
+
+ while (size > 0) {
+ uint16_t count = 0;
+
+ flash_WaitReadFifoNotEmpty();
+
+ count = flash_ReadFifo(size, data);
+ size -= count;
+ data += count;
+ }
+}
+
+void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data) {
+ assert_param(addr + size <= FLASH_MAX_SIZE);
+ assert_param(data);
+
+ flash_WaitInWritting();
+
+ while (size > 0) {
+ uint16_t count = flash_WritePage(addr, size, data);
+
+ addr += count;
+ size -= count;
+ data += count;
+ }
+}
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c
new file mode 100644
index 0000000000..f49e727862
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c
@@ -0,0 +1,181 @@
+/**
+ *****************************************************************************
+ * @file cmem7_gpio.c
+ *
+ * @brief CMEM7 GPIO source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_gpio.h"
+
+#define GPIO_GROUP_GPIO_H (GPIO_GROUP_GPIO + 1)
+#define GPIO_GROUP_GPIO_N (GPIO_GROUP_GPIO + 2)
+
+#define IS_INNER_GPIO_GROUP(GROUP) (((GROUP) == GPIO_GROUP_GPIO) || \
+ ((GROUP) == GPIO_GROUP_GPIO_H) || \
+ ((GROUP) == GPIO_GROUP_GPIO_N))
+
+#define GPIO_PWM_CHANNEL_GPIO_H_9 (GPIO_PWM_CHANNEL_GPIO_31 + 1)
+#define GPIO_PWM_CHANNEL_GPIO_H_19 (GPIO_PWM_CHANNEL_GPIO_31 + 2)
+#define GPIO_PWM_CHANNEL_GPIO_H_20 (GPIO_PWM_CHANNEL_GPIO_31 + 3)
+
+#define IS_INNER_GPIO_PWM_CHANNEL(CHANNEL) (((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_31) || \
+ ((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_H_9) || \
+ ((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_H_19) || \
+ ((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_H_20))
+static uint32_t gpio_GetClock() {
+ return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.GPIO_CLK + 1));
+}
+
+void GPIO_Init(uint8_t Group, uint32_t PositiveTrigger) {
+ assert_param(IS_GPIO_GROUP(Group));
+
+ if (Group == GPIO_GROUP_GPIO) {
+ GPIO->GPIO_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
+ } else if (Group == GPIO_GROUP_GPIO_H) {
+ GPIO->GPIO_H_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
+ } else {
+ GPIO->GPIO_N_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
+ }
+}
+
+void GPIO_EnableOutput(uint8_t Group, uint32_t Enable) {
+ assert_param(IS_GPIO_GROUP(Group));
+
+ if (Group == GPIO_GROUP_GPIO) {
+ GPIO->GPIO_OE = Enable;
+ } else if (Group == GPIO_GROUP_GPIO_H) {
+ GPIO->GPIO_H_OE = Enable;
+ } else {
+ GPIO->GPIO_N_OE = Enable;
+ }
+}
+
+void GPIO_EnableInt(uint8_t Group, uint32_t Enable) {
+ assert_param(IS_GPIO_GROUP(Group));
+
+ if (Group == GPIO_GROUP_GPIO) {
+ GPIO->GPIO_INT_MASK = ~Enable;
+ } else if (Group == GPIO_GROUP_GPIO_H) {
+ GPIO->GPIO_H_INT_MASK = ~Enable;
+ } else {
+ GPIO->GPIO_N_INT_MASK = ~Enable;
+ }
+}
+
+uint32_t GPIO_GetIntStatus(uint8_t Group) {
+ assert_param(IS_GPIO_GROUP(Group));
+
+ if (Group == GPIO_GROUP_GPIO) {
+ return GPIO->GPIO_INT_STATUS;
+ } else if (Group == GPIO_GROUP_GPIO_H) {
+ return GPIO->GPIO_H_INT_STATUS;
+ }
+
+ return GPIO->GPIO_N_INT_STATUS;
+}
+
+void GPIO_ClearInt(uint8_t Group, uint32_t Clear) {
+ assert_param(IS_GPIO_GROUP(Group));
+
+ if (Group == GPIO_GROUP_GPIO) {
+ GPIO->GPIO_INT_STATUS = Clear;
+ } else if (Group == GPIO_GROUP_GPIO_H) {
+ GPIO->GPIO_H_INT_STATUS = Clear;
+ } else {
+ GPIO->GPIO_N_INT_STATUS = Clear;
+ }
+}
+
+uint32_t GPIO_Read(uint8_t Group) {
+ uint32_t data;
+
+ assert_param(IS_GPIO_GROUP(Group));
+
+ if (Group == GPIO_GROUP_GPIO) {
+ data = GPIO->GPIO_IN;
+ } else if (Group == GPIO_GROUP_GPIO_H) {
+ data = GPIO->GPIO_H_IN;
+ } else {
+ data = GPIO->GPIO_N_IN;
+ }
+
+ return data;
+}
+
+void GPIO_Write(uint8_t Group, uint32_t Unmask, uint32_t data) {
+ assert_param(IS_GPIO_GROUP(Group));
+
+ if (Group == GPIO_GROUP_GPIO) {
+ GPIO->GPIO_OUT_UNMASK = Unmask;
+ GPIO->GPIO_OUT_DATA = data;
+ } else if (Group == GPIO_GROUP_GPIO_H) {
+ GPIO->GPIO_H_OUT_UNMASK = Unmask;
+ GPIO->GPIO_H_OUT_DATA = data;
+ } else {
+ GPIO->GPIO_N_OUT_UNMASK = Unmask;
+ GPIO->GPIO_N_OUT_DATA = data;
+ }
+}
+
+void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLevelNanoSecond) {
+ uint16_t lowTick, highTick;
+
+ assert_param(IS_GPIO_PWM_CHANNEL(Channel));
+
+ lowTick = LowLevelNanoSecond * (gpio_GetClock() / 1000000) / 1000;
+ highTick = HighLevelNanoSecond * (gpio_GetClock() / 1000000) / 1000;
+ lowTick = (lowTick < 1) ? lowTick : lowTick - 1;
+ highTick = (highTick < 1) ? highTick : highTick - 1;
+
+ if (Channel == GPIO_PWM_CHANNEL_GPIO_31) {
+ GPIO->PWM_OUT0_LEN_b.LOW_LEVEL_TICK = lowTick;
+ GPIO->PWM_OUT0_LEN_b.HIGH_LEVEL_TICK = highTick;
+ } else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_9) {
+ GPIO->PWM_OUT1_LEN_b.LOW_LEVEL_TICK = lowTick;
+ GPIO->PWM_OUT1_LEN_b.HIGH_LEVEL_TICK = highTick;
+ } else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_19) {
+ GPIO->PWM_OUT2_LEN_b.LOW_LEVEL_TICK = lowTick;
+ GPIO->PWM_OUT2_LEN_b.HIGH_LEVEL_TICK = highTick;
+ } else {
+ GPIO->PWM_OUT3_LEN_b.LOW_LEVEL_TICK = lowTick;
+ GPIO->PWM_OUT3_LEN_b.HIGH_LEVEL_TICK = highTick;
+ }
+}
+
+void GPIO_EnablePwm(uint8_t Channel, BOOL Enable) {
+ assert_param(IS_GPIO_PWM_CHANNEL(Channel));
+
+ if (Channel == GPIO_PWM_CHANNEL_GPIO_31) {
+ GPIO->PWM_OUT_EN_b.GPIO_31 = Enable;
+ GPIO->PWM_OUT_SEL_b.GPIO_31 = Enable;
+ } else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_9) {
+ GPIO->PWM_OUT_EN_b.GPIO_H_9 = Enable;
+ GPIO->PWM_OUT_SEL_b.GPIO_H_9 = Enable;
+ } else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_19) {
+ GPIO->PWM_OUT_EN_b.GPIO_H_19 = Enable;
+ GPIO->PWM_OUT_SEL_b.GPIO_H_19 = Enable;
+ } else {
+ GPIO->PWM_OUT_EN_b.GPIO_H_20 = Enable;
+ GPIO->PWM_OUT_SEL_b.GPIO_H_20 = Enable;
+ }
+}
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_i2c.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_i2c.c
new file mode 100644
index 0000000000..c87ed58241
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_i2c.c
@@ -0,0 +1,321 @@
+/**
+ *****************************************************************************
+ * @file cmem7_i2c.c
+ *
+ * @brief CMEM7 I2C source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_i2c.h"
+
+#define I2C_INNER_INT_ALL 0x3FF
+
+typedef struct {
+ union {
+ uint32_t DATA_CMD;
+
+ struct {
+ uint32_t DATA : 8;
+ uint32_t RD_CMD : 1;
+ uint32_t WR_CMD : 1;
+ uint32_t WR_RD_CMD : 1;
+ } DATA_CMD_b;
+ } INNER;
+} I2C_INNER_DATA_CMD;
+
+static uint32_t i2c_GetClock(I2C0_Type* I2Cx) {
+ uint32_t dividor;
+
+ if ((uint32_t)I2Cx == (uint32_t)I2C0) {
+ dividor = GLOBAL_CTRL->CLK_SEL_0_b.I2C0_CLK;
+ } else if ((uint32_t)I2Cx == (uint32_t)I2C1) {
+ dividor = GLOBAL_CTRL->CLK_SEL_0_b.I2C1_CLK;
+ }
+
+ return SYSTEM_CLOCK_FREQ / (1 << (dividor + 1));
+}
+
+static uint16_t i2c_NormalizeAddr(I2C0_Type* I2Cx, uint16_t addr) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ if (I2Cx->CTRL_b.MODE == I2C_Mode_Master) {
+ if (I2Cx->CTRL_b.MASTER_ADDR_WIDTH == I2C_ADDR_WIDTH_7BIT) {
+ addr &= 0x007F;
+ } else {
+ addr &= 0x3FF;
+ }
+ }
+
+ if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
+ if (I2Cx->CTRL_b.SLAVE_ADDR_WIDTH == I2C_ADDR_WIDTH_7BIT) {
+ addr &= 0x007F;
+ } else {
+ addr &= 0x3FF;
+ }
+ }
+
+ return addr;
+}
+
+static void i2c_ReadClear(uint32_t bit) {
+ uint32_t tmp;
+ tmp = bit;
+ tmp = tmp;
+}
+
+void I2C_Init(I2C0_Type* I2Cx, I2C_InitTypeDef* I2C_Init) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(I2C_Init);
+ assert_param(IS_I2C_MODE(I2C_Init->I2C_Mode));
+ assert_param(IS_I2C_ADDR_WIDTH(I2C_Init->I2C_AddressWidth));
+
+ // reset
+ I2Cx->ENABLE_b.RESET = FALSE;
+ I2Cx->ENABLE_b.RESET = TRUE;
+
+ // clear interrupt
+ I2Cx->INT_MASK = I2C_INNER_INT_ALL;
+ i2c_ReadClear(I2Cx->CLR_ALL_INT_b.CLEAR);
+
+ I2Cx->CTRL_b.MODE = I2C_Init->I2C_Mode;
+ if (I2Cx->CTRL_b.MODE == I2C_Mode_Master) {
+ I2Cx->CTRL_b.MASTER_ADDR_WIDTH = I2C_Init->I2C_AddressWidth;
+ I2Cx->TAR_b.START_BYTE = TRUE;
+ I2Cx->TAR_b.ADDR10 = i2c_NormalizeAddr(I2Cx, I2C_Init->I2C_Address);
+ }
+ if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
+ I2Cx->CTRL_b.SLAVE_ADDR_WIDTH = I2C_Init->I2C_AddressWidth;
+ I2Cx->SAR_b.ADDR10 = i2c_NormalizeAddr(I2Cx, I2C_Init->I2C_Address);
+ }
+
+ I2Cx->RX_TL_b.THRESHOLD = 0;
+ I2Cx->TX_TL_b.THRESHOLD = 0;
+
+ I2Cx->SLAVE_NACK_b.NACK = FALSE;
+
+ if (I2C_Init->timing) {
+ I2Cx->SCL_CNT_b.HIGH_LEVEL_TICK =
+ i2c_GetClock(I2Cx) / I2C_Init->timing->I2C_Freq / 2;
+ I2Cx->SCL_CNT_b.LOW_LEVEL_TICK =
+ i2c_GetClock(I2Cx) / I2C_Init->timing->I2C_Freq / 2;
+ I2Cx->SDA_SETUP_b.TSU_DAT = ((uint64_t)I2C_Init->timing->I2C_TsuDat) *
+ i2c_GetClock(I2Cx) / 1000000000;
+ I2Cx->SDA_SETUP_b.TSETUP = ((uint64_t)I2C_Init->timing->I2C_Tsetup) *
+ i2c_GetClock(I2Cx) / 1000000000;
+ I2Cx->TSU_STA_SETUP_b.TBUF = ((uint64_t)I2C_Init->timing->I2C_Tbuf) *
+ i2c_GetClock(I2Cx) / 1000000000;
+ I2Cx->TSU_STA_SETUP_b.TSU_STA = ((uint64_t)I2C_Init->timing->I2C_TsuSta) *
+ i2c_GetClock(I2Cx) / 1000000000;
+ I2Cx->TSU_STA_SETUP_b.SDA_FILTER_EN = I2C_Init->timing->I2C_SdaFilterEn;
+ I2Cx->TSU_STA_SETUP_b.SDA_FILTER_CNT = I2C_Init->timing->I2C_SdaFilterSpike;
+ I2Cx->TSU_STA_SETUP_b.SCL_FILTER_EN = I2C_Init->timing->I2C_SclFilterEn;
+ I2Cx->TSU_STA_SETUP_b.SCL_FILTER_CNT = I2C_Init->timing->I2C_SclFilterSpike;
+ }
+}
+
+void I2C_Enable(I2C0_Type* I2Cx, BOOL enable) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ I2Cx->ENABLE_b.EN = enable;
+}
+
+void I2C_EnableInt(I2C0_Type* I2Cx, uint32_t Int, BOOL enable) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_INT(Int));
+
+ if (enable) {
+ I2Cx->INT_MASK &= ~Int;
+ } else {
+ I2Cx->INT_MASK |= Int;
+ }
+}
+
+BOOL I2C_GetIntStatus(I2C0_Type* I2Cx, uint32_t Int) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_INT(Int));
+
+ if (0 != (I2Cx->INT_STATUS & Int)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+void I2C_ClearInt(I2C0_Type* I2Cx, uint32_t Int) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_INT(Int));
+
+ if (Int == I2C_INT_RX_FIFO_NOT_EMPTY) {
+ // It can't be clear by sw but read data
+ }
+
+ if (Int == I2C_INT_RD_REQUEST) {
+ i2c_ReadClear(I2Cx->CLR_RD_REQ_b.CLEAR);
+ }
+
+ if (Int == I2C_INT_TX_ABORT) {
+ i2c_ReadClear(I2Cx->CLR_TX_ABRT_b.CLEAR);
+ }
+
+ if (Int == I2C_INT_RX_DONE) {
+ i2c_ReadClear(I2Cx->CLR_RX_DONE_b.CLEAR);
+ }
+
+ if (Int == I2C_INT_TX_DONE) {
+ i2c_ReadClear(I2Cx->CLR_TX_DONE_b.CLEAR);
+ }
+}
+
+BOOL I2C_GetStatus(I2C0_Type* I2Cx, uint32_t Status) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_STATUS(Status));
+
+ if (0 != (I2Cx->STATUS & Status)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+void I2C_ClearStatus(I2C0_Type* I2Cx, uint32_t Status) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_STATUS(Status));
+
+ if (Status & I2C_STATUS_RX_FIFO_NOT_EMPTY) {
+ // It can't be clear by sw but read
+ }
+
+ if (Status & I2C_STATUS_RD_REQUEST) {
+ i2c_ReadClear(I2Cx->CLR_RD_REQ_b.CLEAR);
+ }
+
+ if (Status & I2C_STATUS_TX_ABORT) {
+ i2c_ReadClear(I2Cx->CLR_TX_ABRT_b.CLEAR);
+ }
+
+ if (Status & I2C_STATUS_RX_DONE) {
+ i2c_ReadClear(I2Cx->CLR_RX_DONE_b.CLEAR);
+ }
+
+ if (Status & I2C_STATUS_TX_DONE) {
+ i2c_ReadClear(I2Cx->CLR_TX_DONE_b.CLEAR);
+ }
+}
+
+BOOL I2C_MasterReadReq(I2C0_Type* I2Cx, uint8_t size) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ if (!I2Cx->ENABLE_b.EN || I2Cx->STATUS_b.BUSY) {
+ return FALSE;
+ }
+
+ if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
+ return FALSE;
+ }
+
+ if (size == 0) {
+ return FALSE;
+ }
+
+ I2Cx->WRITE_READ_CNT_b.RD_BYTE_CNT = size;
+ if (size != 0) {
+ I2C_INNER_DATA_CMD inner;
+
+ inner.INNER.DATA_CMD_b.DATA = 0;
+ inner.INNER.DATA_CMD_b.RD_CMD = TRUE;
+ inner.INNER.DATA_CMD_b.WR_CMD = FALSE;
+ inner.INNER.DATA_CMD_b.WR_RD_CMD = FALSE;
+
+ I2Cx->DATA_CMD = inner.INNER.DATA_CMD;
+ }
+
+ return TRUE;
+}
+
+uint8_t I2C_ReadFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data) {
+ uint8_t count;
+
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(data);
+
+ if (!I2Cx->ENABLE_b.EN) {
+ return 0;
+ }
+
+ count = 0;
+ while (I2Cx->STATUS_b.RX_FIFO_NOT_EMPTY && count < size) {
+ *(data + count++) = I2Cx->DATA_CMD_b.DATA;
+ }
+
+ return count;
+}
+
+BOOL I2C_WriteReq(I2C0_Type* I2Cx, uint8_t size, uint8_t firstData) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ if (!I2Cx->ENABLE_b.EN || I2Cx->STATUS_b.BUSY) {
+ return FALSE;
+ }
+
+ if (size == 0) {
+ return FALSE;
+ }
+
+ I2Cx->WRITE_READ_CNT_b.WR_BYTE_CNT = size;
+ if (size != 0) {
+ I2C_INNER_DATA_CMD inner;
+
+ inner.INNER.DATA_CMD_b.DATA = firstData ;
+ inner.INNER.DATA_CMD_b.RD_CMD = FALSE;
+ inner.INNER.DATA_CMD_b.WR_CMD =
+ (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) ? FALSE : TRUE;
+ inner.INNER.DATA_CMD_b.WR_RD_CMD = FALSE;
+
+ I2Cx->DATA_CMD = inner.INNER.DATA_CMD;
+ }
+
+ return TRUE;
+}
+
+uint8_t I2C_WriteFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data) {
+ uint8_t count;
+
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(data);
+
+ if (!I2Cx->ENABLE_b.EN) {
+ return 0;
+ }
+
+ count = 0;
+ while (I2Cx->STATUS_b.TX_FIFO_NOT_FULL && count < size) {
+ I2Cx->DATA_CMD_b.DATA = *(data + count++);
+ }
+
+ return count;
+}
+
+BOOL I2C_StopReq(I2C0_Type* I2Cx) {
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ udelay(600);
+
+ return TRUE;
+}
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c
new file mode 100644
index 0000000000..fd88e6769c
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c
@@ -0,0 +1,139 @@
+/**
+ *****************************************************************************
+ * @file cmem7_misc.c
+ *
+ * @brief CMEM7 miscellaneous file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_misc.h"
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != FALSE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+
+ if (!NewState)
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ } else {
+ SCB->SCR |= LowPowerMode;
+ }
+}
+
+void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) {
+ int n;
+
+ GLOBAL_CTRL->IBUSOFF = GLOBAL_CTRL->DBUSOFF = (from - to);
+ GLOBAL_CTRL->EXTADDR = to;
+
+ // Delay several cycles
+ for (n = 0; n < 100; n++);
+ GLOBAL_CTRL->ICACHE_b.EN = isIcacheOn;
+ for (n = 0; n < 100; n++);
+}
+
+void GLB_SetNmiIrqNum(uint32_t irq) {
+ GLOBAL_CTRL->NMI_SEL_b.NMI = irq;
+}
+
+void GLB_SelectSysClkSource(uint8_t source) {
+ switch (source) {
+ case SYS_CLK_SEL_DLL :
+ // M7's DLL clock should be fixed at PLL loation 2
+ // In constrast, it's C2R1.
+ // Wait DLL clock stable
+ while (PDLOCK->GCLK_b.C2R1D == 0) ;
+ GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_DLL;
+ break;
+ case SYS_CLK_SEL_CRYSTAL :
+ GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_CRYSTAL;
+ break;
+ case SYS_CLK_SEL_EXTERNAL :
+ // TODO, Add the condition that makes sure input
+ // external clock is stable
+ // For example :
+ // PLL location 0
+ // while (PDLOCK->GCLK_b.C1R1P == 0) ;
+ // DLL location 0
+ // while (PDLOCK->GCLK_b.C1R1D == 0) ;
+ GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_EXTERNAL;
+ break;
+ case SYS_CLK_SEL_OSC :
+ // Fall through
+ default :
+ GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_OSC;
+ break;
+ }
+}
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c
new file mode 100644
index 0000000000..d107e0cb8d
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c
@@ -0,0 +1,63 @@
+/**
+ *****************************************************************************
+ * @file cmem7_rtc.c
+ *
+ * @brief CMEM7 RTC source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_rtc.h"
+
+#define SECONDS_IN_A_DAY (86400)
+
+void RTC_EnableInt(uint32_t Int, BOOL Enable) {
+ assert_param(IS_RTC_INT(Int));
+
+ if (Enable) {
+ GLOBAL_CTRL->RTC_INT_EN |= Int;
+ } else {
+ GLOBAL_CTRL->RTC_INT_EN &= ~Int;
+ }
+}
+
+BOOL RTC_GetIntStatus(uint32_t Int) {
+ assert_param(IS_RTC_INT(Int));
+
+ if (0 != (RTC->INT_STATUS & Int)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+void RTC_ClearInt(uint32_t Int) {
+ assert_param(IS_RTC_INT(Int));
+
+ RTC->INT_STATUS = Int;
+}
+
+uint32_t RTC_GetSecond() {
+ return RTC->SECOND;
+}
+
+uint16_t RTC_GetMicroSecond() {
+ return RTC->MICROSECOND_b.MS;
+}
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_spi.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_spi.c
new file mode 100644
index 0000000000..fe673c75f3
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_spi.c
@@ -0,0 +1,145 @@
+/**
+ *****************************************************************************
+ * @file cmem7_spi.c
+ *
+ * @brief CMEM7 SPI source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_spi.h"
+
+void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init) {
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(init);
+ assert_param(IS_SPI_MODE(init->SPI_Mode));
+ assert_param(init->SPI_BitLength != 0);
+
+ if (init->SPI_Mode == SPI_MODE_CPOL_0_CPHA_0) {
+ SPIx->CTRL_b.CLK_HIGH = FALSE;
+ SPIx->CTRL_b.NEG_EDGE = TRUE;
+ } else if (init->SPI_Mode == SPI_MODE_CPOL_0_CPHA_1) {
+ SPIx->CTRL_b.CLK_HIGH = FALSE;
+ SPIx->CTRL_b.NEG_EDGE = FALSE;
+ } else if (init->SPI_Mode == SPI_MODE_CPOL_1_CPHA_0) {
+ SPIx->CTRL_b.CLK_HIGH = TRUE;
+ SPIx->CTRL_b.NEG_EDGE = FALSE;
+ } else {
+ SPIx->CTRL_b.CLK_HIGH = TRUE;
+ SPIx->CTRL_b.NEG_EDGE = TRUE;
+ }
+
+ SPIx->CTRL_b.RX_EN = init->SPI_RxEn;
+ SPIx->BCNT_b.CNT = init->SPI_BitLength - 1;
+ SPIx->DIV = init->SPI_ClockDividor;
+ SPIx->GAP = (init->SPI_Gap == 0) ? 0 : init->SPI_Gap / 2 + 1;
+}
+
+void SPI_Enable(SPI0_Type* SPIx, BOOL enable) {
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ SPIx->CTRL_b.EN = enable;
+}
+
+void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable) {
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_INT(Int));
+
+ if (enable) {
+ SPIx->INT_MASK &= ~Int;
+ } else {
+ SPIx->INT_MASK |= Int;
+ }
+
+ SPIx->INT_MASK &= SPI_INT_ALL;
+}
+
+BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int) {
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_INT(Int));
+
+ if (0 != (SPIx->INT_STATUS & Int)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int) {
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_INT(Int));
+
+ SPIx->INT_STATUS = Int;
+}
+
+uint8_t SPI_ReadFifo(SPI0_Type* SPIx, uint8_t size, uint32_t* data) {
+ uint8_t count;
+
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(data);
+
+ if (!SPIx->CTRL_b.EN) {
+ return 0;
+ }
+
+ count = 0;
+ while (!SPIx->STATUS_b.RFIFO_EMPTY && count < size) {
+ uint32_t d = SPIx->RW_DATA;
+ d <<= (32 - SPIx->BCNT_b.CNT - 1);
+ d >>= (32 - SPIx->BCNT_b.CNT - 1);
+ *(data + count++) = d;
+ }
+
+ return count;
+}
+
+uint8_t SPI_WriteFifo(SPI0_Type* SPIx, uint8_t Size, uint32_t* data) {
+ uint8_t count;
+
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(data);
+
+ if (!SPIx->CTRL_b.EN) {
+ return 0;
+ }
+
+ count = 0;
+ while (!SPIx->STATUS_b.TFIFO_FULL && count < Size) {
+ uint32_t d = *(data + count++);
+ d <<= (32 - SPIx->BCNT_b.CNT - 1);
+ SPIx->RW_DATA = d;
+ }
+
+ return count;
+}
+
+BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size) {
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(size);
+
+ if (!SPIx->CTRL_b.EN) {
+ return FALSE;
+ }
+
+ SPIx->TRANS_CNT = size - 1;
+ SPIx->TRANS_START_b.TX_TRIGGER = TRUE;
+
+ return TRUE;
+}
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_tim.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_tim.c
new file mode 100644
index 0000000000..a174b9f663
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_tim.c
@@ -0,0 +1,80 @@
+/**
+ *****************************************************************************
+ * @file cmem7_tim.c
+ *
+ * @brief CMEM7 timer source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_tim.h"
+
+static uint32_t tim_GetClock() {
+ return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.TIMER_CLK + 1));
+}
+
+void TIM_Init(TIMER0_Type* Timx, uint16_t Ms) {
+ assert_param(IS_TIM_ALL_PERIPH(Timx));
+
+ Timx->CTRL_b.EN = FALSE;
+ Timx->LEN = tim_GetClock() / 1000 * Ms;
+ Timx->TYPE_b.SIGNLE_SHOT = TRUE;
+}
+
+void TIM_EnableInt(TIMER0_Type* Timx, BOOL Enable) {
+ assert_param(IS_TIM_ALL_PERIPH(Timx));
+
+ if (Enable == TRUE) {
+ Timx->INT_EN_b.EN_REVERSE = FALSE;
+ } else {
+ Timx->INT_EN_b.EN_REVERSE = TRUE;
+ }
+}
+
+BOOL TIM_GetIntStatus(TIMER0_Type* Timx) {
+ assert_param(IS_TIM_ALL_PERIPH(Timx));
+
+ return (Timx->INT_STA_b.STA ? TRUE : FALSE);
+}
+
+void TIM_ClearInt(TIMER0_Type* Timx) {
+ assert_param(IS_TIM_ALL_PERIPH(Timx));
+
+ Timx->INT_STA_b.STA = 1;
+}
+
+void TIM_Enable(TIMER0_Type* Timx, BOOL Enable) {
+ assert_param(IS_TIM_ALL_PERIPH(Timx));
+
+ Timx->CTRL_b.EN = Enable;
+}
+
+BOOL TIM_IsOverflow(TIMER0_Type* Timx) {
+ assert_param(IS_TIM_ALL_PERIPH(Timx));
+
+ return (Timx->CNT == 0) ? TRUE : FALSE;
+}
+
+uint32_t TIM_GetCounter(TIMER0_Type* Timx) {
+ assert_param(IS_TIM_ALL_PERIPH(Timx));
+
+ return Timx->CNT;
+}
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_uart.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_uart.c
new file mode 100644
index 0000000000..ade2ba3e9a
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_uart.c
@@ -0,0 +1,177 @@
+/**
+ *****************************************************************************
+ * @file cmem7_uart.c
+ *
+ * @brief CMEM7 uart file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_uart.h"
+
+#define UART_Mode_8b 1
+#define UART_Mode_8b_Parity 7
+
+#define UART_BaudMode_0 0
+#define UART_BaudMode_1 1
+#define UART_BaudMode_Division 19200
+
+#define UART_WR_MAX_FIFO_SIZE 16
+
+static uint32_t UART_GetClock(UART0_Type* UARTx) {
+ uint32_t dividor;
+
+ if ((uint32_t)UARTx == (uint32_t)UART0) {
+ dividor = GLOBAL_CTRL->CLK_SEL_0_b.UART0_CLK;
+ } else if ((uint32_t)UARTx == (uint32_t)UART1) {
+ dividor = GLOBAL_CTRL->CLK_SEL_0_b.UART1_CLK;
+ } else if ((uint32_t)UARTx == (uint32_t)UART2) {
+ dividor = GLOBAL_CTRL->CLK_SEL_1_b.UART2_CLK;
+ }
+
+ return SYSTEM_CLOCK_FREQ / (1 << (dividor + 1));
+}
+
+static uint16_t UART_CalcBaudrateReload(uint32_t FreqHz, uint32_t Baudrate) {
+ if (Baudrate <= UART_BaudMode_Division) {
+ /** reload in mode 0
+ * reload = FreqHz / 16 * Baudrate
+ * round up
+ * reload = FreqHz / 16 * Baudrate + 1/ 2
+ * reload = (2 * FreqHz + 16 * Baudrate) / 2 * 16 * Baudrate
+ */
+ return ((FreqHz << 1) + (Baudrate << 4)) / (Baudrate << 5);
+ }
+
+ /** reload in mode 1
+ * reload = Baudrate * 16 * 65536 / FreqHz
+ * round up
+ * reload = Baudrate * 16 * 65536 / FreqHz + 1/ 2
+ * reload = (2 * Baudrate * 16 * 65536 + FreqHz) / 2 * FreqHz
+ */
+ return ((((uint64_t)(Baudrate)) << 21) + FreqHz) / (FreqHz << 1);
+}
+
+void UART_Init(UART0_Type* UARTx, UART_InitTypeDef *init) {
+ assert_param(IS_UART_ALL_PERIPH(UARTx));
+ assert_param(init);
+ assert_param(IS_UART_STOPBITS(init->UART_StopBits));
+ assert_param(IS_UART_PARITY(init->UART_Parity));
+
+ /* TODO : assume clock is 50MHz */
+ UARTx->BAUDRATE = UART_CalcBaudrateReload(
+ UART_GetClock(UARTx), init->UART_BaudRate);
+ UARTx->CTRL_b.MODE =
+ (init->UART_Parity == UART_Parity_None) ?
+ UART_Mode_8b : UART_Mode_8b_Parity;
+ UARTx->CTRL_b.STOP = init->UART_StopBits;
+ UARTx->CTRL_b.PARITY =
+ (init->UART_Parity == UART_Parity_None) ?
+ UART_Parity_Even : init->UART_Parity;
+ UARTx->CTRL_b.LOOPBACK = init->UART_LoopBack;
+ UARTx->CTRL_b.RX_EN = init->UART_RxEn;
+ UARTx->CTRL_b.CTS = init->UART_CtsEn;
+ UARTx->CTRL_b.BAUD_MODE =
+ (init->UART_BaudRate > UART_BaudMode_Division) ?
+ UART_BaudMode_1 : UART_BaudMode_0;
+ UARTx->CTRL_b.FIFO_EN = TRUE;
+ UARTx->CTRL_b.RX_THRESHOLD = UART_WR_MAX_FIFO_SIZE;
+ UARTx->CTRL_b.RX_HALF_FULL = (UART_WR_MAX_FIFO_SIZE >> 1);
+ UARTx->TIMEOUT = 0xFF;
+
+ UARTx->INT_MASK |= UART_Int_All;
+ UARTx->INT_SEEN &= UART_Int_All;
+}
+
+void UART_EnableInt(UART0_Type* UARTx, uint32_t Int, BOOL enable) {
+ assert_param(IS_UART_ALL_PERIPH(UARTx));
+ assert_param(IS_UART_INT(Int));
+
+ if (enable) {
+ UARTx->INT_MASK &= ~Int;
+ } else {
+ UARTx->INT_MASK |= Int;
+ }
+
+ UARTx->INT_MASK &= UART_Int_All;
+}
+
+void UART_Enable(UART0_Type* UARTx, BOOL enable) {
+ assert_param(IS_UART_ALL_PERIPH(UARTx));
+
+ UARTx->RUN_b.EN = enable;
+}
+
+BOOL UART_GetIntStatus(UART0_Type* UARTx, uint32_t Int) {
+ assert_param(IS_UART_ALL_PERIPH(UARTx));
+ assert_param(IS_UART_INT(Int));
+
+ if (0 != (UARTx->INT_SEEN & Int)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+void UART_ClearInt(UART0_Type* UARTx, uint32_t Int) {
+ assert_param(IS_UART_ALL_PERIPH(UARTx));
+ assert_param(IS_UART_INT(Int));
+
+ UARTx->INT_SEEN = Int;
+}
+
+uint8_t UART_Write(UART0_Type* UARTx, uint8_t Size, uint8_t* Data) {
+ uint8_t count;
+
+ /* Check the parameters */
+ assert_param(IS_UART_ALL_PERIPH(UARTx));
+ assert_param(Data);
+
+ if (!UARTx->RUN_b.EN) {
+ return 0;
+ }
+
+ count = 0;
+ while (!UARTx->STATUS_b.TF && count < Size) {
+ UARTx->TX_BUF = *(Data + count++);
+ }
+
+ return count;
+}
+
+/* return value is actual read data size */
+uint8_t UART_Read(UART0_Type* UARTx, uint8_t Size, uint8_t* Data) {
+ uint8_t count;
+
+ assert_param(IS_UART_ALL_PERIPH(UARTx));
+ assert_param(Data);
+
+ if (!UARTx->RUN_b.EN) {
+ return 0;
+ }
+
+ count = 0;
+ while (UARTx->STATUS_b.RNE && count < Size) {
+ *(Data + count++) = (UARTx->RX_BUF & 0x00FF);
+ }
+
+ return count;
+}
+
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_usb.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_usb.c
new file mode 100644
index 0000000000..80c79d0b47
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_usb.c
@@ -0,0 +1,842 @@
+/**
+ *****************************************************************************
+ * @file cmem7_usb.c
+ *
+ * @brief CMEM7 USB source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_usb.h"
+
+static void USB_SET_REG_HPRT(const USB_REG_HPRT *clr, const USB_REG_HPRT *set)
+{
+ USB_REG_HPRT hprt;
+ hprt.HPRT = USB->__HPRT; // @0x41300440
+ hprt.HPRT_b.POC = hprt.HPRT_b.PEDC = hprt.HPRT_b.PE = hprt.HPRT_b.PCD = 0;
+ if (clr)
+ hprt.HPRT &= (~clr->HPRT);
+ if (set)
+ hprt.HPRT |= (set->HPRT);
+ USB->__HPRT = hprt.HPRT;
+}
+
+void USB_coreInit(uint32_t type)
+{
+ USB->GINTEN = 0;
+ USB->GINTSTS = ~0;
+ GLOBAL_CTRL->USB_PHY_CTRL_b.CKISEL = 0; // Crystal
+ // core initialization
+ // choose PHY and soft reset
+ USB->GUSBCFG_b.PHY_IF = 0; // 60MHz, 8bit
+ USB->GUSBCFG_b.ULPI_UTMI_SEL = 0; // UTMI
+ USB->GUSBCFG_b.PHY_SEL = 0; // USB 2.0 HS UTMI+
+ USB->GRSTCTL_b.CORE_SOFT_RST = 1;
+ while (USB->GRSTCTL_b.CORE_SOFT_RST == 1) ;
+ while (USB->GRSTCTL_b.AHB_IDLE == 0) ;
+
+ USB->GAHBCFG_b.DMA_EN = 1;
+ USB->GAHBCFG_b.GLBL_INTR_EN = 1;
+ USB->GAHBCFG_b.BST_LEN = 0x1; // INCR
+
+ USB->GINTEN_b.RFNE = FALSE;
+
+ USB->GUSBCFG_b.USB_TRD_TIM = 0x9; // 8-bit UTMI+
+ USB->GUSBCFG_b.SRP_CAP = (type & 0x10) ? 1 : 0;
+ USB->GUSBCFG_b.HNP_CAP = (type & 0x20) ? 1 : 0;
+ if (type & 0x1) {
+ USB->GUSBCFG_b.FORCE_HOST_MODE = 1;
+ USB->GUSBCFG_b.FORCE_DEVICE_MODE = 0;
+ } else if (type & 0x2) {
+ USB->GUSBCFG_b.FORCE_DEVICE_MODE = 1;
+ USB->GUSBCFG_b.FORCE_HOST_MODE = 0;
+ }
+ udelay(50000);
+}
+
+void USB_EnableInt(BOOL enable)
+{
+ USB->GAHBCFG_b.GLBL_INTR_EN = enable;
+}
+
+void USB_FlushFIFO(uint32_t num)
+{
+ if (num < 0x10) {
+ USB->GRSTCTL_b.TX_FIFO_FLUSH_NUM = num;
+ USB->GRSTCTL_b.TX_FIFO_FLUSH = 1;
+ while (USB->GRSTCTL_b.TX_FIFO_FLUSH);
+ } else if (num > 0x10) {
+ USB->GRSTCTL_b.RX_FIFO_FLUSH = 1;
+ while (USB->GRSTCTL_b.RX_FIFO_FLUSH);
+ } else {
+ USB->GRSTCTL_b.TX_FIFO_FLUSH_NUM = 0;
+ USB->GRSTCTL_b.TX_FIFO_ALL = 1;
+ USB->GRSTCTL_b.TX_FIFO_FLUSH = 1;
+ while (USB->GRSTCTL_b.TX_FIFO_FLUSH);
+ }
+}
+
+BOOL USB_ogtIsBdevID()
+{
+ return USB->GOTGCTL_b.CON_ID_STS ? TRUE : FALSE;
+}
+
+BOOL USB_hostVBus(uint32_t opt)
+{
+ if (opt & 0x2) {
+ USB_REG_HPRT hprt;
+ hprt.HPRT = 0;
+ hprt.HPRT_b.PP = 1;
+ if (opt & 0x1)
+ USB_SET_REG_HPRT(NULL, &hprt);
+ else
+ USB_SET_REG_HPRT(&hprt, NULL);
+ }
+ return USB->__HPRT_b.PP ? TRUE : FALSE;
+}
+
+void USB_hostInit()
+{
+ USB_REG_HPRT hprt;
+ // HOST MODE
+ USB->HCFG_b.FS_LS_PCS = 0x0; // PHY clock is running at 30/60 MHz
+ USB->HCFG_b.FS_LS_SUPPORT = 0x0; // HS/FS/LS
+ USB->HCFG_b.EN_SG_DMA = 0x1; // Enable Scatter/Gather DMA
+ hprt.HPRT = 0;
+ hprt.HPRT_b.PP = 1;
+ USB_SET_REG_HPRT(NULL, &hprt);
+}
+
+void USB_HostResetPort(BOOL rst)
+{
+ USB_REG_HPRT hprt;
+ hprt.HPRT = 0;
+ hprt.HPRT_b.PRESET = 1;
+ if (rst)
+ USB_SET_REG_HPRT(NULL, &hprt);
+ else
+ USB_SET_REG_HPRT(&hprt, NULL);
+}
+
+uint16_t USB_HostGetCurFrame()
+{
+ return USB->HFNUM_b.FN;
+}
+
+void USB_HostSuspendPort()
+{
+ USB_REG_HPRT hprt;
+ hprt.HPRT = 0;
+ hprt.HPRT_b.PS = 1;
+ USB_SET_REG_HPRT(NULL, &hprt);
+}
+
+USB_ENUM_SPEED USB_hostGetEnumSpd()
+{
+ return (USB_ENUM_SPEED)USB->__HPRT_b.SPEED;
+}
+
+BOOL USB_hostPrtConn()
+{
+ return USB->__HPRT_b.PCS ? TRUE : FALSE;
+}
+
+void USB_hostCH0(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed)
+{
+ USB->HCDMA0_b.ADDR = SET_HCDMA_DESC_ADDR(desc);
+ USB->HCDMA0_b.CTD = ctd;
+ USB->HCTSIZ0_b.PING = ping ? 1 : 0;
+ USB->HCTSIZ0_b.NTD = ntd;
+ USB->HCTSIZ0_b.PID = pid;
+ USB->HCC0_b.MPS = mps;
+ USB->HCC0_b.EP_NUM = epnum;
+ USB->HCC0_b.EP_DIR = in ? 1 : 0;
+ USB->HCC0_b.LSD = (USB_ENUM_SPEED_LS == speed) ? 1 : 0;
+ USB->HCC0_b.EP_TYPE = eptype;
+ USB->HCC0_b.EC = 0;
+ USB->HCC0_b.DA = devaddr;
+ USB->HCC0_b.CE = 1;
+}
+
+void USB_hostCH1(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed)
+{
+ USB->HCDMA1_b.ADDR = SET_HCDMA_DESC_ADDR(desc);
+ USB->HCDMA1_b.CTD = ctd;
+ USB->HCTSIZ1_b.PING = ping ? 1 : 0;
+ USB->HCTSIZ1_b.NTD = ntd;
+ USB->HCTSIZ1_b.PID = pid;
+ USB->HCC1_b.MPS = mps;
+ USB->HCC1_b.EP_NUM = epnum;
+ USB->HCC1_b.EP_DIR = in ? 1 : 0;
+ USB->HCC1_b.LSD = (USB_ENUM_SPEED_LS == speed) ? 1 : 0;
+ USB->HCC1_b.EP_TYPE = eptype;
+ USB->HCC1_b.EC = 0;
+ USB->HCC1_b.DA = devaddr;
+ USB->HCC1_b.CE = 1;
+}
+
+void USB_hostCH2(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed)
+{
+ USB->HCDMA2_b.ADDR = SET_HCDMA_DESC_ADDR(desc);
+ USB->HCDMA2_b.CTD = ctd;
+ USB->HCTSIZ2_b.PING = ping ? 1 : 0;
+ USB->HCTSIZ2_b.NTD = ntd;
+ USB->HCTSIZ2_b.PID = pid;
+ USB->HCC2_b.MPS = mps;
+ USB->HCC2_b.EP_NUM = epnum;
+ USB->HCC2_b.EP_DIR = in ? 1 : 0;
+ USB->HCC2_b.LSD = (USB_ENUM_SPEED_LS == speed) ? 1 : 0;
+ USB->HCC2_b.EP_TYPE = eptype;
+ USB->HCC2_b.EC = 0;
+ USB->HCC2_b.DA = devaddr;
+ USB->HCC2_b.CE = 1;
+}
+
+int USB_hostCHn(uint32_t ch, uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed)
+{
+ USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
+
+ if (ch > 15)
+ return -1;
+ USBn->HCDMA0_b.ADDR = SET_HCDMA_DESC_ADDR(desc);
+ USBn->HCDMA0_b.CTD = ctd;
+ USBn->HCTSIZ0_b.PING = ping ? 1 : 0;
+ USBn->HCTSIZ0_b.NTD = ntd;
+ USBn->HCTSIZ0_b.PID = pid;
+ USBn->HCC0_b.MPS = mps;
+ USBn->HCC0_b.EP_NUM = epnum;
+ USBn->HCC0_b.EP_DIR = in ? 1 : 0;
+ USBn->HCC0_b.LSD = (USB_ENUM_SPEED_LS == speed) ? 1 : 0;
+ USBn->HCC0_b.EP_TYPE = eptype;
+ USBn->HCC0_b.EC = 0;
+ USBn->HCC0_b.DA = devaddr;
+ USBn->HCC0_b.CE = 1;
+ return 0;
+}
+
+int USB_hostCHnHalt(uint32_t ch)
+{
+ uint32_t hcchar;
+ USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
+
+ if (ch > 15)
+ return -1;
+ hcchar = USBn->HCC0;
+ hcchar |= (0x3 << 30);
+ USBn->HCC0 = hcchar;
+ return 0;
+}
+
+BOOL USB_hostPortDisable(BOOL dis)
+{
+ if (dis) {
+ USB_REG_HPRT hprt;
+ hprt.HPRT = 0;
+ hprt.HPRT_b.PE = 1;
+ USB_SET_REG_HPRT(&hprt, NULL);
+ }
+ return USB->__HPRT_b.PE ? FALSE : TRUE;
+}
+
+BOOL USB_roleIsHost()
+{
+ return USB->GINTSTS_b.CUR_MOD ? TRUE : FALSE;
+}
+
+void USB_hostINT_enConn(BOOL en)
+{
+ USB->GINTEN_b.HP = en;
+}
+
+BOOL USB_hostINT_isConn()
+{
+ return USB->GINTSTS_b.HP ? TRUE : FALSE;
+}
+
+BOOL USB_hostINT_isPCD()
+{
+ return USB->__HPRT_b.PCD ? TRUE : FALSE;
+}
+
+void USB_hostINT_clrPCD()
+{
+ USB_REG_HPRT hprt;
+ hprt.HPRT = 0;
+ hprt.HPRT_b.PCD = 1;
+ USB_SET_REG_HPRT(NULL, &hprt);
+}
+
+BOOL USB_hostINT_isPEDC()
+{
+ return USB->__HPRT_b.PEDC ? TRUE : FALSE;
+}
+
+void USB_hostINT_clrPEDC()
+{
+ USB_REG_HPRT hprt;
+ hprt.HPRT = 0;
+ hprt.HPRT_b.PEDC = 1;
+ USB_SET_REG_HPRT(NULL, &hprt);
+}
+
+int USB_hostINT_enDone(uint32_t ch, BOOL en)
+{
+ USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
+
+ if (ch > 15)
+ return -1;
+
+ if (en) {
+ USB->GINTEN_b.HC = 1;
+ USB->HAINT_EN_b.EN |= BIT(ch);
+ } else
+ USB->HAINT_EN_b.EN &= ~BIT(ch);
+
+ USBn->HCINT_EN0_b.TC = USBn->HCINT_EN0_b.CH_HALT = USBn->HCINT_EN0_b.BNA = en ? 1 : 0;
+ return 0;
+}
+
+uint32_t USB_hostINT_isDone(uint32_t ch)
+{
+ uint32_t retval = 0;
+
+ if (ch > 15)
+ return 0;
+
+ if ((USB->GINTSTS_b.HC) && ((USB->HAINT & BIT(ch)))) {
+ USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
+ if (USBn->HCINT0_b.TC) {
+ USBn->HCINT0 = BIT(0);
+ retval |= 0x1;
+ }
+ if (USBn->HCINT0_b.BNA) {
+ USBn->HCINT0 = BIT(11);
+ retval |= 0x2;
+ }
+ if (USBn->HCINT0_b.CH_HALT) {
+ USBn->HCINT0 = BIT(1);
+ retval |= 0x4;
+ }
+ if (USBn->HCINT0_b.ETE) {
+ USBn->HCINT0 = BIT(12);
+ retval |= 0x8;
+ }
+ }
+ return retval;
+}
+
+uint32_t USB_hostINT_isPend(uint32_t ch)
+{
+ uint32_t retval = 0;
+
+ if (ch > 15)
+ return 0;
+
+ if ((USB->GINTSTS_b.HC) && ((USB->HAINT & BIT(ch)))) {
+ USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
+ retval = USBn->HCINT0;
+ USBn->HCINT0 = retval;
+ }
+ return retval;
+}
+
+void USB_devInit()
+{
+ // If still has some int needed to be enable
+ USB->GINTEN_b.MODE_MIS = TRUE;
+ USB->GINTEN_b.OTG_INT = TRUE;
+
+ // DEVICE MODE
+ USB->GINTEN_b.RFNE = FALSE; // REG_CS(0x018/*GINTMSK*/, BIT(5)/*NPTxFEmpMsk*/ | BIT(4)/*RxFLvlMsk*/, 0);
+ USB->GINTEN_b.NPTFE = FALSE;
+ USB->DCFG_b.DSPEED = 0; // HS DEV
+ USB->DCFG_b.NZLSOH = 0; // REG_CS(0x800/*DCFG*/, BIT(2)/*NZStsOUTHShk*/ | BIT(1) | BIT(0)/*DevSpd: HS*/, BIT(23)/*DescDMA*/ | BIT(13)/*EnDevOutNak*/);
+ USB->DCFG_b.EN_SG_DMA = 1;
+ USB->DCFG_b.EDON = 1;
+ USB->DCTL_b.SD = 0;
+}
+
+USB_ENUM_SPEED USB_devGetEnumSpd()
+{
+ return (USB_ENUM_SPEED)USB->DSTS_b.SPEED;
+}
+
+void USB_devSetAddress(uint32_t addr)
+{
+ USB->DCFG_b.DEVICE_ADDR = addr;
+}
+
+void USB_devEP0out(uint32_t size, uint32_t pktcnt, uint32_t stpcnt, void *desc, BOOL snoop)
+{
+ USB->DOEPTSIZ0_b.SIZE = size;
+ USB->DOEPTSIZ0_b.PACKET_CNT = pktcnt;
+ USB->DOEPTSIZ0_b.SETUP_CNT = stpcnt;
+ USB->DOEPDMA0 = (uint32_t)(desc);
+ USB->DOEPCTL0_b.SNOOP = snoop;
+ USB->DOEPCTL0_b.CNAK = 1;
+ USB->DOEPCTL0_b.EPE = 1; // REG_CS(0xB00/*DOEPCTL0*/, 0, BIT(31)/*EPEna*/);
+}
+
+BOOL USB_devEP0in(uint32_t size, uint32_t pktcnt, void *desc, uint32_t mps/*8,16,32,64-byte*/)
+{
+ switch (mps) {
+ case 64: mps = 0x0; break;
+ case 32: mps = 0x1; break;
+ case 16: mps = 0x2; break;
+ case 8: mps = 0x3; break;
+ default: return FALSE;
+ }
+ USB->DIEPTSIZ0_b.SIZE = size;
+ USB->DIEPTSIZ0_b.PACKET_CNT = pktcnt;
+ USB->DIEPDMA0 = (uint32_t)(desc);
+ USB->DIEPCTL0_b.MPS = mps;
+ USB->DIEPCTL0_b.TX_FIFO_NUM = 0;
+ USB->DIEPCTL0_b.CNAK = 1;
+ USB->DIEPCTL0_b.EPE = 1; // REG_CS(0xB00/*DOEPCTL0*/, 0, BIT(31)/*EPEna*/);
+ return TRUE;
+}
+
+void USB_devActEP1(const BOOL in, const uint32_t mps, USB_EP_TYPE type)
+{
+ if (in) {
+ USB->DIEPCTL1_b.MPS = mps;
+ USB->DIEPCTL1_b.EP_TYPE = type;
+ USB->DIEPCTL1_b.UAE = (mps != 0) ? 1 : 0;
+ } else {
+ USB->DOEPCTL1_b.MPS = mps;
+ USB->DOEPCTL1_b.EP_TYPE = type;
+ USB->DOEPCTL1_b.UAE = (mps != 0) ? 1 : 0;
+ }
+}
+
+void USB_devActEP2(const BOOL in, const uint32_t mps, USB_EP_TYPE type)
+{
+ if (in) {
+ USB->DIEPCTL2_b.MPS = mps;
+ USB->DIEPCTL2_b.EP_TYPE = type;
+ USB->DIEPCTL2_b.UAE = (mps != 0) ? 1 : 0;
+ } else {
+ USB->DOEPCTL2_b.MPS = mps;
+ USB->DOEPCTL2_b.EP_TYPE = type;
+ USB->DOEPCTL2_b.UAE = (mps != 0) ? 1 : 0;
+ }
+}
+
+void USB_devEP1in(uint32_t size, uint32_t pktcnt, uint32_t pid, void *desc)
+{
+ USB->DIEPTSIZ1_b.SIZE = size;
+ USB->DIEPTSIZ1_b.PACKET_CNT = pktcnt;
+ USB->DIEPDMA1 = (uint32_t)(desc);
+ USB->DIEPCTL1_b.CNAK = 1;
+ USB->DIEPCTL1_b.SET_D0_PID = (pid >> 0) & 0x1;
+ USB->DIEPCTL1_b.SET_D1_PID = (pid >> 1) & 0x1;
+ USB->DIEPCTL1_b.EPE = 1;
+}
+
+void USB_devEP1out(uint32_t size, uint32_t pktcnt, uint32_t pid, uint32_t stpcnt, void *desc, BOOL snoop)
+{
+ USB->DOEPTSIZ1_b.SIZE = size;
+ USB->DOEPTSIZ1_b.PACKET_CNT = pktcnt;
+ USB->DOEPTSIZ1_b.SETUPCNT_PID = stpcnt;
+ USB->DOEPDMA1 = (uint32_t)(desc);
+ USB->DOEPCTL1_b.EC = snoop;
+ USB->DOEPCTL1_b.CNAK = 1;
+ USB->DOEPCTL1_b.SET_D0_PID = (pid >> 0) & 0x1;
+ USB->DOEPCTL1_b.SET_D1_PID = (pid >> 1) & 0x1;
+ USB->DOEPCTL1_b.EPE = 1;
+}
+
+
+void USB_devEP2in(uint32_t size, uint32_t pktcnt, uint32_t pid, void *desc)
+{
+ USB->DIEPTSIZ2_b.SIZE = size;
+ USB->DIEPTSIZ2_b.PACKET_CNT = pktcnt;
+ USB->DIEPDMA2 = (uint32_t)(desc);
+ USB->DIEPCTL2_b.CNAK = 1;
+ USB->DIEPCTL2_b.SET_D0_PID = (pid >> 0) & 0x1;
+ USB->DIEPCTL2_b.SET_D1_PID = (pid >> 1) & 0x1;
+ USB->DIEPCTL2_b.EPE = 1;
+}
+
+void USB_devEP2out(uint32_t size, uint32_t pktcnt, uint32_t pid, uint32_t stpcnt, void *desc, BOOL snoop)
+{
+ USB->DOEPTSIZ2_b.SIZE = size;
+ USB->DOEPTSIZ2_b.PACKET_CNT = pktcnt;
+ USB->DOEPTSIZ2_b.SETUPCNT_PID = stpcnt;
+ USB->DOEPDMA2 = (uint32_t)(desc);
+ USB->DOEPCTL2_b.EC = snoop;
+ USB->DOEPCTL2_b.CNAK = 1;
+ USB->DOEPCTL2_b.SET_D0_PID = (pid >> 0) & 0x1;
+ USB->DOEPCTL2_b.SET_D1_PID = (pid >> 1) & 0x1;
+ USB->DOEPCTL2_b.EPE = 1;
+}
+
+void USB_devNAKhandshake(uint32_t ep, BOOL in, BOOL en)
+{
+ switch (ep) {
+ case 0:
+ if (in) {
+ if (en) USB->DIEPCTL0_b.SNAK = 1; else USB->DIEPCTL0_b.CNAK = 1;
+ } else {
+ if (en) USB->DOEPCTL0_b.SNAK = 1; else USB->DOEPCTL0_b.CNAK = 1;
+ }
+ break;
+ case 1:
+ if (in) {
+ if (en) USB->DIEPCTL1_b.SNAK = 1; else USB->DIEPCTL1_b.CNAK = 1;
+ } else {
+ if (en) USB->DOEPCTL1_b.SNAK = 1; else USB->DOEPCTL1_b.CNAK = 1;
+ }
+ break;
+ case 2:
+ if (in) {
+ if (en) USB->DIEPCTL2_b.SNAK = 1; else USB->DIEPCTL2_b.CNAK = 1;
+ } else {
+ if (en) USB->DOEPCTL2_b.SNAK = 1; else USB->DOEPCTL2_b.CNAK = 1;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+BOOL USB_devSTALLhandshake(uint32_t ep, BOOL in, BOOL en)
+{
+ BOOL retval = FALSE;
+ switch (ep) {
+ case 0:
+ if (in) {
+ retval = USB->DIEPCTL0_b.STALL;
+ USB->DIEPCTL0_b.STALL = en ? 1 : 0;
+ } else {
+ retval = USB->DOEPCTL0_b.STALL;
+ USB->DOEPCTL0_b.STALL = en ? 1 : 0;
+ }
+ break;
+ case 1:
+ if (in) {
+ retval = USB->DIEPCTL1_b.STALL;
+ USB->DIEPCTL1_b.STALL = en ? 1 : 0;
+ } else {
+ retval = USB->DOEPCTL1_b.STALL;
+ USB->DOEPCTL1_b.STALL = en ? 1 : 0;
+ }
+ break;
+ case 2:
+ if (in) {
+ retval = USB->DIEPCTL2_b.STALL;
+ USB->DIEPCTL2_b.STALL = en ? 1 : 0;
+ } else {
+ retval = USB->DOEPCTL2_b.STALL;
+ USB->DOEPCTL2_b.STALL = en ? 1 : 0;
+ }
+ break;
+ default:
+ break;
+ }
+ return retval;
+}
+
+void USB_devINT_enDone(uint32_t ep, BOOL in, BOOL en)
+{
+ if (in) {
+ USB->DIEPEN_b.TIMEOUT = en ? 1 : 0;
+ USB->DIEPEN_b.TC = en ? 1 : 0;
+ if (en) {
+ USB->GINTEN_b.IEP_INT = 1;
+ USB->DAINT_EN_b.IN_EN |= BIT(ep);
+ } else
+ USB->DAINT_EN_b.IN_EN &= ~BIT(ep);
+ } else {
+ USB->DOEPEN_b.SPD = en ? 1 : 0;
+ USB->DOEPEN_b.TC = en ? 1 : 0;
+ if (en) {
+ USB->GINTEN_b.OEP_INT = 1;
+ USB->DAINT_EN_b.OUT_EN |= BIT(ep);
+ } else
+ USB->DAINT_EN_b.OUT_EN &= ~BIT(ep);
+ }
+}
+
+uint32_t USB_devINT_isDone(uint32_t ep, BOOL in)
+{
+ int32_t retval = 0;
+ if (in) {
+ if (USB->GINTSTS_b.IEP_INT)
+ switch (ep) {
+ case 0:
+ if (USB->DIEPINT0_b.TC) {
+ retval |= 0x1;
+ USB->DIEPINT0 = BIT(0);
+ }
+ if (USB->DIEPINT0_b.BNA) {
+ retval |= 0x2;
+ USB->DIEPINT0 = BIT(9);
+ }
+ break;
+ case 1:
+ if (USB->DIEPINT1_b.TC) {
+ retval |= 0x1;
+ USB->DIEPINT1 = BIT(0);
+ }
+ if (USB->DIEPINT1_b.BNA) {
+ retval |= 0x2;
+ USB->DIEPINT1 = BIT(9);
+ }
+ break;
+ case 2:
+ if (USB->DIEPINT2_b.TC) {
+ retval |= 0x1;
+ USB->DIEPINT2 = BIT(0);
+ }
+ if (USB->DIEPINT2_b.BNA) {
+ retval |= 0x2;
+ USB->DIEPINT2 = BIT(9);
+ }
+ default:
+ break;
+ }
+ } else {
+ if (USB->GINTSTS_b.OEP_INT)
+ switch (ep) {
+ case 0:
+ if (USB->DOEPINT0_b.TC) {
+ retval |= 0x1;
+ USB->DOEPINT0 = BIT(0);
+ }
+ if (USB->DOEPINT0_b.SETUP) {
+ retval |= 0x4;
+ USB->DOEPINT0 = BIT(3);
+ }
+ break;
+ case 1:
+ if (USB->DOEPINT1_b.TC) {
+ retval |= 0x1;
+ USB->DOEPINT1 = BIT(0);
+ }
+ if (USB->DOEPINT1_b.BNA) {
+ retval |= 0x2;
+ USB->DOEPINT1 = BIT(9);
+ }
+ break;
+ case 2:
+ if (USB->DOEPINT2_b.TC) {
+ retval |= 0x1;
+ USB->DOEPINT2 = BIT(0);
+ }
+ if (USB->DOEPINT2_b.BNA) {
+ retval |= 0x2;
+ USB->DOEPINT2 = BIT(9);
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ return retval;
+}
+
+void USB_INT_enOTG(BOOL en)
+{
+ USB->GINTEN_b.OTG_INT = en;
+}
+
+BOOL USB_INT_isOTG()
+{
+ return USB->GINTSTS_b.OTG_INT ? TRUE : FALSE;
+}
+
+BOOL USB_INT_isOTGon(USB_INT_OTG otg)
+{
+ switch (otg) {
+ case USB_INT_OTG_SESEND:
+ return USB->GOTGINT_b.SES_END_DET ? TRUE : FALSE;
+ break;
+ case USB_INT_OTG_STANDAUP:
+ return USB->GOTGINT_b.A_DEV_TOUT_CHG ? TRUE : FALSE;
+ break;
+ case USB_INT_OTG_HNDETECT:
+ return USB->GOTGINT_b.HST_NEG_DET ? TRUE : FALSE;
+ break;
+ case USB_INT_OTG_HNSUCCHG:
+ return USB->GOTGINT_b.HST_NEG_SUC_STS_CHNG ? TRUE : FALSE;
+ break;
+ case USB_INT_OTG_KEEPAPP:
+ return USB->GOTGINT_b.DBNCE_DONE ? TRUE : FALSE;
+ break;
+ default:
+ break;
+ }
+ return FALSE;
+}
+
+void USB_INT_clrOTGon(USB_INT_OTG otg)
+{
+ switch (otg) {
+ case USB_INT_OTG_SESEND:
+ USB->GOTGINT = BIT(2);
+ break;
+ case USB_INT_OTG_STANDAUP:
+ USB->GOTGINT = BIT(18);
+ break;
+ case USB_INT_OTG_HNDETECT:
+ USB->GOTGINT = BIT(17);
+ break;
+ case USB_INT_OTG_HNSUCCHG:
+ USB->GOTGINT = BIT(9);
+ break;
+ case USB_INT_OTG_KEEPAPP:
+ USB->GOTGINT = BIT(19);
+ break;
+ default:
+ break;
+ }
+}
+
+void USB_INT_enGP(USB_INT_GP name, BOOL en)
+{
+ switch (name) {
+ case USB_INT_GP_HOST_DISC:
+ USB->GINTEN_b.DD = en ? 1 : 0;
+ break;
+ case USB_INT_GP_DEV_RESET:
+ USB->GINTEN_b.USB_RST = en ? 1 : 0;
+ break;
+ case USB_INT_GP_DEV_ENUMDONE:
+ USB->GINTEN_b.ENUM_DONE = en ? 1 : 0;
+ break;
+ case USB_INT_GP_DEV_SUSP:
+ USB->GINTEN_b.USB_SUS = en ? 1 : 0;
+ break;
+ case USB_INT_GP_DEV_EARLY:
+ USB->GINTEN_b.EARLY_SUS = en ? 1 : 0;
+ break;
+ case USB_INT_GP_SOF:
+ USB->GINTEN_b.SOF = en ? 1 : 0;
+ break;
+ case USB_INT_GP_MIS:
+ USB->GINTEN_b.MODE_MIS = en ? 1 : 0;
+ break;
+ case USB_INT_GP_IDCHG:
+ USB->GINTEN_b.CIDSC = en ? 1 : 0;
+ break;
+ case USB_INT_GP_SESSREQ:
+ USB->GINTEN_b.SR = en ? 1 : 0;
+ break;
+ default:
+ break;
+ }
+}
+
+BOOL USB_INT_isGP(USB_INT_GP name)
+{
+ switch (name) {
+ case USB_INT_GP_HOST_DISC:
+ return USB->GINTSTS_b.DD ? TRUE : FALSE;
+ break;
+ case USB_INT_GP_DEV_RESET:
+ return USB->GINTSTS_b.USB_RST ? TRUE : FALSE;
+ break;
+ case USB_INT_GP_DEV_ENUMDONE:
+ return USB->GINTSTS_b.ENUM_DONE ? TRUE : FALSE;
+ break;
+ case USB_INT_GP_DEV_SUSP:
+ return USB->GINTSTS_b.USB_SUS ? TRUE : FALSE;
+ break;
+ case USB_INT_GP_DEV_EARLY:
+ return USB->GINTSTS_b.EARLY_SUS ? TRUE : FALSE;
+ break;
+ case USB_INT_GP_SOF:
+ return USB->GINTSTS_b.SOF ? TRUE : FALSE;
+ break;
+ case USB_INT_GP_MIS:
+ return USB->GINTSTS_b.MODE_MIS ? TRUE : FALSE;
+ break;
+ case USB_INT_GP_IDCHG:
+ return USB->GINTSTS_b.CIDSC ? TRUE : FALSE;
+ break;
+ case USB_INT_GP_SESSREQ:
+ return USB->GINTSTS_b.SR ? TRUE : FALSE;
+ break;
+ default:
+ break;
+ }
+ return FALSE;
+}
+
+void USB_INT_clrGP(USB_INT_GP name)
+{
+ switch (name) {
+ case USB_INT_GP_HOST_DISC:
+ USB->GINTSTS = BIT(29);
+ break;
+ case USB_INT_GP_DEV_RESET:
+ USB->GINTSTS = BIT(12);
+ break;
+ case USB_INT_GP_DEV_ENUMDONE:
+ USB->GINTSTS = BIT(13);
+ break;
+ case USB_INT_GP_DEV_SUSP:
+ USB->GINTSTS = BIT(11);
+ break;
+ case USB_INT_GP_DEV_EARLY:
+ USB->GINTSTS = BIT(10);
+ break;
+ case USB_INT_GP_SOF:
+ USB->GINTSTS = BIT(3);
+ break;
+ case USB_INT_GP_MIS:
+ USB->GINTSTS = BIT(1);
+ break;
+ case USB_INT_GP_IDCHG:
+ USB->GINTSTS = BIT(28);
+ break;
+ case USB_INT_GP_SESSREQ:
+ USB->GINTSTS = BIT(30);
+ break;
+ default:
+ break;
+ }
+}
+
+BOOL USB_otgControl(USB_OTG_CTL ctl, BOOL val)
+{
+ BOOL retval = FALSE;
+ switch (ctl) {
+ case USB_OTG_DEV_HNSUCC:
+ retval = USB->GOTGCTL_b.HST_NEG_SCS ? TRUE : FALSE;
+ break;
+ case USB_OTG_DEV_HNPREQ:
+ retval = USB->GOTGCTL_b.HNP_REQ ? TRUE : FALSE;
+ USB->GOTGCTL_b.HNP_REQ = val ? 1 : 0;
+ break;
+ case USB_OTG_HST_HNPENABLE:
+ retval = USB->GOTGCTL_b.HST_SET_HNP_EN ? TRUE : FALSE;
+ USB->GOTGCTL_b.HST_SET_HNP_EN = val ? 1 : 0;
+ break;
+ case USB_OTG_DEV_HNPENABLE:
+ retval = USB->GOTGCTL_b.DEV_HNP_EN ? TRUE : FALSE;
+ USB->GOTGCTL_b.DEV_HNP_EN = val ? 1 : 0;
+ break;
+ default:
+ break;
+ }
+ return retval;
+}
diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c
new file mode 100644
index 0000000000..6518d81225
--- /dev/null
+++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c
@@ -0,0 +1,58 @@
+/**
+ *****************************************************************************
+ * @file cmem7_wdg.c
+ *
+ * @brief CMEM7 watchdog source file
+ *
+ *
+ * @version V1.0
+ * @date 3. September 2013
+ *
+ * @note
+ *
+ *****************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+ * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2013 Capital-micro
+ *****************************************************************************
+ */
+
+#include "cmem7_wdg.h"
+
+static uint32_t wdg_GetClock() {
+ return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.WDG_CLK + 1));
+}
+
+void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond) {
+ assert_param(IS_WDG_TRIGGER_MODE(trigger));
+
+ WDG->INT_CTRL_b.TRIGGER_MODE = trigger;
+ WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMicroSecond / 1000;
+}
+
+void WDG_EnableInt(uint8_t Int, BOOL Enable) {
+ assert_param(IS_WDG_INT(Int));
+
+ WDG->CTRL_b.INT_LEN = Int;
+ WDG->INT_CTRL_b.MASK = !Enable;
+}
+
+BOOL WDG_GetIntStatus() {
+ return (WDG->INT_STA_b.STA == 1) ? TRUE : FALSE;
+}
+
+void WDG_ClearInt() {
+ WDG->INT_STA_b.STA = 1;
+}
+
+void WDG_Enable(BOOL Enable) {
+ WDG->CTRL_b.EN = Enable;
+}
+
diff --git a/bsp/CME_M7/applications/SConscript b/bsp/CME_M7/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/CME_M7/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/CME_M7/applications/application.c b/bsp/CME_M7/applications/application.c
new file mode 100644
index 0000000000..7774152f43
--- /dev/null
+++ b/bsp/CME_M7/applications/application.c
@@ -0,0 +1,48 @@
+/*
+ * File : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-08-03 aozima first implementation
+ */
+
+#include
+#include
+
+#include
+
+void rt_init_thread_entry(void* parameter)
+{
+ rt_components_init();
+}
+
+int rt_application_init()
+{
+ rt_thread_t tid;
+
+ tid = rt_thread_create("init",
+ rt_init_thread_entry,
+ RT_NULL,
+ 2048,
+ RT_THREAD_PRIORITY_MAX/3,
+ 20);
+
+ if (tid != RT_NULL)
+ rt_thread_startup(tid);
+
+ return 0;
+}
+
+
+void NMI_Handler(void)
+{
+ rt_kprintf("NMI_Handler\n");
+}
+
+/*@}*/
diff --git a/bsp/CME_M7/applications/led.c b/bsp/CME_M7/applications/led.c
new file mode 100644
index 0000000000..68df5c1ede
--- /dev/null
+++ b/bsp/CME_M7/applications/led.c
@@ -0,0 +1,39 @@
+#include
+#include
+
+static void led_thread_entry(void* parameter)
+{
+ /* Configure GPIO as Output mode */
+ GPIO_Init(GPIO_GROUP_GPIO, 0xFFFFFFFF);
+ GPIO_EnableOutput(GPIO_GROUP_GPIO, 0x81010101);
+
+ // LED4, 200ns period
+ GPIO_InitPwm(GPIO_PWM_CHANNEL_GPIO_31, 100, 100);
+ GPIO_EnablePwm(GPIO_PWM_CHANNEL_GPIO_31, TRUE);
+
+ while(1)
+ {
+ GPIO_Write(GPIO_GROUP_GPIO, 0x01010101, 0x55555555);
+ rt_thread_delay(RT_TICK_PER_SECOND/3);
+ GPIO_Write(GPIO_GROUP_GPIO, 0x01010101, 0xAAAAAAAA);
+ rt_thread_delay(RT_TICK_PER_SECOND/3);
+ }
+}
+
+static int led_thread_init(void)
+{
+ rt_thread_t tid;
+
+ tid = rt_thread_create("led",
+ led_thread_entry,
+ RT_NULL,
+ 2048,
+ RT_THREAD_PRIORITY_MAX - 1,
+ 1);
+
+ if (tid != RT_NULL)
+ rt_thread_startup(tid);
+
+ return 0;
+}
+INIT_APP_EXPORT(led_thread_init);
diff --git a/bsp/CME_M7/applications/startup.c b/bsp/CME_M7/applications/startup.c
new file mode 100644
index 0000000000..edff582d1f
--- /dev/null
+++ b/bsp/CME_M7/applications/startup.c
@@ -0,0 +1,91 @@
+/*
+ * File : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2014, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-08-03 aozima first implementation
+ */
+
+#include
+#include
+
+#include "board.h"
+
+/**
+ * @addtogroup CME_M7
+ */
+
+/*@{*/
+
+extern int rt_application_init(void);
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define SRAM_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define SRAM_BEGIN (&__bss_end)
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+ /* init board */
+ rt_hw_board_init();
+
+ /* show version */
+ rt_show_version();
+
+ /* init tick */
+ rt_system_tick_init();
+
+ /* init kernel object */
+ rt_system_object_init();
+
+ /* init timer system */
+ rt_system_timer_init();
+
+ rt_system_heap_init((void*)SRAM_BEGIN, (void*)SRAM_END);
+
+ /* init scheduler system */
+ rt_system_scheduler_init();
+
+ /* init application */
+ rt_application_init();
+
+ /* init timer thread */
+ rt_system_timer_thread_init();
+
+ /* init idle thread */
+ rt_thread_idle_init();
+
+ /* start scheduler */
+ rt_system_scheduler_start();
+
+ /* never reach here */
+ return ;
+}
+
+int main(void)
+{
+ /* disable interrupt first */
+ rt_hw_interrupt_disable();
+
+ /* startup RT-Thread RTOS */
+ rtthread_startup();
+
+ return 0;
+}
+
+/*@}*/
diff --git a/bsp/CME_M7/drivers/SConscript b/bsp/CME_M7/drivers/SConscript
new file mode 100644
index 0000000000..5bbef48785
--- /dev/null
+++ b/bsp/CME_M7/drivers/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'drivers')
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/CME_M7/drivers/board.c b/bsp/CME_M7/drivers/board.c
new file mode 100644
index 0000000000..bbaf1dc41d
--- /dev/null
+++ b/bsp/CME_M7/drivers/board.c
@@ -0,0 +1,60 @@
+/*
+ * File : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2014, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-08-03 aozima first implementation
+ */
+
+#include
+#include
+#include
+
+#include "board.h"
+
+/**
+ * @addtogroup CME_M7
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+static void idle_hook(void)
+{
+ __WFI();
+}
+
+/**
+ * This function will initial board.
+ */
+void rt_hw_board_init()
+{
+ rt_thread_idle_sethook(idle_hook);
+
+ SysTick_Config(SYSTEM_CLOCK_FREQ / RT_TICK_PER_SECOND);
+
+ rt_components_board_init();
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+/*@}*/
diff --git a/bsp/CME_M7/drivers/board.h b/bsp/CME_M7/drivers/board.h
new file mode 100644
index 0000000000..8e7425674c
--- /dev/null
+++ b/bsp/CME_M7/drivers/board.h
@@ -0,0 +1,31 @@
+/*
+ * File : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2014-08-03 aozima first implementation
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "cmem7_includes.h"
+//#include "cmem7_retarget.h"
+
+#define SRAM_SIZE 64 // KB
+#define SRAM_END (0x20000000 + SRAM_SIZE * 1024)
+
+//#define RT_USING_UART0
+//#define RT_USING_UART1
+#define RT_USING_UART2
+
+void rt_hw_board_init(void);
+
+#endif
+
diff --git a/bsp/CME_M7/drivers/uart.c b/bsp/CME_M7/drivers/uart.c
new file mode 100644
index 0000000000..2f611288b5
--- /dev/null
+++ b/bsp/CME_M7/drivers/uart.c
@@ -0,0 +1,171 @@
+#include
+#include
+#include
+
+#include
+
+/* CME-M7 uart driver */
+struct CME_M7_uart
+{
+ UART0_Type* uart_device;
+ IRQn_Type irq;
+};
+
+#ifdef RT_USING_UART0
+struct CME_M7_uart uart0 =
+{
+ UART0,
+ UART0_INT_IRQn,
+};
+static struct rt_serial_device serial0;
+#endif /* RT_USING_UART0 */
+
+#ifdef RT_USING_UART2
+struct CME_M7_uart uart2 =
+{
+ UART2,
+ UART2_INT_IRQn,
+};
+static struct rt_serial_device serial2;
+#endif /* RT_USING_UART2 */
+
+static rt_err_t nuc400_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+ struct CME_M7_uart* uart;
+ UART_InitTypeDef init;
+
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+
+ uart = (struct CME_M7_uart *)serial->parent.user_data;
+
+ init.UART_BaudRate = cfg->baud_rate;
+ init.UART_StopBits = UART_StopBits_1;
+ init.UART_Parity = UART_Parity_None;
+ init.UART_LoopBack = FALSE;
+ init.UART_RxEn = FALSE;
+ init.UART_CtsEn = FALSE;
+
+ UART_Init(uart->uart_device, &init);
+ UART_Enable(uart->uart_device, TRUE);
+
+ return RT_EOK;
+}
+
+static rt_err_t nuc400_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+ struct CME_M7_uart* uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = (struct CME_M7_uart *)serial->parent.user_data;
+
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT:
+ /* disable rx irq */
+// UART_DisableInt(uart->uart_device, UART_INTEN_RDAIEN_Msk);
+// NVIC_DisableIRQ(uart->irq);
+ break;
+
+ case RT_DEVICE_CTRL_SET_INT:
+ /* enable rx irq */
+// UART_EnableInt(uart->uart_device, UART_INTEN_RDAIEN_Msk);
+// NVIC_EnableIRQ(uart->irq);
+ break;
+ }
+
+ return RT_EOK;
+}
+
+static int nuc400_putc(struct rt_serial_device *serial, char ch)
+{
+ struct CME_M7_uart* uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = (struct CME_M7_uart *)serial->parent.user_data;
+
+ while (0 == UART_Write(uart->uart_device, 1, &ch)) ;
+
+// while(UART_GET_TX_FULL(uart->uart_device)); //waits for TXFULL bit is clear
+// uart->uart_device->DAT = ch;
+
+ return 1;
+}
+
+static int nuc400_getc(struct rt_serial_device *serial)
+{
+ int ch;
+ struct CME_M7_uart* uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = (struct CME_M7_uart *)serial->parent.user_data;
+
+ ch = -1;
+
+// if(!UART_GET_RX_EMPTY(uart->uart_device))
+// {
+// ch = uart->uart_device->DAT; /* Get Data from UART RX */
+// }
+
+ return ch;
+}
+
+static const struct rt_uart_ops CME_M7_uart_ops =
+{
+ nuc400_configure,
+ nuc400_control,
+ nuc400_putc,
+ nuc400_getc,
+};
+
+int rt_hw_uart_init(void)
+{
+ struct CME_M7_uart* uart;
+ struct rt_serial_device *serial;
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART0
+ CLK->APBCLK0 |= CLK_APBCLK0_UART0CKEN_Msk; // UART0 Clock Enable
+ uart = &uart0;
+
+ serial0.ops = &CME_M7_uart_ops;
+ serial0.config = config;
+
+ /* register UART device */
+ rt_hw_serial_register(&serial0,
+ "uart0",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+ uart);
+#endif /* RT_USING_UART0 */
+
+#ifdef RT_USING_UART2
+ uart = &uart2;
+ serial = &serial2;
+
+ serial->ops = &CME_M7_uart_ops;
+ serial->config = config;
+
+ /* register UART device */
+ rt_hw_serial_register(serial,
+ "uart2",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+ uart);
+#endif /* RT_USING_UART2 */
+
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#ifdef RT_USING_UART0
+void UART0_IRQHandler(void)
+{
+ rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+}
+#endif /* RT_USING_UART0 */
+
+#ifdef RT_USING_UART2
+void UART2_IRQHandler(void)
+{
+ //rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+}
+#endif /* RT_USING_UART2 */
diff --git a/bsp/CME_M7/readme.md b/bsp/CME_M7/readme.md
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/bsp/CME_M7/rtconfig.h b/bsp/CME_M7/rtconfig.h
new file mode 100644
index 0000000000..eb020158c7
--- /dev/null
+++ b/bsp/CME_M7/rtconfig.h
@@ -0,0 +1,139 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX 8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE 4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX 32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND 100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SERIAL
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart2"
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+//#define RT_USING_NEWLIB
+//#define RT_USING_ARM_LIBC
+
+/* SECTION: device filesystem */
+/* #define RT_USING_DFS */
+#define RT_USING_DFS_ELMFAT
+#define RT_DFS_ELM_REENTRANT
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_DRIVES 1
+#define RT_DFS_ELM_USE_LFN 2
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX 2
+/* the max number of opened files */
+#define DFS_FD_MAX 4
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+//#define RT_USING_LWIP
+/* LwIP uses RT-Thread Memory Management */
+// #define RT_LWIP_USING_RT_MEM
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+/* Enable DNS */
+#define RT_LWIP_DNS
+/* Enable DHCP */
+// #define RT_LWIP_DHCP
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM 3
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY 12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
+#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
+
+#define RT_LWIP_ETHTHREAD_PRIORITY 15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
+
+//
+// #define RT_USING_CMSIS_OS
+//
+#define RT_USING_RTT_CMSIS
+
+#endif
diff --git a/bsp/CME_M7/rtconfig.py b/bsp/CME_M7/rtconfig.py
new file mode 100644
index 0000000000..79deea42b2
--- /dev/null
+++ b/bsp/CME_M7/rtconfig.py
@@ -0,0 +1,124 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m3'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'C:\Program Files\GNU Tools ARM Embedded\4.8 2013q4\bin'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = 'C:/Keil'
+elif CROSS_TOOL == 'iar':
+ PLATFORM = 'iar'
+ IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd())
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE + ' -g -Wall -D__FPU_USED'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+ LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T nuc472_flash.ld'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O3'
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cortex-m4.fp'
+ CFLAGS = DEVICE + ' --c99 --apcs=interwork'
+ AFLAGS = DEVICE
+ LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter nuc472_flash.sct'
+
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+ LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+ EXEC_PATH += '/arm/bin40/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = ' -D USE_STDPERIPH_DRIVER'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --debug'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M3'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=None'
+ CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' -Ol'
+
+ AFLAGS = ''
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M4'
+ AFLAGS += ' --fpu None'
+
+ LFLAGS = ' --config nuc472_flash.icf'
+ LFLAGS += ' --semihosting'
+ LFLAGS += ' --entry __iar_program_start'
+
+ EXEC_PATH = IAR_PATH + '/arm/bin/'
+ POST_ACTION = ''
diff --git a/bsp/CME_M7/template.uvopt b/bsp/CME_M7/template.uvopt
new file mode 100644
index 0000000000..21805b8fa9
--- /dev/null
+++ b/bsp/CME_M7/template.uvopt
@@ -0,0 +1,170 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
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+
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+ -S0 -C0 -P0 -FD20000000 -FC1000)
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diff --git a/bsp/CME_M7/template.uvproj b/bsp/CME_M7/template.uvproj
new file mode 100644
index 0000000000..fa91d03d80
--- /dev/null
+++ b/bsp/CME_M7/template.uvproj
@@ -0,0 +1,416 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rtthread
+ 0x4
+ ARM-ADS
+
+
+ ARMCM3
+ ARM
+ ARM.CMSIS.4.1.0
+ http://www.keil.com/pack/
+ CPUTYPE("Cortex-M3") CLOCK(10000000) ESEL ELITTLE
+
+
+
+ 0
+ $$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h
+
+
+
+
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+
+
+
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+ $$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd
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+