update debug project file and MMU file.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@210 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong
parent
72eb3bb827
commit
9d94c39032
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@ -26,10 +26,10 @@ TARGOPT 1, (RT-Thread Debug)
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OPTAX 255
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OPTBL 0,(User's Manual)<DATASHTS\SAMSUNG\S3C2410_UM.PDF>
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OPTDL (SARM.DLL)()(DARMSS9.DLL)(-pS3C2410A)(SARM.DLL)()(TARMSS9.DLL)(-pS3C2410A)
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OPTDBG 48125,-1,()()()()()()()()()() ()()()()
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OPTDBG 47614,6,()()()()()()()()()(.\Ext_RAM.ini) (Segger\JLTAgdi.dll)()()()
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OPTKEY 0,(DLGDARM)((113=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(109=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0))
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OPTKEY 0,(ARMDBGFLAGS)(-T5F)
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OPTDF 0x40000086
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OPTDF 0x86
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OPTLE <>
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OPTLC <>
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EndOpt
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@ -53,7 +53,7 @@ Options 1,0,0 // Target 'RT-Thread Debug'
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ADSFLGA { 242,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
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ACPUTYP (ARM920T)
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RVDEV ()
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ADSTFLGA { 0,8,64,0,96,0,64,64,0,0,0,0,0,0,0,0,0,0,0,0 }
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ADSTFLGA { 0,8,0,0,96,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0 }
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OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
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OCMADSIRAM { 0,0,0,0,64,0,32,0,0 }
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OCMADSIROM { 0,0,0,0,0,0,0,0,0 }
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@ -89,7 +89,7 @@ Options 1,0,0 // Target 'RT-Thread Debug'
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ADSLDIF ()
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ADSLDDW ()
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OPTDL (SARM.DLL)()(DARMSS9.DLL)(-pS3C2410A)(SARM.DLL)()(TARMSS9.DLL)(-pS3C2410A)
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OPTDBG 48125,-1,()()()()()()()()()() ()()()()
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OPTDBG 47614,6,()()()()()()()()()(.\Ext_RAM.ini) (Segger\JLTAgdi.dll)()()()
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FLASH1 { 1,0,0,0,0,0,0,0,255,255,255,255,0,0,0,0,0,0,0,0 }
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FLASH2 ()
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FLASH3 ("" ())
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@ -5,11 +5,12 @@
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://openlab.rt-thread.com/license/LICENSE
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2008-04-25 Yi.qiu first version
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* 2009-12-18 Bernard port to armcc
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*/
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#include <rtthread.h>
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@ -18,19 +19,19 @@
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// #define _MMUTT_STARTADDRESS 0x30080000
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#define _MMUTT_STARTADDRESS 0x30200000
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#define DESC_SEC (0x2|(1<<4))
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#define CB (3<<2) //cache_on, write_back
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#define CNB (2<<2) //cache_on, write_through
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#define NCB (1<<2) //cache_off,WR_BUF on
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#define NCNB (0<<2) //cache_off,WR_BUF off
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#define AP_RW (3<<10) //supervisor=RW, user=RW
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#define AP_RO (2<<10) //supervisor=RW, user=RO
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#define DESC_SEC (0x2|(1<<4))
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#define CB (3<<2) //cache_on, write_back
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#define CNB (2<<2) //cache_on, write_through
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#define NCB (1<<2) //cache_off,WR_BUF on
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#define NCNB (0<<2) //cache_off,WR_BUF off
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#define AP_RW (3<<10) //supervisor=RW, user=RW
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#define AP_RO (2<<10) //supervisor=RW, user=RO
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#define DOMAIN_FAULT (0x0)
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#define DOMAIN_CHK (0x1)
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#define DOMAIN_CHK (0x1)
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#define DOMAIN_NOTCHK (0x3)
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#define DOMAIN0 (0x0<<5)
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#define DOMAIN1 (0x1<<5)
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#define DOMAIN0 (0x0<<5)
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#define DOMAIN1 (0x1<<5)
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#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
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#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
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@ -46,12 +47,12 @@ void mmu_setttbase(register rt_uint32_t i)
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asm ("mcr p15, 0, %0, c2, c2, 0": :"r" (i));
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}
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void mmu_setdomain(register rt_uint32_t i)
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void mmu_set_domain(register rt_uint32_t i)
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{
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asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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}
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void mmu_enablemmu()
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void mmu_enable()
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{
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register rt_uint32_t i;
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@ -64,7 +65,7 @@ void mmu_enablemmu()
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disablemmu()
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void mmu_disable()
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{
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register rt_uint32_t i;
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@ -77,7 +78,7 @@ void mmu_disablemmu()
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enableicache()
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void mmu_enable_icache()
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{
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register rt_uint32_t i;
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@ -90,7 +91,7 @@ void mmu_enableicache()
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enabledcache()
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void mmu_enable_dcache()
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{
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register rt_uint32_t i;
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@ -103,7 +104,7 @@ void mmu_enabledcache()
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disableicache()
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void mmu_disable_icache()
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{
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register rt_uint32_t i;
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@ -116,7 +117,7 @@ void mmu_disableicache()
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disabledcache()
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void mmu_disable_dcache()
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{
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register rt_uint32_t i;
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@ -129,7 +130,7 @@ void mmu_disabledcache()
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enablealignfault()
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void mmu_enable_alignfault()
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{
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register rt_uint32_t i;
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@ -142,7 +143,7 @@ void mmu_enablealignfault()
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disablealignfault()
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void mmu_disable_alignfault()
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{
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register rt_uint32_t i;
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@ -155,17 +156,17 @@ void mmu_disablealignfault()
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_cleaninvalidatedcacheindex(int index)
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void mmu_clean_invalidated_cache_index(int index)
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{
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asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
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}
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void mmu_invalidatetlb()
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void mmu_invalidate_tlb()
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{
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asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
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}
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void mmu_invalidateicache()
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void mmu_invalidate_icache()
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{
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asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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}
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@ -177,79 +178,79 @@ __asm void mmu_setttbase(rt_uint32_t i)
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mcr p15, 0, r0, c2, c2, 0
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}
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__asm void mmu_setdomain(rt_uint32_t i)
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__asm void mmu_set_domain(rt_uint32_t i)
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{
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mcr p15,0, r0, c3, c0, 0
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}
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__asm void mmu_enablemmu()
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__asm void mmu_enable()
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{
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x01
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mcr p15, 0, r0, c1, c0, 0
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}
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__asm void mmu_disablemmu()
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__asm void mmu_disable()
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{
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x01
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mcr p15, 0, r0, c1, c0, 0
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}
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__asm void mmu_enableicache()
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__asm void mmu_enable_icache()
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{
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x100
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mcr p15, 0, r0, c1, c0, 0
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}
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__asm void mmu_enabledcache()
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__asm void mmu_enable_dcache()
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{
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x02
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mcr p15, 0, r0, c1, c0, 0
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}
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__asm void mmu_disableicache()
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__asm void mmu_disable_icache()
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{
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x100
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mcr p15, 0, r0, c1, c0, 0
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}
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__asm void mmu_disabledcache()
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__asm void mmu_disable_dcache()
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{
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x100
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mcr p15, 0, r0, c1, c0, 0
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}
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__asm void mmu_enablealignfault()
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__asm void mmu_enable_alignfault()
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{
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x01
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mcr p15, 0, r0, c1, c0, 0
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}
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__asm void mmu_disablealignfault()
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__asm void mmu_disable_alignfault()
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{
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x02
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mcr p15, 0, r0, c1, c0, 0
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}
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__asm void mmu_cleaninvalidatedcacheindex(int index)
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__asm void mmu_clean_invalidated_cache_index(int index)
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{
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mcr p15, 0, r0, c7, c14, 2
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}
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__asm void mmu_invalidatetlb()
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__asm void mmu_invalidate_tlb()
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{
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mov r0, #0x0
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mcr p15, 0, r0, c8, c7, 0
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}
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__asm void mmu_invalidateicache()
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__asm void mmu_invalidate_icache()
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{
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0
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@ -278,21 +279,21 @@ void rt_hw_mmu_init(void)
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//initialization code is needed.
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//===================================================================
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mmu_disabledcache();
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mmu_disableicache();
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mmu_disable_dcache();
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mmu_disable_icache();
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//If write-back is used,the DCache should be cleared.
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for(i=0;i<64;i++)
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for(j=0;j<8;j++)
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mmu_cleaninvalidatedcacheindex((i<<26)|(j<<5));
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mmu_clean_invalidated_cache_index((i<<26)|(j<<5));
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mmu_invalidateicache();
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mmu_invalidate_icache();
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//To complete mmu_Init() fast, Icache may be turned on here.
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mmu_enableicache();
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mmu_enable_icache();
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mmu_disablemmu();
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mmu_invalidatetlb();
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mmu_disable();
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mmu_invalidate_tlb();
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//mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
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mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
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@ -320,14 +321,14 @@ void rt_hw_mmu_init(void)
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mmu_setttbase(_MMUTT_STARTADDRESS);
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/* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
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mmu_setdomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
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mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
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//mmu_SetProcessId(0x0);
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mmu_enablealignfault();
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mmu_enable_alignfault();
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mmu_enablemmu();
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mmu_enableicache();
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mmu_enable();
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mmu_enable_icache();
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/* DCache should be turned on after mmu is turned on. */
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mmu_enabledcache();
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mmu_enable_dcache();
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}
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