Bernard Xiong
GitHub
commit
9d60727058
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@ -14,7 +14,7 @@ CONFIG_RT_ALIGN_SIZE=4
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CONFIG_RT_THREAD_PRIORITY_32=y
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# CONFIG_RT_THREAD_PRIORITY_256 is not set
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CONFIG_RT_THREAD_PRIORITY_MAX=32
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CONFIG_RT_TICK_PER_SECOND=100
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CONFIG_RT_TICK_PER_SECOND=1000
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CONFIG_RT_USING_OVERFLOW_CHECK=y
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CONFIG_RT_USING_HOOK=y
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CONFIG_RT_USING_IDLE_HOOK=y
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@ -54,6 +54,7 @@ CONFIG_RT_USING_MEMPOOL=y
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# CONFIG_RT_USING_NOHEAP is not set
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CONFIG_RT_USING_SMALL_MEM=y
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# CONFIG_RT_USING_SLAB is not set
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# CONFIG_RT_USING_USERHEAP is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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CONFIG_RT_USING_HEAP=y
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@ -65,7 +66,7 @@ CONFIG_RT_USING_DEVICE=y
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# CONFIG_RT_USING_INTERRUPT_INFO is not set
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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CONFIG_RT_VER_NUM=0x40003
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# CONFIG_RT_USING_CPU_FFS is not set
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CONFIG_ARCH_ARMV8=y
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@ -141,14 +142,20 @@ CONFIG_RT_USING_DFS_DEVFS=y
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#
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CONFIG_RT_USING_DEVICE_IPC=y
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CONFIG_RT_PIPE_BUFSZ=512
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# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
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CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
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CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
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CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
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CONFIG_RT_USING_SERIAL=y
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CONFIG_RT_SERIAL_USING_DMA=y
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CONFIG_RT_SERIAL_RB_BUFSZ=64
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CONFIG_RT_SERIAL_RB_BUFSZ=512
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# CONFIG_RT_USING_CAN is not set
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# CONFIG_RT_USING_HWTIMER is not set
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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CONFIG_RT_USING_I2C=y
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# CONFIG_RT_I2C_DEBUG is not set
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CONFIG_RT_USING_I2C_BITOPS=y
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# CONFIG_RT_I2C_BITOPS_DEBUG is not set
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# CONFIG_RT_USING_PHY is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_ADC is not set
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# CONFIG_RT_USING_DAC is not set
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@ -173,7 +180,7 @@ CONFIG_RT_USING_SPI=y
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CONFIG_RT_USING_WDT=y
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# CONFIG_RT_USING_AUDIO is not set
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# CONFIG_RT_USING_SENSOR is not set
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# CONFIG_RT_USING_TOUCH is not set
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CONFIG_RT_USING_TOUCH=y
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# CONFIG_RT_USING_HWCRYPTO is not set
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# CONFIG_RT_USING_PULSE_ENCODER is not set
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# CONFIG_RT_USING_INPUT_CAPTURE is not set
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@ -204,7 +211,13 @@ CONFIG_RT_USING_POSIX=y
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#
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# Socket abstraction layer
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#
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# CONFIG_RT_USING_SAL is not set
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CONFIG_RT_USING_SAL=y
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#
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# protocol stack implement
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#
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CONFIG_SAL_USING_LWIP=y
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CONFIG_SAL_USING_POSIX=y
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#
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# Network interface device
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@ -376,6 +389,7 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_AGILE_JSMN is not set
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# CONFIG_PKG_USING_PDULIB is not set
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# CONFIG_PKG_USING_BTSTACK is not set
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# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
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#
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# security packages
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@ -402,6 +416,8 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_WAVPLAYER is not set
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# CONFIG_PKG_USING_TJPGD is not set
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# CONFIG_PKG_USING_HELIX is not set
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# CONFIG_PKG_USING_AZUREGUIX is not set
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# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
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#
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# tools packages
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@ -416,6 +432,7 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_ADBD is not set
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# CONFIG_PKG_USING_COREMARK is not set
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# CONFIG_PKG_USING_DHRYSTONE is not set
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# CONFIG_PKG_USING_MEMORYPERF is not set
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# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
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# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
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# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
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@ -423,6 +440,7 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_GPS_RMC is not set
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# CONFIG_PKG_USING_URLENCODE is not set
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# CONFIG_PKG_USING_UMCN is not set
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# CONFIG_PKG_USING_LWRB2RTT is not set
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#
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# system packages
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@ -449,7 +467,16 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_RAMDISK is not set
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# CONFIG_PKG_USING_MININI is not set
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# CONFIG_PKG_USING_QBOOT is not set
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#
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# Micrium: Micrium software products porting for RT-Thread
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#
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# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
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# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
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# CONFIG_PKG_USING_UC_CRC is not set
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# CONFIG_PKG_USING_UC_CLK is not set
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# CONFIG_PKG_USING_UC_COMMON is not set
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# CONFIG_PKG_USING_UC_MODBUS is not set
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# CONFIG_PKG_USING_PPOOL is not set
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#
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@ -505,6 +532,8 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_WK2124 is not set
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# CONFIG_PKG_USING_LY68L6400 is not set
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# CONFIG_PKG_USING_DM9051 is not set
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# CONFIG_PKG_USING_SSD1306 is not set
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# CONFIG_PKG_USING_QKEY is not set
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#
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# miscellaneous packages
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@ -534,6 +563,7 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
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# CONFIG_PKG_USING_HELLO is not set
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# CONFIG_PKG_USING_VI is not set
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# CONFIG_PKG_USING_KI is not set
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# CONFIG_PKG_USING_NNOM is not set
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# CONFIG_PKG_USING_LIBANN is not set
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# CONFIG_PKG_USING_ELAPACK is not set
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@ -542,8 +572,13 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_ULAPACK is not set
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# CONFIG_PKG_USING_UKAL is not set
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# CONFIG_PKG_USING_CRCLIB is not set
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#
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# games: games run on RT-Thread console
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#
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# CONFIG_PKG_USING_THREES is not set
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# CONFIG_PKG_USING_2048 is not set
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# CONFIG_PKG_USING_TETRIS is not set
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# CONFIG_PKG_USING_LWGPS is not set
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# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
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@ -584,6 +619,9 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_DCM is not set
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# CONFIG_PKG_USING_EMQ is not set
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# CONFIG_PKG_USING_CFGM is not set
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# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
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# CONFIG_PKG_USING_VIRTUAL_DEVICE is not set
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# CONFIG_PKG_USING_SMODULE is not set
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CONFIG_BCM2711_SOC=y
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# CONFIG_BSP_SUPPORT_FPU is not set
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@ -596,10 +634,10 @@ CONFIG_BCM2711_SOC=y
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#
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CONFIG_BSP_USING_UART=y
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CONFIG_RT_USING_UART0=y
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# CONFIG_RT_USING_UART1 is not set
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CONFIG_RT_USING_UART1=y
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CONFIG_RT_USING_UART3=y
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CONFIG_RT_USING_UART4=y
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# CONFIG_RT_USING_UART5 is not set
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# CONFIG_RT_USING_UART4 is not set
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CONFIG_RT_USING_UART5=y
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CONFIG_BSP_USING_GIC=y
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CONFIG_BSP_USING_GIC400=y
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# CONFIG_BSP_USING_GIC500 is not set
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@ -607,10 +645,19 @@ CONFIG_BSP_USING_PIN=y
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CONFIG_BSP_USING_SPI=y
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CONFIG_BSP_USING_SPI0_BUS=y
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CONFIG_BSP_USING_SPI0_DEVICE0=y
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# CONFIG_BSP_USING_SPI0_DEVICE1 is not set
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CONFIG_BSP_USING_SPI0_DEVICE1=y
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CONFIG_BSP_USING_I2C=y
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# CONFIG_BSP_USING_I2C0 is not set
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# CONFIG_BSP_USING_I2C1 is not set
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CONFIG_BSP_USING_I2C3=y
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# CONFIG_BSP_USING_I2C4 is not set
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# CONFIG_BSP_USING_I2C5 is not set
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# CONFIG_BSP_USING_I2C6 is not set
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CONFIG_BSP_USING_CORETIMER=y
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# CONFIG_BSP_USING_SYSTIMER is not set
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CONFIG_BSP_USING_WDT=y
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CONFIG_BSP_USING_ETH=y
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# CONFIG_BSP_USING_BULETOOTH is not set
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# CONFIG_BSP_USING_RTC is not set
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CONFIG_BSP_USING_SDIO=y
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CONFIG_BSP_USING_SDIO0=y
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@ -618,5 +665,11 @@ CONFIG_BSP_USING_SDIO0=y
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#
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# Board Peripheral Drivers
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#
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CONFIG_BSP_USING_HDMI=y
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CONFIG_BSP_USING_HDMI_DISPLAY=y
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CONFIG_BSP_USING_LCD=y
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# CONFIG_BSP_USING_HDMI_DISPLAY is not set
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CONFIG_BSP_USING_DSI_DISPLAY=y
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# CONFIG_BSP_USING_ILI9486 is not set
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CONFIG_BSP_USING_TOUCH=y
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CONFIG_BSP_USING_DSI_TOUCH_DEV=y
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# CONFIG_BSP_USING_XPT_TOUCH_DEV is not set
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# CONFIG_USING_LCD_CONSOLE is not set
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@ -129,6 +129,12 @@ msh />
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| HDMI | 支持 | - |
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| SDIO | 支持 | - |
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| ETH | 支持 | - |
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| BSC | 支持 | - |
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| DMA | 支持 | - |
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| DSI LCD/TOUCH | 支持 | DSI接口的LCD和TOUCH |
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| ILI9486 SPI LCD | 支持 | - |
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| XPT2046 TOUCH | 支持 | - |
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| BULETOOTH | 正在完善 | 支持reset，loadfirmware |
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## 5. 注意事项
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@ -69,6 +69,32 @@ menu "Hardware Drivers Config"
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default n
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endif
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menuconfig BSP_USING_I2C
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bool "Enable I2C"
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select RT_USING_I2C
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default n
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if BSP_USING_I2C
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config BSP_USING_I2C0
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bool "Enable I2C0 BUS"
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default n
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config BSP_USING_I2C1
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bool "Enable I2C1 BUS"
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default n
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config BSP_USING_I2C3
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bool "Enable I2C3 BUS"
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default n
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config BSP_USING_I2C4
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bool "Enable I2C4 BUS"
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default n
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config BSP_USING_I2C5
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bool "Enable I2C5 BUS"
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default n
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config BSP_USING_I2C6
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bool "Enable I2C6 BUS"
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default n
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endif
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config BSP_USING_CORETIMER
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bool "Using core timer"
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select RT_USING_CORETIMER
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@ -93,6 +119,14 @@ menu "Hardware Drivers Config"
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select RT_USING_WDT
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default n
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config BSP_USING_ETH
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bool "Enable ETH"
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default n
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config BSP_USING_BULETOOTH
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bool "Enable BULETOOTH"
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default n
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menuconfig BSP_USING_RTC
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bool "Enable RTC"
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select RT_USING_RTC
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@ -119,14 +153,37 @@ menu "Hardware Drivers Config"
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endmenu
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menu "Board Peripheral Drivers"
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menuconfig BSP_USING_HDMI
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bool "Enable HDMI"
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menuconfig BSP_USING_LCD
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bool "Enable LCD"
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default n
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if BSP_USING_HDMI
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if BSP_USING_LCD
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config BSP_USING_HDMI_DISPLAY
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bool "HDMI DISPLAY"
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default n
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config BSP_USING_DSI_DISPLAY
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bool "DSI DISPLAY"
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default n
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config BSP_USING_ILI9486
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bool "ILI9486 DISPLAY"
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default n
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endif
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menuconfig BSP_USING_TOUCH
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bool "Enable Touch"
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default n
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if BSP_USING_TOUCH
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config BSP_USING_DSI_TOUCH_DEV
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bool "DSI TOUCH"
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default n
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config BSP_USING_XPT_TOUCH_DEV
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bool "XPT TOUCH"
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default n
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endif
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config USING_LCD_CONSOLE
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bool "LCD CONSOLE"
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default n
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endmenu
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endmenu
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@ -1,9 +1,19 @@
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# RT-Thread building script for component
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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src = Glob('*.c') + Glob('*.cpp') + Glob('*.a')
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CPPPATH = [cwd, str(Dir('#'))]
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if not GetDepend('BSP_USING_ETH'):
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SrcRemove(src, ['drv_eth.c'])
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if not GetDepend('BSP_USING_SPI'):
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SrcRemove(src, ['drv_spi.c'])
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if not GetDepend('BSP_USING_WDT'):
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SrcRemove(src, ['drv_wdt.c'])
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if not GetDepend('BSP_USING_BULETOOTH'):
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SrcRemove(src, ['drv_bluetooth.c'])
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group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH)
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# build for sub-directory
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@ -16,13 +16,15 @@
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#include "cp15.h"
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#include "mmu.h"
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#include "mbox.h"
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struct mem_desc platform_mem_desc[] = {
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{0x0, 0x6400000, 0x0, NORMAL_MEM},
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{0x8000000, 0x8800000, 0x8000000, DEVICE_MEM}, //mbox msg
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{0x0EA00000, 0x0EE00000, 0x0EA00000, DEVICE_MEM}, //framebuffer
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{0x0E000000, 0x0EE00000, 0x0E000000, DEVICE_MEM}, //framebuffer
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{0x0F400000, 0x0FA00000, 0x0F400000, DEVICE_MEM}, //dsi_touch
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{0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac
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{0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM}, //peripheral
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{0xFE000000, 0xFF000000, 0xFE000000, DEVICE_MEM}, //peripheral
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{0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic
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};
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@ -36,21 +38,25 @@ void rt_hw_timer_isr(int vector, void *parameter)
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void rt_hw_timer_init(void)
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{
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rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(ARM_TIMER_IRQ);
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rt_uint32_t apb_clock = 0;
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rt_uint32_t timer_clock = 1000000;
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/* timer_clock = apb_clock/(pre_divider + 1) */
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ARM_TIMER_PREDIV = (250 - 1);
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apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID);
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ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1);
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ARM_TIMER_RELOAD = 0;
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ARM_TIMER_LOAD = 0;
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ARM_TIMER_IRQCLR = 0;
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ARM_TIMER_CTRL = 0;
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ARM_TIMER_RELOAD = 10000;
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ARM_TIMER_LOAD = 10000;
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ARM_TIMER_RELOAD = 1000000/RT_TICK_PER_SECOND;
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ARM_TIMER_LOAD = 1000000/RT_TICK_PER_SECOND;
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/* 23-bit counter, enable interrupt, enable timer */
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ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
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rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(ARM_TIMER_IRQ);
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}
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void idle_wfi(void)
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@ -0,0 +1,885 @@
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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||||
* Date Author Notes
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* 2020-11-29 bigmagic first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "drv_bluetooth.h"
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#include "drv_uart.h"
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#include "raspi4.h"
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|
||||
//https://github.com/RPi-Distro/bluez-firmware/tree/master/broadcom
|
||||
//arm-none-eabi-objcopy.exe -I binary -O elf32-littlearm -B arm driver\BCM4345C0.hcd driver\BCM4345C0.a
|
||||
|
||||
#define BT_UART_NAME "uart0"
|
||||
#define BT_TX_MAX (256)
|
||||
#define BT_RX_MAX (256)
|
||||
#define BT_HEAD_NUM (4)
|
||||
#define BT_TRY_NUM_MAX (3)
|
||||
#define BT_SEND_MIN_PACK (8)
|
||||
|
||||
unsigned char lo(unsigned int val) { return (unsigned char)(val & 0xff); }
|
||||
unsigned char hi(unsigned int val) { return (unsigned char)((val & 0xff00) >> 8); }
|
||||
|
||||
#define BT_THREAD_STACK_SIZE (2048)
|
||||
#define BT_THREAD_PRIORITY (15)
|
||||
#define BT_THREAD_TICK (10)
|
||||
|
||||
enum
|
||||
{
|
||||
LE_EVENT_CODE = 0x3e,
|
||||
LE_CONNECT_CODE = 0x01,
|
||||
LE_ADREPORT_CODE = 0x02,
|
||||
HCI_ACL_PKT = 0x02,
|
||||
HCI_EVENT_PKT = 0x04
|
||||
};
|
||||
|
||||
static char ch;
|
||||
static rt_sem_t bt_rx_sem = RT_NULL;
|
||||
static rt_device_t bt_device;
|
||||
|
||||
static rt_uint8_t tx_buff[BT_TX_MAX];
|
||||
static rt_uint8_t rx_buff[BT_RX_MAX];
|
||||
|
||||
static rt_err_t bt_rx_ind(rt_device_t dev, rt_size_t size)
|
||||
{
|
||||
rt_sem_release(bt_rx_sem);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
int bt_uart_send_data(rt_device_t dev, rt_uint32_t *buf, int len)
|
||||
{
|
||||
return rt_device_write(dev, 0, buf, len);
|
||||
}
|
||||
|
||||
|
||||
void bt_uart_receive_flush(rt_device_t dev)
|
||||
{
|
||||
rt_device_read(dev, RT_NULL, rx_buff, BT_RX_MAX);
|
||||
}
|
||||
|
||||
int bt_uart_receive_data(rt_device_t dev, rt_uint8_t *buf, rt_uint32_t *len, rt_int32_t time)
|
||||
{
|
||||
rt_uint16_t ii = 0;
|
||||
|
||||
ii = rt_device_read(dev, 0, buf, BT_RX_MAX);
|
||||
*len = ii;
|
||||
return ii;
|
||||
}
|
||||
|
||||
void bt_data_pack(rt_uint8_t *tx_buff, rt_uint8_t ogf, rt_uint8_t ocf, rt_uint32_t data_len)
|
||||
{
|
||||
tx_buff[0] = BT_HCI_COMMAND_PKT;
|
||||
tx_buff[1] = ogf; //hi(ogf << 10 | ocf);//opcode hi
|
||||
tx_buff[2] = ocf; //lo(ogf << 10 | ocf);//opcode lo
|
||||
tx_buff[3] = data_len;
|
||||
}
|
||||
|
||||
rt_uint32_t bt_reply_check(const rt_uint8_t *buff, rt_uint16_t ogf, rt_uint16_t ocf, int pack_len)
|
||||
{
|
||||
//step 1
|
||||
if (buff[0] != BT_HCI_EVENT_PKT)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
//step2
|
||||
if (buff[1] == BT_CONNECT_COMPLETE_CODE)
|
||||
{
|
||||
if (buff[2] != 4)
|
||||
{
|
||||
return 2;
|
||||
}
|
||||
|
||||
//err code
|
||||
if (buff[3] != 0)
|
||||
{
|
||||
rt_kprintf("Saw HCI COMMAND STATUS error:%d", buff[3]);
|
||||
return 12;
|
||||
}
|
||||
|
||||
if (buff[4] == 0)
|
||||
{
|
||||
return 3;
|
||||
}
|
||||
|
||||
if (buff[5] != ogf)
|
||||
{
|
||||
return 4;
|
||||
}
|
||||
|
||||
if (buff[6] != ocf)
|
||||
{
|
||||
return 5;
|
||||
}
|
||||
}
|
||||
else if (buff[1] == BT_COMMAND_COMPLETE_CODE)
|
||||
{
|
||||
if (buff[2] != 4)
|
||||
{
|
||||
return 6;
|
||||
}
|
||||
|
||||
if (buff[3] == 0)
|
||||
{
|
||||
return 7;
|
||||
}
|
||||
|
||||
if (buff[4] != ogf)
|
||||
{
|
||||
return 8;
|
||||
}
|
||||
|
||||
if (buff[5] != ocf)
|
||||
{
|
||||
return 9;
|
||||
}
|
||||
|
||||
if (buff[6] == 0)
|
||||
{
|
||||
return 10;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return 11;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_err_t bt_loadfirmware(void)
|
||||
{
|
||||
|
||||
int ii = 0;
|
||||
int ret = 0;
|
||||
int recv_len = BT_RX_MAX;
|
||||
int step = 0;
|
||||
rt_uint8_t ogf, ocf;
|
||||
|
||||
rt_memset(tx_buff, 0, BT_TX_MAX);
|
||||
|
||||
ogf = hi(BT_OGF_VENDOR << 10 | BT_COMMAND_LOAD_FIRMWARE);
|
||||
ocf = lo(BT_OGF_VENDOR << 10 | BT_COMMAND_LOAD_FIRMWARE);
|
||||
|
||||
bt_data_pack(tx_buff, ogf, ocf, 0);
|
||||
int kk = 0;
|
||||
for (ii = 0; ii < BT_TRY_NUM_MAX; ii++)
|
||||
{
|
||||
recv_len = BT_RX_MAX;
|
||||
bt_uart_receive_flush(bt_device);
|
||||
bt_uart_send_data(bt_device, tx_buff, BT_SEND_MIN_PACK);
|
||||
rt_thread_mdelay(5);
|
||||
|
||||
ret = bt_uart_receive_data(bt_device, rx_buff, &recv_len, 2000);
|
||||
|
||||
if (ret > 0)
|
||||
{
|
||||
ret = bt_reply_check(rx_buff, ogf, ocf, RT_NULL);
|
||||
if (ret == 0)
|
||||
{
|
||||
step = 1;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("err code is %d\n", ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (step == 1)
|
||||
{
|
||||
extern unsigned char _binary_driver_BCM4345C0_hcd_size[];
|
||||
extern unsigned char _binary_driver_BCM4345C0_hcd_start[];
|
||||
unsigned int c = 0;
|
||||
unsigned int size = (long)&_binary_driver_BCM4345C0_hcd_size;
|
||||
while (c < size)
|
||||
{
|
||||
//unsigned char opcodebytes[] = {_binary_BCM4345C0_hcd_start[c], _binary_BCM4345C0_hcd_start[c + 1]};
|
||||
unsigned char length = _binary_driver_BCM4345C0_hcd_start[c + 2];
|
||||
unsigned char *data = &(_binary_driver_BCM4345C0_hcd_start[c + 3]);
|
||||
rt_memset(tx_buff, 0, BT_TX_MAX);
|
||||
|
||||
ogf = _binary_driver_BCM4345C0_hcd_start[c + 1];
|
||||
ocf = _binary_driver_BCM4345C0_hcd_start[c];
|
||||
bt_data_pack(tx_buff, ogf, ocf, length);
|
||||
|
||||
rt_memcpy(&tx_buff[BT_HEAD_NUM], data, length);
|
||||
int kk = 0;
|
||||
for (ii = 0; ii < BT_TRY_NUM_MAX; ii++)
|
||||
{
|
||||
recv_len = BT_RX_MAX;
|
||||
rt_memset(rx_buff, 0, BT_TX_MAX);
|
||||
bt_uart_receive_flush(bt_device);
|
||||
bt_uart_send_data(bt_device, tx_buff, length + BT_HEAD_NUM);
|
||||
bt_uart_receive_flush(bt_device);
|
||||
rt_thread_mdelay(5);
|
||||
ret = bt_uart_receive_data(bt_device, rx_buff, &recv_len, 1000);
|
||||
|
||||
if (ret > 0)
|
||||
{
|
||||
ret = bt_reply_check(rx_buff, ogf, ocf, RT_NULL);
|
||||
if (ret == 0)
|
||||
{
|
||||
step = 2;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("err code is %d\n", ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (ii >= 3)
|
||||
{
|
||||
step = 3;
|
||||
break;
|
||||
}
|
||||
c += 3 + length;
|
||||
}
|
||||
|
||||
if (step != 3)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
rt_err_t bt_setbaud(void)
|
||||
{
|
||||
static unsigned char params[] = {0, 0, 0x00, 0xc2, 0x01, 0x00}; // little endian, 115200
|
||||
int params_len = 6;
|
||||
int ii = 0;
|
||||
int ret = 0;
|
||||
|
||||
int recv_len = BT_RX_MAX;
|
||||
rt_uint16_t ogf, ocf;
|
||||
|
||||
rt_memset(tx_buff, 0, BT_TX_MAX);
|
||||
|
||||
ogf = hi(BT_OGF_VENDOR << 10 | BT_COMMAND_SET_BAUD);
|
||||
ocf = lo(BT_OGF_VENDOR << 10 | BT_COMMAND_SET_BAUD);
|
||||
|
||||
bt_data_pack(tx_buff, ogf, ocf, params_len);
|
||||
|
||||
//rt_memcpy(&tx_buff[BT_HEAD_NUM], params, params_len);
|
||||
tx_buff[4] = 0x00;
|
||||
tx_buff[5] = 0x01;
|
||||
tx_buff[6] = 0xc2;
|
||||
tx_buff[7] = 0x00;
|
||||
tx_buff[8] = 0x00;
|
||||
tx_buff[9] = 0x00;
|
||||
|
||||
for (ii = 0; ii < BT_TRY_NUM_MAX; ii++)
|
||||
{
|
||||
recv_len = BT_RX_MAX;
|
||||
bt_uart_receive_flush(bt_device);
|
||||
bt_uart_send_data(bt_device, tx_buff, params_len + BT_HEAD_NUM);
|
||||
rt_thread_mdelay(5);
|
||||
ret = bt_uart_receive_data(bt_device, rx_buff, &recv_len, 1000);
|
||||
if (ret > 0)
|
||||
{
|
||||
ret = bt_reply_check(rx_buff, ogf, ocf, RT_NULL);
|
||||
if (ret == 0)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("err code is %d\n", ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
rt_err_t setLEeventmask(unsigned char mask)
|
||||
{
|
||||
unsigned char params[] = {mask, 0, 0, 0, 0, 0, 0, 0};
|
||||
|
||||
//static unsigned char params[] = { 0xee, 0xff, 0xc0, 0xee, 0xff, 0xc0 }; // reversed
|
||||
int params_len = 8;
|
||||
int ii = 0;
|
||||
int ret = 0;
|
||||
|
||||
int recv_len = BT_RX_MAX;
|
||||
rt_uint16_t ogf, ocf;
|
||||
|
||||
rt_memset(tx_buff, 0, BT_TX_MAX);
|
||||
|
||||
ogf = hi(BT_OGF_LE_CONTROL << 10 | 0x01);
|
||||
ocf = lo(BT_OGF_LE_CONTROL << 10 | 0x01);
|
||||
|
||||
bt_data_pack(tx_buff, ogf, ocf, params_len);
|
||||
|
||||
//rt_memcpy(&tx_buff[BT_HEAD_NUM], params, params_len);
|
||||
tx_buff[4] = params[0];
|
||||
tx_buff[5] = params[1];
|
||||
tx_buff[6] = params[2];
|
||||
tx_buff[7] = params[3];
|
||||
tx_buff[8] = params[4];
|
||||
tx_buff[9] = params[5];
|
||||
tx_buff[10] = params[6];
|
||||
tx_buff[11] = params[7];
|
||||
|
||||
|
||||
for (ii = 0; ii < BT_TRY_NUM_MAX; ii++)
|
||||
{
|
||||
recv_len = BT_RX_MAX;
|
||||
bt_uart_receive_flush(bt_device);
|
||||
bt_uart_send_data(bt_device, tx_buff, params_len + BT_HEAD_NUM);
|
||||
rt_thread_mdelay(5);
|
||||
ret = bt_uart_receive_data(bt_device, rx_buff, &recv_len, 1000);
|
||||
if (ret > 0)
|
||||
{
|
||||
ret = bt_reply_check(rx_buff, ogf, ocf, RT_NULL);
|
||||
if (ret == 0)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("err code is %d\n", ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
return RT_ERROR;
|
||||
|
||||
//if (hciCommand(OGF_LE_CONTROL, 0x01, params, 8)) uart_writeText("setLEeventmask failed\n");
|
||||
}
|
||||
|
||||
rt_err_t bt_getbdaddr(unsigned char *bdaddr)
|
||||
{
|
||||
static unsigned char params[] = {0x00, 0x10, 0x09, BT_HCI_COMMAND_PKT}; //get bdaddr
|
||||
int params_len = 4;
|
||||
int recv_len = BT_RX_MAX;
|
||||
|
||||
// rt_memcpy(tx_buff, params, 4);
|
||||
tx_buff[0] = BT_HCI_COMMAND_PKT;
|
||||
tx_buff[1] = 0x09;
|
||||
tx_buff[2] = 0x10;
|
||||
tx_buff[3] = 0x00;
|
||||
|
||||
bt_uart_receive_flush(bt_device);
|
||||
bt_uart_send_data(bt_device, tx_buff, 4);
|
||||
rt_thread_mdelay(100);
|
||||
bt_uart_receive_data(bt_device, rx_buff, &recv_len, 1000);
|
||||
if (recv_len > 0)
|
||||
{
|
||||
if ((rx_buff[0] != BT_HCI_EVENT_PKT) || (rx_buff[1] != BT_COMMAND_COMPLETE_CODE))
|
||||
{
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
if ((rx_buff[2] != 0x0a) || (rx_buff[3] != 0x01))
|
||||
{
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
if ((rx_buff[4] != 0x09) || (rx_buff[5] != 0x10))
|
||||
{
|
||||
return RT_ERROR;
|
||||
}
|
||||
bdaddr[0] = rx_buff[7];
|
||||
bdaddr[1] = rx_buff[8];
|
||||
bdaddr[2] = rx_buff[9];
|
||||
|
||||
bdaddr[3] = rx_buff[10];
|
||||
bdaddr[4] = rx_buff[11];
|
||||
bdaddr[5] = rx_buff[12];
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_err_t setLEscanenable(unsigned char state, unsigned char duplicates)
|
||||
{
|
||||
unsigned char params[] = {state, duplicates};
|
||||
|
||||
//static unsigned char params[] = { 0xee, 0xff, 0xc0, 0xee, 0xff, 0xc0 }; // reversed
|
||||
int params_len = 2;
|
||||
int ii = 0;
|
||||
int ret = 0;
|
||||
|
||||
int recv_len = BT_RX_MAX;
|
||||
rt_uint16_t ogf, ocf;
|
||||
|
||||
rt_memset(tx_buff, 0, BT_TX_MAX);
|
||||
|
||||
ogf = hi(BT_OGF_LE_CONTROL << 10 | 0x0c);
|
||||
ocf = lo(BT_OGF_LE_CONTROL << 10 | 0x0c);
|
||||
|
||||
bt_data_pack(tx_buff, ogf, ocf, params_len);
|
||||
tx_buff[4] = params[0];
|
||||
tx_buff[5] = params[1];
|
||||
|
||||
//rt_memcpy(&tx_buff[BT_HEAD_NUM], params, params_len);
|
||||
|
||||
for (ii = 0; ii < BT_TRY_NUM_MAX; ii++)
|
||||
{
|
||||
recv_len = BT_RX_MAX;
|
||||
bt_uart_receive_flush(bt_device);
|
||||
bt_uart_send_data(bt_device, tx_buff, params_len + BT_HEAD_NUM);
|
||||
rt_thread_mdelay(5);
|
||||
ret = bt_uart_receive_data(bt_device, rx_buff, &recv_len, 1000);
|
||||
if (ret > 0)
|
||||
{
|
||||
ret = bt_reply_check(rx_buff, ogf, ocf, RT_NULL);
|
||||
if (ret == 0)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("err code is %d\n", ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
rt_err_t setLEscanparameters(unsigned char type, unsigned char linterval, unsigned char hinterval, unsigned char lwindow, unsigned char hwindow, unsigned char own_address_type, unsigned char filter_policy)
|
||||
{
|
||||
unsigned char params[] = {type, linterval, hinterval, lwindow, hwindow, own_address_type, filter_policy};
|
||||
|
||||
int params_len = 7;
|
||||
int ii = 0;
|
||||
int ret = 0;
|
||||
|
||||
int recv_len = BT_RX_MAX;
|
||||
rt_uint16_t ogf, ocf;
|
||||
|
||||
rt_memset(tx_buff, 0, BT_TX_MAX);
|
||||
|
||||
ogf = hi(BT_OGF_LE_CONTROL << 10 | 0x0b);
|
||||
ocf = lo(BT_OGF_LE_CONTROL << 10 | 0x0b);
|
||||
|
||||
bt_data_pack(tx_buff, ogf, ocf, params_len);
|
||||
tx_buff[4] = params[0];
|
||||
tx_buff[5] = params[1];
|
||||
tx_buff[6] = params[2];
|
||||
tx_buff[7] = params[3];
|
||||
tx_buff[8] = params[4];
|
||||
tx_buff[9] = params[5];
|
||||
tx_buff[10] = params[6];
|
||||
//rt_memcpy(&tx_buff[BT_HEAD_NUM], params, params_len);
|
||||
|
||||
for (ii = 0; ii < BT_TRY_NUM_MAX; ii++)
|
||||
{
|
||||
recv_len = BT_RX_MAX;
|
||||
bt_uart_receive_flush(bt_device);
|
||||
bt_uart_send_data(bt_device, tx_buff, params_len + BT_HEAD_NUM);
|
||||
rt_thread_mdelay(5);
|
||||
ret = bt_uart_receive_data(bt_device, rx_buff, &recv_len, 1000);
|
||||
if (ret > 0)
|
||||
{
|
||||
ret = bt_reply_check(rx_buff, ogf, ocf, RT_NULL);
|
||||
if (ret == 0)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("err code is %d\n", ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
rt_err_t startActiveScanning()
|
||||
{
|
||||
float BleScanInterval = 60; // every 60ms
|
||||
float BleScanWindow = 60;
|
||||
float BleScanDivisor = 0.625;
|
||||
|
||||
unsigned int p = BleScanInterval / BleScanDivisor;
|
||||
unsigned int q = BleScanWindow / BleScanDivisor;
|
||||
|
||||
if (setLEscanparameters(BT_LL_SCAN_ACTIVE, lo(p), hi(p), lo(q), hi(q), 0, 0) == RT_EOK)
|
||||
{
|
||||
rt_kprintf("setLEscanparameters ok!\n");
|
||||
}
|
||||
if (setLEscanenable(1, 0) == RT_EOK)
|
||||
{
|
||||
rt_kprintf("setLEscanenable ok!\n");
|
||||
}
|
||||
}
|
||||
|
||||
rt_err_t bt_setbdaddr(void)
|
||||
{
|
||||
static unsigned char params[] = {0xee, 0xff, 0xc0, 0xee, 0xff, 0xc0}; // reversed
|
||||
int params_len = 6;
|
||||
int ii = 0;
|
||||
int ret = 0;
|
||||
|
||||
int recv_len = BT_RX_MAX;
|
||||
rt_uint16_t ogf, ocf;
|
||||
|
||||
rt_memset(tx_buff, 0, BT_TX_MAX);
|
||||
|
||||
ogf = hi(BT_OGF_VENDOR << 10 | BT_COMMAND_SET_BDADDR);
|
||||
ocf = lo(BT_OGF_VENDOR << 10 | BT_COMMAND_SET_BDADDR);
|
||||
|
||||
bt_data_pack(tx_buff, ogf, ocf, params_len);
|
||||
|
||||
tx_buff[4] = 0xc0;
|
||||
tx_buff[5] = 0xff;
|
||||
tx_buff[6] = 0xee;
|
||||
tx_buff[7] = 0xc0;
|
||||
tx_buff[8] = 0xff;
|
||||
tx_buff[9] = 0xee;
|
||||
|
||||
//rt_memcpy(&tx_buff[BT_HEAD_NUM], params, params_len);
|
||||
|
||||
for (ii = 0; ii < BT_TRY_NUM_MAX; ii++)
|
||||
{
|
||||
recv_len = BT_RX_MAX;
|
||||
bt_uart_receive_flush(bt_device);
|
||||
bt_uart_send_data(bt_device, tx_buff, params_len + BT_HEAD_NUM);
|
||||
rt_thread_mdelay(5);
|
||||
ret = bt_uart_receive_data(bt_device, rx_buff, &recv_len, 1000);
|
||||
if (ret > 0)
|
||||
{
|
||||
ret = bt_reply_check(rx_buff, ogf, ocf, RT_NULL);
|
||||
if (ret == 0)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("err code is %d\n", ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
return RT_ERROR;
|
||||
}
|
||||
rt_err_t bt_reset(void)
|
||||
{
|
||||
int ii = 0;
|
||||
int ret = 0;
|
||||
int recv_len = BT_RX_MAX;
|
||||
rt_uint16_t ogf, ocf;
|
||||
|
||||
rt_memset(tx_buff, 0, BT_TX_MAX);
|
||||
|
||||
ogf = hi(BT_OGF_HOST_CONTROL << 10 | BT_COMMAND_RESET_CHIP);
|
||||
ocf = lo(BT_OGF_HOST_CONTROL << 10 | BT_COMMAND_RESET_CHIP);
|
||||
|
||||
bt_data_pack(tx_buff, ogf, ocf, 0);
|
||||
for (ii = 0; ii < BT_TRY_NUM_MAX; ii++)
|
||||
{
|
||||
recv_len = BT_RX_MAX;
|
||||
bt_uart_receive_flush(bt_device);
|
||||
bt_uart_send_data(bt_device, tx_buff, 8);
|
||||
rt_thread_mdelay(5);
|
||||
ret = bt_uart_receive_data(bt_device, rx_buff, &recv_len, 1000);
|
||||
//rt_kprintf("recv_len is %d\n", recv_len);
|
||||
if (ret > 0)
|
||||
{
|
||||
ret = bt_reply_check(rx_buff, ogf, ocf, RT_NULL);
|
||||
if (ret == 0)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("err code is %d\n", ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
rt_device_t bt_uart_init(const char *uartname)
|
||||
{
|
||||
rt_device_t dev = RT_NULL;
|
||||
if (strcmp(uartname, BT_UART_NAME) == 0)
|
||||
{
|
||||
bt_rx_sem = rt_sem_create("btbuf", 0, RT_IPC_FLAG_FIFO);
|
||||
dev = rt_device_find(uartname);
|
||||
if (dev == RT_NULL)
|
||||
{
|
||||
rt_kprintf("can no find dev %s\n", uartname);
|
||||
return dev;
|
||||
}
|
||||
|
||||
if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) == RT_EOK)
|
||||
{
|
||||
rt_device_set_rx_indicate(dev, bt_rx_ind);
|
||||
}
|
||||
return dev;
|
||||
}
|
||||
return dev;
|
||||
}
|
||||
|
||||
static void bt_task_entry(void *param)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
rt_thread_delay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
#define MAX_MSG_LEN 50
|
||||
#define MAX_READ_RUN 100
|
||||
|
||||
unsigned char data_buf[MAX_MSG_LEN];
|
||||
unsigned int data_len;
|
||||
unsigned int messages_received = 0;
|
||||
unsigned int poll_state = 0;
|
||||
|
||||
unsigned int got_echo_sid = 0;
|
||||
unsigned int got_echo_name = 0;
|
||||
unsigned char echo_addr[6];
|
||||
|
||||
void hci_poll2(unsigned char byte)
|
||||
{
|
||||
switch (poll_state)
|
||||
{
|
||||
case 0:
|
||||
if (byte != HCI_EVENT_PKT)
|
||||
poll_state = 0;
|
||||
else
|
||||
poll_state = 1;
|
||||
break;
|
||||
case 1:
|
||||
if (byte != LE_EVENT_CODE)
|
||||
poll_state = 0;
|
||||
else
|
||||
poll_state = 2;
|
||||
break;
|
||||
case 2:
|
||||
if (byte > MAX_MSG_LEN)
|
||||
poll_state = 0;
|
||||
else
|
||||
{
|
||||
poll_state = 3;
|
||||
data_len = byte;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
data_buf[poll_state - 3] = byte;
|
||||
if (poll_state == data_len + 3 - 1)
|
||||
{
|
||||
messages_received++;
|
||||
poll_state = 0;
|
||||
}
|
||||
else
|
||||
poll_state++;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned char *hci_poll()
|
||||
{
|
||||
int recv_len = 256;
|
||||
unsigned int goal = messages_received + 1;
|
||||
bt_uart_receive_data(bt_device, rx_buff, &recv_len, 1000);
|
||||
rt_thread_mdelay(10);
|
||||
if (recv_len > 0)
|
||||
{
|
||||
unsigned int run = 0;
|
||||
while (run < MAX_READ_RUN && messages_received < goal)
|
||||
{
|
||||
|
||||
recv_len = recv_len - 1;
|
||||
hci_poll2(rx_buff[recv_len]);
|
||||
run++;
|
||||
|
||||
if (recv_len == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (run == MAX_READ_RUN)
|
||||
return 0;
|
||||
else
|
||||
return data_buf;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void bt_search()
|
||||
{
|
||||
unsigned char *buf;
|
||||
|
||||
while ((buf = hci_poll()))
|
||||
{
|
||||
if (data_len >= 2)
|
||||
{
|
||||
if (buf[0] == LE_ADREPORT_CODE)
|
||||
{
|
||||
unsigned char numreports = buf[1];
|
||||
|
||||
if (numreports == 1)
|
||||
{
|
||||
unsigned char event_type = buf[2];
|
||||
|
||||
if (event_type == 0x00)
|
||||
{
|
||||
unsigned char buf_len = buf[10];
|
||||
unsigned char ad_len = buf[11];
|
||||
|
||||
if (ad_len < data_len && buf_len + 11 == data_len - 1)
|
||||
{
|
||||
for (int c = 9; c >= 4; c--)
|
||||
echo_addr[9 - c] = buf[c];
|
||||
buf += 11;
|
||||
|
||||
got_echo_sid = 0;
|
||||
got_echo_name = 0; // Reset the search state machine
|
||||
do
|
||||
{
|
||||
ad_len = buf[0];
|
||||
unsigned char ad_type = buf[1];
|
||||
buf += 2;
|
||||
|
||||
if (ad_len >= 2)
|
||||
{
|
||||
if (ad_type == 0x03)
|
||||
{
|
||||
unsigned int sid = 0;
|
||||
|
||||
for (int d = 0; d < ad_len - 1; d += 2)
|
||||
{
|
||||
sid = buf[d] | (buf[d + 1] << 8);
|
||||
if (sid == 0xEC00)
|
||||
{
|
||||
rt_kprintf("sid is %d\n", sid);
|
||||
//uart_hex(sid); uart_writeText(" ");
|
||||
got_echo_sid = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (ad_type == 0x09)
|
||||
{
|
||||
char remote_name[ad_len - 1];
|
||||
unsigned int d = 0;
|
||||
|
||||
while (d < ad_len - 1)
|
||||
{
|
||||
remote_name[d] = buf[d];
|
||||
d++;
|
||||
}
|
||||
if (!memcmp(remote_name, "echo", 4))
|
||||
{
|
||||
rt_kprintf("remote_name is %s\n", remote_name);
|
||||
got_echo_name = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
buf += ad_len - 1;
|
||||
} while (buf[1]);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void bt_uart_protocol_init()
|
||||
{
|
||||
rt_thread_t bt_tid = RT_NULL;
|
||||
bt_device = bt_uart_init(BT_UART_NAME);
|
||||
bt_tid = rt_thread_create("bt_task", bt_task_entry, RT_NULL, BT_THREAD_STACK_SIZE, BT_THREAD_PRIORITY, BT_THREAD_TICK);
|
||||
if (bt_tid == RT_NULL)
|
||||
{
|
||||
rt_kprintf("bt_task create err!\n");
|
||||
return 0;
|
||||
}
|
||||
rt_thread_startup(bt_tid);
|
||||
}
|
||||
|
||||
int rt_hw_bluetooth_init(void)
|
||||
{
|
||||
bt_uart_protocol_init();
|
||||
if (bt_reset() == RT_EOK)
|
||||
{
|
||||
rt_kprintf("bluetooth reset ok!\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("bluetooth reset err!\n");
|
||||
}
|
||||
|
||||
rt_thread_delay(10);
|
||||
if (bt_loadfirmware() == RT_EOK)
|
||||
{
|
||||
rt_kprintf("loadfirmware ok!\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("loadfirmware err!\n");
|
||||
}
|
||||
rt_thread_delay(10);
|
||||
if (bt_setbaud() == RT_EOK)
|
||||
{
|
||||
rt_kprintf("setbaud ok!\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("setbaud err!\n");
|
||||
}
|
||||
|
||||
rt_thread_delay(10);
|
||||
if (bt_setbdaddr() == RT_EOK)
|
||||
{
|
||||
rt_kprintf("setbdaddr ok!\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("setbdaddr err!\n");
|
||||
}
|
||||
rt_thread_delay(100);
|
||||
rt_uint8_t bdaddr[6];
|
||||
if (bt_getbdaddr(bdaddr) == RT_EOK)
|
||||
{
|
||||
rt_kprintf("bdaddr :%02x:%02x:%02x:%02x:%02x:%02x\n", bdaddr[0], bdaddr[1], bdaddr[2], bdaddr[3], bdaddr[4], bdaddr[5]);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("getbdaddr err!\n");
|
||||
}
|
||||
|
||||
rt_thread_delay(100);
|
||||
|
||||
if (setLEeventmask(0xff) == RT_EOK)
|
||||
{
|
||||
rt_kprintf("setLEeventmask ok!\n");
|
||||
}
|
||||
rt_thread_delay(100);
|
||||
startActiveScanning();
|
||||
rt_thread_delay(500);
|
||||
rt_kprintf("start!\n");
|
||||
while (1)
|
||||
{
|
||||
bt_search();
|
||||
if (got_echo_sid && got_echo_name)
|
||||
{
|
||||
break;
|
||||
}
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
rt_kprintf("stop scan!\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-29 bigmagic first version
|
||||
*/
|
||||
#ifndef __DRV_BT_H__
|
||||
#define __DRV_BT_H__
|
||||
|
||||
#define BT_HCI_COMMAND_PKT (0x01)
|
||||
#define BT_OGF_HOST_CONTROL (0x03)
|
||||
#define BT_OGF_LE_CONTROL (0x08)
|
||||
#define BT_OGF_VENDOR (0x3f)
|
||||
#define BT_COMMAND_SET_BDADDR (0x01)
|
||||
#define BT_COMMAND_RESET_CHIP (0x03)
|
||||
#define BT_COMMAND_SET_BAUD (0x18)
|
||||
#define BT_COMMAND_LOAD_FIRMWARE (0x2e)
|
||||
#define BT_HCI_ACL_PKT (0x02)
|
||||
#define BT_HCI_EVENT_PKT (0x04)
|
||||
#define BT_COMMAND_COMPLETE_CODE (0x0e)
|
||||
#define BT_CONNECT_COMPLETE_CODE (0x0f)
|
||||
#define BT_LL_SCAN_ACTIVE (0x01)
|
||||
#define BT_LL_ADV_NONCONN_IND (0x03)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-12-02 bigmagic first version
|
||||
*/
|
||||
#include "drv_dma.h"
|
||||
#include "raspi4.h"
|
||||
|
||||
volatile unsigned int __attribute__((aligned(256))) dma_disc[32];
|
||||
//https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=10276
|
||||
static struct rt_semaphore dma_sem;
|
||||
|
||||
//DMA 0 1 2 3 4 5 6
|
||||
typedef struct _dma_ctrl_block
|
||||
{
|
||||
unsigned int TI; // Transfer information
|
||||
unsigned int SOURCE_AD; // source address
|
||||
unsigned int DEST_AD; // destination address
|
||||
unsigned int TXFR_LEN; // transfer length
|
||||
unsigned int STRIDE; // 2D mode stride
|
||||
struct _dma_ctrl_block *NEXTCONBK; // Next control block address
|
||||
unsigned int DEBUG;
|
||||
unsigned int reserved1;
|
||||
|
||||
} dma_ctrl_block_t;
|
||||
|
||||
//DMA 7 8 9 10
|
||||
typedef struct _dma_lite_ctrl_block
|
||||
{
|
||||
unsigned int TI; // Transfer information
|
||||
unsigned int SOURCE_AD; // source address
|
||||
unsigned int DEST_AD; // destination address
|
||||
unsigned int TXFR_LEN; // transfer length
|
||||
struct _dma_lite_ctrl_block *NEXTCONBK; // Next control block address
|
||||
unsigned int DEBUG;
|
||||
unsigned int reserved1;
|
||||
unsigned int reserved2;
|
||||
|
||||
} dma_lite_ctrl_block_t;
|
||||
|
||||
//DMA 11 12 13 14 15
|
||||
typedef struct _dma4_ctrl_block
|
||||
{
|
||||
unsigned int TI; // Transfer information
|
||||
unsigned int SOURCE_AD0; // source address0
|
||||
unsigned int SOURCE_AD1; // source address1
|
||||
unsigned int DEST_AD0; // destination address0
|
||||
unsigned int DEST_AD1; // destination address1
|
||||
unsigned int TXFR_LEN; // transfer length
|
||||
unsigned int STRIDE; // 2D mode stride
|
||||
struct _dma4_ctrl_block *NEXTCONBK; // Next control block address
|
||||
} dma4_ctrl_block_t;
|
||||
|
||||
static dma_lite_ctrl_block_t *ctr_blocks;
|
||||
|
||||
static void dma_irq(int irq, void *param)
|
||||
{
|
||||
if (DMA_INT_STATUS_REG & DMA_INT7)
|
||||
{
|
||||
DMA_CS(7) = DMA_CS_INT;
|
||||
rt_sem_release(&dma_sem);
|
||||
}
|
||||
}
|
||||
|
||||
//dma 7 8 9 10:XLENGTH
|
||||
rt_err_t dma_memcpy(void *src, void *dst, unsigned int size, unsigned int dch, unsigned int timeout)
|
||||
{
|
||||
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, dst, size);
|
||||
|
||||
/* Stop DMA, if it was already started */
|
||||
DMA_CS(dch) = DMA_CS_RESET;
|
||||
|
||||
/* Clear DMA status flags */
|
||||
DMA_CS(dch) = DMA_CS_INT | DMA_CS_END; /* Interrupted flag & Transmission ended flag*/
|
||||
//cb info
|
||||
ctr_blocks->TI = DMA_TI_SRC_INC | DMA_TI_DEST_INC | DMA_TI_INTEN;
|
||||
ctr_blocks->SOURCE_AD = (unsigned int)src;
|
||||
ctr_blocks->DEST_AD = (unsigned int)dst;
|
||||
ctr_blocks->TXFR_LEN = size;
|
||||
ctr_blocks->NEXTCONBK = 0;
|
||||
ctr_blocks->reserved1 = 0;
|
||||
ctr_blocks->reserved2 = 0;
|
||||
|
||||
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, ctr_blocks, sizeof(dma_lite_ctrl_block_t) * 8);
|
||||
|
||||
DMA_CONBLK_AD(dch) = (rt_uint32_t)ctr_blocks;
|
||||
DMA_CS(dch) = DMA_CS_INT | DMA_CS_END | DMA_CS_ACTIVE;
|
||||
|
||||
if(rt_sem_take(&dma_sem, timeout) != RT_EOK)
|
||||
{
|
||||
rt_kprintf("dma transfer timeout!\n");
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
void dma_init(unsigned char dch)
|
||||
{
|
||||
rt_sem_init(&dma_sem, "dma_sem", 0, RT_IPC_FLAG_FIFO);
|
||||
|
||||
ctr_blocks = (dma_lite_ctrl_block_t *)&dma_disc[0]; //rt_malloc(sizeof(DMA_Lite_Control_Block));
|
||||
//Make sure DMA channel is enabled by
|
||||
//writing the corresponding bit in DMA_ENABLE in the DMA register to 1
|
||||
DMA_ENABLE_REG = (1 << dch);
|
||||
|
||||
rt_hw_interrupt_install(IRQ_DMA7_DMA8, dma_irq, RT_NULL, "dma_irq");
|
||||
rt_hw_interrupt_umask(IRQ_DMA7_DMA8);
|
||||
}
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-12-02 bigmagic first version
|
||||
*/
|
||||
#ifndef __DRV_DMA_H__
|
||||
#define __DRV_DMA_H__
|
||||
|
||||
#include <rthw.h>
|
||||
|
||||
#define DMA_PER_BASE (0xFE000000)
|
||||
|
||||
//DMA
|
||||
#define DMA_BASE (DMA_PER_BASE+0x7000)
|
||||
#define DMA_INT_STATUS (DMA_BASE + 0xFE0) //Interrupt Status of each DMA Channel
|
||||
#define DMA_ENABLE (DMA_BASE + 0xFF0) //Global Enable bits for each DMA Channel */
|
||||
#define DMA15_BASE (DMA_PER_BASE+0xE05000) //DMA Channel 15 Register Set */
|
||||
|
||||
|
||||
#define DMA_INT_STATUS_REG __REG32(DMA_INT_STATUS)
|
||||
#define DMA_ENABLE_REG __REG32(DMA_ENABLE)
|
||||
//DMA dch 1~14
|
||||
#define DMA_CS(dch) __REG32(DMA_BASE + dch*0x100 + 0x000) /* Control and Status */
|
||||
#define DMA_CONBLK_AD(dch) __REG32(DMA_BASE + dch*0x100 + 0x004) /* Control Block Address */
|
||||
#define DMA_TI(dch) __REG32(DMA_BASE + dch*0x100 + 0x008) /* CB Word 0(Transfer Information) */
|
||||
#define DMA_SOURCE_AD(dch) __REG32(DMA_BASE + dch*0x100 + 0x00c) /* CB Word 1(Source Address) */
|
||||
#define DMA_DEST_AD(dch) __REG32(DMA_BASE + dch*0x100 + 0x010) /* CB Word 2(Destination Address) */
|
||||
#define DMA_TXFR_LEN(dch) __REG32(DMA_BASE + dch*0x100 + 0x014) /* CB Word 3(Transfer Length) */
|
||||
#define DMA_STRIDE(dch) __REG32(DMA_BASE + dch*0x100 + 0x018) /* CB Word 4(2D Stride) */
|
||||
#define DMA_NEXTCONBK(dch) __REG32(DMA_BASE + dch*0x100 + 0x01c) /* CB Word 5(Next CB Address) */
|
||||
#define DMA_DEBUG(dch) __REG32(DMA_BASE + dch*0x100 + 0x01c) /* Debug */
|
||||
|
||||
//DMA dch 15
|
||||
#define DMA15_CS __REG32(DMA15_BASE + 0x000) /* Control and Status */
|
||||
#define DMA15_CONBLK_AD __REG32(DMA15_BASE + 0x004) /* Control Block Address */
|
||||
#define DMA15_TI __REG32(DMA15_BASE + 0x008) /* CB Word 0(Transfer Information) */
|
||||
#define DMA15_SOURCE_AD __REG32(DMA15_BASE + 0x00c) /* CB Word 1(Source Address) */
|
||||
#define DMA15_DEST_AD __REG32(DMA15_BASE + 0x010) /* CB Word 2(Destination Address) */
|
||||
#define DMA15_TXFR_LEN __REG32(DMA15_BASE + 0x014) /* CB Word 3(Transfer Length) */
|
||||
#define DMA15_STRIDE __REG32(DMA15_BASE + 0x018) /* CB Word 4(2D Stride) */
|
||||
#define DMA15_NEXTCONBK __REG32(DMA15_BASE + 0x01c) /* CB Word 5(Next CB Address) */
|
||||
#define DMA15_DEBUG __REG32(DMA15_BASE + 0x01c) /* Debug */
|
||||
|
||||
#define DMA15_ENABLE (1 << 15)
|
||||
#define DMA14_ENABLE (1 << 14)
|
||||
#define DMA13_ENABLE (1 << 13)
|
||||
#define DMA12_ENABLE (1 << 12)
|
||||
#define DMA11_ENABLE (1 << 11)
|
||||
#define DMA10_ENABLE (1 << 10)
|
||||
#define DMA9_ENABLE (1 << 9)
|
||||
#define DMA8_ENABLE (1 << 8)
|
||||
#define DMA7_ENABLE (1 << 7)
|
||||
#define DMA6_ENABLE (1 << 6)
|
||||
#define DMA5_ENABLE (1 << 5)
|
||||
#define DMA4_ENABLE (1 << 4)
|
||||
#define DMA3_ENABLE (1 << 3)
|
||||
#define DMA2_ENABLE (1 << 2)
|
||||
#define DMA1_ENABLE (1 << 1)
|
||||
#define DMA0_ENABLE (1 << 0)
|
||||
|
||||
//Peripheral DREQ Signals
|
||||
#define DREQ_DSI0_PWM1 (1)
|
||||
#define DREQ_PCM_TX (2)
|
||||
#define DREQ_PCM_RX (3)
|
||||
#define DREQ_SMI (4)
|
||||
#define DREQ_PWM0 (5)
|
||||
#define DREQ_SPI0_TX (6)
|
||||
#define DREQ_SPI0_RX (7)
|
||||
#define DREQ_BSC_SPI_SLAVE_TX (8)
|
||||
#define DREQ_BSC_SPI_SLAVE_RX (9)
|
||||
#define DREQ_HSMI0 (10)
|
||||
#define DREQ_EMMC (11)
|
||||
#define DREQ_UART0_TX (12)
|
||||
#define DREQ_SD_HOST (13)
|
||||
#define DREQ_UART0_RX (14)
|
||||
#define DREQ_DSI1 (15)
|
||||
#define DREQ_SPI1_TX (16)
|
||||
#define DREQ_HDMI1 (17)
|
||||
#define DREQ_SPI1_RX (18)
|
||||
#define DREQ_UART3_TX_SPI4_TX (19)
|
||||
#define DREQ_UART3_RX_SPI4_RX (20)
|
||||
#define DREQ_UART5_TX_SPI5_TX (21)
|
||||
#define DREQ_UART5_RX_SPI5_RX (22)
|
||||
#define DREQ_SPI6_TX (23)
|
||||
#define DREQ_SCALER_FIFO0_SMI (24)
|
||||
#define DREQ_SCALER_FIFO1_SMI (25)
|
||||
#define DREQ_SCALER_FIFO2_SMI (26)
|
||||
#define DREQ_SPI6_RX (27)
|
||||
#define DREQ_UART2_TX (28)
|
||||
#define DREQ_UART2_RX (29)
|
||||
#define DREQ_UART4_TX (30)
|
||||
#define DREQ_UART4_RX (31)
|
||||
|
||||
//IRQ
|
||||
#define DMA_INT15 (1 << 15)
|
||||
#define DMA_INT14 (1 << 14)
|
||||
#define DMA_INT13 (1 << 13)
|
||||
#define DMA_INT12 (1 << 12)
|
||||
#define DMA_INT11 (1 << 11)
|
||||
#define DMA_INT10 (1 << 10)
|
||||
#define DMA_INT9 (1 << 9)
|
||||
#define DMA_INT8 (1 << 8)
|
||||
#define DMA_INT7 (1 << 7)
|
||||
#define DMA_INT6 (1 << 6)
|
||||
#define DMA_INT5 (1 << 5)
|
||||
#define DMA_INT4 (1 << 4)
|
||||
#define DMA_INT3 (1 << 3)
|
||||
#define DMA_INT2 (1 << 2)
|
||||
#define DMA_INT1 (1 << 1)
|
||||
#define DMA_INT0 (1 << 0)
|
||||
|
||||
//IRQ_NUMBER
|
||||
#define IRQ_DMA0 (96 + 16)
|
||||
#define IRQ_DMA1 (96 + 17)
|
||||
#define IRQ_DMA2 (96 + 18)
|
||||
#define IRQ_DMA3 (96 + 19)
|
||||
#define IRQ_DMA4 (96 + 20)
|
||||
#define IRQ_DMA5 (96 + 21)
|
||||
#define IRQ_DMA6 (96 + 22)
|
||||
#define IRQ_DMA7_DMA8 (96 + 23)
|
||||
#define IRQ_DMA9_DMA10 (96 + 24)
|
||||
#define IRQ_DMA11 (96 + 25)
|
||||
#define IRQ_DMA12 (96 + 26)
|
||||
#define IRQ_DMA13 (96 + 27)
|
||||
#define IRQ_DMA14 (96 + 28)
|
||||
#define IRQ_DMA15 (96 + 31)
|
||||
|
||||
//CS
|
||||
#define DMA_CS_RESET (1 << 31)
|
||||
#define DMA_CS_ABORT (1 << 30)
|
||||
#define DMA_CS_DISDEBUG (1 << 29)
|
||||
#define DMA_CS_DREQ_STOPS_DMA (1 << 5)
|
||||
#define DMA_CS_PAUSED (1 << 4)
|
||||
#define DMA_CS_DREQ (1 << 3)
|
||||
#define DMA_CS_INT (1 << 2)
|
||||
#define DMA_CS_END (1 << 1)
|
||||
#define DMA_CS_ACTIVE (1 << 0)
|
||||
|
||||
//CONBLK_AD
|
||||
//The address must be256-bit aligned, so the bottom 5 bits of the address mustbe zero.
|
||||
|
||||
//TI
|
||||
//DMA Transfer Information.
|
||||
#define DMA_TI_SRC_IGNORE (1 << 11)
|
||||
#define DMA_TI_SRC_DREQ (1 << 10)
|
||||
#define DMA_TI_SRC_WIDTH (1 << 9)
|
||||
#define DMA_TI_SRC_INC (1 << 8)
|
||||
#define DMA_TI_DEST_IGNORE (1 << 7)
|
||||
#define DMA_TI_DEST_DREQ (1 << 6)
|
||||
#define DMA_TI_DEST_WIDTH (1 << 5)
|
||||
#define DMA_TI_DEST_INC (1 << 4)
|
||||
#define DMA_TI_WAIT_RESP (1 << 3)
|
||||
#define DMA_TI_TDMODE (1 << 1)
|
||||
#define DMA_TI_INTEN (1 << 0)
|
||||
|
||||
//SOURCE_AD
|
||||
//DMA Source Address
|
||||
|
||||
//DEST_AD
|
||||
//DMA Destination Address
|
||||
|
||||
//TXFR_LEN
|
||||
//DMA Transfer Length
|
||||
|
||||
void dma_init(unsigned char dch);
|
||||
rt_err_t dma_memcpy(void *src, void *dst, unsigned int size, unsigned int dch, unsigned int timeout);
|
||||
|
||||
#endif
|
||||
|
|
@ -19,6 +19,15 @@
|
|||
#include "raspi4.h"
|
||||
#include "drv_eth.h"
|
||||
|
||||
//#define ETH_RX_POLL
|
||||
|
||||
#define DBG_LEVEL DBG_LOG
|
||||
#include <rtdbg.h>
|
||||
#define LOG_TAG "drv.eth"
|
||||
|
||||
static int link_speed = 0;
|
||||
static int link_flag = 0;
|
||||
|
||||
#define RECV_CACHE_BUF (1024)
|
||||
#define SEND_DATA_NO_CACHE (0x08200000)
|
||||
#define RECV_DATA_NO_CACHE (0x08400000)
|
||||
|
|
@ -34,6 +43,11 @@
|
|||
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
|
||||
static rt_thread_t link_thread_tid = RT_NULL;
|
||||
#define LINK_THREAD_STACK_SIZE (1024)
|
||||
#define LINK_THREAD_PRIORITY (20)
|
||||
#define LINK_THREAD_TIMESLICE (10)
|
||||
|
||||
static rt_uint32_t tx_index = 0;
|
||||
static rt_uint32_t rx_index = 0;
|
||||
static rt_uint32_t index_flag = 0;
|
||||
|
|
@ -54,6 +68,7 @@ struct rt_eth_dev
|
|||
};
|
||||
static struct rt_eth_dev eth_dev;
|
||||
static struct rt_semaphore sem_lock;
|
||||
static struct rt_semaphore link_ack;
|
||||
|
||||
static inline rt_uint32_t read32(void *addr)
|
||||
{
|
||||
|
|
@ -65,16 +80,33 @@ static inline void write32(void *addr, rt_uint32_t value)
|
|||
(*((volatile unsigned int*)(addr))) = value;
|
||||
}
|
||||
|
||||
void eth_rx_irq(void *param)
|
||||
static void eth_rx_irq(int irq, void *param)
|
||||
{
|
||||
#ifndef ETH_RX_POLL
|
||||
rt_uint32_t val = 0;
|
||||
val = read32(MAC_REG + GENET_INTRL2_CPU_STAT);
|
||||
val &= ~read32(MAC_REG + GENET_INTRL2_CPU_STAT_MASK);
|
||||
write32(MAC_REG + GENET_INTRL2_CPU_CLEAR, val);
|
||||
if (val & GENET_IRQ_RXDMA_DONE)
|
||||
{
|
||||
eth_device_ready(ð_dev.parent);
|
||||
}
|
||||
|
||||
if (val & GENET_IRQ_TXDMA_DONE)
|
||||
{
|
||||
//todo
|
||||
}
|
||||
#else
|
||||
eth_device_ready(ð_dev.parent);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* We only support RGMII (as used on the RPi4). */
|
||||
static int bcmgenet_interface_set(void)
|
||||
{
|
||||
int phy_mode = PHY_INTERFACE_MODE_RGMII;
|
||||
switch (phy_mode) {
|
||||
switch (phy_mode)
|
||||
{
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
write32(MAC_REG + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY);
|
||||
|
|
@ -158,7 +190,6 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va
|
|||
reg_val = read32(MAC_REG + MDIO_CMD);
|
||||
|
||||
return reg_val & 0xffff;
|
||||
|
||||
}
|
||||
|
||||
static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg)
|
||||
|
|
@ -209,7 +240,7 @@ static int get_ethernet_uid(void)
|
|||
|
||||
if (BCM54213PE_VERSION_B1 == uid)
|
||||
{
|
||||
rt_kprintf("version is B1\n");
|
||||
LOG_I("version is B1\n");
|
||||
}
|
||||
return uid;
|
||||
}
|
||||
|
|
@ -236,11 +267,13 @@ static void bcmgenet_mdio_init(void)
|
|||
/* read status reg */
|
||||
bcmgenet_mdio_read(1, BCM54213PE_IEEE_EXTENDED_STATUS);
|
||||
bcmgenet_mdio_read(1, BCM54213PE_AUTO_NEGOTIATION_ADV);
|
||||
|
||||
bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS);
|
||||
bcmgenet_mdio_read(1, BCM54213PE_CONTROL);
|
||||
/* half full duplex capability */
|
||||
bcmgenet_mdio_write(1, BCM54213PE_CONTROL, (CONTROL_HALF_DUPLEX_CAPABILITY | CONTROL_FULL_DUPLEX_CAPABILITY));
|
||||
bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL);
|
||||
|
||||
/* set mii control */
|
||||
bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, (MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART | MII_CONTROL_PHY_FULL_DUPLEX | MII_CONTROL_SPEED_SELECTION));
|
||||
}
|
||||
|
|
@ -284,55 +317,21 @@ static void rx_descs_init(void)
|
|||
void *desc_base = (void *)RX_DESC_BASE;
|
||||
|
||||
len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
|
||||
for (i = 0; i < RX_DESCS; i++) {
|
||||
for (i = 0; i < RX_DESCS; i++)
|
||||
{
|
||||
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO), lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]));
|
||||
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI), upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]));
|
||||
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS), len_stat);
|
||||
}
|
||||
}
|
||||
|
||||
static int phy_startup(void)
|
||||
{
|
||||
int count = 1000000;
|
||||
while ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) && (--count))
|
||||
DELAY_MICROS(1);
|
||||
if(count > 0)
|
||||
{
|
||||
rt_kprintf("bcmgenet: PHY startup ok!\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("bcmgenet: PHY startup err!\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
if(bcmgenet_mdio_read(1, BCM54213PE_STATUS) == 0)
|
||||
{
|
||||
//todo
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("bcmgenet: BCM54213PE_STATUS err!\n");
|
||||
}
|
||||
|
||||
if(bcmgenet_mdio_read(1, BCM54213PE_CONTROL) == (CONTROL_FULL_DUPLEX_CAPABILITY| CONTROL_HALF_DUPLEX_CAPABILITY))
|
||||
{
|
||||
//todo
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("bcmgenet: BCM54213PE_CONTROL err!\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcmgenet_adjust_link(void)
|
||||
{
|
||||
rt_uint32_t speed;
|
||||
rt_uint32_t phy_dev_speed = SPEED_100;
|
||||
rt_uint32_t phy_dev_speed = link_speed;
|
||||
|
||||
switch (phy_dev_speed) {
|
||||
switch (phy_dev_speed)
|
||||
{
|
||||
case SPEED_1000:
|
||||
speed = UMAC_SPEED_1000;
|
||||
break;
|
||||
|
|
@ -358,6 +357,14 @@ static int bcmgenet_adjust_link(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void link_irq(void *param)
|
||||
{
|
||||
if ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) != 0)
|
||||
{
|
||||
rt_sem_release(&link_ack);
|
||||
}
|
||||
}
|
||||
|
||||
static int bcmgenet_gmac_eth_start(void)
|
||||
{
|
||||
rt_uint32_t ret;
|
||||
|
|
@ -375,16 +382,10 @@ static int bcmgenet_gmac_eth_start(void)
|
|||
/* Enable RX/TX DMA */
|
||||
bcmgenet_enable_dma();
|
||||
|
||||
/* read PHY properties over the wire from generic PHY set-up */
|
||||
ret = phy_startup();
|
||||
if (ret) {
|
||||
rt_kprintf("bcmgenet: PHY startup failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Update MAC registers based on PHY property */
|
||||
ret = bcmgenet_adjust_link();
|
||||
if (ret) {
|
||||
if(ret)
|
||||
{
|
||||
rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -410,6 +411,8 @@ static int bcmgenet_gmac_eth_start(void)
|
|||
rx_tx_en |= (CMD_TX_EN | CMD_RX_EN);
|
||||
|
||||
write32(MAC_REG + UMAC_CMD, rx_tx_en);
|
||||
//IRQ
|
||||
write32(MAC_REG + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -424,6 +427,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
|
|||
if(prod_index == index_flag)
|
||||
{
|
||||
cur_recv_cnt = index_flag;
|
||||
index_flag = 0x7fffffff;
|
||||
//no buff
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -452,6 +456,11 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
|
|||
write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt);
|
||||
|
||||
cur_recv_cnt = cur_recv_cnt + 1;
|
||||
|
||||
if(cur_recv_cnt > 0xffff)
|
||||
{
|
||||
cur_recv_cnt = 0;
|
||||
}
|
||||
prev_recv_cnt = cur_recv_cnt;
|
||||
|
||||
return length;
|
||||
|
|
@ -475,37 +484,105 @@ static int bcmgenet_gmac_eth_send(void *packet, int length)
|
|||
write32((desc_base + DMA_DESC_ADDRESS_HI), 0);
|
||||
write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat);
|
||||
|
||||
if(++tx_index>= TX_DESCS)
|
||||
tx_index = tx_index + 1;
|
||||
prod_index = prod_index + 1;
|
||||
|
||||
if (prod_index == 0xe000)
|
||||
{
|
||||
write32(MAC_REG + TDMA_PROD_INDEX, 0);
|
||||
prod_index = 0;
|
||||
}
|
||||
|
||||
if (tx_index == 256)
|
||||
{
|
||||
tx_index = 0;
|
||||
}
|
||||
prod_index++;
|
||||
|
||||
/* Start Transmisson */
|
||||
write32(MAC_REG + TDMA_PROD_INDEX, prod_index);
|
||||
|
||||
do {
|
||||
do
|
||||
{
|
||||
cons = read32(MAC_REG + TDMA_CONS_INDEX);
|
||||
} while ((cons & 0xffff) < prod_index && --tries);
|
||||
|
||||
if (!tries)
|
||||
{
|
||||
rt_kprintf("send err! tries is %d\n", tries);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void link_task_entry(void *param)
|
||||
{
|
||||
struct eth_device *eth_device = (struct eth_device *)param;
|
||||
RT_ASSERT(eth_device != RT_NULL);
|
||||
struct rt_eth_dev *dev = ð_dev;
|
||||
//start mdio
|
||||
bcmgenet_mdio_init();
|
||||
//start timer link
|
||||
rt_timer_init(&dev->link_timer, "link_timer",
|
||||
link_irq,
|
||||
NULL,
|
||||
100,
|
||||
RT_TIMER_FLAG_PERIODIC);
|
||||
rt_timer_start(&dev->link_timer);
|
||||
|
||||
//link wait forever
|
||||
rt_sem_take(&link_ack, RT_WAITING_FOREVER);
|
||||
eth_device_linkchange(ð_dev.parent, RT_TRUE); //link up
|
||||
rt_timer_stop(&dev->link_timer);
|
||||
|
||||
//set mac
|
||||
bcmgenet_gmac_write_hwaddr();
|
||||
bcmgenet_gmac_write_hwaddr();
|
||||
|
||||
//check link speed
|
||||
if ((bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 10)) || (bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 11)))
|
||||
{
|
||||
link_speed = 1000;
|
||||
rt_kprintf("Support link mode Speed 1000M\n");
|
||||
}
|
||||
else if ((bcmgenet_mdio_read(1, 0x05) & (1 << 7)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 8)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 9)))
|
||||
{
|
||||
link_speed = 100;
|
||||
rt_kprintf("Support link mode Speed 100M\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
link_speed = 10;
|
||||
rt_kprintf("Support link mode Speed 10M\n");
|
||||
}
|
||||
|
||||
bcmgenet_gmac_eth_start();
|
||||
//irq or poll
|
||||
#ifdef ETH_RX_POLL
|
||||
rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer",
|
||||
eth_rx_irq,
|
||||
NULL,
|
||||
1,
|
||||
RT_TIMER_FLAG_PERIODIC);
|
||||
|
||||
rt_timer_start(&dev->rx_poll_timer);
|
||||
#else
|
||||
rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq");
|
||||
rt_hw_interrupt_umask(ETH_IRQ);
|
||||
#endif
|
||||
link_flag = 1;
|
||||
}
|
||||
|
||||
static rt_err_t bcmgenet_eth_init(rt_device_t device)
|
||||
{
|
||||
struct eth_device *eth_device = (struct eth_device *)device;
|
||||
RT_ASSERT(eth_device != RT_NULL);
|
||||
rt_uint32_t ret = 0;
|
||||
rt_uint32_t hw_reg = 0;
|
||||
struct rt_eth_dev *dev = ð_dev;
|
||||
|
||||
/* Read GENET HW version */
|
||||
rt_uint8_t major = 0;
|
||||
hw_reg = read32(MAC_REG + SYS_REV_CTRL);
|
||||
major = (hw_reg >> 24) & 0x0f;
|
||||
if (major != 6) {
|
||||
if (major != 6)
|
||||
{
|
||||
if (major == 5)
|
||||
major = 4;
|
||||
else if (major == 0)
|
||||
|
|
@ -514,7 +591,6 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
|
|||
rt_kprintf("Uns upported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f);
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
/* set interface */
|
||||
ret = bcmgenet_interface_set();
|
||||
if (ret)
|
||||
|
|
@ -530,21 +606,11 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
|
|||
/* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
|
||||
write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
|
||||
|
||||
bcmgenet_mdio_init();
|
||||
|
||||
bcmgenet_gmac_write_hwaddr();
|
||||
bcmgenet_gmac_write_hwaddr();
|
||||
|
||||
bcmgenet_gmac_eth_start();
|
||||
|
||||
//irq or poll
|
||||
rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer",
|
||||
eth_rx_irq,
|
||||
NULL,
|
||||
1,
|
||||
RT_TIMER_FLAG_PERIODIC);
|
||||
|
||||
rt_timer_start(&dev->rx_poll_timer);
|
||||
link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device,
|
||||
LINK_THREAD_STACK_SIZE,
|
||||
LINK_THREAD_PRIORITY, LINK_THREAD_TIMESLICE);
|
||||
if (link_thread_tid != RT_NULL)
|
||||
rt_thread_startup(link_thread_tid);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
|
@ -554,8 +620,10 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args)
|
|||
switch (cmd)
|
||||
{
|
||||
case NIOCTL_GADDR:
|
||||
if (args) rt_memcpy(args, eth_dev.dev_addr, 6);
|
||||
else return -RT_ERROR;
|
||||
if (args)
|
||||
rt_memcpy(args, eth_dev.dev_addr, 6);
|
||||
else
|
||||
return -RT_ERROR;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
@ -565,15 +633,17 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args)
|
|||
|
||||
rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
|
||||
{
|
||||
rt_uint32_t sendbuf = SEND_DATA_NO_CACHE;
|
||||
rt_uint32_t sendbuf = (rt_uint32_t)SEND_DATA_NO_CACHE;
|
||||
/* lock eth device */
|
||||
if (link_flag == 1)
|
||||
{
|
||||
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
|
||||
//struct rt_eth_dev *dev = (struct rt_eth_dev *) device;
|
||||
pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0);
|
||||
rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len);
|
||||
|
||||
bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len);
|
||||
rt_sem_release(&sem_lock);
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
|
@ -583,16 +653,17 @@ struct pbuf *rt_eth_rx(rt_device_t device)
|
|||
int recv_len = 0;
|
||||
rt_uint32_t addr_point[8];
|
||||
struct pbuf *pbuf = RT_NULL;
|
||||
if (link_flag == 1)
|
||||
{
|
||||
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
|
||||
|
||||
recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]);
|
||||
|
||||
if (recv_len > 0)
|
||||
{
|
||||
pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
|
||||
rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len);
|
||||
}
|
||||
rt_sem_release(&sem_lock);
|
||||
}
|
||||
return pbuf;
|
||||
}
|
||||
|
||||
|
|
@ -601,11 +672,11 @@ int rt_hw_eth_init(void)
|
|||
rt_uint8_t mac_addr[6];
|
||||
|
||||
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
||||
rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO);
|
||||
|
||||
memset(ð_dev, 0, sizeof(eth_dev));
|
||||
memset((void *)SEND_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE));
|
||||
memset((void *)RECV_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE));
|
||||
|
||||
bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]);
|
||||
|
||||
eth_dev.iobase = MAC_REG;
|
||||
|
|
@ -629,9 +700,8 @@ int rt_hw_eth_init(void)
|
|||
eth_dev.parent.eth_tx = rt_eth_tx;
|
||||
eth_dev.parent.eth_rx = rt_eth_rx;
|
||||
|
||||
|
||||
eth_device_init(&(eth_dev.parent), "e0");
|
||||
eth_device_linkchange(ð_dev.parent, RT_TRUE); //linkup the e0 for lwip to check
|
||||
eth_device_linkchange(ð_dev.parent, RT_FALSE); //link down
|
||||
return 0;
|
||||
}
|
||||
INIT_COMPONENT_EXPORT(rt_hw_eth_init);
|
||||
|
|
|
|||
|
|
@ -53,6 +53,17 @@
|
|||
#define MDIO_REG_SHIFT (16)
|
||||
#define MDIO_REG_MASK (0x1f)
|
||||
|
||||
#define GENET_INTRL2_OFF (0x0200)
|
||||
#define GENET_INTRL2_CPU_STAT (GENET_INTRL2_OFF + 0x00)
|
||||
#define GENET_INTRL2_CPU_CLEAR (GENET_INTRL2_OFF + 0x08)
|
||||
#define GENET_INTRL2_CPU_STAT_MASK (GENET_INTRL2_OFF + 0x0c)
|
||||
#define GENET_INTRL2_CPU_SET_MASK (GENET_INTRL2_OFF + 0x10)
|
||||
#define GENET_INTRL2_CPU_CLEAR_MASK (GENET_INTRL2_OFF + 0x14)
|
||||
#define GENET_IRQ_MDIO_ERROR BIT(24)
|
||||
#define GENET_IRQ_MDIO_DONE BIT(23)
|
||||
#define GENET_IRQ_TXDMA_DONE BIT(16)
|
||||
#define GENET_IRQ_RXDMA_DONE BIT(13)
|
||||
|
||||
#define CMD_TX_EN BIT(0)
|
||||
#define CMD_RX_EN BIT(1)
|
||||
#define UMAC_SPEED_10 (0)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,368 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-28 bigmagic first version
|
||||
*/
|
||||
|
||||
#include "drv_i2c.h"
|
||||
#include "drv_gpio.h"
|
||||
#include "raspi4.h"
|
||||
#include "mbox.h"
|
||||
|
||||
/*
|
||||
* (3.3v) -1 2-
|
||||
* (SDA1/SDA3) -3 4-
|
||||
* (SCL1/SCL3) -5 6-
|
||||
* (SDA3) -7 8-
|
||||
* -9 10-
|
||||
* -11 12-
|
||||
* -13 14-
|
||||
* -15 16-
|
||||
* -17 18-
|
||||
* -19 20-
|
||||
* (SCL4) -21 22-
|
||||
* -23 24- (SDA4)
|
||||
* -25 26- (SCL4)
|
||||
* -27 28-
|
||||
* (SCL3) -29 30-
|
||||
* (SDA4) -31 32-
|
||||
*/
|
||||
|
||||
#define DBG_TAG "drv.i2c"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
struct raspi_i2c_hw_config
|
||||
{
|
||||
rt_uint32_t bsc_num;
|
||||
rt_uint32_t bsc_rate;
|
||||
rt_uint32_t bsc_address;
|
||||
rt_uint32_t sda_pin;
|
||||
rt_uint32_t scl_pin;
|
||||
rt_uint32_t sda_mode;
|
||||
rt_uint32_t scl_mode;
|
||||
};
|
||||
|
||||
rt_uint8_t i2c_read_or_write(volatile rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len, rt_uint8_t flag)
|
||||
{
|
||||
rt_uint32_t status;
|
||||
rt_uint32_t remaining = len;
|
||||
rt_uint32_t i = 0;
|
||||
rt_uint8_t reason = I2C_REASON_OK;
|
||||
|
||||
/* Clear FIFO */
|
||||
BSC_C(base) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
|
||||
/* Clear Status */
|
||||
BSC_S(base) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
|
||||
/* Set Data Length */
|
||||
BSC_DLEN(base) = len;
|
||||
if (flag)
|
||||
{
|
||||
/* Start read */
|
||||
BSC_C(base) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ;
|
||||
/* wait for transfer to complete */
|
||||
while (!(BSC_S(base) & BSC_S_DONE))
|
||||
{
|
||||
/* we must empty the FIFO as it is populated and not use any delay */
|
||||
while (remaining && (BSC_S(base) & BSC_S_RXD))
|
||||
{
|
||||
/* Read from FIFO, no barrier */
|
||||
buf[i] = BSC_FIFO(base);
|
||||
i++;
|
||||
remaining--;
|
||||
}
|
||||
}
|
||||
/* transfer has finished - grab any remaining stuff in FIFO */
|
||||
while (remaining && (BSC_S(base) & BSC_S_RXD))
|
||||
{
|
||||
/* Read from FIFO, no barrier */
|
||||
buf[i] = BSC_FIFO(base);
|
||||
i++;
|
||||
remaining--;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("i2c%d write start", flag);
|
||||
/* pre populate FIFO with max buffer */
|
||||
while (remaining && (i < BSC_FIFO_SIZE))
|
||||
{
|
||||
BSC_FIFO(base) = buf[i];
|
||||
i++;
|
||||
remaining--;
|
||||
}
|
||||
|
||||
/* Enable device and start transfer */
|
||||
BSC_C(base) = BSC_C_I2CEN | BSC_C_ST;
|
||||
|
||||
/* Transfer is over when BCM2835_BSC_S_DONE */
|
||||
while (!(BSC_S(base) & BSC_S_DONE))
|
||||
{
|
||||
while (remaining && (BSC_S(base) & BSC_S_TXD))
|
||||
{
|
||||
/* Write to FIFO */
|
||||
BSC_FIFO(base) = buf[i];
|
||||
i++;
|
||||
remaining--;
|
||||
}
|
||||
}
|
||||
LOG_D("i2c%d write end", flag);
|
||||
}
|
||||
|
||||
status = BSC_S(base);
|
||||
if (status & BSC_S_ERR)
|
||||
{
|
||||
reason = I2C_REASON_ERROR_NACK;
|
||||
}
|
||||
else if (status & BSC_S_CLKT)
|
||||
{
|
||||
reason = I2C_REASON_ERROR_CLKT;
|
||||
}
|
||||
else if (remaining)
|
||||
{
|
||||
reason = I2C_REASON_ERROR_DATA;
|
||||
}
|
||||
BSC_C(base) |= (BSC_S_DONE & BSC_S_DONE);
|
||||
|
||||
return reason;
|
||||
}
|
||||
|
||||
static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
|
||||
struct rt_i2c_msg msgs[],
|
||||
rt_uint32_t num)
|
||||
{
|
||||
rt_size_t i;
|
||||
rt_uint8_t reason;
|
||||
RT_ASSERT(bus != RT_NULL);
|
||||
|
||||
struct raspi_i2c_hw_config *i2c_hw_config = (struct raspi_i2c_hw_config*)(bus->priv);
|
||||
|
||||
//Slave Address
|
||||
BSC_A(i2c_hw_config->bsc_address) = msgs->addr;
|
||||
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
if (msgs[i].flags & RT_I2C_RD)
|
||||
reason = i2c_read_or_write(i2c_hw_config->bsc_address, msgs->buf, msgs->len, 1);
|
||||
else
|
||||
reason = i2c_read_or_write(i2c_hw_config->bsc_address, msgs->buf, msgs->len, 0);
|
||||
}
|
||||
return (reason == 0)? i : 0;
|
||||
}
|
||||
|
||||
static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
|
||||
struct rt_i2c_msg msgs[],
|
||||
rt_uint32_t num)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
|
||||
rt_uint32_t cmd,
|
||||
rt_uint32_t arg)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
static rt_err_t raspi_i2c_configure(struct raspi_i2c_hw_config *cfg)
|
||||
{
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
rt_uint32_t apb_clock = 0;
|
||||
prev_raspi_pin_mode(cfg->sda_pin, cfg->sda_mode);//sda
|
||||
prev_raspi_pin_mode(cfg->scl_pin, cfg->scl_mode);//scl
|
||||
/* use 0xFFFE mask to limit a max value and round down any odd number */
|
||||
apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID);
|
||||
rt_uint32_t divider = (apb_clock / cfg->bsc_rate) & 0xFFFE;
|
||||
|
||||
BSC_DIV(cfg->bsc_address) = (rt_uint16_t)divider;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
|
||||
{
|
||||
.master_xfer = raspi_i2c_mst_xfer,
|
||||
.slave_xfer = raspi_i2c_slv_xfer,
|
||||
.i2c_bus_control = raspi_i2c_bus_control,
|
||||
};
|
||||
|
||||
#if defined (BSP_USING_I2C0)
|
||||
#define I2C0_BUS_NAME "i2c0"
|
||||
static struct raspi_i2c_hw_config hw_device0 =
|
||||
{
|
||||
.bsc_num = 0,
|
||||
.bsc_rate = 100000,//100k
|
||||
.bsc_address = BSC0_BASE,
|
||||
.sda_pin = GPIO_PIN_0,
|
||||
.scl_pin = GPIO_PIN_1,
|
||||
.sda_mode = ALT0,
|
||||
.scl_mode = ALT0,
|
||||
};
|
||||
|
||||
struct rt_i2c_bus_device device0 =
|
||||
{
|
||||
.ops = &raspi_i2c_ops,
|
||||
.priv = (void *)&hw_device0,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_I2C1)
|
||||
#define I2C1_BUS_NAME "i2c1"
|
||||
static struct raspi_i2c_hw_config hw_device1 =
|
||||
{
|
||||
.bsc_num = 1,
|
||||
.bsc_rate = 100000,//100k
|
||||
.bsc_address = BSC1_BASE,
|
||||
.sda_pin = GPIO_PIN_2,
|
||||
.scl_pin = GPIO_PIN_3,
|
||||
.sda_mode = ALT0,
|
||||
.scl_mode = ALT0,
|
||||
};
|
||||
|
||||
struct rt_i2c_bus_device device1 =
|
||||
{
|
||||
.ops = &raspi_i2c_ops,
|
||||
.priv = (void *)&hw_device1,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_I2C3)
|
||||
#define I2C3_BUS_NAME "i2c3"
|
||||
static struct raspi_i2c_hw_config hw_device3 =
|
||||
{
|
||||
.bsc_num = 3,
|
||||
.bsc_rate = 100000,//100k
|
||||
.bsc_address = BSC3_BASE,
|
||||
#ifndef BSP_USING_I2C3_0
|
||||
.sda_pin = GPIO_PIN_2,
|
||||
.scl_pin = GPIO_PIN_3,
|
||||
#else
|
||||
.sda_pin = GPIO_PIN_4,
|
||||
.scl_pin = GPIO_PIN_5,
|
||||
#endif
|
||||
.sda_mode = ALT5,
|
||||
.scl_mode = ALT5,
|
||||
};
|
||||
|
||||
struct rt_i2c_bus_device device3 =
|
||||
{
|
||||
.ops = &raspi_i2c_ops,
|
||||
.priv = (void *)&hw_device3,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_I2C4)
|
||||
#define I2C4_BUS_NAME "i2c4"
|
||||
static struct raspi_i2c_hw_config hw_device4 =
|
||||
{
|
||||
.bsc_num = 4,
|
||||
.bsc_rate = 100000,//100k
|
||||
.bsc_address = BSC4_BASE,
|
||||
#ifdef BSP_USING_I2C4_0
|
||||
.sda_pin = GPIO_PIN_6,
|
||||
.scl_pin = GPIO_PIN_7,
|
||||
#else
|
||||
.sda_pin = GPIO_PIN_8,
|
||||
.scl_pin = GPIO_PIN_9,
|
||||
#endif
|
||||
.sda_mode = ALT5,
|
||||
.scl_mode = ALT5,
|
||||
};
|
||||
|
||||
struct rt_i2c_bus_device device4 =
|
||||
{
|
||||
.ops = &raspi_i2c_ops,
|
||||
.priv = (void *)&hw_device4,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_I2C5)
|
||||
#define I2C5_BUS_NAME "i2c5"
|
||||
static struct raspi_i2c_hw_config hw_device5 =
|
||||
{
|
||||
.bsc_num = 5,
|
||||
.bsc_rate = 100000,//100k
|
||||
.bsc_address = BSC5_BASE,
|
||||
#ifdef BSP_USING_I2C5_0
|
||||
.sda_pin = GPIO_PIN_10,
|
||||
.scl_pin = GPIO_PIN_11,
|
||||
#else
|
||||
.sda_pin = GPIO_PIN_12,
|
||||
.scl_pin = GPIO_PIN_13,
|
||||
#endif
|
||||
.sda_mode = ALT5,
|
||||
.scl_mode = ALT5,
|
||||
};
|
||||
|
||||
struct rt_i2c_bus_device device5 =
|
||||
{
|
||||
.ops = &raspi_i2c_ops,
|
||||
.priv = (void *)&hw_device5,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_I2C6)
|
||||
#define I2C6_BUS_NAME "i2c6"
|
||||
static struct raspi_i2c_hw_config hw_device6 =
|
||||
{
|
||||
.bsc_num = 6,
|
||||
.bsc_rate = 100000,//100k
|
||||
.bsc_address = BSC6_BASE,
|
||||
#ifdef BSP_USING_I2C5_0
|
||||
.sda_pin = GPIO_PIN_0,
|
||||
.scl_pin = GPIO_PIN_1,
|
||||
#else
|
||||
.sda_pin = GPIO_PIN_22,
|
||||
.scl_pin = GPIO_PIN_23,
|
||||
#endif
|
||||
.sda_mode = ALT5,
|
||||
.scl_mode = ALT5,
|
||||
};
|
||||
|
||||
struct rt_i2c_bus_device device6 =
|
||||
{
|
||||
.ops = &raspi_i2c_ops,
|
||||
.priv = (void *)&hw_device6,
|
||||
};
|
||||
#endif
|
||||
|
||||
int rt_hw_i2c_init(void)
|
||||
{
|
||||
#if defined(BSP_USING_I2C0)
|
||||
raspi_i2c_configure(&hw_device0);
|
||||
rt_i2c_bus_device_register(&device0, I2C0_BUS_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C1)
|
||||
raspi_i2c_configure(&hw_device1);
|
||||
rt_i2c_bus_device_register(&device1, I2C1_BUS_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C3)
|
||||
raspi_i2c_configure(&hw_device3);
|
||||
rt_i2c_bus_device_register(&device3, I2C3_BUS_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C4)
|
||||
raspi_i2c_configure(&hw_device4);
|
||||
rt_i2c_bus_device_register(&device4, I2C4_BUS_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C5)
|
||||
raspi_i2c_configure(&hw_device5);
|
||||
rt_i2c_bus_device_register(&device5, I2C5_BUS_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C6)
|
||||
raspi_i2c_configure(&hw_device6);
|
||||
rt_i2c_bus_device_register(&device6, I2C6_BUS_NAME);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
INIT_DEVICE_EXPORT(rt_hw_i2c_init);
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-28 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_I2C_H__
|
||||
#define __DRV_I2C_H__
|
||||
|
||||
#include <rthw.h>
|
||||
|
||||
#define BSC_C(BASE) __REG32(BASE + 0x0000) /* BSC Master Control */
|
||||
#define BSC_S(BASE) __REG32(BASE + 0x0004) /* BSC Master Status */
|
||||
#define BSC_DLEN(BASE) __REG32(BASE + 0x0008) /* BSC Master Data Length */
|
||||
#define BSC_A(BASE) __REG32(BASE + 0x000c) /* BSC Master Slave Address */
|
||||
#define BSC_FIFO(BASE) __REG32(BASE + 0x0010) /* BSC Master Data FIFO */
|
||||
#define BSC_DIV(BASE) __REG32(BASE + 0x0014) /* BSC Master Clock Divider */
|
||||
#define BSC_DEL(BASE) __REG32(BASE + 0x0018) /* BSC Master Data Delay */
|
||||
#define BSC_CLKT(BASE) __REG32(BASE + 0x001c) /* BSC Master Clock Stretch Timeout */
|
||||
|
||||
/* Register masks for C Register */
|
||||
#define BSC_C_I2CEN (0x00008000) /* I2C Enable, 0 = disabled, 1 = enabled */
|
||||
#define BSC_C_INTR (0x00000400) /* Interrupt on RX */
|
||||
#define BSC_C_INTT (0x00000200) /* Interrupt on TX */
|
||||
#define BSC_C_INTD (0x00000100) /* Interrupt on DONE */
|
||||
#define BSC_C_ST (0x00000080) /* Start transfer, 1 = Start a new transfer */
|
||||
#define BSC_C_CLEAR_1 (0x00000020) /* Clear FIFO Clear */
|
||||
#define BSC_C_CLEAR_2 (0x00000010) /* Clear FIFO Clear */
|
||||
#define BSC_C_READ (0x00000001) /* Read transfer */
|
||||
|
||||
/* Register masks for S Register */
|
||||
#define BSC_S_CLKT (0x00000200) /* Clock stretch timeout */
|
||||
#define BSC_S_ERR (0x00000100) /* ACK error */
|
||||
#define BSC_S_RXF (0x00000080) /* RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
|
||||
#define BSC_S_TXE (0x00000040) /* TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
|
||||
#define BSC_S_RXD (0x00000020) /* RXD FIFO contains data */
|
||||
#define BSC_S_TXD (0x00000010) /* TXD FIFO can accept data */
|
||||
#define BSC_S_RXR (0x00000008) /* RXR FIFO needs reading (full) */
|
||||
#define BSC_S_TXW (0x00000004) /* TXW FIFO needs writing (full) */
|
||||
#define BSC_S_DONE (0x00000002) /* Transfer DONE */
|
||||
#define BSC_S_TA (0x00000001) /* Transfer Active */
|
||||
|
||||
#define BSC_FIFO_SIZE (16) /* BSC FIFO size */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_REASON_OK = 0x00, /* Success */
|
||||
I2C_REASON_ERROR_NACK = 0x01, /* Received a NACK */
|
||||
I2C_REASON_ERROR_CLKT = 0x02, /* Received Clock Stretch Timeout */
|
||||
I2C_REASON_ERROR_DATA = 0x04 /* Not all data is sent / received */
|
||||
} i2c_reason_codes;
|
||||
|
||||
int rt_hw_i2c_init(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -103,8 +103,8 @@ rt_err_t sd_int(struct sdhci_pdata_t * pdat, rt_uint32_t mask)
|
|||
{
|
||||
write32(pdat->virt + EMMC_INTERRUPT, r);
|
||||
//qemu maybe can not use sdcard
|
||||
//rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS));
|
||||
//return -RT_ETIMEOUT;
|
||||
rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS));
|
||||
return -RT_ETIMEOUT;
|
||||
}
|
||||
else if (r & INT_ERROR_MASK)
|
||||
{
|
||||
|
|
@ -552,9 +552,8 @@ static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat)
|
|||
|
||||
// Clear control2
|
||||
write32(pdat->virt + EMMC_CONTROL2, 0);
|
||||
|
||||
// Get the base clock rate
|
||||
mmc_base_clock = bcm271x_mbox_clock_get_rate(12);
|
||||
// Get the base clock rate //12
|
||||
mmc_base_clock = bcm271x_mbox_clock_get_rate(EMMC_CLK_ID);
|
||||
if(mmc_base_clock == 0)
|
||||
{
|
||||
rt_kprintf("EMMC: assuming clock rate to be 100MHz\n");
|
||||
|
|
@ -590,7 +589,6 @@ int raspi_sdmmc_init(void)
|
|||
struct rt_mmcsd_host * host = RT_NULL;
|
||||
struct sdhci_pdata_t * pdat = RT_NULL;
|
||||
struct sdhci_t * sdhci = RT_NULL;
|
||||
|
||||
#ifdef BSP_USING_SDIO0
|
||||
host = mmcsd_alloc_host();
|
||||
if (!host)
|
||||
|
|
@ -598,7 +596,6 @@ int raspi_sdmmc_init(void)
|
|||
rt_kprintf("alloc host failed");
|
||||
goto err;
|
||||
}
|
||||
|
||||
sdhci = rt_malloc(sizeof(struct sdhci_t));
|
||||
if (!sdhci)
|
||||
{
|
||||
|
|
@ -608,17 +605,15 @@ int raspi_sdmmc_init(void)
|
|||
rt_memset(sdhci, 0, sizeof(struct sdhci_t));
|
||||
|
||||
virt = MMC2_BASE_ADDR;
|
||||
|
||||
pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t));
|
||||
RT_ASSERT(pdat != RT_NULL);
|
||||
|
||||
pdat->virt = (rt_uint32_t)virt;
|
||||
reset_emmc(pdat);
|
||||
|
||||
sdhci->name = "sd0";
|
||||
sdhci->voltages = VDD_33_34;
|
||||
sdhci->width = MMCSD_BUSWIDTH_4;
|
||||
sdhci->clock = 250 * 1000 * 1000;
|
||||
sdhci->clock = 1000 * 1000 * 1000;
|
||||
sdhci->removeable = RT_TRUE;
|
||||
|
||||
sdhci->detect = sdhci_detect;
|
||||
|
|
@ -634,10 +629,9 @@ int raspi_sdmmc_init(void)
|
|||
host->max_seg_size = 2048;
|
||||
host->max_dma_segs = 10;
|
||||
host->max_blk_size = 512;
|
||||
host->max_blk_count = 4096;
|
||||
host->max_blk_count = 1;
|
||||
|
||||
host->private_data = sdhci;
|
||||
|
||||
write32((pdat->virt + EMMC_IRPT_EN),0xffffffff);
|
||||
write32((pdat->virt + EMMC_IRPT_MASK),0xffffffff);
|
||||
#ifdef RT_MMCSD_DBG
|
||||
|
|
|
|||
|
|
@ -16,8 +16,7 @@
|
|||
|
||||
#ifdef RT_USING_SPI
|
||||
|
||||
#define RPI_CORE_CLK_HZ (250000000)
|
||||
#define BSP_SPI_MAX_HZ (30* 1000 *1000)
|
||||
#define RPI_CORE_CLK_HZ (500 * 1000 * 1000)
|
||||
#define SPITIMEOUT 0x0FFF
|
||||
|
||||
static rt_uint8_t raspi_byte_reverse_table[] =
|
||||
|
|
@ -76,35 +75,35 @@ static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_
|
|||
{
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
rt_uint16_t divider;
|
||||
struct raspi_spi_device* hw_config = (struct raspi_spi_device *)(device->parent.user_data);
|
||||
struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config;
|
||||
// spi clear fifo
|
||||
SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
|
||||
SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
|
||||
if(cfg->mode & RT_SPI_CPOL)
|
||||
{
|
||||
SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPOL;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CPOL;
|
||||
}
|
||||
|
||||
if(cfg->mode & RT_SPI_CPHA)
|
||||
{
|
||||
SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPHA;
|
||||
}else
|
||||
{
|
||||
SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CPHA;
|
||||
}
|
||||
|
||||
if(cfg->mode & RT_SPI_CS_HIGH)
|
||||
{
|
||||
SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH;
|
||||
}
|
||||
|
||||
//set clk
|
||||
if (cfg->max_hz > BSP_SPI_MAX_HZ)
|
||||
cfg->max_hz = BSP_SPI_MAX_HZ;
|
||||
|
||||
divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz);
|
||||
divider &= 0xFFFE;
|
||||
|
||||
SPI_REG_CLK(hwcfg->hw_base) = divider;
|
||||
|
||||
else
|
||||
{
|
||||
SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CSPOL_HIGH;
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
|
@ -120,13 +119,6 @@ static rt_err_t spi_transfernb(struct raspi_spi_hw_config *hwcfg, rt_uint8_t* tb
|
|||
{
|
||||
rt_uint32_t TXCnt=0;
|
||||
rt_uint32_t RXCnt=0;
|
||||
|
||||
/* Clear TX and RX fifos */
|
||||
SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
|
||||
|
||||
/* Set TA = 1 */
|
||||
SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_TA;
|
||||
|
||||
/* Use the FIFO's to reduce the interbyte times */
|
||||
while ((TXCnt < len) || (RXCnt < len))
|
||||
{
|
||||
|
|
@ -145,9 +137,6 @@ static rt_err_t spi_transfernb(struct raspi_spi_hw_config *hwcfg, rt_uint8_t* tb
|
|||
}
|
||||
/* Wait for DONE to be set */
|
||||
while (!(SPI_REG_CS(hwcfg->hw_base) & SPI_CS_DONE));
|
||||
/* Set TA = 0, and also set the barrier */
|
||||
SPI_REG_CS(hwcfg->hw_base) |= (0 & SPI_CS_TA);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
|
@ -159,31 +148,54 @@ static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_me
|
|||
RT_ASSERT(device->bus != RT_NULL);
|
||||
RT_ASSERT(device->parent.user_data != RT_NULL);
|
||||
RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
|
||||
|
||||
struct rt_spi_configuration config = device->config;
|
||||
struct raspi_spi_device * hw_config = (struct raspi_spi_device *)device->parent.user_data;
|
||||
GPIO_PIN cs_pin = (GPIO_PIN)hw_config->cs_pin;
|
||||
struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config;
|
||||
|
||||
//mode MSB
|
||||
if (config.mode & RT_SPI_MSB)
|
||||
{
|
||||
flag = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
flag = 1;
|
||||
}
|
||||
|
||||
if (message->cs_take)
|
||||
else
|
||||
{
|
||||
(config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 1):prev_raspi_pin_write(cs_pin, 0);
|
||||
flag = 0;
|
||||
}
|
||||
|
||||
//max_hz
|
||||
if(config.max_hz == 0)
|
||||
{
|
||||
SPI_REG_CLK(hwcfg->hw_base) = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPI_REG_CLK(hwcfg->hw_base) = (RPI_CORE_CLK_HZ / (config.max_hz));
|
||||
}
|
||||
|
||||
//cs_pin spi0.0
|
||||
if(cs_pin == GPIO_PIN_8)
|
||||
{
|
||||
SPI_REG_CS(hwcfg->hw_base) &= (~(3 << 0));
|
||||
}
|
||||
else if(cs_pin == GPIO_PIN_7)//spi0.1
|
||||
{
|
||||
SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_1;
|
||||
}
|
||||
|
||||
//Clear TX and RX fifos
|
||||
SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
|
||||
if (message->cs_take)
|
||||
{
|
||||
SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_TA;
|
||||
}
|
||||
res = spi_transfernb(hwcfg, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, flag);
|
||||
if (message->cs_release)
|
||||
{
|
||||
(config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 0):prev_raspi_pin_write(cs_pin, 1);
|
||||
//Set TA = 0, and also set the barrier
|
||||
SPI_REG_CS(hwcfg->hw_base) &= (~SPI_CS_TA);
|
||||
}
|
||||
|
||||
if (res != RT_EOK)
|
||||
return RT_ERROR;
|
||||
|
||||
|
|
@ -212,18 +224,6 @@ rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg)
|
|||
#endif
|
||||
//clear rx and tx
|
||||
SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX);
|
||||
//enable chip select
|
||||
#if defined (BSP_USING_SPI0_DEVICE0)
|
||||
SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_0;
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_SPI0_DEVICE1)
|
||||
SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_1;
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1)
|
||||
HWREG32(SPI_REG_CS(hwcfg->hw_base)) |= (SPI_CS_CHIP_SELECT_0 | SPI_CS_CHIP_SELECT_1);
|
||||
#endif
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
|
@ -273,6 +273,7 @@ struct raspi_spi_device raspi_spi0_device1 =
|
|||
.device_name = SPI0_DEVICE1_NAME,
|
||||
.spi_bus = &spi0_bus,
|
||||
.spi_device = &spi0_device1,
|
||||
.spi_hw_config = &raspi_spi0_hw,
|
||||
.cs_pin = GPIO_PIN_7,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -63,15 +63,22 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
|
|||
AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */
|
||||
AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */
|
||||
AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */
|
||||
AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
|
||||
AUX_MU_BAUD_REG(uart->hw_base) = 541; /* 115200 = system clock 500MHz / (8 * (baud + 1)), baud = 541 */
|
||||
AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
if(uart->hw_base == UART0_BASE)
|
||||
{
|
||||
#ifndef BSP_USING_BULETOOTH
|
||||
prev_raspi_pin_mode(GPIO_PIN_14, ALT0);
|
||||
prev_raspi_pin_mode(GPIO_PIN_15, ALT0);
|
||||
#else
|
||||
prev_raspi_pin_mode(GPIO_PIN_30, ALT3);
|
||||
prev_raspi_pin_mode(GPIO_PIN_31, ALT3);
|
||||
prev_raspi_pin_mode(GPIO_PIN_32, ALT3);
|
||||
prev_raspi_pin_mode(GPIO_PIN_33, ALT3);
|
||||
#endif
|
||||
}
|
||||
|
||||
if(uart->hw_base == UART3_BASE)
|
||||
|
|
@ -92,13 +99,21 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
|
|||
prev_raspi_pin_mode(GPIO_PIN_13, ALT4);
|
||||
}
|
||||
|
||||
PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
|
||||
PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
|
||||
PL011_REG_IMSC(uart->hw_base) = 0; /* mask all interrupt */
|
||||
PL011_REG_ICR(uart->hw_base) = 0x7ff; /* clear all interrupt */
|
||||
//PL011 clock 480MHz 480x10^6/baudrate/16
|
||||
PL011_REG_IBRD(uart->hw_base) = ibrd;
|
||||
PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
|
||||
PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
|
||||
PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
|
||||
|
||||
#ifdef BSP_USING_BULETOOTH
|
||||
PL011_REG_IFLS(uart->hw_base) = 0x08;
|
||||
PL011_REG_LCRH(uart->hw_base) = 0x70;
|
||||
PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE | PL011_CR_RTS;
|
||||
#else
|
||||
PL011_REG_IFLS(uart->hw_base) = 0x0;
|
||||
PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;
|
||||
PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;
|
||||
#endif
|
||||
PL011_REG_IMSC(uart->hw_base) = 0;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
if not (GetDepend('BSP_USING_HDMI_DISPLAY') or GetDepend('BSP_USING_DSI_DISPLAY')):
|
||||
SrcRemove(src, ['drv_hdmi.c'])
|
||||
if not GetDepend('BSP_USING_ILI9486'):
|
||||
SrcRemove(src, ['drv_ili9486.c'])
|
||||
if not GetDepend('USING_LCD_CONSOLE'):
|
||||
SrcRemove(src, ['lcd_console.c'])
|
||||
|
||||
group = DefineGroup('drv_lcd', src, depend = ['BSP_USING_LCD'], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -13,10 +13,14 @@
|
|||
#include "mbox.h"
|
||||
#include "drv_hdmi.h"
|
||||
|
||||
#ifdef BSP_USING_HDMI
|
||||
#ifdef USING_LCD_CONSOLE
|
||||
#include "lcd_console.h"
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_HDMI_DISPLAY) || defined(BSP_USING_DSI_DISPLAY)
|
||||
#define LCD_WIDTH (800)
|
||||
#define LCD_HEIGHT (480)
|
||||
#define LCD_DEPTH (32)
|
||||
#define LCD_DEPTH (4)
|
||||
#define LCD_BPP (32)
|
||||
|
||||
#define TAG_ALLOCATE_BUFFER 0x00040001
|
||||
|
|
@ -84,6 +88,9 @@ rt_size_t hdmi_fb_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size)
|
|||
|
||||
rt_size_t hdmi_fb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
|
||||
{
|
||||
#ifdef USING_LCD_CONSOLE
|
||||
fb_print((char*)buffer);
|
||||
#endif
|
||||
return size;
|
||||
}
|
||||
|
||||
|
|
@ -105,7 +112,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args)
|
|||
|
||||
RT_ASSERT(info != RT_NULL);
|
||||
info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888;
|
||||
info->bits_per_pixel= LCD_DEPTH;
|
||||
info->bits_per_pixel= 32;
|
||||
info->width = lcd->width;
|
||||
info->height = lcd->height;
|
||||
info->framebuffer = lcd->fb;
|
||||
|
|
@ -285,12 +292,18 @@ void *bcm271x_mbox_fb_alloc(int width, int height, int bpp, int nrender)
|
|||
mbox[34] = TAG_END;
|
||||
|
||||
mbox_call(8, MMU_DISABLE);
|
||||
|
||||
return (void *)((rt_uint32_t)(mbox[5] & 0x3fffffff));
|
||||
}
|
||||
|
||||
int hdmi_fb_init(void)
|
||||
{
|
||||
_hdmi.fb = (rt_uint8_t *)bcm271x_mbox_fb_alloc(LCD_WIDTH, LCD_HEIGHT, LCD_BPP, 1);
|
||||
if(_hdmi.fb == RT_NULL)
|
||||
{
|
||||
rt_kprintf("init dsi or hdmi err!\n");
|
||||
return 0;
|
||||
}
|
||||
bcm271x_mbox_fb_setoffset(0, 0);
|
||||
bcm271x_mbox_fb_set_porder(0);
|
||||
_hdmi.width = LCD_WIDTH;
|
||||
|
|
@ -299,8 +312,9 @@ int hdmi_fb_init(void)
|
|||
_hdmi.pitch = 0;
|
||||
_hdmi.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888;
|
||||
|
||||
rt_memset(_hdmi.fb, 0, LCD_WIDTH*LCD_HEIGHT*(LCD_BPP/8));
|
||||
//rt_kprintf("_hdmi.fb is %p\n", _hdmi.fb);
|
||||
rt_hdmi_fb_device_init(&_hdmi, "lcd");
|
||||
rt_hdmi_fb_device_init(&_hdmi, "hdmi");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,381 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-08 bigmagic first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <raspi4.h>
|
||||
#include <drv_spi.h>
|
||||
#include "drv_ili9486.h"
|
||||
|
||||
#ifdef USING_LCD_CONSOLE
|
||||
#include "lcd_console.h"
|
||||
#endif
|
||||
|
||||
//http://www.lcdwiki.com/MHS-3.5inch_RPi_Display
|
||||
#define LCD_DEVICE_NAME ("spi0.0")
|
||||
|
||||
#define LCD_SPI_SEND_FAST
|
||||
//waveshare
|
||||
#define LCD_SCREEN_WIDTH (320)
|
||||
#define LCD_SCREEN_HEIGHT (480)
|
||||
|
||||
#define LCD_RESET_PIN (25)
|
||||
#define LCD_RS_PIN (24)
|
||||
|
||||
#define LCD_SPI_FREQ_MAX (125*1000*1000)
|
||||
|
||||
uint16_t LCD_HEIGHT = LCD_SCREEN_HEIGHT;
|
||||
uint16_t LCD_WIDTH = LCD_SCREEN_WIDTH;
|
||||
|
||||
#define SCREEN_VERTICAL_1 (0)
|
||||
#define SCREEN_HORIZONTAL_1 (1)
|
||||
#define SCREEN_VERTICAL_2 (2)
|
||||
#define SCREEN_HORIZONTAL_2 (3)
|
||||
|
||||
struct rt_semaphore lcd_spi_lock;
|
||||
struct rt_semaphore lcd_lock;
|
||||
|
||||
//rgb565 lcd buffer
|
||||
uint16_t _lcd_buffer[LCD_SCREEN_WIDTH * LCD_SCREEN_HEIGHT];
|
||||
uint16_t send_buffer[LCD_SCREEN_WIDTH * LCD_SCREEN_HEIGHT];
|
||||
|
||||
static struct rt_spi_device *lcd_dev;
|
||||
|
||||
static inline void send_cmd(void)
|
||||
{
|
||||
rt_pin_write(LCD_RS_PIN, PIN_LOW);
|
||||
}
|
||||
|
||||
static inline void send_data(void)
|
||||
{
|
||||
rt_pin_write(LCD_RS_PIN, PIN_HIGH);
|
||||
}
|
||||
|
||||
void writeData16(rt_uint16_t data)
|
||||
{
|
||||
rt_uint8_t send_data[2];
|
||||
send_data[1] = data & 0x00FF;
|
||||
send_data[0] = ((data >> 8) & 0x00FF);
|
||||
rt_spi_transfer(lcd_dev, &send_data[0], RT_NULL, 2);
|
||||
}
|
||||
|
||||
void writeData(void* dev,rt_uint8_t data)
|
||||
{
|
||||
writeData16((rt_uint16_t)(data));
|
||||
}
|
||||
|
||||
void writeCommand(void* dev, rt_uint8_t cmd)
|
||||
{
|
||||
send_cmd();
|
||||
writeData16((rt_uint16_t)(cmd));
|
||||
send_data();
|
||||
}
|
||||
|
||||
void lcd_write_commmand(rt_uint8_t cmd)
|
||||
{
|
||||
writeCommand(lcd_dev, cmd);
|
||||
}
|
||||
|
||||
void lcd_write_data(rt_uint8_t data)
|
||||
{
|
||||
writeData(lcd_dev, data);
|
||||
}
|
||||
|
||||
/*Ser rotation of the screen - changes x0 and y0*/
|
||||
static inline void lcd_set_rotation(uint8_t rotation)
|
||||
{
|
||||
writeCommand(lcd_dev, 0x36);
|
||||
rt_thread_mdelay(100);
|
||||
|
||||
switch(rotation) {
|
||||
case SCREEN_VERTICAL_1:
|
||||
writeData(lcd_dev, 0x48);
|
||||
LCD_WIDTH = 320;
|
||||
LCD_HEIGHT = 480;
|
||||
break;
|
||||
case SCREEN_HORIZONTAL_1:
|
||||
writeData(lcd_dev, 0x28);
|
||||
LCD_WIDTH = 480;
|
||||
LCD_HEIGHT = 320;
|
||||
break;
|
||||
case SCREEN_VERTICAL_2:
|
||||
writeData(lcd_dev, 0x98);
|
||||
LCD_WIDTH = 320;
|
||||
LCD_HEIGHT = 480;
|
||||
break;
|
||||
case SCREEN_HORIZONTAL_2:
|
||||
writeData(lcd_dev, 0xF8);
|
||||
LCD_WIDTH = 480;
|
||||
LCD_HEIGHT = 320;
|
||||
break;
|
||||
default:
|
||||
//EXIT IF SCREEN ROTATION NOT VALID!
|
||||
break;
|
||||
}
|
||||
|
||||
if((rotation == SCREEN_VERTICAL_1) || (rotation == SCREEN_VERTICAL_2))
|
||||
{
|
||||
lcd_write_commmand(0x2A);
|
||||
lcd_write_data(0x00);
|
||||
lcd_write_data(0x00);
|
||||
lcd_write_data(0x01);
|
||||
lcd_write_data(0x3F);
|
||||
|
||||
lcd_write_commmand(0x2B);
|
||||
lcd_write_data(0x00);
|
||||
lcd_write_data(0x00);
|
||||
lcd_write_data(0x01);
|
||||
lcd_write_data(0xE0);
|
||||
}
|
||||
|
||||
if((rotation == SCREEN_HORIZONTAL_1) || (rotation == SCREEN_HORIZONTAL_2))
|
||||
{
|
||||
lcd_write_commmand(0x2B);
|
||||
lcd_write_data(0x00);
|
||||
lcd_write_data(0x00);
|
||||
lcd_write_data(0x01);
|
||||
lcd_write_data(0x3F);
|
||||
|
||||
lcd_write_commmand(0x2A);
|
||||
lcd_write_data(0x00);
|
||||
lcd_write_data(0x00);
|
||||
lcd_write_data(0x01);
|
||||
lcd_write_data(0xE0);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void fast_send_data(void)
|
||||
{
|
||||
rt_uint32_t ii = 0;
|
||||
rt_uint32_t tx_index = 0;
|
||||
char *tx_data = (char *)send_buffer;
|
||||
rt_sem_take(&lcd_spi_lock, RT_WAITING_FOREVER);
|
||||
|
||||
SPI_REG_CS(SPI_0_BASE) &= (~(3 << 0));
|
||||
SPI_REG_CLK(SPI_0_BASE) = 4;
|
||||
SPI_REG_CS(SPI_0_BASE) |= SPI_CS_TA;
|
||||
for(tx_index=0;tx_index<(LCD_SCREEN_WIDTH * LCD_SCREEN_HEIGHT) * 2;tx_index++)
|
||||
{
|
||||
for(ii = 0; ii < 32; ii = ii + 2)
|
||||
{
|
||||
SPI_REG_FIFO(SPI_0_BASE) = tx_data[tx_index + ii + 1];
|
||||
SPI_REG_FIFO(SPI_0_BASE) = tx_data[tx_index + ii];
|
||||
}
|
||||
while (!(SPI_REG_CS(SPI_0_BASE) & SPI_CS_DONE));
|
||||
SPI_REG_CS(SPI_0_BASE) |= (SPI_CS_CLEAR_TX) | (SPI_CS_CLEAR_RX);
|
||||
tx_index = tx_index + 31;
|
||||
}
|
||||
SPI_REG_CS(SPI_0_BASE) |= (SPI_CS_CLEAR_TX) | (SPI_CS_CLEAR_RX);
|
||||
SPI_REG_CS(SPI_0_BASE) &= (~SPI_CS_TA);
|
||||
rt_sem_release(&lcd_spi_lock);
|
||||
}
|
||||
|
||||
static inline void lcd_show(void)
|
||||
{
|
||||
|
||||
lcd_write_commmand(0x2C); // Memory write?
|
||||
|
||||
//rt_thread_mdelay(150);
|
||||
|
||||
#ifdef LCD_SPI_SEND_FAST
|
||||
fast_send_data();
|
||||
#else
|
||||
int i, j;
|
||||
for (i = 0 ; i < 30 ; i ++)
|
||||
{
|
||||
uint16_t *tx_data = (uint16_t*)&send_buffer[5120* i];
|
||||
int32_t data_sz = 5120;
|
||||
for( j=0; j<data_sz; j++)
|
||||
{
|
||||
writeData16(tx_data[j]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static void lcd_init(void)
|
||||
{
|
||||
writeCommand(lcd_dev, 0x28);
|
||||
rt_thread_mdelay(150);
|
||||
|
||||
writeCommand(lcd_dev, 0x3A); // Interface Pixel Format
|
||||
writeData(lcd_dev, 0x55); // 16 bit/pixe
|
||||
|
||||
writeCommand(lcd_dev, 0xC2); // Interface Pixel Format
|
||||
writeData(lcd_dev, 0x44);
|
||||
|
||||
writeCommand(lcd_dev, 0xC5); // VCOM Control
|
||||
writeData(lcd_dev, 0x00);
|
||||
writeData(lcd_dev, 0x00);
|
||||
writeData(lcd_dev, 0x00);
|
||||
writeData(lcd_dev, 0x00);
|
||||
|
||||
writeCommand(lcd_dev, 0xE0); // PGAMCTRL(Positive Gamma Control)
|
||||
writeData(lcd_dev, 0x0F);
|
||||
writeData(lcd_dev, 0x1F);
|
||||
writeData(lcd_dev, 0x1C);
|
||||
writeData(lcd_dev, 0x0C);
|
||||
writeData(lcd_dev, 0x0F);
|
||||
writeData(lcd_dev, 0x08);
|
||||
writeData(lcd_dev, 0x48);
|
||||
writeData(lcd_dev, 0x98);
|
||||
writeData(lcd_dev, 0x37);
|
||||
writeData(lcd_dev, 0x0A);
|
||||
writeData(lcd_dev, 0x13);
|
||||
writeData(lcd_dev, 0x04);
|
||||
writeData(lcd_dev, 0x11);
|
||||
writeData(lcd_dev, 0x0D);
|
||||
writeData(lcd_dev, 0x00);
|
||||
|
||||
writeCommand(lcd_dev, 0xE1); // NGAMCTRL (Negative Gamma Correction)
|
||||
writeData(lcd_dev, 0x0F);
|
||||
writeData(lcd_dev, 0x32);
|
||||
writeData(lcd_dev, 0x2E);
|
||||
writeData(lcd_dev, 0x0B);
|
||||
writeData(lcd_dev, 0x0D);
|
||||
writeData(lcd_dev, 0x05);
|
||||
writeData(lcd_dev, 0x47);
|
||||
writeData(lcd_dev, 0x75);
|
||||
writeData(lcd_dev, 0x37);
|
||||
writeData(lcd_dev, 0x06);
|
||||
writeData(lcd_dev, 0x10);
|
||||
writeData(lcd_dev, 0x03);
|
||||
writeData(lcd_dev, 0x24);
|
||||
writeData(lcd_dev, 0x20);
|
||||
writeData(lcd_dev, 0x00);
|
||||
|
||||
writeCommand(lcd_dev, 0x11); // Sleep out, also SW reset
|
||||
rt_thread_mdelay(150);
|
||||
|
||||
writeCommand(lcd_dev, 0x20); // Display Inversion OFF RPi LCD (A)
|
||||
//writeCommand(lcd_dev, 0x21); // Display Inversion ON RPi LCD (B)
|
||||
|
||||
lcd_set_rotation(SCREEN_VERTICAL_2);
|
||||
writeCommand(lcd_dev, 0x29); // Display ON
|
||||
rt_thread_mdelay(150);
|
||||
}
|
||||
|
||||
static inline void lcd_reset(void)
|
||||
{
|
||||
//Reset signal, low reset (pin22)
|
||||
rt_pin_mode(LCD_RESET_PIN,PIN_MODE_OUTPUT);
|
||||
|
||||
rt_pin_write(LCD_RESET_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(100);
|
||||
rt_pin_write(LCD_RESET_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(100);
|
||||
rt_pin_write(LCD_RESET_PIN, PIN_HIGH);
|
||||
}
|
||||
|
||||
|
||||
rt_err_t ili9486_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_err_t ili9486_close(rt_device_t dev)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_size_t ili9486_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_size_t ili9486_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
|
||||
{
|
||||
#ifdef USING_LCD_CONSOLE
|
||||
fb_print((char*)buffer);
|
||||
#endif
|
||||
return size;
|
||||
}
|
||||
|
||||
rt_err_t ili9486_control(rt_device_t dev, int cmd, void *args)
|
||||
{
|
||||
rt_sem_take(&lcd_lock, RT_WAITING_FOREVER);
|
||||
switch (cmd)
|
||||
{
|
||||
case RTGRAPHIC_CTRL_RECT_UPDATE:
|
||||
{
|
||||
struct rt_device_rect_info *info = (struct rt_device_rect_info*)args;
|
||||
info = info;
|
||||
rt_memcpy(send_buffer, _lcd_buffer, LCD_SCREEN_WIDTH * LCD_SCREEN_HEIGHT * 2);
|
||||
lcd_show();
|
||||
}
|
||||
break;
|
||||
|
||||
case RTGRAPHIC_CTRL_GET_INFO:
|
||||
{
|
||||
struct rt_device_graphic_info* info = (struct rt_device_graphic_info*)args;
|
||||
|
||||
RT_ASSERT(info != RT_NULL);
|
||||
info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
|
||||
info->bits_per_pixel= 16;
|
||||
info->width = LCD_WIDTH;
|
||||
info->height = LCD_HEIGHT;
|
||||
info->framebuffer = (void *)_lcd_buffer;//lcd->fb;
|
||||
}
|
||||
break;
|
||||
}
|
||||
rt_sem_release(&lcd_lock);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
const static struct rt_device_ops ili9486_ops =
|
||||
{
|
||||
RT_NULL,
|
||||
ili9486_open,
|
||||
ili9486_close,
|
||||
ili9486_read,
|
||||
ili9486_write,
|
||||
ili9486_control,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int hw_ili9486_lcd_init(void)
|
||||
{
|
||||
struct rt_device *device;
|
||||
device = rt_malloc(sizeof(struct rt_device));
|
||||
rt_memset(device, 0, sizeof(struct rt_device));
|
||||
|
||||
lcd_reset();
|
||||
rt_pin_mode(LCD_RS_PIN, PIN_MODE_OUTPUT);
|
||||
lcd_dev = (struct rt_spi_device *)rt_device_find(LCD_DEVICE_NAME);
|
||||
if (!lcd_dev)
|
||||
{
|
||||
rt_kprintf("no %s!\n", LCD_DEVICE_NAME);
|
||||
}
|
||||
lcd_dev->config.max_hz = LCD_SPI_FREQ_MAX;//125M
|
||||
lcd_init();
|
||||
|
||||
rt_sem_init(&lcd_spi_lock, "lcd_spi_lock", 1, RT_IPC_FLAG_FIFO);
|
||||
rt_sem_init(&lcd_lock, "lcd_spi_lock", 1, RT_IPC_FLAG_FIFO);
|
||||
/* set device type */
|
||||
device->type = RT_Device_Class_Graphic;
|
||||
/* initialize device interface */
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
device->ops = &ili9486_ops;
|
||||
#else
|
||||
device->init = RT_NULL;
|
||||
device->open = ili9486_open;
|
||||
device->close = ili9486_close;
|
||||
device->read = ili9486_read;
|
||||
device->write = ili9486_write;
|
||||
device->control = ili9486_control;
|
||||
#endif
|
||||
/* register to device manager */
|
||||
rt_device_register(device, "lcd", RT_DEVICE_FLAG_RDWR);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(hw_ili9486_lcd_init);
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-08 bigmagic first version
|
||||
*/
|
||||
#ifndef __DRV_ILI9486_H__
|
||||
#define __DRV_ILI9486_H__
|
||||
|
||||
#endif//ILI9486
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-09 bigmagic first version
|
||||
*/
|
||||
|
||||
#include "lcd_console.h"
|
||||
#include "lcd_font_20.h"
|
||||
|
||||
#define LCD_CONSOLE_FLUSH_NOW 1
|
||||
|
||||
#define CONSOLE_NAME "hdmi"
|
||||
#define COLOR_DELTA 0.05
|
||||
|
||||
#ifndef LCD_CONSOLE_FLUSH_NOW
|
||||
static rt_thread_t console_flush_thread_tid = RT_NULL;
|
||||
#define CONSOLE_FLUSH_THREAD_STACK_SIZE (1024)
|
||||
#define CONSOLE_FLUSH_THREAD_PRIORITY (20)
|
||||
#define CONSOLE_FLUSH_THREAD_TIMESLICE (10)
|
||||
#define LCD_CONSOLE_DELAY (100) //100ms
|
||||
#endif
|
||||
|
||||
static rt_device_t console_dev = RT_NULL;
|
||||
|
||||
static fb_t console_fb;
|
||||
static rt_uint8_t* virt_buffer;
|
||||
|
||||
static rt_uint32_t CHAR_W = 8;
|
||||
static rt_uint32_t CHAR_H = 20;
|
||||
|
||||
static int prev_x_offset = 0;
|
||||
|
||||
static void newline(fb_t* fb)
|
||||
{
|
||||
uint8_t* to;
|
||||
uint8_t* from;
|
||||
int i;
|
||||
fb->y++;
|
||||
fb->x = 5 * fb->depth;
|
||||
|
||||
if (fb->y == (fb->height / CHAR_H))
|
||||
{
|
||||
to = (uint8_t*) fb->vaddr;
|
||||
from = to + (CHAR_H * fb->pitch);
|
||||
|
||||
for (i = 0; i < ((fb->height - CHAR_H) * fb->pitch); i++)
|
||||
{
|
||||
*to++ = *from++;
|
||||
}
|
||||
|
||||
if(fb->depth >= 3)
|
||||
{
|
||||
uint32_t *addr_32bit = (uint32_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width;
|
||||
|
||||
for (i = 0; i < (CHAR_H * fb->width); i++)
|
||||
{
|
||||
*addr_32bit++ = fb->back;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
uint16_t *addr_16bit = (uint16_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width;
|
||||
|
||||
for (i = 0; i < (CHAR_H * fb->width); i++)
|
||||
{
|
||||
*addr_16bit++ = fb->back;
|
||||
}
|
||||
}
|
||||
fb->y = fb->y - 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void fb_draw_char(fb_t *fb, char s)
|
||||
{
|
||||
unsigned char* addr = (unsigned char*) fb->vaddr;
|
||||
unsigned char *glyph = (unsigned char *)lcd_console_font_dejavu_20_glyph_bitmap + lcd_console_font_dejavu_20_glyph_dsc[s - 32].glyph_index;
|
||||
CHAR_W = lcd_console_font_dejavu_20_glyph_dsc[s - 32].w_px;
|
||||
|
||||
fb->x = fb->x + prev_x_offset * fb->depth;
|
||||
|
||||
int i, j, line, mask, bytesperline = (CHAR_W + 7) / 8;
|
||||
int kk = (bytesperline) * 8;
|
||||
prev_x_offset = CHAR_W + 2;
|
||||
// calculate the offset on screen
|
||||
int offs = (fb->y * CHAR_H * fb->pitch) + fb->x;
|
||||
|
||||
// display a character
|
||||
for (j = 0; j < CHAR_H; j++)
|
||||
{
|
||||
// display one row
|
||||
line = offs;
|
||||
mask = 1;
|
||||
mask = 0x80;
|
||||
for (i = 0; i < kk; i++)
|
||||
{
|
||||
if(fb->depth >= 3)
|
||||
{
|
||||
*((unsigned int*) (addr + line)) = ((int) *(glyph + ((i)/8)) * 1) & mask ? fb->fore : fb->back;
|
||||
}
|
||||
else
|
||||
{
|
||||
*((unsigned short*) (addr + line)) = ((int) *(glyph + ((i)/8)) * 1) & mask ? fb->fore : fb->back;
|
||||
}
|
||||
|
||||
mask >>= 1;
|
||||
if(mask == 0)
|
||||
{
|
||||
mask = 0x80;
|
||||
}
|
||||
line += fb->depth;
|
||||
}
|
||||
// adjust to next line
|
||||
glyph += bytesperline;
|
||||
offs += fb->pitch;
|
||||
}
|
||||
}
|
||||
|
||||
void fb_print(char *s)
|
||||
{
|
||||
fb_t *fb = &console_fb;
|
||||
// draw next character if it's not zero
|
||||
while (*s)
|
||||
{
|
||||
// handle carrige return
|
||||
if (*s == '\r')
|
||||
{
|
||||
fb->x = 5 * fb->depth;
|
||||
}
|
||||
else if (*s == '\n')
|
||||
{
|
||||
newline(fb);
|
||||
}
|
||||
else if (*s == '\t')
|
||||
{
|
||||
//tab is 8 spaces
|
||||
if((fb->x + 8 * fb->depth) < (fb->width) * fb->depth)
|
||||
{
|
||||
fb->x = fb->x + 8 * fb->depth;
|
||||
}
|
||||
}
|
||||
else if (*s == '\b')
|
||||
{
|
||||
if (fb->x > 5 * fb->depth)
|
||||
{
|
||||
fb->x = fb->x - prev_x_offset * fb->depth;
|
||||
fb_draw_char(fb, ' ');
|
||||
}
|
||||
}
|
||||
else if((fb->x + prev_x_offset * fb->depth + 5 * fb->depth) >= (fb->width * fb->depth))
|
||||
{
|
||||
newline(fb);
|
||||
fb_draw_char(fb, *s);
|
||||
}
|
||||
else
|
||||
{
|
||||
fb_draw_char(fb, *s);
|
||||
}
|
||||
s++;
|
||||
}
|
||||
|
||||
#ifdef LCD_CONSOLE_FLUSH_NOW
|
||||
rt_memcpy((void *)fb->paddr, (void *)fb->vaddr, fb->size);
|
||||
if(console_dev != RT_NULL)
|
||||
{
|
||||
rt_device_control(console_dev,RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef LCD_CONSOLE_FLUSH_NOW
|
||||
void lcd_console_task_entry(void *param)
|
||||
{
|
||||
fb_t *fb = (fb_t *)param;
|
||||
while (1)
|
||||
{
|
||||
rt_memcpy((void *)fb->paddr, (void *)fb->vaddr, fb->size);
|
||||
if(console_dev != RT_NULL)
|
||||
{
|
||||
rt_device_control(console_dev,RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
|
||||
}
|
||||
rt_thread_mdelay(LCD_CONSOLE_DELAY);
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
int lcd_console_init(void)
|
||||
{
|
||||
struct rt_device_graphic_info info;
|
||||
console_dev = rt_device_find(CONSOLE_NAME);
|
||||
if(console_dev == RT_NULL)
|
||||
{
|
||||
rt_kprintf("no console dev!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if(console_dev->ref_count >= 1)
|
||||
{
|
||||
rt_kprintf("lcd console has open!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_device_open(console_dev,RT_DEVICE_OFLAG_RDWR);
|
||||
|
||||
rt_device_control(console_dev, RTGRAPHIC_CTRL_GET_INFO, &info);
|
||||
|
||||
virt_buffer = (rt_uint8_t* )rt_malloc(info.width * info.height * (info.bits_per_pixel/8));
|
||||
rt_memset(virt_buffer, 0 , info.width * info.height * (info.bits_per_pixel/8));
|
||||
console_fb.width = info.width;
|
||||
console_fb.height = info.height;
|
||||
console_fb.pitch = info.width * (info.bits_per_pixel/8);
|
||||
console_fb.vaddr = (rt_uint32_t)virt_buffer;
|
||||
console_fb.paddr = (rt_uint32_t)info.framebuffer;
|
||||
console_fb.size = info.width * info.height * (info.bits_per_pixel/8);
|
||||
console_fb.depth = info.bits_per_pixel/8;
|
||||
console_fb.x = 0;
|
||||
console_fb.y = 0;
|
||||
if(console_fb.depth >= 3)
|
||||
{
|
||||
console_fb.fore = CONSOLE_WHITE_32;
|
||||
console_fb.back = CONSOLE_BLACK_32;
|
||||
}
|
||||
else
|
||||
{
|
||||
console_fb.fore = CONSOLE_WHITE_16;
|
||||
console_fb.back = CONSOLE_BLACK_16;
|
||||
}
|
||||
|
||||
#ifndef LCD_CONSOLE_FLUSH_NOW
|
||||
console_flush_thread_tid = rt_thread_create("lcd_console", lcd_console_task_entry, (void *)&console_fb,
|
||||
CONSOLE_FLUSH_THREAD_STACK_SIZE,
|
||||
CONSOLE_FLUSH_THREAD_PRIORITY, CONSOLE_FLUSH_THREAD_TIMESLICE);
|
||||
if (console_flush_thread_tid != RT_NULL)
|
||||
rt_thread_startup(console_flush_thread_tid);
|
||||
#endif
|
||||
/*
|
||||
* note:
|
||||
* if serial console and lcd console together
|
||||
* you can add /src/kservice.c:rt_kprintf
|
||||
* #ifdef USING_LCD_CONSOLE
|
||||
* fb_print((char*)rt_log_buf);
|
||||
* #endif
|
||||
*
|
||||
* remove rt_console_set_device(CONSOLE_NAME);
|
||||
*/
|
||||
rt_console_set_device(CONSOLE_NAME);
|
||||
|
||||
rt_show_version();//show rt-thread logo
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_APP_EXPORT(lcd_console_init);
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-09 bigmagic first version
|
||||
*/
|
||||
#ifndef __LCD_CONSOLE_H__
|
||||
#define __LCD_CONSOLE_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
|
||||
#define COLOR_BLACK RGB(0, 0, 0)
|
||||
#define COLOR_GREEN RGB(0, 255, 0)
|
||||
#define COLOR_CYAN RGB(0, 255, 255)
|
||||
#define COLOR_RED RGB(255, 0, 0)
|
||||
#define COLOR_YELLOW RGB(255, 255, 0)
|
||||
#define COLOR_WHITE RGB(255, 255, 255)
|
||||
|
||||
#define CONSOLE_WHITE_32 COLOR_WHITE
|
||||
#define CONSOLE_BLACK_32 COLOR_BLACK
|
||||
#define CONSOLE_GREEN_32 COLOR_GREEN
|
||||
#define CONSOLE_CYAN_32 COLOR_CYAN
|
||||
#define CONSOLE_RED_32 COLOR_RED
|
||||
|
||||
|
||||
#define RGB16(r, g, b) ((((r))<<11) | (((g))<<5) | ((b)))
|
||||
#define CONSOLE_YELLOW_16 RGB16(0x1f,0x3f,0)
|
||||
#define CONSOLE_WHITE_16 RGB16(0x1f,0x3f,0x1f)
|
||||
#define CONSOLE_BLACK_16 RGB16(0,0,0)
|
||||
#define CONSOLE_GREEN_16 RGB16(0,0x3f,0)
|
||||
#define CONSOLE_CYAN_16 RGB16(0,0x3f,0x1f)
|
||||
#define CONSOLE_RED_16 RGB16(0x1f,0,0)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
rt_uint32_t width;
|
||||
rt_uint32_t height;
|
||||
rt_uint32_t vwidth;
|
||||
rt_uint32_t vheight;
|
||||
rt_uint32_t pitch;
|
||||
rt_uint32_t depth;
|
||||
rt_uint32_t fore;
|
||||
rt_uint32_t back;
|
||||
rt_uint32_t x;
|
||||
rt_uint32_t y;
|
||||
rt_uint32_t vaddr;
|
||||
rt_uint32_t paddr;
|
||||
rt_uint32_t size;
|
||||
} fb_t;
|
||||
|
||||
void fb_print(char *s);
|
||||
int lcd_console_init(void);
|
||||
|
||||
#endif//CONSOLE
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -49,6 +49,24 @@ int mbox_call(unsigned char ch, int mmu_enable)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int bcm271x_mbox_get_touch(void)
|
||||
{
|
||||
mbox[0] = 8*4; // length of the message
|
||||
mbox[1] = MBOX_REQUEST; // this is a request message
|
||||
|
||||
mbox[2] = MBOX_TAG_GET_TOUCHBUF;
|
||||
mbox[3] = 4; // buffer size
|
||||
mbox[4] = 0; // len
|
||||
|
||||
mbox[5] = 0; // id
|
||||
mbox[6] = 0;
|
||||
|
||||
mbox[7] = MBOX_TAG_LAST;
|
||||
mbox_call(8, MMU_DISABLE);
|
||||
|
||||
return (int)(mbox[5] & ~0xC0000000);
|
||||
}
|
||||
|
||||
int bcm271x_notify_reboot(void)
|
||||
{
|
||||
mbox[0] = 7*4; // length of the message
|
||||
|
|
|
|||
|
|
@ -132,9 +132,27 @@ enum {
|
|||
#define MBOX_TAG_NOTIFY_REBOOT 0x00030048
|
||||
#define MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058
|
||||
|
||||
/*
|
||||
* touch
|
||||
*/
|
||||
#define MBOX_TAG_GET_TOUCHBUF (0x0004000F)
|
||||
|
||||
#define MBOX_ADDR 0x08000000
|
||||
|
||||
#define RES_CLK_ID (0x000000000)
|
||||
#define EMMC_CLK_ID (0x000000001)
|
||||
#define UART_CLK_ID (0x000000002)
|
||||
#define ARM_CLK_ID (0x000000003)
|
||||
#define CORE_CLK_ID (0x000000004)
|
||||
#define V3D_CLK_ID (0x000000005)
|
||||
#define H264_CLK_ID (0x000000006)
|
||||
#define ISP_CLK_ID (0x000000007)
|
||||
#define SDRAM_CLK_ID (0x000000008)
|
||||
#define PIXEL_CLK_ID (0x000000009)
|
||||
#define PWM_CLK_ID (0x00000000a)
|
||||
|
||||
int mbox_call(unsigned char ch, int mmu_enable);
|
||||
int bcm271x_mbox_get_touch(void);
|
||||
int bcm271x_notify_reboot(void);
|
||||
int bcm271x_notify_xhci_reset(void);
|
||||
int bcm271x_gpu_enable(void);
|
||||
|
|
|
|||
|
|
@ -152,6 +152,25 @@ typedef enum {
|
|||
#define MMC0_BASE_ADDR (PER_BASE+0x300000)
|
||||
#define MMC2_BASE_ADDR (PER_BASE+0x340000)
|
||||
|
||||
#define ETH_IRQ (160+29)
|
||||
|
||||
//I2C
|
||||
#define BSC0_BASE_OFFSET (0x205000)
|
||||
#define BSC1_BASE_OFFSET (0x804000)
|
||||
#define BSC3_BASE_OFFSET (0x205600)
|
||||
#define BSC4_BASE_OFFSET (0x205800)
|
||||
#define BSC5_BASE_OFFSET (0x205A80)
|
||||
#define BSC6_BASE_OFFSET (0x205C00)
|
||||
|
||||
//BSC2 and BSC7 masters are dedicated for use by the
|
||||
//HDMI interfaces and should not be accessed byuser programs.
|
||||
#define BSC0_BASE (PER_BASE + BSC0_BASE_OFFSET)
|
||||
#define BSC1_BASE (PER_BASE + BSC1_BASE_OFFSET)
|
||||
#define BSC3_BASE (PER_BASE + BSC3_BASE_OFFSET)
|
||||
#define BSC4_BASE (PER_BASE + BSC4_BASE_OFFSET)
|
||||
#define BSC5_BASE (PER_BASE + BSC5_BASE_OFFSET)
|
||||
#define BSC6_BASE (PER_BASE + BSC6_BASE_OFFSET)
|
||||
|
||||
/* the basic constants and interfaces needed by gic */
|
||||
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
if not GetDepend('BSP_USING_XPT_TOUCH_DEV'):
|
||||
SrcRemove(src, ['drv_xpt2046.c'])
|
||||
if not GetDepend('BSP_USING_DSI_TOUCH_DEV'):
|
||||
SrcRemove(src, ['drv_dsi_touch.c'])
|
||||
|
||||
group = DefineGroup('drv_touch', src, depend = ['BSP_USING_TOUCH'], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-26 bigmagic first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <touch.h>
|
||||
|
||||
#include "mbox.h"
|
||||
#include "drv_dsi_touch.h"
|
||||
|
||||
#define DBG_TAG "dsi_touch"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
static rt_touch_t touch_device = RT_NULL;
|
||||
static struct rt_semaphore dsi_touch_ack;
|
||||
|
||||
static rt_uint32_t touch_x;
|
||||
static rt_uint32_t touch_y;
|
||||
static rt_uint32_t touch_state;
|
||||
|
||||
static rt_thread_t dsi_touch_tid = RT_NULL;
|
||||
#define DSI_TOUCH_THREAD_STACK_SIZE (4096)
|
||||
#define DSI_TOUCH_THREAD_PRIORITY (25)
|
||||
#define DSI_TOUCH_THREAD_TIMESLICE (10)
|
||||
|
||||
#define MAXIMUM_SUPPORTED_POINTS (10)
|
||||
|
||||
struct touch_regs
|
||||
{
|
||||
uint8_t device_mode;
|
||||
uint8_t gesture_id;
|
||||
uint8_t num_points;
|
||||
struct touch
|
||||
{
|
||||
uint8_t xh;
|
||||
uint8_t xl;
|
||||
uint8_t yh;
|
||||
uint8_t yl;
|
||||
uint8_t res1;
|
||||
uint8_t res2;
|
||||
} point[MAXIMUM_SUPPORTED_POINTS];
|
||||
};
|
||||
|
||||
static void dsi_touch_thread_entry(void *param)
|
||||
{
|
||||
static volatile uint32_t touchbuf;
|
||||
touchbuf = bcm271x_mbox_get_touch(); //0x0f436000
|
||||
|
||||
if(touchbuf == RT_NULL)
|
||||
{
|
||||
rt_kprintf("init dsi touch err!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
while (1)
|
||||
{
|
||||
struct touch_regs *regs = (struct touch_regs *)touchbuf;
|
||||
if ((regs->num_points > 0) && (regs->num_points < MAXIMUM_SUPPORTED_POINTS))
|
||||
{
|
||||
//only one touch point
|
||||
touch_x = (((int)regs->point[0].xh & 0xf) << 8) + regs->point[0].xl;
|
||||
touch_y = (((int)regs->point[0].yh & 0xf) << 8) + regs->point[0].yl;
|
||||
touch_state = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
touch_state = 0;
|
||||
}
|
||||
rt_thread_mdelay(50);
|
||||
}
|
||||
}
|
||||
|
||||
static rt_size_t dsi_read_point(struct rt_touch_device *touch, void *buf, rt_size_t read_num)
|
||||
{
|
||||
rt_uint16_t* touchxy = (rt_uint16_t *)buf;
|
||||
if((read_num != 0) && (touch_state == 1))
|
||||
{
|
||||
touchxy[0] = touch_x;
|
||||
touchxy[1] = touch_y;
|
||||
touch_state = 0;
|
||||
return read_num;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t dsi_control(struct rt_touch_device *device, int cmd, void *data)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static struct rt_touch_ops dsi_touch_ops =
|
||||
{
|
||||
.touch_readpoint = dsi_read_point,
|
||||
.touch_control = dsi_control,
|
||||
};
|
||||
|
||||
static int hw_dsi_touch_init(void)
|
||||
{
|
||||
//touch sem
|
||||
rt_sem_init(&dsi_touch_ack, "dsi_touch_ack", 0, RT_IPC_FLAG_FIFO);
|
||||
|
||||
dsi_touch_tid = rt_thread_create("dsi_touch",
|
||||
dsi_touch_thread_entry, RT_NULL,
|
||||
DSI_TOUCH_THREAD_STACK_SIZE,
|
||||
DSI_TOUCH_THREAD_PRIORITY, DSI_TOUCH_THREAD_TIMESLICE);
|
||||
if (dsi_touch_tid != RT_NULL)
|
||||
rt_thread_startup(dsi_touch_tid);
|
||||
|
||||
touch_device = (rt_touch_t)rt_calloc(1, sizeof(struct rt_touch_device));
|
||||
|
||||
if (touch_device == RT_NULL)
|
||||
return -RT_ERROR;
|
||||
|
||||
/* register touch device */
|
||||
touch_device->info.type = RT_TOUCH_TYPE_RESISTANCE;
|
||||
touch_device->info.vendor = RT_TOUCH_VENDOR_UNKNOWN;
|
||||
//rt_memcpy(&touch_device->config, cfg, sizeof(struct rt_touch_config));
|
||||
touch_device->ops = &dsi_touch_ops;
|
||||
rt_hw_touch_register(touch_device, "dsi_touch", RT_DEVICE_FLAG_INT_RX, RT_NULL);
|
||||
return 0;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(hw_dsi_touch_init);
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-26 bigmagic first version
|
||||
*/
|
||||
#ifndef __DRV_DSI_TOUCH_H__
|
||||
#define __DRV_DSI_TOUCH_H__
|
||||
|
||||
#endif//DSI TOUCH
|
||||
|
|
@ -0,0 +1,252 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-08 bigmagic first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <touch.h>
|
||||
|
||||
#include "drv_xpt2046.h"
|
||||
//http://www.lcdwiki.com/MHS-3.5inch_RPi_Display
|
||||
|
||||
#define DBG_TAG "xpt2046"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
//XPT2049
|
||||
#define READ_X (0xD0)
|
||||
#define READ_Y (0x90)
|
||||
|
||||
#define TFT_WIDTH (320)
|
||||
#define TFT_HEIGHT (480)
|
||||
//freq
|
||||
#define TOUCH_SPI_MAX_FREQ (10*1000)
|
||||
|
||||
#define TP_IRQ_PIN (17)
|
||||
#define TOUCH_DEVICE_NAME ("spi0.1")
|
||||
|
||||
static struct rt_semaphore touch_ack;
|
||||
static rt_touch_t touch_device = RT_NULL;
|
||||
|
||||
static rt_thread_t touch_tid = RT_NULL;
|
||||
#define TOUCH_THREAD_STACK_SIZE (1024)
|
||||
#define TOUCH_THREAD_PRIORITY (30)
|
||||
#define TOUCH_THREAD_TIMESLICE (10)
|
||||
|
||||
rt_uint8_t touch_flag = 0;
|
||||
rt_uint16_t touch_x_val = 0;
|
||||
rt_uint16_t touch_y_val = 0;
|
||||
|
||||
extern struct rt_semaphore lcd_spi_lock;
|
||||
static void touch_read_x_y(void *dev, rt_uint16_t *x, rt_uint16_t *y)
|
||||
{
|
||||
struct rt_spi_device *touch_dev = (struct rt_spi_device *)dev;
|
||||
struct rt_spi_message msg1,msg2,msg3,msg4;
|
||||
rt_uint16_t readx_val = 0,ready_val = 0;
|
||||
rt_uint8_t readx[2];
|
||||
rt_uint8_t ready[2];
|
||||
rt_sem_take(&lcd_spi_lock, RT_WAITING_FOREVER);
|
||||
|
||||
int read_x_id = READ_X;
|
||||
int read_y_id = READ_Y;
|
||||
|
||||
msg1.send_buf = &read_x_id;
|
||||
msg1.recv_buf = RT_NULL;
|
||||
msg1.length = 1;
|
||||
msg1.cs_take = 1;
|
||||
msg1.cs_release = 0;
|
||||
msg1.next = &msg2;
|
||||
|
||||
msg2.send_buf = RT_NULL;
|
||||
msg2.recv_buf = &readx[0];
|
||||
msg2.length = 2;
|
||||
msg2.cs_take = 0;
|
||||
msg2.cs_release = 0;
|
||||
msg2.next = &msg3;
|
||||
|
||||
msg3.send_buf = &read_y_id;
|
||||
msg3.recv_buf = RT_NULL;
|
||||
msg3.length = 1;
|
||||
msg3.cs_take = 0;
|
||||
msg3.cs_release = 0;
|
||||
msg3.next = &msg4;
|
||||
|
||||
msg4.send_buf = RT_NULL;
|
||||
msg4.recv_buf = &ready[0];
|
||||
msg4.length = 2;
|
||||
msg4.cs_take = 0;
|
||||
msg4.cs_release = 1;
|
||||
msg4.next = RT_NULL;
|
||||
|
||||
rt_spi_transfer_message(touch_dev, &msg1);
|
||||
|
||||
readx_val = ((readx[0] << 8) | readx[1]) >> 4;
|
||||
ready_val = ((ready[0] << 8) | ready[1]) >> 4;
|
||||
|
||||
rt_sem_release(&lcd_spi_lock);
|
||||
*x = readx_val;
|
||||
*y = ready_val;
|
||||
}
|
||||
|
||||
/*
|
||||
XPT2046:Width:320 High:480
|
||||
no pressed:(0x800,0xfff)
|
||||
---ETH----USB-----------------------
|
||||
| (0x800,0x800) (0xfff,0x800) |
|
||||
| |
|
||||
| (0x800,0xFFF) (0xfff,0xfff) |
|
||||
------------------------------------
|
||||
*/
|
||||
#define XMIN 0x800
|
||||
#define YMAX 0xfff
|
||||
void read_tp(void *dev, rt_uint16_t *x, rt_uint16_t *y)
|
||||
{
|
||||
struct rt_spi_device *touch_dev = (struct rt_spi_device *)dev;
|
||||
rt_uint8_t try = 0;
|
||||
uint16_t _y[5] = {0,0,0,0,0};
|
||||
uint16_t _x[5] = {0,0,0,0,0};
|
||||
uint16_t x_val = 0;
|
||||
uint16_t y_val = 0;
|
||||
uint16_t cur_x = 0;
|
||||
uint16_t cur_y = 0;
|
||||
int index = 0;
|
||||
|
||||
while(1)
|
||||
{
|
||||
try = try + 1;
|
||||
touch_read_x_y(touch_dev, x, y);
|
||||
if((*x > XMIN) && (*y < YMAX))
|
||||
{
|
||||
_x[index] = *x;
|
||||
_y[index] = *y;
|
||||
index = index + 1;
|
||||
}
|
||||
if(index == 5)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if(try > 10)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
x_val = (_x[0] + _x[1] + _x[2] + _x[3]+ _x[4]) / index;
|
||||
y_val = (_y[0] + _y[1] + _y[2] + _y[3]+ _y[4]) / index;
|
||||
|
||||
cur_x = (x_val - 0x800) * TFT_WIDTH / 0x800;
|
||||
cur_y = (y_val - 0x800) * TFT_HEIGHT / 0x800;
|
||||
|
||||
if((cur_x < TFT_WIDTH) && (cur_y < TFT_HEIGHT))
|
||||
{
|
||||
*x = TFT_WIDTH - cur_x;
|
||||
*y = TFT_HEIGHT - cur_y;
|
||||
}
|
||||
else
|
||||
{
|
||||
*x = 0;
|
||||
*y = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void touch_thread_entry(void *param)
|
||||
{
|
||||
rt_uint16_t x,y;
|
||||
struct rt_spi_device *touch_dev;
|
||||
touch_dev = (struct rt_spi_device *)rt_device_find(TOUCH_DEVICE_NAME);
|
||||
touch_dev->config.max_hz = TOUCH_SPI_MAX_FREQ;
|
||||
if (!touch_dev)
|
||||
{
|
||||
rt_kprintf("no %s!\n", TOUCH_DEVICE_NAME);
|
||||
}
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_sem_take(&touch_ack, RT_WAITING_FOREVER);
|
||||
read_tp(touch_dev, &x, &y);
|
||||
if((x!= 0) && (y !=0))
|
||||
{
|
||||
touch_x_val = x;
|
||||
touch_y_val = y;
|
||||
touch_flag = 1;
|
||||
}
|
||||
rt_pin_mode(TP_IRQ_PIN, PIN_MODE_INPUT_PULLUP);
|
||||
}
|
||||
}
|
||||
|
||||
static void touch_readly(void *args)
|
||||
{
|
||||
if(rt_pin_read(TP_IRQ_PIN) == PIN_LOW)
|
||||
{
|
||||
rt_pin_mode(TP_IRQ_PIN, PIN_MODE_OUTPUT);
|
||||
rt_pin_write(TP_IRQ_PIN,PIN_HIGH);
|
||||
rt_sem_release(&touch_ack);
|
||||
}
|
||||
}
|
||||
|
||||
static rt_size_t xpt2046_read_point(struct rt_touch_device *touch, void *buf, rt_size_t read_num)
|
||||
{
|
||||
rt_uint16_t* touchxy = (rt_uint16_t *)buf;
|
||||
if((read_num != 0) && (touch_flag == 1))
|
||||
{
|
||||
touchxy[0] = touch_x_val;
|
||||
touchxy[1] = touch_y_val;
|
||||
touch_flag = 0;
|
||||
return read_num;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t xpt2046_control(struct rt_touch_device *device, int cmd, void *data)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static struct rt_touch_ops touch_ops =
|
||||
{
|
||||
.touch_readpoint = xpt2046_read_point,
|
||||
.touch_control = xpt2046_control,
|
||||
};
|
||||
|
||||
static int hw_xpt2049_touch_init(void)
|
||||
{
|
||||
//touch sem
|
||||
rt_sem_init(&touch_ack, "touch_ack", 0, RT_IPC_FLAG_FIFO);
|
||||
|
||||
touch_tid = rt_thread_create("touch",
|
||||
touch_thread_entry, RT_NULL,
|
||||
TOUCH_THREAD_STACK_SIZE,
|
||||
TOUCH_THREAD_PRIORITY, TOUCH_THREAD_TIMESLICE);
|
||||
if (touch_tid != RT_NULL)
|
||||
rt_thread_startup(touch_tid);
|
||||
|
||||
rt_pin_mode(TP_IRQ_PIN, PIN_MODE_INPUT_PULLUP);
|
||||
rt_pin_attach_irq(TP_IRQ_PIN, PIN_IRQ_MODE_LOW_LEVEL, touch_readly, RT_NULL);
|
||||
rt_pin_irq_enable(TP_IRQ_PIN, PIN_IRQ_ENABLE);
|
||||
|
||||
touch_device = (rt_touch_t)rt_calloc(1, sizeof(struct rt_touch_device));
|
||||
|
||||
if (touch_device == RT_NULL)
|
||||
return -RT_ERROR;
|
||||
|
||||
/* register touch device */
|
||||
touch_device->info.type = RT_TOUCH_TYPE_RESISTANCE;
|
||||
touch_device->info.vendor = RT_TOUCH_VENDOR_UNKNOWN;
|
||||
//rt_memcpy(&touch_device->config, cfg, sizeof(struct rt_touch_config));
|
||||
touch_device->ops = &touch_ops;
|
||||
|
||||
rt_hw_touch_register(touch_device, "xpt2046", RT_DEVICE_FLAG_INT_RX, RT_NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(hw_xpt2049_touch_init);
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-08 bigmagic first version
|
||||
*/
|
||||
#ifndef __DRV_XPT2046_H__
|
||||
#define __DRV_XPT2046_H__
|
||||
|
||||
#endif//XPT2046
|
||||
|
|
@ -63,6 +63,14 @@ SECTIONS
|
|||
_etext = .;
|
||||
}
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
|
||||
__exidx_end = .;
|
||||
|
||||
__rodata_start = .;
|
||||
.rodata : { *(.rodata) *(.rodata.*) }
|
||||
__rodata_end = .;
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_USING_IDLE_HOOK
|
||||
|
|
@ -40,7 +40,7 @@
|
|||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x40003
|
||||
#define ARCH_ARMV8
|
||||
|
||||
|
|
@ -94,9 +94,14 @@
|
|||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SYSTEM_WORKQUEUE
|
||||
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_SERIAL_RB_BUFSZ 512
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_SDIO
|
||||
#define RT_SDIO_STACK_SIZE 512
|
||||
|
|
@ -106,6 +111,7 @@
|
|||
#define RT_MMCSD_MAX_PARTITION 16
|
||||
#define RT_USING_SPI
|
||||
#define RT_USING_WDT
|
||||
#define RT_USING_TOUCH
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
|
@ -119,6 +125,12 @@
|
|||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
#define RT_USING_SAL
|
||||
|
||||
/* protocol stack implement */
|
||||
|
||||
#define SAL_USING_LWIP
|
||||
#define SAL_USING_POSIX
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
|
|
@ -214,6 +226,9 @@
|
|||
/* system packages */
|
||||
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
|
||||
|
|
@ -223,6 +238,9 @@
|
|||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* games: games run on RT-Thread console */
|
||||
|
||||
|
||||
/* Privated Packages of RealThread */
|
||||
|
||||
|
||||
|
|
@ -236,22 +254,29 @@
|
|||
|
||||
#define BSP_USING_UART
|
||||
#define RT_USING_UART0
|
||||
#define RT_USING_UART1
|
||||
#define RT_USING_UART3
|
||||
#define RT_USING_UART4
|
||||
#define RT_USING_UART5
|
||||
#define BSP_USING_GIC
|
||||
#define BSP_USING_GIC400
|
||||
#define BSP_USING_PIN
|
||||
#define BSP_USING_SPI
|
||||
#define BSP_USING_SPI0_BUS
|
||||
#define BSP_USING_SPI0_DEVICE0
|
||||
#define BSP_USING_SPI0_DEVICE1
|
||||
#define BSP_USING_I2C
|
||||
#define BSP_USING_I2C3
|
||||
#define BSP_USING_CORETIMER
|
||||
#define BSP_USING_WDT
|
||||
#define BSP_USING_ETH
|
||||
#define BSP_USING_SDIO
|
||||
#define BSP_USING_SDIO0
|
||||
|
||||
/* Board Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_HDMI
|
||||
#define BSP_USING_HDMI_DISPLAY
|
||||
#define BSP_USING_LCD
|
||||
#define BSP_USING_DSI_DISPLAY
|
||||
#define BSP_USING_TOUCH
|
||||
#define BSP_USING_DSI_TOUCH_DEV
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -221,8 +221,11 @@ rt_inline int _serial_poll_rx(struct rt_serial_device *serial, rt_uint8_t *data,
|
|||
*data = ch;
|
||||
data ++; length --;
|
||||
|
||||
if(serial->parent.open_flag & RT_DEVICE_FLAG_STREAM)
|
||||
{
|
||||
if (ch == '\n') break;
|
||||
}
|
||||
}
|
||||
|
||||
return size - length;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue