修复部分bsp编译报错

This commit is contained in:
mazhiyuan 2021-10-13 11:02:01 +08:00
parent 06fdc108b4
commit 99e9ea61bc
16 changed files with 23 additions and 21 deletions

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@ -44,7 +44,7 @@ static struct clk plla = {
static struct clk mck = {
"mck",
0,
NULL,
RT_NULL,
{RT_NULL, RT_NULL},
};

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@ -32,7 +32,7 @@ typedef struct
{
FSpi_Ctrl_t spi_ctrl;
struct rt_spi_bus spi_bus;
uint16_t spi_cs_pin;
rt_uint16_t spi_cs_pin;
spi_cs_handler_t spi_cs_handler;
} ft2004_spi_class;
@ -214,7 +214,7 @@ static const struct rt_spi_ops ft2004_spi_ops =
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin)
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint16_t cs_gpio_pin)
{
rt_err_t result;
struct rt_spi_device *spi_device;

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@ -19,7 +19,7 @@
#define SPI_BUS_NAME "spi0"
#define SPI_DEV_NAME "S25FS256"
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin);
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint16_t cs_gpio_pin);
#ifdef __cplusplus
extern "C"

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@ -75,7 +75,7 @@ rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluste
void send_core_isg(void)
{
for (size_t i = 0; i <= 0xf; i++)
for (rt_size_t i = 0; i <= 0xf; i++)
{
/* code */
rt_kprintf("i %x \r\n", i);

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@ -86,7 +86,7 @@ static inline rt_uint64_t __get_cntp_cval(void)
* This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
* param value: CNTP_CTL Register value to set
*/
static inline void __set_cntp_ctl(uint32_t value)
static inline void __set_cntp_ctl(rt_uint32_t value)
{
__set_cp(15, 0, value, 14, 2, 1);
}

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@ -158,7 +158,7 @@ static rt_err_t mcu_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
tmp_gpio_cfg.func = GPIO_FUNC_IN;
GPIO_Config(&tmp_gpio_cfg);
GPIO_IntDisable(&tmp_gpio_cfg);
GPIO_RegisterCallback(&tmp_gpio_cfg, NULL, NULL);
GPIO_RegisterCallback(&tmp_gpio_cfg, RT_NULL, RT_NULL);
return RT_EOK;
}
@ -189,7 +189,7 @@ const static struct rt_pin_ops _mcu_pin_ops =
mcu_pin_attach_irq,
mcu_pin_dettach_irq,
mcu_pin_irq_enable,
NULL,
RT_NULL,
};
int rt_hw_pin_init(void)

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@ -241,7 +241,7 @@ int rt_hw_usart_init(void)
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX
, NULL);
, RT_NULL);
RT_ASSERT(result == RT_EOK);
}

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@ -16,6 +16,7 @@
#include <rtthread.h>
#include <rtdevice.h>
#include <sys/time.h>
#include "slcd_rhe6616tp01.h"

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@ -14,7 +14,8 @@
#include <rthw.h>
#include <string.h>
#include <drivers/hwtimer.h>
#include "raspi.h"
#include <raspi.h>
#include <sys/time.h>
#ifdef BSP_USING_HDMI
#include "drv_fb.h"
@ -368,7 +369,7 @@ int test_rtc(void)
{
#ifdef BSP_USING_RTC
rt_kprintf("Hello Test RTC!\n");
uint8_t i;
rt_uint8_t i;
time_t now;
rt_err_t ret = RT_EOK;

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@ -142,7 +142,7 @@ static inline rt_uint32_t read_cntctrl(void)
return val;
}
static inline uint32_t write_cntctrl(uint32_t val)
static inline rt_uint32_t write_cntctrl(rt_uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));

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@ -66,7 +66,7 @@ void rt_hw_interrupt_init(void)
for (index = 0; index < MAX_HANDLERS; index ++)
{
isr_table[index].handler = default_isr_handler;
isr_table[index].param = NULL;
isr_table[index].param = RT_NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
isr_table[index].counter = 0;

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@ -22,9 +22,9 @@ struct hwcrypto_gcm;
struct hwcrypto_gcm_ops
{
rt_err_t (*start)(struct hwcrypto_gcm *gcm_ctx,
const unsigned char *add, size_t add_len); /**< Set additional data. start GCM operation */
const unsigned char *add, rt_size_t add_len); /**< Set additional data. start GCM operation */
rt_err_t (*finish)(struct hwcrypto_gcm *gcm_ctx,
const unsigned char *tag, size_t tag_len); /**< finish GCM operation. get tag */
const unsigned char *tag, rt_size_t tag_len); /**< finish GCM operation. get tag */
};
/**

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@ -66,7 +66,7 @@ rt_err_t rt_hwcrypto_symmetric_crypt(struct rt_hwcrypto_ctx *ctx, hwcrypto_mode
}
if (mode != HWCRYPTO_MODE_ENCRYPT && mode != HWCRYPTO_MODE_DECRYPT)
{
return -EINVAL;
return -RT_EINVAL;
}
/* Input information packaging */

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@ -187,7 +187,7 @@ void arm_gic_clear_pending_irq(rt_uint32_t index, int irq)
}
}
void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config)
void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config)
{
rt_uint32_t icfgr;
rt_uint32_t shift;
@ -428,8 +428,8 @@ rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index)
void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group)
{
uint32_t igroupr;
uint32_t shift;
rt_uint32_t igroupr;
rt_uint32_t shift;
RT_ASSERT(index < ARM_GIC_MAX_NR);
RT_ASSERT(group <= 1U);

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@ -151,7 +151,7 @@ rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq);
void arm_gic_set_pending_irq(rt_uint32_t index, int irq);
void arm_gic_clear_pending_irq(rt_uint32_t index, int irq);
void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config);
void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config);
rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq);
void arm_gic_clear_active(rt_uint32_t index, int irq);

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@ -782,7 +782,7 @@ rt_err_t rt_thread_control(rt_thread_t thread, int cmd, void *arg)
return RT_ERROR;
}
cpu = (rt_uint8_t)(size_t)arg;
cpu = (rt_uint8_t)(rt_size_t)arg;
thread->bind_cpu = cpu > RT_CPUS_NR? RT_CPUS_NR : cpu;
break;
}