修复部分bsp编译报错
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06fdc108b4
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@ -44,7 +44,7 @@ static struct clk plla = {
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static struct clk mck = {
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"mck",
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0,
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NULL,
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RT_NULL,
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{RT_NULL, RT_NULL},
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};
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@ -32,7 +32,7 @@ typedef struct
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{
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FSpi_Ctrl_t spi_ctrl;
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struct rt_spi_bus spi_bus;
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uint16_t spi_cs_pin;
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rt_uint16_t spi_cs_pin;
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spi_cs_handler_t spi_cs_handler;
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} ft2004_spi_class;
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@ -214,7 +214,7 @@ static const struct rt_spi_ops ft2004_spi_ops =
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/**
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* Attach the spi device to SPI bus, this function must be used after initialization.
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*/
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rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin)
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rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint16_t cs_gpio_pin)
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{
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rt_err_t result;
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struct rt_spi_device *spi_device;
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@ -19,7 +19,7 @@
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#define SPI_BUS_NAME "spi0"
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#define SPI_DEV_NAME "S25FS256"
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rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin);
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rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint16_t cs_gpio_pin);
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#ifdef __cplusplus
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extern "C"
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@ -75,7 +75,7 @@ rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluste
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void send_core_isg(void)
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{
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for (size_t i = 0; i <= 0xf; i++)
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for (rt_size_t i = 0; i <= 0xf; i++)
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{
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/* code */
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rt_kprintf("i %x \r\n", i);
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@ -86,7 +86,7 @@ static inline rt_uint64_t __get_cntp_cval(void)
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* This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
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* param value: CNTP_CTL Register value to set
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*/
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static inline void __set_cntp_ctl(uint32_t value)
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static inline void __set_cntp_ctl(rt_uint32_t value)
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{
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__set_cp(15, 0, value, 14, 2, 1);
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}
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@ -158,7 +158,7 @@ static rt_err_t mcu_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
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tmp_gpio_cfg.func = GPIO_FUNC_IN;
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GPIO_Config(&tmp_gpio_cfg);
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GPIO_IntDisable(&tmp_gpio_cfg);
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GPIO_RegisterCallback(&tmp_gpio_cfg, NULL, NULL);
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GPIO_RegisterCallback(&tmp_gpio_cfg, RT_NULL, RT_NULL);
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return RT_EOK;
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}
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@ -189,7 +189,7 @@ const static struct rt_pin_ops _mcu_pin_ops =
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mcu_pin_attach_irq,
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mcu_pin_dettach_irq,
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mcu_pin_irq_enable,
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NULL,
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RT_NULL,
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};
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int rt_hw_pin_init(void)
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@ -241,7 +241,7 @@ int rt_hw_usart_init(void)
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RT_DEVICE_FLAG_RDWR
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| RT_DEVICE_FLAG_INT_RX
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| RT_DEVICE_FLAG_INT_TX
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, NULL);
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, RT_NULL);
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RT_ASSERT(result == RT_EOK);
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}
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@ -16,6 +16,7 @@
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <sys/time.h>
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#include "slcd_rhe6616tp01.h"
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@ -14,7 +14,8 @@
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#include <rthw.h>
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#include <string.h>
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#include <drivers/hwtimer.h>
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#include "raspi.h"
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#include <raspi.h>
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#include <sys/time.h>
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#ifdef BSP_USING_HDMI
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#include "drv_fb.h"
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@ -368,7 +369,7 @@ int test_rtc(void)
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{
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#ifdef BSP_USING_RTC
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rt_kprintf("Hello Test RTC!\n");
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uint8_t i;
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rt_uint8_t i;
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time_t now;
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rt_err_t ret = RT_EOK;
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@ -142,7 +142,7 @@ static inline rt_uint32_t read_cntctrl(void)
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return val;
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}
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static inline uint32_t write_cntctrl(uint32_t val)
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static inline rt_uint32_t write_cntctrl(rt_uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
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@ -66,7 +66,7 @@ void rt_hw_interrupt_init(void)
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for (index = 0; index < MAX_HANDLERS; index ++)
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{
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isr_table[index].handler = default_isr_handler;
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isr_table[index].param = NULL;
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isr_table[index].param = RT_NULL;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
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isr_table[index].counter = 0;
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@ -22,9 +22,9 @@ struct hwcrypto_gcm;
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struct hwcrypto_gcm_ops
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{
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rt_err_t (*start)(struct hwcrypto_gcm *gcm_ctx,
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const unsigned char *add, size_t add_len); /**< Set additional data. start GCM operation */
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const unsigned char *add, rt_size_t add_len); /**< Set additional data. start GCM operation */
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rt_err_t (*finish)(struct hwcrypto_gcm *gcm_ctx,
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const unsigned char *tag, size_t tag_len); /**< finish GCM operation. get tag */
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const unsigned char *tag, rt_size_t tag_len); /**< finish GCM operation. get tag */
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};
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/**
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@ -66,7 +66,7 @@ rt_err_t rt_hwcrypto_symmetric_crypt(struct rt_hwcrypto_ctx *ctx, hwcrypto_mode
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}
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if (mode != HWCRYPTO_MODE_ENCRYPT && mode != HWCRYPTO_MODE_DECRYPT)
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{
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return -EINVAL;
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return -RT_EINVAL;
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}
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/* Input information packaging */
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@ -187,7 +187,7 @@ void arm_gic_clear_pending_irq(rt_uint32_t index, int irq)
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}
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}
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void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config)
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void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config)
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{
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rt_uint32_t icfgr;
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rt_uint32_t shift;
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@ -428,8 +428,8 @@ rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index)
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void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group)
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{
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uint32_t igroupr;
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uint32_t shift;
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rt_uint32_t igroupr;
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rt_uint32_t shift;
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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RT_ASSERT(group <= 1U);
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@ -151,7 +151,7 @@ rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq);
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void arm_gic_set_pending_irq(rt_uint32_t index, int irq);
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void arm_gic_clear_pending_irq(rt_uint32_t index, int irq);
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void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config);
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void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config);
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rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq);
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void arm_gic_clear_active(rt_uint32_t index, int irq);
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@ -782,7 +782,7 @@ rt_err_t rt_thread_control(rt_thread_t thread, int cmd, void *arg)
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return RT_ERROR;
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}
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cpu = (rt_uint8_t)(size_t)arg;
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cpu = (rt_uint8_t)(rt_size_t)arg;
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thread->bind_cpu = cpu > RT_CPUS_NR? RT_CPUS_NR : cpu;
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break;
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}
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