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fix mips64 some bug

This commit is contained in:
bigmagic 2020-04-06 15:46:28 +08:00
parent 0f26ffa7a2
commit 990f731b77
16 changed files with 138 additions and 81 deletions
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22
bsp/ls2kdev/.config
View File

@ -21,11 +21,12 @@ CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=2048
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_PRIO=20
CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
CONFIG_RT_DEBUG_INIT_CONFIG=y
CONFIG_RT_DEBUG_INIT=1
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
@ -106,18 +107,7 @@ CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
@ -161,10 +151,6 @@ CONFIG_RT_USING_PIN=y
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
#

7
bsp/ls2kdev/drivers/board.c
View File

@ -70,10 +70,10 @@ void rt_hw_board_init(void)
/* init hardware interrupt */
rt_hw_interrupt_init();
#ifdef RT_USING_FPU
#ifdef RT_USING_FPU
/* init hardware fpu */
rt_hw_fpu_init();
#endif
#endif
#ifdef RT_USING_SERIAL
/* init hardware UART device */
@ -88,8 +88,7 @@ void rt_hw_board_init(void)
/* init operating system timer */
rt_hw_timer_init();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif

2
bsp/ls2kdev/drivers/board.h
View File

@ -16,7 +16,7 @@
extern unsigned char __bss_end;
#define CPU_HZ (100 * 1000 * 1000)
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_BEGIN KSEG1BASE//(void*)&__bss_end
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
void rt_hw_board_init(void);

2
bsp/ls2kdev/mipssim_ram.lds → bsp/ls2kdev/ls2k_ram.lds
View File

@ -14,7 +14,7 @@ GROUP(-lgcc -lc)
ENTRY(_start)
SECTIONS
{
. = 0x80200000 ;
. = 0xffffffff82000000 ;
.text :
{
__ebase_entry = .;

11
bsp/ls2kdev/rtconfig.h
View File

@ -17,9 +17,11 @@
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 2048
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_PRIO 20
#define RT_TIMER_THREAD_STACK_SIZE 2048
#define RT_DEBUG
#define RT_DEBUG_INIT_CONFIG
#define RT_DEBUG_INIT 1
/* Inter-Thread communication */
@ -71,12 +73,6 @@
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 16
#define RT_USING_DFS_DEVFS
/* Device Drivers */
@ -93,7 +89,6 @@
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_POSIX
/* Network */

8
bsp/ls2kdev/rtconfig.py
View File

@ -40,10 +40,10 @@ OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
READELF = PREFIX + 'readelf'
DEVICE = ' -march=mips64r2 -mabi=64 -msoft-float'
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T mipssim_ram.lds'
DEVICE = ' -march=mips64r2 -mabi=64 -msoft-float -EL'
CFLAGS = DEVICE + ' -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls2k_ram.lds'
CXXFLAGS = CFLAGS
CPATH = ''

4
libcpu/mips/common/asm.h
View File

@ -261,7 +261,11 @@ symbol = value
#define LONG_SRAV srav
#define LONG .word
#ifdef ARCH_MIPS64
#define LONGSIZE 8
#else
#define LONGSIZE 4
#endif
#define LONGMASK 3
#define LONGLOG 2

24
libcpu/mips/common/context_gcc.S
View File

@ -25,11 +25,11 @@
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
MTC0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
REG_S sp, 0(a0) /* store sp in preempted tasks TCB */
REG_L sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
@ -39,7 +39,7 @@ rt_hw_context_switch:
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
REG_L sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
@ -50,17 +50,17 @@ rt_hw_context_switch_to:
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
PTR_LA t0, rt_thread_switch_interrupt_flag
REG_L t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
@ -78,7 +78,7 @@ mips_irq_handle:
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
la sp, _system_stack
PTR_LA sp, _system_stack
jal rt_interrupt_enter
nop
@ -96,7 +96,7 @@ mips_irq_handle:
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and do not return
*/
la k0, rt_thread_switch_interrupt_flag
PTR_LA k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
@ -106,12 +106,12 @@ mips_irq_handle:
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
PTR_LA k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted task TCB */
la k0, rt_interrupt_to_thread
PTR_LA k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task stack pointer */

4
libcpu/mips/common/entry_gcc.S
View File

@ -31,8 +31,8 @@ _start:
PTR_LA ra, _rtthread_entry
/* disable interrupt */
mtc0 zero, CP0_CAUSE
mtc0 zero, CP0_STATUS # Set CPU to disable interrupt.
MTC0 zero, CP0_CAUSE
MTC0 zero, CP0_STATUS # Set CPU to disable interrupt.
ehb
#ifdef ARCH_MIPS64

17
libcpu/mips/common/exception.c
View File

@ -19,10 +19,10 @@
/*@{*/
extern rt_uint32_t __ebase_entry;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
extern rt_ubase_t __ebase_entry;
rt_ubase_t rt_interrupt_from_thread;
rt_ubase_t rt_interrupt_to_thread;
rt_ubase_t rt_thread_switch_interrupt_flag;
rt_base_t rt_hw_interrupt_disable(void)
{
@ -101,7 +101,10 @@ static void install_default_exception_handler(void)
int rt_hw_exception_init(void)
{
rt_uint32_t ebase = (rt_uint32_t)&__ebase_entry;
rt_ubase_t ebase = (rt_ubase_t)&__ebase_entry;
#ifdef ARCH_MIPS64
ebase |= 0xffffffff00000000;
#endif
write_c0_ebase(ebase);
clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL);
clear_c0_status(ST0_IM | ST0_IE);
@ -114,12 +117,12 @@ int rt_hw_exception_init(void)
void rt_general_exc_dispatch(struct pt_regs *regs)
{
rt_uint32_t cause, exccode;
rt_ubase_t cause, exccode;
exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
if (exccode == 0) {
rt_uint32_t status, pending;
rt_ubase_t status, pending;
status = read_c0_status();
pending = (cause & CAUSEF_IP) & (status & ST0_IM);
if (pending & CAUSEF_IP0)

13
libcpu/mips/common/exception_gcc.S
View File

@ -7,6 +7,11 @@
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
.section ".exc_vectors", "ax"
.extern tlb_refill_handler
@ -45,15 +50,15 @@ irq_exception:
/* general exception handler */
_general_exception_handler:
.set noreorder
la $k0, mips_irq_handle
jr $k0
PTR_LA k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la $k0, mips_irq_handle
jr $k0
PTR_LA k0, mips_irq_handle
jr k0
nop
.set reorder

9
libcpu/mips/common/mips_addrspace.h
View File

@ -75,6 +75,12 @@
#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
#define KUSEGBASE 0xffffffff00000000
#define KSEG0BASE 0xffffffff80000000
#define KSEG1BASE 0xffffffffa0000000
#define KSEG2BASE 0xffffffffc0000000
#define KSEG3BASE 0xffffffffe0000000
#else
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
@ -96,8 +102,6 @@
#define CKSEG2 0xc0000000
#define CKSEG3 0xe0000000
#endif
/*
* Memory segments (32bit kernel mode addresses)
* These are the traditional names used in the 32-bit universe.
@ -108,6 +112,7 @@
#define KSEG2BASE 0xc0000000
#define KSEG3BASE 0xe0000000
#endif
/*

46
libcpu/mips/common/mips_regs.h
View File

@ -10,13 +10,14 @@
#ifndef _MIPS_REGS_H_
#define _MIPS_REGS_H_
#include <rtconfig.h>
#define REG_A0 4
#define REG_SP 29
#define REG_GP 28
#define REG_FP 30
#define REG_RA 31
#ifdef ARCH_MIPS64
#define zero $0 /* wired zero */
#define AT $1 /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* return value */
@ -56,6 +57,49 @@
#define s8 $30 /* same like fp! */
#define ra $31 /* return address */
#else
#define zero $0 /* wired zero */
#define AT $at /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* return value - caller saved */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
#define ta0 $8
#define a5 $9
#define ta1 $9
#define a6 $10
#define ta2 $10
#define a7 $11
#define ta3 $11
#define t0 $12 /* caller saved */
#define t1 $13
#define t2 $14
#define t3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25 /* callee address for PIC/temp */
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel temporary */
#define k1 $27
#define gp $28 /* global pointer - caller saved for PIC */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* callee saved */
#define ra $31 /* return address */
#endif
#define fv0 $f0 /* return value */
#define fv0f $f1
#define fv1 $f2

25
libcpu/mips/common/ptrace.h
View File

@ -14,6 +14,8 @@
#include "asm.h"
#include "mips_regs.h"
#define HI_LO_SIZE 4
#define FP_REG_SIZE 8
#define NUM_FPU_REGS 16
@ -27,6 +29,7 @@ struct mips_fpu_struct {
};
struct pt_regs {
#ifndef ARCH_MIPS64
/* Only O32 Need This! */
/* Pad bytes for argument save space on the stack. */
rt_uint32_t pad0[8];
@ -41,6 +44,18 @@ struct pt_regs {
rt_uint32_t cp0_badvaddr;
rt_uint32_t cp0_cause;
rt_uint32_t cp0_epc;
#else
/* Saved main processor registers. */
unsigned long regs[32];
/* Saved special registers. */
rt_uint32_t cp0_status;
rt_uint32_t hi;
rt_uint32_t lo;
unsigned long cp0_badvaddr;
rt_uint32_t cp0_cause;
unsigned long cp0_epc;
#endif
#ifdef RT_USING_FPU
/* FPU Registers */
@ -52,7 +67,7 @@ struct pt_regs {
#endif
/* Note: For call stack o32 ABI has 0x8 shadowsoace Here */
#define PT_R0 (0x8 * LONGSIZE) /* 0 */
#define PT_R0 (0x0 * LONGSIZE) /* 0 */
#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */
#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */
#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */
@ -89,8 +104,8 @@ struct pt_regs {
* Saved special registers
*/
#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */
#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */
#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */
#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */
#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */
#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */
#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */
#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */
@ -115,9 +130,9 @@ struct pt_regs {
#define PT_FPU_R28 ((PT_FPU_R26) + FP_REG_SIZE)
#define PT_FPU_R30 ((PT_FPU_R28) + FP_REG_SIZE)
#define PT_FPU_FCSR31 ((PT_FPU_R30) + FP_REG_SIZE)
#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + LONGSIZE)
#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + 4)
#define PT_FPU_END ((PT_FPU_PAD0) + LONGSIZE)
#define PT_FPU_END ((PT_FPU_PAD0) + 4)
#define PT_SIZE PT_FPU_END
#else
#define PT_SIZE PT_REG_END

21
libcpu/mips/common/stack.c
View File

@ -16,8 +16,8 @@ register rt_uint32_t $GP __asm__ ("$28");
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
static rt_uint32_t wSR=0;
static rt_uint32_t wGP;
static rt_ubase_t wSR=0;
static rt_ubase_t wGP;
rt_uint8_t *stk;
struct pt_regs *pt;
@ -25,26 +25,27 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
rt_uint32_t i;
/* Get stack aligned */
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stack_addr, 8);
stk -= sizeof(struct pt_regs);
pt = (struct pt_regs*)stk;
#ifndef ARCH_MIPS64
for (i = 0; i < 8; ++i)
{
pt->pad0[i] = 0xdeadbeef;
}
#endif
/* Fill Stack register numbers */
for (i = 0; i < 32; ++i)
{
pt->regs[i] = 0xdeadbeef;
}
pt->regs[REG_SP] = (rt_uint32_t)stk;
pt->regs[REG_A0] = (rt_uint32_t)parameter;
pt->regs[REG_GP] = (rt_uint32_t)$GP;
pt->regs[REG_FP] = (rt_uint32_t)0x0;
pt->regs[REG_RA] = (rt_uint32_t)texit;
pt->regs[REG_SP] = (rt_ubase_t)stk;
pt->regs[REG_A0] = (rt_ubase_t)parameter;
pt->regs[REG_GP] = (rt_ubase_t)$GP;
pt->regs[REG_FP] = (rt_ubase_t)0x0;
pt->regs[REG_RA] = (rt_ubase_t)texit;
pt->hi = 0x0;
pt->lo = 0x0;
@ -53,7 +54,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
pt->cp0_status |= (ST0_CU1 | ST0_FR);
#endif
pt->cp0_cause = read_c0_cause();
pt->cp0_epc = (rt_uint32_t)tentry;
pt->cp0_epc = (rt_ubase_t)tentry;
pt->cp0_badvaddr = 0x0;
return stk;

4
libcpu/mips/common/stackframe.h
View File

@ -159,11 +159,11 @@
.endm
.macro RESTORE_TEMP
LONG_L $24, PT_LO(sp)
lw $24, PT_LO(sp)
LONG_L $8, PT_R8(sp)
LONG_L $9, PT_R9(sp)
mtlo $24
LONG_L $24, PT_HI(sp)
lw $24, PT_HI(sp)
LONG_L $10, PT_R10(sp)
LONG_L $11, PT_R11(sp)
mthi $24