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[bsp][stm32][libraries]add stm32h5

This commit is contained in:
Macro 2024-08-15 10:48:18 +08:00
parent 3e246caa1c
commit 98c6e77c2d
6 changed files with 270 additions and 9 deletions
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103
bsp/stm32/libraries/HAL_Drivers/drivers/config/h5/dma_config.h Normal file
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@ -0,0 +1,103 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-14 Macro first version
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 channel0 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_DMA_RX_IRQHandler GPDMA1_Channel0_IRQHandler
#define UART3_RX_DMA_RCC RCC_AHB1ENR_GPDMA1EN
#define UART3_RX_DMA_INSTANCE GPDMA1_Channel0
#define UART3_RX_DMA_REQUEST GPDMA1_REQUEST_USART3_RX
#define UART3_RX_DMA_IRQ GPDMA1_Channel0_IRQn
#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_DMA_TX_IRQHandler GPDMA1_Channel0_IRQHandler
#define UART1_TX_DMA_RCC RCC_AHB1ENR_GPDMA1EN
#define UART1_TX_DMA_INSTANCE GPDMA1_Channel0
#define UART1_TX_DMA_REQUEST GPDMA1_REQUEST_USART1_TX
#define UART1_TX_DMA_IRQ GPDMA1_Channel0_IRQn
#endif
/* DMA1 channel1 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler GPDMA1_Channel1_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1ENR_GPDMA1EN
#define UART1_RX_DMA_INSTANCE GPDMA1_Channel1
#define UART1_RX_DMA_REQUEST GPDMA1_REQUEST_USART1_RX
#define UART1_RX_DMA_IRQ GPDMA1_Channel1_IRQn
#endif
/* DMA1 channel2 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler GPDMA1_Channel2_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_GPDMA1EN
#define SPI1_TX_DMA_INSTANCE GPDMA1_Channel2
#define SPI1_TX_DMA_REQUEST GPDMA1_REQUEST_SPI1_TX
#define SPI1_TX_DMA_IRQ GPDMA1_Channel2_IRQn
#endif
/* DMA1 channel3 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_IRQHandler GPDMA1_Channel3_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_GPDMA1EN
#define SPI1_RX_DMA_INSTANCE GPDMA1_Channel3
#define SPI1_RX_DMA_REQUEST GPDMA1_REQUEST_SPI1_RX
#define SPI1_RX_DMA_IRQ GPDMA1_Channel3_IRQn
#endif
/* DMA1 channel4 */
/* DMA1 channel5 */
/* DMA1 channel6 */
/* DMA1 channel7 */
/* DMA2 channel0 */
/* DMA2 channel1 */
/* DMA2 channel2 */
/* DMA2 channel3 */
/* DMA2 channel4 */
/* DMA2 channel5 */
/* DMA2 channel6 */
/* DMA2 channel7 */
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

129
bsp/stm32/libraries/HAL_Drivers/drivers/config/h5/spi_config.h Normal file
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@ -0,0 +1,129 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-14 Macro first version
*/
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.irq_type = SPI1_IRQn, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.request = SPI1_TX_DMA_REQUEST, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.request = SPI1_RX_DMA_REQUEST, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
.irq_type = SPI2_IRQn, \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \
.request = SPI2_TX_DMA_REQUEST, \
.dma_irq = SPI2_TX_DMA_IRQ, \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \
.request = SPI2_RX_DMA_REQUEST, \
.dma_irq = SPI2_RX_DMA_IRQ, \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
.irq_type = SPI3_IRQn, \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \
.request = SPI3_TX_DMA_REQUEST, \
.dma_irq = SPI3_TX_DMA_IRQ, \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \
.request = SPI3_RX_DMA_REQUEST, \
.dma_irq = SPI3_RX_DMA_IRQ, \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

3
bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h
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@ -7,6 +7,7 @@
* Date Author Notes
* 2018-10-30 SummerGift first version
* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
* 2024-08-15 Macro Porting for stm32h5xx
*/
#ifndef __DRV_CONFIG_H__
@ -149,7 +150,9 @@ extern "C" {
#include "u5/pwm_config.h"
#include "u5/usbd_config.h"
#elif defined(SOC_SERIES_STM32H5)
#include "h5/dma_config.h"
#include "h5/uart_config.h"
#include "h5/spi_config.h"
#include "h5/pwm_config.h"
#include "h5/adc_config.h"
#elif defined(SOC_SERIES_STM32MP1)

4
bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h
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@ -7,6 +7,7 @@
* Date Author Notes
* 2018-11-10 SummerGift first version
* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
* 2024-08-15 Macro add stm32h5
*/
#ifndef __DRV_DMA_H_
@ -39,7 +40,8 @@ struct dma_config {
#endif
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5)
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5)\
|| defined(SOC_SERIES_STM32H5)
rt_uint32_t request;
#endif
};

35
bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.c
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@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2021-06-01 KyleChan first version
* 2024-08-15 Macro add stm32h5
*/
#include "board.h"
@ -516,7 +517,7 @@ static void uart_isr(struct rt_serial_device *serial)
}
#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
&& !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
&& !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
&& !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) && !defined(SOC_SERIES_STM32H5)
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
{
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
@ -1130,7 +1131,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
|| defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
|| defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H5)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
@ -1140,7 +1141,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
#endif
#if defined(DMAMUX1) && (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB))
#if defined(DMAMUX1) && (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H5))
/* enable DMAMUX clock for L4+ and G4 */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
#elif defined(SOC_SERIES_STM32MP1)
@ -1165,27 +1166,49 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Channel = dma_config->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H5)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Request = dma_config->request;
#endif
#if defined(SOC_SERIES_STM32H5)
DMA_Handle->Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
#else
DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
#endif
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
#if defined(SOC_SERIES_STM32H5)
DMA_Handle->Init.SrcInc = DMA_SINC_FIXED;
DMA_Handle->Init.DestInc = DMA_DINC_INCREMENTED;
DMA_Handle->Init.Mode = DMA_PFCTRL;
#elif
DMA_Handle->Init.Mode = DMA_CIRCULAR;
#endif
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
#if defined(SOC_SERIES_STM32H5)
DMA_Handle->Init.SrcInc = DMA_SINC_INCREMENTED;
DMA_Handle->Init.DestInc = DMA_DINC_FIXED;
#endif
DMA_Handle->Init.Mode = DMA_NORMAL;
}
#if defined(SOC_SERIES_STM32H5)
DMA_Handle->Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
DMA_Handle->Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
DMA_Handle->Init.SrcBurstLength = 1;
DMA_Handle->Init.DestBurstLength = 1;
DMA_Handle->Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT1;
DMA_Handle->Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
DMA_Handle->Init.Priority = DMA_LOW_PRIORITY_MID_WEIGHT;
#else
DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
#endif
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
#endif

5
bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.h
View File

@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2021-06-01 KyleChan first version
* 2024-08-15 Macro add stm32h5
*/
#ifndef __DRV_USART_V2_H__
@ -22,7 +23,7 @@ int rt_hw_usart_init(void);
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
|| defined(SOC_SERIES_STM32G4)
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32H5)
#define UART_SET_TDR(__HANDLE__, __DATA__) ((__HANDLE__)->Instance->TDR = (__DATA__))
#define UART_GET_RDR(__HANDLE__, MASK) ((__HANDLE__)->Instance->RDR & MASK)
@ -34,7 +35,7 @@ int rt_hw_usart_init(void);
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2) \
|| defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H5)
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
|| defined(SOC_SERIES_STM32MP1)