[BSP] add spi bus driver. | 添加spi总线驱动.
This commit is contained in:
liu2guang
parent
5f81f8e771
commit
9826f07dfa
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@ -36,7 +36,7 @@ endchoice
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if BOARD_RT1050_EVK
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menu "RT1050_EVK Bsp Config"
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menu "Select uart device"
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menu "Select uart drivers"
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config RT_USING_UART1
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bool "Using uart1"
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select RT_USING_SERIAL
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@ -71,13 +71,32 @@ menu "Select uart device"
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default n
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endmenu
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#menu "SDRAM drive support"
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menu "Select spibus drivers"
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config RT_USING_SPIBUS1
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bool "Using spi1 bus"
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select RT_USING_SPI
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default n
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config RT_USING_SPIBUS2
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bool "Using spi2 bus"
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select RT_USING_SPI
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default n
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config RT_USING_SPIBUS3
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bool "Using spi3 bus"
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select RT_USING_SPI
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default n
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config RT_USING_SPIBUS4
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bool "Using spi4 bus"
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select RT_USING_SPI
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default y
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endmenu
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#menu "SDRAM driver support"
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config RT_USING_SDRAM
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bool "Using sdram"
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default y
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#endmenu
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#menu "RTC drive support"
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#menu "RTC driver support"
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config RT_USING_RTC_HP
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bool "Using hp rtc"
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select RT_USING_RTC
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@ -102,7 +121,7 @@ endif
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if BOARD_RT1050_FIRE
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menu "RT1050_FIRE Bsp Config"
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menu "Select uart device"
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menu "Select uart drivers"
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config RT_USING_UART1
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bool "Using uart1"
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select RT_USING_SERIAL
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@ -137,13 +156,32 @@ menu "Select uart device"
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default n
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endmenu
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#menu "SDRAM drive support"
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menu "Select spibus drivers"
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config RT_USING_SPIBUS1
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bool "Using spi1 bus"
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select RT_USING_SPI
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default n
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config RT_USING_SPIBUS2
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bool "Using spi2 bus"
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select RT_USING_SPI
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default n
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config RT_USING_SPIBUS3
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bool "Using spi3 bus"
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select RT_USING_SPI
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default n
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config RT_USING_SPIBUS4
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bool "Using spi4 bus"
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select RT_USING_SPI
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default y
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endmenu
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#menu "SDRAM driver support"
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config RT_USING_SDRAM
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bool "Using sdram"
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default y
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#endmenu
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#menu "RTC drive support"
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#menu "RTC driver support"
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config RT_USING_RTC_HP
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bool "Using hp rtc"
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select RT_USING_RTC
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@ -17,6 +17,7 @@ CPPDEFINES = []
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if GetDepend('RT_USING_SDRAM'):
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src = src + ['./drv_sdram.c']
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# add pin driver code
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if GetDepend('RT_USING_PIN'):
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src += ['drv_pin.c']
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@ -24,6 +25,10 @@ if GetDepend('RT_USING_PIN'):
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if GetDepend('RT_USING_RTC_HP'):
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src = src + ['./drv_rtc.c']
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# add spibus driver code
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if GetDepend('RT_USING_SPI'):
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src += ['drv_spi_bus.c']
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if GetDepend('BOARD_RT1050_EVK'):
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src += ['hyper_flash_boot.c']
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@ -0,0 +1,336 @@
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/*
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* File : drv_spi_bus.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2013, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2018-03-27 Liuguang the first version.
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*/
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#include "drv_spi_bus.h"
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#include "fsl_common.h"
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#include "fsl_iomuxc.h"
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#include "fsl_lpspi.h"
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#ifdef RT_USING_SPI
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#define LPSPI_CLK_SOURCE (1U)
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#define LPSPI_CLK_SOURCE_DIVIDER (7U)
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#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
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#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
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#endif
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struct rt1050_spi
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{
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LPSPI_Type *base;
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struct rt_spi_configuration *cfg;
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};
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struct rt1050_hw_spi_cs
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{
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rt_uint32_t pin;
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};
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static uint32_t rt1050_get_lpspi_freq(void)
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{
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uint32_t freq = 0;
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/* CLOCK_GetMux(kCLOCK_LpspiMux):
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00b: derive clock from PLL3 PFD1 720M
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01b: derive clock from PLL3 PFD0 720M
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10b: derive clock from PLL2 528M
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11b: derive clock from PLL2 PFD2 396M
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*/
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switch(CLOCK_GetMux(kCLOCK_LpspiMux))
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{
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case 0:
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freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk);
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break;
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case 1:
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freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk);
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break;
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case 2:
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freq = CLOCK_GetFreq(kCLOCK_SysPllClk);
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break;
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case 3:
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freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk);
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break;
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}
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freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U);
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return freq;
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}
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static rt_err_t rt1050_spi_init(LPSPI_Type *base, struct rt_spi_configuration *cfg)
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{
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lpspi_master_config_t masterConfig;
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if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32)
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{
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return RT_EINVAL;
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}
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#if defined(RT_USING_SPIBUS1)
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if(base == LPSPI1)
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{
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IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_27_LPSPI1_SCK, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_27_LPSPI1_SCK, 0x10B0u);
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IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_28_LPSPI1_SDO, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_28_LPSPI1_SDO, 0x10B0u);
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IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_29_LPSPI1_SDI, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_29_LPSPI1_SDI, 0x10B0u);
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}
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#endif
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#if defined(RT_USING_SPIBUS2)
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if(base == LPSPI2)
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{
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IOMUXC_SetPinMux (IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK, 0x10B0u);
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IOMUXC_SetPinMux (IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0, 0x10B0u);
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IOMUXC_SetPinMux (IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI, 0x10B0u);
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/* Optional IO config */
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//IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_00_LPSPI2_SCK, 0U);
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//IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_00_LPSPI2_SCK, 0x10B0u);
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//IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_02_LPSPI2_SDO, 0U);
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//IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_02_LPSPI2_SDO, 0x10B0u);
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//IOMUXC_SetPinMux (IOMUXC_GPIO_EMC_03_LPSPI2_SDI, 0U);
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//IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_03_LPSPI2_SDI, 0x10B0u);
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}
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#endif
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#if defined(RT_USING_SPIBUS3)
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if(base == LPSPI3)
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{
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IOMUXC_SetPinMux (IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, 0x10B0u);
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IOMUXC_SetPinMux (IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, 0x10B0u);
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IOMUXC_SetPinMux (IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, 0x10B0u);
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}
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#endif
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#if defined(RT_USING_SPIBUS4)
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if(base == LPSPI4)
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{
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IOMUXC_SetPinMux (IOMUXC_GPIO_B0_01_LPSPI4_SDI, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LPSPI4_SDI, 0x10B0u);
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IOMUXC_SetPinMux (IOMUXC_GPIO_B0_02_LPSPI4_SDO, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LPSPI4_SDO, 0x10B0u);
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IOMUXC_SetPinMux (IOMUXC_GPIO_B0_03_LPSPI4_SCK, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LPSPI4_SCK, 0x10B0u);
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/* Optional IO config */
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//IOMUXC_SetPinMux (IOMUXC_GPIO_B1_07_LPSPI4_SCK, 0U);
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//IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_LPSPI4_SCK, 0x10B0u);
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//IOMUXC_SetPinMux (IOMUXC_GPIO_B1_06_LPSPI4_SDO, 0U);
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//IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_LPSPI4_SDO, 0x10B0u);
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//IOMUXC_SetPinMux (IOMUXC_GPIO_B1_05_LPSPI4_SDI, 0U);
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//IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_LPSPI4_SDI, 0x10B0u);
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}
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#endif
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LPSPI_MasterGetDefaultConfig(&masterConfig);
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masterConfig.baudRate = cfg->max_hz;
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masterConfig.bitsPerFrame = cfg->data_width;
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if(cfg->mode & RT_SPI_MSB)
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{
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masterConfig.direction = kLPSPI_MsbFirst;
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}
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else
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{
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masterConfig.direction = kLPSPI_LsbFirst;
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}
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if(cfg->mode & RT_SPI_CPHA)
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{
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masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge;
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}
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else
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{
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masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
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}
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if(cfg->mode & RT_SPI_CPOL)
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{
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masterConfig.cpol = kLPSPI_ClockPolarityActiveLow;
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}
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else
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{
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masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
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}
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masterConfig.pinCfg = kLPSPI_SdiInSdoOut;
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masterConfig.dataOutConfig = kLpspiDataOutTristate;
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masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate;
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masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate;
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masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate;
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LPSPI_MasterInit(base, &masterConfig, rt1050_get_lpspi_freq());
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base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK;
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return RT_EOK;
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}
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rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin)
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{
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rt_err_t ret;
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struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
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RT_ASSERT(spi_device != RT_NULL);
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struct rt1050_hw_spi_cs *cs_pin = (struct rt1050_hw_spi_cs *)rt_malloc(sizeof(struct rt1050_hw_spi_cs));
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RT_ASSERT(cs_pin != RT_NULL);
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cs_pin->pin = pin;
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rt_pin_mode(pin, PIN_MODE_OUTPUT);
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rt_pin_write(pin, PIN_HIGH);
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ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
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return ret;
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}
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static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
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{
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rt_err_t ret;
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struct rt1050_spi *spi = RT_NULL;
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RT_ASSERT(cfg != RT_NULL);
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RT_ASSERT(device != RT_NULL);
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spi = (struct rt1050_spi *)(device->bus->parent.user_data);
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spi->cfg = cfg;
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ret = rt1050_spi_init(spi->base, cfg);
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return ret;
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}
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static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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lpspi_transfer_t transfer;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(device->bus->parent.user_data != RT_NULL);
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struct rt1050_spi *spi = (struct rt1050_spi *)(device->bus->parent.user_data);
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struct rt1050_hw_spi_cs *cs = device->parent.user_data;
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if(message->cs_take)
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{
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rt_pin_write(cs->pin, PIN_LOW);
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}
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transfer.rxData = (uint8_t *)(message->recv_buf);
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transfer.txData = (uint8_t *)(message->send_buf);
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transfer.dataSize = message->length;
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status_t stat = LPSPI_MasterTransferBlocking(spi->base, &transfer);
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if(message->cs_release)
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{
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rt_pin_write(cs->pin, PIN_HIGH);
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}
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return message->length;
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}
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#if defined(RT_USING_SPIBUS1)
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static struct rt1050_spi spi1 =
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{
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.base = LPSPI1
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};
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static struct rt_spi_bus spi1_bus =
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{
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.parent.user_data = &spi1
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};
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#endif
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#if defined(RT_USING_SPIBUS2)
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static struct rt1050_spi spi2 =
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{
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.base = LPSPI2
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};
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static struct rt_spi_bus spi2_bus =
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{
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.parent.user_data = &spi2
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};
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#endif
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#if defined(RT_USING_SPIBUS3)
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static struct rt1050_spi spi3 =
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{
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.base = LPSPI3
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};
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static struct rt_spi_bus spi3_bus =
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{
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.parent.user_data = &spi3
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};
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#endif
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#if defined(RT_USING_SPIBUS4)
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static struct rt1050_spi spi4 =
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{
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.base = LPSPI4
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};
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static struct rt_spi_bus spi4_bus =
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{
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.parent.user_data = &spi4
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};
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#endif
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static struct rt_spi_ops rt1050_spi_ops =
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{
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.configure = spi_configure,
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.xfer = spixfer
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};
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int rt_hw_spi_bus_init(void)
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{
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#if defined(RT_USING_SPIBUS1) || defined(RT_USING_SPIBUS2) || \
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defined(RT_USING_SPIBUS3) || defined(RT_USING_SPIBUS4)
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CLOCK_SetMux(kCLOCK_LpspiMux, LPSPI_CLK_SOURCE);
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CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLK_SOURCE_DIVIDER);
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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#endif
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#if defined(RT_USING_SPIBUS1)
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rt_spi_bus_register(&spi1_bus, "spibus1", &rt1050_spi_ops);
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#endif
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#if defined(RT_USING_SPIBUS2)
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rt_spi_bus_register(&spi2_bus, "spibus2", &rt1050_spi_ops);
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#endif
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#if defined(RT_USING_SPIBUS3)
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rt_spi_bus_register(&spi3_bus, "spibus3", &rt1050_spi_ops);
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#endif
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#if defined(RT_USING_SPIBUS4)
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rt_spi_bus_register(&spi4_bus, "spibus4", &rt1050_spi_ops);
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#endif
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return RT_EOK;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_spi_bus_init);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* File : drv_spi_bus.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006-2013, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-03-27 Liuguang the first version.
|
||||
*/
|
||||
|
||||
#ifndef __DRV_SPI_BUS_H__
|
||||
#define __DRV_SPI_BUS_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
int rt_hw_spi_bus_init(void);
|
||||
rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue