From 9779963c6db540b7d38eb05e3ea63d4568517a8f Mon Sep 17 00:00:00 2001
From: ACM32_MCU <90822414+ACM32-MCU@users.noreply.github.com>
Date: Mon, 28 Mar 2022 10:38:46 +0800
Subject: [PATCH] [libcpu/arm/cortex-m33]fix syscall_iar.S compiler error
(#5719)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
* 1. 新增了i2c/spi/rtc/crypto等驱动；2. 删除了部分文件中的未使用到的头文件包含; 3. 修改keil编译时pm文件atoi的头文件stdlib未包含的警告
* 修改文件格式
* BSP
1. 修改f4系列bsp的readme文件与工程文件
2. 修改f0系列源文件的版权信息、删除目前没有的库文件。
3. 其他
* 修改IAR环境下arm cortex-m33内核的syscall_iar.S文件编译错误
* 还原.gitignore文件
Co-authored-by: aisino2200 <90822414+aisino2200@users.noreply.github.com>
---
bsp/acm32f4xx-nucleo/project.ewp | 2302 +++++++++++++++++++++++++++
bsp/acm32f4xx-nucleo/project.eww | 10 +
bsp/acm32f4xx-nucleo/template.ewp | 2074 ++++++++++++++++++++++++
bsp/acm32f4xx-nucleo/template.eww | 10 +
libcpu/arm/cortex-m33/syscall_iar.S | 12 +-
5 files changed, 4404 insertions(+), 4 deletions(-)
create mode 100644 bsp/acm32f4xx-nucleo/project.ewp
create mode 100644 bsp/acm32f4xx-nucleo/project.eww
create mode 100644 bsp/acm32f4xx-nucleo/template.ewp
create mode 100644 bsp/acm32f4xx-nucleo/template.eww
diff --git a/bsp/acm32f4xx-nucleo/project.ewp b/bsp/acm32f4xx-nucleo/project.ewp
new file mode 100644
index 0000000000..39acf76ca0
--- /dev/null
+++ b/bsp/acm32f4xx-nucleo/project.ewp
@@ -0,0 +1,2302 @@
+
+ 3
+
+ rt-thread
+
+ ARM
+
+ 1
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+ General
+ 3
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+ 31
+ 1
+ 1
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+ 10
+ 1
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+ 31
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+ OBJCOPY
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+ 1
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+ CUSTOM
+ 3
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+ 0
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+ BUILDACTION
+ 1
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+ 1
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+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+ BILINK
+ 0
+
+
+
+
+ ACM32_HAL
+
+ $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_UART.c
+
+
+ $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_EXTI.c
+
+
+ $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_DMA.c
+
+
+ $PROJ_DIR$\libraries\Device\Startup_ACM32F4_iar.s
+
+
+ $PROJ_DIR$\libraries\Device\System_ACM32F4.c
+
+
+ $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_GPIO.c
+
+
+ $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_EFlash.c
+
+
+
+ Applications
+
+ $PROJ_DIR$\applications\main.c
+
+
+
+ Compiler
+
+ $PROJ_DIR$\..\..\components\libc\compilers\common\time.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\common\stdlib.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscalls.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c
+
+
+ $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c
+
+
+
+ CPU
+
+ $PROJ_DIR$\..\..\libcpu\arm\common\div0.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\cortex-m33\context_iar.S
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\cortex-m33\syscall_iar.S
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\cortex-m33\trustzone.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\cortex-m33\cpuport.c
+
+
+
+ DeviceDrivers
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\waitqueue.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\pipe.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\ringblk_buf.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\ringbuffer.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\workqueue.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\misc\pin.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\serial\serial.c
+
+
+
+ Drivers
+
+ $PROJ_DIR$\drivers\board.c
+
+
+ $PROJ_DIR$\drivers\drv_gpio.c
+
+
+ $PROJ_DIR$\drivers\drv_uart.c
+
+
+
+ Finsh
+
+ $PROJ_DIR$\..\..\components\finsh\shell.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\msh.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\cmd.c
+
+
+
+ Kernel
+
+ $PROJ_DIR$\..\..\src\components.c
+
+
+ $PROJ_DIR$\..\..\src\kservice.c
+
+
+ $PROJ_DIR$\..\..\src\clock.c
+
+
+ $PROJ_DIR$\..\..\src\object.c
+
+
+ $PROJ_DIR$\..\..\src\irq.c
+
+
+ $PROJ_DIR$\..\..\src\idle.c
+
+
+ $PROJ_DIR$\..\..\src\ipc.c
+
+
+ $PROJ_DIR$\..\..\src\mem.c
+
+
+ $PROJ_DIR$\..\..\src\mempool.c
+
+
+ $PROJ_DIR$\..\..\src\scheduler.c
+
+
+ $PROJ_DIR$\..\..\src\timer.c
+
+
+ $PROJ_DIR$\..\..\src\thread.c
+
+
+ $PROJ_DIR$\..\..\src\device.c
+
+
+
+ POSIX
+
+
diff --git a/bsp/acm32f4xx-nucleo/project.eww b/bsp/acm32f4xx-nucleo/project.eww
new file mode 100644
index 0000000000..c2cb02eb1e
--- /dev/null
+++ b/bsp/acm32f4xx-nucleo/project.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\project.ewp
+
+
+
+
+
diff --git a/bsp/acm32f4xx-nucleo/template.ewp b/bsp/acm32f4xx-nucleo/template.ewp
new file mode 100644
index 0000000000..bbd1adf10c
--- /dev/null
+++ b/bsp/acm32f4xx-nucleo/template.ewp
@@ -0,0 +1,2074 @@
+
+
+ 3
+
+ rt-thread
+
+ ARM
+
+ 1
+
+ General
+ 3
+
+ 31
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
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+
+
+ ICCARM
+ 2
+
+ 35
+ 1
+ 1
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+
+
+
+ AARM
+ 2
+
+ 10
+ 1
+ 1
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+
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+
+
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+ OBJCOPY
+ 0
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+ 1
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+ CUSTOM
+ 3
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+ 0
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+ BICOMP
+ 0
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+
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+ BUILDACTION
+ 1
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+ ILINK
+ 0
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+ 22
+ 1
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+ 0
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+ 0
+ 1
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+ BILINK
+ 0
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+
+
+
+ Release
+
+ ARM
+
+ 0
+
+ General
+ 3
+
+ 31
+ 1
+ 0
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+
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+
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+
+
+
+ ICCARM
+ 2
+
+ 35
+ 1
+ 0
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+
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+
+
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+
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+
+
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+
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+
+
+
+
+
+ AARM
+ 2
+
+ 10
+ 1
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+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+ OBJCOPY
+ 0
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+ 1
+ 1
+ 0
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+
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+ CUSTOM
+ 3
+
+
+
+ 0
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+
+
+ BICOMP
+ 0
+
+
+
+ BUILDACTION
+ 1
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+
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+
+
+
+ ILINK
+ 0
+
+ 22
+ 1
+ 0
+
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+
+
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+
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+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+ BILINK
+ 0
+
+
+
+
diff --git a/bsp/acm32f4xx-nucleo/template.eww b/bsp/acm32f4xx-nucleo/template.eww
new file mode 100644
index 0000000000..bd036bb4c9
--- /dev/null
+++ b/bsp/acm32f4xx-nucleo/template.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\template.ewp
+
+
+
+
+
diff --git a/libcpu/arm/cortex-m33/syscall_iar.S b/libcpu/arm/cortex-m33/syscall_iar.S
index 53a6790ec1..7a058617ae 100644
--- a/libcpu/arm/cortex-m33/syscall_iar.S
+++ b/libcpu/arm/cortex-m33/syscall_iar.S
@@ -6,22 +6,25 @@
; * Change Logs:
; * Date Author Notes
; * 2019-10-25 tyx first version
+; * 2021-03-26 lxf modify bad instruction
; */
;/*
; * @addtogroup cortex-m33
; */
+
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
+ IMPORT rt_secure_svc_handle
+
;/*
; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
; */
-.global tzcall
-.type tzcall, %function
+ EXPORT tzcall
tzcall:
SVC 1 ;/* call SVC 1 */
BX LR
@@ -39,8 +42,7 @@ tzcall_entry:
syscall_entry:
BX LR ;/* return to user app */
-.global SVC_Handler
-.type SVC_Handler, %function
+ EXPORT SVC_Handler
SVC_Handler:
;/* get SP, save to R1 */
@@ -61,3 +63,5 @@ get_sp_done:
;/* if svc == 1, do TrustZone call */
CMP R0, #0x1
BEQ tzcall_entry
+
+ END