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attach #6166 (#6168)

This commit is contained in:
Man, Jianting (Meco) 2022-07-22 23:53:42 -04:00 committed by GitHub
parent f82705db1d
commit 9595df24f1
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GPG Key ID: 4AEE18F83AFDEB23
14 changed files with 188 additions and 182 deletions
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2
bsp/at32/libraries/rt_drivers/drv_wdt.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2021, RT-Thread Development Team * Copyright (c) 2006-2022, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

6
bsp/n32/libraries/.ignore_format.yml Normal file
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@ -0,0 +1,6 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- N32G45x_Firmware_Library

4
bsp/n32/libraries/n32_drivers/SConscript
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@ -40,10 +40,10 @@ if GetDepend(['RT_USING_DAC']):
if GetDepend(['RT_USING_CAN']): if GetDepend(['RT_USING_CAN']):
src += ['drv_can.c'] src += ['drv_can.c']
if GetDepend(['BSP_USING_RTC']): if GetDepend(['RT_USING_RTC']):
src += ['drv_rtc.c'] src += ['drv_rtc.c']
if GetDepend(['BSP_USING_WDT']): if GetDepend(['RT_USING_WDT']):
src += ['drv_wdt.c'] src += ['drv_wdt.c']
path = [cwd] path = [cwd]

24
bsp/n32/libraries/n32_drivers/drv_adc.c
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@ -49,21 +49,21 @@ static struct n32_adc_config adc_config[] =
ADC1, ADC1,
}, },
#endif #endif
#ifdef BSP_USING_ADC2 #ifdef BSP_USING_ADC2
{ {
"adc2", "adc2",
ADC2, ADC2,
}, },
#endif #endif
#ifdef BSP_USING_ADC3 #ifdef BSP_USING_ADC3
{ {
"adc3", "adc3",
ADC3, ADC3,
}, },
#endif #endif
#ifdef BSP_USING_ADC4 #ifdef BSP_USING_ADC4
{ {
"adc4", "adc4",
@ -85,7 +85,7 @@ static void n32_adc_init(struct n32_adc_config *config)
ADC_InitStructure.DatAlign = ADC_DAT_ALIGN_R; ADC_InitStructure.DatAlign = ADC_DAT_ALIGN_R;
ADC_InitStructure.ChsNumber = 1; ADC_InitStructure.ChsNumber = 1;
ADC_Init((ADC_Module*)config->adc_periph, &ADC_InitStructure); ADC_Init((ADC_Module*)config->adc_periph, &ADC_InitStructure);
/* Enable ADC */ /* Enable ADC */
ADC_Enable((ADC_Module*)config->adc_periph, ENABLE); ADC_Enable((ADC_Module*)config->adc_periph, ENABLE);
/* Check ADC Ready */ /* Check ADC Ready */
@ -117,9 +117,9 @@ static rt_err_t n32_adc_convert(struct rt_adc_device *device, rt_uint32_t channe
return RT_EINVAL; return RT_EINVAL;
} }
config = (struct n32_adc_config *)(device->parent.user_data); config = (struct n32_adc_config *)(device->parent.user_data);
ADC_ConfigRegularChannel((ADC_Module*)config->adc_periph, channel, 1, ADC_SAMP_TIME_239CYCLES5); ADC_ConfigRegularChannel((ADC_Module*)config->adc_periph, channel, 1, ADC_SAMP_TIME_239CYCLES5);
/* Start ADC Software Conversion */ /* Start ADC Software Conversion */
ADC_EnableSoftwareStartConv((ADC_Module*)config->adc_periph, ENABLE); ADC_EnableSoftwareStartConv((ADC_Module*)config->adc_periph, ENABLE);
@ -129,7 +129,7 @@ static rt_err_t n32_adc_convert(struct rt_adc_device *device, rt_uint32_t channe
ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC); ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC);
ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_STR); ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_STR);
*value=ADC_GetDat((ADC_Module*)config->adc_periph); *value=ADC_GetDat((ADC_Module*)config->adc_periph);
return RT_EOK; return RT_EOK;
} }
@ -149,13 +149,13 @@ int rt_hw_adc_init(void)
/* Configure PC.00 PC.01 as analog input -------------------------*/ /* Configure PC.00 PC.01 as analog input -------------------------*/
GPIOInit(GPIOC, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_0 | GPIO_PIN_1); GPIOInit(GPIOC, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_0 | GPIO_PIN_1);
#endif /* BSP_USING_ADC1 */ #endif /* BSP_USING_ADC1 */
#if defined(BSP_USING_ADC2) #if defined(BSP_USING_ADC2)
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE); RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE);
/* Configure PC.02 PC.03 as analog input -------------------------*/ /* Configure PC.02 PC.03 as analog input -------------------------*/
GPIOInit(GPIOC, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_2 | GPIO_PIN_3); GPIOInit(GPIOC, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_2 | GPIO_PIN_3);
#endif /* BSP_USING_ADC2 */ #endif /* BSP_USING_ADC2 */
#if defined(BSP_USING_ADC3) #if defined(BSP_USING_ADC3)
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC3, ENABLE); RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC3, ENABLE);
/* Configure PD.10 PD.11 as analog input -------------------------*/ /* Configure PD.10 PD.11 as analog input -------------------------*/
@ -167,10 +167,10 @@ int rt_hw_adc_init(void)
/* Configure PD.12 PD.13 as analog input -------------------------*/ /* Configure PD.12 PD.13 as analog input -------------------------*/
GPIOInit(GPIOD, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_12 | GPIO_PIN_13); GPIOInit(GPIOD, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_12 | GPIO_PIN_13);
#endif /* BSP_USING_ADC4 */ #endif /* BSP_USING_ADC4 */
/* RCC_ADCHCLK_DIV16*/ /* RCC_ADCHCLK_DIV16*/
ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV16); ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV16);
for (i = 0; i < sizeof(adc_obj) / sizeof(adc_obj[0]); i++) for (i = 0; i < sizeof(adc_obj) / sizeof(adc_obj[0]); i++)
{ {
adc_obj[i].config = &adc_config[i]; adc_obj[i].config = &adc_config[i];
@ -183,6 +183,6 @@ int rt_hw_adc_init(void)
INIT_DEVICE_EXPORT(rt_hw_adc_init); INIT_DEVICE_EXPORT(rt_hw_adc_init);
#endif /* defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || defined(BSP_USING_ADC4) */ #endif /* defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || defined(BSP_USING_ADC4) */
#endif /* RT_USING_ADC */ #endif /* RT_USING_ADC */

88
bsp/n32/libraries/n32_drivers/drv_can.c
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@ -32,7 +32,7 @@
* *
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/ */
#include <drv_can.h> #include <drv_can.h>
#include "board.h" #include "board.h"
@ -63,10 +63,10 @@ static struct n32_can drv_can2 =
static rt_err_t setfilter(struct n32_can *pbxcan, CAN_FilterInitType *pconfig) static rt_err_t setfilter(struct n32_can *pbxcan, CAN_FilterInitType *pconfig)
{ {
CAN_FilterInitType CAN_FilterInitStruct; CAN_FilterInitType CAN_FilterInitStruct;
CAN_Module* CANx; CAN_Module* CANx;
CANx = pbxcan->CanHandle.Instance; CANx = pbxcan->CanHandle.Instance;
CAN_FilterInitStruct.Filter_Num = pconfig->Filter_Num; CAN_FilterInitStruct.Filter_Num = pconfig->Filter_Num;
CAN_FilterInitStruct.Filter_Mode = pconfig->Filter_Mode; CAN_FilterInitStruct.Filter_Mode = pconfig->Filter_Mode;
CAN_FilterInitStruct.Filter_Scale = pconfig->Filter_Scale; CAN_FilterInitStruct.Filter_Scale = pconfig->Filter_Scale;
@ -84,7 +84,7 @@ static rt_err_t setfilter(struct n32_can *pbxcan, CAN_FilterInitType *pconfig)
{ {
CAN2_InitFilter(&CAN_FilterInitStruct); CAN2_InitFilter(&CAN_FilterInitStruct);
} }
return RT_EOK; return RT_EOK;
} }
@ -97,12 +97,12 @@ static void bxcan_init(struct rt_can_device *can, struct can_configure *cfg)
drv_can = (struct n32_can *)can->parent.user_data; drv_can = (struct n32_can *)can->parent.user_data;
pbxcan = drv_can->CanHandle.Instance; pbxcan = drv_can->CanHandle.Instance;
uint32_t bps ; uint32_t bps ;
/* CAN register init */ /* CAN register init */
CAN_DeInit(pbxcan); CAN_DeInit(pbxcan);
/* Struct init*/ /* Struct init*/
CAN_InitStruct(&CAN_InitStructure); CAN_InitStruct(&CAN_InitStructure);
switch(cfg->baud_rate) switch(cfg->baud_rate)
@ -131,14 +131,14 @@ static void bxcan_init(struct rt_can_device *can, struct can_configure *cfg)
case CAN10kBaud: case CAN10kBaud:
bps = CAN_BAUDRATE_10K; bps = CAN_BAUDRATE_10K;
break; break;
default: default:
bps = CAN_BAUDRATE_100K; bps = CAN_BAUDRATE_100K;
break; break;
} }
CAN_InitStructure.BaudRatePrescaler = (uint32_t)(CAN_BTR_CALCULATE / bps); CAN_InitStructure.BaudRatePrescaler = (uint32_t)(CAN_BTR_CALCULATE / bps);
switch (cfg->mode) switch (cfg->mode)
{ {
case RT_CAN_MODE_NORMAL: case RT_CAN_MODE_NORMAL:
@ -153,12 +153,12 @@ static void bxcan_init(struct rt_can_device *can, struct can_configure *cfg)
case RT_CAN_MODE_LOOPBACKANLISEN: case RT_CAN_MODE_LOOPBACKANLISEN:
CAN_InitStructure.OperatingMode = CAN_Silent_LoopBack_Mode; CAN_InitStructure.OperatingMode = CAN_Silent_LoopBack_Mode;
break; break;
default: default:
CAN_InitStructure.OperatingMode = CAN_Normal_Mode; CAN_InitStructure.OperatingMode = CAN_Normal_Mode;
break; break;
} }
CAN_InitStructure.TTCM = DISABLE; CAN_InitStructure.TTCM = DISABLE;
CAN_InitStructure.ABOM = DISABLE; CAN_InitStructure.ABOM = DISABLE;
CAN_InitStructure.AWKUM = DISABLE; CAN_InitStructure.AWKUM = DISABLE;
@ -169,10 +169,10 @@ static void bxcan_init(struct rt_can_device *can, struct can_configure *cfg)
CAN_InitStructure.RSJW = CAN_RSJW_1tq; CAN_InitStructure.RSJW = CAN_RSJW_1tq;
CAN_InitStructure.TBS1 = CAN_TBS1_3tq; CAN_InitStructure.TBS1 = CAN_TBS1_3tq;
CAN_InitStructure.TBS2 = CAN_TBS2_2tq; CAN_InitStructure.TBS2 = CAN_TBS2_2tq;
/*Initializes the CAN */ /*Initializes the CAN */
CAN_Init(pbxcan, &CAN_InitStructure); CAN_Init(pbxcan, &CAN_InitStructure);
/* CAN filter init */ /* CAN filter init */
setfilter(drv_can, &drv_can->FilterConfig); setfilter(drv_can, &drv_can->FilterConfig);
@ -209,18 +209,18 @@ static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg)
drv_can = (struct n32_can *)can->parent.user_data; drv_can = (struct n32_can *)can->parent.user_data;
pbxcan = drv_can->CanHandle.Instance; pbxcan = drv_can->CanHandle.Instance;
if (pbxcan == CAN1) if (pbxcan == CAN1)
{ {
#ifdef BSP_USING_CAN1 #ifdef BSP_USING_CAN1
bxcan1_hw_init(); bxcan1_hw_init();
bxcan_init(&drv_can->device, &drv_can->device.config); bxcan_init(&drv_can->device, &drv_can->device.config);
#endif #endif
} }
else if (pbxcan == CAN2) else if (pbxcan == CAN2)
{ {
#ifdef BSP_USING_CAN2 #ifdef BSP_USING_CAN2
bxcan2_hw_init(); bxcan2_hw_init();
bxcan_init(&drv_can->device, &drv_can->device.config); bxcan_init(&drv_can->device, &drv_can->device.config);
#endif #endif
} }
@ -300,7 +300,7 @@ static rt_err_t control(struct rt_can_device *can, int cmd, void *arg)
if (CAN1 == drv_can->CanHandle.Instance) if (CAN1 == drv_can->CanHandle.Instance)
{ {
CAN_NVIC_Config(CAN1_SCE_IRQn, 0, 0, DISABLE); CAN_NVIC_Config(CAN1_SCE_IRQn, 0, 0, DISABLE);
} }
#ifdef CAN2 #ifdef CAN2
if (CAN2 == drv_can->CanHandle.Instance) if (CAN2 == drv_can->CanHandle.Instance)
@ -388,8 +388,8 @@ static rt_err_t control(struct rt_can_device *can, int cmd, void *arg)
{ {
drv_can->FilterConfig.Filter_Num = filter_cfg->items[i].hdr; drv_can->FilterConfig.Filter_Num = filter_cfg->items[i].hdr;
drv_can->FilterConfig.Filter_HighId = (filter_cfg->items[i].id >> 13) & 0xFFFF; drv_can->FilterConfig.Filter_HighId = (filter_cfg->items[i].id >> 13) & 0xFFFF;
drv_can->FilterConfig.Filter_LowId = ((filter_cfg->items[i].id << 3) | drv_can->FilterConfig.Filter_LowId = ((filter_cfg->items[i].id << 3) |
(filter_cfg->items[i].ide << 2) | (filter_cfg->items[i].ide << 2) |
(filter_cfg->items[i].rtr << 1)) & 0xFFFF; (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
drv_can->FilterConfig.FilterMask_HighId = (filter_cfg->items[i].mask >> 16) & 0xFFFF; drv_can->FilterConfig.FilterMask_HighId = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
drv_can->FilterConfig.FilterMask_LowId = filter_cfg->items[i].mask & 0xFFFF; drv_can->FilterConfig.FilterMask_LowId = filter_cfg->items[i].mask & 0xFFFF;
@ -482,7 +482,7 @@ static int sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno
TxMessage.StdId = pmsg->id; TxMessage.StdId = pmsg->id;
TxMessage.ExtId = 0; TxMessage.ExtId = 0;
} }
TxMessage.RTR = pmsg->rtr; TxMessage.RTR = pmsg->rtr;
TxMessage.IDE = pmsg->ide; TxMessage.IDE = pmsg->ide;
TxMessage.DLC = pmsg->len; TxMessage.DLC = pmsg->len;
@ -490,17 +490,17 @@ static int sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno
{ {
TxMessage.Data[i] = pmsg->data[i]; TxMessage.Data[i] = pmsg->data[i];
} }
CAN_TransmitMessage(pbxcan, &TxMessage); CAN_TransmitMessage(pbxcan, &TxMessage);
return RT_EOK; return RT_EOK;
} }
static int recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) static int recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
{ {
struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
int i; int i;
pmsg->ide = (rt_uint32_t) RxMessage.IDE; pmsg->ide = (rt_uint32_t) RxMessage.IDE;
if(RxMessage.IDE == 1) if(RxMessage.IDE == 1)
pmsg->id = RxMessage.ExtId; pmsg->id = RxMessage.ExtId;
else else
@ -512,7 +512,7 @@ static int recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
{ {
pmsg->data[i] = RxMessage.Data[i]; pmsg->data[i] = RxMessage.Data[i];
} }
return RT_EOK; return RT_EOK;
} }
@ -529,14 +529,14 @@ static const struct rt_can_ops canops =
struct rt_can_device bxcan1; struct rt_can_device bxcan1;
void n32_can1_irqhandler(void *param) void n32_can1_irqhandler(void *param)
{ {
CAN_Module* CANx; CAN_Module* CANx;
CANx = CAN1; CANx = CAN1;
/* receive data interrupt */ /* receive data interrupt */
if (CAN_GetIntStatus(CANx, CAN_INT_FMP0)) if (CAN_GetIntStatus(CANx, CAN_INT_FMP0))
{ {
CAN_ReceiveMessage(CANx, CAN_FIFO0, &RxMessage); CAN_ReceiveMessage(CANx, CAN_FIFO0, &RxMessage);
rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_RX_IND); rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_RX_IND);
@ -544,13 +544,13 @@ void n32_can1_irqhandler(void *param)
rt_kprintf("\r\nCan1 int RX happened!\r\n"); rt_kprintf("\r\nCan1 int RX happened!\r\n");
} }
/* send data interrupt */ /* send data interrupt */
else if (CAN_GetFlagSTS(CANx, CAN_FLAG_RQCPM0)) else if (CAN_GetFlagSTS(CANx, CAN_FLAG_RQCPM0))
{ {
rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 0 << 8); rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
CAN_ClearFlag(CANx, CAN_FLAG_RQCPM0); CAN_ClearFlag(CANx, CAN_FLAG_RQCPM0);
} }
/* data overflow interrupt */ /* data overflow interrupt */
else if (CAN_GetIntStatus(CANx, CAN_INT_FOV0)) else if (CAN_GetIntStatus(CANx, CAN_INT_FOV0))
{ {
rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_RXOF_IND); rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_RXOF_IND);
rt_kprintf("\r\nCan1 int RX OF happened!\r\n"); rt_kprintf("\r\nCan1 int RX OF happened!\r\n");
@ -563,7 +563,7 @@ void USB_HP_CAN1_TX_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
n32_can1_irqhandler(&drv_can1.device); n32_can1_irqhandler(&drv_can1.device);
/* leave interrupt */ /* leave interrupt */
rt_interrupt_leave(); rt_interrupt_leave();
} }
@ -574,7 +574,7 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
n32_can1_irqhandler(&drv_can1.device); n32_can1_irqhandler(&drv_can1.device);
/* leave interrupt */ /* leave interrupt */
rt_interrupt_leave(); rt_interrupt_leave();
} }
@ -583,14 +583,14 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
#ifdef BSP_USING_CAN2 #ifdef BSP_USING_CAN2
struct rt_can_device bxcan2; struct rt_can_device bxcan2;
void n32_can2_irqhandler(void *param) void n32_can2_irqhandler(void *param)
{ {
CAN_Module* CANx; CAN_Module* CANx;
CANx = CAN2; CANx = CAN2;
/* receive data interrupt */ /* receive data interrupt */
if (CAN_GetIntStatus(CANx, CAN_INT_FMP0)) if (CAN_GetIntStatus(CANx, CAN_INT_FMP0))
{ {
CAN_ReceiveMessage(CANx, CAN_FIFO0, &RxMessage); CAN_ReceiveMessage(CANx, CAN_FIFO0, &RxMessage);
rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_RX_IND); rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_RX_IND);
@ -598,18 +598,18 @@ void n32_can2_irqhandler(void *param)
rt_kprintf("\r\nCan2 int RX happened!\r\n"); rt_kprintf("\r\nCan2 int RX happened!\r\n");
} }
/* send data interrupt */ /* send data interrupt */
else if (CAN_GetFlagSTS(CANx, CAN_FLAG_RQCPM0)) else if (CAN_GetFlagSTS(CANx, CAN_FLAG_RQCPM0))
{ {
rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 0 << 8); rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
CAN_ClearFlag(CANx, CAN_FLAG_RQCPM0); CAN_ClearFlag(CANx, CAN_FLAG_RQCPM0);
} }
/* data overflow interrupt */ /* data overflow interrupt */
else if (CAN_GetIntStatus(CANx, CAN_INT_FOV0)) else if (CAN_GetIntStatus(CANx, CAN_INT_FOV0))
{ {
rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_RXOF_IND); rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_RXOF_IND);
rt_kprintf("\r\nCan2 int RX OF happened!\r\n"); rt_kprintf("\r\nCan2 int RX OF happened!\r\n");
} }
} }
void CAN2_TX_IRQHandler(void) void CAN2_TX_IRQHandler(void)
{ {
@ -617,7 +617,7 @@ void CAN2_TX_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
n32_can2_irqhandler(&drv_can2.device); n32_can2_irqhandler(&drv_can2.device);
/* leave interrupt */ /* leave interrupt */
rt_interrupt_leave(); rt_interrupt_leave();
} }
@ -628,7 +628,7 @@ void CAN2_RX0_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
n32_can2_irqhandler(&drv_can2.device); n32_can2_irqhandler(&drv_can2.device);
/* leave interrupt */ /* leave interrupt */
rt_interrupt_leave(); rt_interrupt_leave();
} }
@ -665,7 +665,7 @@ int rt_hw_can_init(void)
filterConf.Filter_Mode = CAN_Filter_IdMaskMode; filterConf.Filter_Mode = CAN_Filter_IdMaskMode;
filterConf.Filter_Scale = CAN_Filter_32bitScale; filterConf.Filter_Scale = CAN_Filter_32bitScale;
filterConf.Filter_Act = ENABLE; filterConf.Filter_Act = ENABLE;
#ifdef BSP_USING_CAN1 #ifdef BSP_USING_CAN1
filterConf.Filter_Num = 0; filterConf.Filter_Num = 0;

2
bsp/n32/libraries/n32_drivers/drv_can.h
View File

@ -32,7 +32,7 @@
* *
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/ */
#ifndef __DRV_CAN_H__ #ifndef __DRV_CAN_H__
#define __DRV_CAN_H__ #define __DRV_CAN_H__

24
bsp/n32/libraries/n32_drivers/drv_dac.c
View File

@ -51,7 +51,7 @@ static struct n32_dac_config dac_config[] =
DAC_CHANNEL_1, DAC_CHANNEL_1,
}, },
#endif #endif
#ifdef BSP_USING_DAC2 #ifdef BSP_USING_DAC2
{ {
"dac2", "dac2",
@ -80,32 +80,32 @@ static void n32_dac_init(struct n32_dac_config *config)
static rt_err_t n32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel) static rt_err_t n32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
{ {
RT_ASSERT(device != RT_NULL); RT_ASSERT(device != RT_NULL);
DAC_Enable(channel, ENABLE); DAC_Enable(channel, ENABLE);
return RT_EOK; return RT_EOK;
} }
static rt_err_t n32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel) static rt_err_t n32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
{ {
RT_ASSERT(device != RT_NULL); RT_ASSERT(device != RT_NULL);
DAC_Enable(channel, DISABLE); DAC_Enable(channel, DISABLE);
return RT_EOK; return RT_EOK;
} }
static rt_err_t n32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value) static rt_err_t n32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
{ {
RT_ASSERT(device != RT_NULL); RT_ASSERT(device != RT_NULL);
rt_uint16_t set_value = 0; rt_uint16_t set_value = 0;
set_value = (rt_uint16_t)*value; set_value = (rt_uint16_t)*value;
if(set_value > 4096) if(set_value > 4096)
{ {
set_value = 4096; set_value = 4096;
} }
/* Start DAC Channel conversion by software */ /* Start DAC Channel conversion by software */
if(channel == DAC_CHANNEL_1) if(channel == DAC_CHANNEL_1)
{ {
@ -141,7 +141,7 @@ int rt_hw_dac_init(void)
/* dac init */ /* dac init */
name_buf[3] = '0'; name_buf[3] = '0';
dac_obj[i].config = &dac_config[i]; dac_obj[i].config = &dac_config[i];
#if defined(BSP_USING_DAC1) #if defined(BSP_USING_DAC1)
if (dac_obj[i].config->dac_periph == DAC_CHANNEL_1) if (dac_obj[i].config->dac_periph == DAC_CHANNEL_1)
{ {
name_buf[3] = '1'; name_buf[3] = '1';
@ -155,7 +155,7 @@ int rt_hw_dac_init(void)
} }
GPIOInit(GPIOA, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_5); GPIOInit(GPIOA, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_5);
#endif #endif
/* register dac device */ /* register dac device */
for (i = 0; i < sizeof(dac_obj) / sizeof(dac_obj[0]); i++) for (i = 0; i < sizeof(dac_obj) / sizeof(dac_obj[0]); i++)
{ {
@ -169,7 +169,7 @@ int rt_hw_dac_init(void)
LOG_E("%s register failed", name_buf); LOG_E("%s register failed", name_buf);
result = -RT_ERROR; result = -RT_ERROR;
} }
} }
} }
return result; return result;

34
bsp/n32/libraries/n32_drivers/drv_gpio.c
View File

@ -38,7 +38,7 @@
#ifdef RT_USING_PIN #ifdef RT_USING_PIN
static const struct pin_index pins[] = static const struct pin_index pins[] =
{ {
#if defined(GPIOA) #if defined(GPIOA)
__N32_PIN(0 , GPIOA, GPIO_PIN_0 ), __N32_PIN(0 , GPIOA, GPIO_PIN_0 ),
@ -159,7 +159,7 @@ static const struct pin_index pins[] =
__N32_PIN(109, GPIOG, GPIO_PIN_13), __N32_PIN(109, GPIOG, GPIO_PIN_13),
__N32_PIN(110, GPIOG, GPIO_PIN_14), __N32_PIN(110, GPIOG, GPIO_PIN_14),
__N32_PIN(111, GPIOG, GPIO_PIN_15), __N32_PIN(111, GPIOG, GPIO_PIN_15),
#endif /* defined(GPIOG) */ #endif /* defined(GPIOG) */
#endif /* defined(GPIOF) */ #endif /* defined(GPIOF) */
#endif /* defined(GPIOE) */ #endif /* defined(GPIOE) */
@ -186,7 +186,7 @@ static const struct pin_irq_map pin_irq_map[] =
{GPIO_PIN_12, EXTI15_10_IRQn}, {GPIO_PIN_12, EXTI15_10_IRQn},
{GPIO_PIN_13, EXTI15_10_IRQn}, {GPIO_PIN_13, EXTI15_10_IRQn},
{GPIO_PIN_14, EXTI15_10_IRQn}, {GPIO_PIN_14, EXTI15_10_IRQn},
{GPIO_PIN_15, EXTI15_10_IRQn}, {GPIO_PIN_15, EXTI15_10_IRQn},
}; };
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
@ -269,9 +269,9 @@ static void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{ {
return; return;
} }
GPIO_InitStruct(&GPIO_InitStructure); GPIO_InitStruct(&GPIO_InitStructure);
/* Configure GPIO_InitStructure */ /* Configure GPIO_InitStructure */
GPIO_InitStructure.Pin = index->pin; GPIO_InitStructure.Pin = index->pin;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
@ -350,7 +350,7 @@ rt_inline rt_int32_t port2portsource(GPIO_Module* module)
else else
{ {
return GPIOA_PORT_SOURCE; return GPIOA_PORT_SOURCE;
} }
} }
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
@ -472,7 +472,7 @@ static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
/* Configure GPIO_InitStructure */ /* Configure GPIO_InitStructure */
GPIO_InitStruct(&GPIO_InitStructure); GPIO_InitStruct(&GPIO_InitStructure);
GPIO_InitStructure.Pin = index->pin; GPIO_InitStructure.Pin = index->pin;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
switch (pin_irq_hdr_tab[irqindex].mode) switch (pin_irq_hdr_tab[irqindex].mode)
{ {
@ -494,13 +494,13 @@ static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
/* configure EXTI line */ /* configure EXTI line */
GPIO_ConfigEXTILine(port2portsource(index->gpio), irqindex); GPIO_ConfigEXTILine(port2portsource(index->gpio), irqindex);
/*Configure key EXTI line*/ /*Configure key EXTI line*/
EXTI_InitStructure.EXTI_Line = index->pin; EXTI_InitStructure.EXTI_Line = index->pin;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_InitPeripheral(&EXTI_InitStructure); EXTI_InitPeripheral(&EXTI_InitStructure);
EXTI_ClrITPendBit(index->pin); EXTI_ClrITPendBit(index->pin);
NVIC_SetPriority(irqmap->irqno, 5); NVIC_SetPriority(irqmap->irqno, 5);
NVIC_EnableIRQ(irqmap->irqno); NVIC_EnableIRQ(irqmap->irqno);
@ -522,23 +522,23 @@ static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
if (( irqmap->pinbit>=GPIO_PIN_5 )&&( irqmap->pinbit<=GPIO_PIN_9 )) if (( irqmap->pinbit>=GPIO_PIN_5 )&&( irqmap->pinbit<=GPIO_PIN_9 ))
{ {
if(!(pin_irq_enable_mask&(GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9))) if(!(pin_irq_enable_mask&(GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9)))
{ {
NVIC_DisableIRQ(irqmap->irqno); NVIC_DisableIRQ(irqmap->irqno);
} }
} }
else if (( irqmap->pinbit>=GPIO_PIN_10 )&&( irqmap->pinbit<=GPIO_PIN_15 )) else if (( irqmap->pinbit>=GPIO_PIN_10 )&&( irqmap->pinbit<=GPIO_PIN_15 ))
{ {
if(!(pin_irq_enable_mask&(GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15))) if(!(pin_irq_enable_mask&(GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15)))
{ {
NVIC_DisableIRQ(irqmap->irqno); NVIC_DisableIRQ(irqmap->irqno);
} }
} }
else else
{ {
NVIC_DisableIRQ(irqmap->irqno); NVIC_DisableIRQ(irqmap->irqno);
} }
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
} }
else else
{ {
@ -562,15 +562,15 @@ int rt_hw_pin_init(void)
#if defined(RCC_GPIOA_CLK_ENABLE) #if defined(RCC_GPIOA_CLK_ENABLE)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
#endif #endif
#if defined(RCC_GPIOB_CLK_ENABLE) #if defined(RCC_GPIOB_CLK_ENABLE)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
#endif #endif
#if defined(RCC_GPIOC_CLK_ENABLE) #if defined(RCC_GPIOC_CLK_ENABLE)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
#endif #endif
#if defined(RCC_GPIOD_CLK_ENABLE) #if defined(RCC_GPIOD_CLK_ENABLE)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE);
#endif #endif

32
bsp/n32/libraries/n32_drivers/drv_hwtimer.c
View File

@ -116,30 +116,30 @@ static void caculate_tim_count()
#ifdef BSP_USING_HWTIMER3 #ifdef BSP_USING_HWTIMER3
tim3_count = count; tim3_count = count;
count++; count++;
#endif #endif
#ifdef BSP_USING_HWTIMER4 #ifdef BSP_USING_HWTIMER4
tim4_count = count; tim4_count = count;
count++; count++;
#endif #endif
#ifdef BSP_USING_HWTIMER5 #ifdef BSP_USING_HWTIMER5
tim5_count = count; tim5_count = count;
count++; count++;
#endif #endif
#ifdef BSP_USING_HWTIMER6 #ifdef BSP_USING_HWTIMER6
tim6_count = count; tim6_count = count;
count++; count++;
#endif #endif
#ifdef BSP_USING_HWTIMER7 #ifdef BSP_USING_HWTIMER7
tim7_count = count; tim7_count = count;
count++; count++;
#endif #endif
#ifdef BSP_USING_HWTIMER8 #ifdef BSP_USING_HWTIMER8
tim8_count = count; tim8_count = count;
count++; count++;
#endif #endif
} }
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
static struct n32_hwtimer hwtimer_obj[sizeof(hwtimer_config) / sizeof(hwtimer_config[0])] = {0}; static struct n32_hwtimer hwtimer_obj[sizeof(hwtimer_config) / sizeof(hwtimer_config[0])] = {0};
@ -154,7 +154,7 @@ static rt_err_t n32_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *
config = (struct n32_hwtimer_config *)timer->parent.user_data; config = (struct n32_hwtimer_config *)timer->parent.user_data;
RCC_GetClocksFreqValue(&RCC_ClockFreq); RCC_GetClocksFreqValue(&RCC_ClockFreq);
switch (cmd) switch (cmd)
{ {
case HWTIMER_CTRL_FREQ_SET: case HWTIMER_CTRL_FREQ_SET:
@ -176,7 +176,7 @@ static rt_err_t n32_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *
{ {
clk = clk * 2; clk = clk * 2;
} }
pre = (clk / * ((uint32_t *)args)) - 1; pre = (clk / * ((uint32_t *)args)) - 1;
TIM_ConfigPrescaler(config->timer_periph, pre, TIM_PSC_RELOAD_MODE_IMMEDIATE); TIM_ConfigPrescaler(config->timer_periph, pre, TIM_PSC_RELOAD_MODE_IMMEDIATE);
config->timer_periph->EVTGEN |= TIM_EVTGEN_UDGN; config->timer_periph->EVTGEN |= TIM_EVTGEN_UDGN;
} }
@ -237,10 +237,10 @@ static void n32_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
uint32_t clk; uint32_t clk;
uint8_t clkpre; uint8_t clkpre;
uint32_t pre; uint32_t pre;
RCC_GetClocksFreqValue(&RCC_ClockFreq); RCC_GetClocksFreqValue(&RCC_ClockFreq);
TIM_DeInit(config->timer_periph); TIM_DeInit(config->timer_periph);
if (config->timer_periph != TIM1 && config->timer_periph != TIM8) if (config->timer_periph != TIM1 && config->timer_periph != TIM8)
{ {
clk = RCC_ClockFreq.Pclk1Freq; clk = RCC_ClockFreq.Pclk1Freq;
@ -256,14 +256,14 @@ static void n32_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
clk = clk * 2; clk = clk * 2;
} }
pre = (clk / 10000) - 1; pre = (clk / 10000) - 1;
/* Time Base configuration */ /* Time Base configuration */
TIM_TimeBaseStructure.Prescaler = pre; TIM_TimeBaseStructure.Prescaler = pre;
TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP; TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = 10000 - 1; TIM_TimeBaseStructure.Period = 10000 - 1;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 0; TIM_TimeBaseStructure.RepetCnt = 0;
if (timer->info->cntmode == HWTIMER_CNTMODE_UP) if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
{ {
TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP; TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP;
@ -291,12 +291,12 @@ static rt_err_t n32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim
struct n32_hwtimer_config *config; struct n32_hwtimer_config *config;
RT_ASSERT(timer != RT_NULL); RT_ASSERT(timer != RT_NULL);
config = (struct n32_hwtimer_config *)timer->parent.user_data; config = (struct n32_hwtimer_config *)timer->parent.user_data;
/* set tim cnt */ /* set tim cnt */
TIM_SetCnt(config->timer_periph, 0); TIM_SetCnt(config->timer_periph, 0);
/* set tim arr */ /* set tim arr */
TIM_SetAutoReload(config->timer_periph, cnt - 1); TIM_SetAutoReload(config->timer_periph, cnt - 1);
if (mode == HWTIMER_MODE_ONESHOT) if (mode == HWTIMER_MODE_ONESHOT)
{ {
TIM_SelectOnePulseMode(config->timer_periph, TIM_OPMODE_SINGLE); TIM_SelectOnePulseMode(config->timer_periph, TIM_OPMODE_SINGLE);
@ -310,7 +310,7 @@ static rt_err_t n32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim
TIM_ConfigInt(config->timer_periph, TIM_INT_UPDATE, ENABLE); TIM_ConfigInt(config->timer_periph, TIM_INT_UPDATE, ENABLE);
/* TIM counter enable */ /* TIM counter enable */
TIM_Enable(config->timer_periph, ENABLE); TIM_Enable(config->timer_periph, ENABLE);
TIM_NVIC_Config(config->irqn, 3, 0, ENABLE); TIM_NVIC_Config(config->irqn, 3, 0, ENABLE);
return RT_EOK; return RT_EOK;
@ -426,7 +426,7 @@ void TIM1_UP_IRQHandler(void)
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
// TIM_IRQHandler(hwtimer_obj[0].config->timer_periph); // TIM_IRQHandler(hwtimer_obj[0].config->timer_periph);
TIM_ClrIntPendingBit(hwtimer_obj[tim1_count].config->timer_periph, TIM_INT_UPDATE); TIM_ClrIntPendingBit(hwtimer_obj[tim1_count].config->timer_periph, TIM_INT_UPDATE);
rt_device_hwtimer_isr(&hwtimer_obj[tim1_count].time_device); rt_device_hwtimer_isr(&hwtimer_obj[tim1_count].time_device);
/* leave interrupt */ /* leave interrupt */

22
bsp/n32/libraries/n32_drivers/drv_i2c.c
View File

@ -236,7 +236,7 @@ static rt_err_t n32_i2c_bus_unlock(const struct n32_soft_i2c_config *cfg)
} }
#endif /* RT_USING_I2C_BITOPS */ #endif /* RT_USING_I2C_BITOPS */
#ifdef RT_USING_HARDWARE_I2C #ifdef RT_USING_HARDWARE_I2C
static uint32_t I2CTimeout = I2CT_LONG_TIMEOUT; static uint32_t I2CTimeout = I2CT_LONG_TIMEOUT;
@ -251,7 +251,7 @@ static int rt_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uin
}; };
I2C_ConfigAck((I2C_Module*)i2c_periph, ENABLE); I2C_ConfigAck((I2C_Module*)i2c_periph, ENABLE);
/** Send START condition */ /** Send START condition */
I2C_GenerateStart((I2C_Module*)i2c_periph, ENABLE); I2C_GenerateStart((I2C_Module*)i2c_periph, ENABLE);
@ -265,7 +265,7 @@ static int rt_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uin
/* send slave address to I2C bus */ /* send slave address to I2C bus */
I2C_SendAddr7bit((I2C_Module*)i2c_periph, slave_address, I2C_DIRECTION_RECV); I2C_SendAddr7bit((I2C_Module*)i2c_periph, slave_address, I2C_DIRECTION_RECV);
I2CTimeout = I2CT_LONG_TIMEOUT; I2CTimeout = I2CT_LONG_TIMEOUT;
while (!I2C_CheckEvent((I2C_Module*)i2c_periph, I2C_EVT_MASTER_RXMODE_FLAG)) // EV6 while (!I2C_CheckEvent((I2C_Module*)i2c_periph, I2C_EVT_MASTER_RXMODE_FLAG)) // EV6
{ {
@ -293,7 +293,7 @@ static int rt_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uin
*p_buffer = I2C_RecvData((I2C_Module*)i2c_periph); *p_buffer = I2C_RecvData((I2C_Module*)i2c_periph);
/* point to the next location where the byte read will be saved */ /* point to the next location where the byte read will be saved */
p_buffer++; p_buffer++;
/* decrement the read bytes counter */ /* decrement the read bytes counter */
data_byte--; data_byte--;
@ -402,7 +402,7 @@ static rt_size_t rt_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg ms
} }
} }
} }
ret = i; ret = i;
return ret; return ret;
@ -413,7 +413,7 @@ out:
} }
static const struct rt_i2c_bus_device_ops i2c_ops = static const struct rt_i2c_bus_device_ops i2c_ops =
{ {
rt_i2c_xfer, rt_i2c_xfer,
RT_NULL, RT_NULL,
RT_NULL RT_NULL
@ -425,7 +425,7 @@ int rt_hw_i2c_init(void)
{ {
#ifdef RT_USING_I2C_BITOPS #ifdef RT_USING_I2C_BITOPS
rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct n32_i2c); rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct n32_i2c);
rt_err_t result; rt_err_t result;
for(int i = 0; i < obj_num; i++) for(int i = 0; i < obj_num; i++)
@ -446,7 +446,7 @@ int rt_hw_i2c_init(void)
soft_i2c_config[i].sda); soft_i2c_config[i].sda);
} }
#endif /* RT_USING_I2C_BITOPS */ #endif /* RT_USING_I2C_BITOPS */
#ifdef RT_USING_HARDWARE_I2C #ifdef RT_USING_HARDWARE_I2C
#ifdef BSP_USING_I2C1 #ifdef BSP_USING_I2C1
@ -459,10 +459,10 @@ int rt_hw_i2c_init(void)
GPIO_ConfigPinRemap(GPIO_RMP_I2C1, ENABLE); GPIO_ConfigPinRemap(GPIO_RMP_I2C1, ENABLE);
/* connect PB8 to I2C1_SCL, PB9 to I2C1_SDA */ /* connect PB8 to I2C1_SCL, PB9 to I2C1_SDA */
GPIOInit(GPIOB, GPIO_Mode_AF_OD, GPIO_Speed_50MHz, GPIO_PIN_8 | GPIO_PIN_9); GPIOInit(GPIOB, GPIO_Mode_AF_OD, GPIO_Speed_50MHz, GPIO_PIN_8 | GPIO_PIN_9);
/* enable I2C clock */ /* enable I2C clock */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_I2C1, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_I2C1, ENABLE);
I2C_DeInit(I2C1); I2C_DeInit(I2C1);
I2C_InitStructure.BusMode = I2C_BUSMODE_I2C; I2C_InitStructure.BusMode = I2C_BUSMODE_I2C;
I2C_InitStructure.FmDutyCycle = I2C_FMDUTYCYCLE_2; I2C_InitStructure.FmDutyCycle = I2C_FMDUTYCYCLE_2;
@ -520,7 +520,7 @@ int rt_hw_i2c_init(void)
/* connect PC0 to I2C3_SCL, PC1 to I2C3_SDA */ /* connect PC0 to I2C3_SCL, PC1 to I2C3_SDA */
GPIOInit(GPIOC, GPIO_Mode_AF_OD, GPIO_Speed_50MHz, GPIO_PIN_0 | GPIO_PIN_1); GPIOInit(GPIOC, GPIO_Mode_AF_OD, GPIO_Speed_50MHz, GPIO_PIN_0 | GPIO_PIN_1);
I2C_DeInit(I2C3); I2C_DeInit(I2C3);
I2C_InitStructure.BusMode = I2C_BUSMODE_I2C; I2C_InitStructure.BusMode = I2C_BUSMODE_I2C;
I2C_InitStructure.FmDutyCycle = I2C_FMDUTYCYCLE_2; I2C_InitStructure.FmDutyCycle = I2C_FMDUTYCYCLE_2;

18
bsp/n32/libraries/n32_drivers/drv_rtc.c
View File

@ -42,20 +42,20 @@ uint32_t SynchPrediv, AsynchPrediv;
static rt_err_t n32_rtc_get_timeval(struct timeval *tv) static rt_err_t n32_rtc_get_timeval(struct timeval *tv)
{ {
struct tm tm_new = {0}; struct tm tm_new = {0};
RTC_DateType RTC_DateStructure; RTC_DateType RTC_DateStructure;
RTC_TimeType RTC_TimeStructure; RTC_TimeType RTC_TimeStructure;
RTC_GetTime(RTC_FORMAT_BIN, &RTC_TimeStructure); RTC_GetTime(RTC_FORMAT_BIN, &RTC_TimeStructure);
RTC_GetDate(RTC_FORMAT_BIN, &RTC_DateStructure); RTC_GetDate(RTC_FORMAT_BIN, &RTC_DateStructure);
tm_new.tm_sec = RTC_TimeStructure.Seconds; tm_new.tm_sec = RTC_TimeStructure.Seconds;
tm_new.tm_min = RTC_TimeStructure.Minutes; tm_new.tm_min = RTC_TimeStructure.Minutes;
tm_new.tm_hour = RTC_TimeStructure.Hours; tm_new.tm_hour = RTC_TimeStructure.Hours;
tm_new.tm_wday = RTC_DateStructure.WeekDay; tm_new.tm_wday = RTC_DateStructure.WeekDay;
tm_new.tm_mday = RTC_DateStructure.Date; tm_new.tm_mday = RTC_DateStructure.Date;
tm_new.tm_mon = RTC_DateStructure.Month - 1; tm_new.tm_mon = RTC_DateStructure.Month - 1;
tm_new.tm_year = RTC_DateStructure.Year + 100; tm_new.tm_year = RTC_DateStructure.Year + 100;
tv->tv_sec = timegm(&tm_new); tv->tv_sec = timegm(&tm_new);
@ -64,7 +64,7 @@ static rt_err_t n32_rtc_get_timeval(struct timeval *tv)
static rt_err_t set_rtc_time_stamp(time_t time_stamp) static rt_err_t set_rtc_time_stamp(time_t time_stamp)
{ {
struct tm time = {0}; struct tm time = {0};
RTC_DateType RTC_DateStructure={0}; RTC_DateType RTC_DateStructure={0};
RTC_TimeType RTC_TimeStructure={0}; RTC_TimeType RTC_TimeStructure={0};
@ -93,8 +93,8 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
} }
rt_kprintf("set rtc time.\n"); rt_kprintf("set rtc time.\n");
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_rtc_config(void) static rt_err_t rt_rtc_config(void)
@ -152,7 +152,7 @@ static rt_err_t n32_rtc_init(void)
SynchPrediv = 0xFF; // 32.768KHz SynchPrediv = 0xFF; // 32.768KHz
AsynchPrediv = 0x7F; // value range: 0-7F AsynchPrediv = 0x7F; // value range: 0-7F
#endif /* BSP_RTC_USING_LSI */ #endif /* BSP_RTC_USING_LSI */
/* Enable the RTC Clock */ /* Enable the RTC Clock */
RCC_EnableRtcClk(ENABLE); RCC_EnableRtcClk(ENABLE);
RTC_WaitForSynchro(); RTC_WaitForSynchro();

66
bsp/n32/libraries/n32_drivers/drv_spi.c
View File

@ -58,11 +58,11 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
RT_ASSERT(device != RT_NULL); RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL); RT_ASSERT(configuration != RT_NULL);
RCC_GetClocksFreqValue(&RCC_ClockFreq); RCC_GetClocksFreqValue(&RCC_ClockFreq);
spi_periph = (SPI_Module*)device->bus->parent.user_data; spi_periph = (SPI_Module*)device->bus->parent.user_data;
if(spi_periph != SPI1 && spi_periph != SPI2 && spi_periph != SPI3) if(spi_periph != SPI1 && spi_periph != SPI2 && spi_periph != SPI3)
{ {
return RT_EIO; return RT_EIO;
@ -79,7 +79,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
{ {
return RT_EIO; return RT_EIO;
} }
{ {
rt_uint32_t spi_apb_clock; rt_uint32_t spi_apb_clock;
rt_uint32_t max_hz; rt_uint32_t max_hz;
@ -133,12 +133,12 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_256; SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_256;
} }
} /* baudrate */ } /* baudrate */
switch(configuration->mode & RT_SPI_MODE_3) switch(configuration->mode & RT_SPI_MODE_3)
{ {
case RT_SPI_MODE_0: case RT_SPI_MODE_0:
SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW; SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW;
SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE; SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE;
break; break;
case RT_SPI_MODE_1: case RT_SPI_MODE_1:
SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW; SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW;
@ -153,7 +153,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE; SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE;
break; break;
} }
/* MSB or LSB */ /* MSB or LSB */
if(configuration->mode & RT_SPI_MSB) if(configuration->mode & RT_SPI_MSB)
{ {
@ -168,8 +168,8 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
SPI_InitStructure.SpiMode = SPI_MODE_MASTER; SPI_InitStructure.SpiMode = SPI_MODE_MASTER;
SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE; SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE;
SPI_InitStructure.NSS = SPI_NSS_SOFT; SPI_InitStructure.NSS = SPI_NSS_SOFT;
SPI_InitStructure.CRCPoly = 7; SPI_InitStructure.CRCPoly = 7;
SPI_Init(spi_periph, &SPI_InitStructure); SPI_Init(spi_periph, &SPI_InitStructure);
/*!< Enable the sFLASH_SPI */ /*!< Enable the sFLASH_SPI */
@ -200,7 +200,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
const rt_uint8_t * send_ptr = message->send_buf; const rt_uint8_t * send_ptr = message->send_buf;
rt_uint8_t * recv_ptr = message->recv_buf; rt_uint8_t * recv_ptr = message->recv_buf;
rt_uint32_t size = message->length; rt_uint32_t size = message->length;
DEBUG_PRINTF("spi poll transfer start: %d\n", size); DEBUG_PRINTF("spi poll transfer start: %d\n", size);
while(size--) while(size--)
@ -211,19 +211,19 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
{ {
data = *send_ptr++; data = *send_ptr++;
} }
/*!< Loop while DAT register in not emplty */ /*!< Loop while DAT register in not emplty */
while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET); while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET);
// Send the byte // Send the byte
SPI_I2S_TransmitData(spi_periph, data); SPI_I2S_TransmitData(spi_periph, data);
//Wait until a data is received //Wait until a data is received
while(SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG) == RESET); while(SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG) == RESET);
// Get the received data // Get the received data
data = SPI_I2S_ReceiveData(spi_periph); data = SPI_I2S_ReceiveData(spi_periph);
if(recv_ptr != RT_NULL) if(recv_ptr != RT_NULL)
{ {
*recv_ptr++ = data; *recv_ptr++ = data;
@ -245,16 +245,16 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
{ {
data = *send_ptr++; data = *send_ptr++;
} }
/*!< Loop while DAT register in not emplty */ /*!< Loop while DAT register in not emplty */
while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET); while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET);
// Send the byte // Send the byte
SPI_I2S_TransmitData(spi_periph, data); SPI_I2S_TransmitData(spi_periph, data);
//Wait until a data is received //Wait until a data is received
while(RESET == SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG)); while(RESET == SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG));
// Get the received data // Get the received data
data = SPI_I2S_ReceiveData(spi_periph); data = SPI_I2S_ReceiveData(spi_periph);
@ -285,51 +285,51 @@ static struct rt_spi_ops spi_ops =
int rt_hw_spi_init(void) int rt_hw_spi_init(void)
{ {
int result = 0; int result = 0;
#ifdef BSP_USING_SPI1 #ifdef BSP_USING_SPI1
static struct rt_spi_bus spi_bus1; static struct rt_spi_bus spi_bus1;
spi_bus1.parent.user_data = (void *)SPI1; spi_bus1.parent.user_data = (void *)SPI1;
result = rt_spi_bus_register(&spi_bus1, "spi1", &spi_ops); result = rt_spi_bus_register(&spi_bus1, "spi1", &spi_ops);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1, ENABLE);
/* SPI1_SCK(PA5), SPI1_MISO(PA6) and SPI1_MOSI(PA7) GPIO pin configuration */ /* SPI1_SCK(PA5), SPI1_MISO(PA6) and SPI1_MOSI(PA7) GPIO pin configuration */
GPIOInit(SPI1_SCK_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI1_SCK_PIN); GPIOInit(SPI1_SCK_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI1_SCK_PIN);
GPIOInit(SPI1_MOSI_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI1_MOSI_PIN); GPIOInit(SPI1_MOSI_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI1_MOSI_PIN);
GPIOInit(SPI1_MISO_GPIO_PORT, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, SPI1_MISO_PIN); GPIOInit(SPI1_MISO_GPIO_PORT, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, SPI1_MISO_PIN);
#endif #endif
#ifdef BSP_USING_SPI2 #ifdef BSP_USING_SPI2
static struct rt_spi_bus spi_bus2; static struct rt_spi_bus spi_bus2;
spi_bus2.parent.user_data = (void *)SPI2; spi_bus2.parent.user_data = (void *)SPI2;
result = rt_spi_bus_register(&spi_bus2, "spi2", &spi_ops); result = rt_spi_bus_register(&spi_bus2, "spi2", &spi_ops);
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE);
/* SPI2_SCK(PB13), SPI2_MISO(PB14) and SPI2_MOSI(PB15) GPIO pin configuration */ /* SPI2_SCK(PB13), SPI2_MISO(PB14) and SPI2_MOSI(PB15) GPIO pin configuration */
GPIOInit(SPI2_SCK_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI2_SCK_PIN); GPIOInit(SPI2_SCK_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI2_SCK_PIN);
GPIOInit(SPI2_MOSI_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI2_MOSI_PIN); GPIOInit(SPI2_MOSI_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI2_MOSI_PIN);
GPIOInit(SPI2_MISO_GPIO_PORT, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, SPI2_MISO_PIN); GPIOInit(SPI2_MISO_GPIO_PORT, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, SPI2_MISO_PIN);
#endif #endif
#ifdef BSP_USING_SPI3 #ifdef BSP_USING_SPI3
static struct rt_spi_bus spi_bus3; static struct rt_spi_bus spi_bus3;
spi_bus3.parent.user_data = (void *)SPI3; spi_bus3.parent.user_data = (void *)SPI3;
result = rt_spi_bus_register(&spi_bus3, "spi3", &spi_ops); result = rt_spi_bus_register(&spi_bus3, "spi3", &spi_ops);
/* Enable AFIO clock */ /* Enable AFIO clock */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE, ENABLE); GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE, ENABLE);
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI3, ENABLE); RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI3, ENABLE);
/* SPI3_SCK(PB3), SPI3_MISO(PB4) and SPI3_MOSI(PB5) GPIO pin configuration */ /* SPI3_SCK(PB3), SPI3_MISO(PB4) and SPI3_MOSI(PB5) GPIO pin configuration */
GPIOInit(SPI3_SCK_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI3_SCK_PIN); GPIOInit(SPI3_SCK_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI3_SCK_PIN);
GPIOInit(SPI3_MOSI_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI3_MOSI_PIN); GPIOInit(SPI3_MOSI_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI3_MOSI_PIN);
GPIOInit(SPI3_MISO_GPIO_PORT, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, SPI3_MISO_PIN); GPIOInit(SPI3_MISO_GPIO_PORT, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, SPI3_MISO_PIN);
#endif #endif
return result; return result;
} }

40
bsp/n32/libraries/n32_drivers/drv_usart.c
View File

@ -51,7 +51,7 @@
struct n32_uart struct n32_uart
{ {
USART_Module* uart_periph; //Todo: 3bits USART_Module* uart_periph; //Todo: 3bits
IRQn_Type irqn; //Todo: 7bits IRQn_Type irqn; //Todo: 7bits
uint32_t per_clk; //Todo: 5bits uint32_t per_clk; //Todo: 5bits
uint32_t tx_gpio_clk; //Todo: 5bits uint32_t tx_gpio_clk; //Todo: 5bits
uint32_t rx_gpio_clk; //Todo: 5bits uint32_t rx_gpio_clk; //Todo: 5bits
@ -62,7 +62,7 @@ struct n32_uart
GPIO_ModeType rx_af; //Todo: 4bits GPIO_ModeType rx_af; //Todo: 4bits
uint16_t rx_pin; //Todo: 4bits uint16_t rx_pin; //Todo: 4bits
struct rt_serial_device * serial; struct rt_serial_device * serial;
char *device_name; char *device_name;
}; };
@ -191,7 +191,7 @@ static const struct n32_uart uarts[] = {
"usart1", "usart1",
}, },
#endif #endif
#ifdef BSP_USING_USART2 #ifdef BSP_USING_USART2
{ {
USART2, // uart peripheral index USART2, // uart peripheral index
@ -203,7 +203,7 @@ static const struct n32_uart uarts[] = {
"usart2", "usart2",
}, },
#endif #endif
#ifdef BSP_USING_USART3 #ifdef BSP_USING_USART3
{ {
USART3, // uart peripheral index USART3, // uart peripheral index
@ -227,7 +227,7 @@ static const struct n32_uart uarts[] = {
"uart4", "uart4",
}, },
#endif #endif
#ifdef BSP_USING_UART5 #ifdef BSP_USING_UART5
{ {
UART5, // uart peripheral index UART5, // uart peripheral index
@ -251,7 +251,7 @@ static const struct n32_uart uarts[] = {
"uart6", "uart6",
}, },
#endif #endif
#ifdef BSP_USING_UART7 #ifdef BSP_USING_UART7
{ {
UART7, // uart peripheral index UART7, // uart peripheral index
@ -279,21 +279,21 @@ void n32_uart_gpio_init(struct n32_uart *uart, struct serial_configure *cfg)
{ {
/* enable USART clock */ /* enable USART clock */
RCC_EnableAPB2PeriphClk(uart->tx_gpio_clk | uart->rx_gpio_clk | RCC_APB2_PERIPH_AFIO, ENABLE); RCC_EnableAPB2PeriphClk(uart->tx_gpio_clk | uart->rx_gpio_clk | RCC_APB2_PERIPH_AFIO, ENABLE);
if(uart->uart_periph == USART1 || uart->uart_periph == UART6 || uart->uart_periph == UART7) if(uart->uart_periph == USART1 || uart->uart_periph == UART6 || uart->uart_periph == UART7)
{ {
RCC_EnableAPB2PeriphClk(uart->per_clk, ENABLE); RCC_EnableAPB2PeriphClk(uart->per_clk, ENABLE);
} }
else else
{ {
RCC_EnableAPB1PeriphClk(uart->per_clk, ENABLE); RCC_EnableAPB1PeriphClk(uart->per_clk, ENABLE);
} }
/* connect port to USARTx_Tx */ /* connect port to USARTx_Tx */
GPIOInit(uart->tx_port, uart->tx_af, GPIO_Speed_50MHz, uart->tx_pin); GPIOInit(uart->tx_port, uart->tx_af, GPIO_Speed_50MHz, uart->tx_pin);
/* connect port to USARTx_Rx */ /* connect port to USARTx_Rx */
GPIOInit(uart->tx_port, uart->rx_af, GPIO_Speed_50MHz, uart->rx_pin); GPIOInit(uart->tx_port, uart->rx_af, GPIO_Speed_50MHz, uart->rx_pin);
NVIC_SetPriority(uart->irqn, 0); NVIC_SetPriority(uart->irqn, 0);
NVIC_EnableIRQ(uart->irqn); NVIC_EnableIRQ(uart->irqn);
} }
@ -302,14 +302,14 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con
{ {
struct n32_uart *uart; struct n32_uart *uart;
USART_InitType USART_InitStructure; USART_InitType USART_InitStructure;
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL); RT_ASSERT(cfg != RT_NULL);
uart = (struct n32_uart *)serial->parent.user_data; uart = (struct n32_uart *)serial->parent.user_data;
n32_uart_gpio_init(uart, cfg); n32_uart_gpio_init(uart, cfg);
USART_InitStructure.BaudRate = cfg->baud_rate; USART_InitStructure.BaudRate = cfg->baud_rate;
switch (cfg->data_bits) switch (cfg->data_bits)
@ -355,7 +355,7 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con
default: default:
break; break;
} }
switch (cfg->flowcontrol) switch (cfg->flowcontrol)
{ {
case RT_SERIAL_FLOWCONTROL_NONE: case RT_SERIAL_FLOWCONTROL_NONE:
@ -368,7 +368,7 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con
USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE;
break; break;
} }
USART_InitStructure.Mode = USART_MODE_TX | USART_MODE_RX; USART_InitStructure.Mode = USART_MODE_TX | USART_MODE_RX;
USART_Init(uart->uart_periph, &USART_InitStructure); USART_Init(uart->uart_periph, &USART_InitStructure);
@ -424,7 +424,7 @@ static int n32_putc(struct rt_serial_device *serial, char ch)
USART_SendData(uart->uart_periph, ch); USART_SendData(uart->uart_periph, ch);
while((USART_GetFlagStatus(uart->uart_periph, USART_FLAG_TXDE) == RESET)); while((USART_GetFlagStatus(uart->uart_periph, USART_FLAG_TXDE) == RESET));
return 1; return 1;
} }
@ -454,13 +454,13 @@ static void uart_isr(struct rt_serial_device *serial)
RT_ASSERT(uart != RT_NULL); RT_ASSERT(uart != RT_NULL);
/* UART in mode Receiver -------------------------------------------------*/ /* UART in mode Receiver -------------------------------------------------*/
if (USART_GetIntStatus(uart->uart_periph, USART_INT_RXDNE) != RESET && if (USART_GetIntStatus(uart->uart_periph, USART_INT_RXDNE) != RESET &&
USART_GetFlagStatus(uart->uart_periph, USART_FLAG_RXDNE) != RESET) USART_GetFlagStatus(uart->uart_periph, USART_FLAG_RXDNE) != RESET)
{ {
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
} }
if (USART_GetIntStatus(uart->uart_periph, USART_INT_TXDE) != RESET && if (USART_GetIntStatus(uart->uart_periph, USART_INT_TXDE) != RESET &&
USART_GetFlagStatus(uart->uart_periph, USART_FLAG_TXDE) != RESET) USART_GetFlagStatus(uart->uart_periph, USART_FLAG_TXDE) != RESET)
{ {
/* Write one byte to the transmit data register */ /* Write one byte to the transmit data register */
@ -481,7 +481,7 @@ int rt_hw_usart_init(void)
{ {
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
int i; int i;
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{ {
uarts[i].serial->ops = &n32_uart_ops; uarts[i].serial->ops = &n32_uart_ops;

8
bsp/n32/libraries/n32_drivers/drv_wdt.c
View File

@ -32,7 +32,7 @@
* *
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
*/ */
#include <rthw.h> #include <rthw.h>
#include <rtthread.h> #include <rtthread.h>
#include <rtdbg.h> #include <rtdbg.h>
@ -112,7 +112,7 @@ static rt_err_t n32_wdt_control(rt_watchdog_t *wdt, int cmd, void *args)
uint16_t reload_value; uint16_t reload_value;
uint32_t relv, prediv; uint32_t relv, prediv;
static rt_tick_t last_tick = 0; static rt_tick_t last_tick = 0;
relv = IWDG->RELV; relv = IWDG->RELV;
prediv = IWDG->PREDIV; prediv = IWDG->PREDIV;
switch (cmd) switch (cmd)
@ -125,12 +125,12 @@ static rt_err_t n32_wdt_control(rt_watchdog_t *wdt, int cmd, void *args)
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
{ {
RT_ASSERT(*(uint16_t *)args != 0); RT_ASSERT(*(uint16_t *)args != 0);
reload_value = *(uint16_t *)args; reload_value = *(uint16_t *)args;
if(reload_value > 0xFFF * 32 *1000 / LsiFreq) if(reload_value > 0xFFF * 32 *1000 / LsiFreq)
{ {
LOG_W("wdg set timeout parameter too large, please less than %d ms\n", 0xFFF * 32 *1000 / LsiFreq); LOG_W("wdg set timeout parameter too large, please less than %d ms\n", 0xFFF * 32 *1000 / LsiFreq);
return -RT_EINVAL; return -RT_EINVAL;
} }
/* Enable write access to IWDG_PR and IWDG_RLR registers */ /* Enable write access to IWDG_PR and IWDG_RLR registers */
IWDG_WriteConfig(IWDG_WRITE_ENABLE); IWDG_WriteConfig(IWDG_WRITE_ENABLE);
/* IWDG counter clock: LSI/32 */ /* IWDG counter clock: LSI/32 */