From 9568669109ffcb3aa6de8d07959795de71d505ae Mon Sep 17 00:00:00 2001 From: Grissiom Date: Sun, 20 Oct 2013 04:06:56 +0800 Subject: [PATCH] rm48x50: add GCC support --- bsp/rm48x50/HALCoGen/SConscript | 14 + bsp/rm48x50/HALCoGen/source/sys_core.S | 452 ++++++++++++++++++++++ bsp/rm48x50/HALCoGen/source/sys_intvecs.S | 31 ++ bsp/rm48x50/HALCoGen/source/sys_startup.c | 7 +- bsp/rm48x50/SConscript | 12 + bsp/rm48x50/SConstruct | 31 ++ bsp/rm48x50/application/SConscript | 9 + bsp/rm48x50/application/startup.c | 22 ++ bsp/rm48x50/drivers/SConscript | 9 - bsp/rm48x50/drivers/board.h | 2 +- bsp/rm48x50/rm48x50.ld | 144 +++++++ bsp/rm48x50/rtconfig.h | 6 +- bsp/rm48x50/rtconfig.py | 103 +++++ libcpu/arm/cortex-r4/cpu.c | 7 +- libcpu/arm/cortex-r4/stack.c | 2 +- 15 files changed, 835 insertions(+), 16 deletions(-) create mode 100644 bsp/rm48x50/HALCoGen/SConscript create mode 100644 bsp/rm48x50/HALCoGen/source/sys_core.S create mode 100644 bsp/rm48x50/HALCoGen/source/sys_intvecs.S create mode 100644 bsp/rm48x50/SConscript create mode 100644 bsp/rm48x50/SConstruct create mode 100644 bsp/rm48x50/application/SConscript create mode 100644 bsp/rm48x50/rm48x50.ld create mode 100644 bsp/rm48x50/rtconfig.py diff --git a/bsp/rm48x50/HALCoGen/SConscript b/bsp/rm48x50/HALCoGen/SConscript new file mode 100644 index 0000000000..9a6559f423 --- /dev/null +++ b/bsp/rm48x50/HALCoGen/SConscript @@ -0,0 +1,14 @@ +import copy +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('source/*.c') +src += Glob('source/*.S') + +CPPPATH = [cwd + '/include/'] + +group = DefineGroup('HALCoGen', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/rm48x50/HALCoGen/source/sys_core.S b/bsp/rm48x50/HALCoGen/source/sys_core.S new file mode 100644 index 0000000000..00d459dd34 --- /dev/null +++ b/bsp/rm48x50/HALCoGen/source/sys_core.S @@ -0,0 +1,452 @@ +@------------------------------------------------------------------------------- +@ sys_core.asm +@ +@ (c) Texas Instruments 2009-2013, All rights reserved. +@ + +#include + +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.equ UND_Stack_Size, 0x00000000 +.equ SVC_Stack_Size, 0x00000100 +.equ ABT_Stack_Size, 0x00000000 +.equ FIQ_Stack_Size, 0x00000000 +.equ IRQ_Stack_Size, 0x00000100 +.equ USR_Stack_Size, 0x00000100 + +.section .bss.noinit +/* stack */ +.globl stack_start +.globl stack_top + +stack_start: +.rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) +.long 0 +.endr +stack_top: + +.section .text, "ax" + .text + .arm + + .globl _c_int00 + +.globl _reset +_reset: +@------------------------------------------------------------------------------- +@ Initialize CPU Registers +@ After reset, the CPU is in the Supervisor mode (M = 10011) + cpsid if, #19 + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + @ Turn on FPV coprocessor + mrc p15, #0x00, r2, c1, c0, #0x02 + orr r2, r2, #0xF00000 + mcr p15, #0x00, r2, c1, c0, #0x02 + + fmrx r2, fpexc + orr r2, r2, #0x40000000 + fmxr fpexc, r2 +#endif + +@------------------------------------------------------------------------------- +@ Initialize Stack Pointers + ldr r0, =stack_top + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #FIQ_Stack_Size + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #IRQ_Stack_Size + + @ Enter Supervisor Mode and set its Stack Pointer + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #SVC_Stack_Size + + @ Enter User Mode and set its Stack Pointer + mov sp, r0 + sub sl, sp, #USR_Stack_Size + + bl next1 +next1: + bl next2 +next2: + bl next3 +next3: + bl next4 +next4: + ldr lr, =_c_int00 + bx lr + +.globl data_init +data_init: + /* copy .data to SRAM */ + ldr r1, =_sidata /* .data start in image */ + ldr r2, =_edata /* .data end in image */ + ldr r3, =_sdata /* sram data start */ +data_loop: + ldr r0, [r1, #0] + str r0, [r3] + + add r1, r1, #4 + add r3, r3, #4 + + cmp r3, r2 /* check if data to clear */ + blo data_loop /* loop until done */ + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r3, ip, lr} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r3, ip, lr} + b ctor_loop +ctor_end: + bx lr + +@------------------------------------------------------------------------------- +@ Enable RAM ECC Support + + .globl _coreEnableRamEcc_ +_coreEnableRamEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +@------------------------------------------------------------------------------- +@ Disable RAM ECC Support + + .globl _coreDisableRamEcc_ +_coreDisableRamEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + +@------------------------------------------------------------------------------- +@ Enable Flash ECC Support + + .globl _coreEnableFlashEcc_ +_coreEnableFlashEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x02000000 + dmb + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +@------------------------------------------------------------------------------- +@ Disable Flash ECC Support + + .globl _coreDisableFlashEcc_ +_coreDisableFlashEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x02000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + +@------------------------------------------------------------------------------- +@ Get data fault status register + + .globl _coreGetDataFault_ +_coreGetDataFault_: + + mrc p15, #0, r0, c5, c0, #0 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear data fault status register + + .globl _coreClearDataFault_ +_coreClearDataFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get instruction fault status register + + .globl _coreGetInstructionFault_ +_coreGetInstructionFault_: + + mrc p15, #0, r0, c5, c0, #1 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear instruction fault status register + + .globl _coreClearInstructionFault_ +_coreClearInstructionFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get data fault address register + + .globl _coreGetDataFaultAddress_ +_coreGetDataFaultAddress_: + + mrc p15, #0, r0, c6, c0, #0 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear data fault address register + + .globl _coreClearDataFaultAddress_ +_coreClearDataFaultAddress_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get instruction fault address register + + .globl _coreGetInstructionFaultAddress_ +_coreGetInstructionFaultAddress_: + + mrc p15, #0, r0, c6, c0, #2 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear instruction fault address register + + .globl _coreClearInstructionFaultAddress_ +_coreClearInstructionFaultAddress_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get auxiliary data fault status register + + .globl _coreGetAuxiliaryDataFault_ +_coreGetAuxiliaryDataFault_: + + mrc p15, #0, r0, c5, c1, #0 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear auxiliary data fault status register + + .globl _coreClearAuxiliaryDataFault_ +_coreClearAuxiliaryDataFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get auxiliary instruction fault status register + + .globl _coreGetAuxiliaryInstructionFault_ +_coreGetAuxiliaryInstructionFault_: + + mrc p15, #0, r0, c5, c1, #1 + bx lr + + +@------------------------------------------------------------------------------- +@ Clear auxiliary instruction fault status register + + .globl _coreClearAuxiliaryInstructionFault_ +_coreClearAuxiliaryInstructionFault_: + + stmfd sp!, {r0} + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + ldmfd sp!, {r0} + bx lr + + +@------------------------------------------------------------------------------- +@ Clear ESM CCM errorss + + .globl _esmCcmErrorsClear_ +_esmCcmErrorsClear_: + + stmfd sp!, {r0-r2} + ldr r0, ESMSR1_REG @ load the ESMSR1 status register address + ldr r2, ESMSR1_ERR_CLR + str r2, [r0] @ clear the ESMSR1 register + + ldr r0, ESMSR2_REG @ load the ESMSR2 status register address + ldr r2, ESMSR2_ERR_CLR + str r2, [r0] @ clear the ESMSR2 register + + ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address + ldr r2, ESMSSR2_ERR_CLR + str r2, [r0] @ clear the ESMSSR2 register + + ldr r0, ESMKEY_REG @ load the ESMKEY register address + mov r2, #0x5 @ load R2 with 0x5 + str r2, [r0] @ clear the ESMKEY register + + ldr r0, VIM_INTREQ @ load the INTREQ register address + ldr r2, VIM_INT_CLR + str r2, [r0] @ clear the INTREQ register + ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address + ldr r2, CCMR4_ERR_CLR + str r2, [r0] @ clear the CCMR4 status register + ldmfd sp!, {r0-r2} + bx lr + +ESMSR1_REG: .word 0xFFFFF518 +ESMSR2_REG: .word 0xFFFFF51C +ESMSR3_REG: .word 0xFFFFF520 +ESMKEY_REG: .word 0xFFFFF538 +ESMSSR2_REG: .word 0xFFFFF53C +CCMR4_STAT_REG: .word 0xFFFFF600 +ERR_CLR_WRD: .word 0xFFFFFFFF +CCMR4_ERR_CLR: .word 0x00010000 +ESMSR1_ERR_CLR: .word 0x80000000 +ESMSR2_ERR_CLR: .word 0x00000004 +ESMSSR2_ERR_CLR: .word 0x00000004 +VIM_INT_CLR: .word 0x00000001 +VIM_INTREQ: .word 0xFFFFFE20 + + +@------------------------------------------------------------------------------- +@ Work Around for Errata CORTEX-R4#57: +@ +@ Errata Description: +@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags +@ Workaround: +@ Disable out-of-order single-precision floating point +@ multiply-accumulate instruction completion + + .globl _errata_CORTEXR4_57_ +_errata_CORTEXR4_57_: + + push {r0} + mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register + orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS) + mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register + pop {r0} + bx lr + +@------------------------------------------------------------------------------- +@ Work Around for Errata CORTEX-R4#66: +@ +@ Errata Description: +@ Register Corruption During A Load-Multiple Instruction At +@ an Exception Vector +@ Workaround: +@ Disable out-of-order completion for divide instructions in +@ Auxiliary Control register + + .globl _errata_CORTEXR4_66_ +_errata_CORTEXR4_66_: + + push {r0} + mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register + orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion + @ for divide instructions.) + mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register + pop {r0} + bx lr + + .globl turnon_VFP +turnon_VFP: + @ Enable FPV + STMDB sp!, {r0} + fmrx r0, fpexc + orr r0, r0, #0x40000000 + fmxr fpexc, r0 + LDMIA sp!, {r0} + subs pc, lr, #4 + + .globl _dabort +_dabort: + stmfd r13!, {r0 - r12, lr} + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #8 diff --git a/bsp/rm48x50/HALCoGen/source/sys_intvecs.S b/bsp/rm48x50/HALCoGen/source/sys_intvecs.S new file mode 100644 index 0000000000..b21d5d4910 --- /dev/null +++ b/bsp/rm48x50/HALCoGen/source/sys_intvecs.S @@ -0,0 +1,31 @@ +@------------------------------------------------------------------------------- +@ sys_intvecs.asm +@ +@ (c) Texas Instruments 2009-2013, All rights reserved. +@ + +.section .vectors, "ax" +.code 32 + +@------------------------------------------------------------------------------- +@ import reference for interrupt routines + + .globl _reset + .globl _dabort + .globl turnon_VFP + .globl IRQ_Handler + + +.globl system_vectors +system_vectors: + b _reset + b turnon_VFP +svcEntry: + b svcEntry +prefetchEntry: + b prefetchEntry + b _dabort +reservedEntry: + b reservedEntry + b IRQ_Handler + ldr pc,[pc,#-0x1b0] diff --git a/bsp/rm48x50/HALCoGen/source/sys_startup.c b/bsp/rm48x50/HALCoGen/source/sys_startup.c index 0350e21e2b..6a3cd6eb49 100644 --- a/bsp/rm48x50/HALCoGen/source/sys_startup.c +++ b/bsp/rm48x50/HALCoGen/source/sys_startup.c @@ -42,6 +42,7 @@ typedef void (*handler_fptr)(const uint8 * in, uint8 * out); /*SAFETYMCUSW 218 S MR:20.2 "Functions from library" */ +#ifdef __TI_COMPILER_VERSION__ #pragma WEAK(__TI_Handler_Table_Base) #pragma WEAK(__TI_Handler_Table_Limit) #pragma WEAK(__TI_CINIT_Base) @@ -54,6 +55,7 @@ extern uint32 __TI_CINIT_Limit; extern uint32 __TI_PINIT_Base; extern uint32 __TI_PINIT_Limit; extern uint32 * __binit__; +#endif extern void main(void); @@ -349,6 +351,9 @@ void _c_int00(void) /* USER CODE BEGIN (75) */ /* USER CODE END */ +#ifdef __GNUC__ + data_init(); +#elif defined(__TI_COMPILER_VERSION__) /* initialize copy table */ if ((uint32 *)&__binit__ != (uint32 *)0xFFFFFFFFU) { @@ -384,7 +389,7 @@ void _c_int00(void) p(); } } - +#endif /* USER CODE BEGIN (76) */ /* USER CODE END */ /* call the application */ diff --git a/bsp/rm48x50/SConscript b/bsp/rm48x50/SConscript new file mode 100644 index 0000000000..0992612410 --- /dev/null +++ b/bsp/rm48x50/SConscript @@ -0,0 +1,12 @@ +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/rm48x50/SConstruct b/bsp/rm48x50/SConstruct new file mode 100644 index 0000000000..44e0a61ac7 --- /dev/null +++ b/bsp/rm48x50/SConstruct @@ -0,0 +1,31 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-rm48x50.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) + +if env['PLATFORM'] == 'win32': + env['ASCOM'] = '$AS $ASFLAGS $CCFLAGS $_CCCOMCOM -o $TARGET $SOURCES' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) +Depends(TARGET, 'rm48x50.ld') + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/rm48x50/application/SConscript b/bsp/rm48x50/application/SConscript new file mode 100644 index 0000000000..4ccb177207 --- /dev/null +++ b/bsp/rm48x50/application/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/rm48x50/application/startup.c b/bsp/rm48x50/application/startup.c index 6ec92840f5..31c2f92fa9 100644 --- a/bsp/rm48x50/application/startup.c +++ b/bsp/rm48x50/application/startup.c @@ -43,6 +43,28 @@ extern unsigned char * const system_data_end; #endif #define MEMEND 0x08040000 +void rt_hw_pmu_enable_cnt(void) +{ + unsigned long tmp; + + __asm (" MRC p15, #0, r0, c9, c12, #0"); + __asm (" ORR r0, r0, #0x09\n"); + __asm (" MCR p15, #0, r0, c9, c12, #0\n"); + __asm (" MOV r0, #1\n"); + __asm (" RBIT r0, r0\n"); + __asm (" MCR p15, #0, r0, c9, c12, #1\n"); +} + +void rt_hw_pmu_setcnt(unsigned long val) +{ + __asm (" MCR p15, #0, r0, c9, c13, #0"); +} + +unsigned long rt_hw_pmu_getcnt(void) +{ + __asm (" MRC p15, #0, r0, c9, c13, #0"); +} + /** * This function will startup RT-Thread RTOS. */ diff --git a/bsp/rm48x50/drivers/SConscript b/bsp/rm48x50/drivers/SConscript index a630c8a7c4..9987f53e4b 100644 --- a/bsp/rm48x50/drivers/SConscript +++ b/bsp/rm48x50/drivers/SConscript @@ -6,15 +6,6 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') -# remove no need file. -if GetDepend('RT_USING_LWIP') == False: - src_need_remove = ['dm9000.c'] # need remove file list. - SrcRemove(src, src_need_remove) - -if GetDepend('RT_USING_DFS') == False: - src_need_remove = ['sd.c'] # need remove file list. - SrcRemove(src, src_need_remove) - CPPPATH = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/rm48x50/drivers/board.h b/bsp/rm48x50/drivers/board.h index 6271d45140..8ac5b3f48c 100644 --- a/bsp/rm48x50/drivers/board.h +++ b/bsp/rm48x50/drivers/board.h @@ -20,7 +20,7 @@ #define RT_USING_UART2 #define RT_UART_RX_BUFFER_SIZE 64 void rt_hw_board_init(void); -void rt_hw_led_set(rt_uint32_t led); +void rt_hw_led_set(int led); void rt_hw_led_flash(void); #ifdef RT_USING_FINSH diff --git a/bsp/rm48x50/rm48x50.ld b/bsp/rm48x50/rm48x50.ld new file mode 100644 index 0000000000..340a3a3223 --- /dev/null +++ b/bsp/rm48x50/rm48x50.ld @@ -0,0 +1,144 @@ +/* + * linker script for RM48x50 with GNU ld + * Grissiom 2013-10-20 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 3M + DATA (rw) : ORIGIN = 0x08000000, LENGTH = 256k +} + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(system_vectors) +SECTIONS +{ + .text : + { + __text_start = .; + *(.vectors) + *(.text) + *(.text.*) + + __rodata_start = .; + *(.rodata) + *(.rodata.*) + __rodata_end = .; + + *(.glue_7) + *(.glue_7t) + *(.vfp11_veneer) + *(.v4_bx) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + __text_end = .; + } > CODE = 0 + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } > CODE + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + __data_end = .; + + __noinit_start = .; + .noinit : + { + . = ALIGN(4); + *(.bss.noinit) + } > DATA + __noinit_stop = .; + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } > DATA + __bss_end = .; + + /* Stabs debugging sections. + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + */ + _end = .; +} diff --git a/bsp/rm48x50/rtconfig.h b/bsp/rm48x50/rtconfig.h index d681ef736e..78aa0e1dcf 100644 --- a/bsp/rm48x50/rtconfig.h +++ b/bsp/rm48x50/rtconfig.h @@ -19,7 +19,7 @@ // #define IDLE_THREAD_STACK_SIZE 512 //
-#define RT_DEBUG +//#define RT_DEBUG // // #define RT_THREAD_DEBUG // @@ -27,7 +27,7 @@ //
// -#define RT_USING_HOOK +//#define RT_USING_HOOK //
// #define RT_USING_TIMER_SOFT // @@ -131,7 +131,7 @@ //
//
-#define RT_USING_LWIP +//#define RT_USING_LWIP // #define RT_USING_LWIP141 // diff --git a/bsp/rm48x50/rtconfig.py b/bsp/rm48x50/rtconfig.py new file mode 100644 index 0000000000..b5e3664dbd --- /dev/null +++ b/bsp/rm48x50/rtconfig.py @@ -0,0 +1,103 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-r4' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Program Files\GNU Tools ARM Embedded\4.7 2013q3\bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' +elif CROSS_TOOL == 'iar': + print '================ERROR============================' + print 'Not support IAR yet!' + print '=================================================' + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -Wall -march=armv7-r -mfloat-abi=hard'+\ + ' -ftree-vectorize -ffast-math -mfpu=vfpv3-d16 '+\ + ' -ffunction-sections -fdata-sections ' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-rm48x50.map,-cref,-u,system_vectors -T rm48x50.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 ' + AFLAGS += ' -g -gdwarf-2' + else: + CFLAGS += ' -O3 -g -gdwarf-2' + AFLAGS += ' -g -gdwarf-2' + + POST_ACTION = SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMP' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-beaglebone.map --scatter beaglebone_ram.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' --cpu DARMP' + + CFLAGS = '' + AFLAGS = '' + LFLAGS = ' --config beaglebone_ram.icf' + + EXEC_PATH += '/arm/bin/' + RT_USING_MINILIBC = False + POST_ACTION = '' diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c index d1b5c9df54..89369d5209 100644 --- a/libcpu/arm/cortex-r4/cpu.c +++ b/libcpu/arm/cortex-r4/cpu.c @@ -39,6 +39,7 @@ void rt_hw_cpu_shutdown() while (1); } +#ifdef __TI_COMPILER_VERSION__ #ifdef RT_USING_CPU_FFS int __rt_ffs(int value) { @@ -52,7 +53,6 @@ int __rt_ffs(int value) } #endif -#ifdef __TI_COMPILER_VERSION__ void rt_hw_cpu_icache_enable() { __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); @@ -90,5 +90,10 @@ void rt_hw_cpu_dcache_disable() __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache"); } +#elif __GNUC__ +int __rt_ffs(int value) +{ + return __builtin_ffs(value); +} #endif /*@}*/ diff --git a/libcpu/arm/cortex-r4/stack.c b/libcpu/arm/cortex-r4/stack.c index 02dc84e6f1..769e3360ed 100644 --- a/libcpu/arm/cortex-r4/stack.c +++ b/libcpu/arm/cortex-r4/stack.c @@ -57,7 +57,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, else *(--stk) = SVCMODE; /* arm mode */ -#ifdef __TI_VFP_SUPPORT__ +#if defined(__TI_VFP_SUPPORT__) || (defined (__VFP_FP__) && !defined(__SOFTFP__)) #ifndef RT_VFP_LAZY_STACKING { #define VFP_DATA_NR 32