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Merge pull request #4089 from thread-liu/step4-ev1 

[add] complicated dirvers for STM32MP157A-EV1 board
This commit is contained in:
Bernard Xiong 2020-12-02 23:39:29 +08:00 committed by GitHub
parent dae7f1af9b c5612fd2e1
commit 926a06d347
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
17 changed files with 4333 additions and 26 deletions
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12
bsp/stm32/libraries/STM32MPxx_HAL/SConscript
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@ -35,10 +35,6 @@ if GetDepend(['RT_USING_SERIAL']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c']
#if GetDepend(['RT_USING_SPI']):
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c']
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c']
if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pccard.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pcd.c']
@ -49,11 +45,6 @@ if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
if GetDepend(['RT_USING_CAN']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_can.c']
#if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']):
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c']
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c']
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c']
if GetDepend(['BSP_USING_ETH']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_eth.c']
@ -73,10 +64,9 @@ if GetDepend(['RT_USING_WDT']):
if GetDepend(['RT_USING_SDIO']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_delayblock.c']
if GetDepend(['RT_USING_AUDIO']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2s.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2s_ex.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai_ex.c']

6
bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h
View File

@ -57,8 +57,8 @@
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
@ -153,6 +153,8 @@
#define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
#define USE_SD_TRANSCEIVER 1U
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source

434
bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c
View File

@ -26,7 +26,9 @@
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
DMA_HandleTypeDef hdma_sai2_a = {0};
DMA_HandleTypeDef hdma_sai2_b = {0};
DMA_HandleTypeDef hdma_sai4_a = {0};
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
@ -965,6 +967,436 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hI2c)
}
}
/**
* @brief SD MSP Initialization
* This function configures the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(hsd->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspInit 0 */
if (IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4;
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
/* USER CODE END SDMMC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SDMMC1_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
/**SDMMC1 GPIO Configuration
PB9 ------> SDMMC1_CDIR
PC7 ------> SDMMC1_D123DIR
PC8 ------> SDMMC1_D0
PC9 ------> SDMMC1_D1
PC10 ------> SDMMC1_D2
PC11 ------> SDMMC1_D3
PC12 ------> SDMMC1_CK
PD2 ------> SDMMC1_CMD
PE4 ------> SDMMC1_CKIN
PF2 ------> SDMMC1_D0DIR
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_SDIO1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7;
GPIO_InitStruct.Alternate = GPIO_AF8_SDIO1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
__HAL_RCC_SDMMC1_FORCE_RESET();
__HAL_RCC_SDMMC1_RELEASE_RESET();
/* SDMMC1 interrupt Init */
HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
/* USER CODE BEGIN SDMMC1_MspInit 1 */
/* USER CODE END SDMMC1_MspInit 1 */
}
if(hsd->Instance==SDMMC2)
{
/* USER CODE BEGIN SDMMC2_MspInit 0 */
if (IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4;
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
/* USER CODE END SDMMC2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SDMMC2_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
/**SDMMC2 GPIO Configuration
PB14 ------> SDMMC2_D0
PB15 ------> SDMMC2_D1
PB3 ------> SDMMC2_D2
PB4 ------> SDMMC2_D3
PA8 ------> SDMMC2_D4
PA9 ------> SDMMC2_D5
PE5 ------> SDMMC2_D6
PD3 ------> SDMMC2_D7
PE3 ------> SDMMC2_CK
PG6 ------> SDMMC2_CMD
*/
GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_SDIO2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Alternate = GPIO_AF10_SDIO2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
__HAL_RCC_SDMMC2_FORCE_RESET();
__HAL_RCC_SDMMC2_RELEASE_RESET();
/* SDMMC2 interrupt Init */
HAL_NVIC_SetPriority(SDMMC2_IRQn, 0X05, 0);
HAL_NVIC_EnableIRQ(SDMMC2_IRQn);
/* USER CODE BEGIN SDMMC2_MspInit 1 */
/* USER CODE END SDMMC2_MspInit 1 */
}
}
/**
* @brief SD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
{
if(hsd->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspDeInit 0 */
/* USER CODE END SDMMC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SDMMC1_CLK_DISABLE();
/**SDMMC1 GPIO Configuration
PB9 ------> SDMMC1_CDIR
PC7 ------> SDMMC1_D123DIR
PC8 ------> SDMMC1_D0
PC9 ------> SDMMC1_D1
PC10 ------> SDMMC1_D2
PC11 ------> SDMMC1_D3
PC12 ------> SDMMC1_CK
PD2 ------> SDMMC1_CMD
PE4 ------> SDMMC1_CKIN
PF2 ------> SDMMC1_D0DIR
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2);
/* SDMMC1 interrupt DeInit */
HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
/* USER CODE BEGIN SDMMC1_MspDeInit 1 */
/* USER CODE END SDMMC1_MspDeInit 1 */
}
if(hsd->Instance==SDMMC2)
{
/* USER CODE BEGIN SDMMC2_MspDeInit 0 */
/* USER CODE END SDMMC2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SDMMC2_CLK_DISABLE();
/**SDMMC2 GPIO Configuration
PB14 ------> SDMMC2_D0
PB15 ------> SDMMC2_D1
PB3 ------> SDMMC2_D2
PB4 ------> SDMMC2_D3
PA8 ------> SDMMC2_D4
PA9 ------> SDMMC2_D5
PE5 ------> SDMMC2_D6
PD3 ------> SDMMC2_D7
PE3 ------> SDMMC2_CK
PG6 ------> SDMMC2_CMD
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_14|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_3);
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_3|GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6);
/* SDMMC2 interrupt DeInit */
HAL_NVIC_DisableIRQ(SDMMC2_IRQn);
/* USER CODE BEGIN SDMMC2_MspDeInit 1 */
/* USER CODE END SDMMC2_MspDeInit 1 */
}
}
void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
/* SAI2 */
if (hsai->Instance==SAI2_Block_A)
{
/* Peripheral clock enable */
if(IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2;
PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_SAI2_CLK_ENABLE();
/**SAI2_A_Block_A GPIO Configuration
PE0 ------> SAI2_MCLK_A
PI7 ------> SAI2_FS_A
PI5 ------> SAI2_SCK_A
PI6 ------> SAI2_SD_A
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_5|GPIO_PIN_6;
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
/* Configure DMA used for SAI2 */
__HAL_RCC_DMAMUX_CLK_ENABLE();
__HAL_RCC_DMA1_CLK_ENABLE();
hdma_sai2_a.Instance = DMA1_Stream0;
hdma_sai2_a.Init.Request = DMA_REQUEST_SAI2_A;
hdma_sai2_a.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_sai2_a.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_sai2_a.Init.MemInc = DMA_MINC_ENABLE;
hdma_sai2_a.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_sai2_a.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_sai2_a.Init.Mode = DMA_CIRCULAR;
hdma_sai2_a.Init.Priority = DMA_PRIORITY_HIGH;
hdma_sai2_a.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
hdma_sai2_a.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_sai2_a.Init.MemBurst = DMA_MBURST_SINGLE;
hdma_sai2_a.Init.PeriphBurst = DMA_PBURST_SINGLE;
HAL_DMA_DeInit(&hdma_sai2_a);
if (HAL_DMA_Init(&hdma_sai2_a) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(hsai,hdmatx,hdma_sai2_a);
__HAL_DMA_ENABLE(&hdma_sai2_a);
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0x02, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
}
if (hsai->Instance==SAI2_Block_B)
{
/* Peripheral clock enable */
if (IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2;
PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_SAI2_CLK_ENABLE();
/**SAI2_B_Block_B GPIO Configuration
PE12 ------> SAI2_MCLK_B
PE13 ------> SAI2_FS_B
PE14 ------> SAI2_SCK_B
PF11 ------> SAI2_SD_B
*/
GPIO_InitStruct.Pin = GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
__HAL_RCC_DMAMUX_CLK_ENABLE();
__HAL_RCC_DMA1_CLK_ENABLE();
/* Peripheral DMA init*/
hdma_sai2_b.Instance = DMA1_Stream1;
hdma_sai2_b.Init.Request = DMA_REQUEST_SAI2_B;
hdma_sai2_b.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_sai2_b.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_sai2_b.Init.MemInc = DMA_MINC_ENABLE;
hdma_sai2_b.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_sai2_b.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_sai2_b.Init.Mode = DMA_CIRCULAR;
hdma_sai2_b.Init.Priority = DMA_PRIORITY_HIGH;
hdma_sai2_b.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
hdma_sai2_b.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_sai2_b.Init.MemBurst = DMA_MBURST_SINGLE;
hdma_sai2_b.Init.PeriphBurst = DMA_PBURST_SINGLE;
HAL_DMA_DeInit(&hdma_sai2_b);
if (HAL_DMA_Init(&hdma_sai2_b) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b);
__HAL_DMA_ENABLE(&hdma_sai2_b);
HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0x02, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
}
/* SAI4 */
if(hsai->Instance==SAI4_Block_A)
{
/* Peripheral clock enable */
if(IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI4;
PeriphClkInit.Sai4ClockSelection = RCC_SAI4CLKSOURCE_PLL3_Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_SAI4_CLK_ENABLE();
/**SAI4_A_Block_A GPIO Configuration
PB5 ------> SAI4_SD_A
*/
GPIO_InitStruct.Pin = GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF10_SAI4;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* Peripheral DMA init*/
__HAL_RCC_DMAMUX_CLK_ENABLE();
__HAL_RCC_DMA1_CLK_ENABLE();
hdma_sai4_a.Instance = DMA1_Stream2;
hdma_sai4_a.Init.Request = DMA_REQUEST_SAI4_A;
hdma_sai4_a.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_sai4_a.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_sai4_a.Init.MemInc = DMA_MINC_ENABLE;
hdma_sai4_a.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_sai4_a.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_sai4_a.Init.Mode = DMA_CIRCULAR;
hdma_sai4_a.Init.Priority = DMA_PRIORITY_HIGH;
hdma_sai4_a.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
hdma_sai4_a.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_sai4_a.Init.MemBurst = DMA_MBURST_SINGLE;
hdma_sai4_a.Init.PeriphBurst = DMA_PBURST_SINGLE;
HAL_DMA_DeInit(&hdma_sai4_a);
if (HAL_DMA_Init(&hdma_sai4_a) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(hsai,hdmatx,hdma_sai4_a);
__HAL_DMA_ENABLE(&hdma_sai4_a);
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0x02, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
}
}
/**
* @brief This function is executed in case of error occurrence.
* @retval None

45
bsp/stm32/stm32mp157a-st-ev1/board/Kconfig
View File

@ -33,6 +33,45 @@ menu "Onboard Peripheral Drivers"
select RT_USING_OPENAMP
default n
config BSP_USING_GBE
bool "Enable Ethernet"
default n
select RT_USING_LWIP
menuconfig BSP_USING_SDMMC
bool "Enable SDMMC"
select RT_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
select BSP_USING_PMIC
if BSP_USING_SDMMC
menuconfig BSP_USING_SD_CARD
bool "Enable sd card"
default n
if BSP_USING_SD_CARD
config SD_USING_DFS
bool "sd card fatfs"
default n
endif
menuconfig BSP_USING_EMMC
bool "Enable eMMC (32 Gbits)"
default n
if BSP_USING_EMMC
config EMMC_USING_DFS
bool "emmc card fatfs"
default n
endif
endif
config BSP_USING_AUDIO
bool "Enable Audio Device (WM8994)"
select RT_USING_AUDIO
select BSP_USING_PMIC
select BSP_USING_I2C
select BSP_USING_I2C2
default n
endmenu
menu "On-chip Peripheral Drivers"
@ -48,11 +87,11 @@ menu "On-chip Peripheral Drivers"
if BSP_USING_UART
config BSP_USING_UART3
bool "Enable UART3"
default y
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_TX_USING_DMA
@ -62,7 +101,7 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_UART4
bool "Enable UART4"
default y
default n
config BSP_UART4_RX_USING_DMA
bool "Enable UART4 RX DMA"

16
bsp/stm32/stm32mp157a-st-ev1/board/SConscript
View File

@ -19,6 +19,19 @@ if GetDepend(['BSP_USING_PMIC']):
if GetDepend(['BSP_USING_NAND']):
src += Glob('ports/drv_nand.c')
if GetDepend(['BSP_USING_GBE']):
src += Glob('ports/eth/drv_eth.c')
if GetDepend(['BSP_USING_SD_CARD']):
src += Glob('ports/drv_sdcard.c')
if GetDepend(['BSP_USING_EMMC']):
src += Glob('ports/drv_emmc.c')
if GetDepend(['BSP_USING_AUDIO']):
src += Glob('ports/drv_wm8994.c')
src += Glob('ports/drv_sound.c')
if GetDepend(['BSP_USING_OPENAMP']):
src += Glob('CubeMX_Config/CM4/Src/ipcc.c')
src += Glob('CubeMX_Config/CM4/Src/openamp.c')
@ -45,6 +58,9 @@ if GetDepend(['BSP_USING_OPENAMP']):
path += [cwd + '/ports/OpenAMP/virtual_driver']
path += [cwd + '/CubeMX_Config/CM4/Inc']
if GetDepend(['BSP_USING_GBE']):
path += [cwd + '/ports/eth']
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':

2
bsp/stm32/stm32mp157a-st-ev1/board/board.h
View File

@ -32,7 +32,7 @@ extern "C" {
#if defined(BSP_USING_OPENAMP)
#define STM32_SRAM_BEGIN (uint32_t)0x10020000
#define STM32_SRAM_BEGIN (uint32_t)0x10030000
#else
#define STM32_SRAM_BEGIN (uint32_t)0x2FFF0000
#endif

7
bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.icf
View File

@ -5,7 +5,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_text_start__ = 0x10000000;
define symbol __ICFEDIT_region_text_end__ = 0x1001FFFF;
define symbol __ICFEDIT_region_text_end__ = 0x1002FFFF;
define symbol __ICFEDIT_region_data_start__ = 0x10030000;
define symbol __ICFEDIT_region_data_end__ = 0x1003FFFF;
/*-Sizes-*/
@ -28,11 +28,6 @@ define symbol __OPENAMP_region_size__ = 0x8000;
export symbol __OPENAMP_region_start__;
export symbol __OPENAMP_region_size__;
define symbol __SDMMC_region_start__ = 0x10048000;
define symbol __SDMMC_region_size__ = 0x1FFFF;
export symbol __SDMMC_region_start__;
export symbol __SDMMC_region_size__;
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };

38
bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c
View File

@ -12,6 +12,7 @@
#ifdef BSP_USING_OPENAMP
#include <finsh.h>
#include <drv_openamp.h>
#include <openamp.h>
#include <virt_uart.h>
@ -235,7 +236,10 @@ int rt_hw_openamp_init(void)
rt_hw_openamp_register(&dev_openamp, "openamp", 0, NULL);
rt_console_set_device("openamp");
if (RT_CONSOLE_DEVICE_NAME == "openamp")
{
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
}
return RT_EOK;
}
@ -289,4 +293,36 @@ static int creat_openamp_thread(void)
}
INIT_APP_EXPORT(creat_openamp_thread);
#ifdef FINSH_USING_MSH
static int console(int argc, char **argv)
{
rt_err_t result = RT_EOK;
if (argc > 1)
{
if (!strcmp(argv[1], "set"))
{
rt_kprintf("console change to %s\n", argv[2]);
rt_console_set_device(argv[2]);
finsh_set_device(argv[2]);
}
else
{
rt_kprintf("Unknown command. Please enter 'console' for help\n");
result = -RT_ERROR;
}
}
else
{
rt_kprintf("Usage: \n");
rt_kprintf("console set <name> - change console by name\n");
result = -RT_ERROR;
}
return result;
}
MSH_CMD_EXPORT(console, set console name);
#endif /* FINSH_USING_MSH */
#endif

593
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c Normal file
View File

@ -0,0 +1,593 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-16 thread-liu first version
*/
#include "board.h"
#include "drv_emmc.h"
#include <dfs_fs.h>
#ifdef BSP_USING_EMMC
//#define DRV_DEBUG
//#define EMMC_RX_DUMP
//#define EMMC_TX_DUMP
#define DBG_TAG "drv.emmc"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
static SD_HandleTypeDef hsd;
static struct rt_mmcsd_host *host;
#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000)
#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
struct sdio_pkg
{
struct rt_mmcsd_cmd *cmd;
void *buff;
rt_uint32_t flag;
};
struct rthw_sdio
{
struct rt_mmcsd_host *host;
struct stm32_sdio_des sdio_des;
struct rt_event event;
struct rt_mutex mutex;
struct sdio_pkg *pkg;
};
#define EMMC_BUFF_SIZE 4096
#if defined(__CC_ARM) || defined(__CLANG_ARM)
rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((at(0x2FFCB000)));
#elif defined(__ICCARM__)
#pragma location = 0x2FFCB000
rt_uint8_t cache_buf[EMMC_BUFF_SIZE];
#elif defined ( __GNUC__ )
rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((at(0x2FFCB000)));
#endif
#if defined(EMMC_RX_DUMP) || defined(EMMC_TX_DUMP)
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
{
unsigned char *buf = (unsigned char *)ptr;
int i, j;
for (i = 0; i < buflen; i += 16)
{
rt_kprintf("%08X: ", i);
for (j = 0; j < 16; j++)
if (i + j < buflen)
rt_kprintf("%02X ", buf[i + j]);
else
rt_kprintf(" ");
rt_kprintf(" ");
for (j = 0; j < 16; j++)
if (i + j < buflen)
rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
rt_kprintf("\n");
}
}
#endif
/**
* @brief This function get order from sdio.
* @param data
* @retval sdio order
*/
static int get_order(rt_uint32_t data)
{
int order = 0;
switch (data)
{
case 1:
order = 0;
break;
case 2:
order = 1;
break;
case 4:
order = 2;
break;
case 8:
order = 3;
break;
case 16:
order = 4;
break;
case 32:
order = 5;
break;
case 64:
order = 6;
break;
case 128:
order = 7;
break;
case 256:
order = 8;
break;
case 512:
order = 9;
break;
case 1024:
order = 10;
break;
case 2048:
order = 11;
break;
case 4096:
order = 12;
break;
case 8192:
order = 13;
break;
case 16384:
order = 14;
break;
default :
order = 0;
break;
}
return order;
}
/**
* @brief This function wait sdio cmd completed.
* @param sdio rthw_sdio
* @retval None
*/
static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
{
rt_uint32_t status;
struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
rt_tick_from_millisecond(5000), &status) != RT_EOK)
{
LOG_E("wait cmd completed timeout");
cmd->err = -RT_ETIMEOUT;
return;
}
if (sdio->pkg == RT_NULL)
{
return;
}
cmd->resp[0] = hw_sdio->resp1;
cmd->resp[1] = hw_sdio->resp2;
cmd->resp[2] = hw_sdio->resp3;
cmd->resp[3] = hw_sdio->resp4;
if (status & SDMMC_ERRORS)
{
if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
{
cmd->err = RT_EOK;
}
else
{
cmd->err = -RT_ERROR;
}
if (status & SDMMC_STA_CTIMEOUT)
{
cmd->err = -RT_ETIMEOUT;
}
if (status & SDMMC_STA_DCRCFAIL)
{
data->err = -RT_ERROR;
}
if (status & SDMMC_STA_DTIMEOUT)
{
data->err = -RT_ETIMEOUT;
}
if (cmd->err == RT_EOK)
{
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
}
else
{
LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
status,
status & SDMMC_STA_CCRCFAIL ? "CCRCFAIL " : "",
status & SDMMC_STA_DCRCFAIL ? "DCRCFAIL " : "",
status & SDMMC_STA_CTIMEOUT ? "CTIMEOUT " : "",
status & SDMMC_STA_DTIMEOUT ? "DTIMEOUT " : "",
status & SDMMC_STA_TXUNDERR ? "TXUNDERR " : "",
status & SDMMC_STA_RXOVERR ? "RXOVERR " : "",
status == 0 ? "NULL" : "",
cmd->cmd_code,
cmd->arg,
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0,
data ? data->blksize : 0
);
}
}
else
{
cmd->err = RT_EOK;
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
}
}
/**
* @brief This function send command.
* @param sdio rthw_sdio
* @param pkg sdio package
* @retval None
*/
static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
{
struct rt_mmcsd_cmd *cmd = pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t reg_cmd;
sdio->pkg = pkg;
LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
cmd->cmd_code,
cmd->arg,
resp_type(cmd) == RESP_NONE ? "NONE" : "",
resp_type(cmd) == RESP_R1 ? "R1" : "",
resp_type(cmd) == RESP_R1B ? "R1B" : "",
resp_type(cmd) == RESP_R2 ? "R2" : "",
resp_type(cmd) == RESP_R3 ? "R3" : "",
resp_type(cmd) == RESP_R4 ? "R4" : "",
resp_type(cmd) == RESP_R5 ? "R5" : "",
resp_type(cmd) == RESP_R6 ? "R6" : "",
resp_type(cmd) == RESP_R7 ? "R7" : "",
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0,
data ? data->blksize : 0
);
/* config cmd reg */
reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN;
if (resp_type(cmd) == RESP_NONE)
{
reg_cmd |= SDMMC_RESPONSE_NO;
}
else if (resp_type(cmd) == RESP_R2)
{
reg_cmd |= SDMMC_RESPONSE_LONG;
}
else
{
reg_cmd |= SDMMC_RESPONSE_SHORT;
}
hw_sdio->mask |= SDIO_MASKR_ALL;
/* data pre configuration */
if (data != RT_NULL)
{
hw_sdio->dctrl = 0;
hw_sdio->mask &= ~(SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE);
reg_cmd |= SDMMC_CMD_CMDTRANS;
hw_sdio->dtimer = HW_SDIO_DATATIMEOUT;
hw_sdio->dlen = data->blks * data->blksize;
hw_sdio->dctrl = (get_order(data->blksize)<<4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0);
hw_sdio->idmabase0r = (rt_uint32_t)cache_buf;
hw_sdio->idmatrlr = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
}
hw_sdio->arg = cmd->arg;
hw_sdio->cmd = reg_cmd;
/* wait completed */
rthw_sdio_wait_completed(sdio);
/* Waiting for data to be sent to completion */
if (data != RT_NULL)
{
volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
while (count && (hw_sdio->sta & SDMMC_STA_DPSMACT))
{
count--;
}
if ((count == 0) || (hw_sdio->sta & SDMMC_ERRORS))
{
cmd->err = -RT_ERROR;
}
}
/* data post configuration */
if (data != RT_NULL)
{
if (data->flags & DATA_DIR_READ)
{
#if defined(EMMC_RX_DUMP)
rt_kprintf("\nEMMC Rx:\n");
dump_hex(cache_buf, data->blks * data->blksize);
#endif
rt_memcpy(data->buf, cache_buf, data->blks * data->blksize);
}
}
}
/**
* @brief This function send sdio request.
* @param sdio rthw_sdio
* @param req request
* @retval None
*/
static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
struct sdio_pkg pkg;
struct rthw_sdio *sdio = host->private_data;
struct rt_mmcsd_data *data;
RTHW_SDIO_LOCK(sdio);
if (req->cmd != RT_NULL)
{
rt_memset(&pkg, 0, sizeof(pkg));
data = req->cmd->data;
pkg.cmd = req->cmd;
if (data != RT_NULL)
{
rt_uint32_t size = data->blks * data->blksize;
RT_ASSERT(size <= SDIO_BUFF_SIZE);
if (data->flags & DATA_DIR_WRITE)
{
#if defined(EMMC_TX_DUMP)
rt_kprintf("\nEMMC Tx:\n");
dump_hex(cache_buf, data->blks * data->blksize);
#endif
rt_memcpy(cache_buf, data->buf, size);
}
}
rthw_sdio_send_command(sdio, &pkg);
}
if (req->stop != RT_NULL)
{
rt_memset(&pkg, 0, sizeof(pkg));
pkg.cmd = req->stop;
rthw_sdio_send_command(sdio, &pkg);
}
RTHW_SDIO_UNLOCK(sdio);
mmcsd_req_complete(sdio->host);
}
/**
* @brief This function interrupt process function.
* @param host rt_mmcsd_host
* @retval None
*/
void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
{
struct rthw_sdio *sdio = host->private_data;
struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t intstatus = hw_sdio->sta;
/* clear irq flag*/
hw_sdio->icr = intstatus;
rt_event_send(&sdio->event, intstatus);
}
/**
* @brief This function config sdio.
* @param host rt_mmcsd_host
* @param io_cfg rt_mmcsd_io_cfg
* @retval None
*/
static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
rt_uint32_t temp, clk_src;
rt_uint32_t clk = io_cfg->clock;
struct rthw_sdio *sdio = host->private_data;
struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
LOG_D("clk:%dK width:%s%s%s power:%s%s%s",
clk/1000,
io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
);
RTHW_SDIO_LOCK(sdio);
clk_src = EMMC_CLOCK_FREQ;
if (clk > 0)
{
if (clk > host->freq_max)
{
clk = host->freq_max;
}
temp = DIV_ROUND_UP(clk_src, 2 * clk);
if (temp > 0x3FF)
{
temp = 0x3FF;
}
}
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
{
temp |= SDMMC_BUS_WIDE_8B;
}
else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
{
temp |= SDMMC_BUS_WIDE_4B;
}
else
{
temp |= SDMMC_BUS_WIDE_1B;
}
hw_sdio->clkcr = temp;
if (io_cfg->power_mode == MMCSD_POWER_ON)
hw_sdio->power |= SDMMC_POWER_PWRCTRL;
RTHW_SDIO_UNLOCK(sdio);
}
static const struct rt_mmcsd_host_ops ops =
{
rthw_sdio_request,
rthw_sdio_iocfg,
RT_NULL,
RT_NULL,
};
/**
* @brief This function create mmcsd host.
* @param sdio_des stm32_sdio_des
* @retval rt_mmcsd_host
*/
struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
{
struct rt_mmcsd_host *host;
struct rthw_sdio *sdio = RT_NULL;
if (sdio_des == RT_NULL)
{
return RT_NULL;
}
sdio = rt_malloc(sizeof(struct rthw_sdio));
if (sdio == RT_NULL)
{
LOG_E("malloc rthw_sdio fail");
return RT_NULL;
}
rt_memset(sdio, 0, sizeof(struct rthw_sdio));
host = mmcsd_alloc_host();
if (host == RT_NULL)
{
LOG_E("alloc host fail");
goto err;
}
rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
sdio->sdio_des.hw_sdio = (struct stm32_sdio *)EMMC_BASE_ADDRESS;
rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
/* set host default attributes */
host->ops = &ops;
host->freq_min = 400 * 1000;
host->freq_max = EMMC_MAX_FREQ;
host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */
host->flags = MMCSD_BUSWIDTH_8 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED;
host->max_seg_size = SDIO_BUFF_SIZE;
host->max_dma_segs = 1;
host->max_blk_size = 512;
host->max_blk_count = 512;
/* link up host and sdio */
sdio->host = host;
host->private_data = sdio;
/* ready to change */
mmcsd_change(host);
return host;
err:
if (sdio)
{
rt_free(sdio);
}
return RT_NULL;
}
void SDMMC2_IRQHandler(void)
{
rt_interrupt_enter();
/* Process All SDIO Interrupt Sources */
rthw_sdio_irq_process(host);
rt_interrupt_leave();
}
int rt_hw_sdio_init(void)
{
struct stm32_sdio_des sdio_des;
hsd.Instance = SDMMC2;
HAL_SD_MspInit(&hsd);
host = sdio_host_create(&sdio_des);
if (host == RT_NULL)
{
LOG_E("host create fail");
return RT_NULL;
}
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_sdio_init);
#if defined(EMMC_USING_DFS)
int mnt_init(void)
{
rt_device_t sd = RT_NULL;
#if defined(EMMC_RX_DUMP) || defined(EMMC_TX_DUMP)
rt_thread_delay(3000);
#else
rt_thread_delay(RT_TICK_PER_SECOND);
#endif
sd = rt_device_find("sd0");
if (sd == RT_NULL)
{
rt_kprintf("can't find emmc device!\n");
return RT_ERROR;
}
if (dfs_mount("sd0", "/", "elm", 0, 0) != 0)
{
rt_kprintf("file system mount failed!\n");
}
else
{
rt_kprintf("file system mount success!\n");
}
return 0;
}
INIT_APP_EXPORT(mnt_init);
#endif
#endif /* BSP_USING_SDMMC */

104
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-16 thread-liu first version
*/
#ifndef __DRV_EMMC_H__
#define __DRV_EMMC_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#include <string.h>
#include <drivers/mmcsd_core.h>
#include <drivers/sdio.h>
#define SDIO_BUFF_SIZE 4096
#ifndef EMMC_BASE_ADDRESS
#define EMMC_BASE_ADDRESS (SDMMC2)
#endif
#ifndef EMMC_CLOCK_FREQ
#define EMMC_CLOCK_FREQ (99U * 1000 * 1000)
#endif
#ifndef EMMC_MAX_FREQ
#define EMMC_MAX_FREQ (50 * 1000 * 1000)
#endif
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define SDMMC_ERRORS \
(SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \
SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \
SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \
SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL)
#define SDIO_MASKR_ALL \
(SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \
SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \
SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE)
#define HW_SDIO_DATATIMEOUT (0xFFFFFFFFU)
struct stm32_sdio
{
volatile rt_uint32_t power; /* offset 0x00 */
volatile rt_uint32_t clkcr; /* offset 0x04 */
volatile rt_uint32_t arg; /* offset 0x08 */
volatile rt_uint32_t cmd; /* offset 0x0C */
volatile rt_uint32_t respcmd; /* offset 0x10 */
volatile rt_uint32_t resp1; /* offset 0x14 */
volatile rt_uint32_t resp2; /* offset 0x18 */
volatile rt_uint32_t resp3; /* offset 0x1C */
volatile rt_uint32_t resp4; /* offset 0x20 */
volatile rt_uint32_t dtimer; /* offset 0x24 */
volatile rt_uint32_t dlen; /* offset 0x28 */
volatile rt_uint32_t dctrl; /* offset 0x2C */
volatile rt_uint32_t dcount; /* offset 0x30 */
volatile rt_uint32_t sta; /* offset 0x34 */
volatile rt_uint32_t icr; /* offset 0x38 */
volatile rt_uint32_t mask; /* offset 0x3C */
volatile rt_uint32_t acktimer; /* offset 0x40 */
volatile rt_uint32_t reserved0[3]; /* offset 0x44 ~ 0x4C */
volatile rt_uint32_t idmatrlr; /* offset 0x50 */
volatile rt_uint32_t idmabsizer; /* offset 0x54 */
volatile rt_uint32_t idmabase0r; /* offset 0x58 */
volatile rt_uint32_t idmabase1r; /* offset 0x5C */
volatile rt_uint32_t reserved1[1]; /* offset 0x60 */
volatile rt_uint32_t idmalar;
volatile rt_uint32_t idmabar;
volatile rt_uint32_t reserved2[5];
volatile rt_uint32_t fifo;
volatile rt_uint32_t reserved3[220];
volatile rt_uint32_t verr;
volatile rt_uint32_t ipidr;
volatile rt_uint32_t sidr;
};
typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio);
struct stm32_sdio_des
{
struct stm32_sdio *hw_sdio;
sdio_clk_get clk_get;
};
/* stm32 sdio dirver class */
struct stm32_sdio_class
{
struct stm32_sdio_des *des;
const struct stm32_sdio_config *cfg;
struct rt_mmcsd_host host;
};
extern void stm32_mmcsd_change(void);
#endif /* __DRV_SDIO_H__ */

4
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c
View File

@ -19,6 +19,8 @@
#define LOG_TAG "drv.pmic"
#include <drv_log.h>
#define I2C_NAME "i2c3"
static struct rt_i2c_bus_device *pmic_dev = RT_NULL;
/* i2c read reg */
@ -884,7 +886,7 @@ static int pmic_init(void)
{
BSP_PMIC_MspInit();
result = rt_hw_pmic_init("i2c3");
result = rt_hw_pmic_init(I2C_NAME);
if(result != RT_EOK)
{
LOG_D("stpmic init failed: %02x", result);

413
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c Normal file
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@ -0,0 +1,413 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-04 thread-liu the first version
*/
#include "board.h"
#if defined(BSP_USING_SD_CARD)
#include <dfs_fs.h>
#define DRV_DEBUG
//#define SDMMC_TX_DUMP
//#define SDMMC_RX_DUMP
#define LOG_TAG "drv.sdmmc"
#include <drv_log.h>
static SD_HandleTypeDef SDCARD_Handler = {0};
static HAL_SD_CardInfoTypeDef SDCardInfo = {0};
struct stm32_sd
{
struct rt_device sdcard;
struct rt_semaphore sd_lock;
volatile rt_uint8_t write_flage;
volatile rt_uint8_t read_flage;
volatile rt_base_t level;
};
static struct stm32_sd sd_device;
#define SD_TIMEOUT ((uint32_t)30 * 1000)
#define DETECT_PIN GET_PIN(G, 1)
#define LDO_PIN GET_PIN(F, 14)
struct rt_completion tx_comp;
struct rt_completion rx_comp;
/* SYSRAM SDMMC1/2 accesses */
#define SDIO_BUFF_SIZE 512
#if defined(__CC_ARM) || defined(__CLANG_ARM)
__attribute__((at(0x2FFC0000)))
#elif defined ( __GNUC__ )
__attribute__((at(0x2FFC0000)))
#elif defined(__ICCARM__)
#pragma location = 0x2FFC0000
#endif
static rt_uint32_t cache_buf[SDIO_BUFF_SIZE];
#if defined(SDMMC_RX_DUMP) || defined(SDMMC_TX_DUMP)
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
{
unsigned char *buf = (unsigned char *)ptr;
int i, j;
for (i = 0; i < buflen; i += 16)
{
rt_kprintf("%08X: ", i);
for (j = 0; j < 16; j++)
if (i + j < buflen)
rt_kprintf("%02X ", buf[i + j]);
else
rt_kprintf(" ");
rt_kprintf(" ");
for (j = 0; j < 16; j++)
if (i + j < buflen)
rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
rt_kprintf("\n");
}
}
#endif
static rt_err_t rt_hw_sd_is_detected(void)
{
return rt_pin_read(DETECT_PIN);
}
static rt_err_t rt_hw_sd_init(void)
{
/* sd ldo*/
rt_pin_mode(LDO_PIN, PIN_MODE_OUTPUT);
/* sd detect */
rt_pin_mode(DETECT_PIN, PIN_MODE_INPUT_PULLUP);
/* judge we have a sd card */
if (rt_hw_sd_is_detected() != 0x00)
{
LOG_E("can't find sd card!");
return RT_ERROR;
}
SDCARD_Handler.Instance = SDMMC1;
HAL_SD_DeInit(&SDCARD_Handler);
/* if CLKDIV = 0 then SDMMC Clock frequency = SDMMC Kernel Clock
else SDMMC Clock frequency = SDMMC Kernel Clock / [2 * CLKDIV].
SDMMC Kernel Clock = 99MHz, SDMMC Clock frequency = 50MHz */
SDCARD_Handler.Init.ClockDiv = 1;
SDCARD_Handler.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
SDCARD_Handler.Init.ClockEdge = SDMMC_CLOCK_EDGE_FALLING;
SDCARD_Handler.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
SDCARD_Handler.Init.BusWide = SDMMC_BUS_WIDE_4B;
if (HAL_SD_Init(&SDCARD_Handler) != RT_EOK)
{
LOG_E("sd device init error!");
return RT_ERROR;
}
if (HAL_SD_ConfigWideBusOperation(&SDCARD_Handler, SDMMC_BUS_WIDE_4B) != RT_EOK)
{
LOG_E("sd bus config error!");
return RT_ERROR;
}
if (HAL_SD_GetCardInfo(&SDCARD_Handler, &SDCardInfo) != RT_EOK)
{
LOG_E("sd get card info error!");
return RT_ERROR;
}
rt_thread_mdelay(100);
if(HAL_SD_GetCardState(&SDCARD_Handler) != HAL_SD_CARD_TRANSFER)
{
LOG_E("sd get card state error!");
return RT_ERROR;
}
return RT_EOK;
}
static void rt_hw_sd_deinit(void)
{
HAL_SD_DeInit(&SDCARD_Handler);
}
static rt_err_t sdcard_wait_ok(void)
{
rt_uint32_t tick_start = 0;
tick_start = rt_tick_get();
while ((rt_tick_get() - tick_start) < SD_TIMEOUT)
{
if (HAL_SD_GetCardState(&SDCARD_Handler) == HAL_SD_CARD_TRANSFER)
{
return HAL_OK;
}
}
return HAL_ERROR;
}
void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
{
if (status == SET)
{
rt_pin_write(LDO_PIN, PIN_HIGH);
}
else
{
rt_pin_write(LDO_PIN, PIN_LOW);
}
}
static rt_err_t rt_sdcard_init(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
struct stm32_sd *sd = (struct stm32_sd *)dev;
if (rt_sem_init(&sd->sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
{
LOG_E("init sd lock semaphore failed\n");
}
return RT_EOK;
}
static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_sdcard_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
/**
* @brief Reads Sector(s)
* @param dev : sd dev
* @param sector: Sector address (LBA) Data buffer to store read data
* @param *buffer: Data buffer to store read data
* @param count: Number of sectors to read (1..128)
* @retval DRESULT: Operation result
*/
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t sector, void *buffer, rt_size_t count)
{
RT_ASSERT(dev != RT_NULL);
struct stm32_sd *sd = (struct stm32_sd *)dev;
rt_uint8_t ret = RT_EOK;
volatile uint32_t tickstart = 0;
sd->read_flage = 0;
rt_memset(cache_buf, 0x00, BLOCKSIZE * count);
ret = sdcard_wait_ok();
if (ret != RT_EOK)
{
LOG_D("sdmmc busy!");
return 0;
}
rt_sem_take(&sd->sd_lock, RT_WAITING_FOREVER);
ret = HAL_SD_ReadBlocks_DMA(&SDCARD_Handler, (rt_uint8_t *)cache_buf, (uint32_t)sector, count);
rt_sem_release(&sd->sd_lock);
/* Wait that writing process is completed or a timeout occurs */
tickstart = rt_tick_get();
if (ret == HAL_OK)
{
while ((sd->read_flage == 0) && (rt_tick_get() - tickstart) < SD_TIMEOUT)
{
}
/* over time */
if (sd->read_flage == 0)
{
return 0;
}
else
{
sd->read_flage = 0;
tickstart = rt_tick_get();
while ((rt_tick_get() - tickstart) < SD_TIMEOUT)
{
if (sdcard_wait_ok() == RT_EOK)
{
sd->level=rt_hw_interrupt_disable();
rt_memcpy((rt_uint8_t *)(buffer), cache_buf, BLOCKSIZE * count);
rt_hw_interrupt_enable(sd->level);
#if defined(SDMMC_RX_DUMP)
rt_kprintf("\nsd rx: \n");
dump_hex(cache_buf, BLOCKSIZE * count);
#endif
return count;
}
}
}
}
return 0;
}
/**
* @brief Writes block(s) to a specified address in an SD card, in DMA mode.
* @param dev SD device
* @param sector Block index from where data is to be written P
* @param *buffer Pointer to the buffer that will contain the data to transmit
* @param count Number of SD blocks to write
* @retval BSP status
*/
static rt_size_t rt_sdcard_write(rt_device_t dev, rt_off_t sector, const void *buffer, rt_size_t count)
{
RT_ASSERT(dev != RT_NULL);
struct stm32_sd *sd = (struct stm32_sd *)dev;
rt_uint32_t i = 0;
rt_uint8_t ret = RT_EOK;
for (i = 0; i < count; i++)
{
sd->level = rt_hw_interrupt_disable();
rt_memset(cache_buf, 0x00, BLOCKSIZE);
rt_memcpy(cache_buf, (rt_uint32_t *)((uintptr_t)buffer + BLOCKSIZE * i), BLOCKSIZE);
rt_hw_interrupt_enable(sd->level);
#if defined(SDMMC_TX_DUMP)
rt_kprintf("\nsd tx: \n");
dump_hex(cache_buf, BLOCKSIZE);
#endif
ret = sdcard_wait_ok();
if (ret != RT_EOK)
{
LOG_D("sdmmc busy!");
return 0;
}
rt_completion_init(&tx_comp);
ret = HAL_SD_WriteBlocks_DMA(&SDCARD_Handler, (rt_uint8_t *)cache_buf, (rt_uint32_t)(sector + i), 1);
if (ret != HAL_OK)
{
rt_kprintf("sd write error!\n");
return 0;
}
rt_completion_wait(&tx_comp,RT_WAITING_FOREVER);
}
return count;
}
static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
geometry->bytes_per_sector = 512;
geometry->block_size = SDCARD_Handler.SdCard.BlockSize;
geometry->sector_count = SDCARD_Handler.SdCard.BlockNbr;
}
return RT_EOK;
}
void SDMMC1_IRQHandler(void)
{
rt_interrupt_enter();
HAL_SD_IRQHandler(&SDCARD_Handler);
rt_interrupt_leave();
}
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
{
if (hsd->Instance == SDCARD_Handler.Instance)
{
sd_device.read_flage = 1;
}
}
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
{
if (hsd->Instance == SDCARD_Handler.Instance)
{
rt_completion_done(&tx_comp);
}
}
int rt_hw_sdcard_init(void)
{
if (rt_hw_sd_init() != RT_EOK)
{
rt_hw_sd_deinit();
LOG_E("sdcard init failed");
return RT_ERROR;
}
/* register sdcard device */
sd_device.sdcard.type = RT_Device_Class_Block;
sd_device.sdcard.init = rt_sdcard_init;
sd_device.sdcard.open = rt_sdcard_open;
sd_device.sdcard.close = rt_sdcard_close;
sd_device.sdcard.read = rt_sdcard_read;
sd_device.sdcard.write = rt_sdcard_write;
sd_device.sdcard.control = rt_sdcard_control;
/* no private */
sd_device.sdcard.user_data = &SDCardInfo;
rt_device_register(&sd_device.sdcard, "sd_card", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
LOG_I("sd card init success!");
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_sdcard_init);
#if defined(SD_USING_DFS)
int mnt_init(void)
{
rt_device_t sd_dev = RT_NULL;
LOG_I("init sd card file system.");
#if defined(SDMMC_RX_DUMP) || defined(SDMMC_TX_DUMP)
rt_thread_delay(3000);
#else
rt_thread_delay(RT_TICK_PER_SECOND);
#endif
sd_dev = rt_device_find("sd_card");
if (sd_dev == RT_NULL)
{
LOG_E("can't find sd deivce name!");
return RT_ERROR;
}
if (dfs_mount("sd_card", "/", "elm", 0, 0) != 0)
{
rt_kprintf("file system mount failed!\n");
}
else
{
rt_kprintf("file system mount success!\n");
}
return 0;
}
INIT_APP_EXPORT(mnt_init);
#endif
#endif

572
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c Normal file
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@ -0,0 +1,572 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-31 Zero-Free first implementation
* 2020-07-02 thread-liu Porting for STM32MP1
*/
#include "board.h"
#ifdef BSP_USING_AUDIO
#include "drv_wm8994.h"
#include <dfs_posix.h>
#define DRV_DEBUG
#define LOG_TAG "drv.sound"
#include <drv_log.h>
#define SOUND_BUS_NAME "i2c2"
#define TX_FIFO_SIZE (4096)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
__attribute__((at(0x2FFC2000)))
#elif defined ( __GNUC__ )
__attribute__((at(0x2FFC2000)))
#elif defined(__ICCARM__)
#pragma location = 0x2FFC2000
#endif
static rt_uint8_t AUDIO_TX_FIFO[TX_FIFO_SIZE];
struct sound_device
{
struct rt_audio_device audio;
struct rt_audio_configure replay_config;
rt_device_t decoder;
rt_uint8_t *tx_fifo;
rt_uint8_t volume;
};
static struct sound_device snd_dev = {0};
SAI_HandleTypeDef hsai_BlockA2 = {0};
extern DMA_HandleTypeDef hdma_sai2_a;
static void rt_hw_sai2a_init(void)
{
hsai_BlockA2.Instance = SAI2_Block_A;
hsai_BlockA2.Init.Protocol = SAI_FREE_PROTOCOL;
hsai_BlockA2.Init.AudioMode = SAI_MODEMASTER_TX;
hsai_BlockA2.Init.DataSize = SAI_DATASIZE_16;
hsai_BlockA2.Init.FirstBit = SAI_FIRSTBIT_MSB;
hsai_BlockA2.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
hsai_BlockA2.Init.Synchro = SAI_ASYNCHRONOUS;
hsai_BlockA2.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE;
hsai_BlockA2.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;
hsai_BlockA2.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF;
hsai_BlockA2.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_44K;
hsai_BlockA2.Init.SynchroExt = SAI_SYNCEXT_DISABLE;
hsai_BlockA2.Init.MonoStereoMode = SAI_STEREOMODE;
hsai_BlockA2.Init.CompandingMode = SAI_NOCOMPANDING;
hsai_BlockA2.Init.TriState = SAI_OUTPUT_NOTRELEASED;
hsai_BlockA2.Init.PdmInit.Activation = DISABLE;
hsai_BlockA2.Init.PdmInit.MicPairsNbr = 0;
hsai_BlockA2.Init.PdmInit.ClockEnable = SAI_PDM_CLOCK1_ENABLE;
hsai_BlockA2.FrameInit.FrameLength = 64;
hsai_BlockA2.FrameInit.ActiveFrameLength = 32;
hsai_BlockA2.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;
hsai_BlockA2.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
hsai_BlockA2.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
hsai_BlockA2.SlotInit.FirstBitOffset = 0;
hsai_BlockA2.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE;
hsai_BlockA2.SlotInit.SlotNumber = 2;
hsai_BlockA2.SlotInit.SlotActive = (SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1 | SAI_SLOTACTIVE_2 | SAI_SLOTACTIVE_3);
if(HAL_OK != HAL_SAI_Init(&hsai_BlockA2))
{
Error_Handler();
}
/* Enable SAI to generate clock used by audio driver */
__HAL_SAI_ENABLE(&hsai_BlockA2);
}
void DMA1_Stream0_IRQHandler(void)
{
HAL_DMA_IRQHandler(&hdma_sai2_a);
}
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
{
if (hsai == &hsai_BlockA2)
{
rt_audio_tx_complete(&snd_dev.audio);
}
}
void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
{
if (hsai == &hsai_BlockA2)
{
rt_audio_tx_complete(&snd_dev.audio);
}
}
void SAIA_Frequency_Set(uint32_t frequency)
{
/* Disable SAI peripheral to allow access to SAI internal registers */
__HAL_SAI_DISABLE(&hsai_BlockA2);
/* Update the SAI audio frequency configuration */
hsai_BlockA2.Init.AudioFrequency = frequency;
HAL_SAI_Init(&hsai_BlockA2);
/* Enable SAI peripheral to generate MCLK */
__HAL_SAI_ENABLE(&hsai_BlockA2);
}
void SAIA_Channels_Set(uint8_t channels)
{
if (channels == 1)
{
hsai_BlockA2.Init.MonoStereoMode = SAI_MONOMODE;
}
else
{
hsai_BlockA2.Init.MonoStereoMode = SAI_STEREOMODE;
}
__HAL_SAI_DISABLE(&hsai_BlockA2);
HAL_SAI_Init(&hsai_BlockA2);
__HAL_SAI_ENABLE(&hsai_BlockA2);
}
/**
* RT-Thread Audio Device Driver Interface
*/
static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
rt_err_t result = RT_EOK;
struct sound_device *snd_dev;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
switch (caps->main_type)
{
case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */
{
switch (caps->sub_type)
{
case AUDIO_TYPE_QUERY:
caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
break;
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */
{
switch (caps->sub_type)
{
case AUDIO_DSP_PARAM:
caps->udata.config.samplerate = snd_dev->replay_config.samplerate;
caps->udata.config.channels = snd_dev->replay_config.channels;
caps->udata.config.samplebits = snd_dev->replay_config.samplebits;
break;
case AUDIO_DSP_SAMPLERATE:
caps->udata.config.samplerate = snd_dev->replay_config.samplerate;
break;
case AUDIO_DSP_CHANNELS:
caps->udata.config.channels = snd_dev->replay_config.channels;
break;
case AUDIO_DSP_SAMPLEBITS:
caps->udata.config.samplebits = snd_dev->replay_config.samplebits;
break;
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_MIXER: /* report the Mixer Units */
{
switch (caps->sub_type)
{
case AUDIO_MIXER_QUERY:
caps->udata.mask = AUDIO_MIXER_VOLUME;
break;
case AUDIO_MIXER_VOLUME:
rt_device_control(snd_dev->decoder, GET_VOLUME, &(caps->udata.value));
break;
default:
result = -RT_ERROR;
break;
}
break;
}
default:
result = -RT_ERROR;
break;
}
return result;
}
static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
rt_err_t result = RT_EOK;
struct sound_device *snd_dev;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
switch (caps->main_type)
{
case AUDIO_TYPE_MIXER:
{
switch (caps->sub_type)
{
case AUDIO_MIXER_VOLUME:
{
rt_uint8_t volume = caps->udata.value;
rt_device_control(snd_dev->decoder, SET_VOLUME, &volume);
snd_dev->volume = volume;
LOG_D("set volume %d", volume);
break;
}
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_OUTPUT:
{
switch (caps->sub_type)
{
case AUDIO_DSP_PARAM:
{
/* set samplerate */
SAIA_Frequency_Set(caps->udata.config.samplerate);
/* set channels */
SAIA_Channels_Set(caps->udata.config.channels);
/* save configs */
snd_dev->replay_config.samplerate = caps->udata.config.samplerate;
snd_dev->replay_config.channels = caps->udata.config.channels;
snd_dev->replay_config.samplebits = caps->udata.config.samplebits;
LOG_D("set samplerate %d", snd_dev->replay_config.samplerate);
break;
}
case AUDIO_DSP_SAMPLERATE:
{
SAIA_Frequency_Set(caps->udata.config.samplerate);
snd_dev->replay_config.samplerate = caps->udata.config.samplerate;
LOG_D("set samplerate %d", snd_dev->replay_config.samplerate);
break;
}
case AUDIO_DSP_CHANNELS:
{
SAIA_Channels_Set(caps->udata.config.channels);
snd_dev->replay_config.channels = caps->udata.config.channels;
LOG_D("set channels %d", snd_dev->replay_config.channels);
break;
}
case AUDIO_DSP_SAMPLEBITS:
{
/* not support */
snd_dev->replay_config.samplebits = caps->udata.config.samplebits;
break;
}
default:
result = -RT_ERROR;
break;
}
break;
}
default:
break;
}
return result;
}
static rt_err_t sound_init(struct rt_audio_device *audio)
{
rt_err_t result = RT_EOK;
struct sound_device *snd_dev;
rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
rt_hw_sai2a_init();
/* set default params */
SAIA_Frequency_Set(snd_dev->replay_config.samplerate);
SAIA_Channels_Set(snd_dev->replay_config.channels);
/* set audio play type */
rt_device_control(snd_dev->decoder, SET_PLAY_TYPE, &play_type);
/* open lowlevel audio device */
rt_device_open(snd_dev->decoder, RT_DEVICE_OFLAG_WRONLY);
rt_device_init(snd_dev->decoder);
/* check device id */
result = rt_device_control(snd_dev->decoder, GET_ID, RT_NULL);
if (result != RT_EOK)
{
LOG_E("can't find low level audio device!");
return RT_ERROR;
}
return result;
}
static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
{
struct sound_device *snd_dev;
rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
if (stream == AUDIO_STREAM_REPLAY)
{
LOG_D("open sound device");
rt_device_control(snd_dev->decoder, SET_PLAY_TYPE, &play_type);
rt_device_control(snd_dev->decoder, START_PLAY, RT_NULL);
if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, snd_dev->tx_fifo, TX_FIFO_SIZE / 2) != HAL_OK)
{
return RT_ERROR;
}
}
return RT_EOK;
}
static rt_err_t sound_stop(struct rt_audio_device *audio, int stream)
{
struct sound_device *device;
RT_ASSERT(audio != RT_NULL);
device = (struct sound_device *)audio->parent.user_data;
if (stream == AUDIO_STREAM_REPLAY)
{
HAL_SAI_DMAStop(&hsai_BlockA2);
rt_device_close(device->decoder);
LOG_D("close sound device");
}
return RT_EOK;
}
static void sound_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
{
struct sound_device *device;
RT_ASSERT(audio != RT_NULL);
device = (struct sound_device *)audio->parent.user_data;
info->buffer = device->tx_fifo;
info->total_size = TX_FIFO_SIZE;
info->block_size = TX_FIFO_SIZE / 2;
info->block_count = 2;
}
static struct rt_audio_ops snd_ops =
{
.getcaps = sound_getcaps,
.configure = sound_configure,
.init = sound_init,
.start = sound_start,
.stop = sound_stop,
.transmit = RT_NULL,
.buffer_info = sound_buffer_info,
};
int rt_hw_sound_init(void)
{
rt_err_t result = RT_EOK;
struct rt_device *device = RT_NULL;
rt_memset(AUDIO_TX_FIFO, 0, TX_FIFO_SIZE);
snd_dev.tx_fifo = AUDIO_TX_FIFO;
/* init default configuration */
snd_dev.replay_config.samplerate = 44100;
snd_dev.replay_config.channels = 2;
snd_dev.replay_config.samplebits = 16;
snd_dev.volume = 55;
/* find lowlevel decoder device*/
snd_dev.decoder = rt_device_find("decoder");
if (snd_dev.decoder == RT_NULL)
{
LOG_E("cant't find lowlevel decoder deivce!");
return RT_ERROR;
}
/* register sound device */
snd_dev.audio.ops = &snd_ops;
result = rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev);
/* check sound device register success or not */
if (result != RT_EOK)
{
device = &(snd_dev.audio.parent);
rt_device_unregister(device);
LOG_E("sound device init error!");
return RT_ERROR;
}
return RT_EOK;
}
INIT_APP_EXPORT(rt_hw_sound_init);
struct RIFF_HEADER_DEF
{
char riff_id[4]; // 'R','I','F','F'
uint32_t riff_size;
char riff_format[4]; // 'W','A','V','E'
};
struct WAVE_FORMAT_DEF
{
uint16_t FormatTag;
uint16_t Channels;
uint32_t SamplesPerSec;
uint32_t AvgBytesPerSec;
uint16_t BlockAlign;
uint16_t BitsPerSample;
};
struct FMT_BLOCK_DEF
{
char fmt_id[4]; // 'f','m','t',' '
uint32_t fmt_size;
struct WAVE_FORMAT_DEF wav_format;
};
struct DATA_BLOCK_DEF
{
char data_id[4]; // 'R','I','F','F'
uint32_t data_size;
};
struct wav_info
{
struct RIFF_HEADER_DEF header;
struct FMT_BLOCK_DEF fmt_block;
struct DATA_BLOCK_DEF data_block;
};
int wavplay_sample(int argc, char **argv)
{
#define BUFSZ 1024
#define SOUND_DEVICE_NAME "sound0"
static rt_device_t sound_dev;
int fd = -1;
uint8_t *buffer = NULL;
struct wav_info *info = NULL;
struct rt_audio_caps caps = {0};
if (argc != 2)
{
rt_kprintf("Usage:\n");
rt_kprintf("wavplay_sample song.wav\n");
return 0;
}
fd = open(argv[1], O_WRONLY);
if (fd < 0)
{
rt_kprintf("open file failed!\n");
goto __exit;
}
buffer = rt_malloc(BUFSZ);
if (buffer == RT_NULL)
goto __exit;
info = (struct wav_info *) rt_malloc(sizeof * info);
if (info == RT_NULL)
goto __exit;
if (read(fd, &(info->header), sizeof(struct RIFF_HEADER_DEF)) <= 0)
goto __exit;
if (read(fd, &(info->fmt_block), sizeof(struct FMT_BLOCK_DEF)) <= 0)
goto __exit;
if (read(fd, &(info->data_block), sizeof(struct DATA_BLOCK_DEF)) <= 0)
goto __exit;
rt_kprintf("wav information:\n");
rt_kprintf("samplerate %d\n", info->fmt_block.wav_format.SamplesPerSec);
rt_kprintf("channel %d\n", info->fmt_block.wav_format.Channels);
sound_dev = rt_device_find(SOUND_DEVICE_NAME);
rt_device_open(sound_dev, RT_DEVICE_OFLAG_WRONLY);
caps.main_type = AUDIO_TYPE_OUTPUT;
caps.sub_type = AUDIO_DSP_PARAM;
caps.udata.config.samplerate = info->fmt_block.wav_format.SamplesPerSec;
caps.udata.config.channels = info->fmt_block.wav_format.Channels;
caps.udata.config.samplebits = 16;
rt_device_control(sound_dev, AUDIO_CTL_CONFIGURE, &caps);
while (1)
{
int length;
length = read(fd, buffer, BUFSZ);
if (length <= 0)
break;
rt_device_write(sound_dev, 0, buffer, length);
}
rt_device_close(sound_dev);
__exit:
if (fd >= 0)
close(fd);
if (buffer)
rt_free(buffer);
if (info)
rt_free(info);
return 0;
}
MSH_CMD_EXPORT(wavplay_sample, play wav file);
#endif

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-02 thread-liu first version
*/
#include "board.h"
#if defined(BSP_USING_AUDIO)
#include <drv_wm8994.h>
#define DRV_DEBUG
#define LOG_TAG "drv.wm8994"
#include <drv_log.h>
#define CHIP_ADDRESS 0x1B /* wm8994 address */
#define I2C_NAME "i2c2"
struct wm8994_dev
{
struct rt_device dev;
struct rt_i2c_bus_device *i2c_bus;
rt_uint16_t id;
rt_uint16_t type;
};
static struct wm8994_dev rt_wm8994 = {0};
/* i2c read reg */
static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uint8_t len, rt_uint8_t *buf)
{
struct rt_i2c_msg msg[2] = {0, 0};
static rt_uint8_t i2c_reg[2] = {0, 0};
RT_ASSERT(bus != RT_NULL);
i2c_reg[0] = ((uint16_t)(reg >> 8) & 0xFF);
i2c_reg[1] = ((uint16_t)(reg) & 0xFF);
msg[0].addr = CHIP_ADDRESS;
msg[0].flags = RT_I2C_WR;
msg[0].buf = i2c_reg;
msg[0].len = 2;
msg[1].addr = CHIP_ADDRESS;
msg[1].flags = RT_I2C_RD;
msg[1].len = len;
msg[1].buf = buf;
if (rt_i2c_transfer(bus, msg, 2) == 2)
{
return RT_EOK;
}
return RT_ERROR;
}
/* i2c write reg */
static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uint16_t data)
{
rt_uint8_t buf[4];
struct rt_i2c_msg msgs;
RT_ASSERT(bus != RT_NULL);
buf[0] = ((uint16_t)(reg >> 8) & 0xFF);
buf[1] = ((uint16_t)(reg) & 0xFF);
buf[2] = ((uint16_t)(data >> 8) & 0xFF);
buf[3] = ((uint16_t)(data) & 0xFF);
msgs.addr = CHIP_ADDRESS;
msgs.flags = RT_I2C_WR;
msgs.buf = buf;
msgs.len = 4;
if (rt_i2c_transfer(bus, &msgs, 1) == 1)
{
return RT_EOK;
}
return RT_ERROR;
}
static rt_err_t wm8994_set_output_mode(struct rt_i2c_bus_device *bus, rt_uint16_t mode)
{
switch (mode & 0x000F)
{
case OUTPUT_DEVICE_SPEAKER:
/* Enable DAC1 (Left), Enable DAC1 (Right),
* Disable DAC2 (Left), Disable DAC2 (Right) */
write_reg(bus, 0x0005, 0x0C0C);
/* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
write_reg(bus, 0x0601, 0x0000);
/* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
write_reg(bus, 0x0602, 0x0000);
/* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
write_reg(bus, 0x0604, 0x0002);
/* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
write_reg(bus, 0x0605, 0x0002);
break;
case OUTPUT_DEVICE_HEADPHONE:
/* Disable DAC1 (Left), Disable DAC1 (Right),
Enable DAC2 (Left), Enable DAC2 (Right)*/
write_reg(bus, 0x05, 0x0303);
/* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
write_reg(bus, 0x0601, 0x01);
/* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
write_reg(bus, 0x0602, 0x01);
/* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
write_reg(bus, 0x0604, 0x00);
/* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
write_reg(bus, 0x0605, 0x00);
break;
case OUTPUT_DEVICE_BOTH:
default:
break;
}
return RT_EOK;
}
static rt_err_t wm8994_set_input_mode(struct rt_i2c_bus_device *bus, rt_uint16_t mode)
{
switch (mode & 0x01F0)
{
case INPUT_DEVICE_DIGITAL_MICROPHONE_2:
/* Enable AIF1ADC2 (Left), Enable AIF1ADC2 (Right)
* Enable DMICDAT2 (Left), Enable DMICDAT2 (Right)
* Enable Left ADC, Enable Right ADC */
write_reg(bus, 0x04, 0x0C30);
/* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
write_reg(bus, 0x0450, 0x00DB);
/* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
write_reg(bus, 0x02, 0x6000);
/* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
write_reg(bus, 0x0608, 0x0002);
/* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
write_reg(bus, 0x0609, 0x0002);
/* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC2 signal detect */
write_reg(bus, 0x0700, 0x000E);
break;
case INPUT_DEVICE_INPUT_LINE_1:
/* IN1LN_TO_IN1L, IN1LP_TO_VMID, IN1RN_TO_IN1R, IN1RP_TO_VMID */
write_reg(bus, 0x28, 0x0011);
/* Disable mute on IN1L_TO_MIXINL and +30dB on IN1L PGA output */
write_reg(bus, 0x29, 0x0035);
/* Disable mute on IN1R_TO_MIXINL, Gain = +30dB */
write_reg(bus, 0x2A, 0x0035);
/* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
* Enable Left ADC, Enable Right ADC */
write_reg(bus, 0x04, 0x0303);
/* Enable AIF1 DRC1 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
write_reg(bus, 0x0440, 0x00DB);
/* Enable IN1L and IN1R, Disable IN2L and IN2R, Enable Thermal sensor & shutdown */
write_reg(bus, 0x02, 0x6350);
/* Enable the ADCL(Left) to AIF1 Timeslot 0 (Left) mixer path */
write_reg(bus, 0x0606, 0x0002);
/* Enable the ADCR(Right) to AIF1 Timeslot 0 (Right) mixer path */
write_reg(bus, 0x0607, 0x0002);
/* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
write_reg(bus, 0x0700, 0x000D);
break;
case INPUT_DEVICE_DIGITAL_MICROPHONE_1:
/* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
* Enable DMICDAT1 (Left), Enable DMICDAT1 (Right)
* Enable Left ADC, Enable Right ADC */
write_reg(bus, 0x04, 0x030C);
/* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
write_reg(bus, 0x0440, 0x00DB);
/* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
write_reg(bus, 0x02, 0x6350);
/* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */
write_reg(bus, 0x0606, 0x0002);
/* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */
write_reg(bus, 0x0607, 0x0002);
/* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
write_reg(bus, 0x0700, 0x000D);
break;
case INPUT_DEVICE_DIGITAL_MIC1_MIC2:
/* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
* Enable DMICDAT1 (Left), Enable DMICDAT1 (Right)
* Enable Left ADC, Enable Right ADC */
write_reg(bus, 0x04, 0x0F3C);
/* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
write_reg(bus, 0x0450, 0x00DB);
/* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
write_reg(bus, 0x0440, 0x00DB);
/* Disable IN1L, IN1R, Enable IN2L, IN2R, Thermal sensor & shutdown */
write_reg(bus, 0x02, 0x63A0);
/* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */
write_reg(bus, 0x0606, 0x0002);
/* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */
write_reg(bus, 0x0607, 0x0002);
/* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
write_reg(bus, 0x0608, 0x0002);
/* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
write_reg(bus, 0x0609, 0x0002);
/* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
write_reg(bus, 0x0700, 0x000D);
break;
case INPUT_DEVICE_INPUT_LINE_2:
default:
/* Actually, no other input devices supported */
break;
}
return RT_EOK;
}
static rt_err_t _wm8994_init(struct wm8994_dev *dev)
{
RT_ASSERT(dev != RT_NULL);
/* wm8994 Errata Work-Arounds */
write_reg(dev->i2c_bus, 0x0102, 0x0003);
write_reg(dev->i2c_bus, 0x0817, 0x0000);
write_reg(dev->i2c_bus, 0x0102, 0x0000);
/* Enable VMID soft start (fast), Start-up Bias Current Enabled */
write_reg(dev->i2c_bus, 0x0039, 0x006C);
/* Enable bias generator, Enable VMID */
if ((dev->type & 0x01F0) != 0)
{
/* audio input */
write_reg(dev->i2c_bus, 0x0001, 0x0013);
}
else
{
/* audio output */
write_reg(dev->i2c_bus, 0x0001, 0x0003);
}
rt_thread_mdelay(50);
if ((dev->type & 0x000F) != 0 )
{
/* Path Configurations for output */
wm8994_set_output_mode(dev->i2c_bus, dev->type);
}
if ((dev->type & 0x01F0) != 0 )
{
/* Path Configurations for input */
wm8994_set_input_mode(dev->i2c_bus, dev->type);
}
if (dev->type & INPUT_DEVICE_DIGITAL_MIC1_MIC2)
{
/* AIF1 Word Length = 16-bits, AIF1 Format = DSP mode */
write_reg(dev->i2c_bus, 0x0300, 0x4018);
}
else
{
/* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */
write_reg(dev->i2c_bus, 0x0300, 0x4010);
}
/* slave mode */
write_reg(dev->i2c_bus, 0x0302, 0x0000);
/* Enable the DSP processing clock for AIF1, Enable the core clock */
write_reg(dev->i2c_bus, 0x0208, 0x000A);
/* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */
write_reg(dev->i2c_bus, 0x0200, 0x0001);
/* Audio output selected */
if ((dev->type & 0x000F) != 0 )
{
if (dev->type & OUTPUT_DEVICE_HEADPHONE)
{
/* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */
write_reg(dev->i2c_bus, 0x2D, 0x0100);
/* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */
write_reg(dev->i2c_bus, 0x2E, 0x0100);
/* Startup sequence for Headphone */
write_reg(dev->i2c_bus, 0x0110, 0x8100);
rt_thread_mdelay(300);
/* Soft un-Mute the AIF1 Timeslot 0 DAC1 path L&R */
write_reg(dev->i2c_bus, 0x0420, 0x0000);
}
/* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */
write_reg(dev->i2c_bus, 0x03, 0x0300);
/* Left Speaker Mixer Volume = 0dB */
write_reg(dev->i2c_bus, 0x22, 0x0000);
/* Speaker output mode = Class D, Right Speaker Mixer Volume = 0dB ((0x23, 0x0100) = class AB)*/
write_reg(dev->i2c_bus, 0x23, 0x0000);
/* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path,
Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path */
write_reg(dev->i2c_bus, 0x36, 0x0300);
/* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */
write_reg(dev->i2c_bus, 0x01, 0x3003);
/* Headphone/Speaker Enable */
if (dev->type & INPUT_DEVICE_DIGITAL_MIC1_MIC2)
{
/* Enable Class W, Class W Envelope Tracking = AIF1 Timeslots 0 and 1 */
write_reg(dev->i2c_bus, 0x51, 0x0205);
}
else
{
/* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */
write_reg(dev->i2c_bus, 0x51, 0x0005);
}
/* Enable bias generator, Enable VMID, Enable HPOUT1 (Left) and Enable HPOUT1 (Right) input stages */
/* idem for Speaker */
write_reg(dev->i2c_bus, 0x01, 0x3303);
/* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */
write_reg(dev->i2c_bus, 0x60, 0x0022);
/* Enable Charge Pump */
write_reg(dev->i2c_bus, 0x4C, 0x9F25);
/* Add Delay */
rt_thread_mdelay(15);
/* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */
write_reg(dev->i2c_bus, 0x2D, 0x0001);
/* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */
write_reg(dev->i2c_bus, 0x2E, 0x0001);
/* Enable Left Output Mixer (MIXOUTL), Enable Right Output Mixer (MIXOUTR) */
/* idem for SPKOUTL and SPKOUTR */
write_reg(dev->i2c_bus, 0x03, 0x0330);
/* Enable DC Servo and trigger start-up mode on left and right channels */
write_reg(dev->i2c_bus, 0x54, 0x0033);
/* Add Delay */
rt_thread_mdelay(200);
/* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages. Remove clamps */
write_reg(dev->i2c_bus, 0x60, 0x00EE);
/* Unmute DAC 1 (Left) */
write_reg(dev->i2c_bus, 0x0610, 0x00C0);
/* Unmute DAC 1 (Right) */
write_reg(dev->i2c_bus, 0x0611, 0x00C0);
/* Unmute the AIF1 Timeslot 0 DAC path */
write_reg(dev->i2c_bus, 0x0420, 0x0000);
/* Unmute DAC 2 (Left) */
write_reg(dev->i2c_bus, 0x0612, 0x00C0);
/* Unmute DAC 2 (Right) */
write_reg(dev->i2c_bus, 0x0613, 0x00C0);
/* Unmute the AIF1 Timeslot 1 DAC2 path */
write_reg(dev->i2c_bus, 0x0422, 0x0000);
}
/* Audio input selected */
if ((dev->type & 0x01F0) != 0 )
{
if ((dev->type & INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (dev->type & INPUT_DEVICE_DIGITAL_MICROPHONE_2))
{
/* Enable Microphone bias 1 generator, Enable VMID */
write_reg(dev->i2c_bus, 0x01, 0x0013);
/* ADC oversample enable */
write_reg(dev->i2c_bus, 0x0620, 0x0002);
/* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
write_reg(dev->i2c_bus, 0x0411, 0x3800);
}
else if (dev->type & INPUT_DEVICE_DIGITAL_MIC1_MIC2)
{
/* Enable Microphone bias 1 generator, Enable VMID */
write_reg(dev->i2c_bus, 0x01, 0x0013);
/* ADC oversample enable */
write_reg(dev->i2c_bus, 0x0620, 0x0002);
/* AIF ADC1 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
write_reg(dev->i2c_bus, 0x0410, 0x1800);
/* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
write_reg(dev->i2c_bus, 0x0411, 0x1800);
}
else if ((dev->type & INPUT_DEVICE_INPUT_LINE_1) || (dev->type & INPUT_DEVICE_INPUT_LINE_2))
{
/* Disable mute on IN1L, IN1L Volume = +0dB */
write_reg(dev->i2c_bus, 0x18, 0x000B);
/* Disable mute on IN1R, IN1R Volume = +0dB */
write_reg(dev->i2c_bus, 0x1A, 0x000B);
/* AIF ADC1 HPF enable, HPF cut = hifi mode fc=4Hz at fs=48kHz */
write_reg(dev->i2c_bus, 0x0410, 0x1800);
}
}
/* Return communication control value */
return RT_EOK;
}
static rt_err_t _read_id(struct rt_i2c_bus_device *bus, rt_uint16_t *id)
{
rt_uint8_t read_value[2];
read_reg(bus, 0x0000, 2, read_value);
*id = ((uint16_t)(read_value[0] << 8) & 0xFF00);
*id |= ((uint16_t)(read_value[1])& 0x00FF);
if (*id != WM8994_ID)
{
LOG_E("error id: 0x%04x", *id);
return RT_ERROR;
}
LOG_I("wm8994 init success, id: %04x", *id);
return RT_EOK;
}
static rt_err_t _set_mute(struct rt_i2c_bus_device *bus, uint32_t cmd)
{
/* Set the Mute mode */
if (cmd == AUDIO_MUTE_ON)
{
/* Soft Mute the AIF1 Timeslot 0 DAC1 path L&R */
write_reg(bus, 0x420, 0x0200);
/* Soft Mute the AIF1 Timeslot 1 DAC2 path L&R */
write_reg(bus, 0x422, 0x0200);
}
else /* AUDIO_MUTE_OFF Disable the Mute */
{
/* Unmute the AIF1 Timeslot 0 DAC1 path L&R */
write_reg(bus, 0x420, 0x0010);
/* Unmute the AIF1 Timeslot 1 DAC2 path L&R */
write_reg(bus, 0x422, 0x0010);
}
return RT_EOK;
}
static rt_err_t _play(struct rt_i2c_bus_device *bus)
{
_set_mute(bus, AUDIO_MUTE_OFF);
return RT_EOK;
}
static rt_err_t _set_volume(struct rt_i2c_bus_device *bus, rt_uint16_t type, rt_uint8_t volume)
{
rt_uint8_t convertedvol = VOLUME_CONVERT(volume);
if (type & 0x000F)
{
/* Output volume */
if(convertedvol > 0x3E)
{
/* Unmute audio codec */
_set_mute(bus, AUDIO_MUTE_OFF);
/* Left Headphone Volume */
write_reg(bus, 0x1C, 0x3F | 0x140);
/* Right Headphone Volume */
write_reg(bus, 0x1D, 0x3F | 0x140);
/* Left Speaker Volume */
write_reg(bus, 0x26, 0x3F | 0x140);
/* Right Speaker Volume */
write_reg(bus, 0x27, 0x3F | 0x140);
}
else if (volume == 0)
{
/* Mute audio codec */
_set_mute(bus, AUDIO_MUTE_ON);
}
else
{
/* Unmute audio codec */
_set_mute(bus, AUDIO_MUTE_OFF);
/* Left Headphone Volume */
write_reg(bus, 0x1C, convertedvol | 0x140);
/* Right Headphone Volume */
write_reg(bus, 0x1D, convertedvol | 0x140);
/* Left Speaker Volume */
write_reg(bus, 0x26, convertedvol | 0x140);
/* Right Speaker Volume */
write_reg(bus, 0x27, convertedvol | 0x140);
}
}
/* Input volume */
else
{
convertedvol = VOLUME_IN_CONVERT(volume);
/* Left AIF1 ADC1 volume */
write_reg(bus, 0x400, convertedvol | 0x100);
/* Right AIF1 ADC1 volume */
write_reg(bus, 0x401, convertedvol | 0x100);
/* Left AIF1 ADC2 volume */
write_reg(bus, 0x404, convertedvol | 0x100);
/* Right AIF1 ADC2 volume */
write_reg(bus, 0x405, convertedvol | 0x100);
}
return RT_EOK;
}
static rt_err_t _get_volume(struct rt_i2c_bus_device *bus, rt_uint32_t *value)
{
rt_uint8_t read_value[2];
read_reg(bus, 0x001C, 2, read_value);
*value = ((uint16_t)(read_value[0] << 8) & 0xFF00);
*value |= ((uint16_t)(read_value[1])& 0x00FF);
return RT_EOK;
}
static rt_err_t _set_frequency(struct rt_i2c_bus_device *bus, rt_uint32_t freq)
{
switch (freq)
{
case AUDIO_FREQUENCY_8K:
write_reg(bus, 0x210, 0x0003);
break;
case AUDIO_FREQUENCY_16K:
write_reg(bus, 0x210, 0x0033);
break;
case AUDIO_FREQUENCY_32K:
write_reg(bus, 0x210, 0x0063);
break;
case AUDIO_FREQUENCY_48K:
write_reg(bus, 0x210, 0x0083);
break;
case AUDIO_FREQUENCY_96K:
write_reg(bus, 0x210, 0x00A3);
break;
case AUDIO_FREQUENCY_11K:
write_reg(bus, 0x210, 0x0013);
break;
case AUDIO_FREQUENCY_22K:
write_reg(bus, 0x210, 0x0043);
break;
case AUDIO_FREQUENCY_44K:
write_reg(bus, 0x210, 0x0073);
break;
default:
write_reg(bus, 0x210, 0x0083);
break;
}
return RT_EOK;
}
static rt_err_t _reset(struct rt_i2c_bus_device *bus)
{
/* Reset Codec by writing in 0x0000 address register */
write_reg(bus, 0x0000, 0x0000);
return RT_EOK;
}
static rt_err_t rt_wm8994_init(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
rt_err_t result = RT_EOK;
static rt_uint16_t old_type = DEVICE_NONE;
struct wm8994_dev *device = (struct wm8994_dev *)dev;
if (old_type == device->type)
{
return RT_EOK;
}
old_type = device->type;
device->i2c_bus = rt_i2c_bus_device_find(I2C_NAME);
if (device->i2c_bus == RT_NULL)
{
LOG_E("can't find %c deivce", I2C_NAME);
return RT_ERROR;
}
result = _wm8994_init(device);
/* set volume */
_set_volume(device->i2c_bus, device->type, VOLUME_CONVERT(100));
/* set frequency */
_set_frequency(device->i2c_bus, AUDIO_FREQUENCY_44K);
return result;
}
static rt_err_t rt_wm8994_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_wm8994_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
struct wm8994_dev *device = (struct wm8994_dev *)dev;
_set_mute(device->i2c_bus, AUDIO_MUTE_ON);
/* Mute the AIF1 Timeslot 0 DAC1 path */
write_reg(device->i2c_bus, 0x420, 0x0200);
/* Mute the AIF1 Timeslot 1 DAC2 path */
write_reg(device->i2c_bus, 0x422, 0x0200);
/* Disable DAC1L_TO_HPOUT1L */
write_reg(device->i2c_bus, 0x2D, 0x0000);
/* Disable DAC1R_TO_HPOUT1R */
write_reg(device->i2c_bus, 0x2E, 0x0000);
/* Disable DAC1 and DAC2 */
write_reg(device->i2c_bus, 0x05, 0x0000);
/* Reset Codec by writing in 0x0000 address register */
write_reg(device->i2c_bus, 0x0000, 0x0000);
return RT_EOK;
}
static rt_size_t rt_wm8994_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_wm8994_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_wm8994_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
struct wm8994_dev *device = (struct wm8994_dev *)dev;
rt_err_t result = RT_EOK;
switch (cmd)
{
case GET_ID:
result = _read_id(device->i2c_bus, (rt_uint16_t*)args);
break;
case SET_FREQUENCE:
result = _set_frequency(device->i2c_bus, (*(rt_uint32_t *)args));
break;
case SET_VOLUME:
result = _set_volume(device->i2c_bus, device->type, (*(rt_uint8_t*)args));
break;
case GET_VOLUME:
result = _get_volume(device->i2c_bus, (rt_uint32_t *)args);
break;
case SET_MUTE:
result = _set_mute(device->i2c_bus, (*(rt_uint32_t*)args));
break;
case SET_RESET:
result = _reset(device->i2c_bus);
break;
case START_PLAY:
result = _play(device->i2c_bus);
break;
case SET_PLAY_TYPE:
device->type = 0;
device->type = *(rt_uint32_t *)args;
rt_wm8994_init(dev);
break;
default:
LOG_D("not support cmd");
break;
}
return result;
}
int wm8994_init(void)
{
rt_wm8994.dev.type = RT_Device_Class_Sound;
rt_wm8994.dev.init = rt_wm8994_init;
rt_wm8994.dev.open = rt_wm8994_open;
rt_wm8994.dev.close = rt_wm8994_close;
rt_wm8994.dev.read = rt_wm8994_read;
rt_wm8994.dev.write = rt_wm8994_write;
rt_wm8994.dev.control = rt_wm8994_control;
rt_wm8994.dev.user_data = RT_NULL;
rt_device_register(&rt_wm8994.dev, "decoder", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
LOG_I("lowlevel decoder device init success!");
return RT_EOK;
}
INIT_DEVICE_EXPORT(wm8994_init);
#endif

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bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-02 thread-liu first version
*/
#ifndef __DRV_WM8994_H__
#define __DRV_WM8994_H__
#include "board.h"
#ifdef __cplusplus
extern "C" {
#endif
enum{
GET_ID,
SET_FREQUENCE,
SET_VOLUME,
GET_VOLUME,
SET_MUTE,
SET_RESET,
START_PLAY,
SET_PLAY_TYPE,
};
/* codec device play type */
#define DEVICE_NONE ((uint16_t)0x0000)
#define OUTPUT_DEVICE_SPEAKER ((uint16_t)0x0001)
#define OUTPUT_DEVICE_HEADPHONE ((uint16_t)0x0002)
#define OUTPUT_DEVICE_BOTH ((uint16_t)0x0004)
#define OUTPUT_DEVICE_AUTO ((uint16_t)0x0008)
#define INPUT_DEVICE_DIGITAL_MICROPHONE_1 ((uint16_t)0x0010)
#define INPUT_DEVICE_DIGITAL_MICROPHONE_2 ((uint16_t)0x0020)
#define INPUT_DEVICE_INPUT_LINE_1 ((uint16_t)0x0040)
#define INPUT_DEVICE_INPUT_LINE_2 ((uint16_t)0x0080)
#define INPUT_DEVICE_DIGITAL_MIC1_MIC2 ((uint16_t)0x0100)
/* volume levels values */
#define DEFAULT_VOLMIN 0x00
#define DEFAULT_VOLMAX 0xFF
#define DEFAULT_VOLSTEP 0x04
#define AUDIO_PAUSE 0
#define AUDIO_RESUME 1
/* Codec POWER DOWN modes */
#define CODEC_PDWN_HW 1
#define CODEC_PDWN_SW 2
/* MUTE commands */
#define AUDIO_MUTE_ON 1
#define AUDIO_MUTE_OFF 0
/* AUDIO FREQUENCY */
#define AUDIO_FREQUENCY_192K ((uint32_t)192000)
#define AUDIO_FREQUENCY_96K ((uint32_t)96000)
#define AUDIO_FREQUENCY_48K ((uint32_t)48000)
#define AUDIO_FREQUENCY_44K ((uint32_t)44100)
#define AUDIO_FREQUENCY_32K ((uint32_t)32000)
#define AUDIO_FREQUENCY_22K ((uint32_t)22050)
#define AUDIO_FREQUENCY_16K ((uint32_t)16000)
#define AUDIO_FREQUENCY_11K ((uint32_t)11025)
#define AUDIO_FREQUENCY_8K ((uint32_t)8000)
#define VOLUME_CONVERT(Volume) (((Volume) > 100)? 100:((uint8_t)(((Volume) * 63) / 100)))
#define VOLUME_IN_CONVERT(Volume) (((Volume) >= 100)? 239:((uint8_t)(((Volume) * 240) / 100)))
#define WM8994_ID 0x8994
#define WM8994_CHIPID_ADDR 0x00
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-20 thread-liu the first version
*/
#include "board.h"
#include "drv_config.h"
#include <netif/ethernetif.h>
#include "lwipopts.h"
#include "drv_eth.h"
#if defined(BSP_USING_GBE)
//#define DRV_DEBUG
//#define ETH_RX_DUMP
//#define ETH_TX_DUMP
#define LOG_TAG "drv.emac"
#include <drv_log.h>
#define MAX_ADDR_LEN 6
rt_base_t level;
#define TX_ADD_BASE 0x2FFC3000
#define RX_ADD_BASE 0x2FFC5000
#define TX_DMA_ADD_BASE 0x2FFC7000
#define RX_DMA_ADD_BASE 0x2FFC7100
#if defined(__ICCARM__)
/* transmit buffer */
#pragma location = TX_ADD_BASE
static uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE];
/* Receive buffer */
#pragma location = RX_ADD_BASE
static uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE];
/* Transmit DMA descriptors */
#pragma location = TX_DMA_ADD_BASE
static TxDmaDesc txDmaDesc[ETH_TXBUFNB];
/* Receive DMA descriptors */
#pragma location = RX_DMA_ADD_BASE
static RxDmaDesc rxDmaDesc[ETH_RXBUFNB];
#elif defined(__CC_ARM) || defined(__CLANG_ARM)
/* transmit buffer */
static uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((at(TX_ADD_BASE)));
/* Receive buffer */
static uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((at(RX_ADD_BASE)));
/* Transmit DMA descriptors */
static TxDmaDesc txDmaDesc[ETH_TXBUFNB] __attribute__((at(TX_DMA_ADD_BASE)));
/* Receive DMA descriptors */
static RxDmaDesc rxDmaDesc[ETH_RXBUFNB] __attribute__((at(RX_DMA_ADD_BASE)));
#elif defined ( __GNUC__ )
/* transmit buffer */
static uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((at(TX_ADD_BASE)));
/* Receive buffer */
static uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((at(RX_ADD_BASE)));
/* Transmit DMA descriptors */
static TxDmaDesc txDmaDesc[ETH_TXBUFNB] __attribute__((at(TX_DMA_ADD_BASE)));
/* Receive DMA descriptors */
static RxDmaDesc rxDmaDesc[ETH_RXBUFNB] __attribute__((at(RX_DMA_ADD_BASE)));
#endif
//Current transmit descriptor
static rt_uint8_t txIndex = 0;
//Current receive descriptor
static rt_uint8_t rxIndex = 0;
/* eth */
static struct rt_event rx_event = {0};
#define ETH_TIME_OUT 100000
struct rt_stm32_eth
{
/* inherit from ethernet device */
struct eth_device parent;
#ifndef PHY_USING_INTERRUPT_MODE
rt_timer_t poll_link_timer;
#endif
/* interface address info, hw address */
rt_uint8_t dev_addr[MAX_ADDR_LEN];
/* eth speed */
uint32_t eth_speed;
/* eth duplex mode */
uint32_t eth_mode;
};
static struct rt_stm32_eth stm32_eth_device = {0};
#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
{
unsigned char *buf = (unsigned char *)ptr;
int i, j;
for (i = 0; i < buflen; i += 16)
{
rt_kprintf("%08X: ", i);
for (j = 0; j < 16; j++)
if (i + j < buflen)
rt_kprintf("%02X ", buf[i + j]);
else
rt_kprintf(" ");
rt_kprintf(" ");
for (j = 0; j < 16; j++)
if (i + j < buflen)
rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
rt_kprintf("\n");
}
}
#endif
static rt_err_t phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_value)
{
uint32_t temp;
volatile uint32_t tickstart = 0;
/* Take care not to alter MDC clock configuration */
temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
/* Set up a write operation */
temp |= ETH_MACMDIOAR_GOC_Val(1) | ETH_MACMDIOAR_GB;
/* PHY address */
temp |= (phy_addr << 21) & ETH_MACMDIOAR_PA;
/* Register address */
temp |= (reg_addr << 16) & ETH_MACMDIOAR_RDA;
/* Data to be written in the PHY register */
ETH->MACMDIODR = reg_value & ETH_MACMDIODR_GD;
/* Start a write operation */
ETH->MACMDIOAR = temp;
/* Wait for the write to complete */
tickstart = rt_tick_get();
while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0)
{
/* judge timeout */
if((rt_tick_get() - tickstart) > ETH_TIME_OUT)
{
LOG_E("PHY write reg %02x date %04x timeout!", reg_addr, reg_value);
return RT_ETIMEOUT;
}
}
return RT_EOK;
}
static uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr)
{
uint16_t reg_value = 0;
uint32_t status = 0;
volatile uint32_t tickstart = 0;
/* Take care not to alter MDC clock configuration */
status = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
/* Set up a read operation */
status |= ETH_MACMDIOAR_GOC_Val(3) | ETH_MACMDIOAR_GB;
/* PHY address */
status |= (phy_addr << 21) & ETH_MACMDIOAR_PA;
/* Register address */
status |= (reg_addr << 16) & ETH_MACMDIOAR_RDA;
/* Start a read operation */
ETH->MACMDIOAR = status;
/* Wait for the read to complete */
tickstart = rt_tick_get();
while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0)
{
/* judge timeout */
if((rt_tick_get() - tickstart) > ETH_TIME_OUT)
{
LOG_E("PHY read reg %02x timeout!", reg_addr);
return RT_ETIMEOUT;
}
}
/* Get register value */
reg_value = ETH->MACMDIODR & ETH_MACMDIODR_GD;
return reg_value;
}
static rt_err_t update_mac_mode(void)
{
uint32_t status;
/* Read current MAC configuration */
status = ETH->MACCR;
if (stm32_eth_device.eth_speed & PHY_1000M)
{
status &= ~ETH_MACCR_PS;
status &= ~ETH_MACCR_FES;
}
else if (stm32_eth_device.eth_speed & PHY_100M)
{
status |= ETH_MACCR_PS;
status |= ETH_MACCR_FES;
}
/* 10M */
else
{
status |= ETH_MACCR_PS;
status &= ~ETH_MACCR_FES;
}
if (stm32_eth_device.eth_mode & PHY_FULL_DUPLEX)
{
status |= ETH_MACCR_DM;
}
else
{
status &= ~ETH_MACCR_DM;
}
/* Update MAC configuration register */
ETH->MACCR = status;
return RT_EOK;
}
static void HAL_ETH_MspInit(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH;
PeriphClkInit.EthClockSelection = RCC_ETHCLKSOURCE_PLL4;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Enable GPIO clocks */
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
/* Select RGMII interface mode */
HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RGMII);
/* Enable Ethernet MAC clock */
__HAL_RCC_ETH1MAC_CLK_ENABLE();
__HAL_RCC_ETH1TX_CLK_ENABLE();
__HAL_RCC_ETH1RX_CLK_ENABLE();
/**ETH1 GPIO Configuration
PA1 ------> ETH1_RX_CLK
PA2 ------> ETH1_MDIO
PA7 ------> ETH1_RX_CTL
PB0 ------> ETH1_RXD2
PB1 ------> ETH1_RXD3
PB11 ------> ETH1_TX_CTL
PC1 ------> ETH1_MDC
PC2 ------> ETH1_TXD2
PC4 ------> ETH1_RXD0
PC5 ------> ETH1_RXD1
PE2 ------> ETH1_TXD3
PG4 ------> ETH1_GTX_CLK
PG5 ------> ETH1_CLK125
PG13 ------> ETH1_TXD0
PG14 ------> ETH1_TXD1
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_11;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_14;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
/* ETH interrupt Init */
HAL_NVIC_SetPriority(ETH1_IRQn, 0x01, 0x00);
HAL_NVIC_EnableIRQ(ETH1_IRQn);
/* Configure PHY_RST (PD10) */
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* Reset PHY transceiver */
HAL_GPIO_WritePin(GPIOD, GPIO_PIN_10, GPIO_PIN_RESET);
rt_thread_mdelay(20);
HAL_GPIO_WritePin(GPIOD, GPIO_PIN_10, GPIO_PIN_SET);
rt_thread_mdelay(20);
}
static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
rt_uint32_t status;
int i = 0 ;
volatile uint32_t tickstart = 0;
uint8_t *macAddr = &stm32_eth_device.dev_addr[0];
/* Initialize RX/TX descriptor index */
rxIndex = txIndex = 0;
HAL_ETH_MspInit();
/* Reset Ethernet MAC peripheral */
__HAL_RCC_ETH1MAC_FORCE_RESET();
__HAL_RCC_ETH1MAC_RELEASE_RESET();
/* Ethernet Software reset */
ETH->DMAMR |= ETH_DMAMR_SWR;
/* Wait for the reset to complete */
tickstart = rt_tick_get();
while (READ_BIT(ETH->DMAMR, ETH_DMAMR_SWR))
{
if(((HAL_GetTick() - tickstart ) > ETH_TIME_OUT))
{
LOG_E("ETH software reset timeout!");
return RT_ERROR;
}
}
/* Adjust MDC clock range depending on HCLK frequency */
ETH->MACMDIOAR = ETH_MACMDIOAR_CR_Val(5);
/* Use default MAC configuration */
ETH->MACCR = ETH_MACCR_DO;
/* Set the MAC address of the station */
ETH->MACA0LR = ((macAddr[3] << 24) | (macAddr[2] << 16) | (macAddr[1] << 8) | macAddr[0]);
ETH->MACA0HR = ((macAddr[5] << 8) | macAddr[4]);
/* The MAC supports 3 additional addresses for unicast perfect filtering */
ETH->MACA1LR = 0;
ETH->MACA1HR = 0;
ETH->MACA2LR = 0;
ETH->MACA2HR = 0;
ETH->MACA3LR = 0;
ETH->MACA3HR = 0;
/* Initialize hash table */
ETH->MACHT0R = 0;
ETH->MACHT1R = 0;
/* Configure the receive filter */
ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC;
/* Disable flow control */
ETH->MACQ0TXFCR = 0;
ETH->MACRXFCR = 0;
/* Enable the first RX queue */
ETH->MACRXQC0R = ETH_MACRXQC0R_RXQ0EN_Val(1);
/* Configure DMA operating mode */
ETH->DMAMR = ETH_DMAMR_INTM_Val(0) | ETH_DMAMR_PR_Val(0);
/* Configure system bus mode */
ETH->DMASBMR |= ETH_DMASBMR_AAL;
/* The DMA takes the descriptor table as contiguous */
ETH->DMAC0CR = ETH_DMAC0CR_DSL_Val(0);
/* Configure TX features */
ETH->DMAC0TXCR = ETH_DMAC0TXCR_TXPBL_Val(1);
/* Configure RX features */
ETH->DMAC0RXCR = ETH_DMAC0RXCR_RXPBL_Val(1) | ETH_DMAC0RXCR_RBSZ_Val(ETH_RX_BUF_SIZE);
/* Enable store and forward mode for transmission */
ETH->MTLTXQ0OMR = ETH_MTLTXQ0OMR_TQS_Val(7) | ETH_MTLTXQ0OMR_TXQEN_Val(2) | ETH_MTLTXQ0OMR_TSF;
/* Enable store and forward mode for reception */
ETH->MTLRXQ0OMR = ETH_MTLRXQ0OMR_RQS_Val(7) | ETH_MTLRXQ0OMR_RSF;
/* Initialize TX DMA descriptor list */
for (i = 0; i < ETH_TXBUFNB; i++)
{
/* The descriptor is initially owned by the application */
txDmaDesc[i].tdes0 = 0;
txDmaDesc[i].tdes1 = 0;
txDmaDesc[i].tdes2 = 0;
txDmaDesc[i].tdes3 = 0;
}
/* Initialize RX DMA descriptor list */
for (i = 0; i < ETH_RXBUFNB; i++)
{
/* The descriptor is initially owned by the DMA */
rxDmaDesc[i].rdes0 = (uint32_t)rxBuffer[i];
rxDmaDesc[i].rdes1 = 0;
rxDmaDesc[i].rdes2 = 0;
rxDmaDesc[i].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V;
}
/* Set Transmit Descriptor List Address Register */
ETH->DMAC0TXDLAR = (uint32_t)&txDmaDesc[0];
/* Length of the transmit descriptor ring */
ETH->DMAC0TXRLR = ETH_TXBUFNB - 1;
/* Set Receive Descriptor List Address Register */
ETH->DMAC0RXDLAR = (uint32_t)&rxDmaDesc[0];
/* Length of the receive descriptor ring */
ETH->DMAC0RXRLR = ETH_RXBUFNB - 1;
/* Prevent interrupts from being generated when the transmit statistic
* counters reach half their maximum value */
ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM | ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM;
/* Prevent interrupts from being generated when the receive statistic
* counters reach half their maximum value */
ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM | ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM;
/* Disable MAC interrupts */
ETH->MACIER = 0;
/* Enable the desired DMA interrupts */
ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
/* Enable MAC transmission and reception */
ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
/* Enable DMA transmission and reception */
ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST;
ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR;
/* Reset PHY transceiver */
phy_write_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR, RTL8211E_BMCR_RESET);
status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR);
/* Wait for the reset to complete */
tickstart = rt_tick_get();
while (status & RTL8211E_BMCR_RESET)
{
if((rt_tick_get() - tickstart) > ETH_TIME_OUT)
{
LOG_E("PHY software reset timeout!");
return RT_ETIMEOUT;
}
else
{
status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR);
}
}
/* The PHY will generate interrupts when link status changes are detected */
phy_write_reg(RTL8211E_PHY_ADDR, RTL8211E_INER, RTL8211E_INER_AN_COMPLETE | RTL8211E_INER_LINK_STATUS);
return RT_EOK;
}
static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
LOG_D("emac open");
return RT_EOK;
}
static rt_err_t rt_stm32_eth_close(rt_device_t dev)
{
LOG_D("emac close");
return RT_EOK;
}
static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
LOG_D("emac read");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
LOG_D("emac write");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args)
{
rt_memcpy(args, stm32_eth_device.dev_addr, 6);
}
else
{
return -RT_ERROR;
}
break;
default :
break;
}
return RT_EOK;
}
rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
{
uint32_t framelen = 0;
struct pbuf *q = RT_NULL;
/* Copy user data to the transmit buffer */
for (q = p; q != NULL; q = q->next)
{
/* Make sure the current buffer is available for writing */
if((txDmaDesc[txIndex].tdes3 & ETH_TDES3_OWN) != 0)
{
LOG_D("buffer not valid");
return ERR_USE;
}
level = rt_hw_interrupt_disable();
rt_memcpy(&txBuffer[txIndex][framelen], q->payload, q->len);
framelen += q->len;
rt_hw_interrupt_enable(level);
/* Check the frame length */
if (framelen > ETH_TX_BUF_SIZE - 1)
{
LOG_D(" tx buffer frame length over : %d", framelen);
return ERR_USE;
}
}
#ifdef ETH_TX_DUMP
rt_kprintf("Tx dump, len= %d\r\n", framelen);
dump_hex(txBuffer[txIndex], framelen);
#endif
/* Set the start address of the buffer */
txDmaDesc[txIndex].tdes0 = (uint32_t)txBuffer[txIndex];
/* Write the number of bytes to send */
txDmaDesc[txIndex].tdes2 = ETH_TDES2_IOC | (framelen & ETH_TDES2_B1L);
/* Give the ownership of the descriptor to the DMA */
txDmaDesc[txIndex].tdes3 = ETH_TDES3_OWN | ETH_TDES3_FD | ETH_TDES3_LD;
/* Data synchronization barrier */
__DSB();
/* Clear TBU flag to resume processing */
ETH->DMAC0SR = ETH_DMAC0SR_TBU;
/* Instruct the DMA to poll the transmit descriptor list */
ETH->DMAC0TXDTPR = 0;
if (++txIndex > ETH_TXBUFNB - 1)
{
txIndex = 0;
}
return ERR_OK;
}
struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
{
rt_uint32_t framelength = 0;
uint32_t framelen = 0;
struct pbuf *p = RT_NULL, *q = RT_NULL;
/* The current buffer is available for reading */
if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN))
{
/* FD and LD flags should be set */
if ((rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_FD) && (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_LD))
{
/* Make sure no error occurred */
if(!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_ES))
{
/* Retrieve the length of the frame */
framelength = rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL;
/* check the frame length */
framelength = (framelength > ETH_RX_BUF_SIZE) ? ETH_RX_BUF_SIZE : framelength;
p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM);
if (p != NULL)
{
for (q = p; q != NULL; q = q->next)
{
level=rt_hw_interrupt_disable();
rt_memcpy(q->payload, &rxBuffer[rxIndex][framelen], q->len);
framelen += q->len;
rt_hw_interrupt_enable(level);
if (framelen > framelength)
{
LOG_E("frame len is too long!");
return RT_NULL;
}
}
}
}
else
{
/* The received packet contains an error */
LOG_D("the received packet contains an error!");
return RT_NULL;
}
}
else
{
/* The packet is not valid */
LOG_D("the packet is not valid");
return RT_NULL;
}
/* Set the start address of the buffer */
rxDmaDesc[rxIndex].rdes0 = (uint32_t)rxBuffer[rxIndex];
/* Give the ownership of the descriptor back to the DMA */
rxDmaDesc[rxIndex].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V;
#ifdef ETH_RX_DUMP
rt_kprintf("Rx dump, len= %d\r\n", framelen);
dump_hex(rxBuffer[rxIndex], framelen);
#endif
/* Increment index and wrap around if necessary */
if (++rxIndex > ETH_RXBUFNB - 1)
{
rxIndex = 0;
}
/* Clear RBU flag to resume processing */
ETH->DMAC0SR = ETH_DMAC0SR_RBU;
/* Instruct the DMA to poll the receive descriptor list */
ETH->DMAC0RXDTPR = 0;
}
return p;
}
void ETH1_IRQHandler(void)
{
rt_uint32_t status = 0;
/* enter interrupt */
rt_interrupt_enter();
/* Read DMA status register */
status = ETH->DMAC0SR;
/* Frame transmitted */
if (status & ETH_DMAC0SR_TI)
{
/* Clear the Eth DMA Tx IT pending bits */
ETH->DMAC0SR = ETH_DMAC0SR_TI;
}
/* Frame received */
else if (status & ETH_DMAC0SR_RI)
{
/* Disable RIE interrupt */
ETH->DMAC0IER &= ~ETH_DMAC0IER_RIE;
rt_event_send(&rx_event, status);
}
/* ETH DMA Error */
if (status & ETH_DMAC0SR_AIS)
{
ETH->DMAC0IER &= ~ETH_DMAC0IER_AIE;
LOG_E("eth dam err");
}
/* Clear the interrupt flags */
ETH->DMAC0SR = ETH_DMAC0SR_NIS;
/* leave interrupt */
rt_interrupt_leave();
}
static void phy_linkchange()
{
rt_uint32_t status = 0;
/* Read status register to acknowledge the interrupt */
status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_INSR);
if (status & (RTL8211E_INSR_AN_COMPLETE | RTL8211E_INSR_LINK_STATUS))
{
status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMSR);
status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMSR);
if (status & RTL8211E_BMSR_LINK_STATUS)
{
LOG_D("link up");
status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_PHYSR);
switch (status & RTL8211E_PHYSR_SPEED)
{
case RTL8211E_PHYSR_SPEED_10MBPS:
{
LOG_D("speed: 10M");
stm32_eth_device.eth_speed |= PHY_10M;
break;
}
case RTL8211E_PHYSR_SPEED_100MBPS:
{
LOG_D("speed: 100M");
stm32_eth_device.eth_speed |= PHY_100M;
break;
}
case RTL8211E_PHYSR_SPEED_1000MBPS:
{
LOG_D("speed: 1000M");
stm32_eth_device.eth_speed |= PHY_1000M;
break;
}
/* Unknown speed */
default:
rt_kprintf("Invalid speed.");
break;
}
stm32_eth_device.eth_mode = (status & RTL8211E_PHYSR_DUPLEX)? PHY_FULL_DUPLEX : PHY_HALF_DUPLEX;
update_mac_mode();
/* send link up. */
eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
}
else
{
LOG_D("link down");
eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
}
}
}
#ifdef PHY_USING_INTERRUPT_MODE
static void eth_phy_isr(void *args)
{
rt_uint32_t status = 0;
phy_read_reg(RTL8211E_PHY_ADDR, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
LOG_D("phy interrupt status reg is 0x%X", status);
phy_linkchange();
}
#endif /* PHY_USING_INTERRUPT_MODE */
static void phy_monitor_thread_entry(void *parameter)
{
rt_uint32_t status = 0;
phy_linkchange();
#ifdef PHY_USING_INTERRUPT_MODE
/* configuration intterrupt pin */
rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
/* enable phy interrupt */
phy_write_reg(RTL8211E_PHY_ADDR, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK);
#if defined(PHY_INTERRUPT_CTRL_REG)
phy_write_reg( RTL8211E_PHY_ADDR, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN);
#endif
#else /* PHY_USING_INTERRUPT_MODE */
stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK)
{
LOG_E("Start link change detection timer failed");
}
#endif /* PHY_USING_INTERRUPT_MODE */
while(1)
{
if (rt_event_recv(&rx_event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
RT_WAITING_FOREVER, &status) == RT_EOK)
{
/* check dma rx buffer */
if (ETH->DMAC0SR & ETH_DMAC0SR_RI)
{
/* Clear interrupt flag */
ETH->DMAC0SR = ETH_DMAC0SR_RI;
/* Process all pending packets */
while (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL)
{
/* trigger lwip receive thread */
eth_device_ready(&(stm32_eth_device.parent));
}
}
/* enable DMA interrupts */
ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
}
}
}
/* Register the EMAC device */
static int rt_hw_stm32_eth_init(void)
{
rt_err_t state = RT_EOK;
/* OUI 00-80-E1 STMICROELECTRONICS. */
stm32_eth_device.dev_addr[0] = 0x00;
stm32_eth_device.dev_addr[1] = 0x80;
stm32_eth_device.dev_addr[2] = 0xE1;
/* generate MAC addr from 96bit unique ID. */
stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4);
stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2);
stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0);
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
stm32_eth_device.parent.parent.user_data = RT_NULL;
stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
rt_event_init(&rx_event, "eth_rx", RT_IPC_FLAG_FIFO);
/* register eth device */
state = eth_device_init(&(stm32_eth_device.parent), "e0");
if (RT_EOK == state)
{
LOG_D("emac device init success");
}
else
{
LOG_E("emac device init faild: %d", state);
state = -RT_ERROR;
}
/* start phy monitor */
rt_thread_t tid;
tid = rt_thread_create("phy",
phy_monitor_thread_entry,
RT_NULL,
1024,
RT_THREAD_PRIORITY_MAX - 2,
2);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
state = -RT_ERROR;
}
return state;
}
INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);
#endif

381
bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-20 thread-liu the first version
*/
#ifndef __DRV_ETH_H__
#define __DRV_ETH_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Transmit descriptor
**/
typedef struct
{
uint32_t tdes0;
uint32_t tdes1;
uint32_t tdes2;
uint32_t tdes3;
} TxDmaDesc;
/**
* @brief Receive descriptor
**/
typedef struct
{
uint32_t rdes0;
uint32_t rdes1;
uint32_t rdes2;
uint32_t rdes3;
} RxDmaDesc;
enum {
PHY_LINK = (1 << 0),
PHY_10M = (1 << 1),
PHY_100M = (1 << 2),
PHY_1000M = (1 << 3),
PHY_FULL_DUPLEX = (1 << 4),
PHY_HALF_DUPLEX = (1 << 5)
};
#define RTL8211E_PHY_ADDR 7 /* PHY address */
#define ETH_TXBUFNB 4 /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
#define ETH_TX_BUF_SIZE 1536 /* buffer size for transmit */
#define ETH_RXBUFNB 4 /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_RX_BUF_SIZE 1536 /* buffer size for receive */
#define ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk /* ETH_MMCTXIMR register */
/* Register access macros */
#define ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk)
#define ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk)
#define ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk)
#define ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk)
#define ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk)
#define ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk)
#define ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk)
#define ETH_DMAMR_PR_Val(n) (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk)
#define ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk)
#define ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk)
#define ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk)
#define ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk)
/* Transmit normal descriptor (read format) */
#define ETH_TDES0_BUF1AP 0xFFFFFFFF
#define ETH_TDES1_BUF2AP 0xFFFFFFFF
#define ETH_TDES2_IOC 0x80000000
#define ETH_TDES2_TTSE 0x40000000
#define ETH_TDES2_B2L 0x3FFF0000
#define ETH_TDES2_VTIR 0x0000C000
#define ETH_TDES2_B1L 0x00003FFF
#define ETH_TDES3_OWN 0x80000000
#define ETH_TDES3_CTXT 0x40000000
#define ETH_TDES3_FD 0x20000000
#define ETH_TDES3_LD 0x10000000
#define ETH_TDES3_CPC 0x0C000000
#define ETH_TDES3_SAIC 0x03800000
#define ETH_TDES3_THL 0x00780000
#define ETH_TDES3_TSE 0x00040000
#define ETH_TDES3_CIC 0x00030000
#define ETH_TDES3_FL 0x00007FFF
/* Transmit normal descriptor (write-back format) */
#define ETH_TDES0_TTSL 0xFFFFFFFF
#define ETH_TDES1_TTSH 0xFFFFFFFF
#define ETH_TDES3_OWN 0x80000000
#define ETH_TDES3_CTXT 0x40000000
#define ETH_TDES3_FD 0x20000000
#define ETH_TDES3_LD 0x10000000
#define ETH_TDES3_TTSS 0x00020000
#define ETH_TDES3_ES 0x00008000
#define ETH_TDES3_JT 0x00004000
#define ETH_TDES3_FF 0x00002000
#define ETH_TDES3_PCE 0x00001000
#define ETH_TDES3_LOC 0x00000800
#define ETH_TDES3_NC 0x00000400
#define ETH_TDES3_LC 0x00000200
#define ETH_TDES3_EC 0x00000100
#define ETH_TDES3_CC 0x000000F0
#define ETH_TDES3_ED 0x00000008
#define ETH_TDES3_UF 0x00000004
#define ETH_TDES3_DB 0x00000002
#define ETH_TDES3_IHE 0x00000001
/* Transmit context descriptor */
#define ETH_TDES0_TTSL 0xFFFFFFFF
#define ETH_TDES1_TTSH 0xFFFFFFFF
#define ETH_TDES2_IVT 0xFFFF0000
#define ETH_TDES2_MSS 0x00003FFF
#define ETH_TDES3_OWN 0x80000000
#define ETH_TDES3_CTXT 0x40000000
#define ETH_TDES3_OSTC 0x08000000
#define ETH_TDES3_TCMSSV 0x04000000
#define ETH_TDES3_CDE 0x00800000
#define ETH_TDES3_IVLTV 0x00020000
#define ETH_TDES3_VLTV 0x00010000
#define ETH_TDES3_VT 0x0000FFFF
/* Receive normal descriptor (read format) */
#define ETH_RDES0_BUF1AP 0xFFFFFFFF
#define ETH_RDES2_BUF2AP 0xFFFFFFFF
#define ETH_RDES3_OWN 0x80000000
#define ETH_RDES3_IOC 0x40000000
#define ETH_RDES3_BUF2V 0x02000000
#define ETH_RDES3_BUF1V 0x01000000
/* Receive normal descriptor (write-back format) */
#define ETH_RDES0_IVT 0xFFFF0000
#define ETH_RDES0_OVT 0x0000FFFF
#define ETH_RDES1_OPC 0xFFFF0000
#define ETH_RDES1_TD 0x00008000
#define ETH_RDES1_TSA 0x00004000
#define ETH_RDES1_PV 0x00002000
#define ETH_RDES1_PFT 0x00001000
#define ETH_RDES1_PMT 0x00000F00
#define ETH_RDES1_IPCE 0x00000080
#define ETH_RDES1_IPCB 0x00000040
#define ETH_RDES1_IPV6 0x00000020
#define ETH_RDES1_IPV4 0x00000010
#define ETH_RDES1_IPHE 0x00000008
#define ETH_RDES1_PT 0x00000007
#define ETH_RDES2_L3L4FM 0xE0000000
#define ETH_RDES2_L4FM 0x10000000
#define ETH_RDES2_L3FM 0x08000000
#define ETH_RDES2_MADRM 0x07F80000
#define ETH_RDES2_HF 0x00040000
#define ETH_RDES2_DAF 0x00020000
#define ETH_RDES2_SAF 0x00010000
#define ETH_RDES2_VF 0x00008000
#define ETH_RDES2_ARPRN 0x00000400
#define ETH_RDES3_OWN 0x80000000
#define ETH_RDES3_CTXT 0x40000000
#define ETH_RDES3_FD 0x20000000
#define ETH_RDES3_LD 0x10000000
#define ETH_RDES3_RS2V 0x08000000
#define ETH_RDES3_RS1V 0x04000000
#define ETH_RDES3_RS0V 0x02000000
#define ETH_RDES3_CE 0x01000000
#define ETH_RDES3_GP 0x00800000
#define ETH_RDES3_RWT 0x00400000
#define ETH_RDES3_OE 0x00200000
#define ETH_RDES3_RE 0x00100000
#define ETH_RDES3_DE 0x00080000
#define ETH_RDES3_LT 0x00070000
#define ETH_RDES3_ES 0x00008000
#define ETH_RDES3_PL 0x00007FFF
/* Receive context descriptor */
#define ETH_RDES0_RTSL 0xFFFFFFFF
#define ETH_RDES1_RTSH 0xFFFFFFFF
#define ETH_RDES3_OWN 0x80000000
#define ETH_RDES3_CTXT 0x40000000
#define RTL8211E_BMCR ((uint16_t)0x0000U) /* Basic Mode Control Register. */
#define RTL8211E_BMSR ((uint16_t)0x0001U) /* Basic Mode Status Register. */
#define RTL8211E_PHYID1 ((uint16_t)0x0002U) /* PHY Identifier Register 1. */
#define RTL8211E_PHYID2 ((uint16_t)0x0003U) /* PHY Identifier Register 2. */
#define RTL8211E_ANAR ((uint16_t)0x0004U) /* Auto-Negotiation Advertising Register. */
#define RTL8211E_ANLPAR ((uint16_t)0x0005U) /* Auto-Negotiation Link Partner Ability Register. */
#define RTL8211E_ANER ((uint16_t)0x0006U) /* Auto-Negotiation Expansion Register.*/
#define RTL8211E_ANNPTR ((uint16_t)0x0007U) /* Auto-Negotiation Next Page Transmit Register.*/
#define RTL8211E_ANNPRR ((uint16_t)0x0008U) /* Auto-Negotiation Next Page Receive Register. */
#define RTL8211E_GBCR ((uint16_t)0x0009U) /* 1000Base-T Control Register. */
#define RTL8211E_GBSR ((uint16_t)0x000AU) /* 1000Base-T Status Register. */
#define RTL8211E_MMDACR ((uint16_t)0x000DU) /* MMD Access Control Register. */
#define RTL8211E_MMDAADR ((uint16_t)0x000EU) /* MMD Access Address Data Register. */
#define RTL8211E_GBESR ((uint16_t)0x000FU) /* 1000Base-T Extended Status Register. */
#define RTL8211E_PHYCR ((uint16_t)0x0010U)
#define RTL8211E_PHYSR ((uint16_t)0x0011U)
#define RTL8211E_INER ((uint16_t)0x0012U) /* Interrupt Enable Register. */
#define RTL8211E_INSR ((uint16_t)0x0013U) /* Interrupt Status Register. */
#define RTL8211E_RXERC ((uint16_t)0x0018U)
#define RTL8211E_LDPSR ((uint16_t)0x001BU)
#define RTL8211E_EPAGSR ((uint16_t)0x001EU)
#define RTL8211E_PAGSR ((uint16_t)0x001FU)
/* Basic Mode Control register */
#define RTL8211E_BMCR_RESET 0x8000
#define RTL8211E_BMCR_LOOPBACK 0x4000
#define RTL8211E_BMCR_SPEED_SEL_LSB 0x2000
#define RTL8211E_BMCR_AN_EN 0x1000
#define RTL8211E_BMCR_POWER_DOWN 0x0800
#define RTL8211E_BMCR_ISOLATE 0x0400
#define RTL8211E_BMCR_RESTART_AN 0x0200
#define RTL8211E_BMCR_DUPLEX_MODE 0x0100
#define RTL8211E_BMCR_COL_TEST 0x0080
#define RTL8211E_BMCR_SPEED_SEL_MSB 0x0040
/* Basic Mode Status register */
#define RTL8211E_BMSR_100BT4 0x8000
#define RTL8211E_BMSR_100BTX_FD 0x4000
#define RTL8211E_BMSR_100BTX_HD 0x2000
#define RTL8211E_BMSR_10BT_FD 0x1000
#define RTL8211E_BMSR_10BT_HD 0x0800
#define RTL8211E_BMSR_100BT2_FD 0x0400
#define RTL8211E_BMSR_100BT2_HD 0x0200
#define RTL8211E_BMSR_EXTENDED_STATUS 0x0100
#define RTL8211E_BMSR_PREAMBLE_SUPPR 0x0040
#define RTL8211E_BMSR_AN_COMPLETE 0x0020
#define RTL8211E_BMSR_REMOTE_FAULT 0x0010
#define RTL8211E_BMSR_AN_CAPABLE 0x0008
#define RTL8211E_BMSR_LINK_STATUS 0x0004
#define RTL8211E_BMSR_JABBER_DETECT 0x0002
#define RTL8211E_BMSR_EXTENDED_CAPABLE 0x0001
/* PHY Identifier 1 register */
#define RTL8211E_PHYID1_OUI_MSB 0xFFFF
#define RTL8211E_PHYID1_OUI_MSB_DEFAULT 0x001C
/* PHY Identifier 2 register */
#define RTL8211E_PHYID2_OUI_LSB 0xFC00
#define RTL8211E_PHYID2_OUI_LSB_DEFAULT 0xC800
#define RTL8211E_PHYID2_MODEL_NUM 0x03F0
#define RTL8211E_PHYID2_MODEL_NUM_DEFAULT 0x0110
#define RTL8211E_PHYID2_REVISION_NUM 0x000F
#define RTL8211E_PHYID2_REVISION_NUM_DEFAULT 0x0005
/* Auto-Negotiation Advertisement register */
#define RTL8211E_ANAR_NEXT_PAGE 0x8000
#define RTL8211E_ANAR_REMOTE_FAULT 0x2000
#define RTL8211E_ANAR_ASYM_PAUSE 0x0800
#define RTL8211E_ANAR_PAUSE 0x0400
#define RTL8211E_ANAR_100BT4 0x0200
#define RTL8211E_ANAR_100BTX_FD 0x0100
#define RTL8211E_ANAR_100BTX_HD 0x0080
#define RTL8211E_ANAR_10BT_FD 0x0040
#define RTL8211E_ANAR_10BT_HD 0x0020
#define RTL8211E_ANAR_SELECTOR 0x001F
#define RTL8211E_ANAR_SELECTOR_DEFAULT 0x0001
/* Auto-Negotiation Link Partner Ability register */
#define RTL8211E_ANLPAR_NEXT_PAGE 0x8000
#define RTL8211E_ANLPAR_ACK 0x4000
#define RTL8211E_ANLPAR_REMOTE_FAULT 0x2000
#define RTL8211E_ANLPAR_ASYM_PAUSE 0x0800
#define RTL8211E_ANLPAR_PAUSE 0x0400
#define RTL8211E_ANLPAR_100BT4 0x0200
#define RTL8211E_ANLPAR_100BTX_FD 0x0100
#define RTL8211E_ANLPAR_100BTX_HD 0x0080
#define RTL8211E_ANLPAR_10BT_FD 0x0040
#define RTL8211E_ANLPAR_10BT_HD 0x0020
#define RTL8211E_ANLPAR_SELECTOR 0x001F
#define RTL8211E_ANLPAR_SELECTOR_DEFAULT 0x0001
/* Auto-Negotiation Expansion register */
#define RTL8211E_ANER_PAR_DETECT_FAULT 0x0010
#define RTL8211E_ANER_LP_NEXT_PAGE_ABLE 0x0008
#define RTL8211E_ANER_NEXT_PAGE_ABLE 0x0004
#define RTL8211E_ANER_PAGE_RECEIVED 0x0002
#define RTL8211E_ANER_LP_AN_ABLE 0x0001
/* Auto-Negotiation Next Page Transmit register */
#define RTL8211E_ANNPTR_NEXT_PAGE 0x8000
#define RTL8211E_ANNPTR_MSG_PAGE 0x2000
#define RTL8211E_ANNPTR_ACK2 0x1000
#define RTL8211E_ANNPTR_TOGGLE 0x0800
#define RTL8211E_ANNPTR_MESSAGE 0x07FF
/* Auto-Negotiation Next Page Receive register */
#define RTL8211E_ANNPRR_NEXT_PAGE 0x8000
#define RTL8211E_ANNPRR_ACK 0x4000
#define RTL8211E_ANNPRR_MSG_PAGE 0x2000
#define RTL8211E_ANNPRR_ACK2 0x1000
#define RTL8211E_ANNPRR_TOGGLE 0x0800
#define RTL8211E_ANNPRR_MESSAGE 0x07FF
/* 1000Base-T Control register */
#define RTL8211E_GBCR_TEST_MODE 0xE000
#define RTL8211E_GBCR_MS_MAN_CONF_EN 0x1000
#define RTL8211E_GBCR_MS_MAN_CONF_VAL 0x0800
#define RTL8211E_GBCR_PORT_TYPE 0x0400
#define RTL8211E_GBCR_1000BT_FD 0x0200
/* 1000Base-T Status register */
#define RTL8211E_GBSR_MS_CONF_FAULT 0x8000
#define RTL8211E_GBSR_MS_CONF_RES 0x4000
#define RTL8211E_GBSR_LOCAL_RECEIVER_STATUS 0x2000
#define RTL8211E_GBSR_REMOTE_RECEIVER_STATUS 0x1000
#define RTL8211E_GBSR_LP_1000BT_FD 0x0800
#define RTL8211E_GBSR_LP_1000BT_HD 0x0400
#define RTL8211E_GBSR_IDLE_ERR_COUNT 0x00FF
/* MMD Access Control register */
#define RTL8211E_MMDACR_FUNC 0xC000
#define RTL8211E_MMDACR_FUNC_ADDR 0x0000
#define RTL8211E_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
#define RTL8211E_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
#define RTL8211E_MMDACR_FUNC_DATA_POST_INC_W 0xC000
#define RTL8211E_MMDACR_DEVAD 0x001F
/* 1000Base-T Extended Status register */
#define RTL8211E_GBESR_1000BX_FD 0x8000
#define RTL8211E_GBESR_1000BX_HD 0x4000
#define RTL8211E_GBESR_1000BT_FD 0x2000
#define RTL8211E_GBESR_1000BT_HD 0x1000
/* PHY Specific Control register */
#define RTL8211E_PHYCR_RXC_DIS 0x8000
#define RTL8211E_PHYCR_FPR_FAIL_SEL 0x7000
#define RTL8211E_PHYCR_ASSERT_CRS_ON_TX 0x0800
#define RTL8211E_PHYCR_FORCE_LINK_GOOD 0x0400
#define RTL8211E_PHYCR_CROSSOVER_EN 0x0040
#define RTL8211E_PHYCR_MDI_MODE 0x0020
#define RTL8211E_PHYCR_CLK125_DIS 0x0010
#define RTL8211E_PHYCR_JABBER_DIS 0x0001
/* PHY Specific Status register */
#define RTL8211E_PHYSR_SPEED 0xC000
#define RTL8211E_PHYSR_SPEED_10MBPS 0x0000
#define RTL8211E_PHYSR_SPEED_100MBPS 0x4000
#define RTL8211E_PHYSR_SPEED_1000MBPS 0x8000
#define RTL8211E_PHYSR_DUPLEX 0x2000
#define RTL8211E_PHYSR_PAGE_RECEIVED 0x1000
#define RTL8211E_PHYSR_SPEED_DUPLEX_RESOLVED 0x0800
#define RTL8211E_PHYSR_LINK 0x0400
#define RTL8211E_PHYSR_MDI_CROSSOVER_STATUS 0x0040
#define RTL8211E_PHYSR_PRE_LINKOK 0x0002
#define RTL8211E_PHYSR_JABBER 0x0001
/* Interrupt Status register */
#define RTL8211E_INER_AN_ERROR 0x8000
#define RTL8211E_INER_PAGE_RECEIVED 0x1000
#define RTL8211E_INER_AN_COMPLETE 0x0800
#define RTL8211E_INER_LINK_STATUS 0x0400
#define RTL8211E_INER_SYMBOL_ERROR 0x0200
#define RTL8211E_INER_FALSE_CARRIER 0x0100
#define RTL8211E_INER_JABBER 0x0001
/* Interrupt Status register */
#define RTL8211E_INSR_AN_ERROR 0x8000
#define RTL8211E_INSR_PAGE_RECEIVED 0x1000
#define RTL8211E_INSR_AN_COMPLETE 0x0800
#define RTL8211E_INSR_LINK_STATUS 0x0400
#define RTL8211E_INSR_SYMBOL_ERROR 0x0200
#define RTL8211E_INSR_FALSE_CARRIER 0x0100
#define RTL8211E_INSR_JABBER 0x0001
/* Link Down Power Saving register */
#define RTL8211E_LDPSR_POWER_SAVE_MODE 0x0001
/* Extension Page Select register */
#define RTL8211E_EPAGSR_EXT_PAGE_SEL 0x00FF
#ifdef __cplusplus
}
#endif
#endif