[BSP][HT32]新增合泰ht32f52352和ht32f12366
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@ -126,6 +126,8 @@ jobs:
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#- {RTT_BSP_NAME: "hk32_hk32f030c8-mini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hk32/hk32f030c8-mini"} #scons dist有问题
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- {RTT_BSP_NAME: "hpmicro_hpm6750evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evk"}
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- {RTT_BSP_NAME: "hpmicro_hpm6750evkmini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evkmini"}
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- {RTT_BSP_NAME: "ht32f12366", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f12366"}
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- {RTT_BSP_NAME: "ht32f52352", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f52352"}
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#- {RTT_BSP_NAME: "imx_imx6ull-smart", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx/imx6ull-smart"} # toolchain还没支持
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- {RTT_BSP_NAME: "imx6sx_cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx6sx/cortex-a9"}
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- {RTT_BSP_NAME: "imx6ul", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx6ul"}
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,22 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "../libraries/Kconfig"
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source "board/Kconfig"
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@ -0,0 +1,107 @@
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# HT32F12366 BSP 说明
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## 简介
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ESK32-30105是合泰基于HT32F12366芯片并针对Cortex®-M3入门而设计的评估板。本文档是为ESK32-30105开发板提供的BSP(板级支持包)说明。
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主要内容如下：
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- 开发板资源介绍
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- BSP 快速上手
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- 进阶使用方法
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通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
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## 开发板介绍
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ESK32-30105使用32位ARM® Cortex®-M3高性能、低功耗单片机HT32F12366，针对Cortex®-M3入门而设计。开发板外观如下图所示：
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该开发板常用 **板载资源** 如下：
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- MCU：HT32F12366，主频 96MHz，256KB FLASH ，128KB SRAM
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- 常用外设
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- LED：2个，（绿色，PE0、PD15）
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- 常用接口：USB 转串口 、USB SLAVE
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- 调试接口：板载的 e-Link32 Lite SWD 下载
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开发板更多详细信息请参考合泰官网的相关文档 [ESK32-30105](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30105)。
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## 外设支持
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本 BSP 目前对外设的支持情况如下：
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| **板载外设** | **支持情况** | **备注** |
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| :--- | :---: | :--- |
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| USB 转串口 | 支持 | 使用 USART0 |
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 支持 | PA0, PA1...PE15 ---> PIN: 0, 1...79 |
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| USART | 支持 | USART0/1 |
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| UART | 支持 | UART0/1 |
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| SPI | 支持 | SPI0/1 |
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| I2C | 支持 | 硬件 I2C0/1 |
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| ADC | 暂不支持 | |
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| WDT | 暂不支持 | |
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## 使用说明
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使用说明分为如下两个章节：
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- 快速上手
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本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
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- 进阶使用
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本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多片上资源，实现更多高级功能。
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### 快速上手
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本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
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#### 硬件连接
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使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。
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#### 编译下载
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双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
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> 注：工程默认配置使用CMSIS-DAP下载方式，在通过 e-Link32 Lite 连接开发板的基础上，点击下载按钮即可下载程序到开发板。
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#### 运行结果
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下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED1和LED2交替闪烁。
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连接开发板对应串口到 PC（也可以通过e-Link32 Lite的模拟串口将开发板连接到PC）, 在终端工具里调整好串口配置（115200-8-1-N）并打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
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> 注：由于RT-Thread的finsh控制台使用的是命令行的输入形式，推荐使用串口调试工具如：Tabby terminal 或者 Tera Term。
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```bash
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\ | /
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- RT - Thread Operating System
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/ | \ 5.1.0 build Apr 10 2024 14:39:43
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2006 - 2024 Copyright by RT-Thread team
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msh >
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```
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### 进阶使用
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此 BSP 默认只开启了 GPIO 和 USART0 的功能，如果需使用更多的片上资源，需要利用 ENV 工具对BSP 进行配置，步骤如下：
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1. 在 bsp 下打开 env 工具。
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2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
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3. 输入`scons --target=mdk5` 命令重新生成工程。
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## 注意事项
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开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载，如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。
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## 联系人信息
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维护人:
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- [QT-one](https://github.com/QT-one)
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@ -0,0 +1,15 @@
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# for module compiling
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import os #包含os库
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Import('RTT_ROOT') #导入RTT_ROOT对象（RTT_ROOT代表的是RT-Thread源码包）
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from building import * #把building模块的所有内容都导入到当前模块中
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cwd = GetCurrentDir() #获取当前路径，并将该路径信息保存到变量cwd中
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objs = [] #创建一个list型变量objs
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list = os.listdir(cwd) #得到当前目录下的所有子目录，并保存到变量list中
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for d in list: #for循环用d记录循环的次数，直到寻遍所有路径
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path = os.path.join(cwd, d) #根据d获取到不同的路径
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if os.path.isfile(os.path.join(path, 'SConscript')): #如果该路径下存在名为SConscript的文件
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objs = objs + SConscript(os.path.join(d, 'SConscript')) #将路径中SConscript文件内的源码读取到objs中
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Return('objs') #将objs返回出去
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
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print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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print(RTT_ROOT)
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exit(-1)
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TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM == 'iar':
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env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
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Export('RTT_ROOT')
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Export('rtconfig')
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SDK_ROOT = os.path.abspath('./')
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if os.path.exists(SDK_ROOT + '/libraries'):
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libraries_path_prefix = SDK_ROOT + '/libraries'
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else:
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libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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ht32_library = 'HT32_STD_1xxxx_FWLib'
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rtconfig.BSP_LIBRARY_TYPE = ht32_library
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# include libraries
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objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript')))
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# include drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript')))
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# make a building
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DoBuilding(TARGET, objs)
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#导入其他模块的变量
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Import('RTT_ROOT')
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Import('rtconfig')
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#导入使用到的模块
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from building import *
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#获取当前目录的路径
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cwd = GetCurrentDir()
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#创建一个列表，用于保存需要使用到的C文件路径
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src = Glob('*c')
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#创建一个列表，用于保存需要包含的H文件路径
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path = [cwd]
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#创建一个组别
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
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#返回创建好的组别
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Return('group')
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-04-08 QT-one first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "board.h"
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/* defined the led2 pin: pd15 */
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#define LED1_PIN GET_PIN(D, 15)
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/* defined the led3 pin: pe0 */
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#define LED2_PIN GET_PIN(E, 0)
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int main(void)
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{
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rt_uint32_t speed = 200;
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/* set led1 pin mode to output */
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rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
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/* set led2 pin mode to output */
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rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
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while (1)
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{
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rt_pin_write(LED1_PIN, PIN_LOW);
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rt_pin_write(LED2_PIN, PIN_HIGH);
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rt_thread_mdelay(speed);
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rt_pin_write(LED1_PIN, PIN_HIGH);
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rt_pin_write(LED2_PIN, PIN_LOW);
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rt_thread_mdelay(speed);
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}
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}
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menu "Hardware Drivers Config"
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config SOC_HT32F12366
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bool
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select SOC_SERIES_HT32F1
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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menu "Onboard Peripheral Drivers"
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endmenu
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menu "On-chip Peripheral Drivers"
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config BSP_USING_GPIO
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bool "Enable GPIO"
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select RT_USING_PIN
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default n
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menuconfig BSP_USING_UART
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bool "Enable UART"
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default n
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select RT_USING_SERIAL
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if BSP_USING_UART
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config BSP_USING_USART0
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bool "Enable USART0"
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default n
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config BSP_USING_USART1
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bool "Enable USART1"
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default n
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config BSP_USING_UART0
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bool "Enable UART0"
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default n
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config BSP_USING_UART1
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bool "Enable UART1"
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default n
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endif
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menuconfig BSP_USING_SPI
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bool "Enable SPI Bus"
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default n
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select RT_USING_SPI
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if BSP_USING_SPI
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config BSP_USING_SPI0
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bool "Enable SPI0 Bus"
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default n
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config BSP_USING_SPI1
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bool "Enable SPI1 Bus"
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default n
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endif
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menuconfig BSP_USING_I2C
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bool "Enable I2C Bus"
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default n
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select RT_USING_I2C
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if BSP_USING_I2C
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config BSP_USING_I2C0
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bool "Enable I2C0 Bus"
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default n
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config BSP_USING_I2C1
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bool "Enable I2C1 Bus"
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default n
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endif
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endmenu
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menu "Board extended module Drivers"
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endmenu
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endmenu
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import os
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import rtconfig
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from building import *
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Import('SDK_LIB')
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cwd = GetCurrentDir()
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src = Glob('src/*.c')
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startup_path_prefix = SDK_LIB
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if rtconfig.CROSS_TOOL == 'gcc':
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src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s']
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elif rtconfig.CROSS_TOOL == 'keil':
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src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s']
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elif rtconfig.CROSS_TOOL == 'iar':
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src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s']
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path = [cwd]
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path = [cwd + '/inc']
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CPPDEFINES = ['USE_HT32F12366_SK, USE_HT32F12365_66, USE_MEM_HT32F12366']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
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Return('group')
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@ -0,0 +1,64 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-04-08 QT-one first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <rtthread.h>
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#include "ht32.h"
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#include "ht32_msp.h"
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#ifdef BSP_USING_GPIO
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#include "drv_gpio.h"
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#endif
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#ifdef BSP_USING_UART
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#include "drv_usart.h"
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#endif
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#ifdef BSP_USING_SPI
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#include "drv_spi.h"
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#endif
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#ifdef BSP_USING_I2C
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#include "drv_i2c.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* whether use board external SRAM memory */
|
||||
#define HT32_EXT_SRAM 0
|
||||
#define HT32_EXT_SRAM_BEGIN 0x68000000
|
||||
#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024)
|
||||
|
||||
/* internal sram memory size */
|
||||
#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE)
|
||||
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN ((void *)&__bss_end)
|
||||
#endif
|
||||
#define HEAP_END HT32_SRAM_END
|
||||
|
||||
void rt_hw_board_clock_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __BOARD_H__ */
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-08 QT-one first version
|
||||
*/
|
||||
|
||||
#ifndef __HT32_MSP_H__
|
||||
#define __HT32_MSP_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "ht32.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* UART gpio */
|
||||
#ifdef BSP_USING_UART
|
||||
#ifdef BSP_USING_USART0
|
||||
|
||||
#define HTCFG_USART0_IPN USART0
|
||||
|
||||
#define _HTCFG_USART0_TX_GPIOX A
|
||||
#define _HTCFG_USART0_TX_GPION 8
|
||||
#define _HTCFG_USART0_RX_GPIOX A
|
||||
#define _HTCFG_USART0_RX_GPION 10
|
||||
|
||||
#define HTCFG_USART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_TX_GPIOX)
|
||||
#define HTCFG_USART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_TX_GPIOX)
|
||||
#define HTCFG_USART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_TX_GPIOX)
|
||||
#define HTCFG_USART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_TX_GPION)
|
||||
|
||||
#define HTCFG_USART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_RX_GPIOX)
|
||||
#define HTCFG_USART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_RX_GPIOX)
|
||||
#define HTCFG_USART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_RX_GPIOX)
|
||||
#define HTCFG_USART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_RX_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_USART1
|
||||
|
||||
#define HTCFG_USART1_IPN USART1
|
||||
|
||||
#define _HTCFG_USART1_TX_GPIOX A
|
||||
#define _HTCFG_USART1_TX_GPION 4
|
||||
#define _HTCFG_USART1_RX_GPIOX A
|
||||
#define _HTCFG_USART1_RX_GPION 5
|
||||
|
||||
#define HTCFG_USART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_TX_GPIOX)
|
||||
#define HTCFG_USART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_TX_GPIOX)
|
||||
#define HTCFG_USART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_TX_GPIOX)
|
||||
#define HTCFG_USART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_TX_GPION)
|
||||
|
||||
#define HTCFG_USART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_RX_GPIOX)
|
||||
#define HTCFG_USART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_RX_GPIOX)
|
||||
#define HTCFG_USART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_RX_GPIOX)
|
||||
#define HTCFG_USART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_RX_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_UART0
|
||||
|
||||
#define HTCFG_UART0_IPN UART0
|
||||
|
||||
#define _HTCFG_UART0_TX_GPIOX C
|
||||
#define _HTCFG_UART0_TX_GPION 9
|
||||
#define _HTCFG_UART0_RX_GPIOX C
|
||||
#define _HTCFG_UART0_RX_GPION 10
|
||||
|
||||
#define HTCFG_UART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_TX_GPIOX)
|
||||
#define HTCFG_UART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_TX_GPIOX)
|
||||
#define HTCFG_UART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_TX_GPIOX)
|
||||
#define HTCFG_UART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_TX_GPION)
|
||||
|
||||
#define HTCFG_UART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_RX_GPIOX)
|
||||
#define HTCFG_UART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_RX_GPIOX)
|
||||
#define HTCFG_UART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_RX_GPIOX)
|
||||
#define HTCFG_UART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_RX_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_UART1
|
||||
|
||||
#define HTCFG_UART1_IPN UART1
|
||||
|
||||
#define _HTCFG_UART1_TX_GPIOX C
|
||||
#define _HTCFG_UART1_TX_GPION 2
|
||||
#define _HTCFG_UART1_RX_GPIOX C
|
||||
#define _HTCFG_UART1_RX_GPION 3
|
||||
|
||||
#define HTCFG_UART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_TX_GPIOX)
|
||||
#define HTCFG_UART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_TX_GPIOX)
|
||||
#define HTCFG_UART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_TX_GPIOX)
|
||||
#define HTCFG_UART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_TX_GPION)
|
||||
|
||||
#define HTCFG_UART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_RX_GPIOX)
|
||||
#define HTCFG_UART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_RX_GPIOX)
|
||||
#define HTCFG_UART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_RX_GPIOX)
|
||||
#define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* SPI gpio */
|
||||
#ifdef BSP_USING_SPI
|
||||
#ifdef BSP_USING_SPI0
|
||||
|
||||
#define HTCFG_SPI0_IPN SPI0
|
||||
|
||||
#define _HTCFG_SPI0_SCK_GPIOX B
|
||||
#define _HTCFG_SPI0_SCK_GPION 3
|
||||
|
||||
#define _HTCFG_SPI0_MISO_GPIOX B
|
||||
#define _HTCFG_SPI0_MISO_GPION 5
|
||||
|
||||
#define _HTCFG_SPI0_MOSI_GPIOX B
|
||||
#define _HTCFG_SPI0_MOSI_GPION 4
|
||||
|
||||
#define HTCFG_SPI0_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_SCK_GPIOX)
|
||||
#define HTCFG_SPI0_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_SCK_GPIOX)
|
||||
#define HTCFG_SPI0_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_SCK_GPION)
|
||||
|
||||
#define HTCFG_SPI0_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MISO_GPIOX)
|
||||
#define HTCFG_SPI0_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MISO_GPIOX)
|
||||
#define HTCFG_SPI0_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MISO_GPION)
|
||||
|
||||
#define HTCFG_SPI0_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MOSI_GPIOX)
|
||||
#define HTCFG_SPI0_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MOSI_GPIOX)
|
||||
#define HTCFG_SPI0_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MOSI_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI1
|
||||
|
||||
#define HTCFG_SPI1_IPN SPI1
|
||||
|
||||
#define _HTCFG_SPI1_SCK_GPIOX B
|
||||
#define _HTCFG_SPI1_SCK_GPION 7
|
||||
|
||||
#define _HTCFG_SPI1_MISO_GPIOX B
|
||||
#define _HTCFG_SPI1_MISO_GPION 9
|
||||
|
||||
#define _HTCFG_SPI1_MOSI_GPIOX B
|
||||
#define _HTCFG_SPI1_MOSI_GPION 8
|
||||
|
||||
#define HTCFG_SPI1_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_SCK_GPIOX)
|
||||
#define HTCFG_SPI1_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_SCK_GPIOX)
|
||||
#define HTCFG_SPI1_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_SCK_GPION)
|
||||
|
||||
#define HTCFG_SPI1_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MISO_GPIOX)
|
||||
#define HTCFG_SPI1_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MISO_GPIOX)
|
||||
#define HTCFG_SPI1_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MISO_GPION)
|
||||
|
||||
#define HTCFG_SPI1_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MOSI_GPIOX)
|
||||
#define HTCFG_SPI1_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MOSI_GPIOX)
|
||||
#define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* I2C gpio */
|
||||
#ifdef BSP_USING_I2C
|
||||
#ifdef BSP_USING_I2C0
|
||||
|
||||
#define HTCFG_I2C0_IPN I2C0
|
||||
|
||||
#define _HTCFG_I2C0_SCL_GPIOX B
|
||||
#define _HTCFG_I2C0_SCL_GPION 12
|
||||
|
||||
#define _HTCFG_I2C0_SDA_GPIOX B
|
||||
#define _HTCFG_I2C0_SDA_GPION 13
|
||||
|
||||
#define HTCFG_I2C0_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SCL_GPIOX)
|
||||
#define HTCFG_I2C0_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SCL_GPIOX)
|
||||
#define HTCFG_I2C0_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SCL_GPION)
|
||||
|
||||
#define HTCFG_I2C0_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SDA_GPIOX)
|
||||
#define HTCFG_I2C0_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SDA_GPIOX)
|
||||
#define HTCFG_I2C0_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SDA_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_I2C1
|
||||
|
||||
#define HTCFG_I2C1_IPN I2C1
|
||||
|
||||
#define _HTCFG_I2C1_SCL_GPIOX A
|
||||
#define _HTCFG_I2C1_SCL_GPION 0
|
||||
|
||||
#define _HTCFG_I2C1_SDA_GPIOX A
|
||||
#define _HTCFG_I2C1_SDA_GPION 1
|
||||
|
||||
#define HTCFG_I2C1_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SCL_GPIOX)
|
||||
#define HTCFG_I2C1_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SCL_GPIOX)
|
||||
#define HTCFG_I2C1_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SCL_GPION)
|
||||
|
||||
#define HTCFG_I2C1_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SDA_GPIOX)
|
||||
#define HTCFG_I2C1_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SDA_GPIOX)
|
||||
#define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
void ht32_usart_gpio_init(void *instance);
|
||||
void ht32_spi_gpio_init(void *instance);
|
||||
void ht32_i2c_gpio_init(void *instance);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HT32_MSP_H__ */
|
||||
|
|
@ -0,0 +1,453 @@
|
|||
/*********************************************************************************************************//**
|
||||
* @file IP/Example/ht32f1xxxx_01_usbdconf.h
|
||||
* @version $Rev:: 1090 $
|
||||
* @date $Date:: 2018-01-29 #$
|
||||
* @brief The configuration file of USB Device Driver.
|
||||
*************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Firmware Disclaimer Information
|
||||
*
|
||||
* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
|
||||
* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
|
||||
* other intellectual property laws.
|
||||
*
|
||||
* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
|
||||
* other than HOLTEK and the customer.
|
||||
*
|
||||
* 3. The program technical documentation, including the code, is provided "as is" and for customer reference
|
||||
* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
|
||||
* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
|
||||
* the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
|
||||
*
|
||||
* <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2>
|
||||
************************************************************************************************************/
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
|
||||
#ifndef __HT32F1XXXX_01_USBDCONF_H
|
||||
#define __HT32F1XXXX_01_USBDCONF_H
|
||||
|
||||
// <e0> Enter Low Power mode when Suspended
|
||||
#define USBDCORE_ENABLE_LOW_POWER (0)
|
||||
// </e>
|
||||
|
||||
#if (USBDCORE_ENABLE_LOW_POWER == 1)
|
||||
#define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE)
|
||||
#else
|
||||
#define USBDCore_LowPower(...)
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* USB Interrupt Enable */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <h> USB Interrupt Setting (UIER)
|
||||
// <o0.0> USB Global Interrupt Enable (UGIE) (Default)
|
||||
// <o0.1> Start Of Frame Interrupt Enable (SOFIE)
|
||||
// <o0.2> USB Reset Interrupt Enable (URSTIE) (Default)
|
||||
// <o0.3> Resume Interrupt Enable (RSMIE) (Default)
|
||||
// <o0.4> Suspend Interrupt Enable (SUSPIE) (Default)
|
||||
// <o0.5> Expected Start of Frame Interrupt Enable (ESOFE)
|
||||
// <o0.8> Control Endpoint Interrupt Enable (EP0IE) (Default)
|
||||
// <o0.9> Endpoint1 Interrupt Enable (EP1IE)
|
||||
// <o0.10> Endpoint2 Interrupt Enable (EP2IE)
|
||||
// <o0.11> Endpoint3 Interrupt Enable (EP3IE)
|
||||
// <o0.12> Endpoint4 Interrupt Enable (EP4IE)
|
||||
// <o0.13> Endpoint5 Interrupt Enable (EP5IE)
|
||||
// <o0.14> Endpoint6 Interrupt Enable (EP6IE)
|
||||
// <o0.15> Endpoint7 Interrupt Enable (EP7IE)
|
||||
#define _UIER (0x011D)
|
||||
// </h>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint0 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <h> Control Endpoint0 Configuration
|
||||
// <o0> Endpoint Buffer Length (EPLEN)
|
||||
// <8=> 8 bytes
|
||||
// <16=> 16 bytes
|
||||
// <32=> 32 bytes
|
||||
// <64=> 64 bytes
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP0LEN (64)
|
||||
|
||||
|
||||
// <h> Control Endpoint0 Interrupt Enable Settings (EP0IER)
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE) (Default)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
// <o0.8> SETUP Token Packet Received Interrupt Enable (STRXIE)
|
||||
// <o0.9> SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default)
|
||||
// <o0.10> SETUP Data Error Interrupt Enable (SDERIE)
|
||||
// <o0.11> Zero Length Data Packet Received Interrupt Enable (ZLRXIE)
|
||||
#define _EP0_IER (0x212)
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint1 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint1 Configuration
|
||||
#define _EP1_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP1_CFG_EPADR (1)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP1_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP1_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP1_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP1LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP1_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint2 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint2 Configuration
|
||||
#define _EP2_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP2_CFG_EPADR (2)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP2_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP2_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP2_CFG_EPDIR (0)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP2LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP2_IER (0x002)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint3 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint3 Configuration
|
||||
#define _EP3_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP3_CFG_EPADR (3)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP3_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP3_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP3_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP3LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP3_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint4 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint4 Configuration
|
||||
#define _EP4_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP4_CFG_EPADR (4)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP4_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP4_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP4_CFG_EPDIR (0)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP4LEN_TMP (8)
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP4_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP4_IER (0x02)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint5 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint5 Configuration
|
||||
#define _EP5_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP5_CFG_EPADR (5)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP5_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP5_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP5_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP5LEN_TMP (8)
|
||||
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP5_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP5_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint6 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint6 Configuration
|
||||
#define _EP6_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP6_CFG_EPADR (6)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP6_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP6_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP6_CFG_EPDIR (0)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP6LEN_TMP (8)
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP6_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP6_IER (0x02)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint7 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint7 Configuration
|
||||
#define _EP7_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP7_CFG_EPADR (7)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP7_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP7_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP7_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP7LEN_TMP (8)
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP7_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP7_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,490 @@
|
|||
/*********************************************************************************************************//**
|
||||
* @file IP/Example/ht32f1xxxx_conf.h
|
||||
* @version $Rev:: 2922 $
|
||||
* @date $Date:: 2023-06-07 #$
|
||||
* @brief Library configuration file.
|
||||
*************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Firmware Disclaimer Information
|
||||
*
|
||||
* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
|
||||
* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
|
||||
* other intellectual property laws.
|
||||
*
|
||||
* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
|
||||
* other than HOLTEK and the customer.
|
||||
*
|
||||
* 3. The program technical documentation, including the code, is provided "as is" and for customer reference
|
||||
* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
|
||||
* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
|
||||
* the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
|
||||
*
|
||||
* <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2>
|
||||
************************************************************************************************************/
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
|
||||
#ifndef __HT32F1XXXX_CONF_H
|
||||
#define __HT32F1XXXX_CONF_H
|
||||
|
||||
/* Exported constants --------------------------------------------------------------------------------------*/
|
||||
|
||||
#define RETARGET_ITM 0
|
||||
#define RETARGET_USB 1
|
||||
#define RETARGET_SYSLOG 2
|
||||
#define RETARGET_COM1 10
|
||||
#define RETARGET_COM2 11
|
||||
#define RETARGET_USART0 12
|
||||
#define RETARGET_USART1 13
|
||||
#define RETARGET_UART0 14
|
||||
#define RETARGET_UART1 15
|
||||
|
||||
|
||||
/* Retarget settings of the C standard I/O library functions (printf, scanf, getchar, ...etc.) */
|
||||
/*
|
||||
// <q> Enable Retarget
|
||||
// <o1> Retarget Port
|
||||
// <0=> ITM
|
||||
// <1=> USB Virtual COM
|
||||
// <2=> Syslog
|
||||
// <10=> COM1
|
||||
// <11=> COM2
|
||||
// <12=> USART0
|
||||
// <13=> USART1
|
||||
// <14=> UART0
|
||||
// <15=> UART1
|
||||
// <q2> Enable Auto Return
|
||||
// <i> Auto Return function adds "\r" before "\n" automatically when print message by Retarget.
|
||||
*/
|
||||
#define _RETARGET 1
|
||||
#define RETARGET_PORT 10
|
||||
#define _AUTO_RETURN 0
|
||||
|
||||
#ifndef AUTO_RETURN
|
||||
#if (_AUTO_RETURN == 1)
|
||||
#define AUTO_RETURN
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Enable Interrupt Mode for UxART Retarget
|
||||
// <h> Retarget COM/UxART Setting
|
||||
// <o0> UxART Baudrate
|
||||
// <q1> Enable Interrupt Mode for UxART Tx Retarget
|
||||
// <q2> Define UxARTn_IRQHandler By Retarget (ht32_serial.c)
|
||||
// <i> Disable (RETARGET_DEFINE_HANDLER = 0) if application already have UxARTn_IRQHandler.
|
||||
// <i> RETARGET_UART_IRQHandler() shall be called by UxARTn_IRQHandler when disable.
|
||||
// <o3> Tx Buffer Length (in byte)
|
||||
// </h>
|
||||
*/
|
||||
#define RETARGET_UxART_BAUDRATE 115200
|
||||
#define RETARGET_INT_MODE 0
|
||||
#define RETARGET_DEFINE_HANDLER 1
|
||||
#define RETARGET_INT_BUFFER_SIZE 64
|
||||
|
||||
#if (_RETARGET == 1)
|
||||
#if (RETARGET_PORT == RETARGET_ITM)
|
||||
#elif (RETARGET_PORT == RETARGET_USB)
|
||||
#define RETARGET_IS_USB
|
||||
// <h> Retarget USB Virtual COM Setting
|
||||
// <o0> Communication (Interrupt IN)
|
||||
// <1=> Endpoint 1
|
||||
// <2=> Endpoint 2
|
||||
// <3=> Endpoint 3
|
||||
// <4=> Endpoint 4
|
||||
// <5=> Endpoint 5
|
||||
// <6=> Endpoint 6
|
||||
// <7=> Endpoint 7
|
||||
// <o1> Data Rx (Bulk OUT)
|
||||
// <1=> Endpoint 1
|
||||
// <2=> Endpoint 2
|
||||
// <3=> Endpoint 3
|
||||
// <4=> Endpoint 4
|
||||
// <5=> Endpoint 5
|
||||
// <6=> Endpoint 6
|
||||
// <7=> Endpoint 7
|
||||
// <o2> Data Tx (Bulk IN)
|
||||
// <1=> Endpoint 1
|
||||
// <2=> Endpoint 2
|
||||
// <3=> Endpoint 3
|
||||
// <4=> Endpoint 4
|
||||
// <5=> Endpoint 5
|
||||
// <6=> Endpoint 6
|
||||
// <7=> Endpoint 7
|
||||
// <o3> Communication Endpoint Buffer Length (in byte) <4-64:4>
|
||||
// <o4> Data Rx Endpoint Buffer Length (in byte) <4-64:4>
|
||||
// <o5> Data Tx Endpoint Buffer Length (in byte) <4-64:4>
|
||||
// <o6> Rx Buffer Length (in byte) <64-1024:4>
|
||||
// <o7> Tx Buffer Length (in byte) <1-63:1>
|
||||
// <i> Please use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1.
|
||||
// <o8> USB Tx Mode (BULK IN)
|
||||
// <0=> Block Mode (Wait until both USB and terminal software are ready)
|
||||
// <1=> Non-Block Mode (Drop data if USB or terminal software is not ready)
|
||||
// <q9> Enable HSI Auto Trim By USB Function
|
||||
// <i> Need turn on if the USB clock source is from HSI (PLL USBPLL clock Source).
|
||||
#define RETARGET_CTRL_EPT (5)
|
||||
#define RETARGET_RX_EPT (6)
|
||||
#define RETARGET_TX_EPT (7)
|
||||
#define RETARGET_CTRL_EPTLEN (8)
|
||||
#define RETARGET_RX_EPTLEN (64)
|
||||
#define RETARGET_TX_EPTLEN (64)
|
||||
#define RETARGET_BUFFER_SIZE (64)
|
||||
#define RETARGET_TXBUFFER_SIZE (1) // Use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1.
|
||||
#define RETARGET_USB_MODE (0)
|
||||
#define RETARGET_HSI_ATM (1)
|
||||
// </h>
|
||||
#elif (RETARGET_PORT == RETARGET_COM1)
|
||||
#define RETARGET_COM_PORT COM1
|
||||
#define RETARGET_USART_PORT COM1_PORT
|
||||
#define RETARGET_UART_IRQn COM1_IRQn
|
||||
#define RETARGET_UART_IRQHandler COM1_IRQHandler
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_COM2)
|
||||
#define RETARGET_COM_PORT COM2
|
||||
#define RETARGET_USART_PORT COM2_PORT
|
||||
#define RETARGET_UART_IRQn COM2_IRQn
|
||||
#define RETARGET_UART_IRQHandler COM2_IRQHandler
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_USART0)
|
||||
#define RETARGET_UxART_IPN USART0
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_USART1)
|
||||
#define RETARGET_UxART_IPN USART1
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_UART0)
|
||||
#define RETARGET_UxART_IPN UART0
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_UART1)
|
||||
#define RETARGET_UxART_IPN UART1
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#endif
|
||||
extern void RETARGET_Configuration(void);
|
||||
#else
|
||||
#define RETARGET_Configuration(...)
|
||||
#undef printf
|
||||
#undef getchar
|
||||
#define printf(...)
|
||||
#define getchar() (0)
|
||||
#endif
|
||||
|
||||
#if (RETARGET_DEFINE_HANDLER == 0)
|
||||
#undef RETARGET_UART_IRQHandler
|
||||
#endif
|
||||
|
||||
/*
|
||||
//<e0> Enable HT32 Time Function
|
||||
// <i> Provide "Time_GetTick()" and "Time_Dealy()" functions.
|
||||
|
||||
// <o1> Timer Selection
|
||||
// <0=> BFTM0
|
||||
// <1=> BFTM1
|
||||
// <2=> SCTM0
|
||||
// <3=> SCTM1
|
||||
// <4=> SCTM2
|
||||
// <5=> SCTM3
|
||||
// <6=> PWM0
|
||||
// <7=> PWM1
|
||||
// <8=> PWM2
|
||||
// <9=> GPTM0
|
||||
// <10=> GPTM1
|
||||
// <11=> MCTM0
|
||||
|
||||
// <h> Timer Clock Setting
|
||||
// </h>
|
||||
// <i> Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler)
|
||||
// <i> HTCFG_TIME_CLKSRC = _HTCFG_TIME_CORECLK / (2^HTCFG_TIME_PCLK_DIV)
|
||||
// <i> _HTCFG_TIME_CORECLK = LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL)
|
||||
|
||||
// <o2> -- Core Clock Setting (CK_AHB)
|
||||
// <i> HTCFG_TIME_CLKSEL
|
||||
// <i> 0 = Default Maximum (LIBCFG_MAX_SPEED)
|
||||
// <i> 1 = Manual Input (HTCFG_TIME_CLK_MANUAL)
|
||||
// <0=> Default Maximum (LIBCFG_MAX_SPEED)
|
||||
// <1=> Manual Input (HTCFG_TIME_CLK_MANUAL)
|
||||
|
||||
// <o3> -- Core Clock Manual Input (Hz)
|
||||
// <i> HTCFG_TIME_CLK_MANUAL
|
||||
// <i> Only meaningful when Core Clock Setting (HTCFG_TIME_CLKSEL) = Manual Input (1)
|
||||
|
||||
// <o4> -- APB Peripheral Clock Prescaler
|
||||
// <i> HTCFG_TIME_PCLK_DIV
|
||||
// <0=> /1
|
||||
// <1=> /2
|
||||
// <2=> /4
|
||||
// <3=> /8
|
||||
|
||||
// <o5> Time Tick (Hz, not applicable for BFTM) <1-1000000:100>
|
||||
// <i> Not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM.
|
||||
*/
|
||||
#if (0) // Enable HT32 Time Function
|
||||
#define HTCFG_TIME_IPSEL (0)
|
||||
#define HTCFG_TIME_CLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_TIME_CLKSRC)
|
||||
#define HTCFG_TIME_CLK_MANUAL (20000000) // Only meaningful when HTCFG_TIME_CLKSEL = 1 (Manual Input)
|
||||
#define HTCFG_TIME_PCLK_DIV (0) // 0 ~ 3. (/1, /2, /4, /8)
|
||||
#define HTCFG_TIME_TICKHZ (1000) // Hz, not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM
|
||||
#define HTCFG_TIME_MULTIPLE (1) // MUST be 1, 2, 4, 8. TICK = COUNT / MULTIPLE. Not applicable for BFTM.
|
||||
/*
|
||||
|
||||
Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler)
|
||||
HTCFG_TIME_CLKSRC = (_HTCFG_TIME_CORECLK) / (2^HTCFG_TIME_PCLK_DIV)
|
||||
where _HTCFG_TIME_CORECLK can be LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL)
|
||||
|
||||
Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time)
|
||||
Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second
|
||||
(Interrupt Time is not applicable for BFTM)
|
||||
|
||||
Example: 32-bit BFTM with 48 MHz Timer Clock
|
||||
HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000
|
||||
Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second)
|
||||
BFTM do not use interrupt
|
||||
|
||||
Example: 16-bit GPTM with 1 ms tick
|
||||
HTCFG_TIME_TICKHZ = 1000 (Hz)
|
||||
HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick)
|
||||
Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day)
|
||||
Interrupt Time: 65536 / (1000 * 1) = 65.536 Second (Trigger interrupt every 65.536 Second)
|
||||
*/
|
||||
#endif
|
||||
/*
|
||||
//</e>
|
||||
*/
|
||||
|
||||
/* !!! NOTICE !!!
|
||||
* How to adjust the value of High Speed External oscillator (HSE)?
|
||||
The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h".
|
||||
If your board uses a different HSE speed, please add a new compiler preprocessor
|
||||
C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE,
|
||||
or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file (this file).
|
||||
*/
|
||||
/*
|
||||
//<e0> Enable User Define HSE Value
|
||||
// <i> Enable user define HSE value to overwrite default "HSE_VALUE" define in "ht32fxxxxx_nn.h".
|
||||
// <o1> HSE Value (Hz)
|
||||
*/
|
||||
#if (0)
|
||||
#define HSE_VALUE 16000000
|
||||
#endif
|
||||
/*
|
||||
//</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
//<q> Enable CKOUT Function
|
||||
*/
|
||||
#define ENABLE_CKOUT 0
|
||||
|
||||
|
||||
/* The DEBUG definition to enter debug mode for library */
|
||||
/*
|
||||
//<q> Library Debug Mode
|
||||
*/
|
||||
#define HT32_LIB_DEBUG 0
|
||||
|
||||
|
||||
/* Enable/disable the specific peripheral inclusion */
|
||||
|
||||
// <h> Library Inclusion Configuration
|
||||
/* ADC -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> ADC Library
|
||||
*/
|
||||
#define _ADC 1
|
||||
|
||||
/* AES -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> AES Library
|
||||
*/
|
||||
#define _AES 1
|
||||
|
||||
/* BFTM ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> BFTM Library
|
||||
*/
|
||||
#define _BFTM 1
|
||||
|
||||
/* Clock Control -------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Clock Control Library
|
||||
*/
|
||||
#define _CKCU 1
|
||||
|
||||
/* Comparator/OPA ------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Comparator/OPA Library
|
||||
*/
|
||||
#define _CMP_OPA 1
|
||||
|
||||
/* Comparator ----------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Comparator Library
|
||||
*/
|
||||
#define _CMP 1
|
||||
|
||||
/* CRC -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> CRC Library
|
||||
*/
|
||||
#define _CRC 1
|
||||
|
||||
/* CSIF ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> CSIF Library
|
||||
*/
|
||||
#define _CSIF 1
|
||||
|
||||
/* EBI -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> EBI Library
|
||||
*/
|
||||
#define _EBI 1
|
||||
|
||||
/* EXTI ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> EXTI Library
|
||||
*/
|
||||
#define _EXTI 1
|
||||
|
||||
/* Flash ---------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Flash Library
|
||||
*/
|
||||
#define _FLASH 1
|
||||
|
||||
/* GPIO ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> GPIO Library
|
||||
*/
|
||||
#define _GPIO 1
|
||||
|
||||
/* GPTM ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> GPTM Library
|
||||
*/
|
||||
#define _GPTM 1
|
||||
|
||||
/* I2C -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> I2C Library
|
||||
*/
|
||||
#define _I2C 1
|
||||
|
||||
/* I2S -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> I2S Library
|
||||
*/
|
||||
#define _I2S 1
|
||||
|
||||
/* MCTM ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> MCTM Library
|
||||
*/
|
||||
#define _MCTM 1
|
||||
|
||||
/* PDMA ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> PDMA Library
|
||||
*/
|
||||
#define _PDMA 1
|
||||
|
||||
/* PWM -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> PWM Library
|
||||
*/
|
||||
#define _PWM 1
|
||||
|
||||
/* PWRCU ---------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> PWRCU Library
|
||||
*/
|
||||
#define _PWRCU 1
|
||||
|
||||
/* RSTCU ---------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> RSTCU Library
|
||||
*/
|
||||
#define _RSTCU 1
|
||||
|
||||
/* RTC -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> RTC Library
|
||||
*/
|
||||
#define _RTC 1
|
||||
|
||||
/* SCI -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> SCI Library
|
||||
*/
|
||||
#define _SCI 1
|
||||
|
||||
/* SCTM ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> SCTM Library
|
||||
*/
|
||||
#define _SCTM 1
|
||||
|
||||
/* SDIO ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> SDIO Library
|
||||
*/
|
||||
#define _SDIO 1
|
||||
|
||||
/* SPI -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> SPI Library
|
||||
*/
|
||||
#define _SPI 1
|
||||
|
||||
/* USART ---------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q0> USART/UART Library
|
||||
*/
|
||||
#define _USART 1
|
||||
|
||||
/* USBD ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> USB Library
|
||||
*/
|
||||
#define _USB 1
|
||||
|
||||
/* WDT -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> WDT Library
|
||||
*/
|
||||
#define _WDT 1
|
||||
|
||||
/* Misc ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Misc Library
|
||||
*/
|
||||
#define _MISC 1
|
||||
|
||||
/* Serial --------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Serial Library
|
||||
*/
|
||||
#define _SERIAL 1
|
||||
|
||||
/* Software Random Number ----------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Software Random Number Library
|
||||
*/
|
||||
#define _SWRAND 1
|
||||
|
||||
|
||||
// </h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x0400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, last block CSTACK};
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* linker script for AT32 with GNU ld
|
||||
*/
|
||||
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
|
||||
RAM (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */
|
||||
}
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x200;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
_etext = .;
|
||||
} > ROM = 0
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = .;
|
||||
} > ROM
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >RAM
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sstack = .;
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >RAM
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > RAM
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x0003FC00 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x0003FC00 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00020000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-08 QT-one first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
/* This feature will initialize the HT32 chip clock */
|
||||
void rt_hw_board_clock_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-08 QT-one first version
|
||||
*/
|
||||
|
||||
#include "ht32_msp.h"
|
||||
|
||||
/* GPIO configuration for UART */
|
||||
#ifdef BSP_USING_UART
|
||||
void ht32_usart_gpio_init(void *instance)
|
||||
{
|
||||
CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
|
||||
HT_USART_TypeDef *usart_x = (HT_USART_TypeDef *)instance;
|
||||
#ifdef BSP_USING_USART0
|
||||
if(HT_USART0 == usart_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_USART0_TX_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_USART0_RX_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock,ENABLE);
|
||||
/* Turn on UxART Rx internal pull up resistor to prevent unknow state */
|
||||
GPIO_PullResistorConfig(HTCFG_USART0_RX_GPIO_PORT,HTCFG_USART0_RX_GPIO_PIN,GPIO_PR_UP);
|
||||
/* Config AFIO mode as UxART function */
|
||||
AFIO_GPxConfig(HTCFG_USART0_TX_GPIO_ID,HTCFG_USART0_TX_GPIO_PIN,AFIO_FUN_USART_UART);
|
||||
AFIO_GPxConfig(HTCFG_USART0_RX_GPIO_ID,HTCFG_USART0_RX_GPIO_PIN,AFIO_FUN_USART_UART);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_USART1
|
||||
if(HT_USART1 == usart_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_USART1_TX_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_USART1_RX_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock,ENABLE);
|
||||
/* Turn on UxART Rx internal pull up resistor to prevent unknow state */
|
||||
GPIO_PullResistorConfig(HTCFG_USART1_RX_GPIO_PORT,HTCFG_USART1_RX_GPIO_PIN,GPIO_PR_UP);
|
||||
/* Config AFIO mode as UxART function */
|
||||
AFIO_GPxConfig(HTCFG_USART1_TX_GPIO_ID,HTCFG_USART1_TX_GPIO_PIN,AFIO_FUN_USART_UART);
|
||||
AFIO_GPxConfig(HTCFG_USART1_RX_GPIO_ID,HTCFG_USART1_RX_GPIO_PIN,AFIO_FUN_USART_UART);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_UART0
|
||||
if(HT_UART0 == usart_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_UART0_TX_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_UART0_RX_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock,ENABLE);
|
||||
/* Turn on UxART Rx internal pull up resistor to prevent unknow state */
|
||||
GPIO_PullResistorConfig(HTCFG_UART0_RX_GPIO_PORT,HTCFG_UART0_RX_GPIO_PIN,GPIO_PR_UP);
|
||||
/* Config AFIO mode as UxART function */
|
||||
AFIO_GPxConfig(HTCFG_UART0_TX_GPIO_ID,HTCFG_UART0_TX_GPIO_PIN,AFIO_FUN_USART_UART);
|
||||
AFIO_GPxConfig(HTCFG_UART0_RX_GPIO_ID,HTCFG_UART0_RX_GPIO_PIN,AFIO_FUN_USART_UART);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_UART1
|
||||
if(HT_UART1 == usart_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_UART1_TX_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_UART1_RX_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock,ENABLE);
|
||||
/* Turn on UxART Rx internal pull up resistor to prevent unknow state */
|
||||
GPIO_PullResistorConfig(HTCFG_UART1_RX_GPIO_PORT,HTCFG_UART1_RX_GPIO_PIN,GPIO_PR_UP);
|
||||
/* Config AFIO mode as UxART function */
|
||||
AFIO_GPxConfig(HTCFG_UART1_TX_GPIO_ID,HTCFG_UART1_TX_GPIO_PIN,AFIO_FUN_USART_UART);
|
||||
AFIO_GPxConfig(HTCFG_UART1_RX_GPIO_ID,HTCFG_UART1_RX_GPIO_PIN,AFIO_FUN_USART_UART);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/* GPIO configuration for SPI */
|
||||
#ifdef BSP_USING_SPI
|
||||
void ht32_spi_gpio_init(void *instance)
|
||||
{
|
||||
CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
|
||||
HT_SPI_TypeDef *spi_x = (HT_SPI_TypeDef *)instance;
|
||||
#ifdef BSP_USING_SPI0
|
||||
if(HT_SPI0 == spi_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_SPI0_SCK_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_SPI0_MISO_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_SPI0_MOSI_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock,ENABLE);
|
||||
|
||||
AFIO_GPxConfig(HTCFG_SPI0_SCK_GPIO_ID, HTCFG_SPI0_SCK_GPIO_PIN, AFIO_FUN_SPI);
|
||||
AFIO_GPxConfig(HTCFG_SPI0_MISO_GPIO_ID, HTCFG_SPI0_MISO_GPIO_PIN, AFIO_FUN_SPI);
|
||||
AFIO_GPxConfig(HTCFG_SPI0_MOSI_GPIO_ID, HTCFG_SPI0_MOSI_GPIO_PIN, AFIO_FUN_SPI);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI1
|
||||
if(HT_SPI1 == spi_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_SPI1_SCK_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_SPI1_MISO_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_SPI1_MOSI_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock,ENABLE);
|
||||
|
||||
AFIO_GPxConfig(HTCFG_SPI1_SCK_GPIO_ID, HTCFG_SPI1_SCK_GPIO_PIN, AFIO_FUN_SPI);
|
||||
AFIO_GPxConfig(HTCFG_SPI1_MISO_GPIO_ID, HTCFG_SPI1_MISO_GPIO_PIN, AFIO_FUN_SPI);
|
||||
AFIO_GPxConfig(HTCFG_SPI1_MOSI_GPIO_ID, HTCFG_SPI1_MOSI_GPIO_PIN, AFIO_FUN_SPI);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/* GPIO configuration for I2C */
|
||||
#ifdef BSP_USING_I2C
|
||||
void ht32_i2c_gpio_init(void *instance)
|
||||
{
|
||||
CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
|
||||
HT_I2C_TypeDef *i2c_x = (HT_I2C_TypeDef *)instance;
|
||||
#ifdef BSP_USING_I2C0
|
||||
if(HT_I2C0 == i2c_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_I2C0_SCL_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_I2C0_SDA_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock,ENABLE);
|
||||
/* Configure GPIO to I2C mode */
|
||||
AFIO_GPxConfig(HTCFG_I2C0_SCL_GPIO_ID,HTCFG_I2C0_SCL_GPIO_PIN,AFIO_FUN_I2C);
|
||||
AFIO_GPxConfig(HTCFG_I2C0_SDA_GPIO_ID,HTCFG_I2C0_SDA_GPIO_PIN,AFIO_FUN_I2C);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_I2C1
|
||||
if(HT_I2C1 == i2c_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_I2C1_SCL_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_I2C1_SDA_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock,ENABLE);
|
||||
/* Configure GPIO to I2C mode */
|
||||
AFIO_GPxConfig(HTCFG_I2C1_SCL_GPIO_ID,HTCFG_I2C1_SCL_GPIO_PIN,AFIO_FUN_I2C);
|
||||
AFIO_GPxConfig(HTCFG_I2C1_SDA_GPIO_ID,HTCFG_I2C1_SDA_GPIO_PIN,AFIO_FUN_I2C);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 411 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,273 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_MEMHEAP
|
||||
#define RT_MEMHEAP_FAST_MODE
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "usart0"
|
||||
#define RT_VER_NUM 0x50100
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_M
|
||||
#define ARCH_ARM_CORTEX_M3
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_SPI
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
|
||||
/* Network */
|
||||
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
|
||||
/* AI packages */
|
||||
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
|
||||
/* Sensors */
|
||||
|
||||
|
||||
/* Display */
|
||||
|
||||
|
||||
/* Timing */
|
||||
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
|
||||
/* Device Control */
|
||||
|
||||
|
||||
/* Other */
|
||||
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
#define SOC_FAMILY_HT32
|
||||
#define SOC_SERIES_HT32F1
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_HT32F12366
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART0
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m3'
|
||||
CROSS_TOOL='keil'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
# EXEC_PATH = r'D:\keil5\keil_v532\UV4'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M3 '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M3'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=None'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M3'
|
||||
AFLAGS += ' --fpu None'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<nTsel>2</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,392 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>HT32F12366</Device>
|
||||
<Vendor>Holtek</Vendor>
|
||||
<PackID>Holtek.HT32_DFP.1.0.19</PackID>
|
||||
<PackURL>http://mcu.holtek.com.tw/pack</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x20000) IROM(0x00000000,0x3FC00) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:HT32F12366$ARM\INC\Holtek\HT32F1xxxx\ht32f1xxxx_01.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:HT32F12366$SVD\HT32F12365_66.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
|
||||
<OutputName>rt-thread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M3"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x3fc00</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x3fc00</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>USE_HT32_CHIP=2</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,21 @@
|
|||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "../libraries/Kconfig"
|
||||
source "board/Kconfig"
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
# HT32F52352 BSP 说明
|
||||
|
||||
## 简介
|
||||
|
||||
ESK32-30501是合泰基于HT32F52352芯片并针对Cortex®-M0+入门而设计的评估板。本文档是为ESK32-30501开发板提供的BSP(板级支持包)说明。
|
||||
|
||||
主要内容如下：
|
||||
|
||||
- 开发板资源介绍
|
||||
- BSP 快速上手
|
||||
- 进阶使用方法
|
||||
|
||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
|
||||
|
||||
## 开发板介绍
|
||||
|
||||
ESK32-30501使用32位Arm® Cortex®-M0+高性能、低功耗单片机HT32F52352，针对Cortex®-M0+入门而设计。开发板外观如下图所示：
|
||||
|
||||
|
||||
|
||||
该开发板常用 **板载资源** 如下：
|
||||
|
||||
- MCU：HT32F52352，主频 48MHz，128KB FLASH ，16KB SRAM
|
||||
- 常用外设
|
||||
- LED：2个，（绿色，PC14、PC15）
|
||||
- 常用接口：USB 转串口 、USB SLAVE
|
||||
- 调试接口：板载的 e-Link32 Lite SWD 下载
|
||||
|
||||
开发板更多详细信息请参考合泰官网的相关文档[ESK32-30501](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30501)。
|
||||
|
||||
## 外设支持
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
| :--- | :---: | :--- |
|
||||
| USB 转串口 | 支持 | 使用 USART1 |
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| GPIO | 支持 | PA0, PA1...PD3 ---> PIN: 0, 1...51 |
|
||||
| USART | 支持 | USART0/1 |
|
||||
| UART | 支持 | UART0/1 |
|
||||
| SPI | 支持 | SPI0/1 |
|
||||
| I2C | 支持 | 硬件 I2C0/1 |
|
||||
| ADC | 暂不支持 | |
|
||||
| WDT | 暂不支持 | |
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多片上资源，实现更多高级功能。
|
||||
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 注：工程默认配置使用CMSIS-DAP下载方式，在通过 e-Link32 Lite 连接开发板的基础上，点击下载按钮即可下载程序到开发板。
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED1和LED2交替闪烁。
|
||||
|
||||
连接开发板对应串口到 PC（也可以通过e-Link32 Lite的模拟串口将开发板连接到PC）, 在终端工具里调整好串口配置（115200-8-1-N）并打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
> 注：由于RT-Thread的finsh控制台使用的是命令行的输入形式，推荐使用串口调试工具如：Tabby terminal 或者 Tera Term。
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 5.1.0 build Apr 10 2024 14:39:43
|
||||
2006 - 2024 Copyright by RT-Thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 USART1 的功能，如果需使用更多的片上资源，需要利用 ENV 工具对BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`scons --target=mdk5` 命令重新生成工程。
|
||||
|
||||
## 注意事项
|
||||
|
||||
开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载，如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [QT-one](https://github.com/QT-one)
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# for module compiling
|
||||
import os #包含os库
|
||||
Import('RTT_ROOT') #导入RTT_ROOT对象（RTT_ROOT代表的是RT-Thread源码包）
|
||||
from building import * #把building模块的所有内容都导入到当前模块中
|
||||
|
||||
cwd = GetCurrentDir() #获取当前路径，并将该路径信息保存到变量cwd中
|
||||
objs = [] #创建一个list型变量objs
|
||||
list = os.listdir(cwd) #得到当前目录下的所有子目录，并保存到变量list中
|
||||
|
||||
for d in list: #for循环用d记录循环的次数，直到寻遍所有路径
|
||||
path = os.path.join(cwd, d) #根据d获取到不同的路径
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')): #如果该路径下存在名为SConscript的文件
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript')) #将路径中SConscript文件内的源码读取到objs中
|
||||
|
||||
Return('objs') #将objs返回出去
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
ht32_library = 'HT32_STD_5xxxx_FWLib'
|
||||
rtconfig.BSP_LIBRARY_TYPE = ht32_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
#导入其他模块的变量
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
|
||||
#导入使用到的模块
|
||||
from building import *
|
||||
|
||||
#获取当前目录的路径
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
#创建一个列表，用于保存需要使用到的C文件路径
|
||||
src = Glob('*c')
|
||||
|
||||
#创建一个列表，用于保存需要包含的H文件路径
|
||||
path = [cwd]
|
||||
|
||||
#创建一个组别
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
|
||||
|
||||
#返回创建好的组别
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-08 QT-one first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "board.h"
|
||||
|
||||
/* defined the led2 pin: pc14 */
|
||||
#define LED1_PIN GET_PIN(C, 14)
|
||||
/* defined the led3 pin: pc15 */
|
||||
#define LED2_PIN GET_PIN(C, 15)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
rt_uint32_t speed = 200;
|
||||
/* set led1 pin mode to output */
|
||||
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
|
||||
/* set led2 pin mode to output */
|
||||
rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED1_PIN, PIN_LOW);
|
||||
rt_pin_write(LED2_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(speed);
|
||||
rt_pin_write(LED1_PIN, PIN_HIGH);
|
||||
rt_pin_write(LED2_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(speed);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_HT32F52352
|
||||
bool
|
||||
select SOC_SERIES_HT32F5
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default n
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_USART0
|
||||
bool "Enable USART0"
|
||||
default n
|
||||
|
||||
config BSP_USING_USART1
|
||||
bool "Enable USART1"
|
||||
default n
|
||||
|
||||
config BSP_USING_UART0
|
||||
bool "Enable UART0"
|
||||
default n
|
||||
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Enable SPI Bus"
|
||||
default n
|
||||
select RT_USING_SPI
|
||||
if BSP_USING_SPI
|
||||
config BSP_USING_SPI0
|
||||
bool "Enable SPI0 Bus"
|
||||
default n
|
||||
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable SPI1 Bus"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C
|
||||
bool "Enable I2C Bus"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_I2C
|
||||
config BSP_USING_I2C0
|
||||
bool "Enable I2C0 Bus"
|
||||
default n
|
||||
|
||||
config BSP_USING_I2C1
|
||||
bool "Enable I2C1 Bus"
|
||||
default n
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
|
||||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
Import('SDK_LIB')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = Glob('src/*.c')
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s']
|
||||
|
||||
path = [cwd]
|
||||
path = [cwd + '/inc']
|
||||
|
||||
CPPDEFINES = ['USE_HT32F52352_SK, USE_HT32F52342_52, USE_MEM_HT32F52352']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-08 QT-one first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "ht32.h"
|
||||
#include "ht32_msp.h"
|
||||
|
||||
#ifdef BSP_USING_GPIO
|
||||
#include "drv_gpio.h"
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART
|
||||
#include "drv_usart.h"
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI
|
||||
#include "drv_spi.h"
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C
|
||||
#include "drv_i2c.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* whether use board external SRAM memory */
|
||||
#define HT32_EXT_SRAM 0
|
||||
#define HT32_EXT_SRAM_BEGIN 0x68000000
|
||||
#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024)
|
||||
|
||||
/* internal sram memory size */
|
||||
#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE)
|
||||
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN ((void *)&__bss_end)
|
||||
#endif
|
||||
#define HEAP_END HT32_SRAM_END
|
||||
|
||||
void rt_hw_board_clock_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __BOARD_H__ */
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-08 QT-one first version
|
||||
*/
|
||||
|
||||
#ifndef __HT32_MSP_H__
|
||||
#define __HT32_MSP_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "ht32.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* UART gpio */
|
||||
#ifdef BSP_USING_UART
|
||||
#ifdef BSP_USING_USART0
|
||||
#define HTCFG_USART0_IPN USART0
|
||||
|
||||
#define _HTCFG_USART0_TX_GPIOX A
|
||||
#define _HTCFG_USART0_TX_GPION 2
|
||||
#define _HTCFG_USART0_RX_GPIOX A
|
||||
#define _HTCFG_USART0_RX_GPION 3
|
||||
|
||||
#define HTCFG_USART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_TX_GPIOX)
|
||||
#define HTCFG_USART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_TX_GPIOX)
|
||||
#define HTCFG_USART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_TX_GPIOX)
|
||||
#define HTCFG_USART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_TX_GPION)
|
||||
|
||||
#define HTCFG_USART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_RX_GPIOX)
|
||||
#define HTCFG_USART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_RX_GPIOX)
|
||||
#define HTCFG_USART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_RX_GPIOX)
|
||||
#define HTCFG_USART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_RX_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_USART1
|
||||
|
||||
#define HTCFG_USART1_IPN USART1
|
||||
|
||||
#define _HTCFG_USART1_TX_GPIOX A
|
||||
#define _HTCFG_USART1_TX_GPION 4
|
||||
#define _HTCFG_USART1_RX_GPIOX A
|
||||
#define _HTCFG_USART1_RX_GPION 5
|
||||
|
||||
#define HTCFG_USART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_TX_GPIOX)
|
||||
#define HTCFG_USART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_TX_GPIOX)
|
||||
#define HTCFG_USART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_TX_GPIOX)
|
||||
#define HTCFG_USART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_TX_GPION)
|
||||
|
||||
#define HTCFG_USART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_RX_GPIOX)
|
||||
#define HTCFG_USART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_RX_GPIOX)
|
||||
#define HTCFG_USART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_RX_GPIOX)
|
||||
#define HTCFG_USART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_RX_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_UART0
|
||||
|
||||
#define HTCFG_UART0_IPN UART0
|
||||
|
||||
#define _HTCFG_UART0_TX_GPIOX B
|
||||
#define _HTCFG_UART0_TX_GPION 2
|
||||
#define _HTCFG_UART0_RX_GPIOX B
|
||||
#define _HTCFG_UART0_RX_GPION 3
|
||||
|
||||
#define HTCFG_UART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_TX_GPIOX)
|
||||
#define HTCFG_UART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_TX_GPIOX)
|
||||
#define HTCFG_UART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_TX_GPIOX)
|
||||
#define HTCFG_UART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_TX_GPION)
|
||||
|
||||
#define HTCFG_UART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_RX_GPIOX)
|
||||
#define HTCFG_UART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_RX_GPIOX)
|
||||
#define HTCFG_UART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_RX_GPIOX)
|
||||
#define HTCFG_UART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_RX_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_UART1
|
||||
|
||||
#define HTCFG_UART1_IPN UART1
|
||||
|
||||
#define _HTCFG_UART1_TX_GPIOX B
|
||||
#define _HTCFG_UART1_TX_GPION 4
|
||||
#define _HTCFG_UART1_RX_GPIOX B
|
||||
#define _HTCFG_UART1_RX_GPION 5
|
||||
|
||||
#define HTCFG_UART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_TX_GPIOX)
|
||||
#define HTCFG_UART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_TX_GPIOX)
|
||||
#define HTCFG_UART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_TX_GPIOX)
|
||||
#define HTCFG_UART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_TX_GPION)
|
||||
|
||||
#define HTCFG_UART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_RX_GPIOX)
|
||||
#define HTCFG_UART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_RX_GPIOX)
|
||||
#define HTCFG_UART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_RX_GPIOX)
|
||||
#define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* SPI gpio */
|
||||
#ifdef BSP_USING_SPI
|
||||
#ifdef BSP_USING_SPI0
|
||||
|
||||
#define HTCFG_SPI0_IPN SPI0
|
||||
|
||||
#define _HTCFG_SPI0_SCK_GPIOX C
|
||||
#define _HTCFG_SPI0_SCK_GPION 0
|
||||
|
||||
#define _HTCFG_SPI0_MISO_GPIOX A
|
||||
#define _HTCFG_SPI0_MISO_GPION 11
|
||||
|
||||
#define _HTCFG_SPI0_MOSI_GPIOX A
|
||||
#define _HTCFG_SPI0_MOSI_GPION 9
|
||||
|
||||
#define HTCFG_SPI0_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_SCK_GPIOX)
|
||||
#define HTCFG_SPI0_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_SCK_GPIOX)
|
||||
#define HTCFG_SPI0_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_SCK_GPION)
|
||||
|
||||
#define HTCFG_SPI0_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MISO_GPIOX)
|
||||
#define HTCFG_SPI0_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MISO_GPIOX)
|
||||
#define HTCFG_SPI0_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MISO_GPION)
|
||||
|
||||
#define HTCFG_SPI0_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MOSI_GPIOX)
|
||||
#define HTCFG_SPI0_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MOSI_GPIOX)
|
||||
#define HTCFG_SPI0_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MOSI_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI1
|
||||
|
||||
#define HTCFG_SPI1_IPN SPI1
|
||||
|
||||
#define _HTCFG_SPI1_SCK_GPIOX A
|
||||
#define _HTCFG_SPI1_SCK_GPION 15
|
||||
|
||||
#define _HTCFG_SPI1_MISO_GPIOX B
|
||||
#define _HTCFG_SPI1_MISO_GPION 1
|
||||
|
||||
#define _HTCFG_SPI1_MOSI_GPIOX B
|
||||
#define _HTCFG_SPI1_MOSI_GPION 0
|
||||
|
||||
#define HTCFG_SPI1_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_SCK_GPIOX)
|
||||
#define HTCFG_SPI1_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_SCK_GPIOX)
|
||||
#define HTCFG_SPI1_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_SCK_GPION)
|
||||
|
||||
#define HTCFG_SPI1_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MISO_GPIOX)
|
||||
#define HTCFG_SPI1_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MISO_GPIOX)
|
||||
#define HTCFG_SPI1_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MISO_GPION)
|
||||
|
||||
#define HTCFG_SPI1_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MOSI_GPIOX)
|
||||
#define HTCFG_SPI1_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MOSI_GPIOX)
|
||||
#define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* I2C gpio */
|
||||
#ifdef BSP_USING_I2C
|
||||
#ifdef BSP_USING_I2C0
|
||||
|
||||
#define HTCFG_I2C0_IPN I2C0
|
||||
|
||||
#define _HTCFG_I2C0_SCL_GPIOX C
|
||||
#define _HTCFG_I2C0_SCL_GPION 12
|
||||
|
||||
#define _HTCFG_I2C0_SDA_GPIOX C
|
||||
#define _HTCFG_I2C0_SDA_GPION 13
|
||||
|
||||
#define HTCFG_I2C0_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SCL_GPIOX)
|
||||
#define HTCFG_I2C0_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SCL_GPIOX)
|
||||
#define HTCFG_I2C0_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SCL_GPION)
|
||||
|
||||
#define HTCFG_I2C0_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SDA_GPIOX)
|
||||
#define HTCFG_I2C0_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SDA_GPIOX)
|
||||
#define HTCFG_I2C0_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SDA_GPION)
|
||||
|
||||
#endif
|
||||
#ifdef BSP_USING_I2C1
|
||||
|
||||
#define HTCFG_I2C1_IPN I2C1
|
||||
|
||||
#define _HTCFG_I2C1_SCL_GPIOX A
|
||||
#define _HTCFG_I2C1_SCL_GPION 0
|
||||
|
||||
#define _HTCFG_I2C1_SDA_GPIOX A
|
||||
#define _HTCFG_I2C1_SDA_GPION 1
|
||||
|
||||
#define HTCFG_I2C1_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SCL_GPIOX)
|
||||
#define HTCFG_I2C1_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SCL_GPIOX)
|
||||
#define HTCFG_I2C1_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SCL_GPION)
|
||||
|
||||
#define HTCFG_I2C1_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SDA_GPIOX)
|
||||
#define HTCFG_I2C1_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SDA_GPIOX)
|
||||
#define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
void ht32_usart_gpio_init(void *instance);
|
||||
void ht32_spi_gpio_init(void *instance);
|
||||
void ht32_i2c_gpio_init(void *instance);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HT32_MSP_H__ */
|
||||
|
|
@ -0,0 +1,453 @@
|
|||
/*********************************************************************************************************//**
|
||||
* @file IP/Example/ht32f5xxxx_01_usbdconf.h
|
||||
* @version $Rev:: 2390 $
|
||||
* @date $Date:: 2017-12-21 #$
|
||||
* @brief The configuration file of USB Device Driver.
|
||||
*************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Firmware Disclaimer Information
|
||||
*
|
||||
* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
|
||||
* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
|
||||
* other intellectual property laws.
|
||||
*
|
||||
* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
|
||||
* other than HOLTEK and the customer.
|
||||
*
|
||||
* 3. The program technical documentation, including the code, is provided "as is" and for customer reference
|
||||
* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
|
||||
* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
|
||||
* the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
|
||||
*
|
||||
* <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2>
|
||||
************************************************************************************************************/
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
|
||||
#ifndef __HT32F5XXXX_01_USBDCONF_H
|
||||
#define __HT32F5XXXX_01_USBDCONF_H
|
||||
|
||||
// <e0> Enter Low Power mode when Suspended
|
||||
#define USBDCORE_ENABLE_LOW_POWER (0)
|
||||
// </e>
|
||||
|
||||
#if (USBDCORE_ENABLE_LOW_POWER == 1)
|
||||
#define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE)
|
||||
#else
|
||||
#define USBDCore_LowPower(...)
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* USB Interrupt Enable */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <h> USB Interrupt Setting (UIER)
|
||||
// <o0.0> USB Global Interrupt Enable (UGIE) (Default)
|
||||
// <o0.1> Start Of Frame Interrupt Enable (SOFIE)
|
||||
// <o0.2> USB Reset Interrupt Enable (URSTIE) (Default)
|
||||
// <o0.3> Resume Interrupt Enable (RSMIE) (Default)
|
||||
// <o0.4> Suspend Interrupt Enable (SUSPIE) (Default)
|
||||
// <o0.5> Expected Start of Frame Interrupt Enable (ESOFE)
|
||||
// <o0.8> Control Endpoint Interrupt Enable (EP0IE) (Default)
|
||||
// <o0.9> Endpoint1 Interrupt Enable (EP1IE)
|
||||
// <o0.10> Endpoint2 Interrupt Enable (EP2IE)
|
||||
// <o0.11> Endpoint3 Interrupt Enable (EP3IE)
|
||||
// <o0.12> Endpoint4 Interrupt Enable (EP4IE)
|
||||
// <o0.13> Endpoint5 Interrupt Enable (EP5IE)
|
||||
// <o0.14> Endpoint6 Interrupt Enable (EP6IE)
|
||||
// <o0.15> Endpoint7 Interrupt Enable (EP7IE)
|
||||
#define _UIER (0x011D)
|
||||
// </h>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint0 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <h> Control Endpoint0 Configuration
|
||||
// <o0> Endpoint Buffer Length (EPLEN)
|
||||
// <8=> 8 bytes
|
||||
// <16=> 16 bytes
|
||||
// <32=> 32 bytes
|
||||
// <64=> 64 bytes
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP0LEN (64)
|
||||
|
||||
|
||||
// <h> Control Endpoint0 Interrupt Enable Settings (EP0IER)
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE) (Default)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
// <o0.8> SETUP Token Packet Received Interrupt Enable (STRXIE)
|
||||
// <o0.9> SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default)
|
||||
// <o0.10> SETUP Data Error Interrupt Enable (SDERIE)
|
||||
// <o0.11> Zero Length Data Packet Received Interrupt Enable (ZLRXIE)
|
||||
#define _EP0_IER (0x212)
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint1 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint1 Configuration
|
||||
#define _EP1_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP1_CFG_EPADR (1)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP1_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP1_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP1_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP1LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP1_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint2 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint2 Configuration
|
||||
#define _EP2_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP2_CFG_EPADR (2)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP2_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP2_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP2_CFG_EPDIR (0)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP2LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP2_IER (0x002)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint3 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint3 Configuration
|
||||
#define _EP3_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP3_CFG_EPADR (3)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP3_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP3_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP3_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP3LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP3_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint4 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint4 Configuration
|
||||
#define _EP4_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP4_CFG_EPADR (4)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP4_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP4_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP4_CFG_EPDIR (0)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP4LEN_TMP (8)
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP4_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP4_IER (0x02)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint5 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint5 Configuration
|
||||
#define _EP5_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP5_CFG_EPADR (5)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP5_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP5_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP5_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP5LEN_TMP (8)
|
||||
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP5_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP5_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint6 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint6 Configuration
|
||||
#define _EP6_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP6_CFG_EPADR (6)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP6_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP6_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP6_CFG_EPDIR (0)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP6LEN_TMP (8)
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP6_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP6_IER (0x02)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint7 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint7 Configuration
|
||||
#define _EP7_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
#define _EP7_CFG_EPADR (7)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP7_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP7_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP7_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP7LEN_TMP (8)
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP7_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP7_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,569 @@
|
|||
/*********************************************************************************************************//**
|
||||
* @file IP/Example/ht32f5xxxx_02_usbdconf.h
|
||||
* @version $Rev:: 5656 $
|
||||
* @date $Date:: 2021-11-24 #$
|
||||
* @brief The configuration file of USB Device Driver.
|
||||
*************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Firmware Disclaimer Information
|
||||
*
|
||||
* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
|
||||
* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
|
||||
* other intellectual property laws.
|
||||
*
|
||||
* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
|
||||
* other than HOLTEK and the customer.
|
||||
*
|
||||
* 3. The program technical documentation, including the code, is provided "as is" and for customer reference
|
||||
* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
|
||||
* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
|
||||
* the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
|
||||
*
|
||||
* <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2>
|
||||
************************************************************************************************************/
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
|
||||
#ifndef __HT32F5XXXX_02_USBDCONF_H
|
||||
#define __HT32F5XXXX_02_USBDCONF_H
|
||||
|
||||
// <e0> Enter Low Power mode when Suspended
|
||||
#define USBDCORE_ENABLE_LOW_POWER (0)
|
||||
// </e>
|
||||
|
||||
#if (USBDCORE_ENABLE_LOW_POWER == 1)
|
||||
#define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE)
|
||||
#else
|
||||
#define USBDCore_LowPower(...)
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* USB Interrupt Enable */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <h> USB Interrupt Setting (UIER)
|
||||
// <o0.0> USB Global Interrupt Enable (UGIE) (Default)
|
||||
// <o0.1> Start Of Frame Interrupt Enable (SOFIE)
|
||||
// <o0.2> USB Reset Interrupt Enable (URSTIE) (Default)
|
||||
// <o0.3> Resume Interrupt Enable (RSMIE) (Default)
|
||||
// <o0.4> Suspend Interrupt Enable (SUSPIE) (Default)
|
||||
// <o0.5> Expected Start of Frame Interrupt Enable (ESOFE)
|
||||
// <o0.8> Control Endpoint Interrupt Enable (EP0IE) (Default)
|
||||
// <o0.9> Endpoint1 Interrupt Enable (EP1IE)
|
||||
// <o0.10> Endpoint2 Interrupt Enable (EP2IE)
|
||||
// <o0.11> Endpoint3 Interrupt Enable (EP3IE)
|
||||
// <o0.12> Endpoint4 Interrupt Enable (EP4IE)
|
||||
// <o0.13> Endpoint5 Interrupt Enable (EP5IE)
|
||||
// <o0.14> Endpoint6 Interrupt Enable (EP6IE)
|
||||
// <o0.15> Endpoint7 Interrupt Enable (EP7IE)
|
||||
// <o0.16> Endpoint8 Interrupt Enable (EP8IE)
|
||||
// <o0.17> Endpoint9 Interrupt Enable (EP9IE)
|
||||
#define _UIER (0x011D)
|
||||
// </h>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint0 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <h> Control Endpoint0 Configuration
|
||||
// <o0> Endpoint Buffer Length (EPLEN)
|
||||
// <8=> 8 bytes
|
||||
// <16=> 16 bytes
|
||||
// <32=> 32 bytes
|
||||
// <64=> 64 bytes
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP0LEN (64)
|
||||
|
||||
|
||||
// <h> Control Endpoint0 Interrupt Enable Settings (EP0IER)
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE) (Default)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
// <o0.8> SETUP Token Packet Received Interrupt Enable (STRXIE)
|
||||
// <o0.9> SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default)
|
||||
// <o0.10> SETUP Data Error Interrupt Enable (SDERIE)
|
||||
// <o0.11> Zero Length Data Packet Received Interrupt Enable (ZLRXIE)
|
||||
#define _EP0_IER (0x212)
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint1 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint1 Configuration
|
||||
#define _EP1_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
#define _EP1_CFG_EPADR (1)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP1_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP1_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP1_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP1LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP1_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint2 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint2 Configuration
|
||||
#define _EP2_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
#define _EP2_CFG_EPADR (2)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP2_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP2_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP2_CFG_EPDIR (0)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP2LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP2_IER (0x002)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint3 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint3 Configuration
|
||||
#define _EP3_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
#define _EP3_CFG_EPADR (3)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP3_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP3_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP3_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP3LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP3_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint4 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint4 Configuration
|
||||
#define _EP4_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
#define _EP4_CFG_EPADR (4)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP4_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP4_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP4_CFG_EPDIR (0)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP4LEN_TMP (8)
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP4_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP4_IER (0x02)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint5 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint5 Configuration
|
||||
#define _EP5_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
#define _EP5_CFG_EPADR (5)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP5_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP5_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP5_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP5LEN_TMP (8)
|
||||
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP5_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP5_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint6 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint6 Configuration
|
||||
#define _EP6_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
#define _EP6_CFG_EPADR (6)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP6_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP6_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP6_CFG_EPDIR (0)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP6LEN_TMP (8)
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP6_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP6_IER (0x02)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint7 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint7 Configuration
|
||||
#define _EP7_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
#define _EP7_CFG_EPADR (7)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP7_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <1=> Isochronous
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP7_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP7_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
|
||||
/* Maximum: 1000 Bytes */
|
||||
#define _EP7LEN_TMP (8)
|
||||
|
||||
// <o0> Single/Double Buffer Selection (SDBS)
|
||||
// <0=> Single Buffer
|
||||
// <1=> Double Buffer
|
||||
#define _EP7_CFG_SDBS (0)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP7_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint8 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint8 Configuration
|
||||
#define _EP8_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
#define _EP8_CFG_EPADR (8)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP8_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP8_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP8_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP8LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP8_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Endpoint9 Configuration Setting */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
// <e0> Endpoint9 Configuration
|
||||
#define _EP9_ENABLE (0)
|
||||
|
||||
// <o0> Endpoint Address (EPADR)
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
#define _EP9_CFG_EPADR (9)
|
||||
|
||||
// <o0.0> Endpoint Enable (EPEN)
|
||||
#define _EP9_CFG_EPEN_TMP (1)
|
||||
|
||||
// <o0> Endpoint Transfer Type
|
||||
// <2=> Bulk
|
||||
// <3=> Interrupt
|
||||
#define _EP9_TYPR (3)
|
||||
|
||||
// <o0> Endpoint Direction (EPDIR)
|
||||
// <1=> IN
|
||||
// <0=> OUT
|
||||
#define _EP9_CFG_EPDIR (1)
|
||||
|
||||
// <o0> Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
|
||||
/* Maximum: 64 Bytes */
|
||||
#define _EP9LEN_TMP (8)
|
||||
|
||||
// <h> Endpoint Interrupt Enable Settings (EPIER)
|
||||
// <o0> Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
|
||||
// <o0.0> OUT Token Packet Received Interrupt Enable (OTRXIE)
|
||||
// <o0.1> OUT Data Packet Received Interrupt Enable (ODRXIE)
|
||||
// <o0.2> OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
|
||||
// <o0.3> IN Token Packet Received Interrupt Enable (ITRXIE)
|
||||
// <o0.4> IN Data Packet Transmitted Interrupt Enable (IDTXIE)
|
||||
// <o0.5> NAK Transmitted Interrupt Enable (NAKIE)
|
||||
// <o0.6> STALL Transmitted Interrupt Enable (STLIE)
|
||||
// <o0.7> USB Error Interrupt Enable (UERIE)
|
||||
#define _EP9_IER (0x10)
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,556 @@
|
|||
/*********************************************************************************************************//**
|
||||
* @file IP/Example/ht32f5xxxx_conf.h
|
||||
* @version $Rev:: 7109 $
|
||||
* @date $Date:: 2023-08-10 #$
|
||||
* @brief Library configuration file.
|
||||
*************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Firmware Disclaimer Information
|
||||
*
|
||||
* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
|
||||
* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
|
||||
* other intellectual property laws.
|
||||
*
|
||||
* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
|
||||
* other than HOLTEK and the customer.
|
||||
*
|
||||
* 3. The program technical documentation, including the code, is provided "as is" and for customer reference
|
||||
* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
|
||||
* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
|
||||
* the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
|
||||
*
|
||||
* <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2>
|
||||
************************************************************************************************************/
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
|
||||
#ifndef __HT32F5XXXX_CONF_H
|
||||
#define __HT32F5XXXX_CONF_H
|
||||
|
||||
/* Exported constants --------------------------------------------------------------------------------------*/
|
||||
|
||||
#define RETARGET_USB 1
|
||||
#define RETARGET_SYSLOG 2
|
||||
#define RETARGET_COM1 10
|
||||
#define RETARGET_COM2 11
|
||||
#define RETARGET_USART0 12
|
||||
#define RETARGET_USART1 13
|
||||
#define RETARGET_UART0 14
|
||||
#define RETARGET_UART1 15
|
||||
#define RETARGET_UART2 16
|
||||
#define RETARGET_UART3 17
|
||||
|
||||
|
||||
/* Retarget settings of the C standard I/O library functions (printf, scanf, getchar, ...etc.) */
|
||||
/*
|
||||
// <q> Enable Retarget
|
||||
// <o1> Retarget Port
|
||||
// <1=> USB Virtual COM
|
||||
// <2=> Syslog
|
||||
// <10=> COM1
|
||||
// <11=> COM2
|
||||
// <12=> USART0
|
||||
// <13=> USART1
|
||||
// <14=> UART0
|
||||
// <15=> UART1
|
||||
// <16=> UART2
|
||||
// <17=> UART3
|
||||
// <q2> Enable Auto Return
|
||||
// <i> Auto Return function adds "\r" before "\n" automatically when print message by Retarget.
|
||||
*/
|
||||
#define _RETARGET 1
|
||||
#define RETARGET_PORT 10
|
||||
#define _AUTO_RETURN 0
|
||||
|
||||
#ifndef AUTO_RETURN
|
||||
#if (_AUTO_RETURN == 1)
|
||||
#define AUTO_RETURN
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Enable Interrupt Mode for UxART Retarget
|
||||
// <h> Retarget COM/UxART Setting
|
||||
// <o0> UxART Baudrate
|
||||
// <q1> Enable Interrupt Mode for UxART Tx Retarget
|
||||
// <q2> Define UxARTn_IRQHandler By Retarget (ht32_serial.c)
|
||||
// <i> Disable (RETARGET_DEFINE_HANDLER = 0) if application already have UxARTn_IRQHandler.
|
||||
// <i> RETARGET_UART_IRQHandler() shall be called by UxARTn_IRQHandler when disable.
|
||||
// <o3> Tx Buffer Length (in byte)
|
||||
// </h>
|
||||
*/
|
||||
#define RETARGET_UxART_BAUDRATE 115200
|
||||
#define RETARGET_INT_MODE 0
|
||||
#define RETARGET_DEFINE_HANDLER 1
|
||||
#define RETARGET_INT_BUFFER_SIZE 64
|
||||
|
||||
#if (_RETARGET == 1)
|
||||
#if (RETARGET_PORT == RETARGET_USB)
|
||||
#define RETARGET_IS_USB
|
||||
// <h> Retarget USB Virtual COM Setting
|
||||
// <o0> Communication (Interrupt IN)
|
||||
// <1=> Endpoint 1
|
||||
// <2=> Endpoint 2
|
||||
// <3=> Endpoint 3
|
||||
// <4=> Endpoint 4
|
||||
// <5=> Endpoint 5
|
||||
// <6=> Endpoint 6
|
||||
// <7=> Endpoint 7
|
||||
// <o1> Data Rx (Bulk OUT)
|
||||
// <1=> Endpoint 1
|
||||
// <2=> Endpoint 2
|
||||
// <3=> Endpoint 3
|
||||
// <4=> Endpoint 4
|
||||
// <5=> Endpoint 5
|
||||
// <6=> Endpoint 6
|
||||
// <7=> Endpoint 7
|
||||
// <o2> Data Tx (Bulk IN)
|
||||
// <1=> Endpoint 1
|
||||
// <2=> Endpoint 2
|
||||
// <3=> Endpoint 3
|
||||
// <4=> Endpoint 4
|
||||
// <5=> Endpoint 5
|
||||
// <6=> Endpoint 6
|
||||
// <7=> Endpoint 7
|
||||
// <o3> Communication Endpoint Buffer Length (in byte) <4-64:4>
|
||||
// <o4> Data Rx Endpoint Buffer Length (in byte) <4-64:4>
|
||||
// <o5> Data Tx Endpoint Buffer Length (in byte) <4-64:4>
|
||||
// <o6> Rx Buffer Length (in byte) <64-1024:4>
|
||||
// <o7> Tx Buffer Length (in byte) <1-63:1>
|
||||
// <i> Please use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1.
|
||||
// <o8> USB Tx Mode (BULK IN)
|
||||
// <0=> Block Mode (Wait until both USB and terminal software are ready)
|
||||
// <1=> Non-Block Mode (Drop data if USB or terminal software is not ready)
|
||||
// <q9> Enable HSI Auto Trim By USB Function
|
||||
// <i> Need turn on if the USB clock source is from HSI (PLL USBPLL clock Source).
|
||||
#define RETARGET_CTRL_EPT (5)
|
||||
#define RETARGET_RX_EPT (6)
|
||||
#define RETARGET_TX_EPT (7)
|
||||
#define RETARGET_CTRL_EPTLEN (8)
|
||||
#define RETARGET_RX_EPTLEN (64)
|
||||
#define RETARGET_TX_EPTLEN (64)
|
||||
#define RETARGET_BUFFER_SIZE (64)
|
||||
#define RETARGET_TXBUFFER_SIZE (1) // Use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1.
|
||||
#define RETARGET_USB_MODE (0)
|
||||
#define RETARGET_HSI_ATM (1)
|
||||
// </h>
|
||||
#elif (RETARGET_PORT == RETARGET_COM1)
|
||||
#define RETARGET_COM_PORT COM1
|
||||
#define RETARGET_USART_PORT COM1_PORT
|
||||
#define RETARGET_UART_IRQn COM1_IRQn
|
||||
#define RETARGET_UART_IRQHandler COM1_IRQHandler
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_COM2)
|
||||
#define RETARGET_COM_PORT COM2
|
||||
#define RETARGET_USART_PORT COM2_PORT
|
||||
#define RETARGET_UART_IRQn COM2_IRQn
|
||||
#define RETARGET_UART_IRQHandler COM2_IRQHandler
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_USART0)
|
||||
#define RETARGET_UxART_IPN USART0
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_USART1)
|
||||
#define RETARGET_UxART_IPN USART1
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_UART0)
|
||||
#define RETARGET_UxART_IPN UART0
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_UART1)
|
||||
#define RETARGET_UxART_IPN UART1
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_UART2)
|
||||
#define RETARGET_UxART_IPN UART2
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#elif (RETARGET_PORT == RETARGET_UART3)
|
||||
#define RETARGET_UxART_IPN UART3
|
||||
#define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
|
||||
#define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
|
||||
#define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
|
||||
#define RETARGET_IS_UART
|
||||
#endif
|
||||
extern void RETARGET_Configuration(void);
|
||||
#else
|
||||
#define RETARGET_Configuration(...)
|
||||
#undef printf
|
||||
#undef getchar
|
||||
#define printf(...)
|
||||
#define getchar() (0)
|
||||
#endif
|
||||
|
||||
#if (RETARGET_DEFINE_HANDLER == 0)
|
||||
#undef RETARGET_UART_IRQHandler
|
||||
#endif
|
||||
|
||||
/*
|
||||
//<e0> Enable HT32 Time Function
|
||||
// <i> Provide "Time_GetTick()" and "Time_Dealy()" functions.
|
||||
|
||||
// <o1> Timer Selection
|
||||
// <0=> BFTM0
|
||||
// <1=> BFTM1
|
||||
// <2=> SCTM0
|
||||
// <3=> SCTM1
|
||||
// <4=> SCTM2
|
||||
// <5=> SCTM3
|
||||
// <6=> PWM0
|
||||
// <7=> PWM1
|
||||
// <8=> PWM2
|
||||
// <9=> GPTM0
|
||||
// <10=> GPTM1
|
||||
// <11=> MCTM0
|
||||
|
||||
// <h> Timer Clock Setting
|
||||
// </h>
|
||||
// <i> Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler)
|
||||
// <i> HTCFG_TIME_CLKSRC = _HTCFG_TIME_CORECLK / (2^HTCFG_TIME_PCLK_DIV)
|
||||
// <i> _HTCFG_TIME_CORECLK = LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL)
|
||||
|
||||
// <o2> -- Core Clock Setting (CK_AHB)
|
||||
// <i> HTCFG_TIME_CLKSEL
|
||||
// <i> 0 = Default Maximum (LIBCFG_MAX_SPEED)
|
||||
// <i> 1 = Manual Input (HTCFG_TIME_CLK_MANUAL)
|
||||
// <0=> Default Maximum (LIBCFG_MAX_SPEED)
|
||||
// <1=> Manual Input (HTCFG_TIME_CLK_MANUAL)
|
||||
|
||||
// <o3> -- Core Clock Manual Input (Hz)
|
||||
// <i> HTCFG_TIME_CLK_MANUAL
|
||||
// <i> Only meaningful when Core Clock Setting (HTCFG_TIME_CLKSEL) = Manual Input (1)
|
||||
|
||||
// <o4> -- APB Peripheral Clock Prescaler
|
||||
// <i> HTCFG_TIME_PCLK_DIV
|
||||
// <0=> /1
|
||||
// <1=> /2
|
||||
// <2=> /4
|
||||
// <3=> /8
|
||||
|
||||
// <o5> Time Tick (Hz, not applicable for BFTM) <1-1000000:100>
|
||||
// <i> Not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM.
|
||||
*/
|
||||
#if (0) // Enable HT32 Time Function
|
||||
#define HTCFG_TIME_IPSEL (0)
|
||||
#define HTCFG_TIME_CLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_TIME_CLKSRC)
|
||||
#define HTCFG_TIME_CLK_MANUAL (20000000) // Only meaningful when HTCFG_TIME_CLKSEL = 1 (Manual Input)
|
||||
#define HTCFG_TIME_PCLK_DIV (0) // 0 ~ 3. (/1, /2, /4, /8)
|
||||
#define HTCFG_TIME_TICKHZ (1000) // Hz, not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM
|
||||
#define HTCFG_TIME_MULTIPLE (1) // MUST be 1, 2, 4, 8. TICK = COUNT / MULTIPLE. Not applicable for BFTM.
|
||||
/*
|
||||
|
||||
Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler)
|
||||
HTCFG_TIME_CLKSRC = (_HTCFG_TIME_CORECLK) / (2^HTCFG_TIME_PCLK_DIV)
|
||||
where _HTCFG_TIME_CORECLK can be LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL)
|
||||
|
||||
Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time)
|
||||
Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second
|
||||
(Interrupt Time is not applicable for BFTM)
|
||||
|
||||
Example: 32-bit BFTM with 48 MHz Timer Clock
|
||||
HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000
|
||||
Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second)
|
||||
BFTM do not use interrupt
|
||||
|
||||
Example: 16-bit GPTM with 1 ms tick
|
||||
HTCFG_TIME_TICKHZ = 1000 (Hz)
|
||||
HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick)
|
||||
Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day)
|
||||
Interrupt Time: 65536 / (1000 * 1) = 65.536 Second (Trigger interrupt every 65.536 Second)
|
||||
*/
|
||||
#endif
|
||||
/*
|
||||
//</e>
|
||||
*/
|
||||
|
||||
/* !!! NOTICE !!!
|
||||
* How to adjust the value of High Speed External oscillator (HSE)?
|
||||
The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h".
|
||||
If your board uses a different HSE speed, please add a new compiler preprocessor
|
||||
C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE,
|
||||
or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file (this file).
|
||||
*/
|
||||
/*
|
||||
//<e0> Enable User Define HSE Value
|
||||
// <i> Enable user define HSE value to overwrite default "HSE_VALUE" define in "ht32fxxxxx_nn.h".
|
||||
// <o1> HSE Value (Hz)
|
||||
*/
|
||||
#if (0)
|
||||
#define HSE_VALUE 16000000
|
||||
#endif
|
||||
/*
|
||||
//</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
//<q> Enable CKOUT Function
|
||||
*/
|
||||
#define ENABLE_CKOUT 0
|
||||
|
||||
/*
|
||||
//<q> Enable Get CK_ADC of "CKCU_GetClocksFrequency()"
|
||||
//<i> Enable ADC0_Freq and ADC1_Freq of the "CKCU_GetClocksFrequency()" function. It required the division calculation (by C Library) and increased the code size.
|
||||
*/
|
||||
#define HT32_LIB_ENABLE_GET_CK_ADC 0
|
||||
|
||||
/* The DEBUG definition to enter debug mode for library */
|
||||
/*
|
||||
//<q> Library Debug Mode
|
||||
*/
|
||||
#define HT32_LIB_DEBUG 0
|
||||
|
||||
|
||||
/* Enable/disable the specific peripheral inclusion */
|
||||
|
||||
// <h> Library Inclusion Configuration
|
||||
/* ADC -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> ADC Library
|
||||
*/
|
||||
#define _ADC 1
|
||||
|
||||
/* AES -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> AES Library
|
||||
*/
|
||||
#define _AES 1
|
||||
|
||||
/* BFTM ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> BFTM Library
|
||||
*/
|
||||
#define _BFTM 1
|
||||
|
||||
/* CAN -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> CAN Library
|
||||
*/
|
||||
#define _CAN 1
|
||||
|
||||
/* Clock Control -------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Clock Control Library
|
||||
*/
|
||||
#define _CKCU 1
|
||||
|
||||
/* Comparator ----------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Comparator Library
|
||||
*/
|
||||
#define _CMP 1
|
||||
|
||||
/* CRC -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> CRC Library
|
||||
*/
|
||||
#define _CRC 1
|
||||
|
||||
/* DAC -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> DAC Library
|
||||
*/
|
||||
#define _DAC 1
|
||||
|
||||
/* DAC Dual 16-bit -----------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> DAC_Dual16 Library
|
||||
*/
|
||||
#define _DAC_DUAL16 1
|
||||
|
||||
/* DIV -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> DIV Library
|
||||
*/
|
||||
#define _DIV 1
|
||||
|
||||
/* EBI -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> EBI Library
|
||||
*/
|
||||
#define _EBI 1
|
||||
|
||||
/* EXTI ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> EXTI Library
|
||||
*/
|
||||
#define _EXTI 1
|
||||
|
||||
/* Flash ---------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Flash Library
|
||||
*/
|
||||
#define _FLASH 1
|
||||
|
||||
/* GPIO ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> GPIO Library
|
||||
*/
|
||||
#define _GPIO 1
|
||||
|
||||
/* GPTM ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> GPTM Library
|
||||
*/
|
||||
#define _GPTM 1
|
||||
|
||||
/* I2C -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> I2C Library
|
||||
*/
|
||||
#define _I2C 1
|
||||
|
||||
/* I2S -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> I2S Library
|
||||
*/
|
||||
#define _I2S 1
|
||||
|
||||
/* LCD -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> LCD Library
|
||||
*/
|
||||
#define _LCD 1
|
||||
|
||||
/* LEDC ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> LEDC Library
|
||||
*/
|
||||
#define _LEDC 1
|
||||
|
||||
/* MCTM ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> MCTM Library
|
||||
*/
|
||||
#define _MCTM 1
|
||||
|
||||
/* MIDI ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> MIDI Library
|
||||
*/
|
||||
#define _MIDI 1
|
||||
|
||||
/* OPA -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> OPA
|
||||
*/
|
||||
#define _OPA 1
|
||||
|
||||
/* PDMA ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> PDMA Library
|
||||
*/
|
||||
#define _PDMA 1
|
||||
|
||||
/* PWM -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> PWM Library
|
||||
*/
|
||||
#define _PWM 1
|
||||
|
||||
/* PWRCU ---------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> PWRCU Library
|
||||
*/
|
||||
#define _PWRCU 1
|
||||
|
||||
/* RSTCU ---------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> RSTCU Library
|
||||
*/
|
||||
#define _RSTCU 1
|
||||
|
||||
/* RTC -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> RTC Library
|
||||
*/
|
||||
#define _RTC 1
|
||||
|
||||
/* SCI -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> SCI Library
|
||||
*/
|
||||
#define _SCI 1
|
||||
|
||||
/* SCTM ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> SCTM Library
|
||||
*/
|
||||
#define _SCTM 1
|
||||
|
||||
/* SLED ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> SLED Library
|
||||
*/
|
||||
#define _SLED 1
|
||||
|
||||
/* SPI -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> SPI Library
|
||||
*/
|
||||
#define _SPI 1
|
||||
|
||||
/* TKEY ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> TKEY Library
|
||||
*/
|
||||
#define _TKEY 1
|
||||
|
||||
/* USART ---------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q0> USART/UART Library
|
||||
*/
|
||||
#define _USART 1
|
||||
|
||||
/* USBD ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> USB Library
|
||||
*/
|
||||
#define _USB 1
|
||||
|
||||
/* WDT -----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> WDT Library
|
||||
*/
|
||||
#define _WDT 1
|
||||
|
||||
/* Misc ----------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Misc Library
|
||||
*/
|
||||
#define _MISC 1
|
||||
|
||||
/* Serial --------------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Serial Library
|
||||
*/
|
||||
#define _SERIAL 1
|
||||
|
||||
/* Software DIV --------------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Software Divider Library
|
||||
*/
|
||||
#define _SWDIV 1
|
||||
|
||||
/* Software Random Number ----------------------------------------------------------------------------------*/
|
||||
/*
|
||||
//<q> Software Random Number Library
|
||||
*/
|
||||
#define _SWRAND 1
|
||||
|
||||
|
||||
// </h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x0400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, last block CSTACK};
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* linker script for AT32 with GNU ld
|
||||
*/
|
||||
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
|
||||
RAM (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */
|
||||
}
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x200;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
_etext = .;
|
||||
} > ROM = 0
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = .;
|
||||
} > ROM
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >RAM
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sstack = .;
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >RAM
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > RAM
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x0001FE00 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x0001FE00 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00004000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-08 QT-one first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
/* This feature will initialize the HT32 chip clock */
|
||||
void rt_hw_board_clock_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-08 QT-one first version
|
||||
*/
|
||||
|
||||
#include "ht32_msp.h"
|
||||
|
||||
/* GPIO configuration for UART */
|
||||
#ifdef BSP_USING_UART
|
||||
void ht32_usart_gpio_init(void *instance)
|
||||
{
|
||||
CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
|
||||
HT_USART_TypeDef *usart_x = (HT_USART_TypeDef *)instance;
|
||||
#ifdef BSP_USING_USART0
|
||||
if (HT_USART0 == usart_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_USART0_TX_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_USART0_RX_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock, ENABLE);
|
||||
/* Turn on UxART Rx internal pull up resistor to prevent unknow state */
|
||||
GPIO_PullResistorConfig(HTCFG_USART0_RX_GPIO_PORT, HTCFG_USART0_RX_GPIO_PIN, GPIO_PR_UP);
|
||||
/* Config AFIO mode as UxART function */
|
||||
AFIO_GPxConfig(HTCFG_USART0_TX_GPIO_ID, HTCFG_USART0_TX_GPIO_PIN, AFIO_FUN_USART_UART);
|
||||
AFIO_GPxConfig(HTCFG_USART0_RX_GPIO_ID, HTCFG_USART0_RX_GPIO_PIN, AFIO_FUN_USART_UART);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_USART1
|
||||
if (HT_USART1 == usart_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_USART1_TX_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_USART1_RX_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock, ENABLE);
|
||||
/* Turn on UxART Rx internal pull up resistor to prevent unknow state */
|
||||
GPIO_PullResistorConfig(HTCFG_USART1_RX_GPIO_PORT, HTCFG_USART1_RX_GPIO_PIN, GPIO_PR_UP);
|
||||
/* Config AFIO mode as UxART function */
|
||||
AFIO_GPxConfig(HTCFG_USART1_TX_GPIO_ID, HTCFG_USART1_TX_GPIO_PIN, AFIO_FUN_USART_UART);
|
||||
AFIO_GPxConfig(HTCFG_USART1_RX_GPIO_ID, HTCFG_USART1_RX_GPIO_PIN, AFIO_FUN_USART_UART);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_UART0
|
||||
if (HT_UART0 == usart_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_UART0_TX_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_UART0_RX_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock, ENABLE);
|
||||
/* Turn on UxART Rx internal pull up resistor to prevent unknow state */
|
||||
GPIO_PullResistorConfig(HTCFG_UART0_RX_GPIO_PORT, HTCFG_UART0_RX_GPIO_PIN, GPIO_PR_UP);
|
||||
/* Config AFIO mode as UxART function */
|
||||
AFIO_GPxConfig(HTCFG_UART0_TX_GPIO_ID, HTCFG_UART0_TX_GPIO_PIN, AFIO_FUN_USART_UART);
|
||||
AFIO_GPxConfig(HTCFG_UART0_RX_GPIO_ID, HTCFG_UART0_RX_GPIO_PIN, AFIO_FUN_USART_UART);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_UART1
|
||||
if (HT_UART1 == usart_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_UART1_TX_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_UART1_RX_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock, ENABLE);
|
||||
/* Turn on UxART Rx internal pull up resistor to prevent unknow state */
|
||||
GPIO_PullResistorConfig(HTCFG_UART1_RX_GPIO_PORT, HTCFG_UART1_RX_GPIO_PIN, GPIO_PR_UP);
|
||||
/* Config AFIO mode as UxART function */
|
||||
AFIO_GPxConfig(HTCFG_UART1_TX_GPIO_ID, HTCFG_UART1_TX_GPIO_PIN, AFIO_FUN_USART_UART);
|
||||
AFIO_GPxConfig(HTCFG_UART1_RX_GPIO_ID, HTCFG_UART1_RX_GPIO_PIN, AFIO_FUN_USART_UART);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/* GPIO configuration for SPI */
|
||||
#ifdef BSP_USING_SPI
|
||||
void ht32_spi_gpio_init(void *instance)
|
||||
{
|
||||
CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
|
||||
HT_SPI_TypeDef *spi_x = (HT_SPI_TypeDef *)instance;
|
||||
#ifdef BSP_USING_SPI0
|
||||
if (HT_SPI0 == spi_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_SPI0_SCK_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_SPI0_MISO_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_SPI0_MOSI_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock, ENABLE);
|
||||
|
||||
AFIO_GPxConfig(HTCFG_SPI0_SCK_GPIO_ID, HTCFG_SPI0_SCK_GPIO_PIN, AFIO_FUN_SPI);
|
||||
AFIO_GPxConfig(HTCFG_SPI0_MISO_GPIO_ID, HTCFG_SPI0_MISO_GPIO_PIN, AFIO_FUN_SPI);
|
||||
AFIO_GPxConfig(HTCFG_SPI0_MOSI_GPIO_ID, HTCFG_SPI0_MOSI_GPIO_PIN, AFIO_FUN_SPI);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI1
|
||||
if (HT_SPI1 == spi_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_SPI1_SCK_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_SPI1_MISO_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_SPI1_MOSI_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock, ENABLE);
|
||||
|
||||
AFIO_GPxConfig(HTCFG_SPI1_SCK_GPIO_ID, HTCFG_SPI1_SCK_GPIO_PIN, AFIO_FUN_SPI);
|
||||
AFIO_GPxConfig(HTCFG_SPI1_MISO_GPIO_ID, HTCFG_SPI1_MISO_GPIO_PIN, AFIO_FUN_SPI);
|
||||
AFIO_GPxConfig(HTCFG_SPI1_MOSI_GPIO_ID, HTCFG_SPI1_MOSI_GPIO_PIN, AFIO_FUN_SPI);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/* GPIO configuration for I2C */
|
||||
#ifdef BSP_USING_I2C
|
||||
void ht32_i2c_gpio_init(void *instance)
|
||||
{
|
||||
CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
|
||||
HT_I2C_TypeDef *i2c_x = (HT_I2C_TypeDef *)instance;
|
||||
#ifdef BSP_USING_I2C0
|
||||
if (HT_I2C0 == i2c_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_I2C0_SCL_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_I2C0_SDA_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock, ENABLE);
|
||||
/* Configure GPIO to I2C mode */
|
||||
AFIO_GPxConfig(HTCFG_I2C0_SCL_GPIO_ID, HTCFG_I2C0_SCL_GPIO_PIN, AFIO_FUN_I2C);
|
||||
AFIO_GPxConfig(HTCFG_I2C0_SDA_GPIO_ID, HTCFG_I2C0_SDA_GPIO_PIN, AFIO_FUN_I2C);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_I2C1
|
||||
if (HT_I2C1 == i2c_x)
|
||||
{
|
||||
CKCUClock.Bit.HTCFG_I2C1_SCL_GPIO_CLK = 1;
|
||||
CKCUClock.Bit.HTCFG_I2C1_SDA_GPIO_CLK = 1;
|
||||
CKCU_PeripClockConfig(CKCUClock, ENABLE);
|
||||
/* Configure GPIO to I2C mode */
|
||||
AFIO_GPxConfig(HTCFG_I2C1_SCL_GPIO_ID, HTCFG_I2C1_SCL_GPIO_PIN, AFIO_FUN_I2C);
|
||||
AFIO_GPxConfig(HTCFG_I2C1_SDA_GPIO_ID, HTCFG_I2C1_SDA_GPIO_PIN, AFIO_FUN_I2C);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 373 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,271 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_MEMHEAP
|
||||
#define RT_MEMHEAP_FAST_MODE
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "usart1"
|
||||
#define RT_VER_NUM 0x50100
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_M
|
||||
#define ARCH_ARM_CORTEX_M0
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_SPI
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
|
||||
/* Network */
|
||||
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
|
||||
/* AI packages */
|
||||
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
|
||||
/* Sensors */
|
||||
|
||||
|
||||
/* Display */
|
||||
|
||||
|
||||
/* Timing */
|
||||
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
|
||||
/* Device Control */
|
||||
|
||||
|
||||
/* Other */
|
||||
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
#define SOC_FAMILY_HT32
|
||||
#define SOC_SERIES_HT32F5
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_HT32F52352
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_USART1
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m0'
|
||||
CROSS_TOOL='keil'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
# EXEC_PATH = r'D:\keil5\keil_v532\UV4'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M0 '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M0'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=None'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M0'
|
||||
AFLAGS += ' --fpu None'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<nTsel>2</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,392 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>HT32F52352</Device>
|
||||
<Vendor>Holtek</Vendor>
|
||||
<PackID>Holtek.HT32_DFP.1.0.19</PackID>
|
||||
<PackURL>http://mcu.holtek.com.tw/pack</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x4000) IROM(0x00000000,0x1FE00) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:HT32F52352$ARM\INC\Holtek\HT32F5xxxx\ht32f5xxxx_01.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:HT32F52352$SVD\HT32F52342_52.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
|
||||
<OutputName>rt-thread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> </TargetDllArguments>
|
||||
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>0</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M0+"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x4000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x1fe00</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x1fe00</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x4000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>USE_HT32_CHIP=4</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
# files format check exclude path, please follow the instructions below to modify;
|
||||
# If you need to exclude an entire folder, add the folder path in dir_path;
|
||||
# If you need to exclude a file, add the path to the file in file_path.
|
||||
|
||||
dir_path:
|
||||
- HT32_STD_1xxxx_FWLib
|
||||
- HT32_STD_5xxxx_FWLib
|
||||
|
|
@ -0,0 +1,876 @@
|
|||
/*********************************************************************************************************//**
|
||||
* @file Release_Notes.txt
|
||||
* @version V1.4.1
|
||||
* @date 2023-10-31
|
||||
* @brief The Release notes of HT32 Firmware Library.
|
||||
*************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Firmware Disclaimer Information
|
||||
*
|
||||
* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
|
||||
* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
|
||||
* other intellectual property laws.
|
||||
*
|
||||
* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
|
||||
* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
|
||||
* other than HOLTEK and the customer.
|
||||
*
|
||||
* 3. The program technical documentation, including the code, is provided "as is" and for customer reference
|
||||
* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
|
||||
* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
|
||||
* the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
|
||||
*
|
||||
* <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2>
|
||||
************************************************************************************************************/
|
||||
|
||||
// Supported Device
|
||||
// ========================================
|
||||
// HT32F1653, HT32F1654
|
||||
// HT32F1655, HT32F1656
|
||||
// HT32F12345
|
||||
// HT32F12364
|
||||
// HT32F12365, HT32F12366
|
||||
// HT32F22366
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_V1.4.1_2982 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2023-10-31
|
||||
|
||||
Main Changes
|
||||
+ Add new example.
|
||||
- "GPIO/PinLock"
|
||||
+ Modify examples below, add volatile qualifiers on some variables (in the for loop usage)
|
||||
to fix the Arm Compiler Version 6 optimization issue.
|
||||
("u32" to "vu32", unsigned int to volatile unsigned int).
|
||||
- “PWRCU/PowerDown_WAKEUPPin”
|
||||
- “PWRCU/PowerDown_RTC”
|
||||
- “TM/PWM”
|
||||
+ Modify examples below, use separate "if" statements instead of "if-else" to avoid double-entry ISR.
|
||||
- "PWRCU/DeepSleepMode1"
|
||||
- "PWRCU/DeepSleepMode2"
|
||||
+ Modify "ht32_time.h", "ht32f1xxxx_conf.h" and "ht32_time_conf.h" for "LIBCFG_CKCU_NO_APB_PRESCALER" series.
|
||||
- To ensure the correct configuration of the timer clock, the "HTCFG_TIME_PCLK_DIV" is redefined as 0.
|
||||
+ Add "Project or Target File Clearing" functions ("_ClearProject.bat" and "_ClearTarget.bat").
|
||||
+ Modify "syscall.c" to prevent redundant initialization of the heap index.
|
||||
+ Modify "ht32f1xxxx_01.h" to add below definition.
|
||||
- "sc64", "vs64", "vsc64", "uc64", "vu64", "vuc64"
|
||||
+ Modify PWRCU related define (The left side old one is still kept for backward compatible).
|
||||
- PWRCU_FLAG_BAKPOR -> PWRCU_FLAG_PWRPOR
|
||||
+ Modify "RETARGET_Configuration()", add the operation of UxARTn peripheral clock enable.
|
||||
+ Update and sync "ht32f1xxxx_conf.h", modify related define of UxARTn retarget port.
|
||||
+ Update "ht32_op.c" and "ht32_op.s" to support new version of bootloader waiting time setting address.
|
||||
(The setting address is changed from 0x1FF0002C to 0x1FF0004C)
|
||||
+ Add "ht32_op_V107.c" and "ht32_op_V107.s" to support the use of older versions of bootloader.
|
||||
+ Add "CKCU_ATCInit()" API for HSI Auto Trim initial function.
|
||||
+ Update "ht32f1xxxx_adc.c" and "ht32f1xxxx_adc_02.c", modify the ADC enable related flow.
|
||||
+ Add the below folder, For the BMduino shield/module Keil Driver.
|
||||
- "BestModules"
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Adjust "LIBCFG_xxxxx" definition below.
|
||||
- "LIBCFG_CKCU_APBCLKFIX" rename to "LIBCFG_CKCU_NO_APB_PRESCALER"
|
||||
+ Modify the Sourcery G++ Lite toolchain project.
|
||||
- Set C99 mode to fix issues after updating CMSIS v5.9.0 ("for" loop initial declarations).
|
||||
+ Update e-Link32 Pro/Lite Command line tool as "V1.19" ("utilities/elink32pro/eLink32pro.exe").
|
||||
+ Modify "_ProjectConfigScript.bat" to prevent the creation of project that copy unused system/startup files.
|
||||
+ Update "project_template/Script" for adding project C++ source files and setting the chip model mechanism.
|
||||
- The updated files are as follows:
|
||||
"Script/_ProjectSource.bat"
|
||||
"Script/_ProjectSource.ini"
|
||||
+ Update "project_template/Script" for improving script mechanism.
|
||||
- The updated files are as follows:
|
||||
"Script/_CreateProjectConfScript.bat"
|
||||
"Script/_CreateProjectScript.bat"
|
||||
"Script/_ht32_ic_name.ini"
|
||||
+ Modify and check the example supportability of each IC.
|
||||
+ Add the below file, for the BMduino shield.
|
||||
- "ht32_undef_IP.h"
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_V1.3.2_2858 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2023-02-02
|
||||
|
||||
Main Changes
|
||||
+ Add new examples:
|
||||
- "SRAM_Overwrite/Watchpoint_Heap"
|
||||
- "SRAM_Overwrite/Watchpoint_Stack"
|
||||
+ Update "ht32f1xxxx_conf.h" for user layer HSE_VALUE setting.
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Modify "system_ht32fxxxxx_nn.c", add HSE_VALUE notice and update PLL Out formula.
|
||||
+ Update and sync system.c files.
|
||||
+ Update EEPROM Emulation middleware, improve efficacy and reduce resource usage.
|
||||
"utilities/middleware/eeprom_emulation.c"
|
||||
"utilities/middleware/ht32_eeprom_config_templet.h"
|
||||
+ Update I2C Master middleware, improve setting way and fix minor errors.
|
||||
"utilities/middleware/i2c_master.c/.h"
|
||||
"utilities/middleware/i2c_master_config_templet.h"
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_V1.3.1_2808 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2022-12-01
|
||||
|
||||
Main Changes
|
||||
+ Update "ht32_time.h", fix a formula error of "TIME_TICK2US()" and "TIME_TICK2MS()" macro.
|
||||
+ Modify "ht32_retarget.c", fix retarget can't work when the MicroLIB is not used in Keil's V6 compiler.
|
||||
+ Modify "ht32_serial.c/.h" and "ht32_retarget.c", fix ITM setting issue.
|
||||
+ Update "ht32fxxxx_sk.h", add TRACESWO pin assignment for ITM.
|
||||
+ Update "SPI/PDMA" example, change the order of API execution (SPI_SELOutputCmd() execution before SPI_Cmd()).
|
||||
+ Update "CSIF/Init" example, modify the datatype form and add comments to explain the length of the Rx buffer.
|
||||
+ Update following I2C example. (sync. with M0+)
|
||||
- I2C/7_bit_mode
|
||||
- I2C/10_bit_mode
|
||||
- I2C/EEPROM_Simulate
|
||||
- I2C/Interrupt
|
||||
- I2C/PDMA
|
||||
+ GPIO
|
||||
- Add new define "GPIO_PIN_NUM_n" for GPIO pin number (n = 0 ~ 15).
|
||||
+ EXTI
|
||||
- Add "gEXTIn_IRQn[]" and "EXTI_GetIRQn()" macro to map GPIO pin number (0 ~ 15) to "EXTIn_IRQn".
|
||||
- Add "GPIO2EXTI()" macro to map GPIO pin to EXTI Channel.
|
||||
- Change "AFIO_EXTISourceConfig()" API, remove "AFIO_EXTI_CH_Enum" and "AFIO_ESS_Enum".
|
||||
Old: void AFIO_EXTISourceConfig(AFIO_EXTI_CH_Enum AFIO_EXTI_CH_n, AFIO_ESS_Enum AFIO_ESS_Px)
|
||||
New: void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px)
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Update "ht32_op.s/.c", allow "Bootloader Waiting Time" function for all series.
|
||||
+ Update "CKCU/HSI_AutoTrim_By_USB" example, add the following define to "ht32_board_config.h".
|
||||
- "CKCU_PLL_CFG"
|
||||
- "CKCU_SYSCLK_DIV_CFG"
|
||||
+ Upgrade CMSIS to v5.9.0.
|
||||
+ Modify API parameter check macro of Library Debug Mode, fix parameter check error.
|
||||
+ Modify variable declaration of "PDMACH_InitTypeDef" to reduce memory size.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_V1.2.1_2753 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2022-10-11
|
||||
|
||||
Main Changes
|
||||
+ Add new examples:
|
||||
- "I2C/7_bit_mode_master"
|
||||
- "I2C/7_bit_mode_slave"
|
||||
+ Add the following API for PDMA.
|
||||
- "PDMA_DeInit()"
|
||||
- "PDMA_AddrConfig()"
|
||||
- "PDMA_SrcAddrConfig()"
|
||||
- "PDMA_DstAddrConfig()"
|
||||
- "PDMA_GetRemainBlkCnt()"
|
||||
+ Add the following API for ADC.
|
||||
- "ADC_ChannelDataAlign()"
|
||||
- "ADC_ChannelOffsetValue()"
|
||||
- "ADC_ChannelOffsetCmd()"
|
||||
+ Update "ht32_retarget.c", modify the retarget related functions for SEGGER Embedded Studio.
|
||||
+ Update "FLASH_SetWaitState()" function, disable Pre-fetch and Branch Cache function before change
|
||||
wait state.
|
||||
+ Update following middleware.
|
||||
"utilities/middleware/i2c_master.c/h"
|
||||
"utilities/middleware/uart_module.c"
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Update "BFTM/OneShot" example, fix the register access sequence and time calculation formula.
|
||||
+ Update "TM/PWM/main.c"
|
||||
- Add "HTCFG_PWM_TM_RELOAD" check.
|
||||
- Add PWM channel initial function.
|
||||
- Remove "_ht32_project_source.h" (Use "_ProjectSource.ini" to add "pwm.c" into project compiling list).
|
||||
+ Fix the upper/lower case error of #include file name.
|
||||
+ Update e-Link32 Pro/Lite Command line tool as "V1.18" ("utilities/elink32pro/eLink32pro.exe").
|
||||
+ Change the project recommended minimum version of SEGGER Embedded Studio from V4.12 to V6.20.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_V1.1.1_2647 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2022-06-10
|
||||
|
||||
Main Changes
|
||||
+ Add following middleware.
|
||||
"utilities/middleware/spi_module.c"
|
||||
"utilities/middleware/spi_module.h"
|
||||
"utilities/middleware/spi_module_config_templet.h"
|
||||
+ Fixed FW library compatibility with ARM compiler version 6 of MDK-ARM V5.37.
|
||||
- Add MDK-ARMv537 project template for MDK-ARM V5.37.
|
||||
- Update "project_template/Script". Those MDK-ARMv537 project templates will be added for use if choose
|
||||
the target IDE is "Keil MDK-ARMv5". The fixed files are as follows:
|
||||
"Script/_CreateProjectScript.bat"
|
||||
"Script/_ProjectConfig.bat"
|
||||
"Script/_ProjectSource.bat"
|
||||
- Update "core_cm3.h", fix compiler error.
|
||||
- Update "FMC/FLASH_OperationNoHalt", fix the compiler issue of Arm Compiler Version V6.18 and the
|
||||
compiler warning of linker script file. The fixed files are as follows:
|
||||
"FLASH_OperationNoHalt/main.c"
|
||||
"FLASH_OperationNoHalt/linker.lin"
|
||||
- Update following middleware, remove STRCAT3 usage to fix compiler error.
|
||||
"utilities/middleware/uart_module.c"
|
||||
"utilities/middleware/i2c_master.c"
|
||||
"utilities/middleware/spi_module.c"
|
||||
+ Update "ht32_retarget.c". Implement __write function to fix compiler error in IAR EWARM Version 9.20
|
||||
or later.
|
||||
+ Update GNU Arm makefile in the project_template, fix the compatibility issue that the makefile of GNU Arm
|
||||
Version 11 cannot be compiled.
|
||||
+ Update EWARM in the project_template, fix the compiler error that header file path doesn't exist in
|
||||
the file list of Workspace of IAR EWARM Version 7.
|
||||
+ Fix SPI initial PDMA parameter in the "utilities/common/spi_flash.c".
|
||||
+ Sync M0+ I2C/EEPROM to fix compiler warning of the GNU compiler.
|
||||
+ Sync M0+ library\HT32F1xxxx_Driver\inc\ht32_dependency.h.
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Update e-Link32 Pro/Lite Command line tool as "V1.16" ("utilities/elink32pro/eLink32pro.exe").
|
||||
+ Update the following examples to remove compiler warning of the IAR EWARM.
|
||||
"BFTM\TimeMeasure"
|
||||
"TM\PWMInput\ht32f1xxxx_01_it.c"
|
||||
"USBD\HID_Keyboard_Virtual_COM\ht32_usbd_class.c"
|
||||
"USBD\Mass_Storage_SDIO\sd_disk.c"
|
||||
"USBD\USB_UAC_Sound\ht32_usbd_class.c"
|
||||
"USBD\Virtual_COM\ht32_usbd_class.c"
|
||||
+ Update and sync create project related files ("_ProjectConfig.bat"、"_ProjectConfig.ini").
|
||||
+ Update content of "project_template/IP/Example/readme.txt", add MDK-ARM V5.37 related information.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_V1.0.10_2585 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2022-04-14
|
||||
|
||||
Main Changes
|
||||
+ Update EEPROM Basic and EEPROM Emulation middleware, fix the include and define sequence.
|
||||
"utilities/middleware/eeprom_basic.h"
|
||||
"utilities/middleware/eeprom_emulation.h"
|
||||
+ Update UART Module middleware, add the "UARTM_IsTxFinished()" API.
|
||||
"utilities/middleware/uart_module.c"
|
||||
"utilities/middleware/uart_module.h"
|
||||
|
||||
Others
|
||||
+ Update e-Link32 Pro/Lite Command line tool as "V1.0.15" ("utilities/elink32pro/eLink32pro.exe").
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_V1.0.10_2585 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2022-04-14
|
||||
|
||||
Main Changes
|
||||
+ Update EEPROM Basic and EEPROM Emulation middleware, fix the include and define sequence.
|
||||
"utilities/middleware/eeprom_basic.h"
|
||||
"utilities/middleware/eeprom_emulation.h"
|
||||
+ Update UART Module middleware, add the "UARTM_IsTxFinished()" API.
|
||||
"utilities/middleware/uart_module.c"
|
||||
"utilities/middleware/uart_module.h"
|
||||
|
||||
Others
|
||||
+ Update e-Link32 Pro/Lite Command line tool as "V1.0.15" ("utilities/elink32pro/eLink32pro.exe").
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_V1.0.9_2556 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2022-03-15
|
||||
|
||||
Main Changes
|
||||
+ Change to the new Holtek version format (Vm.n.r).
|
||||
+ Add new "FMC/FLASH_OperationNoHalt" example.
|
||||
+ Modify "utilities/common/ring_buffer.c", fix the thread-safe issue of "Buffer_GetLength()".
|
||||
+ Update "GNU_ARM/linker.ld", fix the heap/stack area overlap problem.
|
||||
+ Add "ADC_SamplingTimeConfig()" function for the "ht32f1xxxx_adc_02.c".
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Modify "bool, TRUE, FALSE" define way for C++/.cpp applications.
|
||||
+ Update "startup_ht32fxxxxx_nn.s", support "USE_HT32_CHIP" define exist at startup.s and project Asm
|
||||
setting in the same time (project's Asm Define has the higher priority).
|
||||
+ Remove unuse global variable "DelayTime" of "ebi_lcd.c" and "spi_lcd.c".
|
||||
+ Update "spi_lcd.c/.h", fix the GPIO Chip SEL define mistake.
|
||||
+ Add following middleware.
|
||||
"utilities/middleware/uart_module.c"
|
||||
"utilities/middleware/uart_module.h"
|
||||
+ Update related middleware (eeprom_basic and eeprom_emulation).
|
||||
+ Update e-Link32 Pro/Lite Command line tool as "V1.0.14" ("utilities/elink32pro/eLink32pro.exe").
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_v008_2470 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2021-08-19
|
||||
|
||||
Main Changes
|
||||
+ Add "ht32_time.c/.h" to support following new functions for delay, time measure, and timeout.
|
||||
"Time_Init()"
|
||||
"Time_Delay()"
|
||||
"Time_GetTick()"
|
||||
+ Add new examples:
|
||||
- "ADC/OneShot_SWTrigger_ByTM"
|
||||
- "GPIO/Input"
|
||||
- "GPIO/Output"
|
||||
- "Time/TimeFun"
|
||||
- "Time/TimeFun_UserConf"
|
||||
- "USART/RS485_NMM_Slave"
|
||||
+ Add new definition, "FLASH_WAITSTATE_MAX".
|
||||
+ Add "USART_PARITY_MARK" and "USART_PARITY_SPACE" for the UART parity mode.
|
||||
+ Update "ADC_RegularTrigConfig()" and "AC_TRIG_XXXX" define to support all the trigger source of ADC.
|
||||
+ Add "CKCU_ADCPRE_DIV1" parameter of "CKCU_SetADCnPrescaler()" for the HT32F12364.
|
||||
+ Modified "SDIO_ClearFlag()", disable Status Enable Register (SER) to clear SDIO_FLAG_BUF_OVERFLOW and
|
||||
SDIO_FLAG_BUF_UNDERFLOW.
|
||||
+ Fix the result mistake of the marco below of HT32F12364 (LIBCFG_FLASH_2PAGE_PER_WPBIT is missing).
|
||||
"#define FLASH_WP_PAGE_SET(OP, PAGE)"
|
||||
"#define FLASH_WP_PAGE_CLEAR(OP, PAGE)"
|
||||
"#define FLASH_IS_WP_PAGE(OP, PAGE)"
|
||||
+ Update following example, modify the default value of "gIsINEmpty" from TRUE to FALSE. The default value
|
||||
TRUE may cause the F/W to not send CSW after the first Inquiry CBW Command in a specific condition.
|
||||
"example/USBD/HID_Keyboard_Mass_Storage"
|
||||
"example/USBD/Mass_Storage"
|
||||
"example/USBD/Mass_Storage_IAP"
|
||||
"example/USBD/Mass_Storage_SDIO"
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Fix compile error when turn on Library debug mode (HT32_LIB_DEBUG = 1).
|
||||
+ Update e-Link32 Pro Commander to V1.10.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_v007_2414 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2021-05-11
|
||||
|
||||
Main Changes
|
||||
+ Add new examples:
|
||||
- "EXTI/GPIO_Interrupt"
|
||||
- "CKCU/HSI_AutoTrim_By_LSE"
|
||||
+ Update the IAP example of HT32F12364 project:
|
||||
- IAR EWARM v6/v7/v8:
|
||||
1. Modify "startup_ht32f1xxxx_03.s" to "startup_ht32f1xxxx_iar_03.s".
|
||||
2. Modify "ht32f1xxxx_adc.c" to "ht32f1xxxx_adc_02.c".
|
||||
- Keil MDK-ARM v4/v5: Modify "ht32f1xxxx_adc.c" to "ht32f1xxxx_adc_02.c".
|
||||
+ Fix the system stuck in CKCU_HSIAutoTrimCmd() because of the misjudgment of CKCU_HSIAutoTrimIsReady().
|
||||
+ Fix the CHIP ID error. Fixed "USE_HT32_CHIP=3" to "USE_HT32_CHIP=16". The fixed files are as follows:
|
||||
- IAP/IAP_Text_RAM/EWARM/Project_12364_IAP.ewp
|
||||
- IAP/IAP_UI/EWARM/Project_12364_IAP.ewp
|
||||
+ Fix the syntax error on the "IAP/IAP_Text_RAM/EWARM/startup_ht32f1xxxx_iar_03_iap.s".
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Update the version of eLink32pro.exe to 1.0.1.1.
|
||||
+ Update the following project setting:
|
||||
- IAR EWARM v6/v7: Modify "_ht32_project_source.c" to "_ht32_project_source.h".
|
||||
- SEGGER Embedded Studio: Add the new definition "arm_compiler_variant="SEGGER"".
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32_STD_1xxxx_FWLib_v006_2361 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2021-02-26
|
||||
|
||||
Main Changes
|
||||
+ Add "Create Project Configuration Menu" to choose the target IDE and Device when the first time to do the
|
||||
create project operation of the example. The configuration file, "_CreateProjectConfig.bat" is saved to
|
||||
the root path of the HT32 Firmware Library. You can reset the create project IDE/IC configuration anytime
|
||||
by deleting the configuration file.
|
||||
Target IDE/Compiler:
|
||||
- Keil MDK-ARM v5
|
||||
- Keil MDK-ARM v4
|
||||
- IAR EWARM v8
|
||||
- IAR EWARM v6/v7
|
||||
- SEGGER Embedded Studio
|
||||
- GNU [with Keil and GNU make]
|
||||
- SourceryG++Lite [with Keil]
|
||||
Target Device:
|
||||
- xxxxx: Single Device
|
||||
- xxx*: Series
|
||||
+ Add new examples:
|
||||
- "NVIC/Disable_Interrupt"
|
||||
- "TM/InternalTrigger"
|
||||
- "TM/PWM_Buzzer"
|
||||
- "WDT/Auto_Enable"
|
||||
+ Add Flash programming function of GNU Maker (via e-Link32 Pro/Lite Commander).
|
||||
"make IC=xxxxx eraseall"
|
||||
"make IC=xxxxx program"
|
||||
"make IC=xxxxx run"
|
||||
+ Update "CKCU_HSIAutoTrimCmd()" and "CKCU_HSIAutoTrimIsReady()" function to improve clock stability.
|
||||
+ Fix the cache address problem of "SDDISK_Read()" function.
|
||||
"USBD/Mass_Storage/sd_disk.c", "USBD/Mass_Storage_SDIO/sd_disk.c"
|
||||
+ Update GNU project (*.uvprojx), fix the compile error when use new GNU Arm version
|
||||
("gcc-arm-none-eabi-10-2020-q2-preview-win32" or above).
|
||||
+ Fix Keil compiling error when disable both retarget and MicroLib.
|
||||
+ Update "ht32f1xxxx_01.h", fix the compatibility issue when user include "stdbool.h".
|
||||
+ Modify GNU compiler settings, output text file (disassembly) after building the code.
|
||||
+ Add "HT32_FWLIB_VER" and "HT32_FWLIB_SVN" in "ht32f1xxxx_lib.h" for the version information of
|
||||
HT32 Firmware Library.
|
||||
Example:
|
||||
"#define HT32_FWLIB_VER (006)"
|
||||
"#define HT32_FWLIB_VER (2361)"
|
||||
+ Add new AFIO define in "ht32f1xxxx_gpio.h".
|
||||
- "AFIO_FUN_MCTM1"
|
||||
- "AFIO_FUN_PWM"
|
||||
- "AFIO_FUN_PWM0", "AFIO_FUN_PWM1", "AFIO_FUN_PWM2", "AFIO_FUN_PWM3"
|
||||
+ Add following alias of MCTM IRQ handler
|
||||
"#define MCTM0_IRQn MCTM0UP_IRQn"
|
||||
"#define MCTM0_IRQHandler MCTM0UP_IRQHandler"
|
||||
"#define MCTM1_IRQn MCTM1UP_IRQn"
|
||||
"#define MCTM1_IRQHandler MCTM1UP_IRQHandler"
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Update "SPI/FIFO_SEL_Hardware" example, add Rx FIFO Timeout function and fix data loss issue.
|
||||
+ Update "USBD/Mass_Storage" example, add "HTCFG_SD_MAXSPEED" define for different board.
|
||||
+ Update "utilities/common/spi_lcd.c".
|
||||
- Remove duplicate SPI parameter setting of "LCD_Init()".
|
||||
- Update SPI chip select define and SPI configuration by "LCD_SPI_SEL_AFIO_MODE".
|
||||
- Swap the "GPIO_DirectionConfig()" and "GPIO_SetOutBits()" function to prevent transient state
|
||||
of SPI_SEL pin.
|
||||
+ Update "_ProjectConfig*.bat" files.
|
||||
+ Add "Project Source File Setting" functions ("_ProjectSource.ini" and "_ProjectSource.bat").
|
||||
+ Rename "_CreateProjectUSB.bat" as "_CreateProject.bat".
|
||||
+ Add dummy xxTM C files, to notify the user that SCTM/PWM/GPTM/MCTM timer use the "ht32f1xxxx_tm.c" driver.
|
||||
"ht32f1xxxx_gptm.c", "ht32f1xxxx_pwm.c", "ht32f1xxxx_sctm.c"
|
||||
+ Add "IS_IPN_MCTM()" and "IS_IPN_GPTM" macro, for use to confirm the xxTMn is GPTM or MCTM.
|
||||
+ Update comment and board/pin configuration of "ADC/OneShot_TMTrigger_PDMA" example.
|
||||
+ Update and sync startup.s/system.c files.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v005_2207 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2020-08-11
|
||||
|
||||
Main Changes
|
||||
+ Add the following files to use e-Link32 Pro with SEGGER Embedded Studio. Refer to the
|
||||
"readme e-Link32 Pro.txt" for how to use it.
|
||||
"emStudiov4/readme e-Link32 Pro.txt"
|
||||
"emStudiov4/Project_xxxxx.bat"
|
||||
"emStudiov4/_MassErase.bat"
|
||||
+ Fix the "I2S_FIFOTrigLevelConfig()" error which did not clear the field of I2S FCR correctly.
|
||||
+ Fix "RPRE_MASK" define error for "RTC_SetPrescaler()" function.
|
||||
+ Add "SPI_FLASH_WaitForWriteEnd()" function in the end of the write status operation
|
||||
("SPI_FLASH_WriteStatus()").
|
||||
+ Modify "SPI_FLASH_WaitForWriteEnd()" function to return value of status register.
|
||||
+ Add below notice of examples to inform the user to check the local structure variable without a
|
||||
default value.
|
||||
"Notice that the local variable (structure) did not have an initial value.
|
||||
Please confirm that there are no missing members in the parameter settings below this function."
|
||||
+ Add "LIBCFG_MAX_SPEED" in the file "ht32fxxxxx_libcfg.h" which indicate the maximum core speed.
|
||||
+ Add the following definition for convenience.
|
||||
PDMACH0_IRQn ~ PDMACH5_IRQn
|
||||
AFIO_FUN_MCTM0
|
||||
AFIO_FUN_GPTM0 ~ AFIO_FUN_GPTM3
|
||||
AFIO_FUN_PWM0
|
||||
AFIO_FUN_SCTM0 ~ AFIO_FUN_SCTM2
|
||||
+ Add new examples.
|
||||
"TM/PWM"
|
||||
"TM/UpdateEvent"
|
||||
+ Add "s64/u64" definition.
|
||||
|
||||
Others
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Add below notice in the "FMC/FLASH_Security" example.
|
||||
"The Option Byte will be write protected (cannot be changed again) after the
|
||||
Security Protection is enabled. Refer to the user manual for details."
|
||||
+ Remove HSI disable setting of Configuration Wizard and add notice in the "system_xxxxx_nn.c".
|
||||
+ Update the following examples to remove compiler warning of the GNU compiler.
|
||||
"USBD/Mass_Storage"
|
||||
"USART/PDMA"
|
||||
"USART/Interrupt"
|
||||
+ Add "-Waddress-of-packed-member" #pragma of below examples to remove compiler warning of the
|
||||
GNU compiler.
|
||||
"USBD/Mass_Storage"
|
||||
"USBD/Mass_Storage_IAP"
|
||||
"USBD/Mass_Storage_SDIO"
|
||||
"USBD/HID_Keyboard"
|
||||
"USBD/HID_Keyboard_Joystick"
|
||||
"USBD/HID_Keyboard_Mass_Storage"
|
||||
"USBD/HID_Keyboard_Virtual_COM"
|
||||
"USBD/HID_Mouse"
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v004_2103 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2020-04-25
|
||||
|
||||
Main Changes
|
||||
+ Remove the "I2C_Cmd()" in the "I2C_Init()" function since it shall be called after the I2C related
|
||||
settings. User shall call the "I2C_Cmd()" by themself after the "I2C_Init()".
|
||||
+ Update "system_ht32f1xxxx_02.c", modify the LDO related setting.
|
||||
+ Add "USART_GetIntStatus()" function to get the enabled interrupt source.
|
||||
+ Add "RETARGET_HSI_ATM" setting to turn on/off the auto-trim function of HSI ("ht32f1xxxx_conf.h").
|
||||
+ Add "USBDClass_Reset()" into the "USBD/*" example to reset related flag for the self-power application.
|
||||
+ Modify "ht32f5xxxx_aes.c", fix "AES_SetKeyTable()" and "_AES_CryptData()" functions who did not clear
|
||||
related fields before set it.
|
||||
+ Rename examples as below.
|
||||
IP Old Name New Name
|
||||
-------- -------- --------
|
||||
ADC EXTITrigger_DiscontinuousMode Discontinuous_EXTITrigger
|
||||
ADC PDMA_ADCResult OneShot_TMTrigger_PDMA
|
||||
ADC Potentiometer_ContinuousMode Continuous_Potentiometer
|
||||
ADC TM_Trigger OneShot_PWMTrigger
|
||||
ADC TM_Trigger_with_Delay OneShot_PWMTrigger_with_Delay
|
||||
USART HyperTerminal_TxRx Retarget
|
||||
USART HyperTerminal_TxRx_Interrupt Interrupt
|
||||
USART HyperTerminal_TxRx_Interrupt_FIFO Interrupt_FIFO
|
||||
+ Update the following example to improve readability.
|
||||
"ADC/AnalogWatchdog"
|
||||
"ADC/Continuous_Potentiometer"
|
||||
"ADC/Discontinuous_EXTITrigger"
|
||||
"ADC/InternalReferenceVoltage"
|
||||
"ADC/OneShot_PWMTrigger"
|
||||
"ADC/OneShot_PWMTrigger_with_Delay"
|
||||
"ADC/OneShot_TMTrigger_PDMA"
|
||||
"ADC/Two_Group_MaxCH"
|
||||
"USART/Interrupt"
|
||||
"USART/Interrupt_FIFO"
|
||||
"USART/PDMA"
|
||||
"USART/Polling"
|
||||
"USART/Retarget"
|
||||
"USBD/HID_Demo"
|
||||
"USBD/HID_DemoVendorReport"
|
||||
+ Update UxART related example, turn on internal pull up to prevent unknown state.
|
||||
+ Add new examples.
|
||||
"BFTM/OneShot"
|
||||
"BFTM/TimeMeasure"
|
||||
+ Remove unnecessary RTC compare match restart setting of the RTC example
|
||||
(which cause the time not correct after entering the low power mode).
|
||||
+ ADC to ADC0 related modification (to compatible with M0+ and ADC1).
|
||||
Modify "HT_ADC" and "ADC_IRQn" to "HT_ADC0" and "ADC0_IRQn".
|
||||
Modify "AFIO_FUN_ADC" as "AFIO_FUN_ADC0".
|
||||
Modify "CKCU_SetADCPrescaler()" to "CKCU_SetADCnPrescaler()".
|
||||
Add "CKCU_ADCPRE_ADCn_TypeDef".
|
||||
Modify "ADC_Freq" to "ADC0_Freq" of "CKCU_ClocksTypeDef".
|
||||
Modify "ADC" to "ADC0" of "RSTCU_PeripReset_TypeDef".
|
||||
Add "HT_ADC", "ADC_IRQn", "AFIO_FUN_ADC" define for backward compatibility.
|
||||
+ Fix "HT_GPIOF" define error of HT32F12364.
|
||||
|
||||
Others
|
||||
+ Update "SPI/FIFO_SEL_Hardware" example, change the code location of the IP enable ("SPI_Cmd()").
|
||||
+ Update "system_ht32fxxxxx_nn.c" (coding style).
|
||||
+ Update "ht32_series.c/h" and "ht32_retarget_usbdconf.h" to improve the compatibly of the
|
||||
terminal software.
|
||||
+ Update comment, format, typing error, and coding style.
|
||||
+ Fix interrupt mode of UxART retarget, remove unnecessary FIFO/interrupt configuration of the
|
||||
retarget function.
|
||||
+ Update format of "CKCU_PeripClockConfig_TypeDef" and "RSTCU_PeripReset_TypeDef".
|
||||
+ Update and modify naming rule of the "HTCFG_xxxx" configuration define in the "ht32_board_config.h".
|
||||
+ Update settings of project files.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v004_1946 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2019-11-28
|
||||
|
||||
Main Changes
|
||||
+ Move the "common/*.h" include from the begin to the end (after the pin define) in the file
|
||||
"HT32_Board/ht32fxxxx_sk/dvb.h". The original include way leads to the pin define lost when you
|
||||
use the EBI_LCD->EBI_LCD_RAM outside the "ebi_lcd.c".
|
||||
+ Fix error of "_CreateProjectScript.bat" which cause the stack size and RW base can not be set by the
|
||||
"_ProjectConfig.bat" of the emStudiov4 project.
|
||||
+ Add "GPIO_GetID()" function to convert HT_GPIOx to GPIO_Px.
|
||||
+ Update "HID_Demo_UI.exe" to support HID Report ID.
|
||||
+ Add "USBD/HID_DemoVendorReport" example.
|
||||
+ Modify "SPI_Init()" function, fix SPIx Clock Prescaler setting of HT32F12364.
|
||||
+ Modify "system_ht32f1xxxx_03.c", fix PLLCFGR initiation error which cause the "PLL_CLK_SRC_DIV" setting
|
||||
is not work.
|
||||
+ Add "RETARGET_UxART_BAUDRATE" setting to change the retarget UART baudrate in "ht32f1xxxx_conf.h".
|
||||
+ Add "RETARGET_HSI_ATM" setting to turn on/off the auto-trim function of HSI.
|
||||
+ Add "RETARGET_DEFINE_HANDLER" setting to remove the UxARTn_IRQHandler() define of the retarget.
|
||||
This setting is used for the model who grouping two UART Interrupt into one vector.
|
||||
+ Add non-block mode of USB Virtual-COM retarget function ((Drop data if USB or terminal software is
|
||||
not ready).
|
||||
+ Modify "PWRCU_SetLDOFTRM()" function, fix the error which cause the LDO output voltage fine trim is
|
||||
not work.
|
||||
+ Update "PWRCU_DeepSleep2()" to restore the LDO output voltage fine trim after system wakeup.
|
||||
+ Add SWCLK toggle of "GPIO_DisableDebugPort()" function.
|
||||
|
||||
Others
|
||||
+ Add "utilities/common/lcd.h" to put the lcd related register together.
|
||||
+ Update format and coding style.
|
||||
+ Add PLL Output frequency comment of "system_ht32f1xxxx_nn.c".
|
||||
+ Update project files.
|
||||
.c and .h files order.
|
||||
Project format.
|
||||
Include path order.
|
||||
+ Add "USAGE_PAGE_L" define of "USB/HID_Demo" example.
|
||||
+ Fix typing error of "ht32f1xxxx_conf.h".
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v004_1812 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2019-09-11
|
||||
|
||||
Main Changes
|
||||
+ Add new device support.
|
||||
HT32F12364
|
||||
+ Update "ebi_lcd.c/h", fix LCD_SPI_BL_GPIO_XXX define error (shall be LCD_EBI_BL_GPIO_XXX).
|
||||
+ Update USB example, use USB PLL by default (if USB PLL exist).
|
||||
+ Fix function name typing error
|
||||
SPI_GUADTCmd() -> SPI_GUARDTCmd()
|
||||
SPI_GUADTConfig -> SPI_GUARDTConfig()
|
||||
+ Update "ADC_RegularGroupConfig()" and "ADC_HPGroupConfig()", prevent to enable the ADC directly after
|
||||
the above function call. User shall use the "ADC_Cmd(HT_ADC, ENABLE);" to enable the ADC.
|
||||
+ Rename following files.
|
||||
"IAR/startup_ht32f1xxxx_01.s" to "IARstartup_ht32f1xxxx_iar_01.s"
|
||||
"IAR/startup_ht32f1xxxx_03.s" to "IARstartup_ht32f1xxxx_iar_03.s"
|
||||
|
||||
Others
|
||||
+ Update comment and coding style.
|
||||
+ Update "USART/HyperTerminal_TxRx_Interrupt" example, remove unnecessary configuration of LED.
|
||||
+ Update readme file of "EBI/LCD" example.
|
||||
+ Add "PWRCU/PowerDown_RTC" example.
|
||||
+ Add "PWRCU/PWRCU_PowerDown_WAKEUPPin" example.
|
||||
+ Add "RTC/Time" example.
|
||||
+ Update and sync "ht32f1xxxx_conf.h".
|
||||
+ Update and sync "HT32F1xxxx_01_DebugSupport.ini".
|
||||
+ Update "ht32f1xxxx_tm.c", remove unnecessary variable initialization.
|
||||
+ Update "ht32_op.c" and "ht32_op.s", edit comment of WDT Enable function.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v003_1679 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2019-04-19
|
||||
|
||||
Main Changes
|
||||
+ Fix error of "CKCU_HSIAutoTrimClkConfig()" function which cause the HSI auto-trim not work.
|
||||
+ Modify following define of ADC.
|
||||
ADC_CH_GNDREF -> ADC_CH_GND_VREF
|
||||
ADC_CH_VREF -> ADC_CH_VDD_VREF
|
||||
|
||||
Others
|
||||
+ None.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v003_1673 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2019-04-09
|
||||
|
||||
Main Changes
|
||||
+ Add SEGGER Embedded Studio IDE support (beta version).
|
||||
+ Update "ht32f1xxxx_usbd.c" and "ht32_usbd_core.c", add Force USB Reset Control function (apply to specific
|
||||
model only).
|
||||
+ Update Create Project script, add Script folder in project_template.
|
||||
+ Add "TM/TriggerCounter" example.
|
||||
+ Add "USBD/HID_Keyboard_Mass_Storage" example.
|
||||
|
||||
Others
|
||||
+ Update comment of example code.
|
||||
+ Update define of "USBD/Mass_Storage" example.
|
||||
+ Update "EXTI/WakeUp_DeepSleepMode1" Example, add LED3 (for some SK have only LED2 and LED3 on board).
|
||||
+ Update/sync startup.s/system.c files.
|
||||
+ Update/sync "HT32F1xxxx_01_DebugSupport.ini".
|
||||
+ Update/sync "ht32_op.s" and "ht32_op.c".
|
||||
+ Update "BootProcess" function.
|
||||
+ Update/sync "FlashMacro.mac".
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v002_1496 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2018-12-17
|
||||
|
||||
Main Changes
|
||||
+ Modify Control IN/OUT method of USB Core, to fix USB transfer problem when CPU in the lower speed or late
|
||||
USB interrupt case.
|
||||
+ Add workaround for PDMA CH3 issue (Interrupt Enable bit of CH3 is not work).
|
||||
|
||||
Others
|
||||
+ Add "USBD_DisableDefaultPull()" function to disable pull resistance when the USB is not use.
|
||||
+ Rename RTC example as below.
|
||||
"Calendar" -> "Time_BackupDomain"
|
||||
+ Add new example.
|
||||
"RTC/Calendar_BackupDomain"
|
||||
"FMC/EnableProtectionByFW"
|
||||
+ Update "EXTI/WakeUp_DeepSleepMode1" example.
|
||||
+ Update coding style.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v002_1406 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2018-09-30
|
||||
|
||||
Main Changes
|
||||
+ Update HardFault_Handler of "ht32f1xxxx_01_it.c",add the debug instruction and system reset.
|
||||
+ Add "RAND/Random_Number" example and update "ht32_rand.c".
|
||||
+ Add "__HT_check_sp" and "__HT_check_heap" symbol into startup.s and watchpoint command into
|
||||
"HT32F1xxxx_01_DebugSupport.ini" for debug stack/heap underflow, overflow, and overwrite.
|
||||
+ Update "USBD/HID_Keyboard_Joystick" and "USBD/HID_Mouse" example, change the set flag sequence
|
||||
(before USBDCore_EPTWriteINData).
|
||||
+ Add GNU Make support of GNU Arm compiler.
|
||||
|
||||
Others
|
||||
+ Add "objcooy.txt" which shows how to use obj tools of GNU Arm compiler.
|
||||
+ Update format and coding style.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v002_1367 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2018-08-02
|
||||
|
||||
Main Changes
|
||||
+ Add GNU Arm compiler support.
|
||||
- Add project_template related files
|
||||
- "startup_ht32f5xxxx_gcc_nn.s"
|
||||
- "linker.ld" (link script)
|
||||
+ Update "ht32f5xxxx_tm.c/.h", add following functions which have TM_CH_n parameter.
|
||||
void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction)
|
||||
void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp)
|
||||
void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp)
|
||||
u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n)
|
||||
|
||||
Others
|
||||
+ Add "USBD/HID_Keyboard_Virtual_COM" example.
|
||||
+ Fix compile error when turn on Library debug mode (HT32_LIB_DEBUG = 1).
|
||||
+ Modify "example/NVIC/Vector_Table_Offset" example code to support GUN compiler.
|
||||
+ Simplify "example/USART/HyperTerminal_TxRx_Interrupt" example.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v001_1302 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2018-06-11
|
||||
|
||||
Main Changes
|
||||
+ Add SourceryG++Lite compiler support.
|
||||
- Add project_template related files
|
||||
- "startup_ht32f1xxxx_cs3_nn.s"
|
||||
- "linker.ld" (link script)
|
||||
+ Add DMA support of "utilities/common/spi_flash.c".
|
||||
+ Add "EXTI_GetEdgeFlag()" function.
|
||||
+ Add LIBCFG_AES_SWAP function to process endian issue of AES.
|
||||
|
||||
Others
|
||||
+ Update "ht32f1xxxx_conf.h" for AUTO_RETURN (\r) option.
|
||||
+ Update format of IAR "startup_ht32f1xxxx_01.s".
|
||||
+ Fix "LIBCFC_CKCU_USB_PLL" typing error of ht32fxxxx_libcfg.h and example code (shall be LIBCFG_CKCU_USB_PLL).
|
||||
+ Fix IAP_PPBIT define error of "IAP/IAP_UI" example.
|
||||
+ Update "ht32f1xxxx_ckcu.c" to remove unnecessary register write of PLL.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v001_1153 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2018-02-28
|
||||
|
||||
Main Changes
|
||||
+ Add "USBD/USB_UAC_Sound_RateControl" Example.
|
||||
+ Add "I2C_SpeedOffset" parameter of I2C_InitTypeDef to reach real I2C speed.
|
||||
Note: Related examples are also updated.
|
||||
+ Change EBI timing of "ebi_lcd.c" to fix LCD display problem on HT32F12345 with ESK32-A2A31.
|
||||
+ Add "CKCU/HSI_AutoTrim_By_USB" Example.
|
||||
+ Update "CKCU_HSIAutoTrimIsReady" function of "ht32f5xxxx_ckcu.c".
|
||||
|
||||
Others
|
||||
+ Update format and coding style.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v001_1023 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2017-12-30
|
||||
|
||||
Main Changes
|
||||
+ Update boot related functions of "startup_ht32f1xxxx_nn.s" and "system_ht32f1xxxx_nn.c".
|
||||
+ Update "ht32_op.c" and "ht32_op.s" to support enable WDT function by Flash Option byte (Apply to specific
|
||||
model only).
|
||||
+ Add "GPIO_DisableDebugPort()"" function to disable SWD function.
|
||||
|
||||
Others
|
||||
+ Fix IAR Project setting error of IAP Example.
|
||||
+ Add "RTC_LSILoadTrimData()" function.
|
||||
+ Add "LIBCFG_RTC_LSI_LOAD_TRIM" define of HT32F165x.
|
||||
+ Remove useless "RTC_LSICmd()"" function.
|
||||
+ Update following examples, remove LSI enable code (LSI default on).
|
||||
"PWRCU/DeepSleepMode1"
|
||||
"PWRCU/BackupData"
|
||||
"PWRCU/DeepSleepMode2"
|
||||
"PWRCU/PowerDownMode"
|
||||
"RTC/Calendar"
|
||||
+ Update I2S and USB UAC related examples (Coding style and remove unuse define).
|
||||
+ Update USB Example, remove invalid remote wakeup configuration by define (Only HID class support Remote
|
||||
Wakeup).
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v001_933 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2017-11-17
|
||||
|
||||
Main Changes
|
||||
+ Fix AES typing error of "ht32f1xxxx_aes.c/.h" (EBC to ECB).
|
||||
+ Fix TM define error of "ht32f1xxxx_tm.c/.h".
|
||||
|
||||
Others
|
||||
+ Update "ht32_virtual_com.inf" file, add Digital Signature.
|
||||
+ Update typing error of example code.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v001_899 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2017-10-19
|
||||
|
||||
Main Changes
|
||||
+ Update "SDIO/SDCard" Example code. Fix read Card SCR problem which causes SDIO working on 1-bit mode
|
||||
abnormally.
|
||||
|
||||
Others
|
||||
+ Update project setting.
|
||||
+ Remove some project files. Use "CreateProject.bat" to copy project files automatically.
|
||||
+ Add "LIBCFG_CHIPNAME" define.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v001_785 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2017-08-31
|
||||
|
||||
Main Changes
|
||||
+ Fix "ht32f1xxxx_conf.h" typing error ("_ADC" to "_AES").
|
||||
+ Fix AES typing error (EBC to ECB).
|
||||
|
||||
Others
|
||||
+ Update "ht32_usbd_core.c" to support vendor function.
|
||||
+ Add "USE_MEM_HT32F1xxxx" define into project.
|
||||
+ Add "USE_MEM_HT32F1xxxx" default define into "ht32f1xxxx_xx_libcfg.h".
|
||||
+ Rename "system_ht32f1xxxx.h" to "system_ht32f1xxxx_01.h" for PACK requirement.
|
||||
+ Update IAP examples.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v001_671 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2017-07-27
|
||||
|
||||
Main Changes
|
||||
+ None
|
||||
|
||||
Others
|
||||
+ Update "ht32_op.c", add CK_CODE/CK_DATA/CK_CODEOP in Option Bytes (same format with e-Writer32).
|
||||
+ Modify USB/Mass_Storage example for WIN10 compatibility issue.
|
||||
+ Add "USE_MEM_HT32F1xxxx" support for memory size define (LIBCFG_FLASH_SIZE/LIBCFG_RAM_SIZE).
|
||||
+ Add IAR EWARMv8 project template (create by IAR EWARM v8.11).
|
||||
+ Upgrade the version of IAR EWARM project template from v6.20 to v6.50.
|
||||
Note:
|
||||
1. Supported CMSIS-DAP: IAR EWARM v6.50 and above.
|
||||
2. RDI/e-Link32 is not supported anymore from the v8.xx of IAR EWARM.
|
||||
|
||||
Known Issue:
|
||||
+ IAP example is not ready, will be update in next release.
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v001_552 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2017-07-17
|
||||
|
||||
Main Changes
|
||||
+ Add example code.
|
||||
+ Update TM for PDMA support.
|
||||
+ Fix "USART_RXTL_01/04/08/14" define error.
|
||||
+ Fix "HT32F_DVB_BuzzerFun()" define error of "ht32f1xxxx_board_01.c".
|
||||
+ Fix pin assignment error of "ht32f12366_sk.h"
|
||||
|
||||
Others
|
||||
+ Add BUTTON_MODE_WAKE_UP support for "ht32f1xxxx_sk.c/.h".
|
||||
+ Update typing error and coding style.
|
||||
+ Remove warning on old MDK-ARM version.
|
||||
+ Update project setting.
|
||||
+ Add DEINIT_ENABLE setting of "ht32f1xxxx_system_nn.c".
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* HT32F1xxxx_FWLib_v001_167 */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
Release Date: 2017-06-14
|
||||
|
||||
Main Changes
|
||||
+ Initial version.
|
||||
|
||||
Others
|
||||
+
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
import rtconfig
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = Split("""
|
||||
library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_bftm.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_crc.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_ebi.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_exti.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_flash.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_gpio.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2c.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2s.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_mctm.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_pdma.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwrcu.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_rstcu.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_sci.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_sdio.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_tm.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_usart.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_usbd.c
|
||||
library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c
|
||||
|
||||
library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c
|
||||
""")
|
||||
#HT32F1xxxx_Driver/src/ht32f1xxxx_csif.c
|
||||
|
||||
path = [
|
||||
cwd + '/library/HT32F1xxxx_Driver/inc',
|
||||
cwd + '/library/CMSIS/Include',
|
||||
cwd + '/library/Device/Holtek/HT32F1xxxx/Include'
|
||||
]
|
||||
|
||||
CPPDEFINES = ['USE_HT32_DRIVER']
|
||||
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,411 @@
|
|||
/******************************************************************************
|
||||
* @file cachel1_armv7.h
|
||||
* @brief CMSIS Level 1 Cache API for Armv7-M and later
|
||||
* @version V1.0.1
|
||||
* @date 19. April 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_CACHEL1_ARMV7_H
|
||||
#define ARM_CACHEL1_ARMV7_H
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||
\brief Functions that configure Instruction and Data cache.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Cache Size ID Register Macros */
|
||||
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
||||
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
||||
|
||||
#ifndef __SCB_DCACHE_LINE_SIZE
|
||||
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
#ifndef __SCB_ICACHE_LINE_SIZE
|
||||
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Enable I-Cache
|
||||
\details Turns on I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable I-Cache
|
||||
\details Turns off I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate I-Cache
|
||||
\details Invalidates I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief I-Cache Invalidate by address
|
||||
\details Invalidates I-Cache for the given address.
|
||||
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] isize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if ( isize > 0 ) {
|
||||
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_ICACHE_LINE_SIZE;
|
||||
op_size -= __SCB_ICACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable D-Cache
|
||||
\details Turns on D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
__DSB();
|
||||
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable D-Cache
|
||||
\details Turns off D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate D-Cache
|
||||
\details Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean D-Cache
|
||||
\details Cleans D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||||
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean & Invalidate D-Cache
|
||||
\details Cleans and Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\details Invalidates D-Cache for the given address.
|
||||
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean by address
|
||||
\details Cleans D-Cache for the given address
|
||||
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean and Invalidate by address
|
||||
\details Cleans and invalidates D_Cache for the given address
|
||||
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_CacheFunctions */
|
||||
|
||||
#endif /* ARM_CACHEL1_ARMV7_H */
|
||||
|
|
@ -0,0 +1,888 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.3.2
|
||||
* @date 27. May 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
|
||||
|
||||
/* CMSIS compiler control DSP macros */
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __ARM_FEATURE_DSP 1
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __memory_changed()
|
||||
#endif
|
||||
|
||||
/* ######################### Startup and Lowlevel Init ######################## */
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __main
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __Vectors
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
|
||||
#endif
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
__ISB();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,283 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.5
|
||||
* @date 02. February 2022
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,952 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.8
|
||||
* @date 21. August 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RESERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
__COMPILER_BARRIER();
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__COMPILER_BARRIER();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
|
||||
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,979 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm1.h
|
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||
* @version V1.0.1
|
||||
* @date 12. November 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC
|
||||
#define __CORE_CM1_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M1
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM1 definitions */
|
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM1_H_DEPENDANT
|
||||
#define __CORE_CM1_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM1_REV
|
||||
#define __CM1_REV 0x0100U
|
||||
#warning "__CM1_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M1 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M1 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
__COMPILER_BARRIER();
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__COMPILER_BARRIER();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,275 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.2
|
||||
* @date 25. May 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,352 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.3
|
||||
* @date 03. February 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
/******************************************************************************
|
||||
* @file pac_armv81.h
|
||||
* @brief CMSIS PAC key functions for Armv8.1-M PAC extension
|
||||
* @version V1.0.0
|
||||
* @date 23. March 2022
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2022 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef PAC_ARMV81_H
|
||||
#define PAC_ARMV81_H
|
||||
|
||||
|
||||
/* ################### PAC Key functions ########################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
|
||||
\brief Functions that access the PAC keys.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for privileged mode
|
||||
\details Reads the PAC key stored in the PAC_KEY_P registers.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_p_0\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_p_1\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_p_2\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_p_3\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for privileged mode
|
||||
\details writes the given PAC key to the PAC_KEY_P registers.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_p_0, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_p_1, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_p_2, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_p_3, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for unprivileged mode
|
||||
\details Reads the PAC key stored in the PAC_KEY_U registers.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_u_0\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_u_1\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_u_2\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_u_3\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for unprivileged mode
|
||||
\details writes the given PAC key to the PAC_KEY_U registers.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_u_0, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_u_1, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_u_2, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_u_3, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for privileged mode (non-secure)
|
||||
\details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_p_0_ns\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_p_1_ns\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_p_2_ns\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_p_3_ns\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for privileged mode (non-secure)
|
||||
\details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_p_0_ns, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_p_1_ns, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_p_2_ns, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_p_3_ns, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for unprivileged mode (non-secure)
|
||||
\details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_u_0_ns\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_u_1_ns\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_u_2_ns\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_u_3_ns\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for unprivileged mode (non-secure)
|
||||
\details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_u_0_ns, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_u_1_ns, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_u_2_ns, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_u_3_ns, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
|
||||
|
||||
#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
|
||||
|
||||
/*@} end of CMSIS_Core_PacKeyFunctions */
|
||||
|
||||
|
||||
#endif /* PAC_ARMV81_H */
|
||||
|
|
@ -0,0 +1,337 @@
|
|||
/******************************************************************************
|
||||
* @file pmu_armv8.h
|
||||
* @brief CMSIS PMU API for Armv8.1-M PMU
|
||||
* @version V1.0.1
|
||||
* @date 15. April 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
/**
|
||||
* \brief PMU Events
|
||||
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||
* */
|
||||
|
||||
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||
|
||||
/** \brief PMU Functions */
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
{
|
||||
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set event to count for PMU eventer counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||
{
|
||||
PMU->EVTYPER[num] = type;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||
{
|
||||
return PMU->CCNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
{
|
||||
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||
{
|
||||
return PMU->OVSSET;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||
{
|
||||
PMU->OVSCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||
{
|
||||
PMU->SWINC = mask;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/******************************************************************************
|
||||
* @file main_s.c
|
||||
* @brief Code template for secure main function
|
||||
* @version V1.1.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* Use CMSE intrinsics */
|
||||
#include <arm_cmse.h>
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/* TZ_START_NS: Start address of non-secure application */
|
||||
#ifndef TZ_START_NS
|
||||
#define TZ_START_NS (0x200000U)
|
||||
#endif
|
||||
|
||||
/* typedef for non-secure callback functions */
|
||||
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
|
||||
|
||||
/* Secure main() */
|
||||
int main(void) {
|
||||
funcptr_void NonSecure_ResetHandler;
|
||||
|
||||
/* Add user setup code for secure part here*/
|
||||
|
||||
/* Set non-secure main stack (MSP_NS) */
|
||||
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
|
||||
|
||||
/* Get non-secure reset handler */
|
||||
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
|
||||
|
||||
/* Start non-secure state software application */
|
||||
NonSecure_ResetHandler();
|
||||
|
||||
/* Non-secure software does not return, this code is not executed */
|
||||
while (1) {
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/******************************************************************************
|
||||
* @file tz_context.c
|
||||
* @brief Context Management for Armv8-M TrustZone - Sample implementation
|
||||
* @version V1.1.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2016-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include "tz_context.h"
|
||||
|
||||
/// Number of process slots (threads may call secure library code)
|
||||
#ifndef TZ_PROCESS_STACK_SLOTS
|
||||
#define TZ_PROCESS_STACK_SLOTS 8U
|
||||
#endif
|
||||
|
||||
/// Stack size of the secure library code
|
||||
#ifndef TZ_PROCESS_STACK_SIZE
|
||||
#define TZ_PROCESS_STACK_SIZE 256U
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint32_t sp_top; // stack space top
|
||||
uint32_t sp_limit; // stack space limit
|
||||
uint32_t sp; // current stack pointer
|
||||
} stack_info_t;
|
||||
|
||||
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
|
||||
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
|
||||
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
|
||||
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_InitContextSystem_S (void) {
|
||||
uint32_t n;
|
||||
|
||||
if (__get_IPSR() == 0U) {
|
||||
return 0U; // Thread Mode
|
||||
}
|
||||
|
||||
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
|
||||
ProcessStackInfo[n].sp = 0U;
|
||||
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
|
||||
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
|
||||
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
|
||||
}
|
||||
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
|
||||
|
||||
ProcessStackFreeSlot = 0U;
|
||||
|
||||
// Default process stack pointer and stack limit
|
||||
__set_PSPLIM((uint32_t)ProcessStackMemory);
|
||||
__set_PSP ((uint32_t)ProcessStackMemory);
|
||||
|
||||
// Privileged Thread Mode using PSP
|
||||
__set_CONTROL(0x02U);
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
|
||||
uint32_t slot;
|
||||
|
||||
(void)module; // Ignore (fixed Stack size)
|
||||
|
||||
if (__get_IPSR() == 0U) {
|
||||
return 0U; // Thread Mode
|
||||
}
|
||||
|
||||
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
|
||||
return 0U; // No slot available
|
||||
}
|
||||
|
||||
slot = ProcessStackFreeSlot;
|
||||
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
|
||||
|
||||
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
|
||||
|
||||
return (slot + 1U);
|
||||
}
|
||||
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
|
||||
uint32_t slot;
|
||||
|
||||
if (__get_IPSR() == 0U) {
|
||||
return 0U; // Thread Mode
|
||||
}
|
||||
|
||||
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
|
||||
return 0U; // Invalid ID
|
||||
}
|
||||
|
||||
slot = id - 1U;
|
||||
|
||||
if (ProcessStackInfo[slot].sp == 0U) {
|
||||
return 0U; // Inactive slot
|
||||
}
|
||||
ProcessStackInfo[slot].sp = 0U;
|
||||
|
||||
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
|
||||
ProcessStackFreeSlot = slot;
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
|
||||
uint32_t slot;
|
||||
|
||||
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
|
||||
return 0U; // Thread Mode or using Main Stack for threads
|
||||
}
|
||||
|
||||
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
|
||||
return 0U; // Invalid ID
|
||||
}
|
||||
|
||||
slot = id - 1U;
|
||||
|
||||
if (ProcessStackInfo[slot].sp == 0U) {
|
||||
return 0U; // Inactive slot
|
||||
}
|
||||
|
||||
// Setup process stack pointer and stack limit
|
||||
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
|
||||
__set_PSP (ProcessStackInfo[slot].sp);
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
__attribute__((cmse_nonsecure_entry))
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
|
||||
uint32_t slot;
|
||||
uint32_t sp;
|
||||
|
||||
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
|
||||
return 0U; // Thread Mode or using Main Stack for threads
|
||||
}
|
||||
|
||||
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
|
||||
return 0U; // Invalid ID
|
||||
}
|
||||
|
||||
slot = id - 1U;
|
||||
|
||||
if (ProcessStackInfo[slot].sp == 0U) {
|
||||
return 0U; // Inactive slot
|
||||
}
|
||||
|
||||
sp = __get_PSP();
|
||||
if ((sp < ProcessStackInfo[slot].sp_limit) ||
|
||||
(sp > ProcessStackInfo[slot].sp_top)) {
|
||||
return 0U; // SP out of range
|
||||
}
|
||||
ProcessStackInfo[slot].sp = sp;
|
||||
|
||||
// Default process stack pointer and stack limit
|
||||
__set_PSPLIM((uint32_t)ProcessStackMemory);
|
||||
__set_PSP ((uint32_t)ProcessStackMemory);
|
||||
|
||||
return 1U; // Success
|
||||
}
|
||||
|
|
@ -0,0 +1,888 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.3.2
|
||||
* @date 27. May 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
|
||||
|
||||
/* CMSIS compiler control DSP macros */
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __ARM_FEATURE_DSP 1
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __memory_changed()
|
||||
#endif
|
||||
|
||||
/* ######################### Startup and Lowlevel Init ######################## */
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __main
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __Vectors
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
|
||||
#endif
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
__ISB();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,283 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.5
|
||||
* @date 02. February 2022
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,275 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.2
|
||||
* @date 25. May 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction,
|
||||
and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
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|
||||
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|
||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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"You" (or "Your") shall mean an individual or Legal Entity
|
||||
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|
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|
@ -0,0 +1,141 @@
|
|||
# CMSIS Version 5
|
||||
|
||||
[](https://github.com/ARM-software/CMSIS_5/releases/latest) [](https://arm-software.github.io/CMSIS_5/General/html/LICENSE.txt)
|
||||
|
||||
The branch *master* of this GitHub repository contains .
|
||||
The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html
|
||||
|
||||
Use [Issues](https://github.com/ARM-software/CMSIS_5#issues-and-labels) to provide feedback and report problems for CMSIS Version 5.
|
||||
|
||||
**Note:** The branch *develop* of this GitHub repository reflects our current state of development and is constantly updated. It gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions.
|
||||
|
||||
A [pre-built documentation](https://arm-software.github.io/CMSIS_5/develop/General/html/index.html) is updated from time to time, but may be also generated using the instructions under [Generate CMSIS Pack for Release](https://github.com/ARM-software/CMSIS_5#generate-cmsis-pack-for-release).
|
||||
|
||||
## Overview of CMSIS Components
|
||||
|
||||
The following is an list of all CMSIS components that are available.
|
||||
|
||||
| CMSIS-... | Target Processors | Description |
|
||||
|:----------|:--------------------|:-------------|
|
||||
|[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore | Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.|
|
||||
|[Core(A)](http://arm-software.github.io/CMSIS_5/Core_A/html/index.html)| Cortex-A5/A7/A9 | API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.|
|
||||
|[Driver](http://arm-software.github.io/CMSIS_5/Driver/html/index.html) | All Cortex-M, SecurCore | Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.|
|
||||
|[DSP](http://arm-software.github.io/CMSIS_5/DSP/html/index.html) | All Cortex-M | DSP library collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P.|
|
||||
|[NN](http://arm-software.github.io/CMSIS_5/NN/html/index.html) | All Cortex-M | Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.|
|
||||
|[RTOS v1](http://arm-software.github.io/CMSIS_5/RTOS/html/index.html) | Cortex-M0/M0+/M3/M4/M7 | Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.|
|
||||
|[RTOS v2](http://arm-software.github.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. |
|
||||
|[Pack](http://arm-software.github.io/CMSIS_5/Pack/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM). <br/>Is part of the [Open CMSIS Pack project](https://www.open-cmsis-pack.org). |
|
||||
|[Build](http://arm-software.github.io/CMSIS_5/Build/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | A set of tools, software frameworks, and work flows that improve productivity, for example with Continuous Integration (CI) support.<br/>Is replaced with the [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools). |
|
||||
|[SVD](http://arm-software.github.io/CMSIS_5/SVD/html/index.html) | All Cortex-M, SecurCore | Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.|
|
||||
|[DAP](http://arm-software.github.io/CMSIS_5/DAP/html/index.html) | All Cortex | Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. |
|
||||
|[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html) | All Cortex-M | Defines methods to describe system resources and to partition these resources into multiple projects and execution areas. |
|
||||
|
||||
## Implemented Enhancements
|
||||
- CMSIS-Pack generation with [shell script template](https://arm-software.github.io/CMSIS_5/Pack/html/bash_script.html) for Windows and Linux
|
||||
- CMSIS-Pack: [Git workflow](https://arm-software.github.io/CMSIS_5/Pack/html/element_repository.html) via Eclipse menu *Window - Preferences - CMSIS Packs - Manage Local Repositories* and [MDK](http://www.keil.com/support/man/docs/uv4/uv4_ca_packinst_repo.htm)
|
||||
- [CMSIS-Zone release 1.0](https://arm-software.github.io/CMSIS_5/Zone/html/index.html) with support for multi-processor, TrustZone, and MPU configuration
|
||||
- Support for Armv8.1M Architecture and Cortex-M55 (release in March 2020)
|
||||
- CMSIS-DSP is fully ported to SIMD for Cortex-M family (Armv8.1-M) and Cortex-A & Cortex-R with NEON, using the same APIs.
|
||||
|
||||
## Further Planned Enhancements
|
||||
- CMSIS-Pack:
|
||||
- System Description SDF Format: describe more complex debug topologies than with a Debug Description in a tool agnostic way
|
||||
- CPDSC project file format: allows project templates that are agnostic of an IDE
|
||||
- Minimize need for IDE specific settings: CMSIS-Pack supports IDE specific parameters. Analyze and minimize
|
||||
- CMSIS-Build: command-line driven make system for CMSIS-Pack based projects (to support CI tests)
|
||||
|
||||
For further details see also the [Slides of the Embedded World CMSIS Partner Meeting](https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS_Review_Meeting_2020.pdf).
|
||||
|
||||
## Other related GitHub repositories
|
||||
|
||||
| Repository | Description |
|
||||
|:--------------------------- |:--------------------------------------------------------- |
|
||||
| [cmsis-pack-eclipse](https://github.com/ARM-software/cmsis-pack-eclipse) | CMSIS-Pack Management for Eclipse reference implementation Pack support |
|
||||
| [CMSIS-FreeRTOS](https://github.com/arm-software/CMSIS-FreeRTOS) | CMSIS-RTOS adoption of FreeRTOS |
|
||||
| [CMSIS-Driver](https://github.com/arm-software/CMSIS-Driver) | Generic MCU driver implementations and templates for Ethernet MAC/PHY and Flash. |
|
||||
| [CMSIS-Driver_Validation](https://github.com/ARM-software/CMSIS-Driver_Validation) | CMSIS-Driver Validation can be used to verify CMSIS-Driver in a user system |
|
||||
| [CMSIS-Zone](https://github.com/ARM-software/CMSIS-Zone) | CMSIS-Zone Utility along with example projects and FreeMarker templates |
|
||||
| [NXP_LPC](https://github.com/ARM-software/NXP_LPC) | CMSIS Driver Implementations for the NXP LPC Microcontroller Series |
|
||||
| [mdk-packs](https://github.com/mdk-packs) | IoT cloud connectors as trail implementations for MDK (help us to make it generic)|
|
||||
| [trustedfirmware.org](https://www.trustedfirmware.org/) | Arm Trusted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.|
|
||||
|
||||
|
||||
## Directory Structure
|
||||
|
||||
| Directory | Content |
|
||||
|:-------------------- |:--------------------------------------------------------- |
|
||||
| CMSIS/Core | CMSIS-Core(M) related files (for release) |
|
||||
| CMSIS/Core_A | CMSIS-Core(A) related files (for release) |
|
||||
| CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release) |
|
||||
| CMSIS/DAP | CMSIS-DAP related files and examples |
|
||||
| CMSIS/Driver | CMSIS-Driver API headers and template files |
|
||||
| CMSIS/DSP | CMSIS-DSP related files |
|
||||
| CMSIS/NN | CMSIS-NN related files |
|
||||
| CMSIS/RTOS | RTOS v1 related files (for Cortex-M) |
|
||||
| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & Armv8-M) |
|
||||
| CMSIS/Pack | CMSIS-Pack examples and tutorials |
|
||||
| CMSIS/DoxyGen | Source of the documentation |
|
||||
| CMSIS/Utilities | Utility programs |
|
||||
|
||||
## Generate CMSIS Pack for Release
|
||||
|
||||
This GitHub development repository lacks pre-built libraries of various software components (RTOS, RTOS2).
|
||||
In order to generate a full pack one needs to have the build environment available to build these libraries.
|
||||
This causes some sort of inconvenience. Hence the pre-built libraries may be moved out into separate pack(s)
|
||||
in the future.
|
||||
|
||||
To build a complete CMSIS pack for installation the following additional tools are required:
|
||||
- **doxygen.exe** Version: 1.8.6 (Documentation Generator)
|
||||
- **mscgen.exe** Version: 0.20 (Message Sequence Chart Converter)
|
||||
- **7z.exe (7-Zip)** Version: 16.02 (File Archiver)
|
||||
|
||||
Using these tools, you can generate on a Windows PC:
|
||||
- **CMSIS Documentation** using the batch file **gen_doc.sh** (located in ./CMSIS/Doxygen).
|
||||
- **CMSIS Software Pack** using the batch file **gen_pack.sh** (located in ./CMSIS/Utilities).
|
||||
The bash script does not generate the documentation. The pre-built libraries for RTX4 and RTX5
|
||||
are not included within this repository.
|
||||
|
||||
The file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation.
|
||||
|
||||
## License
|
||||
|
||||
Arm CMSIS is licensed under Apache 2.0.
|
||||
|
||||
## Contributions and Pull Requests
|
||||
|
||||
Contributions are accepted under Apache 2.0. Only submit contributions where you have authored all of the code.
|
||||
|
||||
### Issues and Labels
|
||||
|
||||
Please feel free to raise an [issue on GitHub](https://github.com/ARM-software/CMSIS_5/issues)
|
||||
to report misbehavior (i.e. bugs) or start discussions about enhancements. This
|
||||
is your best way to interact directly with the maintenance team and the community.
|
||||
We encourage you to append implementation suggestions as this helps to decrease the
|
||||
workload of the very limited maintenance team.
|
||||
|
||||
We will be monitoring and responding to issues as best we can.
|
||||
Please attempt to avoid filing duplicates of open or closed items when possible.
|
||||
In the spirit of openness we will be tagging issues with the following:
|
||||
|
||||
- **bug** – We consider this issue to be a bug that will be investigated.
|
||||
|
||||
- **wontfix** - We appreciate this issue but decided not to change the current behavior.
|
||||
|
||||
- **enhancement** – Denotes something that will be implemented soon.
|
||||
|
||||
- **future** - Denotes something not yet schedule for implementation.
|
||||
|
||||
- **out-of-scope** - We consider this issue loosely related to CMSIS. It might by implemented outside of CMSIS. Let us know about your work.
|
||||
|
||||
- **question** – We have further questions to this issue. Please review and provide feedback.
|
||||
|
||||
- **documentation** - This issue is a documentation flaw that will be improved in future.
|
||||
|
||||
- **review** - This issue is under review. Please be patient.
|
||||
|
||||
- **DONE** - We consider this issue as resolved - please review and close it. In case of no further activity this issues will be closed after a week.
|
||||
|
||||
- **duplicate** - This issue is already addressed elsewhere, see comment with provided references.
|
||||
|
||||
- **Important Information** - We provide essential information regarding planned or resolved major enhancements.
|
||||
|
||||
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