Add fm3 porting.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1297 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong@gmail.com
parent
cabc797a2d
commit
91577f186e
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/**************************************************************************//**
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* @file core_cm3.c
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* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
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* @version V1.40
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* @date 18. February 2010
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*
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* @note
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* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h>
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/* define compiler specific symbols */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for ARM Compiler */
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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#elif defined ( __TASKING__ )
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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#endif
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/* ########################## Core Instruction Access ######################### */
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#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
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/**
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* @brief Reverse byte order (16 bit)
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in unsigned short value
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*/
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#if (__ARMCC_VERSION < 400677)
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__ASM uint32_t __REV16(uint16_t value)
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{
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rev16 r0, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Reverse byte order in signed short value with sign extension to integer
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*
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* @param value value to reverse
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* @return reversed value
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*
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* Reverse byte order in signed short value with sign extension to integer
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*/
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#if (__ARMCC_VERSION < 400677)
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__ASM int32_t __REVSH(int16_t value)
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{
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revsh r0, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Remove the exclusive lock created by ldrex
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*
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* Removes the exclusive lock which is created by ldrex.
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __CLREX(void)
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{
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clrex
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}
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#endif /* __ARMCC_VERSION */
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#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
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/* obsolete */
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#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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/* obsolete */
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#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
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/* obsolete */
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#endif
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/* ########################### Core Function Access ########################### */
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#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
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/**
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* @brief Return the Control Register value
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*
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* @return Control value
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*
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* Return the content of the control register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_CONTROL(void)
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{
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mrs r0, control
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Control Register value
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*
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* @param control Control value
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*
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* Set the control register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_CONTROL(uint32_t control)
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{
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msr control, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Get IPSR Register value
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*
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* @return uint32_t IPSR value
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*
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* return the content of the IPSR register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_IPSR(void)
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{
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mrs r0, ipsr
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Get APSR Register value
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*
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* @return uint32_t APSR value
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*
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* return the content of the APSR register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_APSR(void)
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{
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mrs r0, apsr
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Get xPSR Register value
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*
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* @return uint32_t xPSR value
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*
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* return the content of the xPSR register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_xPSR(void)
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{
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mrs r0, xpsr
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Process Stack Pointer
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*
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* @return ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_PSP(void)
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{
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mrs r0, psp
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param topOfProcStack Process Stack Pointer
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_PSP(uint32_t topOfProcStack)
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{
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msr psp, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Main Stack Pointer
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*
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* @return Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_MSP(void)
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{
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mrs r0, msp
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Main Stack Pointer
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*
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* @param topOfMainStack Main Stack Pointer
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_MSP(uint32_t mainStackPointer)
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{
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msr msp, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Base Priority value
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*
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* @return BasePriority
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*
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* Return the content of the base priority register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_BASEPRI(void)
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{
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mrs r0, basepri
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Base Priority value
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*
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* @param basePri BasePriority
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*
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* Set the base priority register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_BASEPRI(uint32_t basePri)
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{
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msr basepri, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Priority Mask value
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*
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* @return PriMask
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*
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* Return state of the priority mask bit from the priority mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_PRIMASK(void)
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{
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mrs r0, primask
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Priority Mask value
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*
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* @param priMask PriMask
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*
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* Set the priority mask bit in the priority mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_PRIMASK(uint32_t priMask)
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{
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msr primask, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Fault Mask value
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*
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* @return FaultMask
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*
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* Return the content of the fault mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM uint32_t __get_FAULTMASK(void)
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{
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mrs r0, faultmask
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Fault Mask value
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*
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* @param faultMask faultMask value
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*
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* Set the fault mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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__ASM void __set_FAULTMASK(uint32_t faultMask)
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{
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msr faultmask, r0
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bx lr
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the FPSCR value
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*
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* @return FloatingPointStatusControlRegister
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*
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* Return the content of the FPSCR register
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*/
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/**
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* @brief Set the FPSCR value
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*
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* @param fpscr FloatingPointStatusControlRegister
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*
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* Set the FPSCR register
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*/
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||||||
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#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
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||||||
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/* obsolete */
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||||||
|
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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||||||
|
/* obsolete */
|
||||||
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#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
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||||||
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/* obsolete */
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#endif
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File diff suppressed because it is too large
Load Diff
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|
@ -0,0 +1,912 @@
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/**************************************************************************//**
|
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|
* @file core_cmFunc.h
|
||||||
|
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||||
|
* @version V1.40
|
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|
* @date 16. February 2010
|
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|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
* processor based microcontrollers. This file can be freely distributed
|
||||||
|
* within development tools that are supporting such ARM based processors.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
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|
|
||||||
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#ifndef __CORE_CMFUNC_H__
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#define __CORE_CMFUNC_H__
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||||||
|
|
||||||
|
/* ########################### Core Function Access ########################### */
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||||
|
/* ARM armcc specific functions */
|
||||||
|
|
||||||
|
/**
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* @brief Enable IRQ Interrupts
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*
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* Enables IRQ interrupts by clearing the I-bit in the CPSR.
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* Can only be executed in Privileged modes.
|
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*/
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/* intrinsic void __enable_irq(); */
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/**
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* @brief Disable IRQ Interrupts
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*
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* Disables IRQ interrupts by setting the I-bit in the CPSR.
|
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* Can only be executed in Privileged modes.
|
||||||
|
*/
|
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/* intrinsic void __disable_irq(); */
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|
|
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|
/**
|
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* @brief Return the Control Register value
|
||||||
|
*
|
||||||
|
* @return Control value
|
||||||
|
*
|
||||||
|
* Return the content of the control register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern uint32_t __get_CONTROL(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
return(__regControl);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Control Register value
|
||||||
|
*
|
||||||
|
* @param control Control value
|
||||||
|
*
|
||||||
|
* Set the control register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern void __set_CONTROL(uint32_t control);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
__regControl = control;
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get IPSR Register value
|
||||||
|
*
|
||||||
|
* @return uint32_t IPSR value
|
||||||
|
*
|
||||||
|
* return the content of the IPSR register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern uint32_t __get_IPSR(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regIPSR __ASM("ipsr");
|
||||||
|
return(__regIPSR);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get APSR Register value
|
||||||
|
*
|
||||||
|
* @return uint32_t APSR value
|
||||||
|
*
|
||||||
|
* return the content of the APSR register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern uint32_t __get_APSR(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regAPSR __ASM("apsr");
|
||||||
|
return(__regAPSR);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get xPSR Register value
|
||||||
|
*
|
||||||
|
* @return uint32_t xPSR value
|
||||||
|
*
|
||||||
|
* return the content of the xPSR register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern uint32_t __get_xPSR(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regXPSR __ASM("xpsr");
|
||||||
|
return(__regXPSR);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @return ProcessStackPointer
|
||||||
|
*
|
||||||
|
* Return the actual process stack pointer
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern uint32_t __get_PSP(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
return(__regProcessStackPointer);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfProcStack Process Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value ProcessStackPointer to the MSP
|
||||||
|
* (process stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern void __set_PSP(uint32_t topOfProcStack);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
__regProcessStackPointer = topOfProcStack;
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @return Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Return the current value of the MSP (main stack pointer)
|
||||||
|
* Cortex processor register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern uint32_t __get_MSP(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
return(__regMainStackPointer);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfMainStack Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value mainStackPointer to the MSP
|
||||||
|
* (main stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern void __set_MSP(uint32_t topOfMainStack);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE void __set_MSP(uint32_t mainStackPointer)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
__regMainStackPointer = mainStackPointer;
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Priority Mask value
|
||||||
|
*
|
||||||
|
* @return PriMask
|
||||||
|
*
|
||||||
|
* Return state of the priority mask bit from the priority mask register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern uint32_t __get_PRIMASK(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
return(__regPriMask);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Priority Mask value
|
||||||
|
*
|
||||||
|
* @param priMask PriMask
|
||||||
|
*
|
||||||
|
* Set the priority mask bit in the priority mask register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern void __set_PRIMASK(uint32_t priMask);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
__regPriMask = (priMask);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable FIQ Interrupts
|
||||||
|
*
|
||||||
|
* Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable FIQ Interrupts
|
||||||
|
*
|
||||||
|
* Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Base Priority value
|
||||||
|
*
|
||||||
|
* @return BasePriority
|
||||||
|
*
|
||||||
|
* Return the content of the base priority register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern uint32_t __get_BASEPRI(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
return(__regBasePri);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Base Priority value
|
||||||
|
*
|
||||||
|
* @param basePri BasePriority
|
||||||
|
*
|
||||||
|
* Set the base priority register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern void __set_BASEPRI(uint32_t basePri);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE void __set_BASEPRI(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
__regBasePri = (basePri & 0xff);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Fault Mask value
|
||||||
|
*
|
||||||
|
* @return FaultMask
|
||||||
|
*
|
||||||
|
* Return the content of the fault mask register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern uint32_t __get_FAULTMASK(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
return(__regFaultMask);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Fault Mask value
|
||||||
|
*
|
||||||
|
* @param faultMask faultMask value
|
||||||
|
*
|
||||||
|
* Set the fault mask register
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern void __set_FAULTMASK(uint32_t faultMask);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
__regFaultMask = (faultMask & 1);
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M == 0x04)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the FPSCR value
|
||||||
|
*
|
||||||
|
* @return FloatingPointStatusControlRegister
|
||||||
|
*
|
||||||
|
* Return the content of the FPSCR register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1)
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
return(__regfpscr);
|
||||||
|
#else
|
||||||
|
return(0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the FPSCR value
|
||||||
|
*
|
||||||
|
* @param fpscr FloatingPointStatusControlRegister
|
||||||
|
*
|
||||||
|
* Set the FPSCR register
|
||||||
|
*/
|
||||||
|
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1)
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
__regfpscr = (fpscr);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M == 0x04) */
|
||||||
|
|
||||||
|
|
||||||
|
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
#if defined (__ICCARM__)
|
||||||
|
#include <intrinsics.h> /* IAR Intrinsics */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma diag_suppress=Pe940
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable IRQ Interrupts
|
||||||
|
*
|
||||||
|
* Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __enable_irq __enable_interrupt
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable IRQ Interrupts
|
||||||
|
*
|
||||||
|
* Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __disable_irq __disable_interrupt
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Control Register value
|
||||||
|
*
|
||||||
|
* @return Control value
|
||||||
|
*
|
||||||
|
* Return the content of the control register
|
||||||
|
*/
|
||||||
|
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Control Register value
|
||||||
|
*
|
||||||
|
* @param control Control value
|
||||||
|
*
|
||||||
|
* Set the control register
|
||||||
|
*/
|
||||||
|
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get IPSR Register value
|
||||||
|
*
|
||||||
|
* @return uint32_t IPSR value
|
||||||
|
*
|
||||||
|
* return the content of the IPSR register
|
||||||
|
*/
|
||||||
|
static uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
__ASM("mrs r0, ipsr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get APSR Register value
|
||||||
|
*
|
||||||
|
* @return uint32_t APSR value
|
||||||
|
*
|
||||||
|
* return the content of the APSR register
|
||||||
|
*/
|
||||||
|
/* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get xPSR Register value
|
||||||
|
*
|
||||||
|
* @return uint32_t xPSR value
|
||||||
|
*
|
||||||
|
* return the content of the xPSR register
|
||||||
|
*/
|
||||||
|
static uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @return ProcessStackPointer
|
||||||
|
*
|
||||||
|
* Return the actual process stack pointer
|
||||||
|
*/
|
||||||
|
static uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
__ASM("mrs r0, psp");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfProcStack Process Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value ProcessStackPointer to the MSP
|
||||||
|
* (process stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
static void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
__ASM("msr psp, r0");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @return Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Return the current value of the MSP (main stack pointer)
|
||||||
|
* Cortex processor register
|
||||||
|
*/
|
||||||
|
static uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
__ASM("mrs r0, msp");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfMainStack Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value mainStackPointer to the MSP
|
||||||
|
* (main stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
static void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
__ASM("msr msp, r0");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Priority Mask value
|
||||||
|
*
|
||||||
|
* @return PriMask
|
||||||
|
*
|
||||||
|
* Return state of the priority mask bit from the priority mask register
|
||||||
|
*/
|
||||||
|
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Priority Mask value
|
||||||
|
*
|
||||||
|
* @param priMask PriMask
|
||||||
|
*
|
||||||
|
* Set the priority mask bit in the priority mask register
|
||||||
|
*/
|
||||||
|
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable FIQ Interrupts
|
||||||
|
*
|
||||||
|
* Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable FIQ Interrupts
|
||||||
|
*
|
||||||
|
* Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Base Priority value
|
||||||
|
*
|
||||||
|
* @return BasePriority
|
||||||
|
*
|
||||||
|
* Return the content of the base priority register
|
||||||
|
*/
|
||||||
|
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Base Priority value
|
||||||
|
*
|
||||||
|
* @param basePri BasePriority
|
||||||
|
*
|
||||||
|
* Set the base priority register
|
||||||
|
*/
|
||||||
|
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Fault Mask value
|
||||||
|
*
|
||||||
|
* @return FaultMask
|
||||||
|
*
|
||||||
|
* Return the content of the fault mask register
|
||||||
|
*/
|
||||||
|
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Fault Mask value
|
||||||
|
*
|
||||||
|
* @param faultMask faultMask value
|
||||||
|
*
|
||||||
|
* Set the fault mask register
|
||||||
|
*/
|
||||||
|
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M == 0x04)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the FPSCR value
|
||||||
|
*
|
||||||
|
* @return FloatingPointStatusControlRegister
|
||||||
|
*
|
||||||
|
* Return the content of the FPSCR register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1)
|
||||||
|
/* not yet implemented */
|
||||||
|
return(0);
|
||||||
|
#else
|
||||||
|
return(0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the FPSCR value
|
||||||
|
*
|
||||||
|
* @param fpscr FloatingPointStatusControlRegister
|
||||||
|
*
|
||||||
|
* Set the FPSCR register
|
||||||
|
*/
|
||||||
|
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1)
|
||||||
|
/* not yet implemented */
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M == 0x04) */
|
||||||
|
|
||||||
|
#pragma diag_default=Pe940
|
||||||
|
|
||||||
|
|
||||||
|
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
/* GNU gcc specific functions */
|
||||||
|
/**
|
||||||
|
* @brief Enable IRQ Interrupts
|
||||||
|
*
|
||||||
|
* Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable IRQ Interrupts
|
||||||
|
*
|
||||||
|
* Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Control Register value
|
||||||
|
*
|
||||||
|
* @return Control value
|
||||||
|
*
|
||||||
|
* Return the content of the control register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Control Register value
|
||||||
|
*
|
||||||
|
* @param control Control value
|
||||||
|
*
|
||||||
|
* Set the control register
|
||||||
|
*/
|
||||||
|
static __INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get IPSR Register value
|
||||||
|
*
|
||||||
|
* @return uint32_t IPSR value
|
||||||
|
*
|
||||||
|
* return the content of the IPSR register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get APSR Register value
|
||||||
|
*
|
||||||
|
* @return uint32_t APSR value
|
||||||
|
*
|
||||||
|
* return the content of the APSR register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get xPSR Register value
|
||||||
|
*
|
||||||
|
* @return uint32_t xPSR value
|
||||||
|
*
|
||||||
|
* return the content of the xPSR register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @return ProcessStackPointer
|
||||||
|
*
|
||||||
|
* Return the actual process stack pointer
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) );
|
||||||
|
static __INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t result __ASM ("r0") = 0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, psp\n"
|
||||||
|
"BX lr \n" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfProcStack Process Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value ProcessStackPointer to the MSP
|
||||||
|
* (process stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
|
||||||
|
static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR psp, %0\n"
|
||||||
|
"BX lr \n" : : "r" (topOfProcStack) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @return Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Return the current value of the MSP (main stack pointer)
|
||||||
|
* Cortex processor register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) );
|
||||||
|
static __INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t result __ASM ("r0") = 0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, msp\n"
|
||||||
|
"BX lr \n" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfMainStack Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value mainStackPointer to the MSP
|
||||||
|
* (main stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
|
||||||
|
static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR msp, %0\n"
|
||||||
|
"BX lr \n" : : "r" (topOfMainStack) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Priority Mask value
|
||||||
|
*
|
||||||
|
* @return PriMask
|
||||||
|
*
|
||||||
|
* Return state of the priority mask bit from the priority mask register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Priority Mask value
|
||||||
|
*
|
||||||
|
* @param priMask PriMask
|
||||||
|
*
|
||||||
|
* Set the priority mask bit in the priority mask register
|
||||||
|
*/
|
||||||
|
static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable FIQ Interrupts
|
||||||
|
*
|
||||||
|
* Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable FIQ Interrupts
|
||||||
|
*
|
||||||
|
* Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
* Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Base Priority value
|
||||||
|
*
|
||||||
|
* @return BasePriority
|
||||||
|
*
|
||||||
|
* Return the content of the base priority register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Base Priority value
|
||||||
|
*
|
||||||
|
* @param basePri BasePriority
|
||||||
|
*
|
||||||
|
* Set the base priority register
|
||||||
|
*/
|
||||||
|
static __INLINE void __set_BASEPRI(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Fault Mask value
|
||||||
|
*
|
||||||
|
* @return FaultMask
|
||||||
|
*
|
||||||
|
* Return the content of the fault mask register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Fault Mask value
|
||||||
|
*
|
||||||
|
* @param faultMask faultMask value
|
||||||
|
*
|
||||||
|
* Set the fault mask register
|
||||||
|
*/
|
||||||
|
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M == 0x04)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the FPSCR value
|
||||||
|
*
|
||||||
|
* @return FloatingPointStatusControlRegister
|
||||||
|
*
|
||||||
|
* Return the content of the FPSCR register
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1)
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
#else
|
||||||
|
return(0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the FPSCR value
|
||||||
|
*
|
||||||
|
* @param fpscr FloatingPointStatusControlRegister
|
||||||
|
*
|
||||||
|
* Set the FPSCR register
|
||||||
|
*/
|
||||||
|
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1)
|
||||||
|
__ASM volatile ("MSR control, %0" : : "r" (fpscr) );
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M == 0x04) */
|
||||||
|
|
||||||
|
|
||||||
|
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||||||
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif // __CORE_CMFUNC_H__
|
||||||
|
|
@ -0,0 +1,684 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cmInstr.h
|
||||||
|
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||||
|
* @version V1.40
|
||||||
|
* @date 16. February 2010
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
* processor based microcontrollers. This file can be freely distributed
|
||||||
|
* within development tools that are supporting such ARM based processors.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __CORE_CMINSTR_H__
|
||||||
|
#define __CORE_CMINSTR_H__
|
||||||
|
|
||||||
|
/* ########################## Core Instruction Access ######################### */
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||||
|
/* ARM armcc specific functions */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief No Operation
|
||||||
|
*
|
||||||
|
* No Operation does nothing. This instruction can be used for code alignment
|
||||||
|
* purposes.
|
||||||
|
*/
|
||||||
|
#define __NOP __nop
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait For Interrupt
|
||||||
|
*
|
||||||
|
* Wait For Interrupt is a hint instruction that suspends execution until
|
||||||
|
* one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFI __wfi
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait For Event
|
||||||
|
*
|
||||||
|
* Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
* a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFE __wfe
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Send Event
|
||||||
|
*
|
||||||
|
* Send Event is a hint instruction. It causes an event to be signaled
|
||||||
|
* to the CPU.
|
||||||
|
*/
|
||||||
|
#define __SEV __sev
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Instruction Synchronization Barrier
|
||||||
|
*
|
||||||
|
* Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
* so that all instructions following the ISB are fetched from cache or
|
||||||
|
* memory, after the instruction has been completed
|
||||||
|
*/
|
||||||
|
#define __ISB() __isb(0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Data Synchronization Barrier
|
||||||
|
*
|
||||||
|
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
|
||||||
|
* The DSB operation completes when all explicit memory accesses before this
|
||||||
|
* instruction complete.
|
||||||
|
*/
|
||||||
|
#define __DSB() __dsb(0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Data Memory Barrier
|
||||||
|
*
|
||||||
|
* DMB ensures the apparent order of the explicit memory operations before
|
||||||
|
* and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
#define __DMB() __dmb(0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order (32 bit)
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in integer value
|
||||||
|
*/
|
||||||
|
#define __REV __rev
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order (16 bit)
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in unsigned short value
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400677)
|
||||||
|
extern uint32_t __REV16(uint16_t value);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400677) */
|
||||||
|
static __INLINE __ASM uint32_t __REV16(uint16_t value)
|
||||||
|
{
|
||||||
|
rev16 r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400677)
|
||||||
|
extern int32_t __REVSH(int16_t value);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400677) */
|
||||||
|
static __INLINE __ASM int32_t __REVSH(int16_t value)
|
||||||
|
{
|
||||||
|
revsh r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse bit order of value
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse bit order of value
|
||||||
|
*/
|
||||||
|
#define __RBIT __rbit
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 8 bit value
|
||||||
|
*/
|
||||||
|
#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 16 bit values
|
||||||
|
*/
|
||||||
|
#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 32 bit values
|
||||||
|
*/
|
||||||
|
#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 8 bit values
|
||||||
|
*/
|
||||||
|
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 16 bit values
|
||||||
|
*/
|
||||||
|
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 32 bit values
|
||||||
|
*/
|
||||||
|
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Remove the exclusive lock created by ldrex
|
||||||
|
*
|
||||||
|
* Removes the exclusive lock which is created by ldrex.
|
||||||
|
*/
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
extern void __CLREX(void);
|
||||||
|
#else /* (__ARMCC_VERSION >= 400000) */
|
||||||
|
#define __CLREX __clrex
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
#if defined (__ICCARM__)
|
||||||
|
#include <intrinsics.h> /* IAR Intrinsics */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma diag_suppress=Pe940
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief No Operation
|
||||||
|
*
|
||||||
|
* No Operation does nothing. This instruction can be used for code alignment
|
||||||
|
* purposes.
|
||||||
|
*/
|
||||||
|
#define __NOP __no_operation
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait For Interrupt
|
||||||
|
*
|
||||||
|
* Wait For Interrupt is a hint instruction that suspends execution until
|
||||||
|
* one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
static __INLINE void __WFI() { __ASM ("wfi"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait For Event
|
||||||
|
*
|
||||||
|
* Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
* a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
static __INLINE void __WFE() { __ASM ("wfe"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Send Event
|
||||||
|
*
|
||||||
|
* Send Event is a hint instruction. It causes an event to be signaled
|
||||||
|
* to the CPU.
|
||||||
|
*/
|
||||||
|
static __INLINE void __SEV() { __ASM ("sev"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Instruction Synchronization Barrier
|
||||||
|
*
|
||||||
|
* Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
* so that all instructions following the ISB are fetched from cache or
|
||||||
|
* memory, after the instruction has been completed
|
||||||
|
*/
|
||||||
|
/* intrinsic void __ISB(void) (see intrinsics.h */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Data Synchronization Barrier
|
||||||
|
*
|
||||||
|
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
|
||||||
|
* The DSB operation completes when all explicit memory accesses before this
|
||||||
|
* instruction complete.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __DSB(void) (see intrinsics.h */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Data Memory Barrier
|
||||||
|
*
|
||||||
|
* DMB ensures the apparent order of the explicit memory operations before
|
||||||
|
* and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __DMB(void) (see intrinsics.h */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order (32 bit)
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in integer value
|
||||||
|
*/
|
||||||
|
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order (16 bit)
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in unsigned short value
|
||||||
|
*/
|
||||||
|
static uint32_t __REV16(uint16_t value)
|
||||||
|
{
|
||||||
|
__ASM("rev16 r0, r0");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*/
|
||||||
|
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse bit order of value
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse bit order of value
|
||||||
|
*/
|
||||||
|
static uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM("rbit r0, r0");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 8 bit value
|
||||||
|
*/
|
||||||
|
static uint8_t __LDREXB(uint8_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("ldrexb r0, [r0]");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 16 bit values
|
||||||
|
*/
|
||||||
|
static uint16_t __LDREXH(uint16_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("ldrexh r0, [r0]");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 32 bit values
|
||||||
|
*/
|
||||||
|
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */
|
||||||
|
static uint32_t __LDREXW(uint32_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("ldrex r0, [r0]");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 8 bit values
|
||||||
|
*/
|
||||||
|
static uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("strexb r0, r0, [r1]");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 16 bit values
|
||||||
|
*/
|
||||||
|
static uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("strexh r0, r0, [r1]");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 32 bit values
|
||||||
|
*/
|
||||||
|
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */
|
||||||
|
static uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("strex r0, r0, [r1]");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Remove the exclusive lock created by ldrex
|
||||||
|
*
|
||||||
|
* Removes the exclusive lock which is created by ldrex.
|
||||||
|
*/
|
||||||
|
static __INLINE void __CLREX() { __ASM ("clrex"); }
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
#pragma diag_default=Pe940
|
||||||
|
|
||||||
|
|
||||||
|
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
/* GNU gcc specific functions */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief No Operation
|
||||||
|
*
|
||||||
|
* No Operation does nothing. This instruction can be used for code alignment
|
||||||
|
* purposes.
|
||||||
|
*/
|
||||||
|
static __INLINE void __NOP() { __ASM volatile ("nop"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait For Interrupt
|
||||||
|
*
|
||||||
|
* Wait For Interrupt is a hint instruction that suspends execution until
|
||||||
|
* one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
static __INLINE void __WFI() { __ASM volatile ("wfi"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait For Event
|
||||||
|
*
|
||||||
|
* Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
* a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
static __INLINE void __WFE() { __ASM volatile ("wfe"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Send Event
|
||||||
|
*
|
||||||
|
* Send Event is a hint instruction. It causes an event to be signaled
|
||||||
|
* to the CPU.
|
||||||
|
*/
|
||||||
|
static __INLINE void __SEV() { __ASM volatile ("sev"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Instruction Synchronization Barrier
|
||||||
|
*
|
||||||
|
* Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
* so that all instructions following the ISB are fetched from cache or
|
||||||
|
* memory, after the instruction has been completed
|
||||||
|
*/
|
||||||
|
static __INLINE void __ISB() { __ASM volatile ("isb"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Data Synchronization Barrier
|
||||||
|
*
|
||||||
|
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
|
||||||
|
* The DSB operation completes when all explicit memory accesses before this
|
||||||
|
* instruction complete.
|
||||||
|
*/
|
||||||
|
static __INLINE void __DSB() { __ASM volatile ("dsb"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Data Memory Barrier
|
||||||
|
*
|
||||||
|
* DMB ensures the apparent order of the explicit memory operations before
|
||||||
|
* and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
static __INLINE void __DMB() { __ASM volatile ("dmb"); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order (32 bit)
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in integer value
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __REV(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order (16 bit)
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in unsigned short value
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __REV16(uint16_t value)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*/
|
||||||
|
static __INLINE int32_t __REVSH(int16_t value)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse bit order of value
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse bit order of value
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 8 bit value
|
||||||
|
*/
|
||||||
|
static __INLINE uint8_t __LDREXB(uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint8_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 16 bit values
|
||||||
|
*/
|
||||||
|
static __INLINE uint16_t __LDREXH(uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint16_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 32 bit values
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __LDREXW(uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 8 bit values
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 16 bit values
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 32 bit values
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Remove the exclusive lock created by ldrex
|
||||||
|
*
|
||||||
|
* Removes the exclusive lock which is created by ldrex.
|
||||||
|
*/
|
||||||
|
static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||||||
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif // __CORE_CMINSTR_H__
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,111 @@
|
||||||
|
/************************************************************************/
|
||||||
|
/* (C) Fujitsu Semiconductor Europe GmbH */
|
||||||
|
/* */
|
||||||
|
/* The following software deliverable is intended for and must only be */
|
||||||
|
/* used for reference and in an evaluation laboratory environment. */
|
||||||
|
/* It is provided on an as-is basis without charge and is subject to */
|
||||||
|
/* alterations. */
|
||||||
|
/* It is the user’s obligation to fully test the software in its */
|
||||||
|
/* environment and to ensure proper functionality, qualification and */
|
||||||
|
/* compliance with component specifications. */
|
||||||
|
/* */
|
||||||
|
/* In the event the software deliverable includes the use of open */
|
||||||
|
/* source components, the provisions of the governing open source */
|
||||||
|
/* license agreement shall apply with respect to such software */
|
||||||
|
/* deliverable. */
|
||||||
|
/* FSEU does not warrant that the deliverables do not infringe any */
|
||||||
|
/* third party intellectual property right (IPR). In the event that */
|
||||||
|
/* the deliverables infringe a third party IPR it is the sole */
|
||||||
|
/* responsibility of the customer to obtain necessary licenses to */
|
||||||
|
/* continue the usage of the deliverable. */
|
||||||
|
/* */
|
||||||
|
/* To the maximum extent permitted by applicable law FSEU disclaims all */
|
||||||
|
/* warranties, whether express or implied, in particular, but not */
|
||||||
|
/* limited to, warranties of merchantability and fitness for a */
|
||||||
|
/* particular purpose for which the deliverable is not designated. */
|
||||||
|
/* */
|
||||||
|
/* To the maximum extent permitted by applicable law, FSEU's liability */
|
||||||
|
/* is restricted to intention and gross negligence. */
|
||||||
|
/* FSEU is not liable for consequential damages. */
|
||||||
|
/* */
|
||||||
|
/* (V1.4) */
|
||||||
|
/************************************************************************/
|
||||||
|
|
||||||
|
#include "mb9bf506r.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 80MHz : Master Clock
|
||||||
|
*/
|
||||||
|
const uint32_t SystemFrequency = 80000000UL;
|
||||||
|
|
||||||
|
uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */
|
||||||
|
uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */
|
||||||
|
uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */
|
||||||
|
uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */
|
||||||
|
uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Prototype of internal function
|
||||||
|
*/
|
||||||
|
static void ClockInit(void);
|
||||||
|
static void HwwdtDisable(void);
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Setup the microcontroller system
|
||||||
|
*/
|
||||||
|
void SystemInit (void)
|
||||||
|
{
|
||||||
|
HwwdtDisable(); /* Disable Hardware Watchdog */
|
||||||
|
ClockInit(); /* Initialize Clock */
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* Initialize Clock
|
||||||
|
*/
|
||||||
|
static void ClockInit(void)
|
||||||
|
{
|
||||||
|
/*set Main clock stabilization
|
||||||
|
wait time to 2ms*/
|
||||||
|
FM3_CRG->CSW_TMR = 0x79;
|
||||||
|
/*Enable Main Oscilator*/
|
||||||
|
FM3_CRG->SCM_CTL |= 1<<1;
|
||||||
|
/*Wait stabilization end*/
|
||||||
|
while(!(FM3_CRG->SCM_STR & 0x02));
|
||||||
|
|
||||||
|
/* sub CLK enable */
|
||||||
|
FM3_CRG->SCM_CTL |= 0x08;
|
||||||
|
while(!(FM3_CRG->SCM_STR & 0x08));
|
||||||
|
|
||||||
|
/*Set PLL stabilization
|
||||||
|
wait time to 512uS*/
|
||||||
|
FM3_CRG->PSW_TMR |= 2;
|
||||||
|
/*Set PLL to 80MHz*/
|
||||||
|
FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/
|
||||||
|
FM3_CRG->PLL_CTL2 = 19; /*N = 20*/
|
||||||
|
/*Enable PLL*/
|
||||||
|
FM3_CRG->SCM_CTL |= 0x10;
|
||||||
|
/*Set bus prescalers*/
|
||||||
|
FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/
|
||||||
|
FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/
|
||||||
|
FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/
|
||||||
|
FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/
|
||||||
|
/*Wait PLL stabilizatoin end*/
|
||||||
|
while(!(FM3_CRG->SCM_STR & 0x10));
|
||||||
|
/*Select PLL for main clock*/
|
||||||
|
FM3_CRG->SCM_CTL |= 2<<5;
|
||||||
|
/*Wait PLL to be connected*/
|
||||||
|
while((FM3_CRG->SCM_STR & 0xe0) != 0x40);
|
||||||
|
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* Stop HW Watchdog Timer
|
||||||
|
*/
|
||||||
|
static void HwwdtDisable(void)
|
||||||
|
{
|
||||||
|
/* UnLock (except WDG_CTL) */
|
||||||
|
FM3_HWWDT->WDG_LCK = 0x1ACCE551;
|
||||||
|
/* UnLock (WDG_CTL) */
|
||||||
|
FM3_HWWDT->WDG_LCK = 0xE5331AAE;
|
||||||
|
/* Disable WDG */
|
||||||
|
FM3_HWWDT->WDG_CTL = 0x00;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,71 @@
|
||||||
|
/************************************************************************/
|
||||||
|
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
|
||||||
|
/* */
|
||||||
|
/* The following software deliverable is intended for and must only be */
|
||||||
|
/* used for reference and in an evaluation laboratory environment. */
|
||||||
|
/* It is provided on an as-is basis without charge and is subject to */
|
||||||
|
/* alterations. */
|
||||||
|
/* It is the user's obligation to fully test the software in its */
|
||||||
|
/* environment and to ensure proper functionality, qualification and */
|
||||||
|
/* compliance with component specifications. */
|
||||||
|
/* */
|
||||||
|
/* In the event the software deliverable includes the use of open */
|
||||||
|
/* source components, the provisions of the governing open source */
|
||||||
|
/* license agreement shall apply with respect to such software */
|
||||||
|
/* deliverable. */
|
||||||
|
/* FSEU does not warrant that the deliverables do not infringe any */
|
||||||
|
/* third party intellectual property right (IPR). In the event that */
|
||||||
|
/* the deliverables infringe a third party IPR it is the sole */
|
||||||
|
/* responsibility of the customer to obtain necessary licenses to */
|
||||||
|
/* continue the usage of the deliverable. */
|
||||||
|
/* */
|
||||||
|
/* To the maximum extent permitted by applicable law FSEU disclaims all */
|
||||||
|
/* warranties, whether express or implied, in particular, but not */
|
||||||
|
/* limited to, warranties of merchantability and fitness for a */
|
||||||
|
/* particular purpose for which the deliverable is not designated. */
|
||||||
|
/* */
|
||||||
|
/* To the maximum extent permitted by applicable law, FSEU's liability */
|
||||||
|
/* is restricted to intentional misconduct and gross negligence. */
|
||||||
|
/* FSEU is not liable for consequential damages. */
|
||||||
|
/* */
|
||||||
|
/* (V1.5) */
|
||||||
|
/************************************************************************/
|
||||||
|
|
||||||
|
#ifndef _SYSTEM_MB9BF50X_H_
|
||||||
|
#define _SYSTEM_MB9BF50X_H_
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Initialize the system
|
||||||
|
*
|
||||||
|
* @param none
|
||||||
|
* @return none
|
||||||
|
*
|
||||||
|
* @brief Setup the microcontroller system.
|
||||||
|
* Initialize the System and update the SystemCoreClock variable.
|
||||||
|
*/
|
||||||
|
extern void SystemInit (void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Update SystemCoreClock variable
|
||||||
|
*
|
||||||
|
* @param none
|
||||||
|
* @return none
|
||||||
|
*
|
||||||
|
* @brief Updates the SystemCoreClock with current core Clock
|
||||||
|
* retrieved from cpu registers.
|
||||||
|
*/
|
||||||
|
extern void SystemCoreClockUpdate (void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __SYSTEM_MB9BF50X_H */
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
* File : application.c
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2011-02-24 Bernard the first version
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup FM3
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
int rt_application_init()
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
@ -0,0 +1,54 @@
|
||||||
|
/*
|
||||||
|
* File : board.c
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2011-02-24 Bernard first implementation
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
#include <mb9bf506r.h>
|
||||||
|
#include <core_cm3.h>
|
||||||
|
|
||||||
|
extern const uint32_t SystemFrequency;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup FM3
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*@{*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This is the timer interrupt service routine.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void rt_hw_timer_handler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
rt_tick_increase();
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function will initial LPC17xx board.
|
||||||
|
*/
|
||||||
|
void rt_hw_board_init()
|
||||||
|
{
|
||||||
|
/* init systick */
|
||||||
|
SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND - 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
/*
|
||||||
|
* File : board.h
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2009-09-22 Bernard add board.h to this bsp
|
||||||
|
* 2010-02-04 Magicoe add board.h to LPC176x bsp
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __BOARD_H__
|
||||||
|
#define __BOARD_H__
|
||||||
|
|
||||||
|
void rt_hw_board_init(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,474 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.0</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Extensions>
|
||||||
|
<cExt>*.c</cExt>
|
||||||
|
<aExt>*.s*; *.src; *.a*</aExt>
|
||||||
|
<oExt>*.obj</oExt>
|
||||||
|
<lExt>*.lib</lExt>
|
||||||
|
<tExt>*.txt; *.h; *.inc</tExt>
|
||||||
|
<pExt>*.plm</pExt>
|
||||||
|
<CppX>*.cpp</CppX>
|
||||||
|
</Extensions>
|
||||||
|
|
||||||
|
<DaveTm>
|
||||||
|
<dwLowDateTime>0</dwLowDateTime>
|
||||||
|
<dwHighDateTime>0</dwHighDateTime>
|
||||||
|
</DaveTm>
|
||||||
|
|
||||||
|
<Target>
|
||||||
|
<TargetName>RT-Thread FM3</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<CLKADS>4000000</CLKADS>
|
||||||
|
<OPTTT>
|
||||||
|
<gFlags>1</gFlags>
|
||||||
|
<BeepAtEnd>1</BeepAtEnd>
|
||||||
|
<RunSim>1</RunSim>
|
||||||
|
<RunTarget>0</RunTarget>
|
||||||
|
</OPTTT>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<FlashByte>65535</FlashByte>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
</OPTHX>
|
||||||
|
<OPTLEX>
|
||||||
|
<PageWidth>79</PageWidth>
|
||||||
|
<PageLength>66</PageLength>
|
||||||
|
<TabStop>8</TabStop>
|
||||||
|
<ListingPath>.\obj\</ListingPath>
|
||||||
|
</OPTLEX>
|
||||||
|
<ListingPage>
|
||||||
|
<CreateCListing>1</CreateCListing>
|
||||||
|
<CreateAListing>1</CreateAListing>
|
||||||
|
<CreateLListing>1</CreateLListing>
|
||||||
|
<CreateIListing>0</CreateIListing>
|
||||||
|
<AsmCond>1</AsmCond>
|
||||||
|
<AsmSymb>1</AsmSymb>
|
||||||
|
<AsmXref>0</AsmXref>
|
||||||
|
<CCond>1</CCond>
|
||||||
|
<CCode>0</CCode>
|
||||||
|
<CListInc>0</CListInc>
|
||||||
|
<CSymb>0</CSymb>
|
||||||
|
<LinkerCodeListing>0</LinkerCodeListing>
|
||||||
|
</ListingPage>
|
||||||
|
<OPTXL>
|
||||||
|
<LMap>1</LMap>
|
||||||
|
<LComments>1</LComments>
|
||||||
|
<LGenerateSymbols>1</LGenerateSymbols>
|
||||||
|
<LLibSym>1</LLibSym>
|
||||||
|
<LLines>1</LLines>
|
||||||
|
<LLocSym>1</LLocSym>
|
||||||
|
<LPubSym>1</LPubSym>
|
||||||
|
<LXref>0</LXref>
|
||||||
|
<LExpSel>0</LExpSel>
|
||||||
|
</OPTXL>
|
||||||
|
<OPTFL>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<IsCurrentTarget>1</IsCurrentTarget>
|
||||||
|
</OPTFL>
|
||||||
|
<CpuCode>255</CpuCode>
|
||||||
|
<DllOpt>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments>-MPU</SimDllArguments>
|
||||||
|
<SimDlgDllName>DCM.DLL</SimDlgDllName>
|
||||||
|
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments>-MPU</TargetDllArguments>
|
||||||
|
<TargetDlgDllName>TCM.DLL</TargetDlgDllName>
|
||||||
|
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||||
|
</DllOpt>
|
||||||
|
<DebugOpt>
|
||||||
|
<uSim>0</uSim>
|
||||||
|
<uTrg>1</uTrg>
|
||||||
|
<sLdApp>1</sLdApp>
|
||||||
|
<sGomain>1</sGomain>
|
||||||
|
<sRbreak>1</sRbreak>
|
||||||
|
<sRwatch>1</sRwatch>
|
||||||
|
<sRmem>1</sRmem>
|
||||||
|
<sRfunc>1</sRfunc>
|
||||||
|
<sRbox>1</sRbox>
|
||||||
|
<tLdApp>1</tLdApp>
|
||||||
|
<tGomain>1</tGomain>
|
||||||
|
<tRbreak>1</tRbreak>
|
||||||
|
<tRwatch>1</tRwatch>
|
||||||
|
<tRmem>1</tRmem>
|
||||||
|
<tRfunc>0</tRfunc>
|
||||||
|
<tRbox>1</tRbox>
|
||||||
|
<sRunDeb>0</sRunDeb>
|
||||||
|
<sLrtime>0</sLrtime>
|
||||||
|
<nTsel>7</nTsel>
|
||||||
|
<sDll></sDll>
|
||||||
|
<sDllPa></sDllPa>
|
||||||
|
<sDlgDll></sDlgDll>
|
||||||
|
<sDlgPa></sDlgPa>
|
||||||
|
<sIfile></sIfile>
|
||||||
|
<tDll></tDll>
|
||||||
|
<tDllPa></tDllPa>
|
||||||
|
<tDlgDll></tDlgDll>
|
||||||
|
<tDlgPa></tDlgPa>
|
||||||
|
<tIfile></tIfile>
|
||||||
|
<pMon>Segger\JL2CM3.dll</pMon>
|
||||||
|
</DebugOpt>
|
||||||
|
<DebugFlag>
|
||||||
|
<trace>0</trace>
|
||||||
|
<periodic>0</periodic>
|
||||||
|
<aLwin>0</aLwin>
|
||||||
|
<aCover>0</aCover>
|
||||||
|
<aSer1>0</aSer1>
|
||||||
|
<aSer2>0</aSer2>
|
||||||
|
<aPa>0</aPa>
|
||||||
|
<viewmode>0</viewmode>
|
||||||
|
<vrSel>0</vrSel>
|
||||||
|
<aSym>0</aSym>
|
||||||
|
<aTbox>0</aTbox>
|
||||||
|
<AscS1>0</AscS1>
|
||||||
|
<AscS2>0</AscS2>
|
||||||
|
<AscS3>0</AscS3>
|
||||||
|
<aSer3>0</aSer3>
|
||||||
|
<eProf>0</eProf>
|
||||||
|
<aLa>0</aLa>
|
||||||
|
<aPa1>0</aPa1>
|
||||||
|
<AscS4>0</AscS4>
|
||||||
|
<aSer4>0</aSer4>
|
||||||
|
<StkLoc>0</StkLoc>
|
||||||
|
<TrcWin>0</TrcWin>
|
||||||
|
<newCpu>0</newCpu>
|
||||||
|
<uProt>0</uProt>
|
||||||
|
</DebugFlag>
|
||||||
|
<LintExecutable></LintExecutable>
|
||||||
|
<LintConfigFile></LintConfigFile>
|
||||||
|
</TargetOption>
|
||||||
|
</Target>
|
||||||
|
|
||||||
|
<Group>
|
||||||
|
<GroupName>Startup</GroupName>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<cbSel>0</cbSel>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>1</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>0</TopLine>
|
||||||
|
<CurrentLine>0</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>.\application.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>application.c</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>2</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>0</TopLine>
|
||||||
|
<CurrentLine>0</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>.\board.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>board.c</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>3</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>0</TopLine>
|
||||||
|
<CurrentLine>0</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>.\startup.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>startup.c</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
</Group>
|
||||||
|
|
||||||
|
<Group>
|
||||||
|
<GroupName>Kernel</GroupName>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<cbSel>0</cbSel>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>2</GroupNumber>
|
||||||
|
<FileNumber>4</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>0</TopLine>
|
||||||
|
<CurrentLine>0</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\src\clock.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>clock.c</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>2</GroupNumber>
|
||||||
|
<FileNumber>5</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>1</TopLine>
|
||||||
|
<CurrentLine>1</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\src\device.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>device.c</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>2</GroupNumber>
|
||||||
|
<FileNumber>6</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>58</TopLine>
|
||||||
|
<CurrentLine>58</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\src\idle.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>idle.c</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>2</GroupNumber>
|
||||||
|
<FileNumber>7</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>0</TopLine>
|
||||||
|
<CurrentLine>0</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\src\ipc.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>ipc.c</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>2</GroupNumber>
|
||||||
|
<FileNumber>8</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
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|
||||||
|
</File>
|
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</Group>
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|
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|
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|
||||||
|
</File>
|
||||||
|
</Group>
|
||||||
|
|
||||||
|
</ProjectOpt>
|
||||||
|
|
@ -0,0 +1,515 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.1</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>RT-Thread FM3</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>MB9BF500R</Device>
|
||||||
|
<Vendor>Fujitsu Microelectronics</Vendor>
|
||||||
|
<Cpu>IRAM(0x20000000-0x20003FFF) IROM(0x00000000-0x0003FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3")</Cpu>
|
||||||
|
<FlashUtilSpec></FlashUtilSpec>
|
||||||
|
<StartupFile>"STARTUP\FUJITSU\MB9BF50x\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code")</StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BF50x_256 -FS00 -FL040000)</FlashDriverDll>
|
||||||
|
<DeviceId>5155</DeviceId>
|
||||||
|
<RegisterFile>MB9BF50x.h</RegisterFile>
|
||||||
|
<MemoryEnv></MemoryEnv>
|
||||||
|
<Cmp></Cmp>
|
||||||
|
<Asm></Asm>
|
||||||
|
<Linker></Linker>
|
||||||
|
<OHString></OHString>
|
||||||
|
<InfinionOptionDll></InfinionOptionDll>
|
||||||
|
<SLE66CMisc></SLE66CMisc>
|
||||||
|
<SLE66AMisc></SLE66AMisc>
|
||||||
|
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||||
|
<SFDFile></SFDFile>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath></BinPath>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
<LibPath></LibPath>
|
||||||
|
<RegisterFilePath>Fujitsu\MB9BF50x\</RegisterFilePath>
|
||||||
|
<DBRegisterFilePath>Fujitsu\MB9BF50x\</DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\obj\</OutputDirectory>
|
||||||
|
<OutputName>rtthread-fm3</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>0</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>0</BrowseInformation>
|
||||||
|
<ListingPath>.\obj\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
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|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
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|
||||||
|
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|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString></SVCSIdString>
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument></CustomArgument>
|
||||||
|
<IncludeLibraryModules></IncludeLibraryModules>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments>-MPU</SimDllArguments>
|
||||||
|
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments>-MPU</TargetDllArguments>
|
||||||
|
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
<Simulator>
|
||||||
|
<UseSimulator>0</UseSimulator>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>1</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||||
|
</Simulator>
|
||||||
|
<Target>
|
||||||
|
<UseTarget>1</UseTarget>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>0</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
</Target>
|
||||||
|
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||||
|
<TargetSelection>7</TargetSelection>
|
||||||
|
<SimDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
</SimDlls>
|
||||||
|
<TargetDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
<Driver>Segger\JL2CM3.dll</Driver>
|
||||||
|
</TargetDlls>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4102</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<Flash2>Segger\JL2CM3.dll</Flash2>
|
||||||
|
<Flash3></Flash3>
|
||||||
|
<Flash4></Flash4>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
|
<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M3"</AdsCpuType>
|
||||||
|
<RvctDeviceName></RvctDeviceName>
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
|
<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
<hadXRAM>0</hadXRAM>
|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>0</RvdsVP>
|
||||||
|
<hadIRAM2>0</hadIRAM2>
|
||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
|
<StupSel>8</StupSel>
|
||||||
|
<useUlib>1</useUlib>
|
||||||
|
<EndSel>0</EndSel>
|
||||||
|
<uLtcg>0</uLtcg>
|
||||||
|
<RoSelD>3</RoSelD>
|
||||||
|
<RwSelD>3</RwSelD>
|
||||||
|
<CodeSel>0</CodeSel>
|
||||||
|
<OptFeed>0</OptFeed>
|
||||||
|
<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
|
<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>1</Im1Chk>
|
||||||
|
<Im2Chk>0</Im2Chk>
|
||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm1>
|
||||||
|
<Ocm2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
|
<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x4000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x40000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x40000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x2000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector></RvctStartVector>
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>1</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>0</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>0</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath>.\CMSIS;.;..\..\libcpu\arm\fm3;..\..\include</IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
<NoWarn>0</NoWarn>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
<umfTarg>1</umfTarg>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>1</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange>0x00000000</TextAddressRange>
|
||||||
|
<DataAddressRange>0x10000000</DataAddressRange>
|
||||||
|
<ScatterFile></ScatterFile>
|
||||||
|
<IncludeLibs></IncludeLibs>
|
||||||
|
<IncludeLibsPath></IncludeLibsPath>
|
||||||
|
<Misc></Misc>
|
||||||
|
<LinkerInputFile></LinkerInputFile>
|
||||||
|
<DisabledWarnings></DisabledWarnings>
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
<Groups>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Startup</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>application.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>.\application.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>board.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>.\board.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>startup.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>.\startup.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Kernel</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>clock.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\clock.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>device.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\device.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>idle.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\idle.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>ipc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\ipc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>irq.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\irq.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>kservice.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\kservice.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>mem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\mem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>mempool.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\mempool.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>object.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\object.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>scheduler.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\scheduler.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>thread.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\thread.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>timer.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\src\timer.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>FM3</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>context_rvds.S</FileName>
|
||||||
|
<FileType>2</FileType>
|
||||||
|
<FilePath>..\..\libcpu\arm\fm3\context_rvds.S</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>fault_rvds.S</FileName>
|
||||||
|
<FileType>2</FileType>
|
||||||
|
<FilePath>..\..\libcpu\arm\fm3\fault_rvds.S</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>start_rvds.S</FileName>
|
||||||
|
<FileType>2</FileType>
|
||||||
|
<FilePath>..\..\libcpu\arm\fm3\start_rvds.S</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cpuport.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\libcpu\arm\fm3\cpuport.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>CMSIS</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>core_cm3.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>.\CMSIS\core_cm3.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>system_mb9bf50x.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>.\CMSIS\system_mb9bf50x.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
</Groups>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,64 @@
|
||||||
|
/* RT-Thread config file */
|
||||||
|
#ifndef __RTTHREAD_CFG_H__
|
||||||
|
#define __RTTHREAD_CFG_H__
|
||||||
|
|
||||||
|
/* RT_NAME_MAX*/
|
||||||
|
#define RT_NAME_MAX 4
|
||||||
|
|
||||||
|
/* RT_ALIGN_SIZE*/
|
||||||
|
#define RT_ALIGN_SIZE 4
|
||||||
|
|
||||||
|
/* PRIORITY_MAX */
|
||||||
|
#define RT_THREAD_PRIORITY_MAX 32
|
||||||
|
|
||||||
|
/* Tick per Second */
|
||||||
|
#define RT_TICK_PER_SECOND 100
|
||||||
|
|
||||||
|
/* SECTION: RT_DEBUG */
|
||||||
|
/* Thread Debug */
|
||||||
|
#define RT_DEBUG
|
||||||
|
#define RT_USING_OVERFLOW_CHECK
|
||||||
|
|
||||||
|
/* Using Hook */
|
||||||
|
#define RT_USING_HOOK
|
||||||
|
|
||||||
|
/* SECTION: IPC */
|
||||||
|
/* Using Semaphore */
|
||||||
|
#define RT_USING_SEMAPHORE
|
||||||
|
|
||||||
|
/* Using Mutex */
|
||||||
|
#define RT_USING_MUTEX
|
||||||
|
|
||||||
|
/* Using Event */
|
||||||
|
#define RT_USING_EVENT
|
||||||
|
|
||||||
|
/* Using MailBox */
|
||||||
|
#define RT_USING_MAILBOX
|
||||||
|
|
||||||
|
/* Using Message Queue */
|
||||||
|
#define RT_USING_MESSAGEQUEUE
|
||||||
|
|
||||||
|
/* SECTION: Memory Management */
|
||||||
|
/* Using Memory Pool Management*/
|
||||||
|
#define RT_USING_MEMPOOL
|
||||||
|
|
||||||
|
/* Using Dynamic Heap Management */
|
||||||
|
#define RT_USING_HEAP
|
||||||
|
|
||||||
|
/* Using Small MM */
|
||||||
|
#define RT_USING_SMALL_MEM
|
||||||
|
|
||||||
|
/* SECTION: Device System */
|
||||||
|
/* Using Device System */
|
||||||
|
#define RT_USING_DEVICE
|
||||||
|
/* RT_USING_UART */
|
||||||
|
#define RT_USING_UART0
|
||||||
|
#define RT_UART_RX_BUFFER_SIZE 64
|
||||||
|
|
||||||
|
/* SECTION: Console options */
|
||||||
|
#define RT_TINY_SIZE
|
||||||
|
#define RT_USING_CONSOLE
|
||||||
|
/* the buffer size of console */
|
||||||
|
#define RT_CONSOLEBUF_SIZE 128
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,104 @@
|
||||||
|
/*
|
||||||
|
* File : startup.c
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2011-02-24 Bernard first implementation
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup FM3
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*@{*/
|
||||||
|
|
||||||
|
extern int rt_application_init(void);
|
||||||
|
|
||||||
|
#ifdef __CC_ARM
|
||||||
|
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
#elif __ICCARM__
|
||||||
|
#pragma section="HEAP"
|
||||||
|
#else
|
||||||
|
extern int __bss_end;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function will startup RT-Thread RTOS.
|
||||||
|
*/
|
||||||
|
void rtthread_startup(void)
|
||||||
|
{
|
||||||
|
/* init board */
|
||||||
|
rt_hw_board_init();
|
||||||
|
|
||||||
|
/* show version */
|
||||||
|
rt_show_version();
|
||||||
|
|
||||||
|
/* init tick */
|
||||||
|
rt_system_tick_init();
|
||||||
|
|
||||||
|
/* init kernel object */
|
||||||
|
rt_system_object_init();
|
||||||
|
|
||||||
|
/* init timer system */
|
||||||
|
rt_system_timer_init();
|
||||||
|
|
||||||
|
#ifdef RT_USING_HEAP
|
||||||
|
#ifdef __CC_ARM
|
||||||
|
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
|
||||||
|
#elif __ICCARM__
|
||||||
|
rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
|
||||||
|
#else
|
||||||
|
/* init memory system */
|
||||||
|
rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* init scheduler system */
|
||||||
|
rt_system_scheduler_init();
|
||||||
|
|
||||||
|
#ifdef RT_USING_DEVICE
|
||||||
|
/* init all device */
|
||||||
|
rt_device_init_all();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* init application */
|
||||||
|
rt_application_init();
|
||||||
|
|
||||||
|
/* init timer thread */
|
||||||
|
rt_system_timer_thread_init();
|
||||||
|
|
||||||
|
/* init idle thread */
|
||||||
|
rt_thread_idle_init();
|
||||||
|
|
||||||
|
/* start scheduler */
|
||||||
|
rt_system_scheduler_start();
|
||||||
|
|
||||||
|
/* never reach here */
|
||||||
|
return ;
|
||||||
|
}
|
||||||
|
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
rt_uint32_t UNUSED level;
|
||||||
|
|
||||||
|
/* disable interrupt first */
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
|
||||||
|
/* startup RT-Thread RTOS */
|
||||||
|
rtthread_startup();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
* File : context_gcc.S
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2009-10-11 Bernard first version
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup STM32
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.syntax unified
|
||||||
|
.thumb
|
||||||
|
.text
|
||||||
|
|
||||||
|
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
|
||||||
|
.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
|
||||||
|
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
|
||||||
|
.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* rt_base_t rt_hw_interrupt_disable();
|
||||||
|
*/
|
||||||
|
.global rt_hw_interrupt_disable
|
||||||
|
.type rt_hw_interrupt_disable, %function
|
||||||
|
rt_hw_interrupt_disable:
|
||||||
|
MRS r0, PRIMASK
|
||||||
|
CPSID I
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void rt_hw_interrupt_enable(rt_base_t level);
|
||||||
|
*/
|
||||||
|
.global rt_hw_interrupt_enable
|
||||||
|
.type rt_hw_interrupt_enable, %function
|
||||||
|
rt_hw_interrupt_enable:
|
||||||
|
MSR PRIMASK, r0
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||||
|
* r0 --> from
|
||||||
|
* r1 --> to
|
||||||
|
*/
|
||||||
|
.global rt_hw_context_switch_interrupt
|
||||||
|
.type rt_hw_context_switch_interrupt, %function
|
||||||
|
.global rt_hw_context_switch
|
||||||
|
.type rt_hw_context_switch, %function
|
||||||
|
|
||||||
|
rt_hw_context_switch_interrupt:
|
||||||
|
rt_hw_context_switch:
|
||||||
|
/* set rt_thread_switch_interrput_flag to 1 */
|
||||||
|
LDR r2, =rt_thread_switch_interrput_flag
|
||||||
|
LDR r3, [r2]
|
||||||
|
CMP r3, #1
|
||||||
|
BEQ _reswitch
|
||||||
|
MOV r3, #1
|
||||||
|
STR r3, [r2]
|
||||||
|
|
||||||
|
LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
|
||||||
|
STR r0, [r2]
|
||||||
|
|
||||||
|
_reswitch:
|
||||||
|
LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
|
||||||
|
STR r1, [r2]
|
||||||
|
|
||||||
|
LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
|
||||||
|
LDR r1, =NVIC_PENDSVSET
|
||||||
|
STR r1, [r0]
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
/* r0 --> swith from thread stack
|
||||||
|
* r1 --> swith to thread stack
|
||||||
|
* psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
|
||||||
|
*/
|
||||||
|
.global rt_hw_pend_sv
|
||||||
|
.type rt_hw_pend_sv, %function
|
||||||
|
rt_hw_pend_sv:
|
||||||
|
/* disable interrupt to protect context switch */
|
||||||
|
MRS r2, PRIMASK
|
||||||
|
CPSID I
|
||||||
|
|
||||||
|
/* get rt_thread_switch_interrupt_flag */
|
||||||
|
LDR r0, =rt_thread_switch_interrput_flag
|
||||||
|
LDR r1, [r0]
|
||||||
|
CBZ r1, pendsv_exit /* pendsv already handled */
|
||||||
|
|
||||||
|
/* clear rt_thread_switch_interrput_flag to 0 */
|
||||||
|
MOV r1, #0x00
|
||||||
|
STR r1, [r0]
|
||||||
|
|
||||||
|
LDR r0, =rt_interrupt_from_thread
|
||||||
|
LDR r1, [r0]
|
||||||
|
CBZ r1, swtich_to_thread /* skip register save at the first time */
|
||||||
|
|
||||||
|
MRS r1, psp /* get from thread stack pointer */
|
||||||
|
STMFD r1!, {r4 - r11} /* push r4 - r11 register */
|
||||||
|
LDR r0, [r0]
|
||||||
|
STR r1, [r0] /* update from thread stack pointer */
|
||||||
|
|
||||||
|
swtich_to_thread:
|
||||||
|
LDR r1, =rt_interrupt_to_thread
|
||||||
|
LDR r1, [r1]
|
||||||
|
LDR r1, [r1] /* load thread stack pointer */
|
||||||
|
|
||||||
|
LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
|
||||||
|
MSR psp, r1 /* update stack pointer */
|
||||||
|
|
||||||
|
pendsv_exit:
|
||||||
|
/* restore interrupt */
|
||||||
|
MSR PRIMASK, r2
|
||||||
|
|
||||||
|
ORR lr, lr, #0x04
|
||||||
|
BX lr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void rt_hw_context_switch_to(rt_uint32 to);
|
||||||
|
* r0 --> to
|
||||||
|
*/
|
||||||
|
.global rt_hw_context_switch_to
|
||||||
|
.type rt_hw_context_switch_to, %function
|
||||||
|
rt_hw_context_switch_to:
|
||||||
|
LDR r1, =rt_interrupt_to_thread
|
||||||
|
STR r0, [r1]
|
||||||
|
|
||||||
|
/* set from thread to 0 */
|
||||||
|
LDR r1, =rt_interrupt_from_thread
|
||||||
|
MOV r0, #0x0
|
||||||
|
STR r0, [r1]
|
||||||
|
|
||||||
|
/* set interrupt flag to 1 */
|
||||||
|
LDR r1, =rt_thread_switch_interrput_flag
|
||||||
|
MOV r0, #1
|
||||||
|
STR r0, [r1]
|
||||||
|
|
||||||
|
/* set the PendSV exception priority */
|
||||||
|
LDR r0, =NVIC_SYSPRI2
|
||||||
|
LDR r1, =NVIC_PENDSV_PRI
|
||||||
|
LDR.W r2, [r0,#0x00] /* read */
|
||||||
|
ORR r1,r1,r2 /* modify */
|
||||||
|
STR r1, [r0] /* write-back */
|
||||||
|
|
||||||
|
LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
|
||||||
|
LDR r1, =NVIC_PENDSVSET
|
||||||
|
STR r1, [r0]
|
||||||
|
|
||||||
|
CPSIE I /* enable interrupts at processor level */
|
||||||
|
|
||||||
|
/* never reach here! */
|
||||||
|
|
||||||
|
/* compatible with old version */
|
||||||
|
.global rt_hw_interrupt_thread_switch
|
||||||
|
.type rt_hw_interrupt_thread_switch, %function
|
||||||
|
rt_hw_interrupt_thread_switch:
|
||||||
|
BX lr
|
||||||
|
NOP
|
||||||
|
|
@ -0,0 +1,163 @@
|
||||||
|
;/*
|
||||||
|
; * File : context_iar.S
|
||||||
|
; * This file is part of RT-Thread RTOS
|
||||||
|
; * COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||||
|
; *
|
||||||
|
; * The license and distribution terms for this file may be
|
||||||
|
; * found in the file LICENSE in this distribution or at
|
||||||
|
; * http://www.rt-thread.org/license/LICENSE
|
||||||
|
; *
|
||||||
|
; * Change Logs:
|
||||||
|
; * Date Author Notes
|
||||||
|
; * 2009-01-17 Bernard first version
|
||||||
|
; * 2009-09-27 Bernard add protect when contex switch occurs
|
||||||
|
; */
|
||||||
|
|
||||||
|
;/**
|
||||||
|
; * @addtogroup STM32
|
||||||
|
; */
|
||||||
|
;/*@{*/
|
||||||
|
|
||||||
|
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
|
||||||
|
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
|
||||||
|
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
|
||||||
|
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
|
||||||
|
|
||||||
|
SECTION .text:CODE(2)
|
||||||
|
THUMB
|
||||||
|
REQUIRE8
|
||||||
|
PRESERVE8
|
||||||
|
|
||||||
|
IMPORT rt_thread_switch_interrput_flag
|
||||||
|
IMPORT rt_interrupt_from_thread
|
||||||
|
IMPORT rt_interrupt_to_thread
|
||||||
|
|
||||||
|
;/*
|
||||||
|
; * rt_base_t rt_hw_interrupt_disable();
|
||||||
|
; */
|
||||||
|
EXPORT rt_hw_interrupt_disable
|
||||||
|
rt_hw_interrupt_disable:
|
||||||
|
MRS r0, PRIMASK
|
||||||
|
CPSID I
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
;/*
|
||||||
|
; * void rt_hw_interrupt_enable(rt_base_t level);
|
||||||
|
; */
|
||||||
|
EXPORT rt_hw_interrupt_enable
|
||||||
|
rt_hw_interrupt_enable:
|
||||||
|
MSR PRIMASK, r0
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
;/*
|
||||||
|
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||||
|
; * r0 --> from
|
||||||
|
; * r1 --> to
|
||||||
|
; */
|
||||||
|
EXPORT rt_hw_context_switch_interrupt
|
||||||
|
EXPORT rt_hw_context_switch
|
||||||
|
rt_hw_context_switch_interrupt:
|
||||||
|
rt_hw_context_switch:
|
||||||
|
; set rt_thread_switch_interrput_flag to 1
|
||||||
|
LDR r2, =rt_thread_switch_interrput_flag
|
||||||
|
LDR r3, [r2]
|
||||||
|
CMP r3, #1
|
||||||
|
BEQ _reswitch
|
||||||
|
MOV r3, #1
|
||||||
|
STR r3, [r2]
|
||||||
|
|
||||||
|
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
|
||||||
|
STR r0, [r2]
|
||||||
|
|
||||||
|
_reswitch
|
||||||
|
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
|
||||||
|
STR r1, [r2]
|
||||||
|
|
||||||
|
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
|
||||||
|
LDR r1, =NVIC_PENDSVSET
|
||||||
|
STR r1, [r0]
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
; r0 --> swith from thread stack
|
||||||
|
; r1 --> swith to thread stack
|
||||||
|
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
|
||||||
|
EXPORT rt_hw_pend_sv
|
||||||
|
rt_hw_pend_sv:
|
||||||
|
|
||||||
|
; disable interrupt to protect context switch
|
||||||
|
MRS r2, PRIMASK
|
||||||
|
CPSID I
|
||||||
|
|
||||||
|
; get rt_thread_switch_interrupt_flag
|
||||||
|
LDR r0, =rt_thread_switch_interrput_flag
|
||||||
|
LDR r1, [r0]
|
||||||
|
CBZ r1, pendsv_exit ; pendsv already handled
|
||||||
|
|
||||||
|
; clear rt_thread_switch_interrput_flag to 0
|
||||||
|
MOV r1, #0x00
|
||||||
|
STR r1, [r0]
|
||||||
|
|
||||||
|
LDR r0, =rt_interrupt_from_thread
|
||||||
|
LDR r1, [r0]
|
||||||
|
CBZ r1, swtich_to_thread ; skip register save at the first time
|
||||||
|
|
||||||
|
MRS r1, psp ; get from thread stack pointer
|
||||||
|
STMFD r1!, {r4 - r11} ; push r4 - r11 register
|
||||||
|
LDR r0, [r0]
|
||||||
|
STR r1, [r0] ; update from thread stack pointer
|
||||||
|
|
||||||
|
swtich_to_thread
|
||||||
|
LDR r1, =rt_interrupt_to_thread
|
||||||
|
LDR r1, [r1]
|
||||||
|
LDR r1, [r1] ; load thread stack pointer
|
||||||
|
|
||||||
|
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
|
||||||
|
MSR psp, r1 ; update stack pointer
|
||||||
|
|
||||||
|
pendsv_exit
|
||||||
|
; restore interrupt
|
||||||
|
MSR PRIMASK, r2
|
||||||
|
|
||||||
|
ORR lr, lr, #0x04
|
||||||
|
BX lr
|
||||||
|
|
||||||
|
;/*
|
||||||
|
; * void rt_hw_context_switch_to(rt_uint32 to);
|
||||||
|
; * r0 --> to
|
||||||
|
; */
|
||||||
|
EXPORT rt_hw_context_switch_to
|
||||||
|
rt_hw_context_switch_to:
|
||||||
|
LDR r1, =rt_interrupt_to_thread
|
||||||
|
STR r0, [r1]
|
||||||
|
|
||||||
|
; set from thread to 0
|
||||||
|
LDR r1, =rt_interrupt_from_thread
|
||||||
|
MOV r0, #0x0
|
||||||
|
STR r0, [r1]
|
||||||
|
|
||||||
|
; set interrupt flag to 1
|
||||||
|
LDR r1, =rt_thread_switch_interrput_flag
|
||||||
|
MOV r0, #1
|
||||||
|
STR r0, [r1]
|
||||||
|
|
||||||
|
; set the PendSV exception priority
|
||||||
|
LDR r0, =NVIC_SYSPRI2
|
||||||
|
LDR r1, =NVIC_PENDSV_PRI
|
||||||
|
LDR.W r2, [r0,#0x00] ; read
|
||||||
|
ORR r1,r1,r2 ; modify
|
||||||
|
STR r1, [r0] ; write-back
|
||||||
|
|
||||||
|
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
|
||||||
|
LDR r1, =NVIC_PENDSVSET
|
||||||
|
STR r1, [r0]
|
||||||
|
|
||||||
|
CPSIE I ; enable interrupts at processor level
|
||||||
|
|
||||||
|
; never reach here!
|
||||||
|
|
||||||
|
; compatible with old version
|
||||||
|
EXPORT rt_hw_interrupt_thread_switch
|
||||||
|
rt_hw_interrupt_thread_switch:
|
||||||
|
BX lr
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,162 @@
|
||||||
|
;/*
|
||||||
|
; * File : context_rvds.S
|
||||||
|
; * This file is part of RT-Thread RTOS
|
||||||
|
; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
|
||||||
|
; *
|
||||||
|
; * The license and distribution terms for this file may be
|
||||||
|
; * found in the file LICENSE in this distribution or at
|
||||||
|
; * http://www.rt-thread.org/license/LICENSE
|
||||||
|
; *
|
||||||
|
; * Change Logs:
|
||||||
|
; * Date Author Notes
|
||||||
|
; * 2011-02-23 Bernard first version
|
||||||
|
; */
|
||||||
|
|
||||||
|
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
|
||||||
|
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
|
||||||
|
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
|
||||||
|
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY, ALIGN=2
|
||||||
|
THUMB
|
||||||
|
REQUIRE8
|
||||||
|
PRESERVE8
|
||||||
|
|
||||||
|
IMPORT rt_thread_switch_interrput_flag
|
||||||
|
IMPORT rt_interrupt_from_thread
|
||||||
|
IMPORT rt_interrupt_to_thread
|
||||||
|
|
||||||
|
;/*
|
||||||
|
; * rt_base_t rt_hw_interrupt_disable();
|
||||||
|
; */
|
||||||
|
rt_hw_interrupt_disable PROC
|
||||||
|
EXPORT rt_hw_interrupt_disable
|
||||||
|
MRS r0, PRIMASK
|
||||||
|
CPSID I
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/*
|
||||||
|
; * void rt_hw_interrupt_enable(rt_base_t level);
|
||||||
|
; */
|
||||||
|
rt_hw_interrupt_enable PROC
|
||||||
|
EXPORT rt_hw_interrupt_enable
|
||||||
|
MSR PRIMASK, r0
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/*
|
||||||
|
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||||
|
; * r0 --> from
|
||||||
|
; * r1 --> to
|
||||||
|
; */
|
||||||
|
rt_hw_context_switch_interrupt
|
||||||
|
EXPORT rt_hw_context_switch_interrupt
|
||||||
|
rt_hw_context_switch PROC
|
||||||
|
EXPORT rt_hw_context_switch
|
||||||
|
|
||||||
|
; set rt_thread_switch_interrput_flag to 1
|
||||||
|
LDR r2, =rt_thread_switch_interrput_flag
|
||||||
|
LDR r3, [r2]
|
||||||
|
CMP r3, #1
|
||||||
|
BEQ _reswitch
|
||||||
|
MOV r3, #1
|
||||||
|
STR r3, [r2]
|
||||||
|
|
||||||
|
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
|
||||||
|
STR r0, [r2]
|
||||||
|
|
||||||
|
_reswitch
|
||||||
|
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
|
||||||
|
STR r1, [r2]
|
||||||
|
|
||||||
|
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
|
||||||
|
LDR r1, =NVIC_PENDSVSET
|
||||||
|
STR r1, [r0]
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; r0 --> swith from thread stack
|
||||||
|
; r1 --> swith to thread stack
|
||||||
|
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
|
||||||
|
rt_hw_pend_sv PROC
|
||||||
|
EXPORT rt_hw_pend_sv
|
||||||
|
|
||||||
|
; disable interrupt to protect context switch
|
||||||
|
MRS r2, PRIMASK
|
||||||
|
CPSID I
|
||||||
|
|
||||||
|
; get rt_thread_switch_interrupt_flag
|
||||||
|
LDR r0, =rt_thread_switch_interrput_flag
|
||||||
|
LDR r1, [r0]
|
||||||
|
CBZ r1, pendsv_exit ; pendsv already handled
|
||||||
|
|
||||||
|
; clear rt_thread_switch_interrput_flag to 0
|
||||||
|
MOV r1, #0x00
|
||||||
|
STR r1, [r0]
|
||||||
|
|
||||||
|
LDR r0, =rt_interrupt_from_thread
|
||||||
|
LDR r1, [r0]
|
||||||
|
CBZ r1, swtich_to_thread ; skip register save at the first time
|
||||||
|
|
||||||
|
MRS r1, psp ; get from thread stack pointer
|
||||||
|
STMFD r1!, {r4 - r11} ; push r4 - r11 register
|
||||||
|
LDR r0, [r0]
|
||||||
|
STR r1, [r0] ; update from thread stack pointer
|
||||||
|
|
||||||
|
swtich_to_thread
|
||||||
|
LDR r1, =rt_interrupt_to_thread
|
||||||
|
LDR r1, [r1]
|
||||||
|
LDR r1, [r1] ; load thread stack pointer
|
||||||
|
|
||||||
|
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
|
||||||
|
MSR psp, r1 ; update stack pointer
|
||||||
|
|
||||||
|
pendsv_exit
|
||||||
|
; restore interrupt
|
||||||
|
MSR PRIMASK, r2
|
||||||
|
|
||||||
|
ORR lr, lr, #0x04
|
||||||
|
BX lr
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/*
|
||||||
|
; * void rt_hw_context_switch_to(rt_uint32 to);
|
||||||
|
; * r0 --> to
|
||||||
|
; * this fucntion is used to perform the first thread switch
|
||||||
|
; */
|
||||||
|
rt_hw_context_switch_to PROC
|
||||||
|
EXPORT rt_hw_context_switch_to
|
||||||
|
; set to thread
|
||||||
|
LDR r1, =rt_interrupt_to_thread
|
||||||
|
STR r0, [r1]
|
||||||
|
|
||||||
|
; set from thread to 0
|
||||||
|
LDR r1, =rt_interrupt_from_thread
|
||||||
|
MOV r0, #0x0
|
||||||
|
STR r0, [r1]
|
||||||
|
|
||||||
|
; set interrupt flag to 1
|
||||||
|
LDR r1, =rt_thread_switch_interrput_flag
|
||||||
|
MOV r0, #1
|
||||||
|
STR r0, [r1]
|
||||||
|
|
||||||
|
; set the PendSV exception priority
|
||||||
|
LDR r0, =NVIC_SYSPRI2
|
||||||
|
LDR r1, =NVIC_PENDSV_PRI
|
||||||
|
LDR.W r2, [r0,#0x00] ; read
|
||||||
|
ORR r1,r1,r2 ; modify
|
||||||
|
STR r1, [r0] ; write-back
|
||||||
|
|
||||||
|
; trigger the PendSV exception (causes context switch)
|
||||||
|
LDR r0, =NVIC_INT_CTRL
|
||||||
|
LDR r1, =NVIC_PENDSVSET
|
||||||
|
STR r1, [r0]
|
||||||
|
|
||||||
|
; enable interrupts at processor level
|
||||||
|
CPSIE I
|
||||||
|
|
||||||
|
; never reach here!
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,122 @@
|
||||||
|
/*
|
||||||
|
* File : hwport.c
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2011-02-23 Bernard the first version
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#include <mb9bf506r.h>
|
||||||
|
#include <core_cm3.h>
|
||||||
|
|
||||||
|
/* switch flag on interrupt and thread pointer to save switch record */
|
||||||
|
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||||
|
rt_uint32_t rt_thread_switch_interrput_flag;
|
||||||
|
|
||||||
|
/* stack context in ARM Cortex-M3 */
|
||||||
|
struct stack_context
|
||||||
|
{
|
||||||
|
rt_uint32_t r0;
|
||||||
|
rt_uint32_t r1;
|
||||||
|
rt_uint32_t r2;
|
||||||
|
rt_uint32_t r3;
|
||||||
|
rt_uint32_t r12;
|
||||||
|
rt_uint32_t lr;
|
||||||
|
rt_uint32_t pc;
|
||||||
|
rt_uint32_t psr;
|
||||||
|
};
|
||||||
|
|
||||||
|
extern void rt_hw_interrupt_thread_switch(void);
|
||||||
|
extern void list_thread(void);
|
||||||
|
extern rt_thread_t rt_current_thread;
|
||||||
|
void rt_hw_hard_fault_exception(struct stack_context* contex)
|
||||||
|
{
|
||||||
|
rt_kprintf("psr: 0x%08x\n", contex->psr);
|
||||||
|
rt_kprintf(" pc: 0x%08x\n", contex->pc);
|
||||||
|
rt_kprintf(" lr: 0x%08x\n", contex->lr);
|
||||||
|
rt_kprintf("r12: 0x%08x\n", contex->r12);
|
||||||
|
rt_kprintf("r03: 0x%08x\n", contex->r3);
|
||||||
|
rt_kprintf("r02: 0x%08x\n", contex->r2);
|
||||||
|
rt_kprintf("r01: 0x%08x\n", contex->r1);
|
||||||
|
rt_kprintf("r00: 0x%08x\n", contex->r0);
|
||||||
|
|
||||||
|
if (rt_current_thread != RT_NULL)
|
||||||
|
{
|
||||||
|
rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
|
||||||
|
#ifdef RT_USING_FINSH
|
||||||
|
list_thread();
|
||||||
|
#endif
|
||||||
|
while (1);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rt_kprintf("hard fault on initialization\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* reset MCU
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void rt_hw_cpu_reset()
|
||||||
|
{
|
||||||
|
NVIC_SystemReset();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* shutdown CPU
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void rt_hw_cpu_shutdown()
|
||||||
|
{
|
||||||
|
rt_kprintf("shutdown...\n");
|
||||||
|
|
||||||
|
RT_ASSERT(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function will initialize thread stack
|
||||||
|
*
|
||||||
|
* @param tentry the entry of thread
|
||||||
|
* @param parameter the parameter of entry
|
||||||
|
* @param stack_addr the beginning stack address
|
||||||
|
* @param texit the function will be called when thread exit
|
||||||
|
*
|
||||||
|
* @return stack address
|
||||||
|
*/
|
||||||
|
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||||
|
rt_uint8_t *stack_addr, void *texit)
|
||||||
|
{
|
||||||
|
unsigned long *stk;
|
||||||
|
|
||||||
|
stk = (unsigned long *)stack_addr;
|
||||||
|
*(stk) = 0x01000000L; /* PSR */
|
||||||
|
*(--stk) = (unsigned long)tentry; /* entry point, pc */
|
||||||
|
*(--stk) = (unsigned long)texit; /* lr */
|
||||||
|
*(--stk) = 0; /* r12 */
|
||||||
|
*(--stk) = 0; /* r3 */
|
||||||
|
*(--stk) = 0; /* r2 */
|
||||||
|
*(--stk) = 0; /* r1 */
|
||||||
|
*(--stk) = (unsigned long)parameter; /* r0 : argument */
|
||||||
|
|
||||||
|
*(--stk) = 0; /* r11 */
|
||||||
|
*(--stk) = 0; /* r10 */
|
||||||
|
*(--stk) = 0; /* r9 */
|
||||||
|
*(--stk) = 0; /* r8 */
|
||||||
|
*(--stk) = 0; /* r7 */
|
||||||
|
*(--stk) = 0; /* r6 */
|
||||||
|
*(--stk) = 0; /* r5 */
|
||||||
|
*(--stk) = 0; /* r4 */
|
||||||
|
|
||||||
|
/* return task's current stack address */
|
||||||
|
return (rt_uint8_t *)stk;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*
|
||||||
|
* File : fault_gcc.S
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rt-thread.org/license/LICENSE
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2009-10-11 Bernard first version
|
||||||
|
*/
|
||||||
|
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.syntax unified
|
||||||
|
.thumb
|
||||||
|
.text
|
||||||
|
|
||||||
|
.global rt_hw_hard_fault
|
||||||
|
.type rt_hw_hard_fault, %function
|
||||||
|
rt_hw_hard_fault:
|
||||||
|
/* get current context */
|
||||||
|
MRS r0, psp /* get fault thread stack pointer */
|
||||||
|
PUSH {lr}
|
||||||
|
BL rt_hw_hard_fault_exception
|
||||||
|
POP {lr}
|
||||||
|
|
||||||
|
ORR lr, lr, #0x04
|
||||||
|
BX lr
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
;/*
|
||||||
|
; * File : fault_iar.S
|
||||||
|
; * This file is part of RT-Thread RTOS
|
||||||
|
; * COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||||
|
; *
|
||||||
|
; * The license and distribution terms for this file may be
|
||||||
|
; * found in the file LICENSE in this distribution or at
|
||||||
|
; * http://www.rt-thread.org/license/LICENSE
|
||||||
|
; *
|
||||||
|
; * Change Logs:
|
||||||
|
; * Date Author Notes
|
||||||
|
; * 2009-01-17 Bernard first version
|
||||||
|
; */
|
||||||
|
|
||||||
|
SECTION .text:CODE(2)
|
||||||
|
THUMB
|
||||||
|
REQUIRE8
|
||||||
|
PRESERVE8
|
||||||
|
|
||||||
|
IMPORT rt_hw_hard_fault_exception
|
||||||
|
|
||||||
|
EXPORT rt_hw_hard_fault
|
||||||
|
rt_hw_hard_fault:
|
||||||
|
|
||||||
|
; get current context
|
||||||
|
MRS r0, psp ; get fault thread stack pointer
|
||||||
|
PUSH {lr}
|
||||||
|
BL rt_hw_hard_fault_exception
|
||||||
|
POP {lr}
|
||||||
|
|
||||||
|
ORR lr, lr, #0x04
|
||||||
|
BX lr
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,35 @@
|
||||||
|
;/*
|
||||||
|
; * File : fault_rvds.S
|
||||||
|
; * This file is part of RT-Thread RTOS
|
||||||
|
; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
|
||||||
|
; *
|
||||||
|
; * The license and distribution terms for this file may be
|
||||||
|
; * found in the file LICENSE in this distribution or at
|
||||||
|
; * http://www.rt-thread.org/license/LICENSE
|
||||||
|
; *
|
||||||
|
; * Change Logs:
|
||||||
|
; * Date Author Notes
|
||||||
|
; * 2011-02-23 Bernard first version
|
||||||
|
; */
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY, ALIGN=2
|
||||||
|
THUMB
|
||||||
|
REQUIRE8
|
||||||
|
PRESERVE8
|
||||||
|
|
||||||
|
IMPORT rt_hw_hard_fault_exception
|
||||||
|
|
||||||
|
rt_hw_hard_fault PROC
|
||||||
|
EXPORT rt_hw_hard_fault
|
||||||
|
|
||||||
|
; get current context
|
||||||
|
MRS r0, psp ; get fault thread stack pointer
|
||||||
|
PUSH {lr}
|
||||||
|
BL rt_hw_hard_fault_exception
|
||||||
|
POP {lr}
|
||||||
|
|
||||||
|
ORR lr, lr, #0x04
|
||||||
|
BX lr
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,458 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32f10x_hd.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.1.2
|
||||||
|
* @date 09/28/2009
|
||||||
|
* @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address,
|
||||||
|
* - Configure external SRAM mounted on STM3210E-EVAL board
|
||||||
|
* to be used as data memory (optional, to be enabled by user)
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @copy
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
|
||||||
|
*/
|
||||||
|
.section .bss.init
|
||||||
|
.equ Stack_Size, 0x00000200
|
||||||
|
.space Stack_Size
|
||||||
|
Initial_spTop:
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
// .equ Initial_spTop, 0x20000200
|
||||||
|
.equ BootRAM, 0xF1E0F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
/* restore original stack pointer */
|
||||||
|
LDR r0, =Initial_spTop
|
||||||
|
MSR msp, r0
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word Initial_spTop
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word rt_hw_hard_fault
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word rt_hw_pend_sv
|
||||||
|
.word rt_hw_timer_handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.word USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.word CAN1_RX1_IRQHandler
|
||||||
|
.word CAN1_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_IRQHandler
|
||||||
|
.word TIM1_UP_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTCAlarm_IRQHandler
|
||||||
|
.word USBWakeUp_IRQHandler
|
||||||
|
.word TIM8_BRK_IRQHandler
|
||||||
|
.word TIM8_UP_IRQHandler
|
||||||
|
.word TIM8_TRG_COM_IRQHandler
|
||||||
|
.word TIM8_CC_IRQHandler
|
||||||
|
.word ADC3_IRQHandler
|
||||||
|
.word FSMC_IRQHandler
|
||||||
|
.word SDIO_IRQHandler
|
||||||
|
.word TIM5_IRQHandler
|
||||||
|
.word SPI3_IRQHandler
|
||||||
|
.word UART4_IRQHandler
|
||||||
|
.word UART5_IRQHandler
|
||||||
|
.word TIM6_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word DMA2_Channel1_IRQHandler
|
||||||
|
.word DMA2_Channel2_IRQHandler
|
||||||
|
.word DMA2_Channel3_IRQHandler
|
||||||
|
.word DMA2_Channel4_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||||
|
STM32F10x High Density devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SCE_IRQHandler
|
||||||
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTCAlarm_IRQHandler
|
||||||
|
.thumb_set RTCAlarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBWakeUp_IRQHandler
|
||||||
|
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FSMC_IRQHandler
|
||||||
|
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDIO_IRQHandler
|
||||||
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_IRQHandler
|
||||||
|
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||||
|
|
@ -0,0 +1,485 @@
|
||||||
|
;/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f10x_hd.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V3.0.0
|
||||||
|
;* Date : 04/06/2009
|
||||||
|
;* Description : STM32F10x High Density Devices vector table for EWARM5.x
|
||||||
|
;* toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == __iar_program_start,
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address,
|
||||||
|
;* - Configure external SRAM mounted on STM3210E-EVAL board
|
||||||
|
;* to be used as data memory (optional, to be enabled by user)
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||||
|
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||||
|
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||||
|
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||||
|
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
;*******************************************************************************/
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; The modules in this file are included in the libraries, and may be replaced
|
||||||
|
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||||
|
; a user defined start symbol.
|
||||||
|
; To override the cstartup defined in the library, simply add your modified
|
||||||
|
; version to the workbench project.
|
||||||
|
;
|
||||||
|
; The vector table is normally located at address 0.
|
||||||
|
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||||
|
; The name "__vector_table" has special meaning for C-SPY:
|
||||||
|
; it is where the SP start value is found, and the NVIC vector
|
||||||
|
; table register (VTOR) is initialized to this address if != 0.
|
||||||
|
;
|
||||||
|
; Cortex-M version
|
||||||
|
;
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; ICODE is the same segment as cstartup. By placing __low_level_init
|
||||||
|
;; in the same segment, we make sure it can be reached with BL. */
|
||||||
|
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
SECTION .icode:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
IMPORT rt_hw_hard_fault
|
||||||
|
IMPORT rt_hw_pend_sv
|
||||||
|
IMPORT rt_hw_timer_handler
|
||||||
|
|
||||||
|
PUBLIC __low_level_init
|
||||||
|
|
||||||
|
PUBWEAK SystemInit_ExtMemCtl
|
||||||
|
SECTION .text:CODE:REORDER(2)
|
||||||
|
THUMB
|
||||||
|
SystemInit_ExtMemCtl
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
__low_level_init:
|
||||||
|
|
||||||
|
;; Initialize hardware.
|
||||||
|
LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller
|
||||||
|
MOV R11, LR
|
||||||
|
BLX R0
|
||||||
|
LDR R1, =sfe(CSTACK) ; restore original stack pointer
|
||||||
|
MSR MSP, R1
|
||||||
|
MOV R0,#1
|
||||||
|
;; Return with BX to be independent of mode of caller
|
||||||
|
BX R11
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK)
|
||||||
|
DCD __iar_program_start
|
||||||
|
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD rt_hw_hard_fault ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD rt_hw_pend_sv ; PendSV Handler
|
||||||
|
DCD rt_hw_timer_handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||||
|
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||||
|
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||||
|
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup from suspend
|
||||||
|
DCD TIM8_BRK_IRQHandler ; TIM8 Break
|
||||||
|
DCD TIM8_UP_IRQHandler ; TIM8 Update
|
||||||
|
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
|
||||||
|
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||||
|
DCD ADC3_IRQHandler ; ADC3
|
||||||
|
DCD FSMC_IRQHandler ; FSMC
|
||||||
|
DCD SDIO_IRQHandler ; SDIO
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_IRQHandler ; TIM6
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||||
|
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||||
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||||
|
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||||
|
; for STM32F10x Connectivity line devices
|
||||||
|
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
|
||||||
|
DCD ETH_IRQHandler ; Ethernet
|
||||||
|
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||||
|
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||||
|
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||||
|
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||||
|
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
PUBWEAK WWDG_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
WWDG_IRQHandler
|
||||||
|
B WWDG_IRQHandler
|
||||||
|
PUBWEAK PVD_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
PVD_IRQHandler
|
||||||
|
B PVD_IRQHandler
|
||||||
|
PUBWEAK TAMPER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
B TAMPER_IRQHandler
|
||||||
|
PUBWEAK RTC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
RTC_IRQHandler
|
||||||
|
B RTC_IRQHandler
|
||||||
|
PUBWEAK FLASH_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
FLASH_IRQHandler
|
||||||
|
B FLASH_IRQHandler
|
||||||
|
PUBWEAK RCC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
RCC_IRQHandler
|
||||||
|
B RCC_IRQHandler
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
PUBWEAK DMA1_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
B DMA1_Channel1_IRQHandler
|
||||||
|
PUBWEAK DMA1_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
B DMA1_Channel2_IRQHandler
|
||||||
|
PUBWEAK DMA1_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
B DMA1_Channel3_IRQHandler
|
||||||
|
PUBWEAK DMA1_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
B DMA1_Channel4_IRQHandler
|
||||||
|
PUBWEAK DMA1_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
B DMA1_Channel5_IRQHandler
|
||||||
|
PUBWEAK DMA1_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
B DMA1_Channel6_IRQHandler
|
||||||
|
PUBWEAK DMA1_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
B DMA1_Channel7_IRQHandler
|
||||||
|
PUBWEAK ADC1_2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ADC1_2_IRQHandler
|
||||||
|
B ADC1_2_IRQHandler
|
||||||
|
PUBWEAK USB_HP_CAN1_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USB_HP_CAN1_TX_IRQHandler
|
||||||
|
B USB_HP_CAN1_TX_IRQHandler
|
||||||
|
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
B USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
PUBWEAK CAN1_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
B CAN1_RX1_IRQHandler
|
||||||
|
PUBWEAK CAN1_SCE_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
CAN1_SCE_IRQHandler
|
||||||
|
B CAN1_SCE_IRQHandler
|
||||||
|
PUBWEAK EXTI9_5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
B EXTI9_5_IRQHandler
|
||||||
|
PUBWEAK TIM1_BRK_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
B TIM1_BRK_IRQHandler
|
||||||
|
PUBWEAK TIM1_UP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
B TIM1_UP_IRQHandler
|
||||||
|
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
B TIM1_TRG_COM_IRQHandler
|
||||||
|
PUBWEAK TIM1_CC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
B TIM1_CC_IRQHandler
|
||||||
|
PUBWEAK TIM2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM2_IRQHandler
|
||||||
|
B TIM2_IRQHandler
|
||||||
|
PUBWEAK TIM3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM3_IRQHandler
|
||||||
|
B TIM3_IRQHandler
|
||||||
|
PUBWEAK TIM4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM4_IRQHandler
|
||||||
|
B TIM4_IRQHandler
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
PUBWEAK USART3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USART3_IRQHandler
|
||||||
|
B USART3_IRQHandler
|
||||||
|
PUBWEAK EXTI15_10_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
B EXTI15_10_IRQHandler
|
||||||
|
PUBWEAK RTCAlarm_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
RTCAlarm_IRQHandler
|
||||||
|
B RTCAlarm_IRQHandler
|
||||||
|
PUBWEAK OTG_FS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
B OTG_FS_WKUP_IRQHandler
|
||||||
|
PUBWEAK TIM8_BRK_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM8_BRK_IRQHandler
|
||||||
|
B TIM8_BRK_IRQHandler
|
||||||
|
PUBWEAK TIM8_UP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM8_UP_IRQHandler
|
||||||
|
B TIM8_UP_IRQHandler
|
||||||
|
PUBWEAK TIM8_TRG_COM_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM8_TRG_COM_IRQHandler
|
||||||
|
B TIM8_TRG_COM_IRQHandler
|
||||||
|
PUBWEAK TIM8_CC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM8_CC_IRQHandler
|
||||||
|
B TIM8_CC_IRQHandler
|
||||||
|
PUBWEAK ADC3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ADC3_IRQHandler
|
||||||
|
B ADC3_IRQHandler
|
||||||
|
PUBWEAK FSMC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
FSMC_IRQHandler
|
||||||
|
B FSMC_IRQHandler
|
||||||
|
PUBWEAK SDIO_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SDIO_IRQHandler
|
||||||
|
B SDIO_IRQHandler
|
||||||
|
PUBWEAK TIM5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM5_IRQHandler
|
||||||
|
B TIM5_IRQHandler
|
||||||
|
PUBWEAK SPI3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SPI3_IRQHandler
|
||||||
|
B SPI3_IRQHandler
|
||||||
|
PUBWEAK UART4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
UART4_IRQHandler
|
||||||
|
B UART4_IRQHandler
|
||||||
|
PUBWEAK UART5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
UART5_IRQHandler
|
||||||
|
B UART5_IRQHandler
|
||||||
|
PUBWEAK TIM6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM6_IRQHandler
|
||||||
|
B TIM6_IRQHandler
|
||||||
|
PUBWEAK TIM7_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIM7_IRQHandler
|
||||||
|
B TIM7_IRQHandler
|
||||||
|
PUBWEAK DMA2_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA2_Channel1_IRQHandler
|
||||||
|
B DMA2_Channel1_IRQHandler
|
||||||
|
PUBWEAK DMA2_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA2_Channel2_IRQHandler
|
||||||
|
B DMA2_Channel2_IRQHandler
|
||||||
|
PUBWEAK DMA2_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA2_Channel3_IRQHandler
|
||||||
|
B DMA2_Channel3_IRQHandler
|
||||||
|
PUBWEAK DMA2_Channel4_5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA2_Channel4_5_IRQHandler
|
||||||
|
B DMA2_Channel4_5_IRQHandler
|
||||||
|
|
||||||
|
; for STM32F10x Connectivity line devices
|
||||||
|
PUBWEAK DMA2_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA2_Channel5_IRQHandler
|
||||||
|
B DMA2_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ETH_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ETH_IRQHandler
|
||||||
|
B ETH_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ETH_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ETH_WKUP_IRQHandler
|
||||||
|
B ETH_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN2_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
CAN2_TX_IRQHandler
|
||||||
|
B CAN2_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN2_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
CAN2_RX0_IRQHandler
|
||||||
|
B CAN2_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN2_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
CAN2_RX1_IRQHandler
|
||||||
|
B CAN2_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN2_SCE_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
CAN2_SCE_IRQHandler
|
||||||
|
B CAN2_SCE_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_FS_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
B OTG_FS_IRQHandler
|
||||||
|
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,287 @@
|
||||||
|
; /*
|
||||||
|
; * File : start_rvds.s
|
||||||
|
; * This file is part of RT-Thread RTOS
|
||||||
|
; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
|
||||||
|
; *
|
||||||
|
; * The license and distribution terms for this file may be
|
||||||
|
; * found in the file LICENSE in this distribution or at
|
||||||
|
; * http://www.rt-thread.org/license/LICENSE
|
||||||
|
; *
|
||||||
|
; * Change Logs:
|
||||||
|
; * Date Author Notes
|
||||||
|
; * 2011-02-23 Bernard first implementation
|
||||||
|
; */
|
||||||
|
|
||||||
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
; Note: RT-Thread not use malloc/free in Keil MDK, therefore the heap size is 0.
|
||||||
|
Heap_Size EQU 0x00000000
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
IMPORT rt_hw_hard_fault
|
||||||
|
IMPORT rt_hw_pend_sv
|
||||||
|
IMPORT rt_hw_timer_handler
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD rt_hw_hard_fault ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD rt_hw_pend_sv ; PendSV Handler
|
||||||
|
DCD rt_hw_timer_handler ; SysTick Handler
|
||||||
|
|
||||||
|
DCD CSV_Handler ; 0: Clock Super Visor
|
||||||
|
DCD SWDT_Handler ; 1: Software Watchdog Timer
|
||||||
|
DCD LVD_Handler ; 2: Low Voltage Detector
|
||||||
|
DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
|
||||||
|
DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
|
||||||
|
DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
|
||||||
|
DCD DT_Handler ; 6: Dual Timer / Quad Decoder
|
||||||
|
DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
|
||||||
|
DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
|
||||||
|
DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
|
||||||
|
DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
|
||||||
|
DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
|
||||||
|
DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
|
||||||
|
DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
|
||||||
|
DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
|
||||||
|
DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
|
||||||
|
DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
|
||||||
|
DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
|
||||||
|
DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
|
||||||
|
DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
|
||||||
|
DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
|
||||||
|
DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
|
||||||
|
DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
|
||||||
|
DCD PPG_Handler ; 23: PPG
|
||||||
|
DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
|
||||||
|
DCD ADC0_IRQHandler ; 25: ADC0
|
||||||
|
DCD ADC1_IRQHandler ; 26: ADC1
|
||||||
|
DCD ADC2_IRQHandler ; 27: ADC2
|
||||||
|
DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
|
||||||
|
DCD MFT_IPC_IRQHandler ; 29: Input Capture
|
||||||
|
DCD MFT_OPC_IRQHandler ; 30: Output Compare
|
||||||
|
DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
|
||||||
|
DCD CAN0_IRQHandler ; 32: CAN ch.0
|
||||||
|
DCD CAN1_IRQHandler ; 33: CAN ch.1
|
||||||
|
DCD USBF_Handler ; 34: USB Function
|
||||||
|
DCD USB_Handler ; 35: USB Function / USB HOST
|
||||||
|
DCD DummyHandler ; 36: Reserved
|
||||||
|
DCD DummyHandler ; 37: Reserved
|
||||||
|
DCD DMAC0_Handler ; 38: DMAC ch.0
|
||||||
|
DCD DMAC1_Handler ; 39: DMAC ch.1
|
||||||
|
DCD DMAC2_Handler ; 40: DMAC ch.2
|
||||||
|
DCD DMAC3_Handler ; 41: DMAC ch.3
|
||||||
|
DCD DMAC4_Handler ; 42: DMAC ch.4
|
||||||
|
DCD DMAC5_Handler ; 43: DMAC ch.5
|
||||||
|
DCD DMAC6_Handler ; 44: DMAC ch.6
|
||||||
|
DCD DMAC7_Handler ; 45: DMAC ch.7
|
||||||
|
DCD DummyHandler ; 46: Reserved
|
||||||
|
DCD DummyHandler ; 47: Reserved
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler routine
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R1, = __initial_sp ; restore original stack pointer
|
||||||
|
MSR MSP, R1
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT CSV_Handler [WEAK]
|
||||||
|
EXPORT SWDT_Handler [WEAK]
|
||||||
|
EXPORT LVD_Handler [WEAK]
|
||||||
|
EXPORT MFT_WG_IRQHandler [WEAK]
|
||||||
|
EXPORT INT0_7_Handler [WEAK]
|
||||||
|
EXPORT INT8_15_Handler [WEAK]
|
||||||
|
EXPORT DT_Handler [WEAK]
|
||||||
|
EXPORT MFS0RX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS0TX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS1RX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS1TX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS2RX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS2TX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS3RX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS3TX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS4RX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS4TX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS5RX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS5TX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS6RX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS6TX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS7RX_IRQHandler [WEAK]
|
||||||
|
EXPORT MFS7TX_IRQHandler [WEAK]
|
||||||
|
EXPORT PPG_Handler [WEAK]
|
||||||
|
EXPORT TIM_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC0_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC2_IRQHandler [WEAK]
|
||||||
|
EXPORT MFT_FRT_IRQHandler [WEAK]
|
||||||
|
EXPORT MFT_IPC_IRQHandler [WEAK]
|
||||||
|
EXPORT MFT_OPC_IRQHandler [WEAK]
|
||||||
|
EXPORT BT_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_IRQHandler [WEAK]
|
||||||
|
EXPORT USBF_Handler [WEAK]
|
||||||
|
EXPORT USB_Handler [WEAK]
|
||||||
|
EXPORT DMAC0_Handler [WEAK]
|
||||||
|
EXPORT DMAC1_Handler [WEAK]
|
||||||
|
EXPORT DMAC2_Handler [WEAK]
|
||||||
|
EXPORT DMAC3_Handler [WEAK]
|
||||||
|
EXPORT DMAC4_Handler [WEAK]
|
||||||
|
EXPORT DMAC5_Handler [WEAK]
|
||||||
|
EXPORT DMAC6_Handler [WEAK]
|
||||||
|
EXPORT DMAC7_Handler [WEAK]
|
||||||
|
EXPORT DummyHandler [WEAK]
|
||||||
|
|
||||||
|
CSV_Handler
|
||||||
|
SWDT_Handler
|
||||||
|
LVD_Handler
|
||||||
|
MFT_WG_IRQHandler
|
||||||
|
INT0_7_Handler
|
||||||
|
INT8_15_Handler
|
||||||
|
DT_Handler
|
||||||
|
MFS0RX_IRQHandler
|
||||||
|
MFS0TX_IRQHandler
|
||||||
|
MFS1RX_IRQHandler
|
||||||
|
MFS1TX_IRQHandler
|
||||||
|
MFS2RX_IRQHandler
|
||||||
|
MFS2TX_IRQHandler
|
||||||
|
MFS3RX_IRQHandler
|
||||||
|
MFS3TX_IRQHandler
|
||||||
|
MFS4RX_IRQHandler
|
||||||
|
MFS4TX_IRQHandler
|
||||||
|
MFS5RX_IRQHandler
|
||||||
|
MFS5TX_IRQHandler
|
||||||
|
MFS6RX_IRQHandler
|
||||||
|
MFS6TX_IRQHandler
|
||||||
|
MFS7RX_IRQHandler
|
||||||
|
MFS7TX_IRQHandler
|
||||||
|
PPG_Handler
|
||||||
|
TIM_IRQHandler
|
||||||
|
ADC0_IRQHandler
|
||||||
|
ADC1_IRQHandler
|
||||||
|
ADC2_IRQHandler
|
||||||
|
MFT_FRT_IRQHandler
|
||||||
|
MFT_IPC_IRQHandler
|
||||||
|
MFT_OPC_IRQHandler
|
||||||
|
BT_IRQHandler
|
||||||
|
CAN0_IRQHandler
|
||||||
|
CAN1_IRQHandler
|
||||||
|
USBF_Handler
|
||||||
|
USB_Handler
|
||||||
|
DMAC0_Handler
|
||||||
|
DMAC1_Handler
|
||||||
|
DMAC2_Handler
|
||||||
|
DMAC3_Handler
|
||||||
|
DMAC4_Handler
|
||||||
|
DMAC5_Handler
|
||||||
|
DMAC6_Handler
|
||||||
|
DMAC7_Handler
|
||||||
|
DummyHandler
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
; User Initial Stack & Heap
|
||||||
|
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
ELSE
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
Loading…
Reference in New Issue