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81
README.md
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@ -1,6 +1,6 @@
# RT-Thread #
[中文页](README_zh.md) |
**English** | [简体中文](README.zh-CN.md) |
[![GitHub](https://img.shields.io/github/license/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE)
[![GitHub release](https://img.shields.io/github/release/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/releases)
@ -11,9 +11,9 @@
# Introduction
RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS).
RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS).
RT-Thread is mainly written in C language, easy to understand and easy to port(can be quickly port to a wide range of mainstream MCUs and module chips). It applies object-oriented programming methods to real-time system design, making the code elegant, structured, modular, and very tailorable.
RT-Thread is mainly written in C language, easy to understand and easy to port(can be quickly port to a wide range of mainstream MCUs and module chips). It applies object-oriented programming methods to real-time system design, making the code elegant, structured, modular, and very tailorable.
RT-Thread has Standard version and Nano version. For resource-constrained microcontroller (MCU) systems, the NANO kernel version that requires only 3KB Flash and 1.2KB RAM memory resources can be tailored with easy-to-use tools; And for resource-rich IoT devices, RT-Thread can use the on-line software package management tool, together with system configuration tools, to achieve intuitive and rapid modular cutting, seamlessly import rich software packages, thus achieving complex functions like Android's graphical interface and touch sliding effects, smart voice interaction effects, and so on.
@ -29,23 +29,23 @@ It includes:
- Kernel layer: RT-Thread kernel, the core part of RT-Thread, includes the implementation of objects in the kernel system, such as multi-threading and its scheduling, semaphore, mailbox, message queue, memory management, timer, etc.; libcpu/BSP (Chip Migration Related Files/Board Support Package) is closely related to hardware and consists of peripheral drivers and CPU porting.
- Components and Service Layer: Components are based on upper-level software on top of the RT-Thread kernel, such as virtual file systems, FinSH command-line interfaces, network frameworks, device frameworks, and more. Its modular design allows for high internal cohesion inside the components and low coupling between components.
- RT-Thread software package: A general-purpose software component running on the RT-Thread IoT operating system platform for different application areas, consisting of description information, source code or library files. RT-Thread provides an open package platform with officially available or developer-supplied packages that provide developers with a choice of reusable packages that are an important part of the RT-Thread ecosystem. The package ecosystem is critical to the choice of an operating system because these packages are highly reusable and modular, making it easy for application developers to build the system they want in the shortest amount of time. RT-Thread supports more than 180 software packages.
- Components and Service Layer: Components are based on upper-level software on top of the RT-Thread kernel, such as virtual file systems, FinSH command-line interfaces, network frameworks, device frameworks, and more. Its modular design allows for high internal cohesion inside the components and low coupling between components.
- [RT-Thread software package](https://packages.rt-thread.org/en/index.html): A general-purpose software component running on the RT-Thread IoT operating system platform for different application areas, consisting of description information, source code or library files. RT-Thread provides an open package platform with officially available or developer-supplied packages that provide developers with a choice of reusable packages that are an important part of the RT-Thread ecosystem. The package ecosystem is critical to the choice of an operating system because these packages are highly reusable and modular, making it easy for application developers to build the system they want in the shortest amount of time. RT-Thread supports more than 370 software packages.
## RT-Thread Features
- Designed for resource-constrained devices, the minimum kernel requires only 1.2KB of RAM and 3 KB of Flash.
- Designed for resource-constrained devices, the minimum kernel requires only 1.2KB of RAM and 3 KB of Flash.
- Has rich components and a prosperous and fast growing package ecosystem.
- Has rich components and a prosperous and fast growing package ecosystem.
- Elegant code style, easy to use, read and master.
- Elegant code style, easy to use, read and master.
- High Scalability. RT-Thread has high-quality scalable software architecture, loose coupling, modularity, is easy to tailor and expand.
- High Scalability. RT-Thread has high-quality scalable software architecture, loose coupling, modularity, is easy to tailor and expand.
- Supports high-performance applications.
- Supports high-performance applications.
- Supports cross-platform and a wide range of chips.
- Supports cross-platform and a wide range of chips.
## Code Catalogue
@ -62,12 +62,7 @@ It includes:
| src | The source files for the RT-Thread kernel. |
| tools | The script files for the RT-Thread command build tool. |
RT-Thread has now been ported for nearly 90 development boards, most BSPs support MDK, IAR development environment and GCC compiler, and have provided default MDK and IAR project, which allows users to add their own application code directly based on the project. Each BSP has a similar directory structure, and most BSPs provide a README.md file, which is a markdown-format file that contains the basic introduction of BSP, and introduces how to simply start using BSP.
Env is a development tool developed by RT-Thread which provides a build environment, text graphical system configuration, and package management capabilities for project based on the RT-Thread operating system. Its built-in `menuconfig` provides an easy-to-use configuration tool. It can tailor the kernels, components and software packages freely, so that the system can be constructed by building blocks.
- [Download Env Tool](https://www.rt-thread.io/download.html?download=Env)
- [User manual of Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
RT-Thread has now been ported for nearly 200 development boards, most BSPs support MDK, IAR development environment and GCC compiler, and have provided default MDK and IAR project, which allows users to add their own application code directly based on the project. Each BSP has a similar directory structure, and most BSPs provide a README.md file, which is a markdown-format file that contains the basic introduction of BSP, and introduces how to simply start using BSP.
# Resources
@ -86,7 +81,7 @@ RT-Thread supports many architectures, and has covered the major architectures i
- **ARM9**：manufacturers like Allwinner、Xilinx 、GOKE
- **ARM11**：manufacturers like Fullhan
- **MIPS32**：manufacturers like loongson、Ingenic
- **RISC-V**：manufacturers like Hifive、Kendryte、[Nuclei](https://nucleisys.com/)
- **RISC-V**：manufacturers like Hifive、Kendryte、Nuclei
- **ARC**：manufacturers like SYNOPSYS
- **DSP**：manufacturers like TI
- **C-Sky**
@ -96,35 +91,40 @@ RT-Thread supports many architectures, and has covered the major architectures i
The main IDE/compilers supported by RT-Thread are:
- RT-Thread Studio IDE
- MDK KEIL
- IAR
- GCC
- RT-Thread Studio
Use Python-based [scons](http://www.scons.org/) for command-line builds.
## RT-Thread Studio IDE
RT-Thread Studio Demonstration:
[User Manual](https://www.rt-thread.io/document/site/rtthread-studio/um/studio-user-manual/) | [Tutorial Videos](https://youtu.be/ucq5eJgZIQg)
![studio](./documentation/figures/studio.gif)
RT-Thread Studio IDE (a.k.a. RT-Studio) is a one-stop intergrated development environment built by RT-Thread team. It has a easy-to-use graphical configuration system and a wealth of software packages and components resources. RT-Studio has the features of project creation, configuration and management,as well as code editing, SDK management, build configuration, debugging configuration, program download and debug. We're looking to make the use of RT-Studio as intuitive as possible, reducing the duplication of work and improving the development efficiency.
## Getting Started
![studio](./documentation/figures/studio.gif)
## Env Tool
[Env Manual](https://www.rt-thread.io/document/site/programming-manual/env/env/)
In the early stage, RT-Thread team also created an auxiliary tool called Env. It is an auxiliary tool with a TUI (Text-based user interface). Developers can use Env tool to configure and generate the GCC, Keil MDK, and IAR projects.
![env](./documentation/figures/env.png)
# Getting Started
[RT-Thread Programming Guide](https://www.rt-thread.io/document/site/tutorial/quick-start/introduction/introduction/) | [RT-Thread Studio IDE](https://www.rt-thread.io/studio.html) | [Kernel Sample](https://github.com/RT-Thread-packages/kernel-sample) | [RT-Thread Beginners Guide](https://www.youtube.com/watch?v=ZMi1O-Rr7yc&list=PLXUV89C_M3G5KVw2IerI-pqApdSM_IaZo)
[Based on the STM32F103 BluePill](https://github.com/RT-Thread/rt-thread/tree/master/bsp/stm32/stm32f103-blue-pill)
## Simulator
RT-Thread BSP can be compiled directly and downloaded to the corresponding development board for use. In addition, RT-Thread also provides qemu-vexpress-a9 BSP, which can be used without hardware platform. See the getting started guide below for details.
- [Getting Started of QEMU (Windows)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu.md)
- [Getting Started of QEMU with Env(Windows)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu.md)
- [Getting Started of QEMU (Ubuntu)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu_linux.md)
## Documentation
[RT-Thread Programming Guide](https://github.com/RT-Thread/rtthread-manual-doc) | [RT-Thread Supported Chips & Boards](https://www.rt-thread.io/board.html) |
[RT-Thread Software Package](https://github.com/RT-Thread/packages) | [RT-Thread Studio](https://www.rt-thread.io/studio.html)
## Sample
[Kernel Sample](https://github.com/RT-Thread-packages/kernel-sample) | [Device Sample Code](https://github.com/RT-Thread-packages/peripheral-sample) | [File System Sample Code](https://github.com/RT-Thread-packages/filesystem-sample ) | [Network Sample Code](https://github.com/RT-Thread-packages/network-sample ) |
[Based on the STM32L475 IoT Board SDK](https://github.com/RT-Thread/IoT_Board) | [Based on the W601 IoT Board SDK](https://github.com/RT-Thread/W601_IoT_Board)
- [Getting Started of QEMU with Env(Ubuntu)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu_linux.md)
# License
@ -138,14 +138,13 @@ RT-Thread is an open source software and has been licensed under Apache License
*/
```
To avoid possible future license conflicts, developers need to sign a Contributor License Agreement (CLA) when submitting PR to RT-Thread.
# Community
RT-Thread is very grateful for the support from all community developers, and if you have any ideas, suggestions or questions in the process of using RT-Thread, RT-Thread can be reached by the following means, and we are also updating RT-Thread in real time on these channels. At the same time, Any questions can be asked in the [issue section of rtthread-manual-doc](https://github.com/RT-Thread/rtthread-manual-doc/issues). By creating a new issue to describe your questions, community members will answer them.
RT-Thread is very grateful for the support from all community developers, and if you have any ideas, suggestions or questions in the process of using RT-Thread, RT-Thread can be reached by the following means, and we are also updating RT-Thread in real time on these channels. At the same time, any questions can be asked in the [issue section of RT-Thread repository](https://github.com/RT-Thread/rt-thread/issues) or [RT-Thread forum](https://club.rt-thread.io/), and community members will answer them.
[Website](https://www.rt-thread.io) | [Twitter](https://twitter.com/rt_thread) | [Youtube]( https://www.youtube.com/channel/UCdDHtIfSYPq4002r27ffqPw?view_as=subscriber) | [Gitter]( https://gitter.im/RT-Thread) | [Facebook](https://www.facebook.com/RT-Thread-IoT-OS-110395723808463/?modal=admin_todo_tour) | [Medium](https://medium.com/@rt_thread)
[Website](https://www.rt-thread.io) | [Github](https://github.com/RT-Thread/rt-thread) | [Twitter](https://twitter.com/rt_thread) | [LinkedIn](https://www.linkedin.com/company/rt-thread-iot-os/posts/?feedView=all) | [Youtube]( https://www.youtube.com/channel/UCdDHtIfSYPq4002r27ffqPw?view_as=subscriber) | [Facebook](https://www.facebook.com/RT-Thread-IoT-OS-110395723808463/?modal=admin_todo_tour) | [Medium](https://rt-thread.medium.com/)
# Contribution
If you are interested in RT-Thread and want to join in the development of RT-Thread and become a code contributor,please refer to the [Code Contribution Guide](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/contribution_guide/contribution_guide.md).

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README_zh.md → README.zh-CN.md
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@ -9,7 +9,7 @@ RT-Thread有完整版和Nano版，对于资源受限的微控制器（MCU）系
RT-Thread是一个集实时操作系统（RTOS）内核、中间件组件的物联网操作系统，架构如下：
![architecturezh](./documentation/figures/architecturezh.png)
![architecturezh](./documentation/figures/architecturezh.png)
@ -19,14 +19,14 @@ RT-Thread是一个集实时操作系统（RTOS）内核、中间件组件的物
- RT-Thread软件包：运行于 RT-Thread物联网操作系统平台上，面向不同应用领域的通用软件组件，由描述信息、源代码或库文件组成。RT-Thread提供了开放的软件包平台，这里存放了官方提供或开发者提供的软件包，该平台为开发者提供了众多可重用软件包的选择，这也是 RT-Thread生态的重要组成部分。软件包生态对于一个操作系统的选择至关重要，因为这些软件包具有很强的可重用性，模块化程度很高，极大的方便应用开发者在最短时间内，打造出自己想要的系统。RT-Thread已经支持的软件包数量已经达到 180+。
## RT-Thread的特点
- 资源占用极低，超低功耗设计，最小内核（Nano版本）仅需1.2KB RAM，3KB Flash。
- 组件丰富，繁荣发展的软件包生态 。
- 组件丰富，繁荣发展的软件包生态 。
- 简单易用 ，优雅的代码风格，易于阅读、掌握。
@ -117,7 +117,7 @@ RT-Thread主要支持的IDE/编译器包括：
RT-Thread Studio演示：
![studiozh](./documentation/figures/studiozh.gif)
![studiozh](./documentation/figures/studiozh.gif)
## **快速上手**
@ -131,15 +131,15 @@ RT-Thread BSP可以直接编译并下载到相应的开发板使用。此外，R
## 文档
[文档中心](https://www.rt-thread.org/document/site/ ) | [编程指南](https://www.rt-thread.org/document/site/programming-manual/basic/basic/ )
[文档中心](https://www.rt-thread.org/document/site/ ) | [编程指南](https://www.rt-thread.org/document/site/programming-manual/basic/basic/ )
[应用 RT-Thread 实现蜂鸣器播放器教程](https://www.rt-thread.org/document/site/tutorial/beep-player/) | [分布式温度监控系统教程](https://www.rt-thread.org/document/site/tutorial/temperature-system/ ) | [智能车连载教程](https://www.rt-thread.org/document/site/tutorial/smart-car/ )
[应用 RT-Thread 实现蜂鸣器播放器教程](https://www.rt-thread.org/document/site/tutorial/beep-player/) | [分布式温度监控系统教程](https://www.rt-thread.org/document/site/tutorial/temperature-system/ ) | [智能车连载教程](https://www.rt-thread.org/document/site/tutorial/smart-car/ )
## 例程
[内核示例](https://github.com/RT-Thread-packages/kernel-sample) | [设备示例代码](https://github.com/RT-Thread-packages/peripheral-sample ) | [文件系统示例代码](https://github.com/RT-Thread-packages/filesystem-sample ) | [网络示例代码](https://github.com/RT-Thread-packages/network-sample ) | [RT-Thread API参考手册](https://www.rt-thread.org/document/api/ )
[内核示例](https://github.com/RT-Thread-packages/kernel-sample) | [设备示例代码](https://github.com/RT-Thread-packages/peripheral-sample ) | [文件系统示例代码](https://github.com/RT-Thread-packages/filesystem-sample ) | [网络示例代码](https://github.com/RT-Thread-packages/network-sample ) | [RT-Thread API参考手册](https://www.rt-thread.org/document/api/ )
[基于STM32L475 IoT Board 开发板SDK](https://github.com/RT-Thread/IoT_Board) | [基于W601 IoT Board 开发板SDK](https://github.com/RT-Thread/W601_IoT_Board)
[基于STM32L475 IoT Board 开发板SDK](https://github.com/RT-Thread/IoT_Board) | [基于W601 IoT Board 开发板SDK](https://github.com/RT-Thread/W601_IoT_Board)
## 视频
@ -165,7 +165,7 @@ RT-Thread系统完全开源，3.1.0 及以前的版本遵循 GPL V2 + 开源许
RT-Thread非常感谢所有社区小伙伴的支持，在使用RT-Thread的过程中若您有任何的想法，建议或疑问都可通过以下方式联系到 RT-Thread，我们也实时在这些频道更新RT-Thread的最新讯息。同时，任何问题都可以在 [issue section](https://github.com/RT-Thread/rtthread-manual-doc/issues) 中提出。通过创建一个issue来描述您的问题，社区成员将回答这些问题。
[官网]( https://www.rt-thread.org) | [论坛]( https://www.rt-thread.org/qa/forum.php) | [哔哩哔哩官方账号](https://space.bilibili.com/423462075?spm_id_from=333.788.b_765f7570696e666f.2) | [微博官方账号](https://weibo.com/rtthread?is_hot=1) | [知乎官方账号](https://www.zhihu.com/topic/19964581/hot)
[官网]( https://www.rt-thread.org) | [论坛]( https://www.rt-thread.org/qa/forum.php) | [哔哩哔哩官方账号](https://space.bilibili.com/423462075?spm_id_from=333.788.b_765f7570696e666f.2) | [微博官方账号](https://weibo.com/rtthread?is_hot=1) | [知乎官方账号](https://www.zhihu.com/topic/19964581/hot)
RT-Thread微信公众号：

332
bsp/at32/Libraries/rt_drivers/drv_gpio.c
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@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2020-01-07 shelton first version
* 2021-10-28 jonas optimization design pin-index algorithm
*/
#include <board.h>
@ -13,135 +14,43 @@
#ifdef RT_USING_PIN
static const struct pin_index pins[] =
{
#if defined(GPIOA)
__AT32_PIN(0 , A, 0 ),
__AT32_PIN(1 , A, 1 ),
__AT32_PIN(2 , A, 2 ),
__AT32_PIN(3 , A, 3 ),
__AT32_PIN(4 , A, 4 ),
__AT32_PIN(5 , A, 5 ),
__AT32_PIN(6 , A, 6 ),
__AT32_PIN(7 , A, 7 ),
__AT32_PIN(8 , A, 8 ),
__AT32_PIN(9 , A, 9 ),
__AT32_PIN(10, A, 10),
__AT32_PIN(11, A, 11),
__AT32_PIN(12, A, 12),
__AT32_PIN(13, A, 13),
__AT32_PIN(14, A, 14),
__AT32_PIN(15, A, 15),
#if defined(GPIOB)
__AT32_PIN(16, B, 0),
__AT32_PIN(17, B, 1),
__AT32_PIN(18, B, 2),
__AT32_PIN(19, B, 3),
__AT32_PIN(20, B, 4),
__AT32_PIN(21, B, 5),
__AT32_PIN(22, B, 6),
__AT32_PIN(23, B, 7),
__AT32_PIN(24, B, 8),
__AT32_PIN(25, B, 9),
__AT32_PIN(26, B, 10),
__AT32_PIN(27, B, 11),
__AT32_PIN(28, B, 12),
__AT32_PIN(29, B, 13),
__AT32_PIN(30, B, 14),
__AT32_PIN(31, B, 15),
#if defined(GPIOC)
__AT32_PIN(32, C, 0),
__AT32_PIN(33, C, 1),
__AT32_PIN(34, C, 2),
__AT32_PIN(35, C, 3),
__AT32_PIN(36, C, 4),
__AT32_PIN(37, C, 5),
__AT32_PIN(38, C, 6),
__AT32_PIN(39, C, 7),
__AT32_PIN(40, C, 8),
__AT32_PIN(41, C, 9),
__AT32_PIN(42, C, 10),
__AT32_PIN(43, C, 11),
__AT32_PIN(44, C, 12),
__AT32_PIN(45, C, 13),
__AT32_PIN(46, C, 14),
__AT32_PIN(47, C, 15),
#if defined(GPIOD)
__AT32_PIN(48, D, 0),
__AT32_PIN(49, D, 1),
__AT32_PIN(50, D, 2),
__AT32_PIN(51, D, 3),
__AT32_PIN(52, D, 4),
__AT32_PIN(53, D, 5),
__AT32_PIN(54, D, 6),
__AT32_PIN(55, D, 7),
__AT32_PIN(56, D, 8),
__AT32_PIN(57, D, 9),
__AT32_PIN(58, D, 10),
__AT32_PIN(59, D, 11),
__AT32_PIN(60, D, 12),
__AT32_PIN(61, D, 13),
__AT32_PIN(62, D, 14),
__AT32_PIN(63, D, 15),
#if defined(GPIOE)
__AT32_PIN(64, E, 0),
__AT32_PIN(65, E, 1),
__AT32_PIN(66, E, 2),
__AT32_PIN(67, E, 3),
__AT32_PIN(68, E, 4),
__AT32_PIN(69, E, 5),
__AT32_PIN(70, E, 6),
__AT32_PIN(71, E, 7),
__AT32_PIN(72, E, 8),
__AT32_PIN(73, E, 9),
__AT32_PIN(74, E, 10),
__AT32_PIN(75, E, 11),
__AT32_PIN(76, E, 12),
__AT32_PIN(77, E, 13),
__AT32_PIN(78, E, 14),
__AT32_PIN(79, E, 15),
#if defined(GPIOF)
__AT32_PIN(80, F, 0),
__AT32_PIN(81, F, 1),
__AT32_PIN(82, F, 2),
__AT32_PIN(83, F, 3),
__AT32_PIN(84, F, 4),
__AT32_PIN(85, F, 5),
__AT32_PIN(86, F, 6),
__AT32_PIN(87, F, 7),
__AT32_PIN(88, F, 8),
__AT32_PIN(89, F, 9),
__AT32_PIN(90, F, 10),
__AT32_PIN(91, F, 11),
__AT32_PIN(92, F, 12),
__AT32_PIN(93, F, 13),
__AT32_PIN(94, F, 14),
__AT32_PIN(95, F, 15),
#if defined(GPIOG)
__AT32_PIN(96, G, 0),
__AT32_PIN(97, G, 1),
__AT32_PIN(98, G, 2),
__AT32_PIN(99, G, 3),
__AT32_PIN(100, G, 4),
__AT32_PIN(101, G, 5),
__AT32_PIN(102, G, 6),
__AT32_PIN(103, G, 7),
__AT32_PIN(104, G, 8),
__AT32_PIN(105, G, 9),
__AT32_PIN(106, G, 10),
__AT32_PIN(107, G, 11),
__AT32_PIN(108, G, 12),
__AT32_PIN(109, G, 13),
__AT32_PIN(110, G, 14),
__AT32_PIN(111, G, 15),
#endif /* defined(GPIOG) */
#endif /* defined(GPIOF) */
#endif /* defined(GPIOE) */
#endif /* defined(GPIOD) */
#endif /* defined(GPIOC) */
#endif /* defined(GPIOB) */
#endif /* defined(GPIOA) */
};
#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_ATPORTSOURCE(pin) ((uint8_t)(((pin) & 0xF0u) >> 4))
#define PIN_ATPINSOURCE(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_ATPORT(pin) ((GPIO_Type *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
#define PIN_ATPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
#if defined(GPIOZ)
#define __AT32_PORT_MAX 12u
#elif defined(GPIOK)
#define __AT32_PORT_MAX 11u
#elif defined(GPIOJ)
#define __AT32_PORT_MAX 10u
#elif defined(GPIOI)
#define __AT32_PORT_MAX 9u
#elif defined(GPIOH)
#define __AT32_PORT_MAX 8u
#elif defined(GPIOG)
#define __AT32_PORT_MAX 7u
#elif defined(GPIOF)
#define __AT32_PORT_MAX 6u
#elif defined(GPIOE)
#define __AT32_PORT_MAX 5u
#elif defined(GPIOD)
#define __AT32_PORT_MAX 4u
#elif defined(GPIOC)
#define __AT32_PORT_MAX 3u
#elif defined(GPIOB)
#define __AT32_PORT_MAX 2u
#elif defined(GPIOA)
#define __AT32_PORT_MAX 1u
#else
#define __AT32_PORT_MAX 0u
#error Unsupported AT32 GPIO peripheral.
#endif
#define PIN_ATPORT_MAX __AT32_PORT_MAX
static const struct pin_irq_map pin_irq_map[] =
{
@ -182,72 +91,62 @@ static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
static uint32_t pin_irq_enable_mask=0;
static uint32_t pin_irq_enable_mask = 0;
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static const struct pin_index *get_pin(uint8_t pin)
{
const struct pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->index == -1)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
};
static void at32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
GPIO_Type *gpio_port;
uint16_t gpio_pin;
if (PIN_PORT(pin) < PIN_ATPORT_MAX)
{
gpio_port = PIN_ATPORT(pin);
gpio_pin = PIN_ATPIN(pin);
}
else
{
return;
}
GPIO_WriteBit(index->gpio, index->pin, (BitState)value);
GPIO_WriteBit(gpio_port, gpio_pin, (BitState)value);
}
static int at32_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_Type *gpio_port;
uint16_t gpio_pin;
int value;
const struct pin_index *index;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) < PIN_ATPORT_MAX)
{
return value;
gpio_port = PIN_ATPORT(pin);
gpio_pin = PIN_ATPIN(pin);
value = GPIO_ReadInputDataBit(gpio_port, gpio_pin);
}
value = GPIO_ReadInputDataBit(index->gpio, index->pin);
return value;
}
static void at32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
GPIO_InitType GPIO_InitStruct;
GPIO_Type *gpio_port;
uint16_t gpio_pin;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) < PIN_ATPORT_MAX)
{
gpio_port = PIN_ATPORT(pin);
gpio_pin = PIN_ATPIN(pin);
}
else
{
return;
}
/* Configure GPIO_InitStructure */
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pins = index->pin;
GPIO_InitStruct.GPIO_Pins = gpio_pin;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT_PP;
GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
@ -277,7 +176,7 @@ static void at32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT_OD;
}
GPIO_Init(index->gpio, &GPIO_InitStruct);
GPIO_Init(gpio_port, &GPIO_InitStruct);
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
@ -304,21 +203,27 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
};
static rt_err_t at32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
const struct pin_index *index;
RT_UNUSED GPIO_Type *gpio_port;
uint16_t gpio_pin;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) < PIN_ATPORT_MAX)
{
return RT_ENOSYS;
gpio_port = PIN_ATPORT(pin);
gpio_pin = PIN_ATPIN(pin);
}
irqindex = bit2bitno(index->pin);
else
{
return -RT_EINVAL;
}
irqindex = bit2bitno(gpio_pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@ -333,7 +238,7 @@ static rt_err_t at32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
if (pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return RT_EBUSY;
return -RT_EBUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
@ -346,19 +251,24 @@ static rt_err_t at32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
static rt_err_t at32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct pin_index *index;
RT_UNUSED GPIO_Type *gpio_port;
uint16_t gpio_pin;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) < PIN_ATPORT_MAX)
{
return RT_ENOSYS;
gpio_port = PIN_ATPORT(pin);
gpio_pin = PIN_ATPIN(pin);
}
irqindex = bit2bitno(index->pin);
else
{
return -RT_EINVAL;
}
irqindex = bit2bitno(gpio_pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@ -377,28 +287,33 @@ static rt_err_t at32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
}
static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
rt_uint32_t enabled)
{
GPIO_InitType GPIO_InitStruct;
EXTI_InitType EXTI_InitStruct;
NVIC_InitType NVIC_InitStruct;
const struct pin_index *index;
GPIO_Type *gpio_port;
uint16_t gpio_pin;
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) < PIN_ATPORT_MAX)
{
return RT_ENOSYS;
gpio_port = PIN_ATPORT(pin);
gpio_pin = PIN_ATPIN(pin);
}
else
{
return -RT_EINVAL;
}
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(index->pin);
irqindex = bit2bitno(gpio_pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@ -406,7 +321,7 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_ENOSYS;
return -RT_EINVAL;
}
irqmap = &pin_irq_map[irqindex];
@ -431,8 +346,10 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
EXTI_InitStruct.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
}
GPIO_Init(index->gpio, &GPIO_InitStruct);
GPIO_EXTILineConfig(index->portsource, index->pinsource);
GPIO_Init(gpio_port, &GPIO_InitStruct);
GPIO_EXTILineConfig(PIN_ATPORTSOURCE(pin), PIN_ATPINSOURCE(pin));
EXTI_Init(&EXTI_InitStruct);
NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
@ -445,10 +362,10 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
}
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
irqmap = get_pin_irq_map(gpio_pin);
if (irqmap == RT_NULL)
{
return RT_ENOSYS;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@ -459,16 +376,16 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 5;
NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
if (( irqmap->pinbit>=GPIO_Pins_5 )&&( irqmap->pinbit<=GPIO_Pins_9 ))
if ((irqmap->pinbit >= GPIO_Pins_5) && (irqmap->pinbit <= GPIO_Pins_9))
{
if(!(pin_irq_enable_mask&(GPIO_Pins_5|GPIO_Pins_6|GPIO_Pins_7|GPIO_Pins_8|GPIO_Pins_9)))
if (!(pin_irq_enable_mask & (GPIO_Pins_5 | GPIO_Pins_6 | GPIO_Pins_7 | GPIO_Pins_8 | GPIO_Pins_9)))
{
NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
}
}
else if (( irqmap->pinbit>=GPIO_Pins_10 )&&( irqmap->pinbit<=GPIO_Pins_15 ))
else if ((irqmap->pinbit >= GPIO_Pins_10) && (irqmap->pinbit <= GPIO_Pins_15))
{
if(!(pin_irq_enable_mask&(GPIO_Pins_10|GPIO_Pins_11|GPIO_Pins_12|GPIO_Pins_13|GPIO_Pins_14|GPIO_Pins_15)))
if (!(pin_irq_enable_mask & (GPIO_Pins_10 | GPIO_Pins_11 | GPIO_Pins_12 | GPIO_Pins_13 | GPIO_Pins_14 | GPIO_Pins_15)))
{
NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
}
@ -483,11 +400,12 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
}
else
{
return -RT_ENOSYS;
return -RT_EINVAL;
}
return RT_EOK;
}
const static struct rt_pin_ops _at32_pin_ops =
{
at32_pin_mode,
@ -552,23 +470,23 @@ void EXTI4_IRQHandler(void)
void EXTI9_5_IRQHandler(void)
{
rt_interrupt_enter();
if(RESET != EXTI_GetIntStatus(EXTI_Line5))
if (RESET != EXTI_GetIntStatus(EXTI_Line5))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_5);
}
if(RESET != EXTI_GetIntStatus(EXTI_Line6))
if (RESET != EXTI_GetIntStatus(EXTI_Line6))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_6);
}
if(RESET != EXTI_GetIntStatus(EXTI_Line7))
if (RESET != EXTI_GetIntStatus(EXTI_Line7))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_7);
}
if(RESET != EXTI_GetIntStatus(EXTI_Line8))
if (RESET != EXTI_GetIntStatus(EXTI_Line8))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_8);
}
if(RESET != EXTI_GetIntStatus(EXTI_Line9))
if (RESET != EXTI_GetIntStatus(EXTI_Line9))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_9);
}
@ -578,27 +496,27 @@ void EXTI9_5_IRQHandler(void)
void EXTI15_10_IRQHandler(void)
{
rt_interrupt_enter();
if(RESET != EXTI_GetIntStatus(EXTI_Line10))
if (RESET != EXTI_GetIntStatus(EXTI_Line10))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_10);
}
if(RESET != EXTI_GetIntStatus(EXTI_Line11))
if (RESET != EXTI_GetIntStatus(EXTI_Line11))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_11);
}
if(RESET != EXTI_GetIntStatus(EXTI_Line12))
if (RESET != EXTI_GetIntStatus(EXTI_Line12))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_12);
}
if(RESET != EXTI_GetIntStatus(EXTI_Line13))
if (RESET != EXTI_GetIntStatus(EXTI_Line13))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_13);
}
if(RESET != EXTI_GetIntStatus(EXTI_Line14))
if (RESET != EXTI_GetIntStatus(EXTI_Line14))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_14);
}
if(RESET != EXTI_GetIntStatus(EXTI_Line15))
if (RESET != EXTI_GetIntStatus(EXTI_Line15))
{
GPIO_EXTI_IRQHandler(GPIO_Pins_15);
}

145
bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c
View File

@ -44,63 +44,63 @@ static rt_uint32_t n32_adc_get_channel(rt_uint32_t channel)
switch (channel)
{
case 0:
n32_channel = ADC_CH_0;
break;
case 1:
n32_channel = ADC_CH_1;
break;
case 2:
n32_channel = ADC_CH_2;
break;
case 3:
n32_channel = ADC_CH_3;
break;
case 4:
n32_channel = ADC_CH_4;
break;
case 5:
n32_channel = ADC_CH_5;
break;
case 6:
n32_channel = ADC_CH_6;
break;
case 7:
n32_channel = ADC_CH_7;
break;
case 8:
n32_channel = ADC_CH_8;
break;
case 9:
n32_channel = ADC_CH_9;
break;
case 10:
n32_channel = ADC_CH_10;
break;
case 11:
n32_channel = ADC_CH_11;
break;
case 12:
n32_channel = ADC_CH_12;
break;
case 13:
n32_channel = ADC_CH_13;
break;
case 14:
n32_channel = ADC_CH_14;
break;
case 15:
n32_channel = ADC_CH_15;
break;
case 16:
n32_channel = ADC_CH_16;
break;
case 17:
n32_channel = ADC_CH_17;
break;
case 18:
n32_channel = ADC_CH_18;
break;
case 0:
n32_channel = ADC_CH_0;
break;
case 1:
n32_channel = ADC_CH_1;
break;
case 2:
n32_channel = ADC_CH_2;
break;
case 3:
n32_channel = ADC_CH_3;
break;
case 4:
n32_channel = ADC_CH_4;
break;
case 5:
n32_channel = ADC_CH_5;
break;
case 6:
n32_channel = ADC_CH_6;
break;
case 7:
n32_channel = ADC_CH_7;
break;
case 8:
n32_channel = ADC_CH_8;
break;
case 9:
n32_channel = ADC_CH_9;
break;
case 10:
n32_channel = ADC_CH_10;
break;
case 11:
n32_channel = ADC_CH_11;
break;
case 12:
n32_channel = ADC_CH_12;
break;
case 13:
n32_channel = ADC_CH_13;
break;
case 14:
n32_channel = ADC_CH_14;
break;
case 15:
n32_channel = ADC_CH_15;
break;
case 16:
n32_channel = ADC_CH_16;
break;
case 17:
n32_channel = ADC_CH_17;
break;
case 18:
n32_channel = ADC_CH_18;
break;
}
return n32_channel;
@ -124,27 +124,23 @@ static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
ADC_InitStructure.ChsNumber = 1;
ADC_Init(n32_adc_handler, &ADC_InitStructure);
/* ADCx regular channels configuration */
ADC_ConfigRegularChannel(n32_adc_handler, n32_adc_get_channel(channel), 1, ADC_SAMP_TIME_28CYCLES5);
if (((n32_adc_handler == ADC2) || (n32_adc_handler == ADC2))
&& ((n32_adc_get_channel(channel) == ADC_CH_16) || (n32_adc_get_channel(channel) == ADC_CH_18)))
&& ((n32_adc_get_channel(channel) == ADC_CH_16)
|| (n32_adc_get_channel(channel) == ADC_CH_18)))
{
ADC_EnableTempSensorVrefint(ENABLE);
}
/* Enable ADCx */
ADC_Enable(n32_adc_handler, ENABLE);
/* Start ADCx calibration */
ADC_StartCalibration(n32_adc_handler);
/* Check the end of ADCx calibration */
while(ADC_GetCalibrationStatus(n32_adc_handler));
if (enabled)
{
/* Enable ADC1 */
ADC_Enable(n32_adc_handler, ENABLE);
/*Check ADC Ready*/
while (ADC_GetFlagStatusNew(n32_adc_handler, ADC_FLAG_RDY) == RESET);
/* Start ADCx calibration */
ADC_StartCalibration(n32_adc_handler);
/* Check the end of ADCx calibration */
while (ADC_GetCalibrationStatus(n32_adc_handler));
}
else
{
@ -164,11 +160,16 @@ static rt_err_t n32_get_adc_value(struct rt_adc_device *device, rt_uint32_t chan
n32_adc_handler = device->parent.user_data;
/* ADCx regular channels configuration */
ADC_ConfigRegularChannel(n32_adc_handler, n32_adc_get_channel(channel), 1, ADC_SAMP_TIME_28CYCLES5);
/* Start ADCx Software Conversion */
ADC_EnableSoftwareStartConv(n32_adc_handler, ENABLE);
/* Wait for the ADC to convert */
while(ADC_GetFlagStatus(n32_adc_handler, ADC_FLAG_ENDC) == RESET);
while (ADC_GetFlagStatus(n32_adc_handler, ADC_FLAG_ENDC) == RESET);
ADC_ClearFlag(n32_adc_handler, ADC_FLAG_ENDC);
/* get ADC value */
*value = ADC_GetDat(n32_adc_handler);
@ -191,8 +192,8 @@ static int rt_hw_adc_init(void)
{
/* register ADC device */
if (rt_hw_adc_register(&n32_adc_obj[i].n32_adc_device,
n32_adc_obj[i].name, &at_adc_ops,
n32_adc_obj[i].ADC_Handler) == RT_EOK)
n32_adc_obj[i].name, &at_adc_ops,
n32_adc_obj[i].ADC_Handler) == RT_EOK)
{
LOG_D("%s register success", n32_adc_obj[i].name);
}

10
bsp/n32g452xx/Libraries/rt_drivers/drv_common.c
View File

@ -12,11 +12,11 @@
#include "board.h"
#ifdef RT_USING_SERIAL
#ifdef RT_USING_SERIAL_V2
#include "drv_usart_v2.h"
#else
#include "drv_usart.h"
#endif
#ifdef RT_USING_SERIAL_V2
#include "drv_usart_v2.h"
#else
#include "drv_usart.h"
#endif
#endif
#ifdef RT_USING_FINSH

2
bsp/n32g452xx/Libraries/rt_drivers/drv_common.h
View File

@ -14,7 +14,7 @@
#include <rtthread.h>
#include <rthw.h>
#ifdef RT_USING_DEVICE
#include <rtdevice.h>
#include <rtdevice.h>
#endif
#ifdef __cplusplus

10
bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c
View File

@ -15,7 +15,7 @@
#include "drv_flash.h"
#if defined(PKG_USING_FAL)
#include "fal.h"
#include "fal.h"
#endif
//#define DRV_DEBUG
@ -147,11 +147,11 @@ int n32_flash_erase(rt_uint32_t addr, size_t size)
return -RT_EINVAL;
}
while(addr < end_addr)
while (addr < end_addr)
{
page_addr = get_page(addr);
if(FLASH_EraseOnePage(page_addr) != FLASH_COMPL)
if (FLASH_EraseOnePage(page_addr) != FLASH_COMPL)
{
result = -RT_ERROR;
goto __exit;
@ -160,10 +160,10 @@ int n32_flash_erase(rt_uint32_t addr, size_t size)
addr += FLASH_PAGE_SIZE;
}
FLASH_Lock();
FLASH_Lock();
__exit:
if(result != RT_EOK)
if (result != RT_EOK)
{
return result;
}

86
bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
View File

@ -573,9 +573,9 @@ void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
int i;
for(i = 0; i < 32; i++)
for (i = 0; i < 32; i++)
{
if((0x01 << i) == bit)
if ((0x01 << i) == bit)
{
return i;
}
@ -585,7 +585,7 @@ rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
{
rt_int32_t mapindex = bit2bitno(pinbit);
if(mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
{
return RT_NULL;
}
@ -604,22 +604,22 @@ rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
return -RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if(pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args
)
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args
)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if(pin_irq_hdr_tab[irqindex].pin != -1)
if (pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return -RT_EBUSY;
@ -644,13 +644,13 @@ rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
return -RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if(pin_irq_hdr_tab[irqindex].pin == -1)
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
@ -679,15 +679,15 @@ rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
{
return -RT_ENOSYS;
}
if(enabled == PIN_IRQ_ENABLE)
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(index->pin);
if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if(pin_irq_hdr_tab[irqindex].pin == -1)
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return -RT_ENOSYS;
@ -701,35 +701,35 @@ rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitPeripheral(index->gpio, &GPIO_InitStructure);
NVIC_InitStructure.NVIC_IRQChannel= irqmap->irqno;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority= 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority= 2;
NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;
NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
GPIO_ConfigEXTILine(index->port_source, index->pin_source);
EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
switch(pin_irq_hdr_tab[irqindex].mode)
switch (pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
break;
case PIN_IRQ_MODE_FALLING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case PIN_IRQ_MODE_RISING_FALLING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
case PIN_IRQ_MODE_RISING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
break;
case PIN_IRQ_MODE_FALLING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case PIN_IRQ_MODE_RISING_FALLING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
}
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_InitPeripheral(&EXTI_InitStructure);
rt_hw_interrupt_enable(level);
}
else if(enabled == PIN_IRQ_DISABLE)
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
if(irqmap == RT_NULL)
if (irqmap == RT_NULL)
{
return -RT_ENOSYS;
}
@ -768,7 +768,7 @@ INIT_BOARD_EXPORT(n32_hw_pin_init);
rt_inline void pin_irq_hdr(int irqno)
{
EXTI_ClrITPendBit(pin_irq_map[irqno].irqbit);
if(pin_irq_hdr_tab[irqno].hdr)
if (pin_irq_hdr_tab[irqno].hdr)
{
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
}
@ -817,23 +817,23 @@ void EXTI9_5_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(EXTI_GetITStatus(EXTI_LINE5) != RESET)
if (EXTI_GetITStatus(EXTI_LINE5) != RESET)
{
pin_irq_hdr(5);
}
if(EXTI_GetITStatus(EXTI_LINE6) != RESET)
if (EXTI_GetITStatus(EXTI_LINE6) != RESET)
{
pin_irq_hdr(6);
}
if(EXTI_GetITStatus(EXTI_LINE7) != RESET)
if (EXTI_GetITStatus(EXTI_LINE7) != RESET)
{
pin_irq_hdr(7);
}
if(EXTI_GetITStatus(EXTI_LINE8) != RESET)
if (EXTI_GetITStatus(EXTI_LINE8) != RESET)
{
pin_irq_hdr(8);
}
if(EXTI_GetITStatus(EXTI_LINE9) != RESET)
if (EXTI_GetITStatus(EXTI_LINE9) != RESET)
{
pin_irq_hdr(9);
}
@ -844,27 +844,27 @@ void EXTI15_10_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(EXTI_GetITStatus(EXTI_LINE10) != RESET)
if (EXTI_GetITStatus(EXTI_LINE10) != RESET)
{
pin_irq_hdr(10);
}
if(EXTI_GetITStatus(EXTI_LINE11) != RESET)
if (EXTI_GetITStatus(EXTI_LINE11) != RESET)
{
pin_irq_hdr(11);
}
if(EXTI_GetITStatus(EXTI_LINE12) != RESET)
if (EXTI_GetITStatus(EXTI_LINE12) != RESET)
{
pin_irq_hdr(12);
}
if(EXTI_GetITStatus(EXTI_LINE13) != RESET)
if (EXTI_GetITStatus(EXTI_LINE13) != RESET)
{
pin_irq_hdr(13);
}
if(EXTI_GetITStatus(EXTI_LINE14) != RESET)
if (EXTI_GetITStatus(EXTI_LINE14) != RESET)
{
pin_irq_hdr(14);
}
if(EXTI_GetITStatus(EXTI_LINE15) != RESET)
if (EXTI_GetITStatus(EXTI_LINE15) != RESET)
{
pin_irq_hdr(15);
}

52
bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c
View File

@ -82,7 +82,7 @@ enum
struct n32_hwtimer
{
rt_hwtimer_t time_device;
TIM_Module* tim_handle;
TIM_Module *tim_handle;
IRQn_Type tim_irqn;
char *name;
};
@ -198,7 +198,7 @@ static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
TIM_ConfigInt(tim, TIM_INT_UPDATE ,ENABLE);
TIM_ConfigInt(tim, TIM_INT_UPDATE, ENABLE);
TIM_ClrIntPendingBit(tim, TIM_INT_UPDATE);
LOG_D("%s init success", tim_device->name);
@ -270,29 +270,29 @@ static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
tim = (TIM_Module *)timer->parent.user_data;
switch(cmd)
switch (cmd)
{
case HWTIMER_CTRL_FREQ_SET:
{
rt_uint32_t freq;
rt_uint16_t val;
case HWTIMER_CTRL_FREQ_SET:
{
rt_uint32_t freq;
rt_uint16_t val;
/* set timer frequence */
freq = *((rt_uint32_t *)arg);
/* set timer frequence */
freq = *((rt_uint32_t *)arg);
/* time init */
RCC_GetClocksFreqValue(&RCC_ClockStruct);
/* time init */
RCC_GetClocksFreqValue(&RCC_ClockStruct);
val = RCC_ClockStruct.SysclkFreq / freq;
val = RCC_ClockStruct.SysclkFreq / freq;
TIM_ConfigPrescaler(tim, val - 1, TIM_PSC_RELOAD_MODE_IMMEDIATE);
}
break;
default:
{
result = -RT_ENOSYS;
}
break;
TIM_ConfigPrescaler(tim, val - 1, TIM_PSC_RELOAD_MODE_IMMEDIATE);
}
break;
default:
{
result = -RT_ENOSYS;
}
break;
}
return result;
@ -314,7 +314,7 @@ void TIM2_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
if(TIM_GetIntStatus(TIM2, TIM_INT_UPDATE) == SET)
if (TIM_GetIntStatus(TIM2, TIM_INT_UPDATE) == SET)
{
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM2_INDEX].time_device);
@ -332,7 +332,7 @@ void TIM3_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
if(TIM_GetIntStatus(TIM3, TIM_INT_UPDATE) == SET)
if (TIM_GetIntStatus(TIM3, TIM_INT_UPDATE) == SET)
{
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM3_INDEX].time_device);
@ -350,7 +350,7 @@ void TIM4_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
if(TIM_GetIntStatus(TIM4, TIM_INT_UPDATE) == SET)
if (TIM_GetIntStatus(TIM4, TIM_INT_UPDATE) == SET)
{
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM4_INDEX].time_device);
@ -368,7 +368,7 @@ void TIM5_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
if(TIM_GetIntStatus(TIM5, TIM_INT_UPDATE) == SET)
if (TIM_GetIntStatus(TIM5, TIM_INT_UPDATE) == SET)
{
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM5_INDEX].time_device);
@ -386,7 +386,7 @@ void TIM6_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
if(TIM_GetIntStatus(TIM6, TIM_INT_UPDATE) == SET)
if (TIM_GetIntStatus(TIM6, TIM_INT_UPDATE) == SET)
{
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM6_INDEX].time_device);
@ -404,7 +404,7 @@ void TIM7_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
if(TIM_GetIntStatus(TIM7, TIM_INT_UPDATE) == SET)
if (TIM_GetIntStatus(TIM7, TIM_INT_UPDATE) == SET)
{
rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM7_INDEX].time_device);

8
bsp/n32g452xx/Libraries/rt_drivers/drv_log.h
View File

@ -13,15 +13,15 @@
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

76
bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
View File

@ -12,10 +12,10 @@
#include "drv_pwm.h"
#ifdef RT_USING_PWM
#if !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \
!defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4)
#error "Please define at least one BSP_USING_TIMx_CHx"
#endif
#if !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \
!defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4)
#error "Please define at least one BSP_USING_TIMx_CHx"
#endif
#endif /* RT_USING_PWM */
#define DRV_DEBUG
@ -28,7 +28,7 @@ struct rt_device_pwm pwm_device;
struct n32_pwm
{
struct rt_device_pwm pwm_device;
TIM_Module* tim_handle;
TIM_Module *tim_handle;
rt_uint8_t channel;
char *name;
};
@ -58,45 +58,45 @@ static struct rt_pwm_ops drv_ops =
drv_pwm_control
};
static rt_err_t drv_pwm_enable(TIM_Module* TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
static rt_err_t drv_pwm_enable(TIM_Module *TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
/* Get the value of channel */
rt_uint32_t channel = configuration->channel;
if (!enable)
{
if(channel == 1)
if (channel == 1)
{
TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
}
else if(channel == 2)
else if (channel == 2)
{
TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
}
else if(channel == 3)
else if (channel == 3)
{
TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
}
else if(channel == 4)
else if (channel == 4)
{
TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
}
}
else
{
if(channel == 1)
if (channel == 1)
{
TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
}
else if(channel == 2)
else if (channel == 2)
{
TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE);
}
else if(channel == 3)
else if (channel == 3)
{
TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE);
}
else if(channel == 4)
else if (channel == 4)
{
TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE);
}
@ -107,7 +107,7 @@ static rt_err_t drv_pwm_enable(TIM_Module* TIMx, struct rt_pwm_configuration *co
return RT_EOK;
}
static rt_err_t drv_pwm_get(TIM_Module* TIMx, struct rt_pwm_configuration *configuration)
static rt_err_t drv_pwm_get(TIM_Module *TIMx, struct rt_pwm_configuration *configuration)
{
RCC_ClocksType RCC_Clockstruct;
rt_uint32_t ar, div, cc1, cc2, cc3, cc4;
@ -128,19 +128,19 @@ static rt_err_t drv_pwm_get(TIM_Module* TIMx, struct rt_pwm_configuration *confi
/* Convert nanosecond to frequency and duty cycle. */
tim_clock /= 1000000UL;
configuration->period = (ar + 1) * (div + 1) * 1000UL / tim_clock;
if(channel == 1)
if (channel == 1)
configuration->pulse = (cc1 + 1) * (div + 1) * 1000UL / tim_clock;
if(channel == 2)
configuration->pulse = (cc2 + 1) * (div+ 1) * 1000UL / tim_clock;
if(channel == 3)
if (channel == 2)
configuration->pulse = (cc2 + 1) * (div + 1) * 1000UL / tim_clock;
if (channel == 3)
configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock;
if(channel == 4)
if (channel == 4)
configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock;
return RT_EOK;
}
static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *configuration)
static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *configuration)
{
/* Init timer pin and enable clock */
n32_msp_tim_init(TIMx);
@ -155,7 +155,7 @@ static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *confi
}
else
{
if (1 == (RCC_Clock.HclkFreq/RCC_Clock.Pclk1Freq))
if (1 == (RCC_Clock.HclkFreq / RCC_Clock.Pclk1Freq))
input_clock = RCC_Clock.Pclk1Freq;
else
input_clock = RCC_Clock.Pclk1Freq * 2;
@ -186,22 +186,22 @@ static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *confi
TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH;
rt_uint32_t channel = configuration->channel;
if(channel == 1)
if (channel == 1)
{
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
}
else if(channel == 2)
else if (channel == 2)
{
TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
}
else if(channel == 3)
else if (channel == 3)
{
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
}
else if(channel == 4)
else if (channel == 4)
{
TIM_InitOc4(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
@ -220,16 +220,16 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
switch (cmd)
{
case PWM_CMD_ENABLE:
return drv_pwm_enable(TIMx, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return drv_pwm_enable(TIMx, configuration, RT_FALSE);
case PWM_CMD_SET:
return drv_pwm_set(TIMx, configuration);
case PWM_CMD_GET:
return drv_pwm_get(TIMx, configuration);
default:
return RT_EINVAL;
case PWM_CMD_ENABLE:
return drv_pwm_enable(TIMx, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return drv_pwm_enable(TIMx, configuration, RT_FALSE);
case PWM_CMD_SET:
return drv_pwm_set(TIMx, configuration);
case PWM_CMD_GET:
return drv_pwm_get(TIMx, configuration);
default:
return RT_EINVAL;
}
}
@ -238,9 +238,9 @@ static int rt_hw_pwm_init(void)
int i = 0;
int result = RT_EOK;
for(i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++)
for (i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++)
{
if(rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK)
if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK)
{
LOG_D("%s register success", n32_pwm_obj[i].name);
}

22
bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c
View File

@ -17,8 +17,8 @@
#include <drv_log.h>
#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4)
#error "Please define at least one BSP_USING_I2Cx"
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#error "Please define at least one BSP_USING_I2Cx"
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#endif
static const struct n32_soft_i2c_config soft_i2c_config[] =
@ -46,7 +46,7 @@ static struct n32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0
*/
static void n32_i2c_gpio_init(struct n32_i2c *i2c)
{
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)i2c->ops.data;
struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)i2c->ops.data;
rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
@ -63,7 +63,7 @@ static void n32_i2c_gpio_init(struct n32_i2c *i2c)
*/
static void n32_set_sda(void *data, rt_int32_t state)
{
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data;
struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data;
if (state)
{
rt_pin_write(cfg->sda, PIN_HIGH);
@ -82,7 +82,7 @@ static void n32_set_sda(void *data, rt_int32_t state)
*/
static void n32_set_scl(void *data, rt_int32_t state)
{
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data;
struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data;
if (state)
{
rt_pin_write(cfg->scl, PIN_HIGH);
@ -100,7 +100,7 @@ static void n32_set_scl(void *data, rt_int32_t state)
*/
static rt_int32_t n32_get_sda(void *data)
{
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data;
struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data;
return rt_pin_read(cfg->sda);
}
@ -111,7 +111,7 @@ static rt_int32_t n32_get_sda(void *data)
*/
static rt_int32_t n32_get_scl(void *data)
{
struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data;
struct n32_soft_i2c_config *cfg = (struct n32_soft_i2c_config *)data;
return rt_pin_read(cfg->scl);
}
/**
@ -199,7 +199,7 @@ int rt_hw_i2c_init(void)
for (int i = 0; i < obj_num; i++)
{
i2c_obj[i].ops = n32_bit_ops_default;
i2c_obj[i].ops.data = (void*)&soft_i2c_config[i];
i2c_obj[i].ops.data = (void *)&soft_i2c_config[i];
i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops;
n32_i2c_gpio_init(&i2c_obj[i]);
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name);
@ -207,9 +207,9 @@ int rt_hw_i2c_init(void)
n32_i2c_bus_unlock(&soft_i2c_config[i]);
LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].sda);
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].sda);
}
return RT_EOK;

62
bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
View File

@ -51,7 +51,7 @@ static void DMA_Configuration(struct rt_serial_device *serial);
static rt_err_t n32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct n32_uart* uart;
struct n32_uart *uart;
USART_InitType USART_InitStructure;
RT_ASSERT(serial != RT_NULL);
@ -102,14 +102,14 @@ static rt_err_t n32_uart_configure(struct rt_serial_device *serial, struct seria
/* Enable USART */
USART_Enable(uart->uart_device, ENABLE);
USART_ClrFlag(uart->uart_device, USART_FLAG_TXDE|USART_FLAG_TXC);
USART_ClrFlag(uart->uart_device, USART_FLAG_TXDE | USART_FLAG_TXC);
return RT_EOK;
}
static rt_err_t n32_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct n32_uart* uart;
struct n32_uart *uart;
rt_uint32_t ctrl_arg = (rt_uint32_t)(arg);
RT_ASSERT(serial != RT_NULL);
@ -117,34 +117,34 @@ static rt_err_t n32_uart_control(struct rt_serial_device *serial, int cmd, void
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
UART_DISABLE_IRQ(uart->irq);
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
UART_DISABLE_IRQ(uart->irq);
/* disable interrupt */
USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, DISABLE);
break;
USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, DISABLE);
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
UART_ENABLE_IRQ(uart->irq);
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
UART_ENABLE_IRQ(uart->irq);
/* enable interrupt */
USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, ENABLE);
break;
/* USART config */
case RT_DEVICE_CTRL_CONFIG :
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
{
DMA_Configuration(serial);
}
break;
USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, ENABLE);
break;
/* USART config */
case RT_DEVICE_CTRL_CONFIG :
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
{
DMA_Configuration(serial);
}
break;
}
return RT_EOK;
}
static int n32_uart_putc(struct rt_serial_device *serial, char c)
{
struct n32_uart* uart;
struct n32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct n32_uart *)serial->parent.user_data;
@ -171,7 +171,7 @@ static int n32_uart_putc(struct rt_serial_device *serial, char c)
static int n32_uart_getc(struct rt_serial_device *serial)
{
int ch;
struct n32_uart* uart;
struct n32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct n32_uart *)serial->parent.user_data;
@ -250,23 +250,23 @@ static void uart_isr(struct rt_serial_device *serial)
RT_ASSERT(uart != RT_NULL);
if(USART_GetIntStatus(uart->uart_device, USART_INT_RXDNE) != RESET)
if (USART_GetIntStatus(uart->uart_device, USART_INT_RXDNE) != RESET)
{
if(USART_GetFlagStatus(uart->uart_device, USART_FLAG_PEF) == RESET)
if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_PEF) == RESET)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
/* clear interrupt */
USART_ClrIntPendingBit(uart->uart_device, USART_INT_RXDNE);
}
if(USART_GetIntStatus(uart->uart_device, USART_INT_IDLEF) != RESET)
if (USART_GetIntStatus(uart->uart_device, USART_INT_IDLEF) != RESET)
{
dma_uart_rx_idle_isr(serial);
}
if (USART_GetIntStatus(uart->uart_device, USART_INT_TXC) != RESET)
{
/* clear interrupt */
if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
}
@ -443,7 +443,7 @@ void DMA2_Channel3_IRQHandler(void)
}
#endif /* BSP_USING_UART4 */
static void NVIC_Configuration(struct n32_uart* uart)
static void NVIC_Configuration(struct n32_uart *uart)
{
NVIC_InitType NVIC_InitStructure;
@ -473,7 +473,7 @@ static void DMA_Configuration(struct rt_serial_device *serial)
/* rx dma config */
DMA_DeInit(uart->dma.rx_ch);
DMA_InitStructure.PeriphAddr = (uint32_t)&(uart->uart_device->DAT);
DMA_InitStructure.PeriphAddr = (uint32_t) & (uart->uart_device->DAT);
DMA_InitStructure.MemAddr = (uint32_t)(rx_fifo->buffer);
DMA_InitStructure.Direction = DMA_DIR_PERIPH_SRC;
DMA_InitStructure.BufSize = serial->config.bufsz;
@ -500,7 +500,7 @@ static void DMA_Configuration(struct rt_serial_device *serial)
int rt_hw_usart_init(void)
{
struct n32_uart* uart;
struct n32_uart *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#if defined(BSP_USING_UART1)

2
bsp/n32g452xx/n32g452xx-mini-system/board/board.c
View File

@ -15,7 +15,7 @@
#include <board.h>
#ifdef BSP_USING_SRAM
#include "drv_sram.h"
#include "drv_sram.h"
#endif
/**
* @brief This function is executed in case of error occurrence.

72
bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
View File

@ -23,7 +23,7 @@ void n32_msp_usart_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz;
#ifdef BSP_USING_UART1
if(USART1 == USARTx)
if (USART1 == USARTx)
{
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
@ -37,7 +37,7 @@ void n32_msp_usart_init(void *Instance)
}
#endif
#ifdef BSP_USING_UART2
if(USART2 == USARTx)
if (USART2 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
@ -51,7 +51,7 @@ void n32_msp_usart_init(void *Instance)
}
#endif
#ifdef BSP_USING_UART3
if(USART3 == USARTx)
if (USART3 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
@ -65,7 +65,7 @@ void n32_msp_usart_init(void *Instance)
}
#endif
#ifdef BSP_USING_UART4
if(UART4 == USARTx)
if (UART4 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
@ -91,7 +91,7 @@ void n32_msp_spi_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz;
#ifdef BSP_USING_SPI1
if(SPI1 == SPIx)
if (SPI1 == SPIx)
{
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
@ -108,7 +108,7 @@ void n32_msp_spi_init(void *Instance)
}
#endif
#ifdef BSP_USING_SPI2
if(SPI2 == SPIx)
if (SPI2 == SPIx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
@ -137,7 +137,7 @@ void n32_msp_sdio_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStructure);
GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
if(SDIO == SDIOx)
if (SDIO == SDIOx)
{
/* if used dma ... */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_DMA2, ENABLE);
@ -162,7 +162,7 @@ void n32_msp_tim_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStructure);
TIM_Module *TIMx = (TIM_Module *)Instance;
if(TIMx == TIM1)
if (TIMx == TIM1)
{
/* TIM1 clock enable */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE);
@ -177,7 +177,7 @@ void n32_msp_tim_init(void *Instance)
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
}
if(TIMx == TIM2)
if (TIMx == TIM2)
{
/* TIM2 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE);
@ -192,12 +192,12 @@ void n32_msp_tim_init(void *Instance)
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
}
if(TIMx == TIM3)
if (TIMx == TIM3)
{
/* TIM3 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE);
/* GPIOA clock enable */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA|RCC_APB2_PERIPH_GPIOB, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7;
GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
@ -218,15 +218,15 @@ void n32_msp_adc_init(void *Instance)
ADC_Module *ADCx = (ADC_Module *)Instance;
#ifdef BSP_USING_ADC1
if(ADCx == ADC1)
if (ADCx == ADC1)
{
/* ADC1 & GPIO clock enable */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC1, ENABLE);
ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB,RCC_ADCHCLK_DIV8);
ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV8);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
/* Configure ADC Channel as analog input */
GPIO_InitCtlStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitCtlStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3;
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
@ -234,11 +234,11 @@ void n32_msp_adc_init(void *Instance)
#endif
#ifdef BSP_USING_ADC2
if(ADCx == ADC2)
if (ADCx == ADC2)
{
/* ADC2 & GPIO clock enable */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE);
ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB,RCC_ADCHCLK_DIV8);
ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV8);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
/* Configure ADC Channel as analog input */
@ -257,7 +257,7 @@ void n32_msp_hwtim_init(void *Instance)
TIM_Module *TIMx = (TIM_Module *)Instance;
#ifdef BSP_USING_HWTIM3
if(TIMx == TIM3)
if (TIMx == TIM3)
{
/* TIM3 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE);
@ -265,7 +265,7 @@ void n32_msp_hwtim_init(void *Instance)
#endif
#ifdef BSP_USING_HWTIM4
if(TIMx == TIM4)
if (TIMx == TIM4)
{
/* TIM4 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE);
@ -273,7 +273,7 @@ void n32_msp_hwtim_init(void *Instance)
#endif
#ifdef BSP_USING_HWTIM5
if(TIMx == TIM5)
if (TIMx == TIM5)
{
/* TIM5 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE);
@ -281,19 +281,19 @@ void n32_msp_hwtim_init(void *Instance)
#endif
#ifdef BSP_USING_HWTIM6
if(TIMx == TIM6)
{
/* TIM6 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE);
}
if (TIMx == TIM6)
{
/* TIM6 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE);
}
#endif
#ifdef BSP_USING_HWTIM7
if(TIMx == TIM7)
{
/* TIM7 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM7, ENABLE);
}
if (TIMx == TIM7)
{
/* TIM7 clock enable */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM7, ENABLE);
}
#endif
}
#endif
@ -307,7 +307,7 @@ void n32_msp_can_init(void *Instance)
GPIO_InitStruct(&GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz;
#ifdef BSP_USING_CAN1
if(CAN1 == CANx)
if (CAN1 == CANx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN1, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
@ -321,7 +321,7 @@ void n32_msp_can_init(void *Instance)
}
#endif
#ifdef BSP_USING_CAN2
if(CAN2 == CANx)
if (CAN2 == CANx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
@ -347,7 +347,7 @@ static void uart_test_rw(rt_device_t uartx, const char *name)
if (uartx == NULL)
{
uartx = rt_device_find(name);
rt_err_t err = rt_device_open(uartx, RT_DEVICE_FLAG_INT_RX|RT_DEVICE_FLAG_DMA_RX);
rt_err_t err = rt_device_open(uartx, RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX);
RT_ASSERT(err == RT_EOK);
}
rt_device_write(uartx, 0, name, strlen(name));
@ -356,7 +356,7 @@ static void uart_test_rw(rt_device_t uartx, const char *name)
int ret = rt_device_read(uartx, 0, recv_buf, sizeof(recv_buf));
if (ret != 0)
{
for (int i=0; i<ret; ++i)
for (int i = 0; i < ret; ++i)
rt_kprintf("[%02x]", recv_buf[i]);
}
rt_device_write(uartx, 0, "\r\n", 2);
@ -377,9 +377,9 @@ MSH_CMD_EXPORT(uart_test, uart_test)
#ifdef BSP_USING_ADC
#ifdef BSP_USING_ADC1
#define ADC_DEV_NAME "adc1"
#define ADC_DEV_NAME "adc1"
#else
#define ADC_DEV_NAME "adc2"
#define ADC_DEV_NAME "adc2"
#endif
#define REFER_VOLTAGE 3300
#define CONVERT_BITS (1 << 12)
@ -396,7 +396,7 @@ static int adc_vol_sample(int argc, char *argv[])
return RT_ERROR;
}
for (int i=6; i<=9; ++i)
for (int i = 6; i <= 9; ++i)
{
ret = rt_adc_enable(adc_dev, i);
value = rt_adc_read(adc_dev, i);

459
bsp/n32g452xx/n32g452xx-mini-system/project.uvprojx
View File

@ -390,9 +390,9 @@
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>backtrace.c</FileName>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
<FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
</File>
</Files>
<Files>
@ -404,9 +404,9 @@
</Files>
<Files>
<File>
<FileName>showmem.c</FileName>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
</File>
</Files>
<Files>
@ -447,20 +447,6 @@
<FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pipe.c</FileName>
@ -468,6 +454,13 @@
<FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>completion.c</FileName>
@ -475,13 +468,6 @@
<FilePath>..\..\..\components\drivers\src\completion.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ringblk_buf.c</FileName>
@ -491,9 +477,23 @@
</Files>
<Files>
<File>
<FileName>ringbuffer.c</FileName>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
<FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath>
</File>
</Files>
</Group>
@ -508,16 +508,16 @@
</Files>
<Files>
<File>
<FileName>startup_n32g45x.s</FileName>
<FileType>2</FileType>
<FilePath>..\Libraries\N32_Std_Driver\CMSIS\device\startup\startup_n32g45x.s</FilePath>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
<FileName>startup_n32g45x.s</FileName>
<FileType>2</FileType>
<FilePath>..\Libraries\N32_Std_Driver\CMSIS\device\startup\startup_n32g45x.s</FilePath>
</File>
</Files>
<Files>
@ -577,16 +577,9 @@
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>clock.c</FileName>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\clock.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\thread.c</FilePath>
<FilePath>..\..\..\src\irq.c</FilePath>
</File>
</Files>
<Files>
@ -596,6 +589,34 @@
<FilePath>..\..\..\src\mempool.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\clock.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\timer.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>scheduler.c</FileName>
@ -612,44 +633,9 @@
</Files>
<Files>
<File>
<FileName>idle.c</FileName>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\idle.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\timer.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mem.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\irq.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath>
<FilePath>..\..\..\src\thread.c</FilePath>
</File>
</Files>
<Files>
@ -666,9 +652,30 @@
<FilePath>..\..\..\src\kservice.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\idle.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mem.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>libc</GroupName>
<Files>
<File>
<FileName>libc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\libc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>syscalls.c</FileName>
@ -685,9 +692,9 @@
</Files>
<Files>
<File>
<FileName>libc.c</FileName>
<FileName>time.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\libc.c</FilePath>
<FilePath>..\..\..\components\libc\compilers\common\time.c</FilePath>
</File>
</Files>
<Files>
@ -697,16 +704,86 @@
<FilePath>..\..\..\components\libc\compilers\common\stdlib.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>time.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\time.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Libraries</GroupName>
<Files>
<File>
<FileName>n32g45x_wwdg.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_wwdg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_adc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_comp.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_comp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_eth.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_eth.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_i2c.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_pwr.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_flash.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_flash.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_spi.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_exti.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_exti.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_xfmc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_xfmc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_rtc.c</FileName>
@ -714,6 +791,20 @@
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rtc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_crc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_crc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_iwdg.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_iwdg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_qspi.c</FileName>
@ -723,16 +814,23 @@
</Files>
<Files>
<File>
<FileName>n32g45x_sdio.c</FileName>
<FileName>n32g45x_tsc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_sdio.c</FilePath>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tsc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_eth.c</FileName>
<FileName>n32g45x_opamp.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_eth.c</FilePath>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_opamp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_tim.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tim.c</FilePath>
</File>
</Files>
<Files>
@ -749,139 +847,6 @@
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dma.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_usart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_adc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_dvp.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dvp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_opamp.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_opamp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>misc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\misc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_spi.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_dac.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dac.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_exti.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_exti.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_xfmc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_xfmc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_can.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_can.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_pwr.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_i2c.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_wwdg.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_wwdg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_dbg.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dbg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_tim.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tim.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_crc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_crc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_tsc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tsc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_iwdg.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_iwdg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_rcc.c</FileName>
@ -889,6 +854,13 @@
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rcc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_usart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>system_n32g45x.c</FileName>
@ -898,16 +870,45 @@
</Files>
<Files>
<File>
<FileName>n32g45x_comp.c</FileName>
<FileName>n32g45x_dvp.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_comp.c</FilePath>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dvp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_flash.c</FileName>
<FileName>n32g45x_can.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_flash.c</FilePath>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_can.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_dbg.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dbg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>misc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\misc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_dac.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dac.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>n32g45x_sdio.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_sdio.c</FilePath>
</File>
</Files>
</Group>

598
bsp/ra6m4-cpk/.config Normal file
View File

@ -0,0 +1,598 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart7"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_SERIAL_V1 is not set
CONFIG_RT_USING_SERIAL_V2=y
CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
CONFIG_RT_LIBC_USING_TIME=y
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_PTHREADS is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
#
# system packages
#
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_SERIES_R7FA6M4AF=y
#
# Onboard Peripheral Drivers
#
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_ONCHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART7=y
# CONFIG_BSP_UART7_RX_USING_DMA is not set
# CONFIG_BSP_UART7_TX_USING_DMA is not set
CONFIG_BSP_UART7_RX_BUFSIZE=256
CONFIG_BSP_UART7_TX_BUFSIZE=0
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_PWM is not set
#
# Board extended module Drivers
#
CONFIG_SOC_FAMILY_RENESAS=y

8
bsp/ra6m4-cpk/.ignore_format.yml Normal file
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@ -0,0 +1,8 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- ra
- ra_gen
- ra_cfg

21
bsp/ra6m4-cpk/.settings/standalone.prefs Normal file
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@ -0,0 +1,21 @@
#Wed Nov 03 20:31:16 CST 2021
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.1.0/all=1390983687,ra/fsp/inc/instances/r_ioport.h|3204787724,ra/fsp/src/r_ioport/r_ioport.c|1957950123,ra/fsp/inc/api/r_ioport_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.1.0/all=2545672180,ra/fsp/inc/instances/r_icu.h|3018483678,ra/fsp/src/r_icu/r_icu.c|1906465970,ra/fsp/inc/api/r_external_irq_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.1.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.1.0/all=568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1222394411,ra/fsp/src/bsp/mcu/all/bsp_io.c|3098075304,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|905231975,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3590501432,ra/fsp/src/bsp/mcu/all/bsp_io.h|1868795951,ra/fsp/inc/fsp_features.h|2556589544,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3581546608,ra/fsp/inc/fsp_common_api.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|496115995,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|2812024316,ra/fsp/src/bsp/mcu/all/bsp_common.h|1390983687,ra/fsp/inc/instances/r_ioport.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|4191472725,ra/fsp/inc/fsp_version.h|2247478812,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3131094294,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3366593968,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3520119047,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1982083345,ra/fsp/src/bsp/mcu/all/bsp_security.c|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3819230577,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|2966752275,ra/fsp/src/bsp/mcu/all/bsp_delay.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2006974055,ra/fsp/inc/api/bsp_api.h|1957950123,ra/fsp/inc/api/r_ioport_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.7.0+fsp.3.1.0/libraries=
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#R7FA6M4AF3CFB\#\#3.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.7.0+fsp.3.1.0/all=2686445441,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2491522803,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2748964184,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|3589068132,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1536854638,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|206980015,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|4005730526,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1078551279,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|546157604,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|1562896660,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3021372151,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3602366610,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2024281644,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|4231934849,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|3442821435,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|637879414,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|377628369,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|3779323067,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.1.0/all=2349328507,ra/fsp/src/r_sci_uart/r_sci_uart.c|1672784957,ra/fsp/inc/instances/r_sci_uart.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|853178775,ra/fsp/inc/api/r_uart_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.1.0/all=2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h|3852442662,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h|3571093944,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.1.0/libraries=
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.813326093=false
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.1.0/all=3843040667,ra/board/ra6m4_cpk/board_leds.h|2525887392,ra/board/ra6m4_cpk/board_ethernet_phy.h|3559227370,ra/board/ra6m4_cpk/board_init.c|2967196421,ra/board/ra6m4_cpk/board_init.h|3343992478,ra/board/ra6m4_cpk/board.h|3938710240,ra/board/ra6m4_cpk/board_leds.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.1.0/libraries=

38
bsp/ra6m4-cpk/Kconfig Normal file
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@ -0,0 +1,38 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
config ENV_DIR
string
option env="ENV_ROOT"
default "/"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "$BSP_DIR/drivers/Kconfig"
config SOC_FAMILY_RENESAS
bool
default y
config SOC_SERIES_R7FA6M4AF
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_RENESAS
default y

36
bsp/ra6m4-cpk/R7FA6M4AF3CFB.pincfg Normal file
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@ -0,0 +1,36 @@
<?xml version="1.0" encoding="utf-8"?>
<v1:pinSettings xmlns:v1="http://www.tasking.com/schema/pinsettings/v1.1">
<v1:pinMappingsRef version="2.05" file="" />
<v1:deviceSetting id="renesas.ra6m4_fb" pattern="R7FA6M4****FB">
<v1:packageSetting id="renesas.144lqfp" />
</v1:deviceSetting>
<v1:configSetting configurationId="debug0.mode" altId="debug0.mode.jtag" />
<v1:configSetting configurationId="p108.gpio_mode" altId="p108.gpio_mode.gpio_mode_peripheral" />
<v1:configSetting configurationId="p108" altId="p108.debug0.tms">
<v1:connectionSetting altId="debug0.tms.p108" />
</v1:configSetting>
<v1:configSetting configurationId="debug0.tms" altId="debug0.tms.p108">
<v1:connectionSetting altId="p108.debug0.tms" />
</v1:configSetting>
<v1:configSetting configurationId="p109.gpio_mode" altId="p109.gpio_mode.gpio_mode_peripheral" />
<v1:configSetting configurationId="p109" altId="p109.debug0.tdo">
<v1:connectionSetting altId="debug0.tdo.p109" />
</v1:configSetting>
<v1:configSetting configurationId="debug0.tdo" altId="debug0.tdo.p109">
<v1:connectionSetting altId="p109.debug0.tdo" />
</v1:configSetting>
<v1:configSetting configurationId="p110.gpio_mode" altId="p110.gpio_mode.gpio_mode_peripheral" />
<v1:configSetting configurationId="p110" altId="p110.debug0.tdi">
<v1:connectionSetting altId="debug0.tdi.p110" />
</v1:configSetting>
<v1:configSetting configurationId="debug0.tdi" altId="debug0.tdi.p110">
<v1:connectionSetting altId="p110.debug0.tdi" />
</v1:configSetting>
<v1:configSetting configurationId="p300.gpio_mode" altId="p300.gpio_mode.gpio_mode_peripheral" />
<v1:configSetting configurationId="p300" altId="p300.debug0.tck">
<v1:connectionSetting altId="debug0.tck.p300" />
</v1:configSetting>
<v1:configSetting configurationId="debug0.tck" altId="debug0.tck.p300">
<v1:connectionSetting altId="p300.debug0.tck" />
</v1:configSetting>
</v1:pinSettings>

174
bsp/ra6m4-cpk/README.md Normal file
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@ -0,0 +1,174 @@
# 瑞萨 CPK-RA6M4 开发板 BSP 说明
## 简介
本文档为瑞萨 CPK-RA6M4 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
主要内容如下：
- 开发板介绍
- BSP 快速上手指南
## 开发板介绍
基于瑞萨 RA6M4 MCU 开发的 CPK-RA6M4 MCU 评估板，通过灵活配置软件包和 IDE，可帮助用户对 RA6M4 MCU 群组的特性轻松进行评估，并对嵌入系统应用程序进行开发。
开发板正面外观如下图：
![image-20211011174017429](docs/picture/cpk-ra6m4.png)
该开发板常用 **板载资源** 如下：
- MCU：R7FA6M4AF3CFB，200MHz，Arm Cortex®-M33 内核，1MB 代码闪存, 256kB SRAM
- 调试接口：板载 J-Link 接口
- 扩展接口：两个 PMOD 连接器
**更多详细资料及工具**
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------------- | :------------- |
| UART | 支持 | UART7 |
| GPIO | 支持 | |
| IIC | 支持 | 软件 |
| WDT | 支持 | |
| RTC | 支持 | |
| ADC | 支持 | |
| DAC | 支持 | |
| SPI | 支持 | |
| FLASH | 支持 | |
| PWM | 支持 | |
| 持续更新中... | | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 目前仅提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
**硬件连接**
使用 USB 数据线连接开发板到 PC。使用 USB 转串口工具连接 P613(TXD)、P614(RXD)。
**编译下载**
- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
> 注意：此工程需要使用 J-Flash Lite 工具烧录程序。建议使用 V7.50 及以上版本烧录工程。[J-Link 下载链接](https://www.segger.com/downloads/jlink/)
- 下载：打开 J-Flash lite 工具，选择芯片型号 R7FA6M4AF，点击 OK 进入工具。选择 BSP 目录下 MDK 编译出的 /object/ra6m4.hex 文件，点击 Program Device 按钮开始烧录。具体操作过程可参考下图步骤：
![image-20211011181555421](docs/picture/jflash1.png)
![image-20211011182047981](docs/picture/jflash2.png)
![image-20211011182434519](docs/picture/jflash.png)
![image-20211011182949604](docs/picture/jflash3.png)
**查看运行结果**
下载程序成功之后，系统会自动运行并打印系统信息。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.4 build Oct 11 2021
2006 - 2021 Copyright by rt-thread team
Hello RT-Thread!
msh >
msh >help
RT-Thread shell commands:
reboot - Reboot System
help - RT - Thread shell help.
ps - List threads in the system.
free - Show the memory usage in the system.
hello - say hello world
clear - clear the terminal screen
version - show RT - Thread version information
list_thread - list thread
list_sem - list semaphore in system
list_event - list event in system
list_mutex - list mutex in system
list_mailbox - list mail box in system
list_msgqueue - list message queue in system
list_timer - list timer in system
list_device - list device in system
list - list all commands in system
msh >
```
**应用入口函数**
应用层的入口函数在 **bsp\ra6m4-cpk\src\hal_emtry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
```c
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
while (1)
{
rt_pin_write(LED3_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED3_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### 进阶使用
**资料及文档**
- [开发板官网主页](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/cpk-ra6m4-evaluation-board)
- [开发板用户手册](https://www2.renesas.cn/cn/zh/document/mah/1527156?language=zh&r=1527191)
- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091)
- [RA6 MCU 快速设计指南](https://www2.renesas.cn/cn/zh/document/apn/ra6-quick-design-guide)
- [RA6M4_datasheet](https://www2.renesas.cn/cn/zh/document/dst/ra6m4-group-datasheet)
- [RA6M4 Group User’s Manual: Hardware](https://www2.renesas.cn/cn/zh/document/man/ra6m4-group-user-s-manual-hardware)
**FSP 配置**
需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)
2. 下载安装完成后，需要添加 CPK-RA6M4 开发板的[官方板级支持包](https://www2.renesas.cn/document/sws/1527176?language=zh&r=1527191)
3. 如何将 BSP 配置包添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
4. 请查看文档：[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置，
**ENV 配置**
- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
此 BSP 默认只开启了 串口7 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
## 贡献代码
如果您对 CPK-RA6M4 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github) 。

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@ -0,0 +1,14 @@
# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

40
bsp/ra6m4-cpk/SConstruct Normal file
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@ -0,0 +1,40 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
<vendor>Renesas</vendor>
<name>Project Content</name>
<description>Project content managed by the Renesas Smart Configurator</description>
<url/>
<releases>
<release version="1.0.0"/>
</releases>
<generators>
<generator id="Renesas RA Smart Configurator">
<project_files>
<file category="include" name="src/"/>
<file category="source" name="src/hal_entry.c"/>
<file category="other" name="src/SConscript"/>
</project_files>
</generator>
</generators>
<components generator="Renesas RA Smart Configurator">
<component Cclass="Flex Software" Cgroup="Components" Csub="ra">
<files>
<file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
<file category="include" name="ra/fsp/inc/"/>
<file category="include" name="ra/fsp/inc/api/"/>
<file category="include" name="ra/fsp/inc/instances/"/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
<file category="header" name="ra/board/ra6m4_cpk/board.h" path=""/>
<file category="header" name="ra/board/ra6m4_cpk/board_ethernet_phy.h" path=""/>
<file category="source" name="ra/board/ra6m4_cpk/board_init.c"/>
<file category="header" name="ra/board/ra6m4_cpk/board_init.h" path=""/>
<file category="source" name="ra/board/ra6m4_cpk/board_leds.c"/>
<file category="header" name="ra/board/ra6m4_cpk/board_leds.h" path=""/>
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_external_irq_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_icu.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h" path=""/>
<file category="source" name="ra/fsp/src/r_icu/r_icu.c"/>
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
<file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
<file category="other" name="ra/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Build Configuration">
<files>
<file category="include" name="ra_cfg/fsp_cfg/"/>
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_icu_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
<file category="other" name="ra_cfg/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Generated Data">
<files>
<file category="include" name="ra_gen/"/>
<file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
<file category="source" name="ra_gen/common_data.c"/>
<file category="header" name="ra_gen/common_data.h" path=""/>
<file category="source" name="ra_gen/hal_data.c"/>
<file category="header" name="ra_gen/hal_data.h" path=""/>
<file category="source" name="ra_gen/main.c"/>
<file category="source" name="ra_gen/pin_data.c"/>
<file category="other" name="ra_gen/SConscript"/>
<file category="source" name="ra_gen/vector_data.c"/>
<file category="header" name="ra_gen/vector_data.h" path=""/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Linker Script">
<files>
<file category="linkerScript" name="script/fsp.scat"/>
<file category="other" name="script/ac6/fsp_keep.via"/>
</files>
</component>
</components>
</package>

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="6">
<generalSettings>
<option key="#Board#" value="board.ra6m4cpk"/>
<option key="CPU" value="RA6M4"/>
<option key="#TargetName#" value="R7FA6M4AF3CFB"/>
<option key="#TargetARCHITECTURE#" value="cortex-m33"/>
<option key="#DeviceCommand#" value="R7FA6M4AF"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA6M4AF3CFB.pincfg"/>
<option key="#FSPVersion#" value="3.1.0"/>
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra6m4_cpk##"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raBspConfiguration>
<config id="config.bsp.ra6m4.R7FA6M4AF3CFB">
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
<property id="config.bsp.rom_size_bytes_hidden" value="1048576"/>
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
</config>
<config id="config.bsp.ra6m4">
<property id="config.bsp.series" value="config.bsp.series.value"/>
</config>
<config id="config.bsp.ra6m4.fsp">
<property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
<property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
<property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
<property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
<property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/>
<property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
<property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/>
<property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/>
<property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
<property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
<property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/>
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
<property id="config.bsp.fsp.BPS.BPS0" value=""/>
<property id="config.bsp.fsp.BPS.BPS1" value=""/>
<property id="config.bsp.fsp.BPS.BPS2" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS2" value=""/>
<property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/>
<property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/>
<property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="20000000"/>
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/>
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/>
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
</config>
<config id="config.bsp.ra">
<property id="config.bsp.common.main" value="0x400"/>
<property id="config.bsp.common.heap" value="0"/>
<property id="config.bsp.common.vcc" value="3300"/>
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
</config>
</raBspConfiguration>
<raClockConfiguration>
<node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
<node id="board.clock.pll.source" option="board.clock.pll.source.hoco"/>
<node id="board.clock.pll.div" option="board.clock.pll.div.2"/>
<node id="board.clock.pll.mul" option="board.clock.pll.mul.200"/>
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
<node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
<node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
<node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/>
<node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
<node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.uclk.source" option="board.clock.uclk.source.disabled"/>
<node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
<node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/>
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
<node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
<node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.1"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
<node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
</raClockConfiguration>
<raComponentSelection>
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="3.1.0">
<description>Board Support Package Common Files</description>
<originalPack>Renesas.RA.3.1.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="3.1.0">
<description>I/O Port</description>
<originalPack>Renesas.RA.3.1.0.pack</originalPack>
</component>
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.7.0+fsp.3.1.0">
<description>Arm CMSIS Version 5 - Core (M)</description>
<originalPack>Arm.CMSIS5.5.7.0+fsp.3.1.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="Board" subgroup="ra6m4_cpk" variant="" vendor="Renesas" version="3.1.0">
<description>RA6M4-CPK Board Support Files</description>
<originalPack>Renesas.RA_board_ra6m4_cpk.3.1.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m4" subgroup="device" variant="R7FA6M4AF3CFB" vendor="Renesas" version="3.1.0">
<description>Board support package for R7FA6M4AF3CFB</description>
<originalPack>Renesas.RA_mcu_ra6m4.3.1.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m4" subgroup="device" variant="" vendor="Renesas" version="3.1.0">
<description>Board support package for RA6M4</description>
<originalPack>Renesas.RA_mcu_ra6m4.3.1.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m4" subgroup="fsp" variant="" vendor="Renesas" version="3.1.0">
<description>Board support package for RA6M4 - FSP Data</description>
<originalPack>Renesas.RA_mcu_ra6m4.3.1.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="3.1.0">
<description>SCI UART</description>
<originalPack>Renesas.RA.3.1.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_icu" variant="" vendor="Renesas" version="3.1.0">
<description>External Interrupt</description>
<originalPack>Renesas.RA.3.1.0.pack</originalPack>
</component>
</raComponentSelection>
<raElcConfiguration/>
<raIcuConfiguration/>
<raModuleConfiguration>
<module id="module.driver.ioport_on_ioport.0">
<property id="module.driver.ioport.name" value="g_ioport"/>
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
</module>
<module id="module.driver.uart_on_sci_uart.813326093">
<property id="module.driver.uart.name" value="g_uart7"/>
<property id="module.driver.uart.channel" value="7"/>
<property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
<property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
<property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
<property id="module.driver.uart.baud" value="115200"/>
<property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
<property id="module.driver.uart.baudrate_max_err" value="5"/>
<property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
<property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
<property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
<property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
<property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
<property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
<property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
<property id="module.driver.uart.callback" value="uart7_isr_cb"/>
<property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
</module>
<module id="module.driver.external_irq_on_icu.402865750">
<property id="module.driver.external_irq.name" value="g_external_irq0"/>
<property id="module.driver.external_irq.channel" value="0"/>
<property id="module.driver.external_irq.trigger" value="module.driver.external_irq.trigger.trig_rising"/>
<property id="module.driver.external_irq.filter_enable" value="module.driver.external_irq.filter_enable.false"/>
<property id="module.driver.external_irq.pclk_div" value="module.driver.external_irq.pclk_div.pclk_div_by_64"/>
<property id="module.driver.external_irq.p_callback" value="irq0_callback"/>
<property id="module.driver.external_irq.ipl" value="board.icu.common.irq.priority12"/>
</module>
<context id="_hal.0">
<stack module="module.driver.ioport_on_ioport.0"/>
<stack module="module.driver.uart_on_sci_uart.813326093"/>
<stack module="module.driver.external_irq_on_icu.402865750"/>
</context>
<config id="config.driver.ioport">
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
</config>
<config id="config.driver.icu">
<property id="config.driver.icu.param_checking_enable" value="config.driver.icu.param_checking_enable.bsp"/>
</config>
<config id="config.driver.sci_uart">
<property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
<property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
<property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
</config>
</raModuleConfiguration>
<raPinConfiguration>
<symbolicName propertyId="p000.symbolic_name" value="ARDUINO_AN00"/>
<symbolicName propertyId="p001.symbolic_name" value="ARDUINO_AN01"/>
<symbolicName propertyId="p002.symbolic_name" value="ARDUINO_AN02"/>
<symbolicName propertyId="p003.symbolic_name" value="ARDUINO_AN03"/>
<symbolicName propertyId="p004.symbolic_name" value="ARDUINO_AN04"/>
<symbolicName propertyId="p005.symbolic_name" value="ARDUINO_AN05"/>
<symbolicName propertyId="p006.symbolic_name" value="PMODA_IRQ11"/>
<symbolicName propertyId="p007.symbolic_name" value="J4_PIN23"/>
<symbolicName propertyId="p008.symbolic_name" value="PMODA_IO1"/>
<symbolicName propertyId="p009.symbolic_name" value="J4_PIN26"/>
<symbolicName propertyId="p014.symbolic_name" value="PMODA_IO2"/>
<symbolicName propertyId="p015.symbolic_name" value="PMODA_IO3"/>
<symbolicName propertyId="p100.symbolic_name" value="J1_PIN1"/>
<symbolicName propertyId="p101.symbolic_name" value="J2_PIN4"/>
<symbolicName propertyId="p102.symbolic_name" value="J2_PIN6"/>
<symbolicName propertyId="p103.symbolic_name" value="J1_PIN29"/>
<symbolicName propertyId="p104.symbolic_name" value="J3_PIN39"/>
<symbolicName propertyId="p105.symbolic_name" value="SW1"/>
<symbolicName propertyId="p106.symbolic_name" value="LED3"/>
<symbolicName propertyId="p107.symbolic_name" value="J3_PIN37"/>
<symbolicName propertyId="p108.symbolic_name" value="DEBUG_SWDIO_TMS"/>
<symbolicName propertyId="p109.symbolic_name" value="DEBUG_TDO"/>
<symbolicName propertyId="p110.symbolic_name" value="DEBUG_TDI"/>
<symbolicName propertyId="p111.symbolic_name" value="J1_PIN33"/>
<symbolicName propertyId="p112.symbolic_name" value="J3_PIN15"/>
<symbolicName propertyId="p113.symbolic_name" value="J3_PIN16"/>
<symbolicName propertyId="p114.symbolic_name" value="J3_PIN17"/>
<symbolicName propertyId="p115.symbolic_name" value="J3_PIN18"/>
<symbolicName propertyId="p200.symbolic_name" value="NMI"/>
<symbolicName propertyId="p201.symbolic_name" value="MD"/>
<symbolicName propertyId="p202.symbolic_name" value="PMODA_MISO_RXD9"/>
<symbolicName propertyId="p203.symbolic_name" value="PMODA_MOSI_TXD9"/>
<symbolicName propertyId="p204.symbolic_name" value="PMODA_RSPCK"/>
<symbolicName propertyId="p205.symbolic_name" value="PMODA_SSL_CTS9"/>
<symbolicName propertyId="p206.symbolic_name" value="J1_PIN3"/>
<symbolicName propertyId="p207.symbolic_name" value="J1_PIN8"/>
<symbolicName propertyId="p208.symbolic_name" value="J1_PIN32"/>
<symbolicName propertyId="p209.symbolic_name" value="J1_PIN30"/>
<symbolicName propertyId="p210.symbolic_name" value="J1_PIN28"/>
<symbolicName propertyId="p211.symbolic_name" value="J1_PIN22"/>
<symbolicName propertyId="p212.symbolic_name" value="EXTAL"/>
<symbolicName propertyId="p213.symbolic_name" value="XTAL"/>
<symbolicName propertyId="p214.symbolic_name" value="J1_PIN20"/>
<symbolicName propertyId="p300.symbolic_name" value="DEBUG_SWDCLK_TCK"/>
<symbolicName propertyId="p301.symbolic_name" value="J1_PIN11"/>
<symbolicName propertyId="p302.symbolic_name" value="J3_PIN14"/>
<symbolicName propertyId="p303.symbolic_name" value="J3_PIN13"/>
<symbolicName propertyId="p304.symbolic_name" value="J3_PIN12"/>
<symbolicName propertyId="p305.symbolic_name" value="J3_PIN11"/>
<symbolicName propertyId="p306.symbolic_name" value="J3_PIN10"/>
<symbolicName propertyId="p307.symbolic_name" value="J3_PIN9"/>
<symbolicName propertyId="p308.symbolic_name" value="J3_PIN8"/>
<symbolicName propertyId="p309.symbolic_name" value="J3_PIN7"/>
<symbolicName propertyId="p310.symbolic_name" value="J3_PIN6"/>
<symbolicName propertyId="p311.symbolic_name" value="J3_PIN5"/>
<symbolicName propertyId="p312.symbolic_name" value="J3_PIN4"/>
<symbolicName propertyId="p313.symbolic_name" value="J1_PIN14"/>
<symbolicName propertyId="p400.symbolic_name" value="J4_PIN13"/>
<symbolicName propertyId="p401.symbolic_name" value="J4_PIN11"/>
<symbolicName propertyId="p402.symbolic_name" value="J1_PIN27"/>
<symbolicName propertyId="p403.symbolic_name" value="J4_PIN2"/>
<symbolicName propertyId="p404.symbolic_name" value="J4_PIN4"/>
<symbolicName propertyId="p405.symbolic_name" value="J4_PIN6"/>
<symbolicName propertyId="p406.symbolic_name" value="J4_PIN8"/>
<symbolicName propertyId="p407.symbolic_name" value="USB_VBUS_DETECT"/>
<symbolicName propertyId="p408.symbolic_name" value="J2_PIN16"/>
<symbolicName propertyId="p409.symbolic_name" value="J2_PIN18"/>
<symbolicName propertyId="p410.symbolic_name" value="PMODB_MISO_RXD0"/>
<symbolicName propertyId="p411.symbolic_name" value="PMODB_MOSI_TXD0"/>
<symbolicName propertyId="p412.symbolic_name" value="PMODB_RSPCK"/>
<symbolicName propertyId="p413.symbolic_name" value="PMODB_SSL_CTS0"/>
<symbolicName propertyId="p414.symbolic_name" value="ARDUINO_RST"/>
<symbolicName propertyId="p415.symbolic_name" value="PMODB_IO1"/>
<symbolicName propertyId="p500.symbolic_name" value="USB_VBUS_EN"/>
<symbolicName propertyId="p501.symbolic_name" value="USB_OC"/>
<symbolicName propertyId="p502.symbolic_name" value="J4_PIN16"/>
<symbolicName propertyId="p503.symbolic_name" value="PMODB_IO2"/>
<symbolicName propertyId="p504.symbolic_name" value="PMODB_IO3"/>
<symbolicName propertyId="p505.symbolic_name" value="DLS_IRQ14"/>
<symbolicName propertyId="p506.symbolic_name" value="PMODB_IRQ15"/>
<symbolicName propertyId="p507.symbolic_name" value="J4_PIN24"/>
<symbolicName propertyId="p511.symbolic_name" value="DLS_SDA"/>
<symbolicName propertyId="p512.symbolic_name" value="DLS_SCL"/>
<symbolicName propertyId="p600.symbolic_name" value="J1_PIN23"/>
<symbolicName propertyId="p601.symbolic_name" value="J1_PIN19"/>
<symbolicName propertyId="p602.symbolic_name" value="J1_PIN21"/>
<symbolicName propertyId="p603.symbolic_name" value="J1_PIN25"/>
<symbolicName propertyId="p604.symbolic_name" value="J3_PIN36"/>
<symbolicName propertyId="p605.symbolic_name" value="J3_PIN35"/>
<symbolicName propertyId="p608.symbolic_name" value="J3_PIN19"/>
<symbolicName propertyId="p609.symbolic_name" value="J3_PIN20"/>
<symbolicName propertyId="p610.symbolic_name" value="J3_PIN21"/>
<symbolicName propertyId="p611.symbolic_name" value="ARDUINO_GPIO_CLK"/>
<symbolicName propertyId="p612.symbolic_name" value="J3_PIN23"/>
<symbolicName propertyId="p613.symbolic_name" value="ARDUINO_TXD"/>
<symbolicName propertyId="p614.symbolic_name" value="ARDUINO_RXD"/>
<symbolicName propertyId="p700.symbolic_name" value="J4_PIN9"/>
<symbolicName propertyId="p701.symbolic_name" value="J4_PIN7"/>
<symbolicName propertyId="p702.symbolic_name" value="J4_PIN5"/>
<symbolicName propertyId="p703.symbolic_name" value="J4_PIN3"/>
<symbolicName propertyId="p704.symbolic_name" value="J4_PIN1"/>
<symbolicName propertyId="p705.symbolic_name" value="J2_PIN39"/>
<symbolicName propertyId="p708.symbolic_name" value="J2_PIN7"/>
<symbolicName propertyId="p709.symbolic_name" value="J2_PIN11"/>
<symbolicName propertyId="p710.symbolic_name" value="J2_PIN13"/>
<symbolicName propertyId="p711.symbolic_name" value="J2_PIN15"/>
<symbolicName propertyId="p712.symbolic_name" value="ARDUINO_GPIO_PWM"/>
<symbolicName propertyId="p713.symbolic_name" value="ARDUINO_GPIO"/>
<pincfg active="true" name="RA6M4 CPK" selected="true" symbol="g_bsp_pin_cfg">
<configSetting altId="adc0.an03.p003" configurationId="adc0.an03"/>
<configSetting altId="adc0.an04.p004" configurationId="adc0.an04"/>
<configSetting altId="adc0.an05.p005" configurationId="adc0.an05"/>
<configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
<configSetting altId="adc1.an00.p000" configurationId="adc1.an00"/>
<configSetting altId="adc1.an01.p001" configurationId="adc1.an01"/>
<configSetting altId="adc1.an02.p002" configurationId="adc1.an02"/>
<configSetting altId="adc1.mode.custom" configurationId="adc1.mode"/>
<configSetting altId="cgc0.extal.p212" configurationId="cgc0.extal"/>
<configSetting altId="cgc0.mode.mainsub" configurationId="cgc0.mode"/>
<configSetting altId="cgc0.xtal.p213" configurationId="cgc0.xtal"/>
<configSetting altId="dac0.da.p014" configurationId="dac0.da"/>
<configSetting altId="dac0.mode.enabled" configurationId="dac0.mode"/>
<configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
<configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
<configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
<configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
<configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
<configSetting altId="iic1.mode.enabled.a" configurationId="iic1.mode"/>
<configSetting altId="iic1.scl.p512" configurationId="iic1.scl"/>
<configSetting altId="iic1.sda.p511" configurationId="iic1.sda"/>
<configSetting altId="irq0.irq00.p105" configurationId="irq0.irq00"/>
<configSetting altId="irq0.irq11.p006" configurationId="irq0.irq11"/>
<configSetting altId="irq0.irq14.p505" configurationId="irq0.irq14"/>
<configSetting altId="irq0.irq15.p506" configurationId="irq0.irq15"/>
<configSetting altId="irq0.mode.enabled" configurationId="irq0.mode"/>
<configSetting altId="p000.asel" configurationId="p000"/>
<configSetting altId="p000.gpio_mode.gpio_mode_an" configurationId="p000.gpio_mode"/>
<configSetting altId="p001.asel" configurationId="p001"/>
<configSetting altId="p001.gpio_mode.gpio_mode_an" configurationId="p001.gpio_mode"/>
<configSetting altId="p002.asel" configurationId="p002"/>
<configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/>
<configSetting altId="p003.asel" configurationId="p003"/>
<configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
<configSetting altId="p004.asel" configurationId="p004"/>
<configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
<configSetting altId="p005.asel" configurationId="p005"/>
<configSetting altId="p005.gpio_mode.gpio_mode_an" configurationId="p005.gpio_mode"/>
<configSetting altId="p006.irq0.irq11" configurationId="p006"/>
<configSetting altId="p006.gpio_irq.gpio_irq_enabled" configurationId="p006.gpio_irq"/>
<configSetting altId="p006.gpio_mode.gpio_mode_irq" configurationId="p006.gpio_mode"/>
<configSetting altId="p006.gpio_pupd.gpio_pupd_ip_up" configurationId="p006.gpio_pupd"/>
<configSetting altId="p008.output.low" configurationId="p008"/>
<configSetting altId="p008.gpio_mode.gpio_mode_out.low" configurationId="p008.gpio_mode"/>
<configSetting altId="p014.asel" configurationId="p014"/>
<configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/>
<configSetting altId="p015.output.low" configurationId="p015"/>
<configSetting altId="p015.gpio_mode.gpio_mode_out.low" configurationId="p015.gpio_mode"/>
<configSetting altId="p105.irq0.irq00" configurationId="p105"/>
<configSetting altId="p105.gpio_irq.gpio_irq_enabled" configurationId="p105.gpio_irq"/>
<configSetting altId="p105.gpio_mode.gpio_mode_irq" configurationId="p105.gpio_mode"/>
<configSetting altId="p106.output.low" configurationId="p106"/>
<configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/>
<configSetting altId="p108.debug0.tms" configurationId="p108"/>
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
<configSetting altId="p109.debug0.tdo" configurationId="p109"/>
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
<configSetting altId="p110.debug0.tdi" configurationId="p110"/>
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
<configSetting altId="p202.spi0.miso" configurationId="p202"/>
<configSetting altId="p202.gpio_mode.gpio_mode_peripheral" configurationId="p202.gpio_mode"/>
<configSetting altId="p203.spi0.mosi" configurationId="p203"/>
<configSetting altId="p203.gpio_mode.gpio_mode_peripheral" configurationId="p203.gpio_mode"/>
<configSetting altId="p204.spi0.rspck" configurationId="p204"/>
<configSetting altId="p204.gpio_mode.gpio_mode_peripheral" configurationId="p204.gpio_mode"/>
<configSetting altId="p205.spi0.ssl0" configurationId="p205"/>
<configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/>
<configSetting altId="p212.cgc0.extal" configurationId="p212"/>
<configSetting altId="p212.gpio_mode.gpio_mode_peripheral" configurationId="p212.gpio_mode"/>
<configSetting altId="p213.cgc0.xtal" configurationId="p213"/>
<configSetting altId="p213.gpio_mode.gpio_mode_peripheral" configurationId="p213.gpio_mode"/>
<configSetting altId="p300.debug0.tck" configurationId="p300"/>
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
<configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
<configSetting altId="p410.spi1.miso" configurationId="p410"/>
<configSetting altId="p410.gpio_mode.gpio_mode_peripheral" configurationId="p410.gpio_mode"/>
<configSetting altId="p411.spi1.mosi" configurationId="p411"/>
<configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
<configSetting altId="p412.spi1.rspck" configurationId="p412"/>
<configSetting altId="p412.gpio_mode.gpio_mode_peripheral" configurationId="p412.gpio_mode"/>
<configSetting altId="p413.spi1.ssl0" configurationId="p413"/>
<configSetting altId="p413.gpio_mode.gpio_mode_peripheral" configurationId="p413.gpio_mode"/>
<configSetting altId="p414.output.low" configurationId="p414"/>
<configSetting altId="p414.gpio_mode.gpio_mode_out.low" configurationId="p414.gpio_mode"/>
<configSetting altId="p415.output.low" configurationId="p415"/>
<configSetting altId="p415.gpio_mode.gpio_mode_out.low" configurationId="p415.gpio_mode"/>
<configSetting altId="p500.usbfs0.vbusen" configurationId="p500"/>
<configSetting altId="p500.gpio_mode.gpio_mode_peripheral" configurationId="p500.gpio_mode"/>
<configSetting altId="p501.usbfs0.ovrcura" configurationId="p501"/>
<configSetting altId="p501.gpio_mode.gpio_mode_peripheral" configurationId="p501.gpio_mode"/>
<configSetting altId="p503.output.low" configurationId="p503"/>
<configSetting altId="p503.gpio_mode.gpio_mode_out.low" configurationId="p503.gpio_mode"/>
<configSetting altId="p504.output.low" configurationId="p504"/>
<configSetting altId="p504.gpio_mode.gpio_mode_out.low" configurationId="p504.gpio_mode"/>
<configSetting altId="p505.irq0.irq14" configurationId="p505"/>
<configSetting altId="p505.gpio_irq.gpio_irq_enabled" configurationId="p505.gpio_irq"/>
<configSetting altId="p505.gpio_mode.gpio_mode_irq" configurationId="p505.gpio_mode"/>
<configSetting altId="p506.irq0.irq15" configurationId="p506"/>
<configSetting altId="p506.gpio_irq.gpio_irq_enabled" configurationId="p506.gpio_irq"/>
<configSetting altId="p506.gpio_mode.gpio_mode_irq" configurationId="p506.gpio_mode"/>
<configSetting altId="p506.gpio_pupd.gpio_pupd_ip_up" configurationId="p506.gpio_pupd"/>
<configSetting altId="p511.iic1.sda" configurationId="p511"/>
<configSetting altId="p511.gpio_speed.gpio_speed_medium" configurationId="p511.gpio_drivecapacity"/>
<configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/>
<configSetting altId="p512.iic1.scl" configurationId="p512"/>
<configSetting altId="p512.gpio_speed.gpio_speed_medium" configurationId="p512.gpio_drivecapacity"/>
<configSetting altId="p512.gpio_mode.gpio_mode_peripheral" configurationId="p512.gpio_mode"/>
<configSetting altId="p611.output.low" configurationId="p611"/>
<configSetting altId="p611.gpio_mode.gpio_mode_out.low" configurationId="p611.gpio_mode"/>
<configSetting altId="p613.sci7.txd" configurationId="p613"/>
<configSetting altId="p613.gpio_mode.gpio_mode_peripheral" configurationId="p613.gpio_mode"/>
<configSetting altId="p614.sci7.rxd" configurationId="p614"/>
<configSetting altId="p614.gpio_mode.gpio_mode_peripheral" configurationId="p614.gpio_mode"/>
<configSetting altId="p712.output.low" configurationId="p712"/>
<configSetting altId="p712.gpio_mode.gpio_mode_out.low" configurationId="p712.gpio_mode"/>
<configSetting altId="p713.output.low" configurationId="p713"/>
<configSetting altId="p713.gpio_mode.gpio_mode_out.low" configurationId="p713.gpio_mode"/>
<configSetting altId="sci7.mode.asynchronous.c" configurationId="sci7.mode"/>
<configSetting altId="sci7.pairing.c" configurationId="sci7.pairing"/>
<configSetting altId="sci7.rxd.p614" configurationId="sci7.rxd"/>
<configSetting altId="sci7.txd.p613" configurationId="sci7.txd"/>
<configSetting altId="spi0.miso.p202" configurationId="spi0.miso"/>
<configSetting altId="spi0.mode.enabled.free" configurationId="spi0.mode"/>
<configSetting altId="spi0.mosi.p203" configurationId="spi0.mosi"/>
<configSetting altId="spi0.pairing.free" configurationId="spi0.pairing"/>
<configSetting altId="spi0.rspck.p204" configurationId="spi0.rspck"/>
<configSetting altId="spi0.ssl0.p205" configurationId="spi0.ssl0"/>
<configSetting altId="spi1.miso.p410" configurationId="spi1.miso"/>
<configSetting altId="spi1.mode.enabled.b" configurationId="spi1.mode"/>
<configSetting altId="spi1.mosi.p411" configurationId="spi1.mosi"/>
<configSetting altId="spi1.pairing.b" configurationId="spi1.pairing"/>
<configSetting altId="spi1.rspck.p412" configurationId="spi1.rspck"/>
<configSetting altId="spi1.ssl0.p413" configurationId="spi1.ssl0"/>
<configSetting altId="usbfs0.mode.custom" configurationId="usbfs0.mode"/>
<configSetting altId="usbfs0.ovrcura.p501" configurationId="usbfs0.ovrcura"/>
<configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
<configSetting altId="usbfs0.vbusen.p500" configurationId="usbfs0.vbusen"/>
</pincfg>
<pincfg active="false" name="R7FA6M4AF3CFB.pincfg" selected="false" symbol="">
<configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
<configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
<configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
<configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
<configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
<configSetting altId="p108.debug0.tms" configurationId="p108"/>
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
<configSetting altId="p109.debug0.tdo" configurationId="p109"/>
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
<configSetting altId="p110.debug0.tdi" configurationId="p110"/>
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
<configSetting altId="p300.debug0.tck" configurationId="p300"/>
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>

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## 在 MDK 中使用 FSP
- 添加RA Smart Config
1. 打开 MDK，选择 “Tools -> Customize Tools Menu…”
2. 点击 “new” 图标，添加一条自定义命令: RA Smart Configurator
3. Command 输入工具的安装路径， 点击“…”找到安装路径下的“rasc.exe”文件并选中 (setup_fsp_v3_1_0_rasc_ 安装目录下)
4. Initial Folder 输入参数: $P
5. Arguments 输入参数: --device $D --compiler ARMv6 configuration.xml
6. 点击 OK 保存命令“Tools -> RA smart Configurator”
![img](picture/customize.png)
7. 点击添加的命令打开配置工具：RA Smart Config
![image.png](picture/openrasc.png)
- 添加 Device Partition Manager，添加步骤同上。
1. 输入命令名称: `Device Partition Manager`
2. Command: 在安装路径选中 `rasc.exe`
3. Initial Folder : `$P`
4. Arguments: `-application com.renesas.cdt.ddsc.dpm.ui.dpmapplication configuration.xml "SL%L"`
> PS：以上相关操作也可以在 FSP 的说明文档中找到。
>
> 文档路径（本地）：在 FSP 的安装目录下 .\fsp_documentation\v3.1.0\fsp_user_manual_v3.1.0\index.html
>
> 文档路径（官网）：https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document
## 更新工程配置
使用 FSP 配置完成后如果有新的文件添加进工程中，不会马上添加进去。需要先编译一次，如果弹出如下提醒，选择 “是” 然后再次编译即可。
![img](picture/import_changes.png)
## UART
如何添加一个 UART 端口外设配置？
1. 选择 Stacks 配置页，点击 New Stack 找到 UART。
![image.png](picture/rascuart.png)
2. 配置 UART 参数，因为需要适配 RT-Thread 驱动中使用的命名，所以需要修改命名，设置**name** 、**channel** 、**callback** 是一致的标号。![image.png](picture/rascuart1.png)
## GPIO 中断
如何添加一个 IO 中断？
1. 选择引脚编号，进入配置，比如选择 P105 做为中断引脚。可先找到引脚查看可配置成的 IRQx 通道号。
![image-20211103200949759](picture/p105.png)
2. 打开 ICU 中断通道 IRQ00
![image-20211103200813467](picture/irq0.png)
3. 创建 stack 并进入配置。因为需要适配 RT-Thread 驱动中使用的命名，所以需要修改命名，设置**name** 、**channel** 、**callback** 是一致的标号。选择你希望的触发方式，最后保存配置，生成配置代码。
![](picture/1635929089445.png)
![image-20211103201047103](picture/irq1.png)
4. 测试中断是否成功开启
```c
#define IRQ_TEST_PIN "p105"
void irq_callback_test(void *args)
{
rt_kprintf("\n IRQ00 triggered \n");
}
void icu_sample(void)
{
/* init */
rt_uint32_t pin = rt_pin_get(IRQ_TEST_PIN);
rt_kprintf("\n pin number : 0x%04X \n", pin);
rt_err_t err = rt_pin_attach_irq(pin, PIN_IRQ_MODE_RISING, irq_callback_test, RT_NULL);
if(RT_EOK != err)
{
rt_kprintf("\n attach irq failed. \n");
}
err = rt_pin_irq_enable(pin, PIN_IRQ_ENABLE);
if(RT_EOK != err)
{
rt_kprintf("\n enable irq failed. \n");
}
}
MSH_CMD_EXPORT(icu_sample, icu sample);
```
## WDT
1. 创建 WDT
![image-20211019152302939](picture/wdt.png)
2. 配置 WDT，需要注意在 RT-Thread 中只使用了一个 WDT 设备，所以没有对其进行编号，如果是新创建的 WDT 设备需要注意 name 字段，在驱动中默认使用的是`g_wdt` 。
![image-20211019152407572](picture/wdt_config.png)
3. 如何在 ENV 中打开 WDT 以及[WDT 接口使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog)
![image-20211027183406251](picture/wdt_env.png)
## RTC
1. 添加 RTC 设备
![image-20211019152536749](picture/rtc.png)
2. 配置 RTC，需要注意在 RT-Thread 中只是用了一个 RTC 设备，所以没有对其进行编号，如果是新创建的 RTC 设备需要注意 name 字段，在驱动中默认使用的是`g_rtc` 。修改 Callback 为 rtc_callback
![image-20211019152627412](picture/rtc_config.png)
3. 如何在 ENV 中打开 RTC 以及[ RTC 接口使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc)
![image-20211027181550233](picture/rtc_env.png)
## Flash
1. 创建 Flash
![image-20211026105031200](picture/add_flash.png)
2. 配置 Flash，需要注意在 RT-Thread 中只使用了一个 flash 设备，所以没有对其进行编号，如果是新创建的 flash 设备需要注意 name 字段，在驱动中默认使用的是`g_flash` 。
![image-20211026105628706](picture/config_flash.png)
3. 如何在 ENV 中打开 Flash
![image-20211026123252310](picture/flash_menuconfig.png)
## SPI
1. 添加一个 SPI 外设端口
![image-20211027180820968](picture/spi_add.png)
2. 配置 channel、name、Clock Phase、Clock Polarity、Callback、 SPI Mode 等参数，波特率在代码中可通过 API 修改，这里可以设置一个默认值。
![img](picture/spi.png)
3. 如何在 ENV 中打开 SPI 以及 [SPI 接口使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi)
![image-20211027181444023](picture/spi_env.png)
## ADC/DAC
创建 ADC/DAC
![img](picture/adc_dac.png)
- **ADC**
1. 配置 name、unit、mode，选择扫描的通道编号
![img](picture/adc_config.png)
2. 配置扫描通道对应的引脚
![img](picture/adc_config1.png)
3. 在 menuconfig 中打开对应的通道
- **DAC**
1. 需要先关闭 P014 的默认 mode
![img](picture/dac_config0.png)
2. 开启 DAC0 通道
![img](picture/dac_config1.png)
3. 修改通道号为 0，与 DAC0 对应
![img](picture/dac_config2.png)
4. 在 menuconfig 中打开对应的通道
## 通用 PWM 定时器（GPT）
GPT 定时器在该芯片中可作为通用定时器，也可以用于产生 PWM 信号。在将其用于产生 PWM 信号时，GPT 定时器提供了 gpt0 - gpt9 总共 10 个通道，每个通道可以设定两个输出端口。当前版本的 PWM 驱动将每个通道都看做一个单独的 PWM 设备，每个设备都只有一个通道。用户可以选择开启一个通道的任意一个输出端口，或将两个端口均开启，但在同时开启两个端口的情况下，它们输出的波形将完全一致。
1. 添加 GPT 设备
![img](./picture/add_gpt1.png)
2. 配置通道
![img](./picture/add_gpt2.png)
对 GPT 较为关键的配置如图所示，具体解释如下：
1. 将``Common`` ->``Pin Output Support`` 设置为 Enable ，以开启 PWM 波形的输出。
2. 指定 GPT 通道，并根据通道数指定 GPT 的名称，例如此处指定 GPT 通道 3 ，所以 GPT 的名称必须为``g_timer3``。并且将定时器模式设置为 PWM ，并指定每个 PWM 周期的计数值。
3. 设定 PWM 通道默认输出的占空比，这里为 50% 。
4. 设定 GPT 通道下两个输出端口的使能状态。
5. 此处设置 GPT 通道下两个输出端口各自对应的引脚。
3. 配置输出引脚
![img](./picture/add_gpt3.png)
在完成上一步对 GPT 定时器的设置后，根据图示找到对应 GPT 通道输出引脚设置的界面（这里是 GPT3），将图中标号 **1** 处设置为 ``GTIOCA or GTIOCB`` ，并根据需要在图中标号 **2** 处设置 GPT 通道下两个输出端口各自对应的输出引脚。
4. 在 menuconfig 中打开对应的通道，[RT-Thread 的 pwm 框架介绍](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm)
![image-20211103202216381](picture/pwm_env.png)

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menu "Hardware Drivers Config"
config SOC_SERIES_R7FA6M4AF
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
config BSP_USING_ONCHIP_FLASH
bool "Enable Onchip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
if BSP_USING_UART
menuconfig BSP_USING_UART7
bool "Enable UART7 (Console)"
default y
if BSP_USING_UART7
config BSP_UART7_RX_USING_DMA
bool "Enable UART7 RX DMA"
depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
default n
config BSP_UART7_TX_USING_DMA
bool "Enable UART7 TX DMA"
depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
default n
config BSP_UART7_RX_BUFSIZE
int "Set UART7 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART7_TX_BUFSIZE
int "Set UART7 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default y
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 0x0000 0x0B0F
default 0x0512
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0x0000 0x0B0F
default 0x0511
endif
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_ONCHIP_RTC
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_SPI_USING_DTC_DMA
bool "Enable SPI DTC transfers data without using the CPU."
default n
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "Enable ADC0"
default n
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_DAC
bool "Enable DAC"
default n
select RT_USING_DAC
if BSP_USING_DAC
config BSP_USING_DAC0
bool "Enable DAC0"
default n
config BSP_USING_DAC1
bool "Enable DAC1"
default n
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
config BSP_USING_PWM0
bool "Enable GPT0 (32-Bits) output PWM"
default n
config BSP_USING_PWM1
bool "Enable GPT1 (32-Bits) output PWM"
default n
config BSP_USING_PWM2
bool "Enable GPT2 (32-Bits) output PWM"
default n
config BSP_USING_PWM3
bool "Enable GPT3 (32-Bits) output PWM"
default n
config BSP_USING_PWM4
bool "Enable GPT4 (16-Bits) output PWM"
default n
config BSP_USING_PWM5
bool "Enable GPT5 (16-Bits) output PWM"
default n
config BSP_USING_PWM6
bool "Enable GPT6 (16-Bits) output PWM"
default n
config BSP_USING_PWM7
bool "Enable GPT7 (16-Bits) output PWM"
default n
config BSP_USING_PWM8
bool "Enable GPT8 (16-Bits) output PWM"
default n
config BSP_USING_PWM9
bool "Enable GPT9 (16-Bits) output PWM"
default n
endif
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
drv_common.c
""")
if GetDepend(['BSP_USING_UART']):
if GetDepend(['RT_USING_SERIAL_V2']):
src += ['drv_usart_v2.c']
else:
print("\nThe current project does not support serial-v1\n")
Return('group')
if GetDepend(['BSP_USING_GPIO']):
src += ['drv_gpio.c']
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['BSP_USING_ONCHIP_RTC']):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_I2C', 'RT_USING_I2C_BITOPS']):
if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
src += ['drv_soft_i2c.c']
if GetDepend(['BSP_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['BSP_USING_ADC']):
src += ['drv_adc.c']
if GetDepend(['BSP_USING_DAC']):
src += ['drv_dac.c']
if GetDepend(['BSP_USING_ONCHIP_FLASH']):
src += ['drv_flash.c']
if GetDepend(['BSP_USING_PWM']):
src += ['drv_pwm.c']
path = [cwd]
path += [cwd + '/config']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

38
bsp/ra6m4-cpk/drivers/board.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-10 Sherman first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RA_SRAM_SIZE 256
#define RA_SRAM_END (0x20000000 + RA_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RAM_END$$ZI$$Base;
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END RA_SRAM_END
#ifdef __cplusplus
}
#endif
#endif

42
bsp/ra6m4-cpk/drivers/config/drv_config.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#ifndef __DRV_CONFIG_H__
#define __DRV_CONFIG_H__
#include "board.h"
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef SOC_SERIES_R7FA6M4AF
#include "ra6m4/uart_config.h"
#ifdef BSP_USING_ADC
#include "ra6m4/adc_config.h"
#endif
#ifdef BSP_USING_DAC
#include "ra6m4/dac_config.h"
#endif
#ifdef BSP_USING_PWM
#include "ra6m4/pwm_config.h"
#endif
#endif/* SOC_SERIES_R7FA6M4AF */
#ifdef __cplusplus
}
#endif
#endif/* __DRV_CONFIG_H__ */

41
bsp/ra6m4-cpk/drivers/config/ra6m4/adc_config.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
struct ra_adc_map
{
char name;
const adc_cfg_t *g_cfg;
const adc_instance_ctrl_t *g_ctrl;
const adc_channel_cfg_t *g_channel_cfg;
};
struct ra_dev
{
rt_adc_device_t ra_adc_device_t;
struct ra_adc_map *ra_adc_dev;
};
#endif
#endif
#ifdef __cplusplus
}
#endif

41
bsp/ra6m4-cpk/drivers/config/ra6m4/dac_config.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/
#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_DAC
struct ra_dac_map
{
char name;
const struct st_dac_cfg *g_cfg;
const struct st_dac_instance_ctrl *g_ctrl;
};
struct ra_dac_dev
{
rt_dac_device_t ra_dac_device_t;
struct ra_dac_map *ra_dac_map_dev;
};
#endif
#endif
#ifdef __cplusplus
}
#endif

68
bsp/ra6m4-cpk/drivers/config/ra6m4/pwm_config.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-26 KevinXu first version
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__
#include <rtthread.h>
#include <drv_config.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
enum
{
#ifdef BSP_USING_PWM0
BSP_PWM0_INDEX,
#endif
#ifdef BSP_USING_PWM1
BSP_PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
BSP_PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
BSP_PWM3_INDEX,
#endif
#ifdef BSP_USING_PWM4
BSP_PWM4_INDEX,
#endif
#ifdef BSP_USING_PWM5
BSP_PWM5_INDEX,
#endif
#ifdef BSP_USING_PWM6
BSP_PWM6_INDEX,
#endif
#ifdef BSP_USING_PWM7
BSP_PWM7_INDEX,
#endif
#ifdef BSP_USING_PWM8
BSP_PWM8_INDEX,
#endif
#ifdef BSP_USING_PWM9
BSP_PWM9_INDEX,
#endif
BSP_PWMS_NUM
};
#define PWM_DRV_INITIALIZER(num) \
{ \
.name = "pwm"#num , \
.g_cfg = &g_timer##num##_cfg, \
.g_ctrl = &g_timer##num##_ctrl, \
.g_timer = &g_timer##num, \
}
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */

36
bsp/ra6m4-cpk/drivers/config/ra6m4/uart_config.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.p_api_ctrl = &g_uart7_ctrl, \
.p_cfg = &g_uart7_cfg, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#ifdef __cplusplus
}
#endif
#endif

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bsp/ra6m4-cpk/drivers/drv_adc.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/
#include "drv_config.h"
#ifdef RT_USING_ADC
// #define DRV_DEBUG
#define DBG_TAG "drv.adc"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
struct ra_adc_map ra_adc[] =
{
#if defined(BSP_USING_ADC0)
{'0', &g_adc0_cfg, &g_adc0_ctrl, &g_adc0_channel_cfg},
#endif
#if defined(BSP_USING_ADC1)
{'1', &g_adc1_cfg, &g_adc1_ctrl, &g_adc1_channel_cfg},
#endif
};
#if defined(BSP_USING_ADC0)
struct rt_adc_device adc0_device;
struct ra_dev _ra_adc0_device = {.ra_adc_device_t = &adc0_device, .ra_adc_dev = &ra_adc[0]};
#endif
#if defined(BSP_USING_ADC1)
struct rt_adc_device adc1_device;
struct ra_dev _ra_adc1_device = {.ra_adc_device_t = &adc1_device, .ra_adc_dev = &ra_adc[1]};
#endif
static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
RT_ASSERT(device != RT_NULL);
struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
/**< start adc*/
if (enabled)
{
if (FSP_SUCCESS != R_ADC_ScanStart((adc_ctrl_t *)adc->g_ctrl))
{
LOG_E("start adc%c failed.", adc->name);
return -RT_ERROR;
}
}
else
{
/**< stop adc*/
if (FSP_SUCCESS != R_ADC_ScanStop((adc_ctrl_t *)adc->g_ctrl))
{
LOG_E("stop adc%c failed.", adc->name);
return -RT_ERROR;
}
}
return RT_EOK;
}
rt_err_t ra_adc_close(struct rt_adc_device *device)
{
RT_ASSERT(device != RT_NULL);
struct ra_adc_map *adc = (struct ra_adc_map *)(struct ra_adc_map *)device->parent.user_data;
if (FSP_SUCCESS != R_ADC_Close((adc_ctrl_t *)adc->g_ctrl))
{
LOG_E("close adc%c failed.", adc->name);
return -RT_ERROR;
}
return RT_EOK;
}
static rt_err_t ra_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
RT_ASSERT(device != RT_NULL);
struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
if (RT_EOK != R_ADC_Read32((adc_ctrl_t *)adc->g_ctrl, channel, value))
{
LOG_E("get adc value failed.\n");
return -RT_ERROR;
}
return RT_EOK;
}
static const struct rt_adc_ops ra_adc_ops =
{
.enabled = ra_adc_enabled,
.convert = ra_get_adc_value,
};
static int ra_adc_init(void)
{
#if defined(BSP_USING_ADC0)
R_ADC_Open((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl,
(adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_cfg);
R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl,
(adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_channel_cfg);
if (RT_EOK != rt_hw_adc_register(_ra_adc0_device.ra_adc_device_t, "adc0", &ra_adc_ops, (void *)_ra_adc0_device.ra_adc_dev))
{
LOG_E("adc0 register failed");
return -RT_ERROR;
}
#endif
#if defined(BSP_USING_ADC1)
R_ADC_Open((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl,
(adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_cfg);
R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl,
(adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_channel_cfg);
if (RT_EOK != rt_hw_adc_register(_ra_adc1_device.ra_adc_device_t, "adc1", &ra_adc_ops, (void *)_ra_adc1_device.ra_adc_dev))
{
LOG_E("adc1 register failed");
return -RT_ERROR;
}
#endif
return RT_EOK;
}
INIT_BOARD_EXPORT(ra_adc_init);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-7 SummerGift first version
*/
#include <drv_common.h>
#include <bsp_api.h>
#include "board.h"
#ifdef RT_USING_PIN
#include <drv_gpio.h>
#endif
#ifdef RT_USING_SERIAL
#ifdef RT_USING_SERIAL_V2
#include <drv_usart_v2.h>
#else
#include <drv_usart.h>
#endif
#endif
#ifdef RT_USING_FINSH
#include <finsh.h>
static void reboot(uint8_t argc, char **argv)
{
rt_hw_cpu_reset();
}
MSH_CMD_EXPORT(reboot, Reboot System);
#endif /* RT_USING_FINSH */
/* SysTick configuration */
void rt_hw_systick_init(void)
{
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
NVIC_SetPriority(SysTick_IRQn, 0xFF);
}
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* @brief This function is executed in case of error occurrence.
* @param None
* @retval None
*/
void _Error_Handler(char *s, int num)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while (1)
{
}
/* USER CODE END Error_Handler */
}
/**
* This function will delay for some us.
*
* @param us the delay time of us
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
/**
* This function will initial STM32 board.
*/
RT_WEAK void rt_hw_board_init()
{
rt_hw_systick_init();
/* Heap initialization */
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
/* Pin driver initialization is open by default */
#ifdef RT_USING_PIN
rt_hw_pin_init();
#endif
/* USART driver initialization is open by default */
#ifdef RT_USING_SERIAL
rt_hw_usart_init();
#endif
/* Set the shell console output device */
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* Board underlying hardware initialization */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-7 SummerGift first version
*/
#ifndef __DRV_COMMON_H__
#define __DRV_COMMON_H__
#include <rtthread.h>
#include <rthw.h>
#ifdef RT_USING_DEVICE
#include <rtdevice.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
void _Error_Handler(char *s, int num);
#ifndef Error_Handler
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
#endif
#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/
#include <rtthread.h>
#include "drv_config.h"
#ifdef RT_USING_DAC
//#define DRV_DEBUG
#define DBG_TAG "drv.dac"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
struct ra_dac_map ra_dac[] =
{
#ifdef BSP_USING_DAC0
{'0', &g_dac0_cfg, &g_dac0_ctrl},
#endif
#ifdef BSP_USING_DAC1
{'1', &g_dac1_cfg, &g_dac1_ctrl},
#endif
};
#ifdef BSP_USING_DAC0
struct rt_dac_device dac0_device;
struct ra_dac_dev _ra_dac0_device = {.ra_dac_device_t = &dac0_device, .ra_dac_map_dev = &ra_dac[0]};
#endif
#ifdef BSP_USING_DAC1
struct rt_dac_device dac1_device;
struct ra_dac_dev _ra_dac1_device = {.ra_dac_device_t = &dac1_device, .ra_dac_map_dev = &ra_dac[1]};
#endif
rt_err_t ra_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
{
RT_ASSERT(device != RT_NULL);
struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
if (FSP_SUCCESS != R_DAC_Stop((dac_ctrl_t *)dac->g_ctrl))
{
LOG_E("dac%c stop failed.", dac->name);
return -RT_ERROR;
}
return RT_EOK;
}
rt_err_t ra_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
{
RT_ASSERT(device != RT_NULL);
struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
if (FSP_SUCCESS != R_DAC_Start((dac_ctrl_t *)dac->g_ctrl))
{
LOG_E("dac%c start failed.", dac->name);
return -RT_ERROR;
}
return RT_EOK;
}
rt_err_t ra_dac_write(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
RT_ASSERT(device != RT_NULL);
struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
if (FSP_SUCCESS != R_DAC_Write((dac_ctrl_t *)dac->g_ctrl, *value))
{
LOG_E("dac%c set value failed.", dac->name);
return -RT_ERROR;
}
return RT_EOK;
}
struct rt_dac_ops ra_dac_ops =
{
.disabled = ra_dac_disabled,
.enabled = ra_dac_enabled,
.convert = ra_dac_write,
};
static int ra_dac_init(void)
{
#ifdef BSP_USING_DAC0
_ra_dac0_device.ra_dac_device_t->ops = &ra_dac_ops;
R_DAC_Open((dac_ctrl_t *)_ra_dac0_device.ra_dac_map_dev->g_ctrl, (dac_cfg_t const *)_ra_dac0_device.ra_dac_map_dev->g_cfg);
if (FSP_SUCCESS != rt_hw_dac_register(_ra_dac0_device.ra_dac_device_t, "dac0", &ra_dac_ops, (void *)_ra_dac0_device.ra_dac_map_dev))
{
LOG_E("dac0 register failed");
return -RT_ERROR;
}
#endif
#ifdef BSP_USING_DAC1
_ra_dac1_device.ra_dac_device_t->ops = &ra_dac_ops;
R_DAC_Open((dac_ctrl_t *)_ra_dac1_device.ra_dac_map_dev->g_ctrl, (dac_cfg_t const *) _ra_dac1_device.ra_dac_map_dev->g_cfg);
if (FSP_SUCCESS != rt_hw_dac_register(_ra_dac1_device.ra_dac_device_t, "dac1", &ra_dac_ops, (void *)_ra_dac1_device.ra_dac_map_dev))
{
LOG_E("dac1 register failed");
return -RT_ERROR;
}
#endif
return RT_EOK;
}
INIT_DEVICE_EXPORT(ra_dac_init);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "board.h"
#include "hal_data.h"
#include "drv_flash.h"
#include <rtthread.h>
#if defined(PKG_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
int _flash_init(void)
{
fsp_err_t err = FSP_SUCCESS;
/* Open Flash_HP */
err = R_FLASH_HP_Open(&g_flash_ctrl, &g_flash_cfg);
/* Handle Error */
if (FSP_SUCCESS != err)
{
LOG_E("\r\n Flah_HP_Open API failed");
}
/* Setup Default Block 0 as Startup Setup Block */
err = R_FLASH_HP_StartUpAreaSelect(&g_flash_ctrl, FLASH_STARTUP_AREA_BLOCK0, true);
if (err != FSP_SUCCESS)
{
LOG_E("\r\n Flah_HP_StartUpAreaSelect API failed");
}
return 0;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int _flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size) > FLASH_HP_CF_BLCOK_10 + BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -1;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int _flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_base_t level;
fsp_err_t err = FSP_SUCCESS;
size_t written_size = 0;
if ((addr + size) > FLASH_HP_CF_BLCOK_10 + BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
{
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
if (size % BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE)
{
LOG_E("Flash Write size must be an integer multiple of %d", BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
return -RT_EINVAL;
}
while (written_size < size)
{
level = rt_hw_interrupt_disable();
/* Write code flash data*/
err = R_FLASH_HP_Write(&g_flash_ctrl, (uint32_t)(buf + written_size), addr + written_size, BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
rt_hw_interrupt_enable(level);
/* Error Handle */
if (FSP_SUCCESS != err)
{
LOG_E("Write API failed");
return -RT_EIO;
}
written_size += BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE;
}
if (result != RT_EOK)
{
return result;
}
return size;
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int _flash_erase_8k(rt_uint32_t addr, size_t size)
{
fsp_err_t err = FSP_SUCCESS;
rt_base_t level;
if ((addr + size) > BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE)
{
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
if (size < 1)
{
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
/* Erase Block */
err = R_FLASH_HP_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, FLASH_HP_CF_BLOCK_SIZE_8KB), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE + 1);
rt_hw_interrupt_enable(level);
if (err != FSP_SUCCESS)
{
LOG_E("Erase API failed");
return -RT_EIO;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
return size;
}
int _flash_erase_128k(rt_uint32_t addr, size_t size)
{
fsp_err_t err = FSP_SUCCESS;
rt_base_t level;
if ((addr + size) > FLASH_HP_CF_BLCOK_10 + BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
{
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
if (size < 1)
{
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
/* Erase Block */
err = R_FLASH_HP_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, FLASH_HP_CF_BLOCK_SIZE_32KB), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE + 1);
rt_hw_interrupt_enable(level);
if (err != FSP_SUCCESS)
{
LOG_E("Erase API failed");
return -RT_EIO;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
return size;
}
#if defined(PKG_USING_FAL)
static int fal_flash_read_8k(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write_8k(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase_8k(long offset, size_t size);
static int fal_flash_erase_128k(long offset, size_t size);
const struct fal_flash_dev _onchip_flash_8k = { "onchip_flash_8k", FLASH_HP_CF_BLCOK_0, FLASH_HP_CF_BLOCK_8, (8 * 1024), {_flash_init, fal_flash_read_8k, fal_flash_write_8k, fal_flash_erase_8k} };
const struct fal_flash_dev _onchip_flash_128k = { "onchip_flash_128k", FLASH_HP_CF_BLOCK_8, 32 * 3 * 1024, (128 * 1024), {_flash_init, fal_flash_read_128k, fal_flash_write_128k, fal_flash_erase_128k} };
static int fal_flash_read_8k(long offset, rt_uint8_t *buf, size_t size)
{
return _flash_read(_onchip_flash_8k.addr + offset, buf, size);
}
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size)
{
return _flash_read(_onchip_flash_128k.addr + offset, buf, size);
}
static int fal_flash_write_8k(long offset, const rt_uint8_t *buf, size_t size)
{
return _flash_write(_onchip_flash_8k.addr + offset, buf, size);
}
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size)
{
return _flash_write(_onchip_flash_128k.addr + offset, buf, size);
}
static int fal_flash_erase_8k(long offset, size_t size)
{
return _flash_erase_8k(_onchip_flash_8k.addr + offset, size);
}
static int fal_flash_erase_128k(long offset, size_t size)
{
return _flash_erase_128k(_onchip_flash_128k.addr + offset, size);
}
int flash_test(void)
{
#define TEST_OFF 0x10000
const struct fal_partition *param;
uint8_t write_buffer[BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE] = {0};
uint8_t read_buffer[BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE] = {0};
/* Set write buffer, clear read buffer */
for (uint8_t index = 0; index < BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE; index++)
{
write_buffer[index] = index;
read_buffer[index] = 0;
}
fal_init();
param = fal_partition_find("param");
if (param == RT_NULL)
{
LOG_E("not find partition param!");
return -1;
}
LOG_I("Erase Start...");
fal_partition_erase(param, TEST_OFF, BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE);
LOG_I("Erase succeeded!");
LOG_I("Write Start...");
fal_partition_write(param, TEST_OFF, write_buffer, sizeof(write_buffer));
LOG_I("Write succeeded!");
LOG_I("Read Start...");
fal_partition_read(param, TEST_OFF, read_buffer, BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
LOG_I("Read succeeded!");
for (int i = 0; i < BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE; i++)
{
if (read_buffer[i] != write_buffer[i])
{
LOG_E("Data verification failed!");
return -1;
}
}
LOG_I("Data verification succeeded!");
return 0;
}
MSH_CMD_EXPORT(flash_test, "drv flash test.");
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Code Flash */
#define FLASH_HP_CF_BLOCK_SIZE_32KB (32*1024) /* Block Size 32 KB */
#define FLASH_HP_CF_BLOCK_SIZE_8KB (8*1024) /* Block Size 8KB */
#define FLASH_HP_CF_BLCOK_0 0x00000000U /* 8 KB: 0x00000000 - 0x00001FFF */
#define FLASH_HP_CF_BLOCK_1 0x00002000U /* 8 KB: 0x00002000 - 0x00003FFF */
#define FLASH_HP_CF_BLOCK_2 0x00004000U /* 8 KB: 0x00004000 - 0x00005FFF */
#define FLASH_HP_CF_BLOCK_3 0x00006000U /* 8 KB: 0x00006000 - 0x00007FFF */
#define FLASH_HP_CF_BLOCK_4 0x00008000U /* 8 KB: 0x00008000 - 0x00009FFF */
#define FLASH_HP_CF_BLOCK_5 0x0000A000U /* 8 KB: 0x0000A000 - 0x0000BFFF */
#define FLASH_HP_CF_BLOCK_6 0x0000C000U /* 8 KB: 0x0000C000 - 0x0000DFFF */
#define FLASH_HP_CF_BLOCK_7 0x0000E000U /* 8 KB: 0x0000E000 - 0x0000FFFF */
#define FLASH_HP_CF_BLOCK_8 0x00010000U /* 32 KB: 0x00010000 - 0x00017FFF */
#define FLASH_HP_CF_BLOCK_9 0x00018000U /* 32 KB: 0x00018000 - 0x0001FFFF */
#define FLASH_HP_CF_BLCOK_10 0x00020000U /* 32 KB: 0x00020000 - 0x0004FFFF */
#define FLASH_HP_DF_BLOCK_SIZE (64)
/* Data Flash */
#if (defined (BOARD_RA6M4_EK) || defined (BOARD_RA6M5_EK) || defined (BOARD_RA4M3_EK)||defined(BOARD_RA4M2_EK))
#define FLASH_HP_DF_BLOCK_0 0x08000000U /* 64 B: 0x40100000 - 0x4010003F */
#define FLASH_HP_DF_BLOCK_1 0x08000040U /* 64 B: 0x40100040 - 0x4010007F */
#define FLASH_HP_DF_BLOCK_2 0x08000080U /* 64 B: 0x40100080 - 0x401000BF */
#define FLASH_HP_DF_BLOCK_3 0x080000C0U /* 64 B: 0x401000C0 - 0x401000FF */
#else
#define FLASH_HP_DF_BLOCK_0 0x40100000U /* 64 B: 0x40100000 - 0x4010003F */
#define FLASH_HP_DF_BLOCK_1 0x40100040U /* 64 B: 0x40100040 - 0x4010007F */
#define FLASH_HP_DF_BLOCK_2 0x40100080U /* 64 B: 0x40100080 - 0x401000BF */
#define FLASH_HP_DF_BLOCK_3 0x401000C0U /* 64 B: 0x401000C0 - 0x401000FF */
#endif
#define BLOCK_SIZE (128)
#define BLOCK_NUM (2)
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FLASH_H__ */

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#include <drv_gpio.h>
#ifdef RT_USING_PIN
#define DBG_TAG "drv.gpio"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#ifdef R_ICU_H
static rt_base_t ra_pin_get_irqx(rt_uint32_t pin)
{
switch (pin)
{
case BSP_IO_PORT_04_PIN_00:
case BSP_IO_PORT_02_PIN_06:
case BSP_IO_PORT_01_PIN_05:
return 0;
case BSP_IO_PORT_02_PIN_05:
case BSP_IO_PORT_01_PIN_01:
case BSP_IO_PORT_01_PIN_04:
return 1;
case BSP_IO_PORT_02_PIN_03:
case BSP_IO_PORT_01_PIN_00:
case BSP_IO_PORT_02_PIN_13:
return 2;
case BSP_IO_PORT_02_PIN_02:
case BSP_IO_PORT_01_PIN_10:
case BSP_IO_PORT_02_PIN_12:
return 3;
case BSP_IO_PORT_04_PIN_02:
case BSP_IO_PORT_01_PIN_11:
case BSP_IO_PORT_04_PIN_11:
return 4;
case BSP_IO_PORT_04_PIN_01:
case BSP_IO_PORT_03_PIN_02:
case BSP_IO_PORT_04_PIN_10:
return 5;
case BSP_IO_PORT_03_PIN_01:
case BSP_IO_PORT_00_PIN_00:
case BSP_IO_PORT_04_PIN_09:
return 6;
case BSP_IO_PORT_00_PIN_01:
case BSP_IO_PORT_04_PIN_08:
return 7;
case BSP_IO_PORT_00_PIN_02:
case BSP_IO_PORT_03_PIN_05:
case BSP_IO_PORT_04_PIN_15:
return 8;
case BSP_IO_PORT_00_PIN_04:
case BSP_IO_PORT_03_PIN_04:
case BSP_IO_PORT_04_PIN_14:
return 9;
case BSP_IO_PORT_00_PIN_05:
case BSP_IO_PORT_07_PIN_09:
return 10;
case BSP_IO_PORT_05_PIN_01:
case BSP_IO_PORT_00_PIN_06:
case BSP_IO_PORT_07_PIN_08:
return 11;
case BSP_IO_PORT_05_PIN_02:
case BSP_IO_PORT_00_PIN_08:
return 12;
case BSP_IO_PORT_00_PIN_15:
case BSP_IO_PORT_00_PIN_09:
return 13;
case BSP_IO_PORT_04_PIN_03:
case BSP_IO_PORT_05_PIN_12:
case BSP_IO_PORT_05_PIN_05:
return 14;
case BSP_IO_PORT_04_PIN_04:
case BSP_IO_PORT_05_PIN_11:
case BSP_IO_PORT_05_PIN_06:
return 15;
default :
return -1;
}
}
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
#define RA_IRQ_MAX 16
struct ra_pin_irq_map pin_irq_map[RA_IRQ_MAX] = {0};
static void ra_pin_map_init(void)
{
#ifdef VECTOR_NUMBER_ICU_IRQ0
pin_irq_map[0].irq_ctrl = &g_external_irq0_ctrl;
pin_irq_map[0].irq_cfg = &g_external_irq0_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ1
pin_irq_map[1].irq_ctrl = &g_external_irq1_ctrl;
pin_irq_map[1].irq_cfg = &g_external_irq1_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ2
pin_irq_map[2].irq_ctrl = &g_external_irq2_ctrl;
pin_irq_map[2].irq_cfg = &g_external_irq2_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ3
pin_irq_map[3].irq_ctrl = &g_external_irq3_ctrl;
pin_irq_map[3].irq_cfg = &g_external_irq3_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ4
pin_irq_map[4].irq_ctrl = &g_external_irq4_ctrl;
pin_irq_map[4].irq_cfg = &g_external_irq4_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ5
pin_irq_map[5].irq_ctrl = &g_external_irq5_ctrl;
pin_irq_map[5].irq_cfg = &g_external_irq5_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ6
pin_irq_map[6].irq_ctrl = &g_external_irq6_ctrl;
pin_irq_map[6].irq_cfg = &g_external_irq6_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ7
pin_irq_map[7].irq_ctrl = &g_external_irq7_ctrl;
pin_irq_map[7].irq_cfg = &g_external_irq7_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ8
pin_irq_map[8].irq_ctrl = &g_external_irq8_ctrl;
pin_irq_map[8].irq_cfg = &g_external_irq8_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ9
pin_irq_map[9].irq_ctrl = &g_external_irq9_ctrl;
pin_irq_map[9].irq_cfg = &g_external_irq9_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ10
pin_irq_map[10].irq_ctrl = &g_external_irq10_ctrl;
pin_irq_map[10].irq_cfg = &g_external_irq10_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ11
pin_irq_map[11].irq_ctrl = &g_external_irq11_ctrl;
pin_irq_map[11].irq_cfg = &g_external_irq11_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ12
pin_irq_map[12].irq_ctrl = &g_external_irq12_ctrl;
pin_irq_map[12].irq_cfg = &g_external_irq12_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ13
pin_irq_map[13].irq_ctrl = &g_external_irq13_ctrl;
pin_irq_map[13].irq_cfg = &g_external_irq13_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ14
pin_irq_map[14].irq_ctrl = &g_external_irq14_ctrl;
pin_irq_map[14].irq_cfg = &g_external_irq14_cfg;
#endif
#ifdef VECTOR_NUMBER_ICU_IRQ15
pin_irq_map[15].irq_ctrl = &g_external_irq15_ctrl;
pin_irq_map[15].irq_cfg = &g_external_irq15_cfg;
#endif
}
#endif /* R_ICU_H */
static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
fsp_err_t err;
/* Initialize the IOPORT module and configure the pins */
err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
if (err != FSP_SUCCESS)
{
LOG_E("GPIO open failed");
return;
}
switch (mode)
{
case PIN_MODE_OUTPUT:
err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_OUTPUT);
if (err != FSP_SUCCESS)
{
LOG_E("PIN_MODE_OUTPUT configuration failed");
return;
}
break;
case PIN_MODE_INPUT:
err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_INPUT);
if (err != FSP_SUCCESS)
{
LOG_E("PIN_MODE_INPUT configuration failed");
return;
}
break;
case PIN_MODE_OUTPUT_OD:
err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, IOPORT_CFG_NMOS_ENABLE);
if (err != FSP_SUCCESS)
{
LOG_E("PIN_MODE_OUTPUT_OD configuration failed");
return;
}
break;
}
}
static void ra_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
bsp_io_level_t level = BSP_IO_LEVEL_HIGH;
if (value != level)
{
level = BSP_IO_LEVEL_LOW;
}
R_BSP_PinAccessEnable();
R_BSP_PinWrite(pin, level);
R_BSP_PinAccessDisable();
}
static int ra_pin_read(rt_device_t dev, rt_base_t pin)
{
if ((pin > RA_MAX_PIN_VALUE) || (pin < RA_MIN_PIN_VALUE))
{
LOG_E("GPIO pin value is illegal");
return -RT_ERROR;
}
return R_BSP_PinRead(pin);
}
static rt_err_t ra_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
#ifdef R_ICU_H
rt_err_t err;
rt_int32_t irqx = ra_pin_get_irqx(pin);
if (PIN_IRQ_ENABLE == enabled)
{
if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
{
err = R_ICU_ExternalIrqOpen((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl,
(external_irq_cfg_t const * const)pin_irq_map[irqx].irq_cfg);
/* Handle error */
if (FSP_SUCCESS != err)
{
/* ICU Open failure message */
LOG_E("\r\n**R_ICU_ExternalIrqOpen API FAILED**\r\n");
return -RT_ERROR;
}
err = R_ICU_ExternalIrqEnable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
/* Handle error */
if (FSP_SUCCESS != err)
{
/* ICU Enable failure message */
LOG_E("\r\n**R_ICU_ExternalIrqEnable API FAILED**\r\n");
return -RT_ERROR;
}
}
}
else if (PIN_IRQ_DISABLE == enabled)
{
err = R_ICU_ExternalIrqDisable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
if (FSP_SUCCESS != err)
{
/* ICU Disable failure message */
LOG_E("\r\n**R_ICU_ExternalIrqDisable API FAILED**\r\n");
return -RT_ERROR;
}
err = R_ICU_ExternalIrqClose((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
if (FSP_SUCCESS != err)
{
/* ICU Close failure message */
LOG_E("\r\n**R_ICU_ExternalIrqClose API FAILED**\r\n");
return -RT_ERROR;
}
}
return RT_EOK;
#else
return -RT_ERROR;
#endif
}
static rt_err_t ra_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
#ifdef R_ICU_H
rt_int32_t irqx = ra_pin_get_irqx(pin);
if (0 <= irqx && irqx < (sizeof(pin_irq_map) / sizeof(pin_irq_map[0])))
{
int level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqx].pin == irqx &&
pin_irq_hdr_tab[irqx].hdr == hdr &&
pin_irq_hdr_tab[irqx].mode == mode &&
pin_irq_hdr_tab[irqx].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if (pin_irq_hdr_tab[irqx].pin != -1)
{
rt_hw_interrupt_enable(level);
return RT_EBUSY;
}
pin_irq_hdr_tab[irqx].pin = irqx;
pin_irq_hdr_tab[irqx].hdr = hdr;
pin_irq_hdr_tab[irqx].mode = mode;
pin_irq_hdr_tab[irqx].args = args;
rt_hw_interrupt_enable(level);
}
else return -RT_ERROR;
return RT_EOK;
#else
return -RT_ERROR;
#endif
}
static rt_err_t ra_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
#ifdef R_ICU_H
rt_int32_t irqx = ra_pin_get_irqx(pin);
if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
{
int level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqx].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
pin_irq_hdr_tab[irqx].pin = -1;
pin_irq_hdr_tab[irqx].hdr = RT_NULL;
pin_irq_hdr_tab[irqx].mode = 0;
pin_irq_hdr_tab[irqx].args = RT_NULL;
rt_hw_interrupt_enable(level);
}
else
{
return -RT_ERROR;
}
return RT_EOK;
#else
return -RT_ERROR;
#endif
}
static rt_base_t ra_pin_get(const char *name)
{
int pin_number = -1, port = -1, pin = -1;
if (rt_strlen(name) != 4)
return -1;
if ((name[0] == 'P') || (name[0] == 'p'))
{
if ('0' <= (int)name[1] && (int)name[1] <= '9')
{
port = ((int)name[1] - 48) * 16 * 16;
if ('0' <= (int)name[2] && (int)name[2] <= '9')
{
if ('0' <= (int)name[3] && (int)name[3] <= '9')
{
pin = ((int)name[2] - 48) * 10;
pin += (int)name[3] - 48;
pin_number = port + pin;
}
else return -1;
}
else return -1;
}
else return -1;
}
return pin_number;
}
const static struct rt_pin_ops _ra_pin_ops =
{
.pin_mode = ra_pin_mode,
.pin_write = ra_pin_write,
.pin_read = ra_pin_read,
.pin_attach_irq = ra_pin_attach_irq,
.pin_detach_irq = ra_pin_dettach_irq,
.pin_irq_enable = ra_pin_irq_enable,
.pin_get = ra_pin_get,
};
int rt_hw_pin_init(void)
{
#ifdef R_ICU_H
ra_pin_map_init();
#endif
return rt_device_pin_register("pin", &_ra_pin_ops, RT_NULL);
}
#ifdef R_ICU_H
void irq0_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (0 == pin_irq_hdr_tab[0].pin)
{
pin_irq_hdr_tab[0].hdr(pin_irq_hdr_tab[0].args);
}
rt_interrupt_leave();
};
void irq1_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (1 == pin_irq_hdr_tab[1].pin)
{
pin_irq_hdr_tab[1].hdr(pin_irq_hdr_tab[1].args);
}
rt_interrupt_leave();
};
void irq2_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (2 == pin_irq_hdr_tab[2].pin)
{
pin_irq_hdr_tab[2].hdr(pin_irq_hdr_tab[2].args);
}
rt_interrupt_leave();
};
void irq3_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (3 == pin_irq_hdr_tab[3].pin)
{
pin_irq_hdr_tab[3].hdr(pin_irq_hdr_tab[3].args);
}
rt_interrupt_leave();
};
void irq4_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (4 == pin_irq_hdr_tab[4].pin)
{
pin_irq_hdr_tab[4].hdr(pin_irq_hdr_tab[4].args);
}
rt_interrupt_leave();
};
void irq5_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (5 == pin_irq_hdr_tab[5].pin)
{
pin_irq_hdr_tab[5].hdr(pin_irq_hdr_tab[5].args);
}
rt_interrupt_leave();
};
void irq6_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (6 == pin_irq_hdr_tab[6].pin)
{
pin_irq_hdr_tab[6].hdr(pin_irq_hdr_tab[6].args);
}
rt_interrupt_leave();
};
void irq7_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (7 == pin_irq_hdr_tab[7].pin)
{
pin_irq_hdr_tab[7].hdr(pin_irq_hdr_tab[7].args);
}
rt_interrupt_leave();
};
void irq8_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (8 == pin_irq_hdr_tab[8].pin)
{
pin_irq_hdr_tab[8].hdr(pin_irq_hdr_tab[8].args);
}
rt_interrupt_leave();
};
void irq9_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (9 == pin_irq_hdr_tab[9].pin)
{
pin_irq_hdr_tab[9].hdr(pin_irq_hdr_tab[9].args);
}
rt_interrupt_leave();
};
void irq10_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (10 == pin_irq_hdr_tab[10].pin)
{
pin_irq_hdr_tab[10].hdr(pin_irq_hdr_tab[10].args);
}
rt_interrupt_leave();
};
void irq11_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (11 == pin_irq_hdr_tab[11].pin)
{
pin_irq_hdr_tab[11].hdr(pin_irq_hdr_tab[11].args);
}
rt_interrupt_leave();
};
void irq12_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (12 == pin_irq_hdr_tab[12].pin)
{
pin_irq_hdr_tab[12].hdr(pin_irq_hdr_tab[12].args);
}
rt_interrupt_leave();
};
void irq13_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (13 == pin_irq_hdr_tab[13].pin)
{
pin_irq_hdr_tab[13].hdr(pin_irq_hdr_tab[13].args);
}
rt_interrupt_leave();
};
void irq14_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (14 == pin_irq_hdr_tab[14].pin)
{
pin_irq_hdr_tab[14].hdr(pin_irq_hdr_tab[14].args);
}
rt_interrupt_leave();
};
void irq15_callback(external_irq_callback_args_t *p_args)
{
rt_interrupt_enter();
if (15 == pin_irq_hdr_tab[15].pin)
{
pin_irq_hdr_tab[15].hdr(pin_irq_hdr_tab[15].args);
}
rt_interrupt_leave();
};
#endif /* R_ICU_H */
#endif /* RT_USING_PIN */

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <board.h>
#include <rthw.h>
#include <rtdbg.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <drv_common.h>
#include <hal_data.h>
#ifdef __cplusplus
extern "C" {
#endif
#define RA_MIN_PIN_VALUE BSP_IO_PORT_00_PIN_00
#define RA_MAX_PIN_VALUE BSP_IO_PORT_11_PIN_15
#ifdef R_ICU_H
struct ra_pin_irq_map
{
const icu_instance_ctrl_t *irq_ctrl;
const external_irq_cfg_t *irq_cfg;
};
#endif
int rt_hw_pin_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_GPIO_H__ */

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bsp/ra6m4-cpk/drivers/drv_pwm.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-25 KevinXu first version
*/
#include "drv_pwm.h"
#ifdef RT_USING_PWM
/* Declare the control function first */
static rt_err_t drv_pwm_control(struct rt_device_pwm *, int, void *);
static struct rt_pwm_ops drv_ops =
{
drv_pwm_control
};
static struct ra_pwm ra6m4_pwm_obj[BSP_PWMS_NUM] =
{
#ifdef BSP_USING_PWM0
[BSP_PWM0_INDEX] = PWM_DRV_INITIALIZER(0),
#endif
#ifdef BSP_USING_PWM1
[BSP_PWM1_INDEX] = PWM_DRV_INITIALIZER(1),
#endif
#ifdef BSP_USING_PWM2
[BSP_PWM2_INDEX] = PWM_DRV_INITIALIZER(2),
#endif
#ifdef BSP_USING_PWM3
[BSP_PWM3_INDEX] = PWM_DRV_INITIALIZER(3),
#endif
#ifdef BSP_USING_PWM4
[BSP_PWM4_INDEX] = PWM_DRV_INITIALIZER(4),
#endif
#ifdef BSP_USING_PWM5
[BSP_PWM5_INDEX] = PWM_DRV_INITIALIZER(5),
#endif
#ifdef BSP_USING_PWM6
[BSP_PWM6_INDEX] = PWM_DRV_INITIALIZER(6),
#endif
#ifdef BSP_USING_PWM7
[BSP_PWM7_INDEX] = PWM_DRV_INITIALIZER(7),
#endif
#ifdef BSP_USING_PWM8
[BSP_PWM8_INDEX] = PWM_DRV_INITIALIZER(8),
#endif
#ifdef BSP_USING_PWM9
[BSP_PWM9_INDEX] = PWM_DRV_INITIALIZER(9),
#endif
};
/* Convert the raw PWM period counts into ns */
static rt_uint32_t _convert_counts_ns(uint32_t source_div, uint32_t raw)
{
uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
uint32_t ns = (uint32_t)(((uint64_t)raw * 1000000000ULL) / pclkd_freq_hz);
return ns;
}
/* Convert ns into raw PWM period counts */
static rt_uint32_t _convert_ns_counts(uint32_t source_div, uint32_t raw)
{
uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
uint32_t counts = (uint32_t)(((uint64_t)raw * (uint64_t)pclkd_freq_hz) / 1000000000ULL);
return counts;
}
/* PWM_CMD_ENABLE or PWM_CMD_DISABLE */
static rt_err_t drv_pwm_enable(struct ra_pwm *device,
struct rt_pwm_configuration *configuration,
rt_bool_t enable)
{
fsp_err_t err = FSP_SUCCESS;
if (enable)
{
err = R_GPT_Start(device->g_ctrl);
}
else
{
err = R_GPT_Stop(device->g_ctrl);
}
return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR;
}
/* PWM_CMD_GET */
static rt_err_t drv_pwm_get(struct ra_pwm *device,
struct rt_pwm_configuration *configuration)
{
timer_info_t info;
if (R_GPT_InfoGet(device->g_ctrl, &info) != FSP_SUCCESS)
return -RT_ERROR;
configuration->pulse =
_convert_counts_ns(device->g_cfg->source_div, device->g_cfg->duty_cycle_counts);
configuration->period =
_convert_counts_ns(device->g_cfg->source_div, info.period_counts);
configuration->channel = device->g_cfg->channel;
return RT_EOK;
}
/* PWM_CMD_SET */
static rt_err_t drv_pwm_set(struct ra_pwm *device,
struct rt_pwm_configuration *conf)
{
uint32_t counts;
fsp_err_t fsp_erra;
fsp_err_t fsp_errb;
rt_err_t rt_err;
uint32_t pulse;
uint32_t period;
struct rt_pwm_configuration orig_conf;
rt_err = drv_pwm_get(device, &orig_conf);
if (rt_err != RT_EOK)
{
return rt_err;
}
/* Pulse cannot last longer than period. */
period = conf->period;
pulse = (period >= conf->pulse) ? conf->pulse : period;
/* Not to set period again if it's not changed. */
if (period != orig_conf.period)
{
counts = _convert_ns_counts(device->g_cfg->source_div, period);
fsp_erra = R_GPT_PeriodSet(device->g_ctrl, counts);
if (fsp_erra != FSP_SUCCESS)
{
return -RT_ERROR;
}
}
/* Two pins of a channel will not be separated. */
counts = _convert_ns_counts(device->g_cfg->source_div, pulse);
fsp_erra = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCA);
fsp_errb = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCB);
if (fsp_erra != FSP_SUCCESS || fsp_errb != FSP_SUCCESS)
{
return -RT_ERROR;
}
return RT_EOK;
}
/**
* Implement of control method in struct rt_pwm_ops.
*/
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
{
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
struct ra_pwm *pwm_device = (struct ra_pwm *)device->parent.user_data;
/**
* There's actually only one GPT timer with 10 channels. In this case, the
* timer is separated into 10 PWM devices, so each device has only one
* channel.
*/
if (configuration->channel != 0)
{
return -RT_EINVAL;
}
switch (cmd)
{
case PWM_CMD_ENABLE:
return drv_pwm_enable(pwm_device, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return drv_pwm_enable(pwm_device, configuration, RT_FALSE);
case PWM_CMD_GET:
return drv_pwm_get(pwm_device, configuration);
case PWM_CMD_SET:
return drv_pwm_set(pwm_device, configuration);
default:
return -RT_EINVAL;
}
return RT_EOK;
}
/**
* This is to register the PWM device
*
* Note that the PWM driver only supports one fixed pin.
*/
int rt_hw_pwm_init(void)
{
rt_err_t ret = RT_EOK;
rt_err_t rt_err = RT_EOK;
fsp_err_t fsp_err = FSP_SUCCESS;
for (int i = 0; i < BSP_PWMS_NUM; i++)
{
fsp_err = R_GPT_Open(ra6m4_pwm_obj[i].g_ctrl,
ra6m4_pwm_obj[i].g_cfg);
rt_err = rt_device_pwm_register(&ra6m4_pwm_obj[i].pwm_device,
ra6m4_pwm_obj[i].name,
&drv_ops,
&ra6m4_pwm_obj[i]);
if (fsp_err != FSP_SUCCESS || rt_err != RT_EOK)
{
ret = -RT_ERROR;
}
}
return ret;
}
INIT_BOARD_EXPORT(rt_hw_pwm_init);
#endif /* RT_USING_PWM */

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bsp/ra6m4-cpk/drivers/drv_pwm.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-25 KevinXu first version
*/
#ifndef __DRV_PWM_H__
#define __DRV_PWM_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include <drv_common.h>
#include <drv_config.h>
#include <hal_data.h>
/* PWM device object structure */
struct ra_pwm
{
struct rt_device_pwm pwm_device;
gpt_instance_ctrl_t *g_ctrl;
timer_instance_t const *const g_timer;
timer_cfg_t const *const g_cfg;
char *name;
};
/* Get ra6m4 pwm device object from the general pwm device object */
#define _GET_RA6M4_PWM_OBJ(ptr) rt_container_of(ptr, struct ra_pwm, pwm_device)
#endif /* __DRV_PWM_H__ */

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bsp/ra6m4-cpk/drivers/drv_rtc.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-14 Mr.Tiger first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include <sys/time.h>
#include "hal_data.h"
#ifdef BSP_USING_ONCHIP_RTC
#define DBG_TAG "drv.rtc"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
static rt_err_t ra_rtc_init(void)
{
rt_err_t result = RT_EOK;
if (R_RTC_Open(&g_rtc_ctrl, &g_rtc_cfg) != RT_EOK)
{
LOG_E("rtc init failed.");
result = -RT_ERROR;
}
return result;
}
static time_t get_rtc_timestamp(void)
{
struct tm tm_new = {0};
rtc_time_t g_current_time = {0};
R_RTC_CalendarTimeGet(&g_rtc_ctrl, &g_current_time);
tm_new.tm_year = g_current_time.tm_year;
tm_new.tm_mon = g_current_time.tm_mon;
tm_new.tm_mday = g_current_time.tm_mday;
tm_new.tm_hour = g_current_time.tm_hour;
tm_new.tm_min = g_current_time.tm_min;
tm_new.tm_sec = g_current_time.tm_sec;
tm_new.tm_wday = g_current_time.tm_wday;
tm_new.tm_yday = g_current_time.tm_yday;
tm_new.tm_isdst = g_current_time.tm_isdst;
return timegm(&tm_new);
}
static rt_err_t ra_get_secs(void *args)
{
*(rt_uint32_t *)args = get_rtc_timestamp();
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
return RT_EOK;
}
static rt_err_t set_rtc_time_stamp(time_t time_stamp)
{
struct tm *p_tm;
rtc_time_t g_current_time = {0};
p_tm = gmtime(&time_stamp);
if (p_tm->tm_year < 100)
{
return -RT_ERROR;
}
g_current_time.tm_sec = p_tm->tm_sec ;
g_current_time.tm_min = p_tm->tm_min ;
g_current_time.tm_hour = p_tm->tm_hour;
g_current_time.tm_mday = p_tm->tm_mday;
g_current_time.tm_mon = p_tm->tm_mon;
g_current_time.tm_year = p_tm->tm_year;
g_current_time.tm_wday = p_tm->tm_wday;
g_current_time.tm_yday = p_tm->tm_yday;
if (R_RTC_CalendarTimeSet(&g_rtc_ctrl, &g_current_time) != FSP_SUCCESS)
{
LOG_E("set rtc time failed.");
return -RT_ERROR;
}
return RT_EOK;
}
static rt_err_t ra_set_secs(void *args)
{
rt_err_t result = RT_EOK;
if (set_rtc_time_stamp(*(rt_uint32_t *)args))
{
result = -RT_ERROR;
}
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
return result;
}
#ifdef RT_USING_ALARM
static rt_err_t ra_get_alarm(void *arg)
{
rt_err_t result = RT_EOK;
struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
rtc_alarm_time_t alarm_time_get =
{
.sec_match = RT_FALSE,
.min_match = RT_FALSE,
.hour_match = RT_FALSE,
.mday_match = RT_FALSE,
.mon_match = RT_FALSE,
.year_match = RT_FALSE,
.dayofweek_match = RT_FALSE,
};
if (RT_EOK == R_RTC_CalendarAlarmGet(&g_rtc_ctrl, &alarm_time_get))
{
wkalarm->tm_hour = alarm_time_get.time.tm_hour;
wkalarm->tm_min = alarm_time_get.time.tm_min;
wkalarm->tm_sec = alarm_time_get.time.tm_sec;
}
else
{
LOG_E("Calendar alarm Get failed.");
}
return result;
}
static rt_err_t ra_set_alarm(void *arg)
{
rt_err_t result = RT_EOK;
struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
rtc_alarm_time_t alarm_time_set =
{
.sec_match = RT_TRUE,
.min_match = RT_TRUE,
.hour_match = RT_TRUE,
.mday_match = RT_FALSE,
.mon_match = RT_FALSE,
.year_match = RT_FALSE,
.dayofweek_match = RT_FALSE,
};
alarm_time_set.time.tm_hour = wkalarm->tm_hour;
alarm_time_set.time.tm_min = wkalarm->tm_min;
alarm_time_set.time.tm_sec = wkalarm->tm_sec;
if (1 == wkalarm->enable)
{
if (RT_EOK != R_RTC_CalendarAlarmSet(&g_rtc_ctrl, &alarm_time_set))
{
LOG_E("Calendar alarm Set failed.");
result = -RT_ERROR;
}
}
else
{
alarm_time_set.sec_match = RT_FALSE;
alarm_time_set.min_match = RT_FALSE;
alarm_time_set.hour_match = RT_FALSE;
if (RT_EOK != R_RTC_CalendarAlarmSet(&g_rtc_ctrl, &alarm_time_set))
{
LOG_E("Calendar alarm Stop failed.");
result = -RT_ERROR;
}
}
return result;
}
#endif /* RT_USING_ALARM */
void rtc_callback(rtc_callback_args_t *p_args)
{
#ifdef RT_USING_ALARM
static rt_device_t ra_device;
if (RTC_EVENT_ALARM_IRQ == p_args->event)
{
rt_alarm_update(ra_device, 1);
}
#endif
}
static const struct rt_rtc_ops ra_rtc_ops =
{
.init = ra_rtc_init,
.get_secs = ra_get_secs,
.set_secs = ra_set_secs,
#ifdef RT_USING_ALARM
.set_alarm = ra_set_alarm,
.get_alarm = ra_get_alarm,
#endif
};
static rt_rtc_dev_t ra_rtc_dev;
static int rt_hw_rtc_init(void)
{
rt_err_t result;
ra_rtc_dev.ops = &ra_rtc_ops;
result = rt_hw_rtc_register(&ra_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL);
if (result != RT_EOK)
{
LOG_E("rtc register err code: %d", result);
return result;
}
LOG_D("rtc init success");
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#include "board.h"
#include "drv_soft_i2c.h"
#include "drv_config.h"
#ifdef RT_USING_I2C
#define DBG_TAG "drv.i2c"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1)
#error "Please define at least one BSP_USING_I2Cx"
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#endif
static const struct ra_soft_i2c_config soft_i2c_config[] =
{
#ifdef BSP_USING_I2C0
I2C0_BUS_CONFIG,
#endif
#ifdef BSP_USING_I2C1
I2C1_BUS_CONFIG,
#endif
};
static struct ra_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
/**
* This function initializes the i2c pin.
*
* @param ra i2c dirver class.
*/
static void ra_i2c_gpio_init(struct ra_i2c *i2c)
{
struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)i2c->ops.data;
rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
rt_pin_write(cfg->scl, PIN_HIGH);
rt_pin_write(cfg->sda, PIN_HIGH);
}
/**
* This function sets the sda pin.
*
* @param ra config class.
* @param The sda pin state.
*/
static void ra_set_sda(void *data, rt_int32_t state)
{
struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
if (state)
{
rt_pin_write(cfg->sda, PIN_HIGH);
}
else
{
rt_pin_write(cfg->sda, PIN_LOW);
}
}
/**
* This function sets the scl pin.
*
* @param ra config class.
* @param The scl pin state.
*/
static void ra_set_scl(void *data, rt_int32_t state)
{
struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
if (state)
{
rt_pin_write(cfg->scl, PIN_HIGH);
}
else
{
rt_pin_write(cfg->scl, PIN_LOW);
}
}
/**
* This function gets the sda pin state.
*
* @param The sda pin state.
*/
static rt_int32_t ra_get_sda(void *data)
{
struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
return rt_pin_read(cfg->sda);
}
/**
* This function gets the scl pin state.
*
* @param The scl pin state.
*/
static rt_int32_t ra_get_scl(void *data)
{
struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
return rt_pin_read(cfg->scl);
}
/**
* The time delay function.
*
* @param microseconds.
*/
static void ra_udelay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
static const struct rt_i2c_bit_ops ra_bit_ops_default =
{
.data = RT_NULL,
.set_sda = ra_set_sda,
.set_scl = ra_set_scl,
.get_sda = ra_get_sda,
.get_scl = ra_get_scl,
.udelay = ra_udelay,
.delay_us = 1,
.timeout = 100
};
/**
* if i2c is locked, this function will unlock it
*
* @param ra config class
*
* @return RT_EOK indicates successful unlock.
*/
static rt_err_t ra_i2c_bus_unlock(const struct ra_soft_i2c_config *cfg)
{
rt_int32_t i = 0;
if (PIN_LOW == rt_pin_read(cfg->sda))
{
while (i++ < 9)
{
rt_pin_write(cfg->scl, PIN_HIGH);
ra_udelay(100);
rt_pin_write(cfg->scl, PIN_LOW);
ra_udelay(100);
}
}
if (PIN_LOW == rt_pin_read(cfg->sda))
{
return -RT_ERROR;
}
return RT_EOK;
}
/* I2C initialization function */
int rt_hw_i2c_init(void)
{
rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct ra_i2c);
rt_err_t result;
for (int i = 0; i < obj_num; i++)
{
i2c_obj[i].ops = ra_bit_ops_default;
i2c_obj[i].ops.data = (void *)&soft_i2c_config[i];
i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
ra_i2c_gpio_init(&i2c_obj[i]);
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
RT_ASSERT(result == RT_EOK);
ra_i2c_bus_unlock(&soft_i2c_config[i]);
LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].sda);
}
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_hw_i2c_init);
#endif /* RT_USING_I2C */

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bsp/ra6m4-cpk/drivers/drv_soft_i2c.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#ifndef __DRV_I2C__
#define __DRV_I2C__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <rtdbg.h>
/* ra config class */
struct ra_soft_i2c_config
{
rt_uint32_t scl;
rt_uint32_t sda;
const char *bus_name;
};
/* ra i2c dirver class */
struct ra_i2c
{
struct rt_i2c_bit_ops ops;
struct rt_i2c_bus_device i2c2_bus;
};
#ifdef BSP_USING_I2C1
#define I2C1_BUS_CONFIG \
{ \
.scl = BSP_I2C1_SCL_PIN, \
.sda = BSP_I2C1_SDA_PIN, \
.bus_name = "i2c1", \
}
#endif
#ifdef BSP_USING_I2C2
#define I2C2_BUS_CONFIG \
{ \
.scl = BSP_I2C2_SCL_PIN, \
.sda = BSP_I2C2_SDA_PIN, \
.bus_name = "i2c2", \
}
#endif
int rt_hw_i2c_init(void);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-23 Mr.Tiger first version
*/
/**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
#include "drv_spi.h"
#ifdef RT_USING_SPI
//#define DRV_DEBUG
#define DBG_TAG "drv.spi"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
static struct ra_spi_handle spi_handle[] =
{
#ifdef BSP_USING_SPI0
{.bus_name = "spi0", .spi_ctrl_t = &g_spi0_ctrl, .spi_cfg_t = &g_spi0_cfg,},
#endif
#ifdef BSP_USING_SPI1
{.bus_name = "spi1", .spi_ctrl_t = &g_spi1_ctrl, .spi_cfg_t = &g_spi1_cfg,},
#endif
};
static struct ra_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0};
void g_spi0_callback(spi_callback_args_t *p_args)
{
rt_interrupt_enter();
if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event)
{
LOG_D("SPI0 cb");
}
rt_interrupt_leave();
}
void g_spi1_callback(spi_callback_args_t *p_args)
{
rt_interrupt_enter();
if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event)
{
LOG_D("SPI1 cb");
}
rt_interrupt_leave();
}
static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
{
RT_ASSERT(device != NULL);
RT_ASSERT(device->parent.user_data != NULL);
RT_ASSERT(send_buf != NULL);
RT_ASSERT(len > 0);
rt_err_t err = RT_EOK;
struct ra_spi *spi_dev = rt_container_of(device->bus, struct ra_spi, bus);
spi_dev->cs_pin = *(rt_uint32_t *)device->parent.user_data;
/**< Configure Select Line */
R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_HIGH);
/* Start a write transfer */
R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_LOW);
/**< send msessage */
err = R_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, spi_dev->rt_spi_cfg_t->data_width);
if (RT_EOK != err)
{
LOG_E("%s write failed.", spi_dev->ra_spi_handle_t->bus_name);
return -RT_ERROR;
}
return len;
}
static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len)
{
RT_ASSERT(device != NULL);
RT_ASSERT(device->parent.user_data != NULL);
RT_ASSERT(recv_buf != NULL);
RT_ASSERT(len > 0);
rt_err_t err = RT_EOK;
struct ra_spi *spi_dev = rt_container_of(device->bus, struct ra_spi, bus);
spi_dev->cs_pin = *(rt_uint32_t *)device->parent.user_data;
/**< Configure Select Line */
R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_HIGH);
/* Start read transfer */
R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_LOW);
/**< receive message */
err = R_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, spi_dev->rt_spi_cfg_t->data_width);
if (RT_EOK != err)
{
LOG_E("\n%s write failed.\n", spi_dev->ra_spi_handle_t->bus_name);
return -RT_ERROR;
}
return len;
}
static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
RT_ASSERT(message->length > 0);
rt_err_t err = RT_EOK;
struct ra_spi *spi_dev = rt_container_of(device->bus, struct ra_spi, bus);
/**< write and receive message */
err = R_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, spi_dev->rt_spi_cfg_t->data_width);
if (RT_EOK != err)
{
LOG_E("%s write and read failed.", spi_dev->ra_spi_handle_t->bus_name);
return -RT_ERROR;
}
return message->length;
}
/**< init spi TODO : MSB does not support modification */
static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
RT_ASSERT(device != NULL);
RT_ASSERT(configuration != NULL);
rt_err_t err = RT_EOK;
struct ra_spi *spi_dev = rt_container_of(device->bus, struct ra_spi, bus);
spi_dev->cs_pin = (rt_uint32_t)device->parent.user_data;
/**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/
rt_uint8_t data_width = configuration->data_width / 8;
RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4);
configuration->data_width = configuration->data_width / 8;
spi_dev->rt_spi_cfg_t = configuration;
spi_extended_cfg_t *spi_cfg = (spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
/**< Configure Select Line */
R_BSP_PinWrite(spi_dev->cs_pin, BSP_IO_LEVEL_HIGH);
/**< config bitrate */
R_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->spck_div);
/**< init */
err = R_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
/* handle error */
if (RT_EOK != err)
{
LOG_E("%s init failed.", spi_dev->ra_spi_handle_t->bus_name);
return -RT_ERROR;
}
return RT_EOK;
}
static rt_uint32_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
rt_err_t err = RT_EOK;
if (message->length <= 0)
{
LOG_E("buf length err.");
}
else
{
if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
{
/**< receive message */
err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length);
}
else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
{
/**< send message */
err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length);
}
else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
{
/**< send and receive message */
err = ra_write_read_message(device, message);
}
}
return err;
}
static const struct rt_spi_ops ra_spi_ops =
{
.configure = ra_hw_spi_configure,
.xfer = ra_spixfer,
};
void rt_hw_spi_device_attach(struct rt_spi_device *device, const char *device_name, const char *bus_name, void *user_data)
{
RT_ASSERT(device != NULL);
RT_ASSERT(device_name != NULL);
RT_ASSERT(bus_name != NULL);
RT_ASSERT(user_data != NULL);
rt_err_t err = rt_spi_bus_attach_device(device, device_name, bus_name, user_data);
if (RT_EOK != err)
{
LOG_E("%s attach failed.", bus_name);
}
}
int ra_hw_spi_init(void)
{
for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
{
spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index];
/**< register spi bus */
rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops);
if (RT_EOK != err)
{
LOG_E("%s bus register failed.", spi_config[spi_index].ra_spi_handle_t->bus_name);
}
}
return RT_EOK;
}
INIT_BOARD_EXPORT(ra_hw_spi_init);
#endif /* RT_USING_SPI */

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-23 Mr.Tiger first version
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#include "board.h"
#include <rthw.h>
#include <drv_common.h>
#include <drv_config.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef R_SPI_H
struct ra_spi_handle
{
const char *bus_name;
const spi_cfg_t *spi_cfg_t;
const spi_instance_ctrl_t *spi_ctrl_t;
};
struct ra_spi
{
rt_uint32_t cs_pin;
struct ra_spi_handle *ra_spi_handle_t;
struct rt_spi_configuration *rt_spi_cfg_t;
struct rt_spi_bus bus;
};
#endif
void rt_hw_spi_device_attach(struct rt_spi_device *device, const char *device_name, const char *bus_name, void *user_data);
#ifdef __cplusplus
}
#endif
/* stm32 spi dirver class */
#endif /*__DRV_SPI_H__ */

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#include <drv_usart_v2.h>
#ifdef RT_USING_SERIAL_V2
//#define DRV_DEBUG
#define DBG_TAG "drv.usart"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
static struct ra_uart_config uart_config[] =
{
#ifdef BSP_USING_UART7
UART7_CONFIG,
#endif
#ifdef BSP_USING_UART1
UART1_CONFIG,
#endif
};
enum
{
#ifdef BSP_USING_UART7
UART7_INDEX,
#endif
#ifdef BSP_USING_UART1
UART1_INDEX,
#endif
};
static struct ra_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
static void ra_uart_get_config(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef BSP_USING_UART7
uart_obj[UART7_INDEX].serial.config = config;
uart_obj[UART7_INDEX].uart_dma_flag = 0;
uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
#endif
#ifdef BSP_USING_UART1
uart_obj[UART1_INDEX].serial.config = config;
uart_obj[UART1_INDEX].uart_dma_flag = 0;
uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
#endif
}
/*
* UART interface
*/
static rt_err_t ra_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct ra_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
fsp_err_t err = FSP_SUCCESS;
uart = rt_container_of(serial, struct ra_uart, serial);
RT_ASSERT(uart != RT_NULL);
err = R_SCI_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg);
if (FSP_SUCCESS != err)
{
return RT_ERROR;
}
return RT_EOK;
}
static rt_err_t ra_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
return RT_EOK;
}
static int ra_uart_putc(struct rt_serial_device *serial, char c)
{
struct ra_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct ra_uart, serial);
RT_ASSERT(uart != RT_NULL);
sci_uart_instance_ctrl_t *p_ctrl = (sci_uart_instance_ctrl_t *)uart->config->p_api_ctrl;
p_ctrl->p_reg->TDR = c;
while ((p_ctrl->p_reg->SSR_b.TEND) == 0);
return RT_EOK;
}
static int ra_uart_getc(struct rt_serial_device *serial)
{
return RT_EOK;
}
#ifdef BSP_USING_UART7
void uart7_isr_cb(uart_callback_args_t *p_args)
{
rt_interrupt_enter();
struct rt_serial_device *serial = &uart_obj[0].serial;
RT_ASSERT(serial != RT_NULL);
if (UART_EVENT_RX_CHAR == p_args->event)
{
struct rt_serial_rx_fifo *rx_fifo;
rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
RT_ASSERT(rx_fifo != RT_NULL);
rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_UART1
void uart1_isr_cb(uart_callback_args_t *p_args)
{
rt_interrupt_enter();
struct rt_serial_device *serial = &uart_obj[1].serial;
RT_ASSERT(serial != RT_NULL);
if (UART_EVENT_RX_CHAR == p_args->event)
{
struct rt_serial_rx_fifo *rx_fifo;
rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
RT_ASSERT(rx_fifo != RT_NULL);
rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
rt_interrupt_leave();
}
#endif
static const struct rt_uart_ops ra_uart_ops =
{
.configure = ra_uart_configure,
.control = ra_uart_control,
.putc = ra_uart_putc,
.getc = ra_uart_getc,
};
int rt_hw_usart_init(void)
{
rt_err_t result = 0;
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct ra_uart);
ra_uart_get_config();
for (int i = 0; i < obj_num; i++)
{
/* init UART object */
uart_obj[i].config = &uart_config[i];
uart_obj[i].serial.ops = &ra_uart_ops;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial,
uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR,
NULL);
RT_ASSERT(result == RT_EOK);
}
return result;
}
#endif /* RT_USING_SERIAL_V2 */

40
bsp/ra6m4-cpk/drivers/drv_usart_v2.h Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#ifndef __DRV_USART_V2_H__
#define __DRV_USART_V2_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include <drv_common.h>
#include <drv_config.h>
#include <hal_data.h>
/* renesas config class */
struct ra_uart_config
{
const char *name;
uart_ctrl_t *const p_api_ctrl;
uart_cfg_t const *const p_cfg;
};
struct ra_uart
{
struct rt_serial_device serial;
rt_uint16_t uart_dma_flag;
struct ra_uart_config *config;
};
int rt_hw_usart_init(void);
#endif /* __DRV_USART_H__ */

94
bsp/ra6m4-cpk/drivers/drv_wdt.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 Mr.Tiger first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include <drv_common.h>
#include <drv_config.h>
#include <hal_data.h>
#ifdef RT_USING_WDT
//#define DRV_DEBUG
#define LOG_TAG "drv.wdt"
#include <rtdbg.h>
static struct rt_watchdog_device ra_wdt_dev;
static struct rt_watchdog_ops ops;
static rt_err_t wdt_init(rt_watchdog_t *wdt)
{
return RT_EOK;
}
static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
struct st_wdt_timeout_values *wdt_value = {0};
switch (cmd)
{
/* feed the watchdog */
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
if (R_WDT_Refresh(&g_wdt_ctrl) != FSP_SUCCESS)
{
LOG_E("watch dog keepalive fail.");
}
break;
/* set watchdog timeout */
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
/**< set*/
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
wdt_value = (struct st_wdt_timeout_values *)arg;
if (R_WDT_TimeoutGet(&g_wdt_ctrl, wdt_value) != FSP_SUCCESS)
{
LOG_E("wdt get timeout failed.");
return -RT_ERROR;
}
break;
case RT_DEVICE_CTRL_WDT_START:
if (R_WDT_Open(&g_wdt_ctrl, &g_wdt_cfg) == FSP_SUCCESS)
{
if (R_WDT_Refresh(&g_wdt_ctrl) != FSP_SUCCESS)
{
LOG_E("wdt start failed.");
return -RT_ERROR;
}
}
else
{
LOG_E("wdt start failed.");
return -RT_ERROR;
}
break;
default:
LOG_W("This command is not supported.");
return -RT_ERROR;
}
return RT_EOK;
}
int rt_wdt_init(void)
{
ops.init = &wdt_init;
ops.control = &wdt_control;
ra_wdt_dev.ops = &ops;
/* register watchdog device */
if (rt_hw_watchdog_register(&ra_wdt_dev, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
LOG_E("wdt device register failed.");
return -RT_ERROR;
}
LOG_D("wdt device register success.");
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_wdt_init);
#endif /* RT_USING_WDT */

12
bsp/ra6m4-cpk/ports/SConscript Normal file
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import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

20
bsp/ra6m4-cpk/ports/fal/SConscript Normal file
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@ -0,0 +1,20 @@
from building import *
import rtconfig
cwd = GetCurrentDir()
src = []
src += Glob('*.c')
CPPPATH = [cwd]
LOCAL_CCFLAGS = ''
if rtconfig.CROSS_TOOL == 'gcc':
LOCAL_CCFLAGS += ' -std=c99'
elif rtconfig.CROSS_TOOL == 'keil':
LOCAL_CCFLAGS += ' --c99'
group = DefineGroup('FAL', src, depend = ['PKG_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS)
Return('group')

39
bsp/ra6m4-cpk/ports/fal/fal_cfg.h Normal file
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@ -0,0 +1,39 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-08-21 MurphyZhao the first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
/* enable stm32l4 onchip flash driver sample */
#define FAL_FLASH_PORT_DRIVER_STM32L4
/* enable SFUD flash driver sample */
#define FAL_FLASH_PORT_DRIVER_SFUD
extern const struct fal_flash_dev _onchip_flash_8k;
extern const struct fal_flash_dev _onchip_flash_128k;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&_onchip_flash_8k, \
&_onchip_flash_128k, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_8k", 0, 64 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash_128k", 0, 3 * 128 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

656
bsp/ra6m4-cpk/project.uvoptx Normal file
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@ -0,0 +1,656 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>1</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U-O78 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD0 -FC800 -FN0</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>CPU</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\libcpu\arm\common\backtrace.c</PathWithFileName>
<FilenameWithoutPath>backtrace.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\libcpu\arm\common\div0.c</PathWithFileName>
<FilenameWithoutPath>div0.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\libcpu\arm\common\showmem.c</PathWithFileName>
<FilenameWithoutPath>showmem.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\libcpu\arm\cortex-m4\cpuport.c</PathWithFileName>
<FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\libcpu\arm\cortex-m4\context_rvds.S</PathWithFileName>
<FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\drivers\misc\pin.c</PathWithFileName>
<FilenameWithoutPath>pin.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\drivers\serial\serial_v2.c</PathWithFileName>
<FilenameWithoutPath>serial_v2.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\drivers\src\waitqueue.c</PathWithFileName>
<FilenameWithoutPath>waitqueue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\drivers\src\dataqueue.c</PathWithFileName>
<FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\drivers\src\ringblk_buf.c</PathWithFileName>
<FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\drivers\src\pipe.c</PathWithFileName>
<FilenameWithoutPath>pipe.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\drivers\src\ringbuffer.c</PathWithFileName>
<FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\drivers\src\workqueue.c</PathWithFileName>
<FilenameWithoutPath>workqueue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\drivers\src\completion.c</PathWithFileName>
<FilenameWithoutPath>completion.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>drivers\drv_gpio.c</PathWithFileName>
<FilenameWithoutPath>drv_gpio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>drivers\drv_usart_v2.c</PathWithFileName>
<FilenameWithoutPath>drv_usart_v2.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>drivers\drv_common.c</PathWithFileName>
<FilenameWithoutPath>drv_common.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Finsh</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\finsh\shell.c</PathWithFileName>
<FilenameWithoutPath>shell.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\finsh\msh.c</PathWithFileName>
<FilenameWithoutPath>msh.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\finsh\cmd.c</PathWithFileName>
<FilenameWithoutPath>cmd.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\components.c</PathWithFileName>
<FilenameWithoutPath>components.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\irq.c</PathWithFileName>
<FilenameWithoutPath>irq.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\object.c</PathWithFileName>
<FilenameWithoutPath>object.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>24</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\idle.c</PathWithFileName>
<FilenameWithoutPath>idle.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\kservice.c</PathWithFileName>
<FilenameWithoutPath>kservice.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\clock.c</PathWithFileName>
<FilenameWithoutPath>clock.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\device.c</PathWithFileName>
<FilenameWithoutPath>device.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\scheduler.c</PathWithFileName>
<FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\thread.c</PathWithFileName>
<FilenameWithoutPath>thread.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\mem.c</PathWithFileName>
<FilenameWithoutPath>mem.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>31</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\ipc.c</PathWithFileName>
<FilenameWithoutPath>ipc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>32</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\timer.c</PathWithFileName>
<FilenameWithoutPath>timer.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>libc</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\components\libc\compilers\common\time.c</PathWithFileName>
<FilenameWithoutPath>time.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\src\hal_entry.c</PathWithFileName>
<FilenameWithoutPath>hal_entry.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>35</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\src\SConscript</PathWithFileName>
<FilenameWithoutPath>SConscript</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::Flex Software</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>R7FA6M4AF</Device>
<Vendor>Renesas</Vendor>
<PackID>Renesas.RA_DFP.3.1.0</PackID>
<PackURL>https://www2.renesas.eu/Keil_MDK_Packs/</PackURL>
<Cpu>CPUTYPE("Cortex-M33") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:R7FA6M4AF$SVD\R7FA6M4AF.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>ra6m4</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>0</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2></Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M33"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>0</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>0</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>0</RoSelD>
<RwSelD>0</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IRAM>
<IROM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>6</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>-Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal</MiscControls>
<Define>SOC_R7FA6M4AF, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Undefine></Undefine>
<IncludePath>..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;drivers\config;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\nogcc;..\..\examples\utest\testcases\kernel</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>0</RepFail>
<useFile>0</useFile>
<TextAddressRange></TextAddressRange>
<DataAddressRange></DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\script\fsp.scat</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings>6319,6314</DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
</File>
<File>
<FileName>div0.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
</File>
<File>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
</File>
<File>
<FileName>cpuport.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
</File>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\misc\pin.c</FilePath>
</File>
<File>
<FileName>serial_v2.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\serial\serial_v2.c</FilePath>
</File>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\waitqueue.c</FilePath>
</File>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
</File>
<File>
<FileName>ringblk_buf.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath>
</File>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\pipe.c</FilePath>
</File>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
</File>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
</File>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\completion.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\drv_gpio.c</FilePath>
</File>
<File>
<FileName>drv_usart_v2.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\drv_usart_v2.c</FilePath>
</File>
<File>
<FileName>drv_common.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\drv_common.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\msh.c</FilePath>
</File>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\components.c</FilePath>
</File>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\irq.c</FilePath>
</File>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\object.c</FilePath>
</File>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\idle.c</FilePath>
</File>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\kservice.c</FilePath>
</File>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\clock.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\device.c</FilePath>
</File>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\scheduler.c</FilePath>
</File>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\thread.c</FilePath>
</File>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\mem.c</FilePath>
</File>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\ipc.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\timer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>libc</GroupName>
<Files>
<File>
<FileName>time.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\libc\compilers\common\time.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
<Files>
<File>
<FileName>hal_entry.c</FileName>
<FileType>1</FileType>
<FilePath>.\src\hal_entry.c</FilePath>
</File>
<File>
<FileName>SConscript</FileName>
<FileType>5</FileType>
<FilePath>.\src\SConscript</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::Flex Software</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<gpdscs>
<gpdsc name="buildinfo.gpdsc">
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</gpdsc>
</gpdscs>
<apis/>
<components>
<component Cclass="Flex Software" Cgroup="RA Configuration" Cvendor="Renesas" Cversion="1.0.0" condition="RA Device" generator="Renesas RA Smart Configurator">
<package name="RA_DFP" schemaVersion="1.6.0" url="https://www2.renesas.eu/Keil_MDK_Packs/" vendor="Renesas" version="3.1.0"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
</components>
<files/>
</RTE>
</Project>

32
bsp/ra6m4-cpk/ra/SConscript Normal file
View File

@ -0,0 +1,32 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
CPPDEFINES = ['SOC_R7FA6M4AF']
if rtconfig.CROSS_TOOL == 'iar':
print("\nThe current project does not support iar build\n")
Return('group')
elif rtconfig.CROSS_TOOL == 'gcc':
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
src += [cwd + '/fsp/src/r_ioport/r_ioport.c']
if GetDepend(['RT_USING_SERIAL']):
src += [cwd + '/fsp/src/r_sci_uart/r_sci_uart.c']
if GetDepend(['RT_USING_PIN']):
src += [cwd + '/fsp/src/r_icu/r_icu.c']
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
cwd + '/fsp/inc',
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')

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