From 90c69a0588090e181e4ce12767738b1853510d3f Mon Sep 17 00:00:00 2001 From: flyingcys Date: Sat, 22 Apr 2023 23:57:53 +0800 Subject: [PATCH] update bouffalo_lab libraries && script (#7349) --- bsp/bouffalo_lab/.gitignore | 4 +- bsp/bouffalo_lab/bl60x/combine.sh | 14 +- bsp/bouffalo_lab/bl61x/combine.sh | 18 +- bsp/bouffalo_lab/bl70x/combine.sh | 18 +- bsp/bouffalo_lab/bl808/lp/combine.sh | 18 +- bsp/bouffalo_lab/bl808/m0/combine.sh | 18 +- bsp/bouffalo_lab/bouffalo_flash_cube.sh | 12 +- .../bl_mcu_sdk/drivers/lhal/SConscript | 8 +- .../drivers/lhal/config/bl616/bl616_irq.h | 1 - .../lhal/config/bl616/bl616_memorymap.h | 2 +- .../drivers/lhal/config/bl616/device_table.c | 41 +- .../lhal/config/bl808/bl808_memorymap.h | 1 - .../lhal/include/arch/risc-v/t-head/rv_pmp.c | 20 +- .../drivers/lhal/include/bflb_acomp.h | 162 ++++ .../drivers/lhal/include/bflb_core.h | 9 +- .../drivers/lhal/include/bflb_dma.h | 8 - .../drivers/lhal/include/bflb_gpio.h | 22 - .../drivers/lhal/include/bflb_iso11898.h | 249 ------ .../drivers/lhal/include/bflb_mjpeg.h | 12 + .../drivers/lhal/include/bflb_pec_ip.h | 189 ----- .../drivers/lhal/include/bflb_platform_dma.h | 104 +++ .../drivers/lhal/include/bflb_rtc.h | 7 + .../drivers/lhal/include/bflb_spi.h | 9 + .../drivers/lhal/include/bflb_uart.h | 65 +- .../lhal/include/compiler/compiler_ld.h | 2 + .../drivers/lhal/include/hardware/acomp_reg.h | 84 ++ .../lhal/include/hardware/iso11898_reg.h | 310 -------- .../lhal/include/hardware/platform_dma_reg.h | 746 ++++++++++++++++++ .../drivers/lhal/include/hardware/rtc_reg.h | 13 +- .../bl_mcu_sdk/drivers/lhal/src/bflb_acomp.c | 318 ++++++++ .../bl_mcu_sdk/drivers/lhal/src/bflb_clock.c | 2 - .../bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c | 7 - .../bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c | 38 +- .../drivers/lhal/src/bflb_iso11898.c | 366 --------- .../bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c | 20 + .../drivers/lhal/src/bflb_platform_dma.c | 95 +++ .../bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c | 40 +- .../drivers/lhal/src/bflb_sec_trng.c | 2 +- .../bl_mcu_sdk/drivers/lhal/src/bflb_spi.c | 113 +++ .../bl_mcu_sdk/drivers/lhal/src/bflb_uart.c | 38 +- .../bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c | 15 + .../bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c | 46 +- .../drivers/lhal/src/flash/bflb_sf_ctrl.h | 2 + .../drivers/soc/bl602/std/include/bl602_pm.h | 2 + .../drivers/soc/bl602/std/src/bl602_hbn.c | 6 +- .../drivers/soc/bl602/std/src/bl602_pm.c | 609 ++++++++++++++ .../drivers/soc/bl602/std/startup/start.S | 4 +- .../soc/bl616/std/include/bl616_acomp.h | 214 ----- .../soc/bl616/std/include/bl616_clock.h | 44 +- .../drivers/soc/bl616/std/include/bl616_glb.h | 59 +- .../drivers/soc/bl616/std/include/bl616_pds.h | 2 +- .../drivers/soc/bl616/std/include/bl616_pm.h | 2 +- .../bl616/std/include/bl616_romdriver_e907.h | 5 +- .../soc/bl616/std/include/bl616_tzc_sec.h | 1 - .../soc/bl616/std/include/hardware/bl616.h | 3 +- .../soc/bl616/std/include/hardware/glb_reg.h | 18 - .../drivers/soc/bl616/std/src/bl616_clock.c | 35 - .../drivers/soc/bl616/std/src/bl616_glb.c | 54 -- .../drivers/soc/bl616/std/src/bl616_hbn.c | 2 +- .../drivers/soc/bl616/std/src/bl616_pm.c | 4 +- .../soc/bl616/std/src/bl616_romapi_e907.c | 7 - .../soc/bl616/std/src/bl616_romapi_patch.c | 42 - .../soc/bl616/std/src/bl616_romdriver_e907.c | 2 +- .../bl_mcu_sdk/drivers/soc/bl808/SConscript | 49 +- .../drivers/soc/bl808/std/include/bl808_glb.h | 4 +- .../soc/bl808/std/include/hardware/bl808.h | 1 - .../drivers/soc/bl808/std/src/bl808_clock.c | 4 +- .../drivers/soc/bl808/std/src/bl808_glb.c | 20 +- .../soc/bl808/std/src/bl808_psram_uhs.c | 5 +- .../drivers/soc/bl808/std/src/bl808_uhs_phy.c | 2 +- .../soc/bl808/std/startup/m0/interrupt.c | 6 +- .../bflb_tools/bflb_fw_post_proc/usage.txt | 17 - .../tools/bflb_tools/get_bflb_fw_post_proc.sh | 47 ++ .../bflb_tools/get_bouffalo_flash_cube.sh | 46 ++ 74 files changed, 2741 insertions(+), 1843 deletions(-) create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_acomp.h delete mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_iso11898.h delete mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pec_ip.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_platform_dma.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/acomp_reg.h delete mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/iso11898_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/platform_dma_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_acomp.c delete mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_iso11898.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_platform_dma.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_pm.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_pm.c delete mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_acomp.h delete mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc/usage.txt create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/get_bflb_fw_post_proc.sh create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/get_bouffalo_flash_cube.sh diff --git a/bsp/bouffalo_lab/.gitignore b/bsp/bouffalo_lab/.gitignore index 9b96be28e1..76aba406b5 100755 --- a/bsp/bouffalo_lab/.gitignore +++ b/bsp/bouffalo_lab/.gitignore @@ -5,4 +5,6 @@ *.asm *.exe *-ubuntu -*-macos \ No newline at end of file +*-macos +bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc +bl_mcu_sdk/tools/bflb_tools/bouffalo_flash_cube \ No newline at end of file diff --git a/bsp/bouffalo_lab/bl60x/combine.sh b/bsp/bouffalo_lab/bl60x/combine.sh index 198f6dccf2..c79554fcee 100755 --- a/bsp/bouffalo_lab/bl60x/combine.sh +++ b/bsp/bouffalo_lab/bl60x/combine.sh @@ -8,28 +8,24 @@ SYSTEM=`uname -s` echo "system: $SYSTEM" CONFIG=./board/config -TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc +TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools if [ $SYSTEM = "Darwin" ] then TOOL_NAME=bflb_fw_post_proc-macos - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos elif [ $SYSTEM = "Linux" ] then TOOL_NAME=bflb_fw_post_proc-ubuntu - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu else TOOL_NAME=bflb_fw_post_proc.exe - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe fi -if [ -f "$TOOL_DIR/$TOOL_NAME" ] +if [ -f "$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME" ] then echo "bflb_fw_post_proc exist" else - echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR" - curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME - chmod +x $TOOL_DIR/$TOOL_NAME + echo "bflb_fw_post_proc not exist, try download... " + ./$TOOL_DIR/get_bflb_fw_post_proc.sh fi -./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file +./$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file diff --git a/bsp/bouffalo_lab/bl61x/combine.sh b/bsp/bouffalo_lab/bl61x/combine.sh index 11a925dff0..c79554fcee 100755 --- a/bsp/bouffalo_lab/bl61x/combine.sh +++ b/bsp/bouffalo_lab/bl61x/combine.sh @@ -8,32 +8,24 @@ SYSTEM=`uname -s` echo "system: $SYSTEM" CONFIG=./board/config -TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc +TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools if [ $SYSTEM = "Darwin" ] then TOOL_NAME=bflb_fw_post_proc-macos - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos elif [ $SYSTEM = "Linux" ] then TOOL_NAME=bflb_fw_post_proc-ubuntu - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu else TOOL_NAME=bflb_fw_post_proc.exe - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe fi -if [ -f "$TOOL_DIR/$TOOL_NAME" ] +if [ -f "$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME" ] then echo "bflb_fw_post_proc exist" else - echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR" - curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME - if [ $SYSTEM = "Darwin" ]; then - chmod +x $TOOL_DIR/$TOOL_NAME - elif [ $SYSTEM = "Linux" ]; then - chmod +x $TOOL_DIR/$TOOL_NAME - fi + echo "bflb_fw_post_proc not exist, try download... " + ./$TOOL_DIR/get_bflb_fw_post_proc.sh fi -./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file +./$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file diff --git a/bsp/bouffalo_lab/bl70x/combine.sh b/bsp/bouffalo_lab/bl70x/combine.sh index 11a925dff0..c79554fcee 100755 --- a/bsp/bouffalo_lab/bl70x/combine.sh +++ b/bsp/bouffalo_lab/bl70x/combine.sh @@ -8,32 +8,24 @@ SYSTEM=`uname -s` echo "system: $SYSTEM" CONFIG=./board/config -TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc +TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools if [ $SYSTEM = "Darwin" ] then TOOL_NAME=bflb_fw_post_proc-macos - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos elif [ $SYSTEM = "Linux" ] then TOOL_NAME=bflb_fw_post_proc-ubuntu - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu else TOOL_NAME=bflb_fw_post_proc.exe - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe fi -if [ -f "$TOOL_DIR/$TOOL_NAME" ] +if [ -f "$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME" ] then echo "bflb_fw_post_proc exist" else - echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR" - curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME - if [ $SYSTEM = "Darwin" ]; then - chmod +x $TOOL_DIR/$TOOL_NAME - elif [ $SYSTEM = "Linux" ]; then - chmod +x $TOOL_DIR/$TOOL_NAME - fi + echo "bflb_fw_post_proc not exist, try download... " + ./$TOOL_DIR/get_bflb_fw_post_proc.sh fi -./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file +./$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file diff --git a/bsp/bouffalo_lab/bl808/lp/combine.sh b/bsp/bouffalo_lab/bl808/lp/combine.sh index ee1436b881..388d20de0b 100755 --- a/bsp/bouffalo_lab/bl808/lp/combine.sh +++ b/bsp/bouffalo_lab/bl808/lp/combine.sh @@ -8,32 +8,24 @@ SYSTEM=`uname -s` echo "system: $SYSTEM" CONFIG=../config -TOOL_DIR=../../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc +TOOL_DIR=../../libraries/bl_mcu_sdk/tools/bflb_tools if [ $SYSTEM = "Darwin" ] then TOOL_NAME=bflb_fw_post_proc-macos - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos elif [ $SYSTEM = "Linux" ] then TOOL_NAME=bflb_fw_post_proc-ubuntu - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu else TOOL_NAME=bflb_fw_post_proc.exe - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe fi -if [ -f "$TOOL_DIR/$TOOL_NAME" ] +if [ -f "$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME" ] then echo "bflb_fw_post_proc exist" else - echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR" - curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME - if [ $SYSTEM = "Darwin" ]; then - chmod +x $TOOL_DIR/$TOOL_NAME - elif [ $SYSTEM = "Linux" ]; then - chmod +x $TOOL_DIR/$TOOL_NAME - fi + echo "bflb_fw_post_proc not exist, try download... " + ./$TOOL_DIR/get_bflb_fw_post_proc.sh fi -./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file +./$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file diff --git a/bsp/bouffalo_lab/bl808/m0/combine.sh b/bsp/bouffalo_lab/bl808/m0/combine.sh index ee1436b881..388d20de0b 100755 --- a/bsp/bouffalo_lab/bl808/m0/combine.sh +++ b/bsp/bouffalo_lab/bl808/m0/combine.sh @@ -8,32 +8,24 @@ SYSTEM=`uname -s` echo "system: $SYSTEM" CONFIG=../config -TOOL_DIR=../../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc +TOOL_DIR=../../libraries/bl_mcu_sdk/tools/bflb_tools if [ $SYSTEM = "Darwin" ] then TOOL_NAME=bflb_fw_post_proc-macos - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos elif [ $SYSTEM = "Linux" ] then TOOL_NAME=bflb_fw_post_proc-ubuntu - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu else TOOL_NAME=bflb_fw_post_proc.exe - TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe fi -if [ -f "$TOOL_DIR/$TOOL_NAME" ] +if [ -f "$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME" ] then echo "bflb_fw_post_proc exist" else - echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR" - curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME - if [ $SYSTEM = "Darwin" ]; then - chmod +x $TOOL_DIR/$TOOL_NAME - elif [ $SYSTEM = "Linux" ]; then - chmod +x $TOOL_DIR/$TOOL_NAME - fi + echo "bflb_fw_post_proc not exist, try download... " + ./$TOOL_DIR/get_bflb_fw_post_proc.sh fi -./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file +./$TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE \ No newline at end of file diff --git a/bsp/bouffalo_lab/bouffalo_flash_cube.sh b/bsp/bouffalo_lab/bouffalo_flash_cube.sh index 07c7974681..5ddc73f039 100755 --- a/bsp/bouffalo_lab/bouffalo_flash_cube.sh +++ b/bsp/bouffalo_lab/bouffalo_flash_cube.sh @@ -35,8 +35,16 @@ else echo "chip name error" fi -TOOL_DIR=./libraries/bl_mcu_sdk/tools/bflb_tools/bouffalo_flash_cube +TOOL_DIR=./libraries/bl_mcu_sdk/tools/bflb_tools TOOL_NAME='BLFlashCommand'$TOOL_SUFFIX CONFIG_FILE=$CONFIG_DIR'/flash_prog_cfg.ini' -./$TOOL_DIR/$TOOL_NAME --interface=uart --baudrate=2000000 --chipname=$CHIPNAME --config=$CONFIG_FILE --port=$PORT +if [ -f "$TOOL_DIR/bouffalo_flash_cube/$TOOL_NAME" ] +then + echo "bouffalo_flash_cube exist" +else + echo "bouffalo_flash_cube not exist, try download... " + ./$TOOL_DIR/get_bouffalo_flash_cube.sh +fi + +./$TOOL_DIR/bouffalo_flash_cube/$TOOL_NAME --interface=uart --baudrate=2000000 --chipname=$CHIPNAME --config=$CONFIG_FILE --port=$PORT diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/SConscript index f9dc4f5d67..ce0285bb0e 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/SConscript +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/SConscript @@ -31,11 +31,13 @@ src = Split(""" src/flash/bflb_xip_sflash.c src/flash/bflb_sflash.c src/flash/bflb_sf_ctrl.c - src/bflb_irq.c src/bflb_l1c.c src/bflb_mtimer.c """) +if not GetDepend('BL808_CORE_D0'): + src += ['src/bflb_irq.c'] + if not GetDepend('BSP_USING_ROMAPI'): src += ['src/bflb_common.c'] else: @@ -50,9 +52,9 @@ if GetDepend('BSP_USING_BL61X'): src/bflb_mjpeg.c src/bflb_pwm_v2.c src/bflb_cam.c - src/bflb_iso11898.c src/bflb_i2s.c src/bflb_common.c + src/bflb_platform_dma.c include/arch/risc-v/t-head/rv_hart.c include/arch/risc-v/t-head/rv_pmp.c """) @@ -93,7 +95,6 @@ elif GetDepend('BSP_USING_BL628'): src/bflb_emac.c src/bflb_clock.c src/bflb_pwm_v2.c - src/bflb_iso11898.c include/arch/risc-v/t-head/rv_hart.c include/arch/risc-v/t-head/rv_pmp.c """) @@ -106,7 +107,6 @@ elif GetDepend('BSP_USING_BL808'): src/bflb_mjpeg.c src/bflb_pwm_v2.c src/bflb_cam.c - src/bflb_iso11898.c src/bflb_csi.c src/bflb_i2s.c include/arch/risc-v/t-head/rv_hart.c diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_irq.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_irq.h index 869a2fd128..9ab66c51eb 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_irq.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_irq.h @@ -52,7 +52,6 @@ #define BL616_IRQ_SPI0 (BL616_IRQ_NUM_BASE + 27) #define BL616_IRQ_UART0 (BL616_IRQ_NUM_BASE + 28) #define BL616_IRQ_UART1 (BL616_IRQ_NUM_BASE + 29) -#define BL616_IRQ_ISO11898 (BL616_IRQ_NUM_BASE + 30) #define BL616_IRQ_GPIO_DMA (BL616_IRQ_NUM_BASE + 31) #define BL616_IRQ_I2C0 (BL616_IRQ_NUM_BASE + 32) #define BL616_IRQ_PWM (BL616_IRQ_NUM_BASE + 33) diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_memorymap.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_memorymap.h index d22c1b6cad..8513784863 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_memorymap.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_memorymap.h @@ -80,7 +80,6 @@ #define CKS_BASE ((uint32_t)0x2000a700) #define DBI_BASE ((uint32_t)0x2000a800) #define I2C1_BASE ((uint32_t)0x2000a900) -#define ISO11898_BASE ((uint32_t)0x2000aa00) #define I2S_BASE ((uint32_t)0x2000ab00) #define AUADC_BASE ((uint32_t)0x2000ac00) #define QSPI_BASE ((uint32_t)0x2000b000) @@ -104,5 +103,6 @@ #define EMAC_BASE ((uint32_t)0x20070000) #define USB_BASE ((uint32_t)0x20072000) #define HBN_RAM_BASE ((uint32_t)0x20010000) +#define PLFM_DMA_BASE ((uint32_t)0x24A00000) #endif \ No newline at end of file diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/device_table.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/device_table.c index c972011ae7..3715307b82 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/device_table.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/device_table.c @@ -45,12 +45,6 @@ struct bflb_device_s bl616_device_table[] = { .idx = 1, .dev_type = BFLB_DEVICE_TYPE_UART, .user_data = NULL }, - { .name = "iso11898", - .reg_base = ISO11898_BASE, - .irq_num = BL616_IRQ_ISO11898, - .idx = 0, - .dev_type = BFLB_DEVICE_TYPE_ISO11898, - .user_data = NULL }, { .name = "spi0", .reg_base = SPI_BASE, .irq_num = BL616_IRQ_SPI0, @@ -260,6 +254,41 @@ struct bflb_device_s bl616_device_table[] = { .sub_idx = 0, .dev_type = BFLB_DEVICE_TYPE_DBI, .user_data = NULL }, + { .name = "plfm_dma_ch0", + .reg_base = PLFM_DMA_BASE, + .irq_num = 0, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PLFMDMA, + .user_data = NULL }, + { .name = "plfm_dma_ch1", + .reg_base = PLFM_DMA_BASE, + .irq_num = 0, + .idx = 1, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PLFMDMA, + .user_data = NULL }, + { .name = "plfm_dma_ch2", + .reg_base = PLFM_DMA_BASE, + .irq_num = 0, + .idx = 2, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PLFMDMA, + .user_data = NULL }, + { .name = "plfm_dma_ch3", + .reg_base = PLFM_DMA_BASE, + .irq_num = 0, + .idx = 3, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PLFMDMA, + .user_data = NULL }, + { .name = "plfm_dma_ch4", + .reg_base = PLFM_DMA_BASE, + .irq_num = 0, + .idx = 4, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PLFMDMA, + .user_data = NULL }, }; struct bflb_device_s *bflb_device_get_by_name(const char *name) diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_memorymap.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_memorymap.h index 03585b85bd..77f7bfd0e4 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_memorymap.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_memorymap.h @@ -85,7 +85,6 @@ #define IPC1_BASE ((uint32_t)0x2000a840) #define I2C1_BASE ((uint32_t)0x2000a900) #define UART2_BASE ((uint32_t)0x2000aa00) -#define ISO11898_BASE ((uint32_t)0x2000aa00) #define I2S_BASE ((uint32_t)0x2000ab00) #define PDM0_BASE ((uint32_t)0x2000a000) #define LZ4D_BASE ((uint32_t)0x2000ad00) diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c index 0e9b3f77ea..033e9c18a1 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c @@ -13,7 +13,7 @@ static void rvpmp_reg_write(uintptr_t i, uintptr_t attr, uintptr_t pa) : : "r"(pa)); break; - +#ifndef CONIFG_DISABLE_ALL_PMP_EXCEPT_PMPADDR0 case 1: __asm volatile("csrw pmpaddr1, %0" : @@ -103,7 +103,7 @@ static void rvpmp_reg_write(uintptr_t i, uintptr_t attr, uintptr_t pa) : : "r"(pa)); break; - +#endif default: break; } @@ -121,7 +121,7 @@ static void rvpmp_reg_write(uintptr_t i, uintptr_t attr, uintptr_t pa) : : "r"(cfg)); break; - +#ifndef CONIFG_DISABLE_ALL_PMP_EXCEPT_PMPADDR0 case 4 ... 7: __asm volatile("csrr %0, pmpcfg1" : "=r"(cfg)); @@ -154,7 +154,7 @@ static void rvpmp_reg_write(uintptr_t i, uintptr_t attr, uintptr_t pa) : : "r"(cfg)); break; - +#endif default: break; } @@ -172,7 +172,7 @@ static void rvpmp_reg_write(uintptr_t i, uintptr_t attr, uintptr_t pa) : : "r"(cfg)); break; - +#ifndef CONIFG_DISABLE_ALL_PMP_EXCEPT_PMPADDR0 case 8 ... 15: __asm volatile("csrr %0, pmpcfg2" : "=r"(cfg)); @@ -183,7 +183,7 @@ static void rvpmp_reg_write(uintptr_t i, uintptr_t attr, uintptr_t pa) : : "r"(cfg)); break; - +#endif default: break; } @@ -205,7 +205,7 @@ static uint32_t pmp_get_config(uintptr_t e) __asm volatile("csrr %0, pmpcfg0" : "=r"(cfg)); break; - +#ifndef CONIFG_DISABLE_ALL_PMP_EXCEPT_PMPADDR0 case 4 ... 7: __asm volatile("csrr %0, pmpcfg1" : "=r"(cfg)); @@ -220,7 +220,7 @@ static uint32_t pmp_get_config(uintptr_t e) __asm volatile("csrr %0, pmpcfg3" : "=r"(cfg)); break; - +#endif default: break; } @@ -232,12 +232,12 @@ static uint32_t pmp_get_config(uintptr_t e) __asm volatile("csrr %0, pmpcfg0" : "=r"(cfg)); break; - +#ifndef CONIFG_DISABLE_ALL_PMP_EXCEPT_PMPADDR0 case 8 ... 15: __asm volatile("csrr %0, pmpcfg2" : "=r"(cfg)); break; - +#endif default: break; } diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_acomp.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_acomp.h new file mode 100755 index 0000000000..029e3d96c1 --- /dev/null +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_acomp.h @@ -0,0 +1,162 @@ +#ifndef _BFLB_ACOMP_H +#define _BFLB_ACOMP_H + +#include "bflb_core.h" + +/** @addtogroup LHAL + * @{ + */ + +/** @addtogroup ACOMP + * @{ + */ + +/** @defgroup Analog compare id type definition + * @{ + */ +#define AON_ACOMP0_ID 0 +#define AON_ACOMP1_ID 1 + + +/** @defgroup Analog compare scaling factor type definition + * @{ + */ +#define AON_ACOMP_SCALING_FACTOR_0P25 0x00 /*!< Analog compare level scaling factor 0.25 */ +#define AON_ACOMP_SCALING_FACTOR_0P5 0x10 /*!< Analog compare level scaling factor 0.5 */ +#define AON_ACOMP_SCALING_FACTOR_0P75 0x20 /*!< Analog compare level scaling factor 0.75 */ +#define AON_ACOMP_SCALING_FACTOR_1 0x30 /*!< Analog compare level scaling factor 1 */ + +/** + * @brief Analog compare channel type definition + */ +#define AON_ACOMP_CHAN_ADC0 0 /*!< Analog compare channel,ADC input channel 0 */ +#define AON_ACOMP_CHAN_ADC1 1 /*!< Analog compare channel,ADC input channel 1 */ +#define AON_ACOMP_CHAN_ADC2 2 /*!< Analog compare channel,ADC input channel 2 */ +#define AON_ACOMP_CHAN_ADC3 3 /*!< Analog compare channel,ADC input channel 3 */ +#define AON_ACOMP_CHAN_ADC4 4 /*!< Analog compare channel,ADC input channel 4 */ +#define AON_ACOMP_CHAN_ADC5 5 /*!< Analog compare channel,ADC input channel 5 */ +#define AON_ACOMP_CHAN_ADC6 6 /*!< Analog compare channel,ADC input channel 6 */ +#define AON_ACOMP_CHAN_ADC7 7 /*!< Analog compare channel,ADC input channel 7 */ +#define AON_ACOMP_CHAN_DACA 8 /*!< Analog compare channel,DAC output channel A */ +#define AON_ACOMP_CHAN_DACB 9 /*!< Analog compare channel,DAC output channel B */ +#define AON_ACOMP_CHAN_VREF_1P25V 10 /*!< Analog compare channel,1.25V ref voltage */ +#define AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_1 11 /*!< Analog compare channel,first,VIO * scaling factor */ +#define AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_2 12 /*!< Analog compare channel,second,VIO * scaling factor */ +#define AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_3 13 /*!< Analog compare channel,third,VIO * scaling factor */ +#define AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_4 14 /*!< Analog compare channel,forth,VIO * scaling factor */ +#define AON_ACOMP_CHAN_VSS 15 /*!< Analog compare channel,vss */ + +/** + * @brief Analog compare bias current control type definition + */ +#define AON_ACOMP_BIAS_POWER_MODE1 0 /*!< Analog compare power mode 1,slow response mode */ +#define AON_ACOMP_BIAS_POWER_MODE2 1 /*!< Analog compare power mode 2,medium response mode */ +#define AON_ACOMP_BIAS_POWER_MODE3 2 /*!< Analog compare power mode 3,fast response mode */ +#define AON_ACOMP_BIAS_POWER_NONE 3 /*!< Analog compare power mode none */ + +/** + * @brief Analog compare hysteresis voltage type definition + */ +#define AON_ACOMP_HYSTERESIS_VOLT_NONE 0 /*!< Analog compare hysteresis voltage none */ +#define AON_ACOMP_HYSTERESIS_VOLT_10MV 1 /*!< Analog compare hysteresis voltage 10mv */ +#define AON_ACOMP_HYSTERESIS_VOLT_20MV 2 /*!< Analog compare hysteresis voltage 20mv */ +#define AON_ACOMP_HYSTERESIS_VOLT_30MV 3 /*!< Analog compare hysteresis voltage 30mv */ +#define AON_ACOMP_HYSTERESIS_VOLT_40MV 4 /*!< Analog compare hysteresis voltage 40mv */ +#define AON_ACOMP_HYSTERESIS_VOLT_50MV 5 /*!< Analog compare hysteresis voltage 50mv */ +#define AON_ACOMP_HYSTERESIS_VOLT_60MV 6 /*!< Analog compare hysteresis voltage 60mv */ +#define AON_ACOMP_HYSTERESIS_VOLT_70MV 7 /*!< Analog compare hysteresis voltage 70mv */ + + +/** + * @brief ACOMP configuration structure + * + * @param mux_en ACOMP mux enable + * @param pos_chan_sel ACOMP positive channel select + * @param neg_chan_sel ACOMP negtive channel select + * @param vio_sel ACOMP VIO voltage select, (vioSel/66)*avdd33 + * @param scaling_factor ACOMP scaling factor select factor + * @param bias_prog ACOMP bias current control + * @param hysteresis_pos_volt ACOMP hysteresis voltage for positive + * @param hysteresis_neg_volt ACOMP hysteresis voltage for negtive + */ +struct bflb_acomp_config_s { + uint8_t mux_en; + uint8_t pos_chan_sel; + uint8_t neg_chan_sel; + uint8_t vio_sel; + uint8_t scaling_factor; + uint8_t bias_prog; + uint8_t hysteresis_pos_volt; + uint8_t hysteresis_neg_volt; +}; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize acomp. + * + * @param [in] acomp_id acomp index + * @param [in] config pointer to save acomp configuration + */ +void bflb_acomp_init(uint8_t acomp_id, const struct bflb_acomp_config_s *config); + +/** + * @brief Enable acomp. + * + * @param [in] acomp_id acomp index + */ +void bflb_acomp_enable(uint8_t acomp_id); + +/** + * @brief Disable acomp. + * + * @param [in] acomp_id acomp index + */ +void bflb_acomp_disable(uint8_t acomp_id); + +/** + * @brief Get acomp result. + * + * @param [in] acomp_id acomp index + * @return acomp result + */ +uint32_t bflb_acomp_get_result(uint8_t acomp_id); + +/** + * @brief gpio change adc_chan_id. + * + * @param [in] pin gpio index + * @param [out] channel adc channel index + * @return Zero on success; a negated errno value on failure + */ +uint32_t bflb_acomp_gpio_2_chanid(uint32_t pin, uint32_t* channel); + +/** + * @brief adc_chan_id change gpio index. + * + * @param [in] channel adc channel index + * @param [out] pin gpio index + * @return Zero on success; a negated errno value on failure + */ +uint32_t bflb_acomp_chanid_2_gpio(uint32_t channel, uint32_t* pin); + + +#if 0 +/** + * @brief Get acomp postive input. + * + * @param [in] acomp_id acomp index + * @return acomp postive input + */ +uint32_t bflb_acomp_get_postive_input(uint8_t acomp_id); +#endif + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_core.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_core.h index 7c7da5536b..e68737b854 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_core.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_core.h @@ -59,7 +59,6 @@ void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *strin #define BFLB_DEVICE_TYPE_IR 10 #define BFLB_DEVICE_TYPE_TIMER 11 #define BFLB_DEVICE_TYPE_PWM 12 -#define BFLB_DEVICE_TYPE_ISO11898 13 #define BFLB_DEVICE_TYPE_CAMERA 14 #define BFLB_DEVICE_TYPE_FLASH 15 #define BFLB_DEVICE_TYPE_QSPI 16 @@ -83,11 +82,11 @@ void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *strin #define BFLB_DEVICE_TYPE_MJPEG 34 #define BFLB_DEVICE_TYPE_KYS 35 #define BFLB_DEVICE_TYPE_DBI 36 -#define BFLB_DEVICE_TYPE_PEC 37 -#define BFLB_DEVICE_TYPE_WDT 38 -#define BFLB_DEVICE_TYPE_EF_CTRL 39 +#define BFLB_DEVICE_TYPE_WDT 37 +#define BFLB_DEVICE_TYPE_EF_CTRL 38 +#define BFLB_DEVICE_TYPE_SDIO2 39 #define BFLB_DEVICE_TYPE_SDIO3 40 -#define BFLB_DEVICE_TYPE_SDIO2 41 +#define BFLB_DEVICE_TYPE_PLFMDMA 41 struct bflb_device_s { const char *name; diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dma.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dma.h index fb7aeed185..2a07c7c270 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dma.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dma.h @@ -156,14 +156,6 @@ #define DMA_REQUEST_I2S_TX 0x00000011 #define DMA_REQUEST_ADC 0x00000016 #define DMA_REQUEST_DAC 0x00000017 -#define DMA_REQUEST_PEC0_SM0_RX 0x00000018 -#define DMA_REQUEST_PEC0_SM1_RX 0x00000019 -#define DMA_REQUEST_PEC0_SM2_RX 0x0000001A -#define DMA_REQUEST_PEC0_SM3_RX 0x0000001B -#define DMA_REQUEST_PEC0_SM0_TX 0x0000001C -#define DMA_REQUEST_PEC0_SM1_TX 0x0000001D -#define DMA_REQUEST_PEC0_SM2_TX 0x0000001E -#define DMA_REQUEST_PEC0_SM3_TX 0x0000001F /** * @} diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_gpio.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_gpio.h index e4f410d83b..f8ca377c0a 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_gpio.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_gpio.h @@ -122,7 +122,6 @@ #define GPIO_FUNC_DBI_QSPI (24 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_AUDAC_PWM (25 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_JTAG (26 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_PEC (27 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT) #elif defined(BL606P) || defined(BL808) #define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT) @@ -160,7 +159,6 @@ #define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_DBI_B (22 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_DBI_C (23 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_PEC (27 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT) #endif @@ -233,17 +231,6 @@ * @} */ -/** @defgroup GPIO_ISO11898_FUNC gpio iso11898 function definition - * @{ - */ -#if defined(BL808) || defined(BL606P)|| defined(BL616)|| defined(BL628) -#define GPIO_ISO11898_FUNC_TX 10 -#define GPIO_ISO11898_FUNC_RX 11 -#endif -/** - * @} - */ - /** @defgroup GPIO_CMD gpio feature control cmd definition * @{ */ @@ -374,15 +361,6 @@ void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin); */ void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_func); -/** - * @brief Config gpio pin with iso11898 function. - * - * @param [in] dev device handle - * @param [in] pin gpio pin, use @ref GPIO_PIN - * @param [in] iso11898_func iso11898 function, use @ref GPIO_ISO11898_FUNC - */ -void bflb_gpio_iso11898_init(struct bflb_device_s *dev, uint8_t pin, uint8_t iso11898_func); - /** * @brief Control gpio feature. * diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_iso11898.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_iso11898.h deleted file mode 100755 index 2d7b683aaf..0000000000 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_iso11898.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef _BFLB_ISO11898_H -#define _BFLB_ISO11898_H - -#include "bflb_core.h" - -/** @addtogroup LHAL - * @{ - */ - -/** @addtogroup ISO11898 - * @{ - */ - -#define ISO11898_TIMEOUT (320 * 1000 * 1000) - -#define ISO11898_MODE_NORMAL 0 /*!< normal mode */ -#define ISO11898_MODE_LOOPBACK 1 /*!< loopback mode */ -#define ISO11898_MODE_SILENT 2 /*!< silent mode */ -#define ISO11898_MODE_SILENT_LOOPBACK 3 /*!< loopback combined with silent mode */ - -#define ISO11898_SAMPLE_SINGLE 0 /*!< the bus is sampled three times, recommended for low/medium speed buses */ -#define ISO11898_SAMPLE_TRIPLE 1 /*!< the bus is sampled once, recommended for high speed buses */ - -#define ISO11898_SJW_1TQ 0 /*!< 1 time quantum */ -#define ISO11898_SJW_2TQ 1 /*!< 2 time quantum */ -#define ISO11898_SJW_3TQ 2 /*!< 3 time quantum */ -#define ISO11898_SJW_4TQ 3 /*!< 4 time quantum */ - -#define ISO11898_BS1_1TQ 0 /*!< 1 time quantum */ -#define ISO11898_BS1_2TQ 1 /*!< 2 time quantum */ -#define ISO11898_BS1_3TQ 2 /*!< 3 time quantum */ -#define ISO11898_BS1_4TQ 3 /*!< 4 time quantum */ -#define ISO11898_BS1_5TQ 4 /*!< 5 time quantum */ -#define ISO11898_BS1_6TQ 5 /*!< 6 time quantum */ -#define ISO11898_BS1_7TQ 6 /*!< 7 time quantum */ -#define ISO11898_BS1_8TQ 7 /*!< 8 time quantum */ -#define ISO11898_BS1_9TQ 8 /*!< 9 time quantum */ -#define ISO11898_BS1_10TQ 9 /*!< 10 time quantum */ -#define ISO11898_BS1_11TQ 10 /*!< 11 time quantum */ -#define ISO11898_BS1_12TQ 11 /*!< 12 time quantum */ -#define ISO11898_BS1_13TQ 12 /*!< 13 time quantum */ -#define ISO11898_BS1_14TQ 13 /*!< 14 time quantum */ -#define ISO11898_BS1_15TQ 14 /*!< 15 time quantum */ -#define ISO11898_BS1_16TQ 15 /*!< 16 time quantum */ - -#define ISO11898_BS2_1TQ 0 /*!< 1 time quantum */ -#define ISO11898_BS2_2TQ 1 /*!< 2 time quantum */ -#define ISO11898_BS2_3TQ 2 /*!< 3 time quantum */ -#define ISO11898_BS2_4TQ 3 /*!< 4 time quantum */ -#define ISO11898_BS2_5TQ 4 /*!< 5 time quantum */ -#define ISO11898_BS2_6TQ 5 /*!< 6 time quantum */ -#define ISO11898_BS2_7TQ 6 /*!< 7 time quantum */ -#define ISO11898_BS2_8TQ 7 /*!< 8 time quantum */ - -#define ISO11898_ID_STANDARD 0 /*!< standard ID */ -#define ISO11898_ID_EXTENDED 1 /*!< extended ID */ - -#define ISO11898_RTR_DATA 0 /*!< data frame */ -#define ISO11898_RTR_REMOTE 1 /*!< remote frame */ - -/** @defgroup ISO11898_INTSTS iso11898 interrupt status definition - * @{ - */ -#define ISO11898_INTSTS_RX (1 << 0) -#define ISO11898_INTSTS_TX (1 << 1) -#define ISO11898_INTSTS_ERROR_WARNING (1 << 2) -#define ISO11898_INTSTS_DATA_OVERRUN (1 << 3) -#define ISO11898_INTSTS_ERROR_PASSIVE (1 << 5) -#define ISO11898_INTSTS_ARBITRATION_LOST (1 << 6) -#define ISO11898_INTSTS_BUS_ERROR (1 << 7) -/** - * @} - */ - -#define ISO11898_STATUS_RX_NOT_EMPTY (1 << 0) -#define ISO11898_STATUS_RX_OVERRUN (1 << 1) -#define ISO11898_STATUS_TX_AVAILABLE (1 << 2) -#define ISO11898_STATUS_TX_COMPLETE (1 << 3) -#define ISO11898_STATUS_RX_RECEIVING (1 << 4) -#define ISO11898_STATUS_TX_SENDING (1 << 5) -#define ISO11898_STATUS_ERROR_COUNTER (1 << 6) -#define ISO11898_STATUS_BUS_OFF (1 << 7) - -#define ISO11898_FILTER_TYPE_SINGLE 0 -#define ISO11898_FILTER_TYPE_DUAL 1 - -struct bflb_iso11898_config_s { - uint8_t prescaler; /*!< specifies the length of a time quantum, ranges from 1 to 63, tq=tclk*2*(prescaler+1) */ - uint8_t mode; /*!< specifies the CAN operating mode. @ref ISO11898_MODE_XXX */ - uint8_t sample; /*!< specifies the number of sample times. @ref ISO11898_SAMPLE_XXX */ - uint8_t sjw; /*!< specifies the maximum number of time quanta the ISO11898 hardware is allowed to lengthen or shorten a bit to perform resynchronization. @ref ISO11898_SJW_XXX */ - uint8_t bs1; /*!< specifies the number of time quanta in Bit Segment 1. @ref ISO11898_BS1_XXX */ - uint8_t bs2; /*!< specifies the number of time quanta in Bit Segment 2. @ref ISO11898_BS2_XXX */ -}; - -struct bflb_iso11898_msg_s { - uint32_t std_id; /*!< specifies the standard identifier, this parameter can be a value between 0 to 0x7FF */ - uint32_t ext_id; /*!< specifies the extended identifier, this parameter can be a value between 0 to 0x1FFFFFFF */ - uint8_t id_type; /*!< specifies the type of identifier for the message that will be send or received. @ref ISO11898_ID_XXX */ - uint8_t rtr; /*!< specifies the type of frame for the message that will be send or received, @ref ISO11898_RTR_XXX */ - uint8_t dlc; /*!< specifies the length of the frame that will be send or received, this parameter can be a value between 0 to 8 */ - uint8_t data[8]; /*!< contains the data to be send or received, it ranges from 0 to 0xFF */ -}; - -struct bflb_iso11898_filter_s { - uint8_t filter_type; - uint8_t code0; - uint8_t code1; - uint8_t code2; - uint8_t code3; - uint8_t mask0; - uint8_t mask1; - uint8_t mask2; - uint8_t mask3; -}; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief - * - * @param [in] dev - * @param [in] config - */ -void bflb_iso11898_init(struct bflb_device_s *dev, struct bflb_iso11898_config_s *config); - -/** - * @brief - * - * @param [in] dev - */ -void bflb_iso11898_deinit(struct bflb_device_s *dev); - -/** - * @brief - * - * @param [in] dev - */ -void bflb_iso11898_abort_send(struct bflb_device_s *dev); - -/** - * @brief - * - * @param [in] dev - * @param [in] msg - * @param [in] timeout - * @return int8_t - */ -int8_t bflb_iso11898_send(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout); - -/** - * @brief - * - * @param [in] dev - * @param [in] msg - * @param [in] timeout - * @return int8_t - */ -int8_t bflb_iso11898_recv(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout); - -/** - * @brief - * - * @param [in] dev - * @param [in] mode - */ -void bflb_iso11898_set_mode(struct bflb_device_s *dev, uint8_t mode); - -/** - * @brief - * - * @param [in] dev - * @return uint8_t - */ -uint8_t bflb_iso11898_get_status(struct bflb_device_s *dev); - -/** - * @brief - * - * @param [in] dev - * @return uint8_t - */ -uint8_t bflb_iso11898_get_mode(struct bflb_device_s *dev); - -/** - * @brief - * - * @param [in] dev - * @param [in] filter - */ -void bflb_iso11898_set_filter(struct bflb_device_s *dev, struct bflb_iso11898_filter_s *filter); - -/** - * @brief - * - * @param [in] dev - * @param [in] mask - */ -void bflb_iso11898_txint_mask(struct bflb_device_s *dev, bool mask); - -/** - * @brief - * - * @param [in] dev - * @param [in] mask - */ -void bflb_iso11898_rxint_mask(struct bflb_device_s *dev, bool mask); - -/** - * @brief - * - * @param [in] dev - * @param [in] mask - */ -void bflb_iso11898_errint_mask(struct bflb_device_s *dev, bool mask); - -/** - * @brief - * - * @param [in] dev - * @return uint32_t - */ -uint32_t bflb_iso11898_get_int_status(struct bflb_device_s *dev); - -/** - * @brief - * - * @param [in] dev - * @param [in] cmd - * @param [in] arg - * @return int - */ -int bflb_iso11898_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -#endif diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mjpeg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mjpeg.h index 7cde648d49..a05996d8d4 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mjpeg.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mjpeg.h @@ -236,6 +236,18 @@ void bflb_mjpeg_set_yuv420sp_cam_input(struct bflb_device_s *dev, uint8_t yy, ui */ int bflb_mjpeg_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); +/** + * @brief Control mjpeg feature. + * + * @param [in] dev device handle + * @param [in] input_buf0 input buffer 0 + * @param [in] input_buf1 input buffer 1 + * @param [in] output_buff output buffer + * @param [in] output_buff_size size of output buffer + * @return A negated errno value on failure. + */ +void bflb_mjpeg_update_input_output_buff(struct bflb_device_s *dev, void *input_buf0, void *input_buf1, void *output_buff, size_t output_buff_size); + #ifdef __cplusplus } #endif diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pec_ip.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pec_ip.h deleted file mode 100755 index fcf1768df9..0000000000 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pec_ip.h +++ /dev/null @@ -1,189 +0,0 @@ -#ifndef __BFLB_PEC_IP_H__ -#define __BFLB_PEC_IP_H__ - -#include "bflb_core.h" - -#define PEC0 0 -#define PEC_MAX 1 - -#define PEC_SM0 0 -#define PEC_SM1 1 -#define PEC_SM2 2 -#define PEC_SM3 3 -#define PEC_SM_MAX 4 - -#define PEC_FLAG_0 (1 << 0) -#define PEC_FLAG_1 (1 << 1) -#define PEC_FLAG_2 (1 << 2) -#define PEC_FLAG_3 (1 << 3) -#define PEC_FLAG_4 (1 << 4) -#define PEC_FLAG_5 (1 << 5) -#define PEC_FLAG_6 (1 << 6) -#define PEC_FLAG_7 (1 << 7) - -#define PEC_IP_NULL 0 -#define PEC_IP_PWM 1 -#define PEC_IP_UART_TX 2 -#define PEC_IP_UART_RX 3 -#define PEC_IP_SPI 4 -#define PEC_IP_I2C 5 -#define PEC_IP_WS2812 6 -#define PEC_IP_JTAG 7 -#define PEC_IP_DPI 8 -#define PEC_IP_LA 9 -#define PEC_IP_SEG 10 -#define PEC_IP_DBI_B 11 -#define PEC_IP_4xI2S 12 - -#define PEC_ERR_OK 0 -#define PEC_ERR_NOT_SUPPORT 1 -#define PEC_ERR_PIN_CONFLICT 2 -#define PEC_ERR_SM_LACK 3 -#define PEC_ERR_CODE_SPACE_LACK 4 -#define PEC_ERR_FLAG_LACK 5 - -extern uint32_t bflb_pec_get_tx_fifo_addr(uint8_t pec_id, uint8_t sm_id); -extern uint32_t bflb_pec_get_rx_fifo_addr(uint8_t pec_id, uint8_t sm_id); -extern void bflb_pec_dma_tx_enable(uint8_t pec_id, uint8_t sm_id, uint8_t enable); -extern void bflb_pec_dma_rx_enable(uint8_t pec_id, uint8_t sm_id, uint8_t enable); - -struct bflb_pec_pwm_s { - uint32_t high_cnt; /*!< high level count */ - uint32_t low_cnt; /*!< low level count */ - uint16_t div; /*!< divisor */ - uint8_t pin; /*!< PWM output assert pin index */ - uint8_t pec; - uint8_t sm; - uint8_t addr; -}; - -int bflb_pec_pwm_init(struct bflb_pec_pwm_s *pwm); -void bflb_pec_pwm_start(struct bflb_pec_pwm_s *pwm); -void bflb_pec_pwm_stop(struct bflb_pec_pwm_s *pwm); - -struct bflb_pec_jtag_s { - uint8_t pin_tck; - uint8_t pin_tms; - uint8_t pin_tdo; - uint8_t pin_tdi; - uint8_t pec; - uint8_t sm; - uint8_t addr; -}; - -int bflb_pec_jtag_init(struct bflb_pec_jtag_s *jtag); -void bflb_pec_jtag_set_tck(struct bflb_pec_jtag_s *jtag, uint8_t value); -void bflb_pec_jtag_set_tms(struct bflb_pec_jtag_s *jtag, uint8_t value); -void bflb_pec_jtag_set_tdi(struct bflb_pec_jtag_s *jtag, uint8_t value); -int bflb_pec_jtag_get_tdo(struct bflb_pec_jtag_s *jtag); -void bflb_pec_jtag_set_path(struct bflb_pec_jtag_s *jtag, uint32_t path, uint32_t bits); -void bflb_pec_jtag_select_ir(struct bflb_pec_jtag_s *jtag); -void bflb_pec_jtag_exit_ir(struct bflb_pec_jtag_s *jtag); -void bflb_pec_jtag_select_dr(struct bflb_pec_jtag_s *jtag); -void bflb_pec_jtag_exit_dr(struct bflb_pec_jtag_s *jtag); -void bflb_pec_jtag_scan_ir(struct bflb_pec_jtag_s *jtag, uint8_t ir_bits, uint8_t *ir_out, uint8_t *ir_in); -void bflb_pec_jtag_scan_dr(struct bflb_pec_jtag_s *jtag, uint8_t dr_bits, uint8_t *dr_out, uint8_t *dr_in); -void bflb_pec_jtag_scan(struct bflb_pec_jtag_s *jtag, uint8_t ir_bits, uint8_t *ir_out, uint8_t *ir_in, uint8_t dr_bits, uint8_t *dr_out, uint8_t *dr_in); -void bflb_pec_jtag_write_ir(struct bflb_pec_jtag_s *jtag, uint8_t ir_bits, uint8_t *ir_out); -void bflb_pec_jtag_write_dr(struct bflb_pec_jtag_s *jtag, uint8_t dr_bits, uint8_t *dr_out); -void bflb_pec_jtag_read_dr(struct bflb_pec_jtag_s *jtag, uint8_t dr_bits, uint8_t *dr_in); - -/* pixel format */ -#define PEC_DBI_B_PIXEL_FORMAT_NRGB8888 1 /* 32-bit */ -#define PEC_DBI_B_PIXEL_FORMAT_NBGR8888 2 /* 32-bit */ -#define PEC_DBI_B_PIXEL_FORMAT_RGB888 3 /* 24-bit */ -#define PEC_DBI_B_PIXEL_FORMAT_BGR888 4 /* 24-bit */ -#define PEC_DBI_B_PIXEL_FORMAT_RGB565 5 /* 16-bit */ -#define PEC_DBI_B_PIXEL_FORMAT_BGR565 6 /* 16-bit */ - -/* transmit mode */ -#define PEC_DBI_TRANSMIT_MODE_CMD 0 -#define PEC_DBI_TRANSMIT_MODE_PIXEL 1 - -struct bflb_pec_dbi_b_s { - uint32_t clk_src; - uint32_t clk; - uint8_t pixel_format; - uint8_t pin_dc; - uint8_t pin_wr; - uint8_t pin_data; - uint8_t pec; - uint8_t sm; - uint8_t addr; - uint8_t fifo_threshold; -}; - -int bflb_pec_dbi_b_init(struct bflb_pec_dbi_b_s *dbi_b); -uint32_t bflb_pec_dbi_b_build_head(struct bflb_pec_dbi_b_s *dbi_b, uint8_t transmit_mode, uint8_t cmd, size_t data_num); -uint32_t bflb_pec_dbi_b_get_fifo_address(struct bflb_pec_dbi_b_s *dbi_b); -int bflb_pec_dbi_b_get_fifo_cnt(struct bflb_pec_dbi_b_s *dbi_b); -int bflb_pec_dbi_b_dma_enable(struct bflb_pec_dbi_b_s *dbi_b, bool en); - -/* Signal polarity selection */ -#define V_SYNC_SINGLE_POL 0 -#define H_SYNC_SINGLE_POL 0 -#define DE_SINGLE_POL 1 - -struct bflb_pec_dpi_s { - uint16_t width; - uint16_t height; - - uint16_t hsw; - uint16_t hbp; - uint16_t hfp; - - uint16_t vsw; - uint16_t vbp; - uint16_t vfp; - - bool data_latch_mode; - bool de_sig_enable; - bool de_sig_polarity; - bool v_sync_sig_polarity; - bool h_sync_sig_polarity; - - uint32_t *invalid_row_para; - - uint16_t frame_rate; - uint16_t data_format; - - uint8_t pin_clk; - uint8_t pin_hs; - uint8_t pin_data; - uint8_t pec; - uint8_t sm; -}; - -int bflb_pec_dpi_init(struct bflb_pec_dpi_s *dpi); - -#define PEC_I2S_SAMPLE_RATE_24KHZ 1 -#define PEC_I2S_SAMPLE_RATE_48KHZ 2 -#define PEC_I2S_SAMPLE_RATE_96KHZ 3 - -#define PEC_I2S_DATA_FORMAT_BIT24IN32R 0 -#define PEC_I2S_DATA_FORMAT_BIT16 1 -#define PEC_I2S_DATA_FORMAT_BIT32 2 - -struct bflb_pec_i2sx4_s { - uint8_t sample_rate; - uint8_t data_format; - uint8_t pin_bck; - uint8_t pin_ws; - uint8_t pin_d0; - uint8_t pin_d1; - uint8_t pin_d2; - uint8_t pin_d3; - uint8_t pec; - // uint8_t sm; - // uint8_t addr; - uint8_t flag; -}; - -int bflb_pec_i2sx4_init(struct bflb_pec_i2sx4_s *i2s); -void bflb_pec_i2sx4_enable(struct bflb_pec_i2sx4_s *i2s); -void bflb_pec_i2sx4_disable(struct bflb_pec_i2sx4_s *i2s); -void bflb_pec_i2sx4_rx_start(struct bflb_pec_i2sx4_s *i2s); -void bflb_pec_i2sx4_rx_stop(struct bflb_pec_i2sx4_s *i2s); -uint8_t bflb_pec_i2sx4_get_data(struct bflb_pec_i2sx4_s *i2s, uint8_t ch, uint32_t *data); - -#endif /* __BFLB_PEC_IP_H__ */ diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_platform_dma.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_platform_dma.h new file mode 100755 index 0000000000..2facd1299e --- /dev/null +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_platform_dma.h @@ -0,0 +1,104 @@ +#ifndef _BFLB_PLATFORM_DMA_H +#define _BFLB_PLATFORM_DMA_H + +#include "bflb_core.h" + +/** @addtogroup LHAL + * @{ + */ + +#define PLFM_DMA_CHANNEL_MAX 5 + +/** @addtogroup PLATFORM_DMA + * @{ + */ + +struct bflb_platform_dma_desc { + /** Application subsystem address which is used as source address for DMA payload + * transfer*/ + uint32_t src; + /** Points to the start of the embedded data buffer associated with this descriptor. + * This address acts as the destination address for the DMA payload transfer*/ + uint32_t dest; + /// Complete length of the buffer in memory + uint16_t length; + /// Control word for the DMA engine (e.g. for interrupt generation) + uint16_t ctrl; + /// Pointer to the next element of the chained list + uint32_t next; +}; + +/// Structure describing the DMA driver environment +struct bflb_platform_dma_env_tag { + /** last DMA descriptor pushed for each channel, can point to descriptor already + * deallocated, but then will not be use`d because root register will be NULL + */ + volatile struct bflb_platform_dma_desc *last_dma[PLFM_DMA_CHANNEL_MAX]; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + **************************************************************************************** + * @brief Initialize the bridge DMA registers + * + * @param [in] dev device handle + **************************************************************************************** + */ +void bflb_platform_dma_init(struct bflb_device_s *dev); + +/** + **************************************************************************************** + * @brief Chains a chained list of descriptors in the DMA + * + * @param [in] dev device handle + * @param [in] first First DMA descriptor of the list (filled by the caller) + * @param [in] last last DMA descriptor of the list (filled by the caller) + * + **************************************************************************************** + */ +void bflb_platform_dma_push(struct bflb_device_s *dev, struct bflb_platform_dma_desc *first, struct bflb_platform_dma_desc *last); + +/** + **************************************************************************************** + * @brief Interrupt service routine when a bus error is detected while in a DMA transfer. + * This error is considered as fatal and triggers a non-recoverable assertion. + * + * @param [in] dev device handle + **************************************************************************************** + */ +void bflb_platform_dma_buserr_isr(struct bflb_device_s *dev); + +/** + **************************************************************************************** + * @brief Active wait until DMA channel become inactive + * + * @param [in] dev device handle + **************************************************************************************** + */ +void bflb_platform_dma_wait_eot(struct bflb_device_s *dev); + +/** + **************************************************************************************** + * @brief Active wait until DMA channel become inactive + * + * @param [in] dev device handle + **************************************************************************************** + */ +void bflb_platform_dma_clear_eot(struct bflb_device_s *dev); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif \ No newline at end of file diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_rtc.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_rtc.h index a8fa56d74b..1a510c9acd 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_rtc.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_rtc.h @@ -18,6 +18,13 @@ extern "C" { #endif +/** + * @brief clear and disable rtc. + * + * @param [in] dev device handle + */ +void bflb_rtc_disable(struct bflb_device_s *dev); + /** * @brief Set rtc alarming time. * diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi.h index 237fbd6f9a..7d6ed80562 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi.h @@ -110,6 +110,15 @@ #define SPI_CMD_CLEAR_RX_FIFO (0x04) #define SPI_CMD_SET_CS_INTERVAL (0x05) #define SPI_CMD_RX_IGNORE (0x06) +#define SPI_CMD_SET_MODE (0x07) +#define SPI_CMD_GET_MODE (0x08) +#define SPI_CMD_SET_FREQ (0x09) +#define SPI_CMD_GET_FREQ (0x0A) +#define SPI_CMD_SET_BIT_ORDER (0x0B) +#define SPI_CMD_GET_BIT_ORDER (0x0C) +#define SPI_CMD_SET_BYTE_ORDER (0x0E) +#define SPI_CMD_GET_BYTE_ORDER (0x0F) + /** * @} */ diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_uart.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_uart.h index 555ef6ecfa..6970713282 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_uart.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_uart.h @@ -14,10 +14,10 @@ /** @defgroup UART_DIRECTION uart direction enable definition * @{ */ -#define UART_DIRECTION_TX (1 << 0) -#define UART_DIRECTION_RX (1 << 1) -#define UART_DIRECTION_TXRX (UART_DIRECTION_TX | UART_DIRECTION_RX) -#define UART_DIRECTION_MASK UART_DIRECTION_TXRX +#define UART_DIRECTION_TX (1 << 0) +#define UART_DIRECTION_RX (1 << 1) +#define UART_DIRECTION_TXRX (UART_DIRECTION_TX | UART_DIRECTION_RX) +#define UART_DIRECTION_MASK UART_DIRECTION_TXRX /** * @} */ @@ -25,10 +25,10 @@ /** @defgroup UART_DATABITS uart data bits definition * @{ */ -#define UART_DATA_BITS_5 0 -#define UART_DATA_BITS_6 1 -#define UART_DATA_BITS_7 2 -#define UART_DATA_BITS_8 3 +#define UART_DATA_BITS_5 0 +#define UART_DATA_BITS_6 1 +#define UART_DATA_BITS_7 2 +#define UART_DATA_BITS_8 3 /** * @} */ @@ -36,10 +36,10 @@ /** @defgroup UART_STOPBITS uart stop bits definition * @{ */ -#define UART_STOP_BITS_0_5 0 -#define UART_STOP_BITS_1 1 -#define UART_STOP_BITS_1_5 2 -#define UART_STOP_BITS_2 3 +#define UART_STOP_BITS_0_5 0 +#define UART_STOP_BITS_1 1 +#define UART_STOP_BITS_1_5 2 +#define UART_STOP_BITS_2 3 /** * @} */ @@ -47,11 +47,11 @@ /** @defgroup UART_PARITY uart parity definition * @{ */ -#define UART_PARITY_NONE 0 -#define UART_PARITY_ODD 1 -#define UART_PARITY_EVEN 2 -#define UART_PARITY_MARK 3 -#define UART_PARITY_SPACE 4 +#define UART_PARITY_NONE 0 +#define UART_PARITY_ODD 1 +#define UART_PARITY_EVEN 2 +#define UART_PARITY_MARK 3 +#define UART_PARITY_SPACE 4 /** * @} */ @@ -59,8 +59,8 @@ /** @defgroup UART_BITORDER uart bitorder definition * @{ */ -#define UART_LSB_FIRST 0 -#define UART_MSB_FIRST 1 +#define UART_LSB_FIRST 0 +#define UART_MSB_FIRST 1 /** * @} */ @@ -79,14 +79,14 @@ /** @defgroup UART_INTSTS uart interrupt status definition * @{ */ -#define UART_INTSTS_TX_END (1 << 0) -#define UART_INTSTS_RX_END (1 << 1) -#define UART_INTSTS_TX_FIFO (1 << 2) -#define UART_INTSTS_RX_FIFO (1 << 3) -#define UART_INTSTS_RTO (1 << 4) -#define UART_INTSTS_PCE (1 << 5) -#define UART_INTSTS_TX_FER (1 << 6) -#define UART_INTSTS_RX_FER (1 << 7) +#define UART_INTSTS_TX_END (1 << 0) +#define UART_INTSTS_RX_END (1 << 1) +#define UART_INTSTS_TX_FIFO (1 << 2) +#define UART_INTSTS_RX_FIFO (1 << 3) +#define UART_INTSTS_RTO (1 << 4) +#define UART_INTSTS_PCE (1 << 5) +#define UART_INTSTS_TX_FER (1 << 6) +#define UART_INTSTS_RX_FER (1 << 7) #if !defined(BL602) #define UART_INTSTS_RX_LSE (1 << 8) #endif @@ -136,7 +136,7 @@ #define UART_CMD_SET_BREAK_VALUE (0x0d) #define UART_CMD_SET_TX_LIN_VALUE (0x0e) #define UART_CMD_SET_RX_LIN_VALUE (0x0f) -#define UART_CMD_SET_TX_RX_EN (0x10) +#define UART_CMD_SET_GLITCH_VALUE (0x10) #define UART_CMD_SET_TX_RS485_EN (0x11) #define UART_CMD_SET_TX_RS485_POLARITY (0x12) #define UART_CMD_SET_ABR_ALLOWABLE_ERROR (0x13) @@ -150,12 +150,16 @@ #define UART_CMD_SET_TX_EN (0x21) #define UART_CMD_SET_BCR_END_INTERRUPT (0x22) #define UART_CMD_GET_BCR_COUNT (0x23) +#define UART_CMD_SET_CTS_EN (0x24) +#define UART_CMD_SET_TX_FIFO_THREHOLD (0x25) +#define UART_CMD_SET_RX_FIFO_THREHOLD (0x26) + /** * @} */ -#define UART_AUTO_BAUD_START 0 -#define UART_AUTO_BAUD_0X55 1 +#define UART_AUTO_BAUD_START 0 +#define UART_AUTO_BAUD_0X55 1 struct bflb_uart_ir_config_s { bool tx_en; @@ -342,7 +346,6 @@ uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev); */ void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear); - /** * @brief Control uart feature. * diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_ld.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_ld.h index 0ff7dd9890..f7da3aa85e 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_ld.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_ld.h @@ -11,6 +11,8 @@ #define ATTR_DTCM_SECTION __attribute__((section(".tcm_data"))) #define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code"))) #define ATTR_DMA_RAM_SECTION __attribute__((section(".system_ram"))) +#define ATTR_WIFI_RAM_SECTION __attribute__((section(".wifi_ram"))) +#define ATTR_NOINIT_PSRAM_SECTION __attribute__((section(".psram_noinit"))) #define ATTR_NOCACHE_RAM_SECTION __attribute__((section(".nocache_ram"))) #define ATTR_NOCACHE_NOINIT_RAM_SECTION __attribute__((section(".nocache_noinit_ram"))) #define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_ram_code"))) diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/acomp_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/acomp_reg.h new file mode 100755 index 0000000000..5e1f4c9dd2 --- /dev/null +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/acomp_reg.h @@ -0,0 +1,84 @@ +/** + ****************************************************************************** + * @file acomp_reg.h + * @version V1.0 + * @date 2023-03-07 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#ifndef __HARDWARE_ACOMP_H__ +#define __HARDWARE_ACOMP_H__ + +/**************************************************************************** + * Pre-processor Definitions +****************************************************************************/ + +/* Register offsets *********************************************************/ +/* aon base */ +#define AON_ACOMP_REG_ACOMP0_CTRL_OFFSET (0x900) /* acomp0_ctrl */ +#define AON_ACOMP_REG_ACOMP1_CTRL_OFFSET (0x904) /* acomp0_ctrl */ +#define AON_ACOMP_REG_ACOMP_CFG_OFFSET (0x908) /* acomp_ctrl */ + + +/* Register Bitfield definitions *****************************************************/ +/* 0x900 : acomp0_ctrl */ +/* 0x904 : acomp1_ctrl */ +#define AON_ACOMP_MUX_EN (1 << 26U) +#define AON_ACOMP_POS_SEL_SHIFT (22U) +#define AON_ACOMP_POS_SEL_MASK (0xf << AON_ACOMP_POS_SEL_SHIFT) +#define AON_ACOMP_NEG_SEL_SHIFT (18U) +#define AON_ACOMP_NEG_SEL_MASK (0xf << AON_ACOMP_NEG_SEL_SHIFT) +#define AON_ACOMP_LEVEL_SEL_SHIFT (12U) +#define AON_ACOMP_LEVEL_SEL_MASK (0x3f << AON_ACOMP_LEVEL_SEL_SHIFT) +#define AON_ACOMP_BIAS_PROG_SHIFT (10U) +#define AON_ACOMP_BIAS_PROG_MASK (0x3 << AON_ACOMP_BIAS_PROG_SHIFT) +#define AON_ACOMP_HYST_SELP_SHIFT (7U) +#define AON_ACOMP_HYST_SELP_MASK (0x7 << AON_ACOMP_HYST_SELP_SHIFT) +#define AON_ACOMP_HYST_SELN_SHIFT (4U) +#define AON_ACOMP_HYST_SELN_MASK (0x7 << AON_ACOMP_HYST_SELN_SHIFT) +#define AON_ACOMP_EN (1 << 0U) + +/* 0x908 : acomp_ctrl */ +#define AON_ACOMP_VREF_SEL_SHIFT (24U) +#define AON_ACOMP_VREF_SEL_MASK (0x3f << AON_ACOMP_VREF_SEL_SHIFT) +#define AON_ACOMP0_OUT_RAW_DATA_SHIFT (19U) +#define AON_ACOMP0_OUT_RAW_DATA_MASK (0x1 << AON_ACOMP0_OUT_RAW_DATA_SHIFT) +#define AON_ACOMP1_OUT_RAW_DATA_SHIFT (17U) +#define AON_ACOMP1_OUT_RAW_DATA_MASK (0x1 << AON_ACOMP1_OUT_RAW_DATA_SHIFT) +#define AON_ACOMP0_TEST_SEL_SHIFT (12U) +#define AON_ACOMP0_TEST_SEL_MASK (0x3 << AON_ACOMP0_TEST_SEL_SHIFT) +#define AON_ACOMP1_TEST_SEL_SHIFT (10U) +#define AON_ACOMP1_TEST_SEL_MASK (0x3 << AON_ACOMP1_TEST_SEL_SHIFT) +#define AON_ACOMP0_TEST_EN (1 << 9U) +#define AON_ACOMP1_TEST_EN (1 << 8U) +#define AON_ACOMP0_RSTN_ANA (1 << 1U) +#define AON_ACOMP1_RSTN_ANA (1 << 0U) +#endif diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/iso11898_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/iso11898_reg.h deleted file mode 100755 index 4b609c5977..0000000000 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/iso11898_reg.h +++ /dev/null @@ -1,310 +0,0 @@ -/** - ****************************************************************************** - * @file iso11898_reg.h - * @version V1.0 - * @date 2022-10-31 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __ISO11898_REG_H__ -#define __ISO11898_REG_H__ - -/**************************************************************************** - * Pre-processor Definitions -****************************************************************************/ - -/* Register offsets *********************************************************/ - -#define ISO11898_MODE_OFFSET (0x0)/* mode */ -#define ISO11898_COMMAND_OFFSET (0x4)/* command */ -#define ISO11898_STATUS_OFFSET (0x8)/* status */ -#define ISO11898_INTERRUPT_OFFSET (0xc)/* interrupt */ -#define ISO11898_INTERRUPT_ENABLE_OFFSET (0x10)/* interrupt_enable */ -#define ISO11898_BUS_TIMING_0_OFFSET (0x18)/* bus_timing_0 */ -#define ISO11898_BUS_TIMING_1_OFFSET (0x1c)/* bus_timing_1 */ -#define ISO11898_ARB_LOST_CAPTURE_OFFSET (0x2c)/* arb_lost_capture */ -#define ISO11898_ERROR_CODE_CAPTURE_OFFSET (0x30)/* error_code_capture */ -#define ISO11898_ERROR_WARNING_LIMIT_OFFSET (0x34)/* error_warning_limit */ -#define ISO11898_RX_ERR_COUNT_OFFSET (0x38)/* rx_err_count */ -#define ISO11898_TX_ERR_COUNT_OFFSET (0x3c)/* tx_err_count */ -#define ISO11898_FRAME_INFORMATION_OFFSET (0x40)/* frame_information */ -#define ISO11898_ACCEPTANCE_CODE_0_OFFSET (0x40)/* acceptance_code_0 */ -#define ISO11898_SFF_ID1_OFFSET (0x44)/* sff_id1 */ -#define ISO11898_EFF_ID1_OFFSET (0x44)/* eff_id1 */ -#define ISO11898_ACCEPTANCE_CODE_1_OFFSET (0x44)/* acceptance_code_1 */ -#define ISO11898_SFF_ID2_OFFSET (0x48)/* sff_id2 */ -#define ISO11898_EFF_ID2_OFFSET (0x48)/* eff_id2 */ -#define ISO11898_ACCEPTANCE_CODE_2_OFFSET (0x48)/* acceptance_code_2 */ -#define ISO11898_SFF_DATA1_OFFSET (0x4c)/* sff_data1 */ -#define ISO11898_EFF_ID3_OFFSET (0x4c)/* eff_id3 */ -#define ISO11898_ACCEPTANCE_CODE_3_OFFSET (0x4c)/* acceptance_code_3 */ -#define ISO11898_SFF_DATA2_OFFSET (0x50)/* sff_data2 */ -#define ISO11898_EFF_ID4_OFFSET (0x50)/* eff_id4 */ -#define ISO11898_ACCEPTANCE_MASK_0_OFFSET (0x50)/* acceptance_mask_0 */ -#define ISO11898_SFF_DATA3_OFFSET (0x54)/* sff_data3 */ -#define ISO11898_EFF_DATA1_OFFSET (0x54)/* eff_data1 */ -#define ISO11898_ACCEPTANCE_MASK_1_OFFSET (0x54)/* acceptance_mask_1 */ -#define ISO11898_SFF_DATA4_OFFSET (0x58)/* sff_data4 */ -#define ISO11898_EFF_DATA2_OFFSET (0x58)/* eff_data2 */ -#define ISO11898_ACCEPTANCE_MASK_2_OFFSET (0x58)/* acceptance_mask_2 */ -#define ISO11898_SFF_DATA5_OFFSET (0x5c)/* sff_data5 */ -#define ISO11898_EFF_DATA3_OFFSET (0x5c)/* eff_data3 */ -#define ISO11898_ACCEPTANCE_MASK_3_OFFSET (0x5c)/* acceptance_mask_3 */ -#define ISO11898_SFF_DATA6_OFFSET (0x60)/* sff_data6 */ -#define ISO11898_EFF_DATA4_OFFSET (0x60)/* eff_data4 */ -#define ISO11898_SFF_DATA7_OFFSET (0x64)/* sff_data7 */ -#define ISO11898_EFF_DATA5_OFFSET (0x64)/* eff_data5 */ -#define ISO11898_SFF_DATA8_OFFSET (0x68)/* sff_data8 */ -#define ISO11898_EFF_DATA6_OFFSET (0x68)/* eff_data6 */ -#define ISO11898_EFF_DATA7_OFFSET (0x6c)/* eff_data7 */ -#define ISO11898_EFF_DATA8_OFFSET (0x70)/* eff_data8 */ -#define ISO11898_RX_MESSAGE_COUNT_OFFSET (0x74)/* rx_message_count */ -#define ISO11898_CLOCK_DIVIDER_OFFSET (0x7c)/* clock_divider */ - -/* Register Bitfield definitions *****************************************************/ - -/* 0x0 : mode */ -#define ISO11898_RESET_REQUEST (1<<0U) -#define ISO11898_LISTEN_ONLY (1<<1U) -#define ISO11898_SELF_TEST (1<<2U) -#define ISO11898_FILTER_TYPE (1<<3U) - -/* 0x4 : command */ -#define ISO11898_TRANSMIT_REQUEST (1<<0U) -#define ISO11898_ABORT_TRANSMISSION (1<<1U) -#define ISO11898_RELEASE_RECEIVE_BUFFER (1<<2U) -#define ISO11898_CLEAR_DATA_OVERRUN (1<<3U) -#define ISO11898_SELF_REQUEST (1<<4U) - -/* 0x8 : status */ -#define ISO11898_RECEIVE_BUFFER_STS (1<<0U) -#define ISO11898_DATA_OVERRUN_STS (1<<1U) -#define ISO11898_TRANSMIT_BUFFER_STS (1<<2U) -#define ISO11898_TRANSMIT_COMPLETE_STS (1<<3U) -#define ISO11898_RECEIVE_STS (1<<4U) -#define ISO11898_TRANSMIT_STS (1<<5U) -#define ISO11898_ERROR_STS (1<<6U) -#define ISO11898_BUS_STS (1<<7U) - -/* 0xc : interrupt */ -#define ISO11898_RECEIVE_INT (1<<0U) -#define ISO11898_TRANSMIT_INT (1<<1U) -#define ISO11898_ERROR_INT (1<<2U) -#define ISO11898_DATA_OVERRUN_INT (1<<3U) -#define ISO11898_ERROR_PASSIVE_INT (1<<5U) -#define ISO11898_ARB_LOST_INT (1<<6U) -#define ISO11898_BUS_ERROR_INT (1<<7U) - -/* 0x10 : interrupt_enable */ -#define ISO11898_RECEIVE_INT_EN (1<<0U) -#define ISO11898_TRANSMIT_INT_EN (1<<1U) -#define ISO11898_ERROR_INT_EN (1<<2U) -#define ISO11898_DATA_OVERRUN_INT_EN (1<<3U) -#define ISO11898_ERROR_PASSIVE_INT_EN (1<<5U) -#define ISO11898_ARB_LOST_INT_EN (1<<6U) -#define ISO11898_BUS_ERROR_INT_EN (1<<7U) - -/* 0x18 : bus_timing_0 */ -#define ISO11898_BAUD_RATE_PRESCALER_SHIFT (0U) -#define ISO11898_BAUD_RATE_PRESCALER_MASK (0x3f<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HARDWARE_PLATFORM_DMA_H__ +#define __HARDWARE_PLATFORM_DMA_H__ + +/** @brief Number of registers in the REG_DMA peripheral. + */ +#define REG_DMA_COUNT 49 + +/** @brief Decoding mask of the REG_DMA peripheral registers from the CPU point of view. + */ +#define REG_DMA_DECODING_MASK 0x000000FF + +/** + * @name CH_LLI_ROOT register definitions + * + * @{ + */ + +/// Address of the CH_LLI_ROOT register +//#define DMA_CH_LLI_ROOT_ADDR 0x24A00000 +/// Offset of the CH_LLI_ROOT register from the base address +#define DMA_CH_LLI_ROOT_OFFSET 0x00000000 +/// Index of the CH_LLI_ROOT register +#define DMA_CH_LLI_ROOT_INDEX 0x00000000 +/// Reset value of the CH_LLI_ROOT register +#define DMA_CH_LLI_ROOT_RESET 0x00000000 +/// Number of elements of the CH_LLI_ROOT register array +#define DMA_CH_LLI_ROOT_COUNT 4 + +/// @} + +/** + * @name DMA_STATUS register definitions + * + * + *
DMA_STATUS bitfields
Bits Field Name HW Access SW Access Reset Value + *
31 CH4_STOPPED W R 0 + *
30 MID_STREAM_BSY W R 0 + *
29 DOWN_STREAM_BSY W R 0 + *
28 UP_STREAM_BSY W R 0 + *
27 ARB_Q4_VALID W R 0 + *
26 ARB_Q3_VALID W R 0 + *
25 ARB_Q2_VALID W R 0 + *
24 ARB_Q1_VALID W R 0 + *
23 ARB_Q0_VALID W R 0 + *
22:20 REQUEST_STATE W R 0x0 + *
19 CH3_STOPPED W R 0 + *
18 CH2_STOPPED W R 0 + *
17 CH1_STOPPED W R 0 + *
16 CH0_STOPPED W R 0 + *
15:00 OFT_FREE W R 0x0 + *
+ * + * @{ + */ + +/// Address of the DMA_STATUS register +//#define DMA_DMA_STATUS_ADDR 0x24A00010 +/// Offset of the DMA_STATUS register from the base address +#define DMA_DMA_STATUS_OFFSET 0x00000010 +/// Index of the DMA_STATUS register +#define DMA_DMA_STATUS_INDEX 0x00000004 +/// Reset value of the DMA_STATUS register +#define DMA_DMA_STATUS_RESET 0x00000000 + +// field definitions +/// CH4_STOPPED field bit +#define DMA_CH4_STOPPED_BIT ((uint32_t)0x80000000) +/// CH4_STOPPED field position +#define DMA_CH4_STOPPED_POS 31 +/// MID_STREAM_BSY field bit +#define DMA_MID_STREAM_BSY_BIT ((uint32_t)0x40000000) +/// MID_STREAM_BSY field position +#define DMA_MID_STREAM_BSY_POS 30 +/// DOWN_STREAM_BSY field bit +#define DMA_DOWN_STREAM_BSY_BIT ((uint32_t)0x20000000) +/// DOWN_STREAM_BSY field position +#define DMA_DOWN_STREAM_BSY_POS 29 +/// UP_STREAM_BSY field bit +#define DMA_UP_STREAM_BSY_BIT ((uint32_t)0x10000000) +/// UP_STREAM_BSY field position +#define DMA_UP_STREAM_BSY_POS 28 +/// ARB_Q4_VALID field bit +#define DMA_ARB_Q4_VALID_BIT ((uint32_t)0x08000000) +/// ARB_Q4_VALID field position +#define DMA_ARB_Q4_VALID_POS 27 +/// ARB_Q3_VALID field bit +#define DMA_ARB_Q3_VALID_BIT ((uint32_t)0x04000000) +/// ARB_Q3_VALID field position +#define DMA_ARB_Q3_VALID_POS 26 +/// ARB_Q2_VALID field bit +#define DMA_ARB_Q2_VALID_BIT ((uint32_t)0x02000000) +/// ARB_Q2_VALID field position +#define DMA_ARB_Q2_VALID_POS 25 +/// ARB_Q1_VALID field bit +#define DMA_ARB_Q1_VALID_BIT ((uint32_t)0x01000000) +/// ARB_Q1_VALID field position +#define DMA_ARB_Q1_VALID_POS 24 +/// ARB_Q0_VALID field bit +#define DMA_ARB_Q0_VALID_BIT ((uint32_t)0x00800000) +/// ARB_Q0_VALID field position +#define DMA_ARB_Q0_VALID_POS 23 +/// REQUEST_STATE field mask +#define DMA_REQUEST_STATE_MASK ((uint32_t)0x00700000) +/// REQUEST_STATE field LSB position +#define DMA_REQUEST_STATE_LSB 20 +/// REQUEST_STATE field width +#define DMA_REQUEST_STATE_WIDTH ((uint32_t)0x00000003) +/// CH3_STOPPED field bit +#define DMA_CH3_STOPPED_BIT ((uint32_t)0x00080000) +/// CH3_STOPPED field position +#define DMA_CH3_STOPPED_POS 19 +/// CH2_STOPPED field bit +#define DMA_CH2_STOPPED_BIT ((uint32_t)0x00040000) +/// CH2_STOPPED field position +#define DMA_CH2_STOPPED_POS 18 +/// CH1_STOPPED field bit +#define DMA_CH1_STOPPED_BIT ((uint32_t)0x00020000) +/// CH1_STOPPED field position +#define DMA_CH1_STOPPED_POS 17 +/// CH0_STOPPED field bit +#define DMA_CH0_STOPPED_BIT ((uint32_t)0x00010000) +/// CH0_STOPPED field position +#define DMA_CH0_STOPPED_POS 16 +/// OFT_FREE field mask +#define DMA_OFT_FREE_MASK ((uint32_t)0x0000FFFF) +/// OFT_FREE field LSB position +#define DMA_OFT_FREE_LSB 0 +/// OFT_FREE field width +#define DMA_OFT_FREE_WIDTH ((uint32_t)0x00000010) + +/// CH4_STOPPED field reset value +#define DMA_CH4_STOPPED_RST 0x0 +/// MID_STREAM_BSY field reset value +#define DMA_MID_STREAM_BSY_RST 0x0 +/// DOWN_STREAM_BSY field reset value +#define DMA_DOWN_STREAM_BSY_RST 0x0 +/// UP_STREAM_BSY field reset value +#define DMA_UP_STREAM_BSY_RST 0x0 +/// ARB_Q4_VALID field reset value +#define DMA_ARB_Q4_VALID_RST 0x0 +/// ARB_Q3_VALID field reset value +#define DMA_ARB_Q3_VALID_RST 0x0 +/// ARB_Q2_VALID field reset value +#define DMA_ARB_Q2_VALID_RST 0x0 +/// ARB_Q1_VALID field reset value +#define DMA_ARB_Q1_VALID_RST 0x0 +/// ARB_Q0_VALID field reset value +#define DMA_ARB_Q0_VALID_RST 0x0 +/// REQUEST_STATE field reset value +#define DMA_REQUEST_STATE_RST 0x0 +/// CH3_STOPPED field reset value +#define DMA_CH3_STOPPED_RST 0x0 +/// CH2_STOPPED field reset value +#define DMA_CH2_STOPPED_RST 0x0 +/// CH1_STOPPED field reset value +#define DMA_CH1_STOPPED_RST 0x0 +/// CH0_STOPPED field reset value +#define DMA_CH0_STOPPED_RST 0x0 +/// OFT_FREE field reset value +#define DMA_OFT_FREE_RST 0x0 + +/// @} + +/** + * @name INT_RAWSTATUS register definitions + * + * + *
INT_RAWSTATUS bitfields
Bits Field Name HW Access SW Access Reset Value + *
24 CH4_EOT W R 0 + *
23 CH3_EOT W R 0 + *
22 CH2_EOT W R 0 + *
21 CH1_EOT W R 0 + *
20 CH0_EOT W R 0 + *
16 ERROR W R 0 + *
15:00 LLI_IRQ W R 0x0 + *
+ * + * @{ + */ + +/// Address of the INT_RAWSTATUS register +//#define DMA_INT_RAWSTATUS_ADDR 0x24A00014 +/// Offset of the INT_RAWSTATUS register from the base address +#define DMA_INT_RAWSTATUS_OFFSET 0x00000014 +/// Index of the INT_RAWSTATUS register +#define DMA_INT_RAWSTATUS_INDEX 0x00000005 +/// Reset value of the INT_RAWSTATUS register +#define DMA_INT_RAWSTATUS_RESET 0x00000000 + +// field definitions +/// CH4_EOT field bit +#define DMA_CH4_EOT_BIT ((uint32_t)0x01000000) +/// CH4_EOT field position +#define DMA_CH4_EOT_POS 24 +/// CH3_EOT field bit +#define DMA_CH3_EOT_BIT ((uint32_t)0x00800000) +/// CH3_EOT field position +#define DMA_CH3_EOT_POS 23 +/// CH2_EOT field bit +#define DMA_CH2_EOT_BIT ((uint32_t)0x00400000) +/// CH2_EOT field position +#define DMA_CH2_EOT_POS 22 +/// CH1_EOT field bit +#define DMA_CH1_EOT_BIT ((uint32_t)0x00200000) +/// CH1_EOT field position +#define DMA_CH1_EOT_POS 21 +/// CH0_EOT field bit +#define DMA_CH0_EOT_BIT ((uint32_t)0x00100000) +/// CH0_EOT field position +#define DMA_CH0_EOT_POS 20 +/// ERROR field bit +#define DMA_ERROR_BIT ((uint32_t)0x00010000) +/// ERROR field position +#define DMA_ERROR_POS 16 +/// LLI_IRQ field mask +#define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF) +/// LLI_IRQ field LSB position +#define DMA_LLI_IRQ_LSB 0 +/// LLI_IRQ field width +#define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010) + +/// CH4_EOT field reset value +#define DMA_CH4_EOT_RST 0x0 +/// CH3_EOT field reset value +#define DMA_CH3_EOT_RST 0x0 +/// CH2_EOT field reset value +#define DMA_CH2_EOT_RST 0x0 +/// CH1_EOT field reset value +#define DMA_CH1_EOT_RST 0x0 +/// CH0_EOT field reset value +#define DMA_CH0_EOT_RST 0x0 +/// ERROR field reset value +#define DMA_ERROR_RST 0x0 +/// LLI_IRQ field reset value +#define DMA_LLI_IRQ_RST 0x0 + +/// @} + +/** + * @name INT_UNMASK_SET register definitions + * + * + *
INT_UNMASK_SET bitfields
Bits Field Name HW Access SW Access Reset Value + *
24 CH4_EOT R/W S 0 + *
23 CH3_EOT R/W S 0 + *
22 CH2_EOT R/W S 0 + *
21 CH1_EOT R/W S 0 + *
20 CH0_EOT R/W S 0 + *
16 ERROR R/W S 0 + *
15:00 LLI_IRQ R/W S 0x0 + *
+ * + * @{ + */ + +/// Address of the INT_UNMASK_SET register +//#define DMA_INT_UNMASK_SET_ADDR 0x24A00018 +/// Offset of the INT_UNMASK_SET register from the base address +#define DMA_INT_UNMASK_SET_OFFSET 0x00000018 +/// Index of the INT_UNMASK_SET register +#define DMA_INT_UNMASK_SET_INDEX 0x00000006 +/// Reset value of the INT_UNMASK_SET register +#define DMA_INT_UNMASK_SET_RESET 0x00000000 + +// field definitions +/// CH4_EOT field bit +#define DMA_CH4_EOT_BIT ((uint32_t)0x01000000) +/// CH4_EOT field position +#define DMA_CH4_EOT_POS 24 +/// CH3_EOT field bit +#define DMA_CH3_EOT_BIT ((uint32_t)0x00800000) +/// CH3_EOT field position +#define DMA_CH3_EOT_POS 23 +/// CH2_EOT field bit +#define DMA_CH2_EOT_BIT ((uint32_t)0x00400000) +/// CH2_EOT field position +#define DMA_CH2_EOT_POS 22 +/// CH1_EOT field bit +#define DMA_CH1_EOT_BIT ((uint32_t)0x00200000) +/// CH1_EOT field position +#define DMA_CH1_EOT_POS 21 +/// CH0_EOT field bit +#define DMA_CH0_EOT_BIT ((uint32_t)0x00100000) +/// CH0_EOT field position +#define DMA_CH0_EOT_POS 20 +/// ERROR field bit +#define DMA_ERROR_BIT ((uint32_t)0x00010000) +/// ERROR field position +#define DMA_ERROR_POS 16 +/// LLI_IRQ field mask +#define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF) +/// LLI_IRQ field LSB position +#define DMA_LLI_IRQ_LSB 0 +/// LLI_IRQ field width +#define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010) + +/// CH4_EOT field reset value +#define DMA_CH4_EOT_RST 0x0 +/// CH3_EOT field reset value +#define DMA_CH3_EOT_RST 0x0 +/// CH2_EOT field reset value +#define DMA_CH2_EOT_RST 0x0 +/// CH1_EOT field reset value +#define DMA_CH1_EOT_RST 0x0 +/// CH0_EOT field reset value +#define DMA_CH0_EOT_RST 0x0 +/// ERROR field reset value +#define DMA_ERROR_RST 0x0 +/// LLI_IRQ field reset value +#define DMA_LLI_IRQ_RST 0x0 + +/// @} + +/** + * @name INT_UNMASK_CLEAR register definitions + * + * + *
INT_UNMASK_CLEAR bitfields
Bits Field Name HW Access SW Access Reset Value + *
24 CH4_EOT R/W C 0 + *
23 CH3_EOT R/W C 0 + *
22 CH2_EOT R/W C 0 + *
21 CH1_EOT R/W C 0 + *
20 CH0_EOT R/W C 0 + *
16 ERROR R/W C 0 + *
15:00 LLI_IRQ R/W C 0x0 + *
+ * + * @{ + */ + +/// Address of the INT_UNMASK_CLEAR register +//#define DMA_INT_UNMASK_CLEAR_ADDR 0x24A0001C +/// Offset of the INT_UNMASK_CLEAR register from the base address +#define DMA_INT_UNMASK_CLEAR_OFFSET 0x0000001C +/// Index of the INT_UNMASK_CLEAR register +#define DMA_INT_UNMASK_CLEAR_INDEX 0x00000007 +/// Reset value of the INT_UNMASK_CLEAR register +#define DMA_INT_UNMASK_CLEAR_RESET 0x00000000 + +/// @} + +/** + * @name INT_ACK register definitions + * + * + *
INT_ACK bitfields
Bits Field Name HW Access SW Access Reset Value + *
24 CH4_EOT R/W C 0 + *
23 CH3_EOT R/W C 0 + *
22 CH2_EOT R/W C 0 + *
21 CH1_EOT R/W C 0 + *
20 CH0_EOT R/W C 0 + *
16 ERROR R/W C 0 + *
15:00 LLI_IRQ R/W C 0x0 + *
+ * + * @{ + */ + +/// Address of the INT_ACK register +//#define DMA_INT_ACK_ADDR 0x24A00020 +/// Offset of the INT_ACK register from the base address +#define DMA_INT_ACK_OFFSET 0x00000020 +/// Index of the INT_ACK register +#define DMA_INT_ACK_INDEX 0x00000008 +/// Reset value of the INT_ACK register +#define DMA_INT_ACK_RESET 0x00000000 + + +// field definitions +/// CH4_EOT field bit +#define DMA_CH4_EOT_BIT ((uint32_t)0x01000000) +/// CH4_EOT field position +#define DMA_CH4_EOT_POS 24 +/// CH3_EOT field bit +#define DMA_CH3_EOT_BIT ((uint32_t)0x00800000) +/// CH3_EOT field position +#define DMA_CH3_EOT_POS 23 +/// CH2_EOT field bit +#define DMA_CH2_EOT_BIT ((uint32_t)0x00400000) +/// CH2_EOT field position +#define DMA_CH2_EOT_POS 22 +/// CH1_EOT field bit +#define DMA_CH1_EOT_BIT ((uint32_t)0x00200000) +/// CH1_EOT field position +#define DMA_CH1_EOT_POS 21 +/// CH0_EOT field bit +#define DMA_CH0_EOT_BIT ((uint32_t)0x00100000) +/// CH0_EOT field position +#define DMA_CH0_EOT_POS 20 +/// ERROR field bit +#define DMA_ERROR_BIT ((uint32_t)0x00010000) +/// ERROR field position +#define DMA_ERROR_POS 16 +/// LLI_IRQ field mask +#define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF) +/// LLI_IRQ field LSB position +#define DMA_LLI_IRQ_LSB 0 +/// LLI_IRQ field width +#define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010) + +/// CH4_EOT field reset value +#define DMA_CH4_EOT_RST 0x0 +/// CH3_EOT field reset value +#define DMA_CH3_EOT_RST 0x0 +/// CH2_EOT field reset value +#define DMA_CH2_EOT_RST 0x0 +/// CH1_EOT field reset value +#define DMA_CH1_EOT_RST 0x0 +/// CH0_EOT field reset value +#define DMA_CH0_EOT_RST 0x0 +/// ERROR field reset value +#define DMA_ERROR_RST 0x0 +/// LLI_IRQ field reset value +#define DMA_LLI_IRQ_RST 0x0 + +/// @} + +/** + * @name INT_STATUS register definitions + * + * + *
INT_STATUS bitfields
Bits Field Name HW Access SW Access Reset Value + *
24 CH4_EOT W R 0 + *
23 CH3_EOT W R 0 + *
22 CH2_EOT W R 0 + *
21 CH1_EOT W R 0 + *
20 CH0_EOT W R 0 + *
16 ERROR W R 0 + *
15:00 LLI_IRQ W R 0x0 + *
+ * + * @{ + */ + +/// Address of the INT_STATUS register +//#define DMA_INT_STATUS_ADDR 0x24A00024 +/// Offset of the INT_STATUS register from the base address +#define DMA_INT_STATUS_OFFSET 0x00000024 +/// Index of the INT_STATUS register +#define DMA_INT_STATUS_INDEX 0x00000009 +/// Reset value of the INT_STATUS register +#define DMA_INT_STATUS_RESET 0x00000000 + +// field definitions +/// CH4_EOT field bit +#define DMA_CH4_EOT_BIT ((uint32_t)0x01000000) +/// CH4_EOT field position +#define DMA_CH4_EOT_POS 24 +/// CH3_EOT field bit +#define DMA_CH3_EOT_BIT ((uint32_t)0x00800000) +/// CH3_EOT field position +#define DMA_CH3_EOT_POS 23 +/// CH2_EOT field bit +#define DMA_CH2_EOT_BIT ((uint32_t)0x00400000) +/// CH2_EOT field position +#define DMA_CH2_EOT_POS 22 +/// CH1_EOT field bit +#define DMA_CH1_EOT_BIT ((uint32_t)0x00200000) +/// CH1_EOT field position +#define DMA_CH1_EOT_POS 21 +/// CH0_EOT field bit +#define DMA_CH0_EOT_BIT ((uint32_t)0x00100000) +/// CH0_EOT field position +#define DMA_CH0_EOT_POS 20 +/// ERROR field bit +#define DMA_ERROR_BIT ((uint32_t)0x00010000) +/// ERROR field position +#define DMA_ERROR_POS 16 +/// LLI_IRQ field mask +#define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF) +/// LLI_IRQ field LSB position +#define DMA_LLI_IRQ_LSB 0 +/// LLI_IRQ field width +#define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010) + +/// CH4_EOT field reset value +#define DMA_CH4_EOT_RST 0x0 +/// CH3_EOT field reset value +#define DMA_CH3_EOT_RST 0x0 +/// CH2_EOT field reset value +#define DMA_CH2_EOT_RST 0x0 +/// CH1_EOT field reset value +#define DMA_CH1_EOT_RST 0x0 +/// CH0_EOT field reset value +#define DMA_CH0_EOT_RST 0x0 +/// ERROR field reset value +#define DMA_ERROR_RST 0x0 +/// LLI_IRQ field reset value +#define DMA_LLI_IRQ_RST 0x0 + +/// @} + +/** + * @name ARBITRATION register definitions + * + * + *
ARBITRATION bitfields
Bits Field Name HW Access SW Access Reset Value + *
03:00 DOWNSTREAM_TAG_USAGE R R/W 0xC + *
+ * + * @{ + */ + +/// Address of the ARBITRATION register +//#define DMA_ARBITRATION_ADDR 0x24A00034 +/// Offset of the ARBITRATION register from the base address +#define DMA_ARBITRATION_OFFSET 0x00000034 +/// Index of the ARBITRATION register +#define DMA_ARBITRATION_INDEX 0x0000000D +/// Reset value of the ARBITRATION register +#define DMA_ARBITRATION_RESET 0x0000000C + +// field definitions +/// DOWNSTREAM_TAG_USAGE field mask +#define DMA_DOWNSTREAM_TAG_USAGE_MASK ((uint32_t)0x0000000F) +/// DOWNSTREAM_TAG_USAGE field LSB position +#define DMA_DOWNSTREAM_TAG_USAGE_LSB 0 +/// DOWNSTREAM_TAG_USAGE field width +#define DMA_DOWNSTREAM_TAG_USAGE_WIDTH ((uint32_t)0x00000004) + +/// DOWNSTREAM_TAG_USAGE field reset value +#define DMA_DOWNSTREAM_TAG_USAGE_RST 0xC + +/// @} + +/** + * @name CHANNEL_MUTEX_SET register definitions + * + * + *
CHANNEL_MUTEX_SET bitfields
Bits Field Name HW Access SW Access Reset Value + *
04 CH4_MUTEX R/W S 0 + *
03 CH3_MUTEX R/W S 0 + *
02 CH2_MUTEX R/W S 0 + *
01 CH1_MUTEX R/W S 0 + *
00 CH0_MUTEX R/W S 0 + *
+ * + * @{ + */ + +/// Address of the CHANNEL_MUTEX_SET register +//#define DMA_CHANNEL_MUTEX_SET_ADDR 0x24A00038 +/// Offset of the CHANNEL_MUTEX_SET register from the base address +#define DMA_CHANNEL_MUTEX_SET_OFFSET 0x00000038 +/// Index of the CHANNEL_MUTEX_SET register +#define DMA_CHANNEL_MUTEX_SET_INDEX 0x0000000E +/// Reset value of the CHANNEL_MUTEX_SET register +#define DMA_CHANNEL_MUTEX_SET_RESET 0x00000000 + +// field definitions +/// CH4_MUTEX field bit +#define DMA_CH4_MUTEX_BIT ((uint32_t)0x00000010) +/// CH4_MUTEX field position +#define DMA_CH4_MUTEX_POS 4 +/// CH3_MUTEX field bit +#define DMA_CH3_MUTEX_BIT ((uint32_t)0x00000008) +/// CH3_MUTEX field position +#define DMA_CH3_MUTEX_POS 3 +/// CH2_MUTEX field bit +#define DMA_CH2_MUTEX_BIT ((uint32_t)0x00000004) +/// CH2_MUTEX field position +#define DMA_CH2_MUTEX_POS 2 +/// CH1_MUTEX field bit +#define DMA_CH1_MUTEX_BIT ((uint32_t)0x00000002) +/// CH1_MUTEX field position +#define DMA_CH1_MUTEX_POS 1 +/// CH0_MUTEX field bit +#define DMA_CH0_MUTEX_BIT ((uint32_t)0x00000001) +/// CH0_MUTEX field position +#define DMA_CH0_MUTEX_POS 0 + +/// CH4_MUTEX field reset value +#define DMA_CH4_MUTEX_RST 0x0 +/// CH3_MUTEX field reset value +#define DMA_CH3_MUTEX_RST 0x0 +/// CH2_MUTEX field reset value +#define DMA_CH2_MUTEX_RST 0x0 +/// CH1_MUTEX field reset value +#define DMA_CH1_MUTEX_RST 0x0 +/// CH0_MUTEX field reset value +#define DMA_CH0_MUTEX_RST 0x0 + +/// @} + +/** + * @name CHANNEL_MUTEX_CLEAR register definitions + * + * + *
CHANNEL_MUTEX_CLEAR bitfields
Bits Field Name HW Access SW Access Reset Value + *
04 CH4_MUTEX R/W C 0 + *
03 CH3_MUTEX R/W C 0 + *
02 CH2_MUTEX R/W C 0 + *
01 CH1_MUTEX R/W C 0 + *
00 CH0_MUTEX R/W C 0 + *
+ * + * @{ + */ + +/// Address of the CHANNEL_MUTEX_CLEAR register +//#define DMA_CHANNEL_MUTEX_CLEAR_ADDR 0x24A0003C +/// Offset of the CHANNEL_MUTEX_CLEAR register from the base address +#define DMA_CHANNEL_MUTEX_CLEAR_OFFSET 0x0000003C +/// Index of the CHANNEL_MUTEX_CLEAR register +#define DMA_CHANNEL_MUTEX_CLEAR_INDEX 0x0000000F +/// Reset value of the CHANNEL_MUTEX_CLEAR register +#define DMA_CHANNEL_MUTEX_CLEAR_RESET 0x00000000 + +/// @} + +/** + * @name CH4_LLI_ROOT register definitions + * + * + *
CH4_LLI_ROOT bitfields
Bits Field Name HW Access SW Access Reset Value + *
31:00 CH4_LLI_ROOT R R/W 0x0 + *
+ * + * @{ + */ + +/// Address of the CH4_LLI_ROOT register +//#define DMA_CH4_LLI_ROOT_ADDR 0x24A00040 +/// Offset of the CH4_LLI_ROOT register from the base address +#define DMA_CH4_LLI_ROOT_OFFSET 0x00000040 +/// Index of the CH4_LLI_ROOT register +#define DMA_CH4_LLI_ROOT_INDEX 0x00000010 +/// Reset value of the CH4_LLI_ROOT register +#define DMA_CH4_LLI_ROOT_RESET 0x00000000 + +// field definitions +/// CH4_LLI_ROOT field mask +#define DMA_CH4_LLI_ROOT_MASK ((uint32_t)0xFFFFFFFF) +/// CH4_LLI_ROOT field LSB position +#define DMA_CH4_LLI_ROOT_LSB 0 +/// CH4_LLI_ROOT field width +#define DMA_CH4_LLI_ROOT_WIDTH ((uint32_t)0x00000020) + +/// CH4_LLI_ROOT field reset value +#define DMA_CH4_LLI_ROOT_RST 0x0 + +/// @} + +/** + * @name LLI_COUNTER register definitions + * + * + *
LLI_COUNTER bitfields
Bits Field Name HW Access SW Access Reset Value + *
15:00 COUNTER W R 0x0 + *
+ * + * @{ + */ + +/// Address of the LLI_COUNTER register +//#define DMA_LLI_COUNTER_ADDR 0x24A00080 +/// Offset of the LLI_COUNTER register from the base address +#define DMA_LLI_COUNTER_OFFSET 0x00000080 +/// Index of the LLI_COUNTER register +#define DMA_LLI_COUNTER_INDEX 0x00000020 +/// Reset value of the LLI_COUNTER register +#define DMA_LLI_COUNTER_RESET 0x00000000 +/// Number of elements of the LLI_COUNTER register array +#define DMA_LLI_COUNTER_COUNT 16 + +// field definitions +/// COUNTER field mask +#define DMA_COUNTER_MASK ((uint32_t)0x0000FFFF) +/// COUNTER field LSB position +#define DMA_COUNTER_LSB 0 +/// COUNTER field width +#define DMA_COUNTER_WIDTH ((uint32_t)0x00000010) + +/// COUNTER field reset value +#define DMA_COUNTER_RST 0x0 + +/// @} + +/** + * @name DUMMY register definitions + * + * + *
DUMMY bitfields
Bits Field Name HW Access SW Access Reset Value + *
00 DUMMY R R/W 0 + *
+ * + * @{ + */ + +/// Address of the DUMMY register +//#define DMA_DUMMY_ADDR 0x24A000C0 +/// Offset of the DUMMY register from the base address +#define DMA_DUMMY_OFFSET 0x000000C0 +/// Index of the DUMMY register +#define DMA_DUMMY_INDEX 0x00000030 +/// Reset value of the DUMMY register +#define DMA_DUMMY_RESET 0x00000000 + +// field definitions +/// DUMMY field bit +#define DMA_DUMMY_BIT ((uint32_t)0x00000001) +/// DUMMY field position +#define DMA_DUMMY_POS 0 + +/// DUMMY field reset value +#define DMA_DUMMY_RST 0x0 + + +/// @} + +#endif /* __HARDWARE_PLATFORM_DMA_H__ */ diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/rtc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/rtc_reg.h index dee3bfee8e..79e3300073 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/rtc_reg.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/rtc_reg.h @@ -51,8 +51,16 @@ /* Register Bitfield definitions *****************************************************/ /* 0x0 : HBN_CTL */ -#define HBN_RTC_CTL_SHIFT (0U) -#define HBN_RTC_CTL_MASK (0x7f << HBN_RTC_CTL_SHIFT) +#define HBN_RTC_ENABLE (1 << 0U) +#define HBN_RTC_CTL_SHIFT (1U) +#if defined(BL602) || defined(BL702) +#define HBN_RTC_CTL_MASK (0x3f << HBN_RTC_CTL_SHIFT) +#define HBN_RTC_DLY_OPTION (1 << 24U) +#elif defined(BL808) || defined(BL606P) || defined(BL616) || defined(BL702L) || defined(BL628) +#define HBN_RTC_CTL_MASK (0x7 << HBN_RTC_CTL_SHIFT) +#define HBN_RTC_DLY_OPTION (1 << 4U) +#endif +#define HBN_RTC_BIT39_0_COMPARE (1 << HBN_RTC_CTL_SHIFT) #define HBN_MODE (1 << 7U) #define HBN_TRAP_MODE (1 << 8U) #define HBN_PWRDN_HBN_CORE (1 << 9U) @@ -65,7 +73,6 @@ #define HBN_LDO11_AON_VOUT_SEL_SHIFT (19U) #define HBN_LDO11_AON_VOUT_SEL_MASK (0xf << HBN_LDO11_AON_VOUT_SEL_SHIFT) #define HBN_PU_DCDC18_AON (1 << 23U) -#define HBN_RTC_DLY_OPTION (1 << 24U) #define HBN_PWR_ON_OPTION (1 << 25U) #define HBN_SRAM_SLP_OPTION (1 << 26U) #define HBN_SRAM_SLP (1 << 27U) diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_acomp.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_acomp.c new file mode 100755 index 0000000000..e232789310 --- /dev/null +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_acomp.c @@ -0,0 +1,318 @@ +#include "bflb_acomp.h" +#include "bflb_core.h" +#include "bflb_gpio.h" +#include "hardware/acomp_reg.h" + +#if defined(BL702) || defined(BL602) || defined(BL702L) +#define ACOMP_BASE ((uint32_t)0x4000f000) +#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) +#define ACOMP_BASE ((uint32_t)0x2000f000) +#endif + +void bflb_acomp_init(uint8_t acomp_id, const struct bflb_acomp_config_s *config) +{ + uint32_t regval; + uint32_t reg_base; + + if(AON_ACOMP0_ID == acomp_id){ + reg_base = ACOMP_BASE + AON_ACOMP_REG_ACOMP0_CTRL_OFFSET; + } else { + reg_base = ACOMP_BASE + AON_ACOMP_REG_ACOMP1_CTRL_OFFSET; + } + + /* disable ACOMPx */ + regval = getreg32(reg_base); + regval &=~ AON_ACOMP_EN; + putreg32(regval, reg_base); + + /* set ACOMPx config */ + if(config->mux_en) { + regval |= AON_ACOMP_MUX_EN; + } else { + regval &=~ AON_ACOMP_MUX_EN; + } + regval &=~ AON_ACOMP_POS_SEL_MASK; + regval |= (config->pos_chan_sel << AON_ACOMP_POS_SEL_SHIFT); + regval &=~ AON_ACOMP_NEG_SEL_MASK; + regval |= (config->neg_chan_sel << AON_ACOMP_NEG_SEL_SHIFT); + regval &=~ AON_ACOMP_LEVEL_SEL_MASK; + regval |= (config->scaling_factor << AON_ACOMP_LEVEL_SEL_SHIFT); + regval &=~ AON_ACOMP_BIAS_PROG_MASK; + regval |= (config->bias_prog << AON_ACOMP_BIAS_PROG_SHIFT); + regval &=~ AON_ACOMP_HYST_SELP_MASK; + regval |= (config->hysteresis_pos_volt << AON_ACOMP_HYST_SELP_SHIFT); + regval &=~ AON_ACOMP_HYST_SELN_MASK; + regval |= (config->hysteresis_neg_volt << AON_ACOMP_HYST_SELN_SHIFT); + putreg32(regval, reg_base); + + reg_base = ACOMP_BASE + AON_ACOMP_REG_ACOMP_CFG_OFFSET; + regval = getreg32(reg_base); + regval &=~ AON_ACOMP_VREF_SEL_MASK; + regval |= (config->vio_sel << AON_ACOMP_POS_SEL_SHIFT); + putreg32(regval, reg_base); +} + +void bflb_acomp_enable(uint8_t acomp_id) +{ + uint32_t regval; + uint32_t reg_base; + + if(AON_ACOMP0_ID == acomp_id){ + reg_base = ACOMP_BASE + AON_ACOMP_REG_ACOMP0_CTRL_OFFSET; + } else { + reg_base = ACOMP_BASE + AON_ACOMP_REG_ACOMP1_CTRL_OFFSET; + } + + regval = getreg32(reg_base); + regval |= AON_ACOMP_EN; + putreg32(regval, reg_base); +} + +void bflb_acomp_disable(uint8_t acomp_id) +{ + uint32_t regval; + uint32_t reg_base; + + if(AON_ACOMP0_ID == acomp_id){ + reg_base = ACOMP_BASE + AON_ACOMP_REG_ACOMP0_CTRL_OFFSET; + } else { + reg_base = ACOMP_BASE + AON_ACOMP_REG_ACOMP1_CTRL_OFFSET; + } + + /* disable ACOMPx */ + regval = getreg32(reg_base); + regval &=~ AON_ACOMP_EN; + putreg32(regval, reg_base); +} + +uint32_t bflb_acomp_get_result(uint8_t acomp_id) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = ACOMP_BASE + AON_ACOMP_REG_ACOMP_CFG_OFFSET; + regval = getreg32(reg_base); + + if(AON_ACOMP0_ID == acomp_id){ + return (regval & AON_ACOMP0_OUT_RAW_DATA_MASK) >> AON_ACOMP0_OUT_RAW_DATA_SHIFT; + } else { + return (regval & AON_ACOMP1_OUT_RAW_DATA_MASK) >> AON_ACOMP1_OUT_RAW_DATA_SHIFT; + } +} + +uint32_t bflb_acomp_gpio_2_chanid(uint32_t pin, uint32_t* channel) +{ +#if defined(BL602) + if ( pin == GPIO_PIN_12 ) { + *channel = AON_ACOMP_CHAN_ADC0; + } else if ( pin == GPIO_PIN_4 ) { + *channel = AON_ACOMP_CHAN_ADC1; + } else if ( pin == GPIO_PIN_14 ) { + *channel = AON_ACOMP_CHAN_ADC2; + } else if ( pin == GPIO_PIN_13 ) { + *channel = AON_ACOMP_CHAN_ADC3; + } else if ( pin == GPIO_PIN_5 ) { + *channel = AON_ACOMP_CHAN_ADC4; + } else if ( pin == GPIO_PIN_6 ) { + *channel = AON_ACOMP_CHAN_ADC5; + } else if ( pin == GPIO_PIN_9 ) { + *channel = AON_ACOMP_CHAN_ADC6; + // } else if ( pin == GPIO_PIN_9 ) { + // *channel = AON_ACOMP_CHAN_ADC7; + } else { + return -1; + } +#elif defined(BL702) + if ( pin == GPIO_PIN_8 ) { + *channel = AON_ACOMP_CHAN_ADC0; + } else if ( pin == GPIO_PIN_15 ) { + *channel = AON_ACOMP_CHAN_ADC1; + } else if ( pin == GPIO_PIN_17 ) { + *channel = AON_ACOMP_CHAN_ADC2; + } else if ( pin == GPIO_PIN_11 ) { + *channel = AON_ACOMP_CHAN_ADC3; + } else if ( pin == GPIO_PIN_12 ) { + *channel = AON_ACOMP_CHAN_ADC4; + } else if ( pin == GPIO_PIN_14 ) { + *channel = AON_ACOMP_CHAN_ADC5; + } else if ( pin == GPIO_PIN_7 ) { + *channel = AON_ACOMP_CHAN_ADC6; + } else if ( pin == GPIO_PIN_9 ) { + *channel = AON_ACOMP_CHAN_ADC7; + } else { + return -1; + } +#elif defined(BL702L) + if ( pin == GPIO_PIN_14 ) { + *channel = AON_ACOMP_CHAN_ADC0; + } else if ( pin == GPIO_PIN_15 ) { + *channel = AON_ACOMP_CHAN_ADC1; + } else if ( pin == GPIO_PIN_17 ) { + *channel = AON_ACOMP_CHAN_ADC2; + } else if ( pin == GPIO_PIN_18 ) { + *channel = AON_ACOMP_CHAN_ADC3; + } else if ( pin == GPIO_PIN_19 ) { + *channel = AON_ACOMP_CHAN_ADC4; + } else if ( pin == GPIO_PIN_20 ) { + *channel = AON_ACOMP_CHAN_ADC5; + } else if ( pin == GPIO_PIN_21 ) { + *channel = AON_ACOMP_CHAN_ADC6; + } else if ( pin == GPIO_PIN_7 ) { + *channel = AON_ACOMP_CHAN_ADC7; + } else { + return -1; + } +#elif defined(BL616) + if (pin == GPIO_PIN_20) { + *channel = AON_ACOMP_CHAN_ADC0; + } else if (pin == GPIO_PIN_19) { + *channel = AON_ACOMP_CHAN_ADC1; + } else if (pin == GPIO_PIN_2) { + *channel = AON_ACOMP_CHAN_ADC2; + } else if (pin == GPIO_PIN_3) { + *channel = AON_ACOMP_CHAN_ADC3; + } else if (pin == GPIO_PIN_14) { + *channel = AON_ACOMP_CHAN_ADC4; + } else if (pin == GPIO_PIN_13) { + *channel = AON_ACOMP_CHAN_ADC5; + } else if (pin == GPIO_PIN_12) { + *channel = AON_ACOMP_CHAN_ADC6; + } else if (pin == GPIO_PIN_10) { + *channel = AON_ACOMP_CHAN_ADC7; + } else { + return -1; + } +#elif defined(BL606P) || defined(BL808) + if (pin == GPIO_PIN_17) { + *channel = AON_ACOMP_CHAN_ADC0; + } else if (pin == GPIO_PIN_5) { + *channel = AON_ACOMP_CHAN_ADC1; + } else if (pin == GPIO_PIN_4) { + *channel = AON_ACOMP_CHAN_ADC2; + } else if (pin == GPIO_PIN_11) { + *channel = AON_ACOMP_CHAN_ADC3; + } else if (pin == GPIO_PIN_6) { + *channel = AON_ACOMP_CHAN_ADC4; + } else if (pin == GPIO_PIN_40) { + *channel = AON_ACOMP_CHAN_ADC5; + } else if (pin == GPIO_PIN_12) { + *channel = AON_ACOMP_CHAN_ADC6; + } else if (pin == GPIO_PIN_13) { + *channel = AON_ACOMP_CHAN_ADC7; + } else { + return -1; + } +#else + return -1; +#endif + return 0; +} + +uint32_t bflb_acomp_chanid_2_gpio(uint32_t channel, uint32_t* pin) +{ +#if defined(BL602) + if ( channel == AON_ACOMP_CHAN_ADC0 ) { + *pin = GPIO_PIN_12; + } else if ( channel == AON_ACOMP_CHAN_ADC1 ) { + *pin = GPIO_PIN_4; + } else if ( channel == AON_ACOMP_CHAN_ADC2 ) { + *pin = GPIO_PIN_14; + } else if ( channel == AON_ACOMP_CHAN_ADC3 ) { + *pin = GPIO_PIN_13; + } else if ( channel == AON_ACOMP_CHAN_ADC4 ) { + *pin = GPIO_PIN_5; + } else if ( channel == AON_ACOMP_CHAN_ADC5 ) { + *pin = GPIO_PIN_6; + } else if ( channel == AON_ACOMP_CHAN_ADC6 ) { + *pin = GPIO_PIN_9; + } else if ( channel == AON_ACOMP_CHAN_ADC7 ) { + *pin = GPIO_PIN_9; + } else { + return -1; + } +#elif defined(BL702) + if ( channel == AON_ACOMP_CHAN_ADC0 ) { + *pin = GPIO_PIN_8; + } else if ( channel == AON_ACOMP_CHAN_ADC1 ) { + *pin = GPIO_PIN_15; + } else if ( channel == AON_ACOMP_CHAN_ADC2 ) { + *pin = GPIO_PIN_17; + } else if ( channel == AON_ACOMP_CHAN_ADC3 ) { + *pin = GPIO_PIN_11; + } else if ( channel == AON_ACOMP_CHAN_ADC4 ) { + *pin = GPIO_PIN_12; + } else if ( channel == AON_ACOMP_CHAN_ADC5 ) { + *pin = GPIO_PIN_14; + } else if ( channel == AON_ACOMP_CHAN_ADC6 ) { + *pin = GPIO_PIN_7; + } else if ( channel == AON_ACOMP_CHAN_ADC7 ) { + *pin = GPIO_PIN_9; + } else { + return -1; + } +#elif defined(BL702L) + if ( channel == AON_ACOMP_CHAN_ADC0 ) { + *pin = GPIO_PIN_14; + } else if ( channel == AON_ACOMP_CHAN_ADC1 ) { + *pin = GPIO_PIN_15; + } else if ( channel == AON_ACOMP_CHAN_ADC2 ) { + *pin = GPIO_PIN_17; + } else if ( channel == AON_ACOMP_CHAN_ADC3 ) { + *pin = GPIO_PIN_18; + } else if ( channel == AON_ACOMP_CHAN_ADC4 ) { + *pin = GPIO_PIN_19; + } else if ( channel == AON_ACOMP_CHAN_ADC5 ) { + *pin = GPIO_PIN_20; + } else if ( channel == AON_ACOMP_CHAN_ADC6 ) { + *pin = GPIO_PIN_21; + } else if ( channel == AON_ACOMP_CHAN_ADC7 ) { + *pin = GPIO_PIN_7; + } else { + return -1; + } +#elif defined(BL616) + if (channel == AON_ACOMP_CHAN_ADC0) { + *pin = GPIO_PIN_20; + } else if (channel == AON_ACOMP_CHAN_ADC1) { + *pin = GPIO_PIN_19; + } else if (channel == AON_ACOMP_CHAN_ADC2) { + *pin = GPIO_PIN_2; + } else if (channel == AON_ACOMP_CHAN_ADC3) { + *pin = GPIO_PIN_3; + } else if (channel == AON_ACOMP_CHAN_ADC4) { + *pin = GPIO_PIN_14; + } else if (channel == AON_ACOMP_CHAN_ADC5) { + *pin = GPIO_PIN_13; + } else if (channel == AON_ACOMP_CHAN_ADC6) { + *pin = GPIO_PIN_12; + } else if (channel == AON_ACOMP_CHAN_ADC7) { + *pin = GPIO_PIN_10; + } else { + return -1; + } +#elif defined(BL606P) || defined(BL808) + if (channel == AON_ACOMP_CHAN_ADC0) { + *pin = GPIO_PIN_17; + } else if (channel == AON_ACOMP_CHAN_ADC1) { + *pin = GPIO_PIN_5; + } else if (channel == AON_ACOMP_CHAN_ADC2) { + *pin = GPIO_PIN_4; + } else if (channel == AON_ACOMP_CHAN_ADC3) { + *pin = GPIO_PIN_11; + } else if (channel == AON_ACOMP_CHAN_ADC4) { + *pin = GPIO_PIN_6; + } else if (channel == AON_ACOMP_CHAN_ADC5) { + *pin = GPIO_PIN_40; + } else if (channel == AON_ACOMP_CHAN_ADC6) { + *pin = GPIO_PIN_12; + } else if (channel == AON_ACOMP_CHAN_ADC7) { + *pin = GPIO_PIN_13; + } else { + return -1; + } +#else + return -1; +#endif + return 0; +} + diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_clock.c index e46bfd7858..0e3e6723a2 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_clock.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_clock.c @@ -82,8 +82,6 @@ uint32_t ATTR_CLOCK_SECTION bflb_clk_get_peripheral_clock(uint8_t type, uint8_t return bflb_clock_get_cam(); case BFLB_DEVICE_TYPE_DBI: return bflb_clock_get_dbi(); - case BFLB_DEVICE_TYPE_PEC: - return bflb_clock_get_pec(); case BFLB_DEVICE_TYPE_I2S: return bflb_clock_get_i2s(); default: diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c index cd8f5282c6..b20e6717cb 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c @@ -409,13 +409,6 @@ void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_fu bflb_gpio_init(dev, pin, (7 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); } -#if defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) -void bflb_gpio_iso11898_init(struct bflb_device_s *dev, uint8_t pin, uint8_t iso11898_func) -{ - bflb_gpio_uart_init(dev, pin, iso11898_func); -} -#endif - int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) { int ret = 0; diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c index a82ef5fdb5..920e8c1ba3 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c @@ -76,18 +76,30 @@ static void bflb_i2c_set_frequence(struct bflb_device_s *dev, uint32_t freq) uint32_t regval; uint32_t reg_base; uint32_t phase; + uint32_t tmp; reg_base = dev->reg_base; phase = bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_I2C, dev->idx) / (freq * 4) - 1; - regval = phase << I2C_CR_I2C_PRD_S_PH_0_SHIFT; - regval |= phase << I2C_CR_I2C_PRD_S_PH_1_SHIFT; - regval |= phase << I2C_CR_I2C_PRD_S_PH_2_SHIFT; - regval |= phase << I2C_CR_I2C_PRD_S_PH_3_SHIFT; + if (freq > 100000) { + tmp = ((phase / 4) / 0.5); + } else { + tmp = (phase / 4); + } + + regval = (phase - tmp) << I2C_CR_I2C_PRD_S_PH_0_SHIFT; + regval |= (phase + tmp) << I2C_CR_I2C_PRD_S_PH_1_SHIFT; + regval |= (phase) << I2C_CR_I2C_PRD_S_PH_2_SHIFT; + regval |= (phase) << I2C_CR_I2C_PRD_S_PH_3_SHIFT; putreg32(regval, reg_base + I2C_PRD_START_OFFSET); putreg32(regval, reg_base + I2C_PRD_STOP_OFFSET); + + regval = (phase - tmp) << I2C_CR_I2C_PRD_D_PH_0_SHIFT; + regval |= (phase + tmp) << I2C_CR_I2C_PRD_D_PH_1_SHIFT; + regval |= (phase + tmp) << I2C_CR_I2C_PRD_D_PH_2_SHIFT; + regval |= (phase - tmp) << I2C_CR_I2C_PRD_D_PH_3_SHIFT; putreg32(regval, reg_base + I2C_PRD_DATA_OFFSET); } @@ -123,6 +135,22 @@ static inline bool bflb_i2c_isend(struct bflb_device_s *dev) return false; } +static inline bool bflb_i2c_isnak(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + I2C_INT_STS_OFFSET); + + if (regval & I2C_NAK_INT) { + return true; + } + + return false; +} + static inline void bflb_i2c_enable(struct bflb_device_s *dev) { uint32_t regval; @@ -218,7 +246,7 @@ static int bflb_i2c_write_bytes(struct bflb_device_s *dev, uint8_t *data, uint32 } start_time = bflb_mtimer_get_time_ms(); - while (bflb_i2c_isbusy(dev) || !bflb_i2c_isend(dev)) { + while (bflb_i2c_isbusy(dev) || !bflb_i2c_isend(dev) || bflb_i2c_isnak(dev)) { if ((bflb_mtimer_get_time_ms() - start_time) > 100) { return -ETIMEDOUT; } diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_iso11898.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_iso11898.c deleted file mode 100755 index f926516540..0000000000 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_iso11898.c +++ /dev/null @@ -1,366 +0,0 @@ -#include "bflb_iso11898.h" -#include "hardware/iso11898_reg.h" - -void bflb_iso11898_init(struct bflb_device_s *dev, struct bflb_iso11898_config_s *config) -{ - uint32_t reg_base; - uint32_t regval; - - reg_base = dev->reg_base; - /* first enter reset mode */ - regval = getreg32(reg_base + ISO11898_MODE_OFFSET); - regval |= ISO11898_RESET_REQUEST; - putreg32(regval, reg_base + ISO11898_MODE_OFFSET); - - /* force using PeliISO11898 not BasicISO11898 */ - regval = getreg32(reg_base + ISO11898_CLOCK_DIVIDER_OFFSET); - regval |= ISO11898_CAN_MODE; - putreg32(regval, reg_base + ISO11898_CLOCK_DIVIDER_OFFSET); - - /* config prescale and synchronisation_jump_width */ - regval = getreg32(reg_base + ISO11898_BUS_TIMING_0_OFFSET); - regval &= ~ISO11898_BAUD_RATE_PRESCALER_MASK; - regval |= (config->prescaler << ISO11898_BAUD_RATE_PRESCALER_SHIFT); - regval &= ~ISO11898_SYNC_JUMP_WIDTH_MASK; - regval |= (config->sjw << ISO11898_SYNC_JUMP_WIDTH_SHIFT); - putreg32(regval, reg_base + ISO11898_BUS_TIMING_0_OFFSET); - - /* config samping and bit_segment_1/2 */ - regval = getreg32(reg_base + ISO11898_BUS_TIMING_1_OFFSET); - if (config->sample == ISO11898_SAMPLE_SINGLE) { - regval &= ~ISO11898_SAMPLING; - } else { - regval |= ISO11898_SAMPLING; - } - regval &= ~ISO11898_TIME_SEGMENT_1_MASK; - regval |= (config->bs1 << ISO11898_TIME_SEGMENT_1_SHIFT); - regval &= ~ISO11898_TIME_SEGMENT_2_MASK; - regval |= (config->bs2 << ISO11898_TIME_SEGMENT_2_SHIFT); - putreg32(regval, reg_base + ISO11898_BUS_TIMING_1_OFFSET); - - /* config mode */ - regval = getreg32(reg_base + ISO11898_MODE_OFFSET); - if (config->mode == ISO11898_MODE_NORMAL) { - regval &= ~ISO11898_LISTEN_ONLY; - regval &= ~ISO11898_SELF_TEST; - } else if (config->mode == ISO11898_MODE_LOOPBACK) { - regval &= ~ISO11898_LISTEN_ONLY; - regval |= ISO11898_SELF_TEST; - } else if (config->mode == ISO11898_MODE_SILENT) { - regval |= ISO11898_LISTEN_ONLY; - regval &= ~ISO11898_SELF_TEST; - } else if (config->mode == ISO11898_MODE_SILENT_LOOPBACK) { - regval |= ISO11898_LISTEN_ONLY; - regval |= ISO11898_SELF_TEST; - } else { - } - putreg32(regval, reg_base + ISO11898_MODE_OFFSET); - - /* last leave reset mode */ - regval = getreg32(reg_base + ISO11898_MODE_OFFSET); - regval &= ~ISO11898_RESET_REQUEST; - putreg32(regval, reg_base + ISO11898_MODE_OFFSET); -} - -void bflb_iso11898_deinit(struct bflb_device_s *dev) -{ -} - -void bflb_iso11898_abort_send(struct bflb_device_s *dev) -{ - putreg32(ISO11898_ABORT_TRANSMISSION, dev->reg_base + ISO11898_COMMAND_OFFSET); -} - -int8_t bflb_iso11898_send(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout) -{ - uint32_t reg_base; - uint32_t regval; - uint32_t data_base_addr; - uint8_t mode; - uint64_t start_time; - - reg_base = dev->reg_base; - - start_time = bflb_mtimer_get_time_ms(); - while (!(bflb_iso11898_get_status(dev) & ISO11898_STATUS_TX_AVAILABLE)) { - if ((bflb_mtimer_get_time_ms() - start_time) > timeout) { - return -ETIMEDOUT; - } - } - - /* config frame information register */ - regval = getreg32(reg_base + ISO11898_FRAME_INFORMATION_OFFSET); - regval &= ~ISO11898_FRAME_INFORMATION_DLC_MASK; - regval |= (msg->dlc << ISO11898_FRAME_INFORMATION_DLC_SHIFT); - if (msg->id_type == ISO11898_ID_STANDARD) { - regval &= ~ISO11898_FRAME_INFORMATION_FF; - } else { - regval |= ISO11898_FRAME_INFORMATION_FF; - } - if (msg->rtr == ISO11898_RTR_DATA) { - regval &= ~ISO11898_FRAME_INFORMATION_RTR; - } else { - regval |= ISO11898_FRAME_INFORMATION_RTR; - } - putreg32(regval, reg_base + ISO11898_FRAME_INFORMATION_OFFSET); - - /* config id */ - if (msg->id_type == ISO11898_ID_STANDARD) { - putreg32(msg->std_id >> (8 - ISO11898_SFF_ID2_BIT20_18_SHIFT), reg_base + ISO11898_SFF_ID1_OFFSET); - putreg32(msg->std_id << ISO11898_SFF_ID2_BIT20_18_SHIFT, reg_base + ISO11898_SFF_ID2_OFFSET); - data_base_addr = reg_base + ISO11898_SFF_DATA1_OFFSET; - } else { - putreg32(msg->ext_id >> 21, reg_base + ISO11898_EFF_ID1_OFFSET); - putreg32(msg->ext_id >> 13, reg_base + ISO11898_EFF_ID2_OFFSET); - putreg32(msg->ext_id >> 5, reg_base + ISO11898_EFF_ID3_OFFSET); - putreg32(msg->ext_id << ISO11898_EFF_ID4_BIT4_0_SHIFT, reg_base + ISO11898_EFF_ID4_OFFSET); - data_base_addr = reg_base + ISO11898_EFF_DATA1_OFFSET; - } - - /* move data from user buff to registers */ - for (uint32_t i = 0; i < msg->dlc; i++) { - *((uint32_t *)data_base_addr + i) = msg->data[i]; - } - - /* trig a request for transmit */ - mode = bflb_iso11898_get_mode(dev); - if (mode == ISO11898_MODE_SILENT_LOOPBACK || mode == ISO11898_MODE_LOOPBACK) { - putreg32(ISO11898_SELF_REQUEST, reg_base + ISO11898_COMMAND_OFFSET); - } else if (mode == ISO11898_MODE_NORMAL) { - putreg32(ISO11898_TRANSMIT_REQUEST, reg_base + ISO11898_COMMAND_OFFSET); - } else { - return -2; - } - return 0; -} - -int8_t bflb_iso11898_recv(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout) -{ - uint32_t reg_base; - uint32_t regval, regval2, regval3, regval4; - uint32_t data_base_addr; - uint64_t start_time; - - reg_base = dev->reg_base; - - start_time = bflb_mtimer_get_time_ms(); - while (!(bflb_iso11898_get_status(dev) & ISO11898_STATUS_RX_NOT_EMPTY)) { - if ((bflb_mtimer_get_time_ms() - start_time) > timeout) { - return -ETIMEDOUT; - } - } - - /* read information register */ - regval = getreg32(reg_base + ISO11898_FRAME_INFORMATION_OFFSET); - msg->dlc = (uint8_t)((regval & ISO11898_FRAME_INFORMATION_DLC_MASK) >> ISO11898_FRAME_INFORMATION_DLC_SHIFT); - if (regval & ISO11898_FRAME_INFORMATION_FF) { - msg->id_type = ISO11898_ID_EXTENDED; - } else { - msg->id_type = ISO11898_ID_STANDARD; - } - if (regval & ISO11898_FRAME_INFORMATION_RTR) { - msg->rtr = ISO11898_RTR_REMOTE; - } else { - msg->rtr = ISO11898_RTR_DATA; - } - - /* receive with 11 or 29 bits ID */ - if (msg->id_type == ISO11898_ID_STANDARD) { - regval = getreg32(reg_base + ISO11898_SFF_ID1_OFFSET); - regval &= ISO11898_SFF_ID1_BIT28_21_MASK; - regval <<= (8 - ISO11898_SFF_ID2_BIT20_18_SHIFT); - regval2 = getreg32(reg_base + ISO11898_SFF_ID2_OFFSET); - regval2 &= ISO11898_SFF_ID2_BIT20_18_MASK; - regval2 >>= ISO11898_SFF_ID2_BIT20_18_SHIFT; - msg->std_id = regval | regval2; - data_base_addr = reg_base + ISO11898_SFF_DATA1_OFFSET; - } else { - regval = getreg32(reg_base + ISO11898_EFF_ID1_OFFSET); - regval &= ISO11898_EFF_ID1_BIT28_21_MASK; - regval <<= 21; - regval2 = getreg32(reg_base + ISO11898_EFF_ID2_OFFSET); - regval2 &= ISO11898_EFF_ID2_BIT20_13_MASK; - regval2 <<= 13; - regval3 = getreg32(reg_base + ISO11898_EFF_ID3_OFFSET); - regval3 &= ISO11898_EFF_ID3_BIT12_5_MASK; - regval3 <<= 5; - regval4 = getreg32(reg_base + ISO11898_EFF_ID4_OFFSET); - regval4 &= ISO11898_EFF_ID4_BIT4_0_MASK; - regval4 >>= ISO11898_EFF_ID4_BIT4_0_SHIFT; - msg->ext_id = regval | regval2 | regval3 | regval4; - data_base_addr = reg_base + ISO11898_EFF_DATA1_OFFSET; - } - - /* move data from registers to user buff */ - for (uint32_t i = 0; i < msg->dlc; i++) { - msg->data[i] = (uint8_t)(*((uint32_t *)data_base_addr + i)); - } - putreg32(ISO11898_RELEASE_RECEIVE_BUFFER, reg_base + ISO11898_COMMAND_OFFSET); - return 0; -} - -uint8_t bflb_iso11898_get_status(struct bflb_device_s *dev) -{ - return getreg32(dev->reg_base + ISO11898_STATUS_OFFSET) & 0xff; -} - -void bflb_iso11898_set_mode(struct bflb_device_s *dev, uint8_t mode) -{ - uint32_t reg_base; - uint32_t regval; - - reg_base = dev->reg_base; - /* first enter reset mode */ - regval = getreg32(reg_base + ISO11898_MODE_OFFSET); - regval |= ISO11898_RESET_REQUEST; - putreg32(regval, reg_base + ISO11898_MODE_OFFSET); - - /* config mode */ - regval = getreg32(reg_base + ISO11898_MODE_OFFSET); - if (mode == ISO11898_MODE_NORMAL) { - regval &= ~ISO11898_LISTEN_ONLY; - regval &= ~ISO11898_SELF_TEST; - } else if (mode == ISO11898_MODE_LOOPBACK) { - regval &= ~ISO11898_LISTEN_ONLY; - regval |= ISO11898_SELF_TEST; - } else if (mode == ISO11898_MODE_SILENT) { - regval |= ISO11898_LISTEN_ONLY; - regval &= ~ISO11898_SELF_TEST; - } else if (mode == ISO11898_MODE_SILENT_LOOPBACK) { - regval |= ISO11898_LISTEN_ONLY; - regval |= ISO11898_SELF_TEST; - } else { - } - putreg32(regval, reg_base + ISO11898_MODE_OFFSET); - - /* last leave reset mode */ - regval = getreg32(reg_base + ISO11898_MODE_OFFSET); - regval &= ~ISO11898_RESET_REQUEST; - putreg32(regval, reg_base + ISO11898_MODE_OFFSET); -} - -uint8_t bflb_iso11898_get_mode(struct bflb_device_s *dev) -{ - uint32_t regval; - uint8_t silent, loopback; - - regval = getreg32(dev->reg_base + ISO11898_MODE_OFFSET); - if (regval & ISO11898_SELF_TEST) { - loopback = 1; - } else { - loopback = 0; - } - if (regval & ISO11898_LISTEN_ONLY) { - silent = 1; - } else { - silent = 0; - } - if (loopback && silent) { - return ISO11898_MODE_SILENT_LOOPBACK; - } else if (!loopback && silent) { - return ISO11898_MODE_SILENT; - } else if (loopback && !silent) { - return ISO11898_MODE_LOOPBACK; - } else { - return ISO11898_MODE_NORMAL; - } -} - -void bflb_iso11898_set_filter(struct bflb_device_s *dev, struct bflb_iso11898_filter_s *filter) -{ - uint32_t reg_base; - uint32_t regval; - uint8_t mode; - - reg_base = dev->reg_base; - /* first save mode */ - mode = bflb_iso11898_get_mode(dev); - - /* enter reset mode */ - regval = getreg32(reg_base + ISO11898_MODE_OFFSET); - regval |= ISO11898_RESET_REQUEST; - putreg32(regval, reg_base + ISO11898_MODE_OFFSET); - - /* config filter type */ - regval = getreg32(dev->reg_base + ISO11898_MODE_OFFSET); - if (filter->filter_type == ISO11898_FILTER_TYPE_SINGLE) { - regval |= ISO11898_FILTER_TYPE; - } else { - regval &= ~ISO11898_FILTER_TYPE; - } - putreg32(regval, reg_base + ISO11898_MODE_OFFSET); - - /* config filter code and mask */ - putreg32(filter->code0, reg_base + ISO11898_ACCEPTANCE_CODE_0_OFFSET); - putreg32(filter->code1, reg_base + ISO11898_ACCEPTANCE_CODE_1_OFFSET); - putreg32(filter->code2, reg_base + ISO11898_ACCEPTANCE_CODE_2_OFFSET); - putreg32(filter->code3, reg_base + ISO11898_ACCEPTANCE_CODE_3_OFFSET); - putreg32(filter->mask0, reg_base + ISO11898_ACCEPTANCE_MASK_0_OFFSET); - putreg32(filter->mask1, reg_base + ISO11898_ACCEPTANCE_MASK_1_OFFSET); - putreg32(filter->mask2, reg_base + ISO11898_ACCEPTANCE_MASK_2_OFFSET); - putreg32(filter->mask3, reg_base + ISO11898_ACCEPTANCE_MASK_3_OFFSET); - - /* restore saved mode */ - bflb_iso11898_set_mode(dev, mode); -} - -void bflb_iso11898_txint_mask(struct bflb_device_s *dev, bool mask) -{ - uint32_t reg_base; - uint32_t regval; - - reg_base = dev->reg_base; - regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET); - if (mask) { - regval &= ~ISO11898_TRANSMIT_INT_EN; - } else { - regval |= ISO11898_TRANSMIT_INT_EN; - } - - putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET); -} - -void bflb_iso11898_rxint_mask(struct bflb_device_s *dev, bool mask) -{ - uint32_t reg_base; - uint32_t regval; - - reg_base = dev->reg_base; - regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET); - if (mask) { - regval &= ~ISO11898_RECEIVE_INT_EN; - } else { - regval |= ISO11898_RECEIVE_INT_EN; - } - - putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET); -} - -void bflb_iso11898_errint_mask(struct bflb_device_s *dev, bool mask) -{ - uint32_t reg_base; - uint32_t regval; - - reg_base = dev->reg_base; - regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET); - if (mask) { - regval &= ~ISO11898_ERROR_INT_EN; - regval &= ~ISO11898_DATA_OVERRUN_INT_EN; - regval &= ~ISO11898_ERROR_PASSIVE_INT_EN; - regval &= ~ISO11898_ARB_LOST_INT_EN; - regval &= ~ISO11898_BUS_ERROR_INT_EN; - } else { - regval |= ISO11898_ERROR_INT_EN; - regval |= ISO11898_DATA_OVERRUN_INT_EN; - regval |= ISO11898_ERROR_PASSIVE_INT_EN; - regval |= ISO11898_ARB_LOST_INT_EN; - regval |= ISO11898_BUS_ERROR_INT_EN; - } - - putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET); -} - -uint32_t bflb_iso11898_get_int_status(struct bflb_device_s *dev) -{ - return getreg32(dev->reg_base + ISO11898_INTERRUPT_OFFSET); -} \ No newline at end of file diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c index 0414102e5b..d23f04578d 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c @@ -545,6 +545,26 @@ void bflb_mjpeg_set_yuv420sp_cam_input(struct bflb_device_s *dev, uint8_t yy, ui putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET); } +void bflb_mjpeg_update_input_output_buff(struct bflb_device_s *dev, void *input_buf0, void *input_buf1, void *output_buff, size_t output_buff_size) +{ + uint32_t reg_base; + + reg_base = dev->reg_base; + + if (input_buf0 != NULL) { + putreg32((uint32_t)input_buf0, reg_base + MJPEG_YY_FRAME_ADDR_OFFSET); + } + + if (input_buf1 != NULL) { + putreg32((uint32_t)input_buf1, reg_base + MJPEG_UV_FRAME_ADDR_OFFSET); + } + + if (output_buff != NULL) { + putreg32((uint32_t)output_buff, reg_base + MJPEG_JPEG_FRAME_ADDR_OFFSET); + putreg32((uint32_t)output_buff_size / 128, reg_base + MJPEG_JPEG_STORE_MEMORY_OFFSET); + } +} + int bflb_mjpeg_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) { int ret = 0; diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_platform_dma.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_platform_dma.c new file mode 100755 index 0000000000..d89dbd2bcb --- /dev/null +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_platform_dma.c @@ -0,0 +1,95 @@ +#include "bflb_platform_dma.h" +#include "bflb_l1c.h" +#include "hardware/platform_dma_reg.h" + +struct bflb_platform_dma_env_tag dma_env; + +void bflb_platform_dma_init(struct bflb_device_s *dev) +{ + memset(dma_env.last_dma, 0, sizeof(dma_env.last_dma)); + + // configure the channel priorities + putreg32(0x0C, dev->reg_base + DMA_ARBITRATION_OFFSET); + + putreg32(0x04, dev->reg_base + 0x44); + + // configure the interrupts (enable all interrupts) + putreg32(DMA_ERROR_BIT | DMA_LLI_IRQ_MASK, dev->reg_base + DMA_INT_UNMASK_SET_OFFSET); +} + +void bflb_platform_dma_push(struct bflb_device_s *dev, struct bflb_platform_dma_desc *first, struct bflb_platform_dma_desc *last) +{ + uint32_t value; + uintptr_t flag; + uint32_t channel_idx; + + channel_idx = dev->idx; + + // current DMA descriptor is pushed at the end of the list + last->next = 0; + + // prevent accesses to the same DMA channel from both BK and IRQ simultaneously + flag = bflb_irq_save(); + + // set the MUTEX + putreg32(1 << channel_idx, dev->reg_base + DMA_CHANNEL_MUTEX_SET_OFFSET); + + // read the root in the DMA HW + if (channel_idx == 4) { + value = getreg32(dev->reg_base + DMA_CH4_LLI_ROOT_OFFSET); + } else { + value = getreg32(dev->reg_base + DMA_CH_LLI_ROOT_OFFSET + channel_idx * 4); + } + + // check if the root is empty + if (value) { + // append the descriptor to the last LLI of the list + dma_env.last_dma[channel_idx]->next = (uint32_t)first; + + // clear the MUTEX + putreg32(1 << channel_idx, dev->reg_base + DMA_CHANNEL_MUTEX_CLEAR_OFFSET); + } else { + // write directly the DMA to the root + if (channel_idx == 4) { + putreg32((uint32_t)first, dev->reg_base + DMA_CH4_LLI_ROOT_OFFSET); + } else { + putreg32((uint32_t)first, dev->reg_base + DMA_CH_LLI_ROOT_OFFSET + channel_idx * 4); + } + } + + // save the new last LLI descriptor on this channel + dma_env.last_dma[channel_idx] = last; + + bflb_irq_restore(flag); +} + +void bflb_platform_dma_buserr_isr(struct bflb_device_s *dev) +{ + // For now consider this error as a fatal one + while (1) { + } +} + +void bflb_platform_dma_wait_eot(struct bflb_device_s *dev) +{ + uint32_t channel_idx; + + channel_idx = dev->idx; + uint32_t stopped = 0; + if (channel_idx < 5) { + do { + stopped = getreg32(dev->reg_base + DMA_INT_RAWSTATUS_OFFSET); + stopped = (stopped >> (20 + channel_idx)) & 0x01; + } while (!stopped); + } +} + +void bflb_platform_dma_clear_eot(struct bflb_device_s *dev) +{ + uint32_t channel_idx; + + channel_idx = dev->idx; + if (channel_idx < 5) { + putreg32(1 << (20 + channel_idx), dev->reg_base + DMA_INT_ACK_OFFSET); + } +} \ No newline at end of file diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c index 6287a8a7d8..d2ca2801a7 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c @@ -9,19 +9,36 @@ #define BFLB_RTC_BASE 0x2008F000 #endif -void bflb_rtc_set_time(struct bflb_device_s *dev, uint64_t time) +void bflb_rtc_disable(struct bflb_device_s *dev) { uint32_t reg_base; uint32_t regval; - uint32_t comp_l, comp_h; reg_base = BFLB_RTC_BASE; /* Clear & Disable RTC counter */ regval = getreg32(reg_base + HBN_CTL_OFFSET); + regval &=~ HBN_RTC_ENABLE; + putreg32(regval, reg_base + HBN_CTL_OFFSET); +} + +void bflb_rtc_set_time(struct bflb_device_s *dev, uint64_t time) +{ + uint32_t reg_base; + uint32_t regval; + uint64_t rtc_cnt; + + reg_base = BFLB_RTC_BASE; + + /* Clear RTC Control */ + regval = getreg32(reg_base + HBN_CTL_OFFSET); regval &= ~HBN_RTC_CTL_MASK; putreg32(regval, reg_base + HBN_CTL_OFFSET); + regval |= HBN_RTC_DLY_OPTION; + regval |= HBN_RTC_BIT39_0_COMPARE; + putreg32(regval, reg_base + HBN_CTL_OFFSET); + /* Tigger RTC val read */ regval = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET); regval |= HBN_RTC_TIME_LATCH; @@ -30,25 +47,20 @@ void bflb_rtc_set_time(struct bflb_device_s *dev, uint64_t time) putreg32(regval, reg_base + HBN_RTC_TIME_H_OFFSET); /* Read RTC val */ - comp_l = getreg32(reg_base + HBN_RTC_TIME_L_OFFSET); - comp_h = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET) & 0xff; + rtc_cnt = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET) & 0xff; + rtc_cnt <<= 32; + rtc_cnt |= getreg32(reg_base + HBN_RTC_TIME_L_OFFSET); /* calculate RTC Comp time */ - comp_l += (uint32_t)(time & 0xFFFFFFFF); - comp_h += (uint32_t)((time >> 32) & 0xFFFFFFFF); + rtc_cnt += time; /* Set RTC Comp time */ - putreg32(comp_l, reg_base + HBN_TIME_L_OFFSET); - putreg32(comp_h, reg_base + HBN_TIME_H_OFFSET); - - regval = getreg32(reg_base + HBN_CTL_OFFSET); - regval |= HBN_RTC_DLY_OPTION; - regval |= (0x01 << 1); - putreg32(regval, reg_base + HBN_CTL_OFFSET); + putreg32((uint32_t)rtc_cnt, reg_base + HBN_TIME_L_OFFSET); + putreg32((uint32_t)(rtc_cnt >> 32) & 0xff, reg_base + HBN_TIME_H_OFFSET); /* Enable RTC Counter */ regval = getreg32(reg_base + HBN_CTL_OFFSET); - regval |= (1 << 0); + regval |= HBN_RTC_ENABLE; putreg32(regval, reg_base + HBN_CTL_OFFSET); } diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_trng.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_trng.c index 5358485705..bf302e836d 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_trng.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_trng.c @@ -134,7 +134,7 @@ int bflb_trng_readlen(uint8_t *data, uint32_t len) return 0; } -long random(void) +__WEAK long random(void) { uint32_t data[8]; struct bflb_device_s *trng; diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi.c index de9da2599d..42e6d09067 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi.c @@ -516,6 +516,7 @@ int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) int ret = 0; uint32_t reg_base; uint32_t regval; + uint32_t div; reg_base = dev->reg_base; @@ -578,6 +579,118 @@ int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) putreg32(regval, reg_base + SPI_CONFIG_OFFSET); break; + case SPI_CMD_SET_MODE: + /* set spi mode (clk phase and polarity), arg use @ref SPI_MODE*/ + regval = getreg32(reg_base + SPI_CONFIG_OFFSET); + switch (arg) { + case SPI_MODE0: + /* CPOL=0 CHPHA=0 */ + regval &= ~SPI_CR_SPI_SCLK_POL; + regval |= SPI_CR_SPI_SCLK_PH; + break; + case SPI_MODE1: + /* CPOL=0 CHPHA=1 */ + regval &= ~SPI_CR_SPI_SCLK_POL; + regval &= ~SPI_CR_SPI_SCLK_PH; + break; + case SPI_MODE2: + /* CPOL=1 CHPHA=0 */ + regval |= SPI_CR_SPI_SCLK_POL; + regval |= SPI_CR_SPI_SCLK_PH; + break; + case SPI_MODE3: + /* CPOL=1 CHPHA=1 */ + regval |= SPI_CR_SPI_SCLK_POL; + regval &= ~SPI_CR_SPI_SCLK_PH; + break; + default: + break; + } + putreg32(regval, reg_base + SPI_CONFIG_OFFSET); + break; + + case SPI_CMD_GET_MODE: + /* get spi mode (clk phase and polarity), ret @ref SPI_MODE*/ + regval = getreg32(reg_base + SPI_CONFIG_OFFSET); + if (regval & SPI_CR_SPI_SCLK_POL) { + if (regval & SPI_CR_SPI_SCLK_PH) { + ret = SPI_MODE2; + } else { + ret = SPI_MODE3; + } + } else { + if (regval & SPI_CR_SPI_SCLK_PH) { + ret = SPI_MODE0; + } else { + ret = SPI_MODE1; + } + } + break; + + case SPI_CMD_SET_FREQ: + /* set clk frequence, should be less than spi_clk/2*/ + /* integer frequency segmentation by rounding */ + div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_SPI, dev->idx) / 2 * 10 / arg + 5) / 10; + div = (div) ? (div - 1) : 0; + div = (div > 0xff) ? 0xff : div; + + regval = 0; + regval |= div << SPI_CR_SPI_PRD_D_PH_0_SHIFT; + regval |= div << SPI_CR_SPI_PRD_D_PH_1_SHIFT; + regval |= div << SPI_CR_SPI_PRD_S_SHIFT; + regval |= div << SPI_CR_SPI_PRD_P_SHIFT; + putreg32(regval, reg_base + SPI_PRD_0_OFFSET); + break; + + case SPI_CMD_GET_FREQ: + /* get clk frequence */ + regval = getreg32(reg_base + SPI_PRD_0_OFFSET); + div = (regval & SPI_CR_SPI_PRD_D_PH_0_MASK) >> SPI_CR_SPI_PRD_D_PH_0_SHIFT; + div += (regval & SPI_CR_SPI_PRD_D_PH_1_MASK) >> SPI_CR_SPI_PRD_D_PH_1_SHIFT; + + ret = bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_SPI, dev->idx) / div; + break; + + case SPI_CMD_SET_BIT_ORDER: + /* set bit order, arg use @ref SPI_BIT_ORDER */ + regval = getreg32(reg_base + SPI_CONFIG_OFFSET); + if (arg == SPI_BIT_LSB) { + regval |= SPI_CR_SPI_BIT_INV; + } else { + regval &= ~SPI_CR_SPI_BIT_INV; + } + putreg32(regval, reg_base + SPI_CONFIG_OFFSET); + break; + + case SPI_CMD_GET_BIT_ORDER: + regval = getreg32(reg_base + SPI_CONFIG_OFFSET); + if (regval & SPI_CR_SPI_BIT_INV) { + ret = SPI_BIT_LSB; + } else { + ret = !SPI_BIT_LSB; + } + break; + + case SPI_CMD_SET_BYTE_ORDER: + /* set byte order, arg use @ref SPI_BYTE_ORDER */ + regval = getreg32(reg_base + SPI_CONFIG_OFFSET); + if (arg == SPI_BYTE_LSB) { + regval &= ~SPI_CR_SPI_BYTE_INV; + } else { + regval |= SPI_CR_SPI_BYTE_INV; + } + putreg32(regval, reg_base + SPI_CONFIG_OFFSET); + break; + + case SPI_CMD_GET_BYTE_ORDER: + regval = getreg32(reg_base + SPI_CONFIG_OFFSET); + if (regval & SPI_CR_SPI_BYTE_INV) { + ret = !SPI_BYTE_LSB; + } else { + ret = SPI_BYTE_LSB; + } + break; + default: ret = -EPERM; break; diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_uart.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_uart.c index acd93c1e08..abed55c829 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_uart.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_uart.c @@ -527,18 +527,14 @@ int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET); break; #endif - case UART_CMD_SET_TX_RX_EN: - /* Set tx and rx enable */ - tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); + case UART_CMD_SET_GLITCH_VALUE: rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET); - tx_tmp &= ~UART_CR_UTX_EN; - rx_tmp &= ~UART_CR_URX_EN; + rx_tmp &= ~UART_CR_URX_DEG_CNT_MASK; + rx_tmp &= ~UART_CR_URX_DEG_EN; if (arg) { - tx_tmp |= UART_CR_UTX_EN; - rx_tmp |= UART_CR_URX_EN; + rx_tmp |= (arg << UART_CR_URX_DEG_CNT_SHIFT) & UART_CR_URX_DEG_CNT_MASK; + rx_tmp |= UART_CR_URX_DEG_EN; } - - putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET); putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET); break; #if !defined(BL602) && !defined(BL702) @@ -668,17 +664,15 @@ int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) case UART_CMD_SET_TX_TRANSFER_LEN: /* Set tx transfer length */ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); - + tx_tmp &= ~UART_CR_UTX_LEN_MASK; tx_tmp |= ((arg - 1) << UART_CR_UTX_LEN_SHIFT); - putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET); break; case UART_CMD_SET_RX_TRANSFER_LEN: /* Set rx transfer length */ rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET); - + rx_tmp &= ~UART_CR_URX_LEN_MASK; rx_tmp |= ((arg - 1) << UART_CR_URX_LEN_SHIFT); - putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET); break; case UART_CMD_SET_TX_EN: @@ -711,6 +705,24 @@ int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) return ((rx_tmp & UART_STS_URX_BCR_COUNT_MASK) >> UART_STS_URX_BCR_COUNT_SHIFT); break; #endif + case UART_CMD_SET_CTS_EN: + tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); + if (arg) { + tx_tmp |= UART_CR_UTX_CTS_EN; + } else { + tx_tmp &= ~UART_CR_UTX_CTS_EN; + } + putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET); + case UART_CMD_SET_TX_FIFO_THREHOLD: + tx_tmp = getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET); + tx_tmp &= ~UART_TX_FIFO_TH_MASK; + tx_tmp |= (arg << UART_TX_FIFO_TH_SHIFT) & UART_TX_FIFO_TH_MASK; + putreg32(tx_tmp, reg_base + UART_FIFO_CONFIG_1_OFFSET); + case UART_CMD_SET_RX_FIFO_THREHOLD: + rx_tmp = getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET); + rx_tmp &= ~UART_RX_FIFO_TH_MASK; + rx_tmp |= (arg << UART_RX_FIFO_TH_SHIFT) & UART_RX_FIFO_TH_MASK; + putreg32(rx_tmp, reg_base + UART_FIFO_CONFIG_1_OFFSET); default: ret = -EPERM; break; diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c index 88d90c9d95..89f8ad7695 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c @@ -293,6 +293,21 @@ int usb_dc_init(void) return 0; } +int usb_dc_deinit(void) +{ + uint32_t regval; + + regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET); + regval &= ~USB_CR_USB_EN; + putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET); + + regval = getreg32(BL702_GLB_BASE + GLB_USB_XCVR_OFFSET); + regval &= ~GLB_USB_ENUM; + putreg32(regval, BL702_GLB_BASE + GLB_USB_XCVR_OFFSET); + + return 0; +} + int usbd_set_address(const uint8_t addr) { uint32_t regval; diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c index 497f928fbe..537c8f3a9d 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c @@ -593,6 +593,24 @@ int usb_dc_init(void) int usb_dc_deinit(void) { + uint32_t regval; + + /* disable global irq */ + regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET); + regval &= ~USB_GLINT_EN_HOV; + putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET); + + regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_UNPLUG; + putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET); + + regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET); + regval |= USB_SFRST_HOV; + putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET); + + while (getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET) & USB_SFRST_HOV) { + } + return 0; } @@ -847,24 +865,21 @@ int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len) return -2; } + if (data_len == 0) { + return 0; + } + g_bl_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; g_bl_udc.out_ep[ep_idx].xfer_len = data_len; g_bl_udc.out_ep[ep_idx].actual_xfer_len = 0; g_bl_udc.out_ep[ep_idx].ep_active = true; if (ep_idx == 0) { - if (data_len == 0) { - g_bl_udc.out_ep[ep_idx].ep_active = false; - } else { - data_len = MIN(data_len, g_bl_udc.out_ep[ep_idx].ep_mps); - g_bl_udc.in_ep[ep_idx].xfer_len = data_len; - bflb_usb_vdma_start_read(USB_FIFO_CXF, data, data_len); - } + data_len = MIN(data_len, g_bl_udc.out_ep[ep_idx].ep_mps); + g_bl_udc.out_ep[ep_idx].xfer_len = data_len; + bflb_usb_vdma_start_read(USB_FIFO_CXF, data, data_len); } else { - if (data_len == 0) { - } else { - bflb_usb_vdma_start_read(usb_get_transfer_fifo(ep_idx), data, data_len); - } + bflb_usb_vdma_start_read(usb_get_transfer_fifo(ep_idx), data, data_len); } return 0; } @@ -897,6 +912,13 @@ void USBD_IRQHandler(int irq, void *arg) if (subgroup_intstatus & USB_SUSP_INT) { bflb_usb_source_group_int_clear(2, USB_SUSP_INT); + bflb_usb_reset_fifo(USB_FIFO_F0); + bflb_usb_reset_fifo(USB_FIFO_F1); + bflb_usb_reset_fifo(USB_FIFO_F2); + bflb_usb_reset_fifo(USB_FIFO_F3); + bflb_usb_reset_fifo(USB_FIFO_CXF); + + memset(&g_bl_udc, 0, sizeof(g_bl_udc)); usbd_event_suspend_handler(); } if (subgroup_intstatus & USB_RESM_INT) { @@ -970,7 +992,7 @@ void USBD_IRQHandler(int irq, void *arg) g_bl_udc.in_ep[ep_idx].ep_active = 0; g_bl_udc.in_ep[ep_idx].actual_xfer_len = g_bl_udc.in_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i); usbd_event_ep_in_complete_handler(ep_idx | 0x80, g_bl_udc.in_ep[ep_idx].actual_xfer_len); - } else { + } else if (g_bl_udc.out_ep[ep_idx].ep_active) { g_bl_udc.out_ep[ep_idx].ep_active = 0; g_bl_udc.out_ep[ep_idx].actual_xfer_len = g_bl_udc.out_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i); usbd_event_ep_out_complete_handler(ep_idx & 0x7f, g_bl_udc.out_ep[ep_idx].actual_xfer_len); diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.h index de58709eac..30add9cd6a 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.h @@ -73,7 +73,9 @@ #endif #if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P) +#ifndef CONFIG_DISABLE_SBUS2_ENABLE_SUPPORT #define BFLB_SF_CTRL_SBUS2_ENABLE +#endif #define BFLB_SF_CTRL_32BITS_ADDR_ENABLE #define BFLB_SF_CTRL_AES_XTS_ENABLE #endif diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_pm.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_pm.h new file mode 100755 index 0000000000..8bb4c70c31 --- /dev/null +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_pm.h @@ -0,0 +1,2 @@ + +void PDS_Mode_Enter(PDS_APP_CFG_Type *cfg); diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_hbn.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_hbn.c index 9f64ea3b23..72800e01f8 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_hbn.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_hbn.c @@ -179,7 +179,7 @@ void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) SFlash_Powerdown(); } #endif -#if 0 +#if 1 /****************************************************************************/ /** * @brief Enable HBN mode * @@ -261,8 +261,8 @@ void ATTR_TCM_SECTION HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoL tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); - *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT0_IRQn) = 0; - *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT1_IRQn) = 0; + bflb_irq_clear_pending(HBN_OUT0_IRQn); + bflb_irq_clear_pending(HBN_OUT1_IRQn); BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_pm.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_pm.c new file mode 100755 index 0000000000..4959d8884f --- /dev/null +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_pm.c @@ -0,0 +1,609 @@ +/** + ****************************************************************************** + * @file bl602_pm.c + * @version V1.0 + * @date + * @brief This file is the peripheral case c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "bl602.h" +#include "bl602_aon.h" +#include "bl602_hbn.h" +#include "bl602_glb.h" +#include "bl602_pds.h" +#include "bflb_sf_cfg.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sflash.h" +#include "bflb_spi.h" +#include "bflb_xip_sflash.h" +#include "bl602_common.h" +#include "bflb_sec_trng.h" +/** @addtogroup BL602_Peripheral_Case + * @{ + */ + +/** @addtogroup PDS_SETTING + * @{ + */ + +/** @defgroup PDS_SETTING_Private_Macros + * @{ + */ + +/*@} end of group PDS_SETTING_Private_Macros */ + +/** @defgroup PDS_SETTING_Private_Types + * @{ + */ + +/*@} end of group PDS_SETTING_Private_Types */ + +/** @defgroup PDS_SETTING_Private_Variables + * @{ + */ +PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel0 = { + .pdsCtl = { + .pdsStart =1, + .sleepForever =0, + .xtalForceOff =0, + .saveWiFiState=0, + .dcdc18Off =1, + .bgSysOff =1, + .clkOff =1, + .memStby =1, + .isolation =1, + .waitXtalRdy =0, + .pdsPwrOff =1, + .xtalOff =0, + .socEnbForceOn=1, + .pdsRstSocEn =0, + .pdsRC32mOn =0, + .pdsLdoVselEn =0, + .wfiMask =0, /* aviod cpu catch wfi signal */ + .ldo11Off =1, /* E_ITEM_03 */ + .pdsLdoVol =0xA, + .pdsCtlRfSel =3, + .pdsCtlPllSel =0, + }, + .pdsCtl2 = { + .forceCpuPwrOff =0, + .forceWbPwrOff =0, + .forceCpuIsoPwrOff=0, + .forceWbIsoPwrOff =0, + .forceCpuPdsRst =0, + .forceWbPdsRst =0, + .forceCpuMemStby =0, + .forceWbMemStby =0, + .forceCpuGateClk =0, + .forceWbGateClk =0, + }, + .pdsCtl3 = { + .forceMiscPwrOff =0, + .forceMiscIsoEn =0, + .forceMiscPdsRst =0, + .forceMiscMemStby=0, + .forceMiscGateClk=0, + .CpuIsoEn =0, + .WbIsoEn =0, + .MiscIsoEn =0, + }, + .pdsCtl4 = { + .cpuPwrOff =0, + .cpuRst =0, + .cpuMemStby =1, + .cpuGateClk =1, + .WbPwrOff =0, + .WbRst =0, + .WbMemStby =1, + .WbGateClk =1, + .MiscPwrOff =0, + .MiscRst =0, + .MiscMemStby=1, + .MiscGateClk=1, + } +}; +PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel1 = { + .pdsCtl = { + .pdsStart =1, + .sleepForever =0, + .xtalForceOff =0, + .saveWiFiState=0, + .dcdc18Off =1, + .bgSysOff =1, + .clkOff =1, + .memStby =1, + .isolation =1, + .waitXtalRdy =0, + .pdsPwrOff =1, + .xtalOff =0, + .socEnbForceOn=1, + .pdsRstSocEn =0, + .pdsRC32mOn =0, + .pdsLdoVselEn =0, + .wfiMask =0, /* aviod cpu catch wfi signal */ + .ldo11Off =1, /* E_ITEM_03 */ + .pdsLdoVol =0xA, + .pdsCtlRfSel =2, + .pdsCtlPllSel =0, + }, + .pdsCtl2 = { + .forceCpuPwrOff =0, + .forceWbPwrOff =0, + .forceCpuIsoPwrOff=0, + .forceWbIsoPwrOff =0, + .forceCpuPdsRst =0, + .forceWbPdsRst =0, + .forceCpuMemStby =0, + .forceWbMemStby =0, + .forceCpuGateClk =0, + .forceWbGateClk =0, + }, + .pdsCtl3 = { + .forceMiscPwrOff =0, + .forceMiscIsoEn =0, + .forceMiscPdsRst =0, + .forceMiscMemStby=0, + .forceMiscGateClk=0, + .CpuIsoEn =0, + .WbIsoEn =1, + .MiscIsoEn =0, + }, + .pdsCtl4 = { + .cpuPwrOff =0, + .cpuRst =0, + .cpuMemStby =1, + .cpuGateClk =1, + .WbPwrOff =1, + .WbRst =1, + .WbMemStby =1, + .WbGateClk =1, + .MiscPwrOff =0, + .MiscRst =0, + .MiscMemStby=1, + .MiscGateClk=1, + } +}; +PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel2 = { + .pdsCtl = { + .pdsStart =1, + .sleepForever =0, + .xtalForceOff =0, + .saveWiFiState=0, + .dcdc18Off =1, + .bgSysOff =1, + .clkOff =1, + .memStby =1, + .isolation =1, + .waitXtalRdy =0, + .pdsPwrOff =1, + .xtalOff =0, + .socEnbForceOn=1, + .pdsRstSocEn =0, + .pdsRC32mOn =0, + .pdsLdoVselEn =0, + .wfiMask =0, /* aviod cpu catch wfi signal */ + .ldo11Off =1, /* E_ITEM_03 */ + .pdsLdoVol =0xA, + .pdsCtlRfSel =3, + .pdsCtlPllSel =0, + }, + .pdsCtl2 = { + .forceCpuPwrOff =0, + .forceWbPwrOff =0, + .forceCpuIsoPwrOff=0, + .forceWbIsoPwrOff =0, + .forceCpuPdsRst =0, + .forceWbPdsRst =0, + .forceCpuMemStby =0, + .forceWbMemStby =0, + .forceCpuGateClk =0, + .forceWbGateClk =0, + }, + .pdsCtl3 = { + .forceMiscPwrOff =0, + .forceMiscIsoEn =0, + .forceMiscPdsRst =0, + .forceMiscMemStby=0, + .forceMiscGateClk=0, + .CpuIsoEn =1, + .WbIsoEn =0, + .MiscIsoEn =0, + }, + .pdsCtl4 = { + .cpuPwrOff =1, + .cpuRst =1, + .cpuMemStby =1, + .cpuGateClk =1, + .WbPwrOff =0, + .WbRst =0, + .WbMemStby =1, + .WbGateClk =1, + .MiscPwrOff =0, + .MiscRst =0, + .MiscMemStby=1, + .MiscGateClk=1, + } +}; +PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = { + .pdsCtl = { + .pdsStart =1, + .sleepForever =0, + .xtalForceOff =0, + .saveWiFiState=0, + .dcdc18Off =1, + .bgSysOff =1, + .clkOff =1, + .memStby =1, + .isolation =1, + .waitXtalRdy =0, + .pdsPwrOff =1, + .xtalOff =1, + .socEnbForceOn=1, + .pdsRstSocEn =0, + .pdsRC32mOn =0, + .pdsLdoVselEn =0, + .wfiMask =0, /* aviod cpu catch wfi signal */ + .ldo11Off =0, /* E_ITEM_03 */ + .pdsLdoVol =0xA, + .pdsCtlRfSel =2, + .pdsCtlPllSel =0, + }, + .pdsCtl2 = { + .forceCpuPwrOff =0, + .forceWbPwrOff =0, + .forceCpuIsoPwrOff=0, + .forceWbIsoPwrOff =0, + .forceCpuPdsRst =0, + .forceWbPdsRst =0, + .forceCpuMemStby =0, + .forceWbMemStby =0, + .forceCpuGateClk =0, + .forceWbGateClk =0, + }, + .pdsCtl3 = { + .forceMiscPwrOff =0, + .forceMiscIsoEn =0, + .forceMiscPdsRst =0, + .forceMiscMemStby=0, + .forceMiscGateClk=0, + .CpuIsoEn =1, + .WbIsoEn =1, + .MiscIsoEn =0, + }, + .pdsCtl4 = { + .cpuPwrOff =1, + .cpuRst =1, + .cpuMemStby =1, + .cpuGateClk =1, + .WbPwrOff =1, + .WbRst =1, + .WbMemStby =1, + .WbGateClk =1, + .MiscPwrOff =0, + .MiscRst =0, + .MiscMemStby=1, + .MiscGateClk=1, + } +}; +PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = { + .pdsCtl = { + .pdsStart =1, + .sleepForever =0, + .xtalForceOff =0, + .saveWiFiState=0, + .dcdc18Off =1, + .bgSysOff =1, + .clkOff =1, + .memStby =1, + .isolation =1, + .waitXtalRdy =0, + .pdsPwrOff =1, + .xtalOff =0, + .socEnbForceOn=0, + .pdsRstSocEn =0, + .pdsRC32mOn =0, + .pdsLdoVselEn =0, + .wfiMask =0, /* aviod cpu catch wfi signal */ + .ldo11Off =0, /* E_ITEM_03 */ + .pdsLdoVol =0xA, + .pdsCtlRfSel =2, + .pdsCtlPllSel =0, + }, + .pdsCtl2 = { + .forceCpuPwrOff =0, + .forceWbPwrOff =0, + .forceCpuIsoPwrOff=0, + .forceWbIsoPwrOff =0, + .forceCpuPdsRst =0, + .forceWbPdsRst =0, + .forceCpuMemStby =0, + .forceWbMemStby =0, + .forceCpuGateClk =0, + .forceWbGateClk =0, + }, + .pdsCtl3 = { + .forceMiscPwrOff =0, + .forceMiscIsoEn =0, + .forceMiscPdsRst =0, + .forceMiscMemStby=0, + .forceMiscGateClk=0, + .CpuIsoEn =1, + .WbIsoEn =1, + .MiscIsoEn =1, + }, + .pdsCtl4 = { + .cpuPwrOff =1, + .cpuRst =1, + .cpuMemStby =1, + .cpuGateClk =1, + .WbPwrOff =1, + .WbRst =1, + .WbMemStby =1, + .WbGateClk =1, + .MiscPwrOff =1, + .MiscRst =1, + .MiscMemStby=1, + .MiscGateClk=1, + } +}; +PDS_RAM_CFG_Type ATTR_TCM_CONST_SECTION ramCfg = { + .PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET =1, + .PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET=1, + .PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET=1, + .PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET=1, + .PDS_RAM_CFG_0KB_16KB_CPU_RAM_SLP =0, + .PDS_RAM_CFG_16KB_32KB_CPU_RAM_SLP=0, + .PDS_RAM_CFG_32KB_48KB_CPU_RAM_SLP=0, + .PDS_RAM_CFG_48KB_64KB_CPU_RAM_SLP=0, +}; + + +/*@} end of group PDS_SETTING_Private_Variables */ + +/** @defgroup PDS_SETTING_Global_Variables + * @{ + */ + +/*@} end of group PDS_SETTING_Global_Variables */ + +/** @defgroup PDS_SETTING_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PDS_SETTING_Private_Fun_Declaration */ + +/** @defgroup PDS_SETTING_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief PDS update flash_ctrl setting + * + * @param fastClock: fast clock + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION PDS_Update_Flash_Ctrl_Setting(uint8_t fastClock) +{ + if(fastClock){ + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_80M, 0); + }else{ + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XTAL, 0); + } + bflb_sf_ctrl_set_clock_delay(fastClock); +} + +/****************************************************************************//** + * @brief PDS power on flash + * + * @param cfg: PDS app config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION PDS_Power_On_Flash(PDS_APP_CFG_Type *cfg) +{ + /* Init flash gpio */ + bflb_sf_cfg_init_flash_gpio(0, 1); + + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + + /* Restore flash */ + bflb_sflash_restore_from_powerdown(cfg->flashCfg, cfg->flashContRead, 0); +} + + +/****************************************************************************//** + * @brief power down sleep mode test function + * + * @param cfg: PDS app config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION PDS_Mode_Enter(PDS_APP_CFG_Type *cfg) +{ + PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL; + + if(cfg->useXtal32k){ + HBN_32K_Sel(HBN_32K_XTAL); + }else{ + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* always disable HBN pin pull up/down for reduce PDS0/1/2/3/7 current, 0x4000F014[16]=0 */ + /* system_init should set reg_en_hw_pu_pd = 0 */ + /* set reg_en_hw_pu_pd = 0, never reg_en_hw_pu_pd = 1 */ + HBN_Hw_Pu_Pd_Cfg(DISABLE); + + /* mask/unmask HBN pin wakeup, 0x4000F014[4:3] */ + HBN_Pin_WakeUp_Mask(~(cfg->pdsAonGpioWakeupSrc)); + if(cfg->pdsAonGpioWakeupSrc!=0){ + HBN_Aon_Pad_IeSmt_Cfg(ENABLE); + HBN_GPIO_INT_Enable(cfg->pdsAonGpioTrigType); + }else{ + HBN_Aon_Pad_IeSmt_Cfg(DISABLE); + } + + /* turn_off_sec_ring */ + // bflb_sec_eng_turn_off_sec_ring(); /* E_ITEM_04 */ + + /* disable sec_eng to reduce current which enabled by bflb_platform_init(0) */ + // bflb_sec_eng_trng_disable(); + + /* pre callback */ + if(cfg->preCbFun){ + cfg->preCbFun(); + } + + /* To make it simple and safe*/ + __disable_irq(); + + uint32_t sf_pin_select = 0; + if(cfg->powerDownFlash){ + uint32_t tmpVal = 0; + + /* get sw uasge 0 */ + // EF_Ctrl_Read_Sw_Usage(0, (uint32_t *)&tmpVal); + putreg32(tmpVal, 0x40007000 + 0x10); + // tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_0); + /* get flash type */ + sf_pin_select = (tmpVal >> 14) & 0x3f; + + HBN_Power_Down_Flash(cfg->flashCfg); + GLB_Select_External_Flash(); + /* PDS7 and HBN use HBN_Pull up since GPIO/pad turned into HZ */ + if(cfg->pdsLevel==7){ + HBN_Set_Embedded_Flash_Pullup(ENABLE); /* E_ITEM_06 */ + } + } + + HBN_Set_Ldo11_All_Vout(cfg->ldoLevel); + + /* if pdsLevel!=2 and pdsLevel!=3, power_down_flash_pin */ + if(cfg->turnOffFlashPad){ + if(cfg->pdsLevel==7){ + /* turn_off_internal_gpio, GPIO23 - GPIO28 */ + /* in PDS7, flash power down, flash GPIO turn to HighZ */ + }else{ + for(uint32_t pin=23;pin<29;pin++){ + GLB_GPIO_Set_PullUp(pin); + } + } + } + + /* power off PLL to reduce current */ + //if(cfg->turnoffPLL){ + GLB_Set_System_CLK(GLB_PLL_XTAL_NONE,GLB_SYS_CLK_RC32M); + PDS_Update_Flash_Ctrl_Setting(0); + PDS_Power_Off_PLL(); + //AON_Power_Off_XTAL(); + //} + + if(cfg->pdsLevel==0){ + pPdsCfg = &pdsCfgLevel0; + }else if(cfg->pdsLevel==1){ + pPdsCfg = &pdsCfgLevel1; + }else if(cfg->pdsLevel==2){ + pPdsCfg = &pdsCfgLevel2; + }else if(cfg->pdsLevel==3){ + pPdsCfg = &pdsCfgLevel3; + }else if(cfg->pdsLevel==7){ + pPdsCfg = &pdsCfgLevel7; + }else{ + /* pdsLevel error */ + while(1){ + BL602_Delay_MS(500); + } + } + + pPdsCfg->pdsCtl.pdsLdoVol = cfg->ldoLevel; + pPdsCfg->pdsCtl.pdsLdoVselEn = 1; + + if(!(cfg->turnOffRF)){ + pPdsCfg->pdsCtl.pdsCtlRfSel = 0; + } + + /* config ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */ + AON_Set_LDO11_SOC_Sstart_Delay(0x2); + + *((volatile uint32_t *)(GLB_BASE + 0x50)) |= (1 << 8); + *((volatile uint32_t *)(GLB_BASE + 0x50)) |= (0xF << 0); + + if(cfg->ocramRetetion){ + PDS_Default_Level_Config(pPdsCfg,&ramCfg,cfg->sleepTime); + }else{ + PDS_Default_Level_Config(pPdsCfg,NULL,cfg->sleepTime); + } + __WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */ + + /* System will Reset when PDS2\3\7 Entry Fail */ + if (cfg->pdsLevel > 1) { + GLB_SW_System_Reset(); + } + + /* Wake up from PDS */ + /* post callback, mainly for GPIO or peripherals on/off */ + if(cfg->postCbFun){ + cfg->postCbFun(); + } + + //if(cfg->turnoffPLL){ + GLB_Set_System_CLK(cfg->xtalType,GLB_SYS_CLK_PLL160M); + PDS_Update_Flash_Ctrl_Setting(1); + //} + + if(cfg->turnOffFlashPad){ + bflb_sf_cfg_init_flash_gpio((uint8_t)sf_pin_select, 1); + } + + if(cfg->powerDownFlash){ + HBN_Set_Embedded_Flash_Pullup(DISABLE); /* E_ITEM_06 */ + PDS_Power_On_Flash(cfg); /* call GLB_Select_Internal_Flash() in this API */ + } + + /* always turn_on_sec_ring, may cost more current */ + // SEC_Eng_Turn_On_Sec_Ring(); /* E_ITEM_04 */ + + /* always enable sec_eng, may cost more current */ + // Sec_Eng_Trng_Enable(); + + HBN_Aon_Pad_IeSmt_Cfg(ENABLE); + + __enable_irq(); +} + +/*@} end of group PDS_SETTING_Private_Functions */ + +/*@} end of group PDS_SETTING */ + +/*@} end of group BL602_Peripheral_Case */ \ No newline at end of file diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start.S index d1b331cb04..dd3cf2af8b 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start.S +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start.S @@ -78,7 +78,7 @@ __start: /* start load code to itcm like. */ jal start_load - jal System_Post_Init + call System_Post_Init /* At this point we can enter the C runtime's startup file. The arguments * to this function are designed to match those provided to the SEE, just @@ -86,7 +86,7 @@ __start: csrr a0, mhartid li a1, 0 li a2, 0 - jal entry + call entry csrci mstatus, (1 << 3) diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_acomp.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_acomp.h deleted file mode 100755 index f6b87526fa..0000000000 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_acomp.h +++ /dev/null @@ -1,214 +0,0 @@ -/** - ****************************************************************************** - * @file wb03_acomp.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __WB03_ACOMP_H__ -#define __WB03_ACOMP_H__ - -#include "aon_reg.h" -#include "bl616_common.h" - -/** @addtogroup BL606P_Peripheral_Driver - * @{ - */ - -/** @addtogroup ACOMP - * @{ - */ - -/** @defgroup ACOMP_Public_Types - * @{ - */ - -/** - * @brief Analog compare id type definition - */ -typedef enum { - AON_ACOMP0_ID, /*!< Analog compare 0 */ - AON_ACOMP1_ID, /*!< Analog compare 1 */ -} AON_ACOMP_ID_Type; - -/** - * @brief Analog compare level type definition - */ -typedef enum { - AON_ACOMP_SCALING_FACTOR_0P25 = 0x00, /*!< Analog compare level scaling factor 0.25 */ - AON_ACOMP_SCALING_FACTOR_0P5 = 0x10, /*!< Analog compare level scaling factor 0.5 */ - AON_ACOMP_SCALING_FACTOR_0P75 = 0x20, /*!< Analog compare level scaling factor 0.75 */ - AON_ACOMP_SCALING_FACTOR_1 = 0x30, /*!< Analog compare level scaling factor 1 */ -} AON_ACOMP_Scaling_Factor_Type; - -/** - * @brief Analog compare channel type definition - */ -typedef enum { - AON_ACOMP_CHAN_ADC0, /*!< Analog compare channel,ADC input channel 0 */ - AON_ACOMP_CHAN_ADC1, /*!< Analog compare channel,ADC input channel 1 */ - AON_ACOMP_CHAN_ADC2, /*!< Analog compare channel,ADC input channel 2 */ - AON_ACOMP_CHAN_ADC3, /*!< Analog compare channel,ADC input channel 3 */ - AON_ACOMP_CHAN_ADC4, /*!< Analog compare channel,ADC input channel 4 */ - AON_ACOMP_CHAN_ADC5, /*!< Analog compare channel,ADC input channel 5 */ - AON_ACOMP_CHAN_ADC6, /*!< Analog compare channel,ADC input channel 6 */ - AON_ACOMP_CHAN_ADC7, /*!< Analog compare channel,ADC input channel 7 */ - AON_ACOMP_CHAN_DACA, /*!< Analog compare channel,DAC output channel A */ - AON_ACOMP_CHAN_DACB, /*!< Analog compare channel,DAC output channel B */ - AON_ACOMP_CHAN_VREF_1P25V, /*!< Analog compare channel,1.25V ref voltage */ - AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_1, /*!< Analog compare channel,first,VIO * scaling factor */ - AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_2, /*!< Analog compare channel,second,VIO * scaling factor */ - AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_3, /*!< Analog compare channel,third,VIO * scaling factor */ - AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_4, /*!< Analog compare channel,forth,VIO * scaling factor */ - AON_ACOMP_CHAN_VSS, /*!< Analog compare channel,vss */ -} AON_ACOMP_Chan_Type; - -/** - * @brief Analog compare bias current control type definition - */ -typedef enum { - AON_ACOMP_BIAS_POWER_MODE1, /*!< Analog compare power mode 1,slow response mode */ - AON_ACOMP_BIAS_POWER_MODE2, /*!< Analog compare power mode 2,medium response mode */ - AON_ACOMP_BIAS_POWER_MODE3, /*!< Analog compare power mode 3,fast response mode */ - AON_ACOMP_BIAS_POWER_NONE, /*!< Analog compare power mode none */ -} AON_ACOMP_Bias_Prog_Type; - -/** - * @brief Analog compare hysteresis voltage type definition - */ -typedef enum { - AON_ACOMP_HYSTERESIS_VOLT_NONE, /*!< Analog compare hysteresis voltage none */ - AON_ACOMP_HYSTERESIS_VOLT_10MV, /*!< Analog compare hysteresis voltage 10mv */ - AON_ACOMP_HYSTERESIS_VOLT_20MV, /*!< Analog compare hysteresis voltage 20mv */ - AON_ACOMP_HYSTERESIS_VOLT_30MV, /*!< Analog compare hysteresis voltage 30mv */ - AON_ACOMP_HYSTERESIS_VOLT_40MV, /*!< Analog compare hysteresis voltage 40mv */ - AON_ACOMP_HYSTERESIS_VOLT_50MV, /*!< Analog compare hysteresis voltage 50mv */ - AON_ACOMP_HYSTERESIS_VOLT_60MV, /*!< Analog compare hysteresis voltage 60mv */ - AON_ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */ -} AON_ACOMP_Hysteresis_Volt_Type; - -/** - * @brief AON ACOMP configuration type definition - */ -typedef struct -{ - BL_Fun_Type muxEn; /*!< ACOMP mux enable */ - uint8_t posChanSel; /*!< ACOMP positive channel select */ - uint8_t negChanSel; /*!< ACOMP negtive channel select */ - uint8_t vioSel; /*!< ACOMP VIO voltage select, (vioSel/66)*avdd33 */ - AON_ACOMP_Scaling_Factor_Type scalingFactor; /*!< ACOMP scaling factor select factor */ - AON_ACOMP_Bias_Prog_Type biasProg; /*!< ACOMP bias current control */ - AON_ACOMP_Hysteresis_Volt_Type hysteresisPosVolt; /*!< ACOMP hysteresis voltage for positive */ - AON_ACOMP_Hysteresis_Volt_Type hysteresisNegVolt; /*!< ACOMP hysteresis voltage for negtive */ -} AON_ACOMP_CFG_Type; - -/*@} end of group ACOMP_Public_Types */ - -/** @defgroup ACOMP_Public_Constants - * @{ - */ - -/** @defgroup AON_ACOMP_ID_TYPE - * @{ - */ -#define IS_AON_ACOMP_ID_TYPE(type) (((type) == AON_ACOMP0_ID) || \ - ((type) == AON_ACOMP1_ID)) - -/** @defgroup AON_ACOMP_SCALING_FACTOR_TYPE - * @{ - */ -#define IS_AON_ACOMP_SCALING_FACTOR_TYPE(type) (((type) == AON_ACOMP_SCALING_FACTOR_0P25) || \ - ((type) == AON_ACOMP_SCALING_FACTOR_0P5) || \ - ((type) == AON_ACOMP_SCALING_FACTOR_0P75) || \ - ((type) == AON_ACOMP_SCALING_FACTOR_1)) - -/** @defgroup AON_ACOMP_CHAN_TYPE - * @{ - */ -#define IS_AON_ACOMP_CHAN_TYPE(type) (((type) == AON_ACOMP_CHAN_ADC0) || \ - ((type) == AON_ACOMP_CHAN_ADC1) || \ - ((type) == AON_ACOMP_CHAN_ADC2) || \ - ((type) == AON_ACOMP_CHAN_ADC3) || \ - ((type) == AON_ACOMP_CHAN_ADC4) || \ - ((type) == AON_ACOMP_CHAN_ADC5) || \ - ((type) == AON_ACOMP_CHAN_ADC6) || \ - ((type) == AON_ACOMP_CHAN_ADC7) || \ - ((type) == AON_ACOMP_CHAN_DACA) || \ - ((type) == AON_ACOMP_CHAN_DACB) || \ - ((type) == AON_ACOMP_CHAN_VREF_1P25V) || \ - ((type) == AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_1) || \ - ((type) == AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_2) || \ - ((type) == AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_3) || \ - ((type) == AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_4) || \ - ((type) == AON_ACOMP_CHAN_VSS)) - -/** @defgroup AON_ACOMP_BIAS_PROG_TYPE - * @{ - */ -#define IS_AON_ACOMP_BIAS_PROG_TYPE(type) (((type) == AON_ACOMP_BIAS_POWER_MODE1) || \ - ((type) == AON_ACOMP_BIAS_POWER_MODE2) || \ - ((type) == AON_ACOMP_BIAS_POWER_MODE3) || \ - ((type) == AON_ACOMP_BIAS_POWER_NONE)) - -/** @defgroup AON_ACOMP_HYSTERESIS_VOLT_TYPE - * @{ - */ -#define IS_AON_ACOMP_HYSTERESIS_VOLT_TYPE(type) (((type) == AON_ACOMP_HYSTERESIS_VOLT_NONE) || \ - ((type) == AON_ACOMP_HYSTERESIS_VOLT_10MV) || \ - ((type) == AON_ACOMP_HYSTERESIS_VOLT_20MV) || \ - ((type) == AON_ACOMP_HYSTERESIS_VOLT_30MV) || \ - ((type) == AON_ACOMP_HYSTERESIS_VOLT_40MV) || \ - ((type) == AON_ACOMP_HYSTERESIS_VOLT_50MV) || \ - ((type) == AON_ACOMP_HYSTERESIS_VOLT_60MV) || \ - ((type) == AON_ACOMP_HYSTERESIS_VOLT_70MV)) - -/*@} end of group ACOMP_Public_Constants */ - -/** @defgroup ACOMP_Public_Macros - * @{ - */ - -/*@} end of group ACOMP_Public_Macros */ - -/** @defgroup ACOMP_Public_Functions - * @{ - */ -BL_Err_Type AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg); -BL_Err_Type AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo); -BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo); - -/*@} end of group ACOMP_Public_Functions */ - -/*@} end of group ACOMP */ - -/*@} end of group BL606P_Peripheral_Driver */ - -#endif /* __BL606P_ACOMP_H__ */ diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_clock.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_clock.h index 29a70e03db..f2336ea72a 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_clock.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_clock.h @@ -70,8 +70,8 @@ typedef enum { } BL_System_Clock_Type; typedef enum { - BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, /*!< MCU xclk clock */ - BL_MTIMER_SOURCE_CLOCK_MCU_CLK, /*!< MCU root clock */ + BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, /*!< MCU xclk clock */ + BL_MTIMER_SOURCE_CLOCK_MCU_CLK, /*!< MCU root clock */ } BL_MTimer_Source_Clock_Type; /** @@ -100,26 +100,26 @@ typedef enum { * @brief Peripheral clock type definition */ typedef enum { - BL_PERIPHERAL_CLOCK_UART0, /*!< UART0 clock */ - BL_PERIPHERAL_CLOCK_UART1, /*!< UART1 clock */ - BL_PERIPHERAL_CLOCK_UART2, /*!< UART2 clock */ - BL_PERIPHERAL_CLOCK_SPI, /*!< SPI clock */ - BL_PERIPHERAL_CLOCK_PEC, /*!< PEC clock */ - BL_PERIPHERAL_CLOCK_DBI, /*!< DBI clock */ - BL_PERIPHERAL_CLOCK_EMI, /*!< EMI clock */ - BL_PERIPHERAL_CLOCK_ISP, /*!< ISP clock */ - BL_PERIPHERAL_CLOCK_I2C0, /*!< I2C0 clock */ - BL_PERIPHERAL_CLOCK_I2C1, /*!< I2C1 clock */ - BL_PERIPHERAL_CLOCK_PSRAMB, /*!< PSRAMB clock */ - BL_PERIPHERAL_CLOCK_FLASH, /*!< FLASH clock */ - BL_PERIPHERAL_CLOCK_I2S, /*!< I2S clock */ - BL_PERIPHERAL_CLOCK_IR, /*!< IR clock */ - BL_PERIPHERAL_CLOCK_ADC, /*!< ADC clock */ - BL_PERIPHERAL_CLOCK_GPADC, /*!< GPADC clock */ - BL_PERIPHERAL_CLOCK_GPDAC, /*!< GPDAC clock */ - BL_PERIPHERAL_CLOCK_CAM, /*!< CAM clock */ - BL_PERIPHERAL_CLOCK_SDH, /*!< SDH clock */ - BL_PERIPHERAL_CLOCK_PKA, /*!< PKA clock */ + BL_PERIPHERAL_CLOCK_UART0, /*!< UART0 clock */ + BL_PERIPHERAL_CLOCK_UART1, /*!< UART1 clock */ + BL_PERIPHERAL_CLOCK_UART2, /*!< UART2 clock */ + BL_PERIPHERAL_CLOCK_SPI, /*!< SPI clock */ + BL_PERIPHERAL_CLOCK_RESERVED, /*!< reserved clock */ + BL_PERIPHERAL_CLOCK_DBI, /*!< DBI clock */ + BL_PERIPHERAL_CLOCK_EMI, /*!< EMI clock */ + BL_PERIPHERAL_CLOCK_ISP, /*!< ISP clock */ + BL_PERIPHERAL_CLOCK_I2C0, /*!< I2C0 clock */ + BL_PERIPHERAL_CLOCK_I2C1, /*!< I2C1 clock */ + BL_PERIPHERAL_CLOCK_PSRAMB, /*!< PSRAMB clock */ + BL_PERIPHERAL_CLOCK_FLASH, /*!< FLASH clock */ + BL_PERIPHERAL_CLOCK_I2S, /*!< I2S clock */ + BL_PERIPHERAL_CLOCK_IR, /*!< IR clock */ + BL_PERIPHERAL_CLOCK_ADC, /*!< ADC clock */ + BL_PERIPHERAL_CLOCK_GPADC, /*!< GPADC clock */ + BL_PERIPHERAL_CLOCK_GPDAC, /*!< GPDAC clock */ + BL_PERIPHERAL_CLOCK_CAM, /*!< CAM clock */ + BL_PERIPHERAL_CLOCK_SDH, /*!< SDH clock */ + BL_PERIPHERAL_CLOCK_PKA, /*!< PKA clock */ BL_PERIPHERAL_CLOCK_MAX, } BL_Peripheral_Type; diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_glb.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_glb.h index 21052332e0..72ac433fb5 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_glb.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_glb.h @@ -306,14 +306,6 @@ typedef enum { GLB_PERI_DMA_GAUGE = 20, /*!< gauge */ GLB_PERI_DMA_GPADC = 22, /*!< gpadc */ GLB_PERI_DMA_GPDAC_TX = 23, /*!< gpdac_tx */ - GLB_PERI_DMA_PEC_RX0 = 24, /*!< pec_rx0 */ - GLB_PERI_DMA_PEC_RX1 = 25, /*!< pec_rx1 */ - GLB_PERI_DMA_PEC_RX2 = 26, /*!< pec_rx2 */ - GLB_PERI_DMA_PEC_RX3 = 27, /*!< pec_rx3 */ - GLB_PERI_DMA_PEC_TX0 = 28, /*!< pec_tx0 */ - GLB_PERI_DMA_PEC_TX1 = 29, /*!< pec_tx1 */ - GLB_PERI_DMA_PEC_TX2 = 30, /*!< pec_tx2 */ - GLB_PERI_DMA_PEC_TX3 = 31, /*!< pec_tx3 */ } GLB_PERI_DMA_Type; /** @@ -358,14 +350,6 @@ typedef enum { GLB_SPI_CLK_XCLK, /*!< Select xclk as SPI clock */ } GLB_SPI_CLK_Type; -/** - * @brief GLB PEC clock type definition - */ -typedef enum { - GLB_PEC_CLK_MCU_MUXPLL_160M, /*!< Select MCU MUXPLL 160M as PEC clock */ - GLB_PEC_CLK_XCLK, /*!< Select xclk as PEC clock */ -} GLB_PEC_CLK_Type; - /** * @brief GLB PWM1 io type definition */ @@ -454,7 +438,6 @@ typedef enum { GLB_AHB_MCU_SW_D2XA = 25, GLB_AHB_MCU_SW_D2XB = 26, GLB_AHB_MCU_SW_JENC = 27, - GLB_AHB_MCU_SW_EXT_PEC = 28, GLB_AHB_MCU_SW_GLB = 32, GLB_AHB_MCU_SW_MIX = 33, GLB_AHB_MCU_SW_GPIP = 34, @@ -481,7 +464,6 @@ typedef enum { GLB_AHB_MCU_SW_CHECKSUM = 55, GLB_AHB_MCU_SW_DBI = 56, GLB_AHB_MCU_SW_I2C1 = 57, - GLB_AHB_MCU_SW_ISO11898 = 58, GLB_AHB_MCU_SW_I2S = 59, GLB_AHB_MCU_SW_AUSOLO = 60, GLB_AHB_MCU_SW_RSV61 = 61, @@ -511,7 +493,6 @@ typedef enum { GLB_DISRST_CHECKSUM = 23, GLB_DISRST_DBI = 24, GLB_DISRST_I2C1 = 25, - GLB_DISRST_ISO11898 = 26, } GLB_DISRST_Type; /** @@ -710,10 +691,8 @@ typedef enum { GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */ GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */ GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */ - GLB_UART_SIG_FUN_N_ISO11898_TXD, /*!< UART funtion: UART 2 RTS */ - GLB_UART_SIG_FUN_RESERVED, /*!< UART funtion: UART 2 CTS */ - GLB_UART_SIG_FUN_ISO11898_TXD, /*!< UART funtion: UART 2 TXD */ - GLB_UART_SIG_FUN_ISO11898_RXD, /*!< UART funtion: UART 2 RXD */ + GLB_UART_SIG_FUN_RESERVED1, /*!< UART funtion: UART 2 RTS */ + GLB_UART_SIG_FUN_RESERVED2, /*!< UART funtion: UART 2 CTS */ } GLB_UART_SIG_FUN_Type; /** @@ -848,8 +827,6 @@ typedef enum { GLB_AHB_CLOCK_IP_AUPDM, GLB_AHB_CLOCK_IP_GAUGE, GLB_AHB_CLOCK_IP_DBI, - GLB_AHB_CLOCK_IP_PEC, - GLB_AHB_CLOCK_IP_ISO11898, GLB_AHB_CLOCK_IP_AUSOLO_TOP, GLB_AHB_CLOCK_IP_DMA_GPIO, GLB_AHB_CLOCK_IP_MM_MISC, @@ -860,7 +837,6 @@ typedef enum { GLB_SLAVE_GRP_0_IR, GLB_SLAVE_GRP_0_I2C, GLB_SLAVE_GRP_0_SPI, - GLB_SLAVE_GRP_0_PEC, GLB_SLAVE_GRP_0_DBI, GLB_SLAVE_GRP_0_AUDIO_AUTO, GLB_SLAVE_GRP_0_AUDIO_ADC, @@ -886,7 +862,6 @@ typedef union { GLB_IR_CLK_SRC_Type irClkSel; GLB_I2C_CLK_Type i2cClkSel; GLB_SPI_CLK_Type spiClkSel; - GLB_PEC_CLK_Type pecClkSel; GLB_DBI_CLK_Type dbiClkSel; GLB_AUDIO_AUTO_CLK_Type audioAutoClkSel; GLB_AUDIO_ADC_CLK_Type audioAdcClkSel; @@ -1123,15 +1098,7 @@ typedef union { ((type) == GLB_PERI_DMA_PADC) || \ ((type) == GLB_PERI_DMA_GAUGE) || \ ((type) == GLB_PERI_DMA_GPADC) || \ - ((type) == GLB_PERI_DMA_GPDAC_TX) || \ - ((type) == GLB_PERI_DMA_PEC_RX0) || \ - ((type) == GLB_PERI_DMA_PEC_RX1) || \ - ((type) == GLB_PERI_DMA_PEC_RX2) || \ - ((type) == GLB_PERI_DMA_PEC_RX3) || \ - ((type) == GLB_PERI_DMA_PEC_TX0) || \ - ((type) == GLB_PERI_DMA_PEC_TX1) || \ - ((type) == GLB_PERI_DMA_PEC_TX2) || \ - ((type) == GLB_PERI_DMA_PEC_TX3)) + ((type) == GLB_PERI_DMA_GPDAC_TX)) /** @defgroup GLB_PERI_DMA_CN_SEL_TYPE * @{ @@ -1165,12 +1132,6 @@ typedef union { #define IS_GLB_SPI_CLK_TYPE(type) (((type) == GLB_SPI_CLK_PLL160M) || \ ((type) == GLB_SPI_CLK_XCLK)) -/** @defgroup GLB_PEC_CLK_TYPE - * @{ - */ -#define IS_GLB_PEC_CLK_TYPE(type) (((type) == GLB_PEC_CLK_PLL160M) || \ - ((type) == GLB_PEC_CLK_XCLK)) - /** @defgroup GLB_PWM1_IO_SEL_TYPE * @{ */ @@ -1236,7 +1197,6 @@ typedef union { ((type) == GLB_AHB_MCU_SW_D2XA) || \ ((type) == GLB_AHB_MCU_SW_D2XB) || \ ((type) == GLB_AHB_MCU_SW_JENC) || \ - ((type) == GLB_AHB_MCU_SW_EXT_PEC) || \ ((type) == GLB_AHB_MCU_SW_GLB) || \ ((type) == GLB_AHB_MCU_SW_MIX) || \ ((type) == GLB_AHB_MCU_SW_GPIP) || \ @@ -1263,7 +1223,6 @@ typedef union { ((type) == GLB_AHB_MCU_SW_CHECKSUM) || \ ((type) == GLB_AHB_MCU_SW_DBI) || \ ((type) == GLB_AHB_MCU_SW_I2C1) || \ - ((type) == GLB_AHB_MCU_SW_ISO11898) || \ ((type) == GLB_AHB_MCU_SW_I2S) || \ ((type) == GLB_AHB_MCU_SW_AUSOLO) || \ ((type) == GLB_AHB_MCU_SW_RSV61) || \ @@ -1290,8 +1249,7 @@ typedef union { ((type) == GLB_DISRST_IR_REMOTE) || \ ((type) == GLB_DISRST_CHECKSUM) || \ ((type) == GLB_DISRST_DBI) || \ - ((type) == GLB_DISRST_I2C1) || \ - ((type) == GLB_DISRST_ISO11898)) + ((type) == GLB_DISRST_I2C1)) /** @defgroup GLB_PKA_CLK_TYPE * @{ @@ -1444,10 +1402,7 @@ typedef union { ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \ ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \ ((type) == GLB_UART_SIG_FUN_UART1_RXD) || \ - ((type) == GLB_UART_SIG_FUN_N_ISO11898_TXD) || \ - ((type) == GLB_UART_SIG_FUN_RESERVED) || \ - ((type) == GLB_UART_SIG_FUN_ISO11898_TXD) || \ - ((type) == GLB_UART_SIG_FUN_ISO11898_RXD)) + ((type) == GLB_UART_SIG_FUN_RESERVED)) /** @defgroup GLB_XTAL_TYPE * @{ @@ -1510,7 +1465,6 @@ typedef union { ((type) == GLB_SLAVE_GRP_0_IR) || \ ((type) == GLB_SLAVE_GRP_0_I2C) || \ ((type) == GLB_SLAVE_GRP_0_SPI) || \ - ((type) == GLB_SLAVE_GRP_0_PEC) || \ ((type) == GLB_SLAVE_GRP_0_DBI) || \ ((type) == GLB_SLAVE_GRP_0_AUDIO_AUTO) || \ ((type) == GLB_SLAVE_GRP_0_AUDIO_ADC) || \ @@ -1588,8 +1542,6 @@ typedef union { #define GLB_AHB_CLOCK_AUPDM (1ULL<>= 1; - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0); - tmpVal >>= 1; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0); - tmpVal >>= 1; - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PEC_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal); -#endif - return SUCCESS; -} - /****************************************************************************/ /** * @brief set PWM1 clock * @@ -2896,12 +2854,6 @@ BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips) case GLB_AHB_CLOCK_IP_DBI: tmpValCfg1 &= ~(1 << 24); break; - case GLB_AHB_CLOCK_IP_PEC: - tmpValCfg2 &= ~(1 << 25); - break; - case GLB_AHB_CLOCK_IP_ISO11898: - tmpValCfg1 &= ~(1 << 26); - break; case GLB_AHB_CLOCK_IP_AUSOLO_TOP: tmpValCfg1 &= ~(1 << 28); break; @@ -3085,12 +3037,6 @@ BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips) case GLB_AHB_CLOCK_IP_DBI: tmpValCfg1 |= (1 << 24); break; - case GLB_AHB_CLOCK_IP_PEC: - tmpValCfg2 |= (1 << 25); - break; - case GLB_AHB_CLOCK_IP_ISO11898: - tmpValCfg1 |= (1 << 26); - break; case GLB_AHB_CLOCK_IP_AUSOLO_TOP: tmpValCfg1 |= (1 << 28); break; diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_hbn.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_hbn.c index a255387421..c360a6a962 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_hbn.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_hbn.c @@ -35,7 +35,7 @@ */ #include "bl616_hbn.h" -#include "bl616_acomp.h" +#include "bflb_acomp.h" #include "bl616_glb.h" #include "bl616_xip_sflash.h" diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pm.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pm.c index 21e11b1336..9106218268 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pm.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pm.c @@ -783,7 +783,7 @@ void ATTR_TCM_SECTION pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, * @param hbn_level */ ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, - uint8_t sleep_time) + uint64_t sleep_time) { uint32_t tmpVal; @@ -798,7 +798,7 @@ ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, if (sleep_time) { struct bflb_device_s *rtc_dev = NULL; - bflb_rtc_set_time(rtc_dev,sleep_time); // sleep time,unit is second + bflb_rtc_set_time(rtc_dev,sleep_time); // sleep time,unit is cycle } if (hbn_level >= PM_HBN_LEVEL_2) { diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_e907.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_e907.c index f7e11000be..603e673379 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_e907.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_e907.c @@ -676,13 +676,6 @@ BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel){ return RomDriver_GLB_Set_ETH_REF_O_CLK_Sel(clkSel); } -#if 0 -__ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type GLB_Set_PEC_CLK(uint8_t enable, GLB_PEC_CLK_Type clkSel, uint8_t div){ - return RomDriver_GLB_Set_PEC_CLK(enable,clkSel,div); -} -#endif - #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div){ diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_patch.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_patch.c index c5b592124e..d9e906c214 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_patch.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_patch.c @@ -198,7 +198,6 @@ const GLB_SLAVE_GRP_0_TBL_Type ATTR_CLOCK_CONST_SECTION glb_slave_grp_0_table[GL { GLB_IR_CFG0_OFFSET, GLB_IR_CLK_EN_POS, 0, GLB_IR_CLK_DIV_POS, GLB_IR_CLK_EN_LEN, 0, GLB_IR_CLK_DIV_LEN }, { GLB_I2C_CFG0_OFFSET, GLB_I2C_CLK_EN_POS, GLB_I2C_CLK_SEL_POS, GLB_I2C_CLK_DIV_POS, GLB_I2C_CLK_EN_LEN, GLB_I2C_CLK_SEL_LEN, GLB_I2C_CLK_DIV_LEN }, { GLB_SPI_CFG0_OFFSET, GLB_SPI_CLK_EN_POS, GLB_SPI_CLK_SEL_POS, GLB_SPI_CLK_DIV_POS, GLB_SPI_CLK_EN_LEN, GLB_SPI_CLK_SEL_LEN, GLB_SPI_CLK_DIV_LEN }, - { GLB_PEC_CFG0_OFFSET, GLB_PEC_CLK_EN_POS, GLB_PEC_CLK_SEL_POS, GLB_PEC_CLK_DIV_POS, GLB_PEC_CLK_EN_LEN, GLB_PEC_CLK_SEL_LEN, GLB_PEC_CLK_DIV_LEN }, { GLB_DBI_CFG0_OFFSET, GLB_DBI_CLK_EN_POS, GLB_DBI_CLK_SEL_POS, GLB_DBI_CLK_DIV_POS, GLB_DBI_CLK_EN_LEN, GLB_DBI_CLK_SEL_LEN, GLB_DBI_CLK_DIV_LEN }, { GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_AUTO_DIV_EN_POS, 0, 0, GLB_REG_AUDIO_AUTO_DIV_EN_LEN, 0, 0 }, { GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_ADC_CLK_EN_POS, 0, GLB_REG_AUDIO_ADC_CLK_DIV_POS, GLB_REG_AUDIO_ADC_CLK_EN_LEN, 0, GLB_REG_AUDIO_ADC_CLK_DIV_LEN }, @@ -2090,47 +2089,6 @@ BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div return SUCCESS; } -/****************************************************************************/ /** - * @brief set PEC clock - * - * @param enable: Enable or disable PEC clock - * @param clkSel: clock selection - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_PEC_CLK(uint8_t enable, GLB_PEC_CLK_Type clkSel, uint8_t div) -{ -#ifndef BOOTROM - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PEC_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x1F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0); - tmpVal >>= 1; - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0); - tmpVal >>= 1; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0); - tmpVal >>= 1; - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PEC_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal); -#endif - return SUCCESS; -} - /****************************************************************************/ /** * @brief set DBI clock * diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romdriver_e907.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romdriver_e907.c index bb5b21ecaa..60529fe975 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romdriver_e907.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romdriver_e907.c @@ -214,7 +214,7 @@ uint32_t const romDriverTable[]={ [ROM_API_INDEX_GLB_Set_DMA_CLK] = (uint32_t)GLB_Set_DMA_CLK, [ROM_API_INDEX_GLB_Set_EM_Sel] = (uint32_t)GLB_Set_EM_Sel, [ROM_API_INDEX_GLB_Set_ETH_REF_O_CLK_Sel] = (uint32_t)GLB_Set_ETH_REF_O_CLK_Sel, - [ROM_API_INDEX_GLB_Set_PEC_CLK] = (uint32_t)GLB_Set_PEC_CLK, + [ROM_API_INDEX_GLB_Set_ETH_REF_O_CLK_Sel_2] = (uint32_t)NULL, [ROM_API_INDEX_GLB_Set_I2C_CLK] = (uint32_t)GLB_Set_I2C_CLK, [ROM_API_INDEX_GLB_Set_I2S_CLK] = (uint32_t)GLB_Set_I2S_CLK, [ROM_API_INDEX_GLB_Set_IR_CLK] = (uint32_t)GLB_Set_IR_CLK, diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/SConscript index d568364440..d6bfd46f57 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/SConscript +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/SConscript @@ -29,34 +29,29 @@ elif GetDepend('BL808_CORE_LP'): std/startup/lp/interrupt.c """) CPPDEFINES += ['CPU_LP'] - -elif GetDepend('BL808_CORE_D0'): - src += Split(""" - std/startup/d0/start.S - std/startup/d0/vector.S - std/startup/d0/riscv_fpu.S - std/startup/d0/start_load.c - std/startup/d0/system_bl808.c - std/startup/d0/interrupt.c - """) - CPPDEFINES += ['CPU_D0'] -src += Split(""" - std/src/bl808_aon.c - std/src/bl808_clock.c - std/src/bl808_common.c - std/src/bl808_ef_cfg.c - std/src/bl808_glb.c - std/src/bl808_glb_gpio.c - std/src/bl808_hbn.c - std/src/bl808_l1c.c - std/src/bl808_pds.c - std/src/bl808_sdh.c - std/src/bl808_tzc_sec.c - std/src/bl808_psram_uhs.c - std/src/bl808_uhs_phy.c - std/port/bl808_clock.c -""") +elif GetDepend('BL808_CORE_D0'): + CPPDEFINES += ['CPU_D0'] + if GetDepend('RT_USING_SMART'): + LOCAL_CFLAGS += ' -DRT_USING_SMART' + +if GetDepend('BL808_CORE_M0') or GetDepend('BL808_CORE_LP'): + src += Split(""" + std/src/bl808_aon.c + std/src/bl808_clock.c + std/src/bl808_common.c + std/src/bl808_ef_cfg.c + std/src/bl808_glb.c + std/src/bl808_glb_gpio.c + std/src/bl808_hbn.c + std/src/bl808_l1c.c + std/src/bl808_pds.c + std/src/bl808_sdh.c + std/src/bl808_tzc_sec.c + std/src/bl808_psram_uhs.c + std/src/bl808_uhs_phy.c + std/port/bl808_clock.c + """) CPPPATH += [cwd + r'/std/include', cwd + r'/std/include/hardware'] diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb.h index 156335ad54..55b12d2976 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb.h @@ -956,7 +956,6 @@ typedef enum { */ typedef enum { GLB_UART2_IO_SEL_UART2, /*!< Select UART2 function */ - GLB_UART2_IO_SEL_ISO11898, /*!< Select ISO11898 function */ } GLB_UART2_IO_SEL_Type; /** @@ -1991,8 +1990,7 @@ typedef enum { /** @defgroup GLB_UART2_IO_SEL_TYPE * @{ */ -#define IS_GLB_UART2_IO_SEL_TYPE(type) (((type) == GLB_UART2_IO_SEL_UART2) || \ - ((type) == GLB_UART2_IO_SEL_ISO11898)) +#define IS_GLB_UART2_IO_SEL_TYPE(type) (((type) == GLB_UART2_IO_SEL_UART2)) /** @defgroup GLB_UART_SIG_TYPE * @{ diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/bl808.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/bl808.h index b96b9b687b..4e34802d14 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/bl808.h +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/bl808.h @@ -429,7 +429,6 @@ typedef enum { #define IPC1_BASE ((uint32_t)0x2000a840) #define I2C1_BASE ((uint32_t)0x2000a900) #define UART2_BASE ((uint32_t)0x2000aa00) -#define ISO11898_BASE ((uint32_t)0x2000aa00) #define I2S_BASE ((uint32_t)0x2000ab00) #define PDM0_BASE ((uint32_t)0x2000a000) #define LZ4D_BASE ((uint32_t)0x2000ad00) diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_clock.c index 46b94265fc..2d5b250e6f 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_clock.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_clock.c @@ -851,7 +851,7 @@ uint32_t ATTR_CLOCK_SECTION Clock_System_Clock_Get(BL_System_Clock_Type type) clock = Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val()); div = Clock_Get_MCU_HClk_Div_Val(); return clock / (div + 1); - +#ifndef CONIFG_DISABLE_ALL_CLOCK_GET_EXCEPT_SYSTEM_CLOCK case BL_SYSTEM_CLOCK_MCU_BCLK: ATTR_FALLTHROUGH(); @@ -900,7 +900,7 @@ uint32_t ATTR_CLOCK_SECTION Clock_System_Clock_Get(BL_System_Clock_Type type) case BL_SYSTEM_CLOCK_XTAL: /*!< xtal clock */ return Clock_Xtal_Output(); - +#endif default: return 0; } diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_glb.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_glb.c index 239ba7d115..00aebe293b 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_glb.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_glb.c @@ -669,6 +669,7 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is RC32M */ }; +#ifndef CONIFG_DISABLE_ALL_UHS_EXCEPT_40M /* uhs PLL 2000 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = { .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ @@ -714,7 +715,24 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */ }; - +#else +const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = { + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */ +}; +const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = { + { NULL, 0x0 }, /*!< XTAL is None */ + { NULL, 0x0 }, /*!< XTAL is 24M */ + { NULL, 0x0 }, /*!< XTAL is 32M */ + { NULL, 0x0 }, /*!< XTAL is 38.4M */ + { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */ + { NULL, 0x0 }, /*!< XTAL is 26M */ + { NULL, 0x0 }, /*!< XTAL is RC32M */ +}; +#endif /*@} end of group GLB_Private_Variables */ /** @defgroup GLB_Global_Variables diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_psram_uhs.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_psram_uhs.c index 1f06618aff..924a717eb9 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_psram_uhs.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_psram_uhs.c @@ -102,7 +102,9 @@ int config_uhs_phy(uint32_t datarate) tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1); BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); - } else if (datarate > 1600) { + } +#ifndef CONIFG_DISABLE_ALL_PSRAM_FRQ_EXCEPT_2000 + else if (datarate > 1600) { BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F283203); BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0a020303); BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040d0416); @@ -165,6 +167,7 @@ int config_uhs_phy(uint32_t datarate) tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0); BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); } +#endif return 0; } diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_uhs_phy.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_uhs_phy.c index 72d5a6fc81..2110267129 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_uhs_phy.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_uhs_phy.c @@ -19,7 +19,7 @@ #else #define uhs_phy_printf_debug(...) #define uhs_phy_printf(...) - #define uhs_phy_printfe printf + #define uhs_phy_printfe(...) #endif #define ODT_EN (0) diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/interrupt.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/interrupt.c index b48bed4759..0af3f9db14 100755 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/interrupt.c +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/interrupt.c @@ -117,6 +117,7 @@ const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = { void exception_entry(uintptr_t *regs) { +#ifndef CONFIG_TRAP_DUMP_DISABLE unsigned long cause; unsigned long epc; unsigned long tval; @@ -132,7 +133,7 @@ void exception_entry(uintptr_t *regs) cause = (cause & 0x3ff); -#ifndef CONFIG_TRAP_DUMP_DISABLE + const char *mcause_str[] = { "Instruction address misaligned", "Instruction access fault", @@ -153,7 +154,7 @@ void exception_entry(uintptr_t *regs) }; printf("%s\r\n", mcause_str[cause & 0xf]); -#endif + if ((cause == 8) || (cause == 11)) { epc += 4; WRITE_CSR(CSR_MEPC, epc); @@ -161,6 +162,7 @@ void exception_entry(uintptr_t *regs) while (1) { } } +#endif } void interrupt_entry(void) diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc/usage.txt b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc/usage.txt deleted file mode 100755 index d64151b6b4..0000000000 --- a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc/usage.txt +++ /dev/null @@ -1,17 +0,0 @@ -bflb_fw_post_proc is a command line firmware process tool to update correct bootheder information and encrypt or sign firmware. -In order to achieve this goal, some parameters must be specified: - --chipname: chipname that you are buiding - --brdcfgdir: board config directory that you are using,this is used to copy boot2 like file to image directory - --imgfile: image file that you want to deal with,',' can be used to split multiple files and '*' can be used to match the only one file - --key: AES key when you want to encrypt you image with AES CTR - --iv: AES iv when you want to encrypt you image with AES CTR - --xtsmode: xts mode enable when you want to encrypt you image with AES xts and your chip support - --privatekey: private key of ecc-256 in pem format - --publickey: public key of ecc-256 in pem format - -Examples: -bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin -bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin,./build/build_out/boot2_*.bin -bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin --key=000102030405060708090A0B0C0D0E0F --iv=100102030405060708090A0B00000000 -bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin --key=000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F --iv=100102030405060708090A0B00000000 --xtsmode=1 -bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin --privatekey=privatekey_uecc.pem --publickey=publickey_uecc.pem \ No newline at end of file diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/get_bflb_fw_post_proc.sh b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/get_bflb_fw_post_proc.sh new file mode 100755 index 0000000000..65fe042e5e --- /dev/null +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/get_bflb_fw_post_proc.sh @@ -0,0 +1,47 @@ +#/bin/bash +CHIPNAME=$1 +BIN_FILE=$2 + +set -e + +SYSTEM=`uname -s` +echo "system: $SYSTEM" + +SHELL_DIR=$(cd "$(dirname "$0")"; pwd) +TOOL_DIR=$SHELL_DIR + +URL_GITEE=https://gitee.com/flyingcys/bflb_tools/releases/download/v1.0.4 +URL_GITHUB=https://github.com/flyingcys/bflb_tools/releases/download/v1.0.4 +if [ $SYSTEM = "Darwin" ] +then + TOOL_NAME=bflb_fw_post_proc-macos + FILE_NAME=bflb_fw_post_proc-macos.tar.gz +elif [ $SYSTEM = "Linux" ] +then + TOOL_NAME=bflb_fw_post_proc-ubuntu + FILE_NAME=bflb_fw_post_proc-linux.tar.gz +else + TOOL_NAME=bflb_fw_post_proc.exe + FILE_NAME=bflb_fw_post_proc-win.tar.gz +fi + +DOWNLOAD_URL=$URL_GITEE +if [ -f "$TOOL_DIR/$TOOL_NAME" ] +then + echo "bflb_fw_post_proc exist" +else + echo "bflb_fw_post_proc not exist, try download... " + echo "url:$DOWNLOAD_URL/$FILE_NAME" + + # 连接超时30s 下载超时120s + curl -LjO --connect-timeout 30 -m 120 $DOWNLOAD_URL/$FILE_NAME + + mkdir -p $TOOL_DIR/bflb_fw_post_proc + tar zxvf $FILE_NAME -C $TOOL_DIR/bflb_fw_post_proc + rm -rf $FILE_NAME + if [ $SYSTEM = "Darwin" ]; then + chmod +x $TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME + elif [ $SYSTEM = "Linux" ]; then + chmod +x $TOOL_DIR/bflb_fw_post_proc/$TOOL_NAME + fi +fi diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/get_bouffalo_flash_cube.sh b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/get_bouffalo_flash_cube.sh new file mode 100755 index 0000000000..6fe36ee8eb --- /dev/null +++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/get_bouffalo_flash_cube.sh @@ -0,0 +1,46 @@ +#/bin/bash +CHIPNAME=$1 +BIN_FILE=$2 + +set -e + +SYSTEM=`uname -s` +echo "system: $SYSTEM" + +SHELL_DIR=$(cd "$(dirname "$0")"; pwd) +TOOL_DIR=$SHELL_DIR + +URL_GITEE=https://gitee.com/flyingcys/bflb_tools/releases/download/v1.0.4 +URL_GITHUB=https://github.com/flyingcys/bflb_tools/releases/download/v1.0.4 +if [ $SYSTEM = "Darwin" ] +then + TOOL_NAME=BLFlashCommand-macos + FILE_NAME=bouffalo_flash_cube-macos.tar.gz +elif [ $SYSTEM = "Linux" ] +then + TOOL_NAME=BLFlashCommand-ubuntu + FILE_NAME=bouffalo_flash_cube-linux.tar.gz +else + TOOL_NAME=BLFlashCommand.exe + FILE_NAME=bouffalo_flash_cube-win.tar.gz +fi + +DOWNLOAD_URL=$URL_GITEE +if [ -f "$TOOL_DIR/$TOOL_NAME" ] +then + echo "bouffalo_flash_cube exist" +else + echo "bouffalo_flash_cube not exist, try download... " + echo "url:$DOWNLOAD_URL/$FILE_NAME" + + # 连接超时30s 下载超时300s + curl -LjO --connect-timeout 30 -m 300 $DOWNLOAD_URL/$FILE_NAME + + tar zxvf $FILE_NAME -C $TOOL_DIR + rm -rf $FILE_NAME + if [ $SYSTEM = "Darwin" ]; then + chmod +x $TOOL_DIR/bouffalo_flash_cube/$TOOL_NAME + elif [ $SYSTEM = "Linux" ]; then + chmod +x $TOOL_DIR/bouffalo_flash_cube/$TOOL_NAME + fi +fi