From 8ed4ae144fda951d7a3f5ffbfbf810b1ce1bf2c8 Mon Sep 17 00:00:00 2001 From: flyingcys Date: Wed, 13 Nov 2024 23:23:38 +0800 Subject: [PATCH] support milkv-duo rt-smart 1. switches memory management to SLA 2. use ioremap modification driver Signed-off-by: flyingcys flyingcys@163.com --- bsp/cvitek/README.md | 20 +- bsp/cvitek/cv18xx_risc-v/.config | 105 +++++-- bsp/cvitek/cv18xx_risc-v/board/board.c | 2 +- bsp/cvitek/cv18xx_risc-v/board/board.h | 12 +- bsp/cvitek/cv18xx_risc-v/link.lds | 7 +- bsp/cvitek/cv18xx_risc-v/link_smart.lds | 7 +- bsp/cvitek/cv18xx_risc-v/rtconfig.h | 55 +++- bsp/cvitek/cv18xx_risc-v/rtconfig.py | 5 +- bsp/cvitek/drivers/drv_adc.c | 16 +- bsp/cvitek/drivers/drv_eth.c | 18 +- bsp/cvitek/drivers/drv_eth.h | 3 +- bsp/cvitek/drivers/drv_gpio.c | 7 +- bsp/cvitek/drivers/drv_hw_i2c.c | 2 + bsp/cvitek/drivers/drv_por.c | 14 +- bsp/cvitek/drivers/drv_pwm.c | 3 + bsp/cvitek/drivers/drv_rtc.c | 37 ++- bsp/cvitek/drivers/drv_sdhci.c | 86 +++--- bsp/cvitek/drivers/drv_sdhci.h | 2 +- bsp/cvitek/drivers/drv_spi.c | 3 + bsp/cvitek/drivers/drv_timer.c | 37 ++- bsp/cvitek/drivers/drv_uart.c | 26 +- bsp/cvitek/drivers/drv_wdt.c | 15 +- bsp/cvitek/drivers/libraries/cv180x/pinctrl.h | 4 +- bsp/cvitek/drivers/libraries/cv181x/pinctrl.h | 10 +- .../drivers/libraries/eth/cvi_eth_phy.h | 23 +- bsp/cvitek/drivers/libraries/eth/dw_eth_mac.c | 84 ++++-- bsp/cvitek/drivers/libraries/eth/dw_eth_mac.h | 93 +++--- .../drivers/libraries/eth/eth_phy_cvitek.c | 272 +++++++++--------- bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h | 23 +- 29 files changed, 609 insertions(+), 382 deletions(-) diff --git a/bsp/cvitek/README.md b/bsp/cvitek/README.md index d5c4a0f95e..80a23f1ede 100755 --- a/bsp/cvitek/README.md +++ b/bsp/cvitek/README.md @@ -44,12 +44,14 @@ Duo 家族开发板采用 CV18xx 系列芯片。芯片的工作模式总结如 | BSP 名称 | 大小核 | 芯片架构 | 默认串口控制台 | 备注 | | ------------- | ------- |---------------- | -------------- | -------- | -| cv18xx_risc-v | 大核 | RISC-V C906 | uart0 | 支持 MMU，支持 RT-Thread 标准版 和 RT-SMART 模式，默认运行 RT-Thread 标准版本 | +| cv18xx_risc-v | 大核 | RISC-V C906 | uart0 | 支持 MMU，支持 RT-Thread 标准版 和 RT-SMART 模式，默认运行 RT-SMART 版本 | | c906-little | 小核 | RISC-V C906 | uart1 | 无 MMU，运行 RT-Thread 标准版 | | cv18xx_aarch64| 大核 | ARM Cortex A53 | uart0 | 支持 MMU， 支持 RT-Thread 标准版 和 RT-SMART 版，默认运行 RT-Thread 标准版本 | 由于开发板默认运行的大核为 "cv18xx_risc-v", 所以本文将主要介绍 "cv18xx_risc-v" 和 "c906-little" 的构建和使用。有关 "cv18xx_aarch64" 的介绍请参考 [这里](./cv18xx_aarch64/README.md)。 +> 注：不同开发板 uart 输出管脚不同，默认配置可能导致串口无法正常显示，请根据开发板 uart 通过 `scons --menuconfig` 配置对应 uart 的输出管脚。 + ## 驱动支持列表 | 驱动 | 支持情况 | 备注 | @@ -113,7 +115,21 @@ Board Type (milkv-duo) ---> ( ) milkv-duos ``` -2. 编译 +2. 可按照以下方式开启 RT-Smart + +```shell +RT-Thread Kernel ---> + [*] Enable RT-Thread Smart (microkernel on kernel/userland) +``` + +并配置内核虚拟起始地址 `0xFFFFFFC000200000` +```shell + RT-Thread Kernel ---> +(0xFFFFFFC000200000) The virtural address of kernel start + RT-Thread Components ---> +``` + +3. 编译 ```shell $ scons ``` diff --git a/bsp/cvitek/cv18xx_risc-v/.config b/bsp/cvitek/cv18xx_risc-v/.config index c9c54d5e4d..290b22b466 100644 --- a/bsp/cvitek/cv18xx_risc-v/.config +++ b/bsp/cvitek/cv18xx_risc-v/.config @@ -4,7 +4,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMART is not set +CONFIG_RT_USING_SMART=y # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set @@ -17,13 +17,13 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_HOOKLIST=y +# CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_IDLE_THREAD_STACK_SIZE=16384 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=16384 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set CONFIG_RT_USING_CPU_USAGE_TRACER=y @@ -65,13 +65,13 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y # CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set @@ -83,7 +83,6 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_DEVICE_OPS=y # CONFIG_RT_USING_INTERRUPT_INFO is not set # CONFIG_RT_USING_THREADSAFE_PRINTF is not set -CONFIG_RT_USING_SCHED_THREAD_CTX=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" @@ -95,11 +94,14 @@ CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 CONFIG_ARCH_CPU_64BIT=y CONFIG_RT_USING_CACHE=y CONFIG_ARCH_MM_MMU=y +CONFIG_KERNEL_VADDR_START=0xFFFFFFC000200000 CONFIG_ARCH_RISCV=y CONFIG_ARCH_RISCV_FPU=y CONFIG_ARCH_RISCV_FPU_D=y CONFIG_ARCH_RISCV64=y +CONFIG_ARCH_USING_NEW_CTX_SWITCH=y CONFIG_ARCH_USING_RISCV_COMMON64=y +CONFIG_ARCH_REMAP_KERNEL=y # # RT-Thread Components @@ -132,8 +134,7 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_POSIX=y CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_V1 is not set +CONFIG_DFS_FD_MAX=128 CONFIG_RT_USING_DFS_V2=y CONFIG_RT_USING_DFS_ELMFAT=y @@ -164,9 +165,22 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DFS_ROMFS=y # CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set +CONFIG_RT_USING_DFS_TMPFS=y # CONFIG_RT_USING_DFS_MQUEUE is not set +CONFIG_RT_USING_PAGECACHE=y + +# +# page cache config +# +CONFIG_RT_PAGECACHE_COUNT=4096 +CONFIG_RT_PAGECACHE_ASPACE_COUNT=1024 +CONFIG_RT_PAGECACHE_PRELOAD=4 +CONFIG_RT_PAGECACHE_HASH_NR=1024 +CONFIG_RT_PAGECACHE_GC_WORK_LEVEL=90 +CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 +# end of page cache config # end of DFS: device virtual file system # CONFIG_RT_USING_FAL is not set @@ -214,7 +228,7 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22 CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set +CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set @@ -224,7 +238,7 @@ CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y -# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -256,6 +270,9 @@ CONFIG_RT_USING_POSIX_STDIO=y CONFIG_RT_USING_POSIX_POLL=y CONFIG_RT_USING_POSIX_SELECT=y # CONFIG_RT_USING_POSIX_EVENTFD is not set +CONFIG_RT_USING_POSIX_EPOLL=y +CONFIG_RT_USING_POSIX_SIGNALFD=y +CONFIG_RT_SIGNALFD_MAX_NUM=10 # CONFIG_RT_USING_POSIX_TIMERFD is not set CONFIG_RT_USING_POSIX_SOCKET=y CONFIG_RT_USING_POSIX_TERMIOS=y @@ -367,6 +384,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set CONFIG_RT_LWIP_USING_PING=y # CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_ENABLE_USER_HOOKS is not set # CONFIG_RT_LWIP_DEBUG is not set # CONFIG_RT_USING_AT is not set # end of Network @@ -395,6 +413,25 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_LWP=y +CONFIG_LWP_DEBUG=y +# CONFIG_LWP_DEBUG_INIT is not set +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +CONFIG_RT_USING_LDSO=y +# CONFIG_ELF_DEBUG_ENABLE is not set +# CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 + +# +# Memory management +# +# CONFIG_RT_USING_MEMBLOCK is not set +# end of Memory management # # Using USB legacy version @@ -431,6 +468,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -535,6 +573,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set # end of IoT - internet of things # @@ -562,6 +601,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set # end of JSON: JavaScript Object Notation, a lightweight data-interchange format # @@ -680,6 +720,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set # end of enhanced kernel services +# CONFIG_PKG_USING_AUNITY is not set + # # acceleration: Assembly language or algorithmic acceleration packages # @@ -770,11 +812,29 @@ CONFIG_RT_USING_ADT_REF=y # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set # end of STM32 HAL & SDK Drivers +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -948,6 +1008,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_SYSTEM_RUN_LED is not set # CONFIG_PKG_USING_BT_MX01 is not set # CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -969,6 +1030,7 @@ CONFIG_RT_USING_ADT_REF=y # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set @@ -1020,7 +1082,13 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set +CONFIG_PKG_USING_ZLIB=y +CONFIG_PKG_ZLIB_PATH="/packages/misc/zlib" +# CONFIG_ZLIB_USING_SAMPLE is not set +# CONFIG_PKG_USING_ZLIB_V100 is not set +# CONFIG_PKG_USING_ZLIB_V123 is not set +CONFIG_PKG_USING_ZLIB_LATEST_VERSION=y +CONFIG_PKG_ZLIB_VER="latest" # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set # CONFIG_PKG_USING_DSTR is not set @@ -1056,6 +1124,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -1297,6 +1366,7 @@ CONFIG_BSP_UART_IRQ_BASE=44 # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_TIMER is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_SDH is not set @@ -1314,5 +1384,6 @@ CONFIG_SOC_TYPE_SG2002=y # CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR is not set CONFIG_BOARD_TYPE_MILKV_DUO256M=y # CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set +# CONFIG_BOARD_TYPE_MILKV_DUOS is not set CONFIG_BSP_ROOTFS_TYPE_ROMFS=y # CONFIG_BSP_ROOTFS_TYPE_CROMFS is not set diff --git a/bsp/cvitek/cv18xx_risc-v/board/board.c b/bsp/cvitek/cv18xx_risc-v/board/board.c index 720ef5f072..ab3a7178ed 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/board.c +++ b/bsp/cvitek/cv18xx_risc-v/board/board.c @@ -108,6 +108,6 @@ void rt_hw_board_init(void) #endif #ifdef RT_USING_HEAP - rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t)RT_HW_HEAP_BEGIN, (rt_ubase_t)RT_HW_HEAP_END); + rt_kprintf("heap: [0x%p - 0x%p]\n", (rt_ubase_t)RT_HW_HEAP_BEGIN, (rt_ubase_t)RT_HW_HEAP_END); #endif /* RT_USING_HEAP */ } diff --git a/bsp/cvitek/cv18xx_risc-v/board/board.h b/bsp/cvitek/cv18xx_risc-v/board/board.h index a06085a941..5f23ff4a6f 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/board.h +++ b/bsp/cvitek/cv18xx_risc-v/board/board.h @@ -15,17 +15,17 @@ #include "drv_uart.h" #include "tick.h" +extern unsigned int __sram_end; +#define RAM_END (rt_size_t)((void *)&__sram_end) + extern unsigned int __bss_start; extern unsigned int __bss_end; -#ifndef RT_USING_SMART -#define KERNEL_VADDR_START 0x80200000 -#endif - #define RT_HW_HEAP_BEGIN ((void *)&__bss_end) -#define RT_HW_HEAP_END ((void *)(KERNEL_VADDR_START + 16 * 1024 * 1024)) +#define RT_HW_HEAP_END ((void *)((rt_size_t)RT_HW_HEAP_BEGIN + 8 * 1024 * 1024)) + #define RT_HW_PAGE_START RT_HW_HEAP_END -#define RT_HW_PAGE_END ((void *)(KERNEL_VADDR_START + 32 * 1024 * 1024)) +#define RT_HW_PAGE_END ((void *)(RAM_END)) void rt_hw_board_init(void); diff --git a/bsp/cvitek/cv18xx_risc-v/link.lds b/bsp/cvitek/cv18xx_risc-v/link.lds index 891669e03c..8458177504 100755 --- a/bsp/cvitek/cv18xx_risc-v/link.lds +++ b/bsp/cvitek/cv18xx_risc-v/link.lds @@ -21,15 +21,18 @@ OUTPUT_ARCH( "riscv" ) MEMORY { - SRAM : ORIGIN = 0x80200000, LENGTH = 32M + SRAM(wx): ORIGIN = 0x80200000, LENGTH = 32M } ENTRY(_start) SECTIONS { - . = 0x80200000 ; + . = ORIGIN(SRAM) ; /* __STACKSIZE__ = 4096; */ + __sram_base = ORIGIN(SRAM); + __sram_size = LENGTH(SRAM); + __sram_end = __sram_base + __sram_size; __text_start = .; .start : { diff --git a/bsp/cvitek/cv18xx_risc-v/link_smart.lds b/bsp/cvitek/cv18xx_risc-v/link_smart.lds index ec130f0e60..7dc21101f1 100644 --- a/bsp/cvitek/cv18xx_risc-v/link_smart.lds +++ b/bsp/cvitek/cv18xx_risc-v/link_smart.lds @@ -21,15 +21,18 @@ OUTPUT_ARCH( "riscv" ) MEMORY { - SRAM : ORIGIN = 0xFFFFFFC000200000, LENGTH = 64M + SRAM(wx): ORIGIN = 0xFFFFFFC000200000, LENGTH = 64M } ENTRY(_start) SECTIONS { - . = 0xFFFFFFC000200000 ; + . = ORIGIN(SRAM) ; /* __STACKSIZE__ = 4096; */ + __sram_base = ORIGIN(SRAM); + __sram_size = LENGTH(SRAM); + __sram_end = __sram_base + __sram_size; __text_start = .; .start : { diff --git a/bsp/cvitek/cv18xx_risc-v/rtconfig.h b/bsp/cvitek/cv18xx_risc-v/rtconfig.h index 38b60f936f..ef152eb30c 100755 --- a/bsp/cvitek/cv18xx_risc-v/rtconfig.h +++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.h @@ -4,6 +4,7 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 +#define RT_USING_SMART #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -11,13 +12,12 @@ #define RT_TICK_PER_SECOND 1000 #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR -#define RT_USING_HOOKLIST #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 8192 +#define IDLE_THREAD_STACK_SIZE 16384 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 8192 +#define RT_TIMER_THREAD_STACK_SIZE 16384 #define RT_USING_CPU_USAGE_TRACER /* kservice optimization */ @@ -46,14 +46,12 @@ /* Memory Management */ #define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB +#define RT_USING_SLAB_AS_HEAP #define RT_USING_HEAP /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_DEVICE_OPS -#define RT_USING_SCHED_THREAD_CTX #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart0" @@ -64,11 +62,14 @@ #define ARCH_CPU_64BIT #define RT_USING_CACHE #define ARCH_MM_MMU +#define KERNEL_VADDR_START 0xFFFFFFC000200000 #define ARCH_RISCV #define ARCH_RISCV_FPU #define ARCH_RISCV_FPU_D #define ARCH_RISCV64 +#define ARCH_USING_NEW_CTX_SWITCH #define ARCH_USING_RISCV_COMMON64 +#define ARCH_REMAP_KERNEL /* RT-Thread Components */ @@ -96,7 +97,7 @@ #define RT_USING_DFS #define DFS_USING_POSIX #define DFS_USING_WORKDIR -#define DFS_FD_MAX 16 +#define DFS_FD_MAX 128 #define RT_USING_DFS_V2 #define RT_USING_DFS_ELMFAT @@ -116,6 +117,19 @@ /* end of elm-chan's FatFs, Generic FAT Filesystem Module */ #define RT_USING_DFS_DEVFS #define RT_USING_DFS_ROMFS +#define RT_USING_DFS_PTYFS +#define RT_USING_DFS_TMPFS +#define RT_USING_PAGECACHE + +/* page cache config */ + +#define RT_PAGECACHE_COUNT 4096 +#define RT_PAGECACHE_ASPACE_COUNT 1024 +#define RT_PAGECACHE_PRELOAD 4 +#define RT_PAGECACHE_HASH_NR 1024 +#define RT_PAGECACHE_GC_WORK_LEVEL 90 +#define RT_PAGECACHE_GC_STOP_LEVEL 70 +/* end of page cache config */ /* end of DFS: device virtual file system */ /* Device Drivers */ @@ -142,8 +156,10 @@ #define RT_MMCSD_STACK_SIZE 8192 #define RT_MMCSD_THREAD_PREORITY 22 #define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_WDT #define RT_USING_PIN #define RT_USING_KTIME +#define RT_USING_HWTIMER /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -166,6 +182,9 @@ #define RT_USING_POSIX_STDIO #define RT_USING_POSIX_POLL #define RT_USING_POSIX_SELECT +#define RT_USING_POSIX_EPOLL +#define RT_USING_POSIX_SIGNALFD +#define RT_SIGNALFD_MAX_NUM 10 #define RT_USING_POSIX_SOCKET #define RT_USING_POSIX_TERMIOS #define RT_USING_POSIX_DELAY @@ -257,6 +276,20 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ +#define RT_USING_LWP +#define LWP_DEBUG +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 +#define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 + +/* Memory management */ + +/* end of Memory management */ /* Using USB legacy version */ @@ -357,6 +390,10 @@ /* end of STM32 HAL & SDK Drivers */ +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + /* Kendryte SDK */ /* end of Kendryte SDK */ @@ -392,6 +429,8 @@ /* entertainment: terminal games and other interesting software packages */ /* end of entertainment: terminal games and other interesting software packages */ +#define PKG_USING_ZLIB +#define PKG_USING_ZLIB_LATEST_VERSION /* end of miscellaneous packages */ /* Arduino libraries */ diff --git a/bsp/cvitek/cv18xx_risc-v/rtconfig.py b/bsp/cvitek/cv18xx_risc-v/rtconfig.py index 91667d1bf0..8137d1d922 100755 --- a/bsp/cvitek/cv18xx_risc-v/rtconfig.py +++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.py @@ -16,7 +16,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin' + EXEC_PATH = r'/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) @@ -29,8 +29,7 @@ CHIP_TYPE = 'cv180x' if PLATFORM == 'gcc': # toolchains - #PREFIX = 'riscv64-unknown-elf-' - PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-elf-' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-' CC = PREFIX + 'gcc' CXX = PREFIX + 'g++' AS = PREFIX + 'gcc' diff --git a/bsp/cvitek/drivers/drv_adc.c b/bsp/cvitek/drivers/drv_adc.c index 7108de75a8..c7a6adb466 100644 --- a/bsp/cvitek/drivers/drv_adc.c +++ b/bsp/cvitek/drivers/drv_adc.c @@ -11,6 +11,7 @@ #include #include "drv_adc.h" #include "drv_pinmux.h" +#include "drv_ioremap.h" #define DBG_LEVEL DBG_LOG #include @@ -247,15 +248,24 @@ int rt_hw_adc_init(void) { rt_uint8_t i; + for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++) + { + if (!rt_strcmp(adc_dev_config[i].name, "adc1")) + { + adc_dev_config[i].base = (rt_ubase_t)DRV_IOREMAP(SARADC_BASE, 0x10000); + } + else if (!rt_strcmp(adc_dev_config[i].name, "adc2")) + { + adc_dev_config[i].base = (rt_ubase_t)DRV_IOREMAP(RTC_ADC_BASE, 0x1000); + } + } + rt_hw_adc_pinmux_config(); for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++) { cvi_do_calibration(adc_dev_config[i].base); - } - for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++) - { if (rt_hw_adc_register(&adc_dev_config[i].device, adc_dev_config[i].name, &_adc_ops, &adc_dev_config[i]) != RT_EOK) { LOG_E("%s register failed!", adc_dev_config[i].name); diff --git a/bsp/cvitek/drivers/drv_eth.c b/bsp/cvitek/drivers/drv_eth.c index d25b395a11..a798a70f7d 100644 --- a/bsp/cvitek/drivers/drv_eth.c +++ b/bsp/cvitek/drivers/drv_eth.c @@ -32,7 +32,7 @@ struct _dw_eth { - rt_uint32_t *base; + rt_ubase_t base; rt_uint32_t irq; struct eth_device parent; /* inherit from ethernet device */ @@ -55,20 +55,20 @@ static uint8_t RecvDataBuf[GMAC_BUF_LEN]; static void cvi_ephy_id_init(void) { // set rg_ephy_apb_rw_sel 0x0804@[0]=1/APB by using APB interface - mmio_write_32(0x03009804, 0x0001); + mmio_write_32(ETH_PHY_BASE + 0x804, 0x0001); // Release 0x0800[0]=0/shutdown - mmio_write_32(0x03009800, 0x0900); + mmio_write_32(ETH_PHY_BASE + 0x800, 0x0900); // Release 0x0800[2]=1/dig_rst_n, Let mii_reg can be accessabile - mmio_write_32(0x03009800, 0x0904); + mmio_write_32(ETH_PHY_BASE + 0x800, 0x0904); // PHY_ID - mmio_write_32(0x03009008, 0x0043); - mmio_write_32(0x0300900c, 0x5649); + mmio_write_32(ETH_PHY_BASE + 0x008, 0x0043); + mmio_write_32(ETH_PHY_BASE + 0x00c, 0x5649); // switch to MDIO control by ETH_MAC - mmio_write_32(0x03009804, 0x0000); + mmio_write_32(ETH_PHY_BASE + 0x804, 0x0000); } static int cvi_eth_mac_phy_enable(uint32_t enable) @@ -256,7 +256,7 @@ static rt_err_t rt_dw_eth_init(rt_device_t dev) } else { - err = -RT_ERROR; + return -RT_ERROR; } return RT_EOK; @@ -431,7 +431,7 @@ static int rthw_eth_init(void) { rt_err_t ret = RT_EOK; - dw_eth_device.base = (rt_uint32_t *)DW_MAC_BASE; + dw_eth_device.base = (rt_ubase_t)DW_MAC_BASE; dw_eth_device.irq = DW_MAC_IRQ; dw_eth_device.parent.parent.ops = &dw_eth_ops; diff --git a/bsp/cvitek/drivers/drv_eth.h b/bsp/cvitek/drivers/drv_eth.h index c390ae441c..54d8ded9af 100644 --- a/bsp/cvitek/drivers/drv_eth.h +++ b/bsp/cvitek/drivers/drv_eth.h @@ -13,8 +13,9 @@ #include "mmio.h" #include "dw_eth_mac.h" #include "cvi_eth_phy.h" +#include "drv_ioremap.h" -#define DW_MAC_BASE 0x04070000UL +#define DW_MAC_BASE DRV_IOREMAP((void *)0x04070000, 0x10000) #define DW_MAC_IRQ 31 #endif /* __DRV_ETH_H__ */ diff --git a/bsp/cvitek/drivers/drv_gpio.c b/bsp/cvitek/drivers/drv_gpio.c index e90fd48135..74f2e1c626 100644 --- a/bsp/cvitek/drivers/drv_gpio.c +++ b/bsp/cvitek/drivers/drv_gpio.c @@ -11,9 +11,7 @@ #include #include #include -#ifdef RT_USING_SMART -#include -#endif +#include "drv_ioremap.h" #ifdef RT_USING_PIN #include "drv_gpio.h" @@ -303,6 +301,9 @@ static void rt_hw_gpio_isr(int irqno, void *param) int rt_hw_gpio_init(void) { + dwapb_gpio_base = (rt_ubase_t)DRV_IOREMAP((void *)dwapb_gpio_base, 0x1000); + dwapb_gpio_base_e = (rt_ubase_t)DRV_IOREMAP((void *)dwapb_gpio_base_e, 0x1000); + rt_device_pin_register("gpio", &_dwapb_ops, RT_NULL); #define INT_INSTALL_GPIO_DEVICE(no) \ diff --git a/bsp/cvitek/drivers/drv_hw_i2c.c b/bsp/cvitek/drivers/drv_hw_i2c.c index 7e116f9fea..114745c300 100644 --- a/bsp/cvitek/drivers/drv_hw_i2c.c +++ b/bsp/cvitek/drivers/drv_hw_i2c.c @@ -11,6 +11,7 @@ #include #include #include "drv_pinmux.h" +#include "drv_ioremap.h" #define DBG_TAG "drv.i2c" #define DBG_LVL DBG_INFO @@ -583,6 +584,7 @@ int rt_hw_i2c_init(void) for (rt_size_t i = 0; i < sizeof(_i2c_obj) / sizeof(struct dw_iic_bus); i++) { + _i2c_obj->iic_base = (rt_ubase_t)DRV_IOREMAP((void *)_i2c_obj->iic_basee, 0x10000); dw_iic_init(_i2c_obj->iic_base); _i2c_obj[i].parent.ops = &i2c_ops; diff --git a/bsp/cvitek/drivers/drv_por.c b/bsp/cvitek/drivers/drv_por.c index 0d25f06582..de3795a3cf 100644 --- a/bsp/cvitek/drivers/drv_por.c +++ b/bsp/cvitek/drivers/drv_por.c @@ -17,9 +17,13 @@ #include #include "mmio.h" +#include "drv_ioremap.h" -#define CVI_RTC_CTRL_BASE 0x05025000U -#define CVI_RTC_REG_BASE 0x05026000U +static rt_ubase_t _cvi_rtc_ctrl_base = 0x05025000U; +static rt_ubase_t _cvi_rtc_reg_base = 0x05026000U; + +#define CVI_RTC_CTRL_BASE _cvi_rtc_ctrl_base +#define CVI_RTC_REG_BASE _cvi_rtc_reg_base #define RTC_CTRL0_UNLOCKKEY 0x4 #define RTC_CTRL0 0x8 #define RTC_APB_BUSY_SEL 0x3C @@ -48,8 +52,14 @@ static int cvi_restart(void) void rt_hw_cpu_reset(void) { + rt_kprintf("Rebooting...\n"); + + _cvi_rtc_ctrl_base = (rt_ubase_t)DRV_IOREMAP((void *)_cvi_rtc_ctrl_base, 0x1000); + _cvi_rtc_reg_base = (rt_ubase_t)DRV_IOREMAP((void *)_cvi_rtc_reg_base, 0x1000); + cvi_restart(); + rt_kprintf("ERROR: Failed to reboot the system\n"); while (1); } diff --git a/bsp/cvitek/drivers/drv_pwm.c b/bsp/cvitek/drivers/drv_pwm.c index 28616218a9..a07b688727 100644 --- a/bsp/cvitek/drivers/drv_pwm.c +++ b/bsp/cvitek/drivers/drv_pwm.c @@ -11,6 +11,7 @@ #include #include "drv_pwm.h" #include "drv_pinmux.h" +#include "drv_ioremap.h" #define DBG_LEVEL DBG_LOG #include @@ -326,6 +327,8 @@ int rt_hw_pwm_init(void) for (i = 0; i < sizeof(cvi_pwm) / sizeof(cvi_pwm[0]); i++) { + cvi_pwm[i].device.base = (rt_ubase_t)DRV_IOREMAP((void *)cvi_pwm[i].device.base, 0x1000); + result = rt_device_pwm_register(&cvi_pwm[i].device, cvi_pwm[i].name, &cvi_pwm_ops, &cvi_pwm[i]); if (result != RT_EOK) { diff --git a/bsp/cvitek/drivers/drv_rtc.c b/bsp/cvitek/drivers/drv_rtc.c index a3388afc55..93f2b07082 100644 --- a/bsp/cvitek/drivers/drv_rtc.c +++ b/bsp/cvitek/drivers/drv_rtc.c @@ -17,12 +17,13 @@ #include "pinctrl.h" #include "mmio.h" +#include "drv_ioremap.h" -#define CVI_RTC_BASE 0x05026000U -#define RTC_ALARM_O 17 -#define CVI_RTC_CTRL_BASE 0x05025000U -#define CLK_EN_0 0x03002000U -#define CLK_RTC_25M_BIT (1 << 8) +#define CVI_RTC_BASE 0x05026000U +#define RTC_ALARM_O 17 +#define CVI_RTC_CTRL_BASE 0x05025000U +#define CLK_EN_0 0x03002000U +#define CLK_RTC_25M_BIT (1 << 8) /* CVITEK RTC registers */ #define CVI_RTC_ANA_CALIB 0x0 @@ -57,6 +58,7 @@ struct rtc_device_object { rt_rtc_dev_t rtc_dev; + rt_ubase_t base; }; static struct rtc_device_object rtc_device; @@ -91,25 +93,26 @@ static int rtc_month_days(unsigned int month, unsigned int year) static void hal_cvi_rtc_clk_set(int enable) { uint32_t clk_state; + rt_ubase_t clk = (rt_ubase_t)DRV_IOREMAP((void *)CLK_EN_0, 0x1000); - clk_state = mmio_read_32((long unsigned int)CLK_EN_0); + clk_state = mmio_read_32(clk); if(enable) clk_state |= CLK_RTC_25M_BIT; else clk_state &= ~(CLK_RTC_25M_BIT); - mmio_write_32((long unsigned int)CLK_EN_0, clk_state); + mmio_write_32(clk, clk_state); } static void hal_cvi_rtc_enable_sec_counter(uintptr_t rtc_base) { uint32_t value = 0; - value = mmio_read_32(rtc_base + CVI_RTC_SEC_PULSE_GEN) & ~(1 << 31); + value = mmio_read_32(rtc_base + CVI_RTC_SEC_PULSE_GEN) & 0x7FFFFFFF; mmio_write_32(rtc_base + CVI_RTC_SEC_PULSE_GEN, value); - value = mmio_read_32(rtc_base + CVI_RTC_ANA_CALIB) & ~(1 << 31); + value = mmio_read_32(rtc_base + CVI_RTC_ANA_CALIB) & 0x7FFFFFFF; mmio_write_32(rtc_base + CVI_RTC_ANA_CALIB, value); mmio_read_32(rtc_base + CVI_RTC_SEC_CNTR_VALUE); @@ -239,7 +242,7 @@ static rt_err_t _rtc_get_timeval(struct timeval *tv) cvi_rtc_time_t t = {0}; struct tm tm_new = {0}; - hal_cvi_rtc_get_time_sec(CVI_RTC_BASE, &sec); + hal_cvi_rtc_get_time_sec(rtc_device.base, &sec); rtc_time64_to_tm(sec, &t); tm_new.tm_sec = t.tm_sec; @@ -258,7 +261,7 @@ static rt_err_t _rtc_get_timeval(struct timeval *tv) static rt_err_t _rtc_init(void) { hal_cvi_rtc_clk_set(1); - hal_cvi_rtc_enable_sec_counter(CVI_RTC_BASE); + hal_cvi_rtc_enable_sec_counter(rtc_device.base); return RT_EOK; } @@ -292,7 +295,7 @@ static rt_err_t _rtc_set_secs(time_t *sec) t.tm_wday = tm.tm_wday; set_sec = rtc_tm_to_time64(&t); - hal_cvi_rtc_set_time(CVI_RTC_BASE, set_sec); + hal_cvi_rtc_set_time(rtc_device.base, set_sec); return result; } @@ -300,7 +303,7 @@ static rt_err_t _rtc_set_secs(time_t *sec) #ifdef RT_USING_ALARM static void rtc_alarm_enable(rt_bool_t enable) { - mmio_write_32(CVI_RTC_BASE + CVI_RTC_ALARM_ENABLE, enable); + mmio_write_32(rtc_device.base + CVI_RTC_ALARM_ENABLE, enable); } static void rt_hw_rtc_isr(int irqno, void *param) @@ -324,7 +327,7 @@ static rt_err_t _rtc_get_alarm(struct rt_rtc_wkalarm *alarm) unsigned long int sec; cvi_rtc_time_t t = {0}; - sec = mmio_read_32(CVI_RTC_BASE + CVI_RTC_ALARM_TIME); + sec = mmio_read_32(rtc_device.base + CVI_RTC_ALARM_TIME); rtc_time64_to_tm(sec, &t); alarm->tm_sec = t.tm_sec; @@ -355,7 +358,7 @@ static rt_err_t _rtc_set_alarm(struct rt_rtc_wkalarm *alarm) t.tm_year = alarm->tm_year; set_sec = rtc_tm_to_time64(&t); - mmio_write_32(CVI_RTC_BASE + CVI_RTC_ALARM_TIME, set_sec); + mmio_write_32(rtc_device.base + CVI_RTC_ALARM_TIME, set_sec); LOG_D("GET_ALARM %d:%d:%d", alarm->tm_hour, alarm->tm_min, alarm->tm_sec); } @@ -386,6 +389,10 @@ static int rt_hw_rtc_init(void) rt_err_t result; rtc_device.rtc_dev.ops = &_rtc_ops; + + rtc_device.base = CVI_RTC_BASE; + rtc_device.base = (rt_ubase_t)DRV_IOREMAP((void *)rtc_device.base, 0x1000); + result = rt_hw_rtc_register(&rtc_device.rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL); if (result != RT_EOK) { diff --git a/bsp/cvitek/drivers/drv_sdhci.c b/bsp/cvitek/drivers/drv_sdhci.c index 1b6c78d6a2..d9ab8d48c3 100644 --- a/bsp/cvitek/drivers/drv_sdhci.c +++ b/bsp/cvitek/drivers/drv_sdhci.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -31,7 +32,7 @@ struct rthw_sdhci { struct rt_mmcsd_host *host; - rt_uint32_t *base; + rt_ubase_t base; rt_uint32_t irq; volatile rt_err_t cmd_error; volatile rt_err_t data_error; @@ -42,7 +43,7 @@ struct rthw_sdhci rt_sem_t sem_data; }; -static uint32_t sdhci_set_card_clock(rt_uint32_t *base, uint32_t srcClock_Hz, uint32_t target_HZ) +static uint32_t sdhci_set_card_clock(rt_ubase_t base, uint32_t srcClock_Hz, uint32_t target_HZ) { uintptr_t BASE = (uintptr_t)base; uint32_t divider = 1U; @@ -118,7 +119,7 @@ static uint32_t sdhci_set_card_clock(rt_uint32_t *base, uint32_t srcClock_Hz, ui return -1; } -static uint32_t SDIF_ChangeCardClock(rt_uint32_t *base, uint32_t srcClock_Hz, uint32_t target_HZ) +static uint32_t SDIF_ChangeCardClock(rt_ubase_t base, uint32_t srcClock_Hz, uint32_t target_HZ) { uintptr_t BASE = (uintptr_t)base; uint32_t divider = 1U; @@ -217,23 +218,26 @@ static void sdhci_wait_data_complete(struct rthw_sdhci *sdhci) } } -uint32_t sdhci_prepare_data(struct rthw_sdhci *sdhci, struct rt_mmcsd_cmd *cmd, struct rt_mmcsd_data *data, sdhci_dma_config_t *dma_config) +static uint32_t sdhci_prepare_data(struct rthw_sdhci *sdhci, struct rt_mmcsd_cmd *cmd, struct rt_mmcsd_data *data, rt_ubase_t start_addr, rt_uint32_t load_len) { uintptr_t BASE = (uintptr_t)sdhci->base; - uint64_t load_addr; uint32_t block_cnt, blksz; uint8_t tmp; + rt_ubase_t dma_addr; blksz = data->blksize; block_cnt = data->blks; - load_addr = (uint64_t)dma_config->dma_des_buffer_start_addr; + rt_hw_cpu_dcache_clean((void *)start_addr, load_len); +#ifdef RT_USING_SMART + dma_addr = (rt_ubase_t)rt_kmem_v2p((void *)start_addr); +#else + dma_addr = start_addr; +#endif - rt_hw_cpu_dcache_clean((void *)load_addr, dma_config->dma_des_buffer_len); - - mmio_write_32(BASE + SDIF_ADMA_SA_LOW, load_addr); - mmio_write_32(BASE + SDIF_ADMA_SA_HIGH, (load_addr >> 32)); + mmio_write_32(BASE + SDIF_ADMA_SA_LOW, dma_addr); + mmio_write_32(BASE + SDIF_ADMA_SA_HIGH, (dma_addr >> 32)); mmio_write_32(BASE + SDIF_DMA_ADDRESS, block_cnt); mmio_write_16(BASE + SDIF_BLOCK_COUNT, 0); @@ -292,7 +296,7 @@ static rt_err_t sdhci_send_data_cmd(struct rthw_sdhci *sdhci, struct rt_mmcsd_cm return -RT_ETIMEOUT; } - void *src_align = NULL; + rt_ubase_t start_addr; void *src_unalign = NULL; if (data) @@ -302,20 +306,19 @@ static rt_err_t sdhci_send_data_cmd(struct rthw_sdhci *sdhci, struct rt_mmcsd_cm { if ((uint64_t)data->buf & (SDMMC_DMA_ALIGN_CACHE - 1)) { - src_align = align_alloc(SDMMC_DMA_ALIGN_CACHE, dma_config.dma_des_buffer_len, (void **)&src_unalign); - dma_config.dma_des_buffer_start_addr = (uint32_t *)src_align; + start_addr = (rt_ubase_t)align_alloc(SDMMC_DMA_ALIGN_CACHE, dma_config.dma_des_buffer_len, (void **)&src_unalign); } else { - dma_config.dma_des_buffer_start_addr = (uint32_t *)data->buf; + start_addr = (rt_ubase_t)data->buf; } } else { - dma_config.dma_des_buffer_start_addr = (uint32_t *)data->buf; + start_addr = (rt_ubase_t)data->buf; } - sdhci_prepare_data(sdhci, cmd, data, &dma_config); + sdhci_prepare_data(sdhci, cmd, data, start_addr, dma_config.dma_des_buffer_len); mode = SDIF_TRNS_DMA; if (mmc_op_multi(cmd->cmd_code) || data->blks > 1) @@ -370,12 +373,11 @@ static rt_err_t sdhci_send_data_cmd(struct rthw_sdhci *sdhci, struct rt_mmcsd_cm if (data->flags & DATA_DIR_READ) { - rt_hw_cpu_dcache_invalidate((uint64_t *)dma_config.dma_des_buffer_start_addr, dma_config.dma_des_buffer_len); + rt_hw_cpu_dcache_invalidate((void *)start_addr, dma_config.dma_des_buffer_len); if (src_unalign) { - memcpy((void *)data->buf, src_align, dma_config.dma_des_buffer_len); + memcpy((void *)data->buf, (void *)start_addr, dma_config.dma_des_buffer_len); rt_free(src_unalign); - src_align = NULL; src_unalign = NULL; } } @@ -525,7 +527,7 @@ static void sdhci_transfer_handle_irq(int irqno, void *param) } while (intmask && --max_loop); } -static uint32_t sdhci_set_clock(rt_uint32_t *base, uint32_t target_hz) +static uint32_t sdhci_set_clock(rt_ubase_t base, uint32_t target_hz) { uint32_t source_clock_hz; uint32_t ret; @@ -539,7 +541,7 @@ static uint32_t sdhci_set_clock(rt_uint32_t *base, uint32_t target_hz) return ret; } -static void sdhci_set_bus_width(rt_uint32_t *base, uint8_t bus_width) +static void sdhci_set_bus_width(rt_ubase_t base, uint8_t bus_width) { uintptr_t BASE = (uintptr_t)base; uint32_t ctrl; @@ -562,7 +564,7 @@ static void sdhci_set_bus_width(rt_uint32_t *base, uint8_t bus_width) mmio_write_8(BASE + SDIF_HOST_CONTROL, ctrl); } -static void sdhci_enable_card_power(rt_uint32_t *base, bool enable) +static void sdhci_enable_card_power(rt_ubase_t base, bool enable) { uintptr_t BASE = (uintptr_t)base; @@ -576,7 +578,7 @@ static void sdhci_enable_card_power(rt_uint32_t *base, bool enable) } } -static uint32_t sdhci_detect_card_insert(rt_uint32_t *base, bool data3) +static uint32_t sdhci_detect_card_insert(rt_ubase_t base, bool data3) { uintptr_t BASE = (uintptr_t)base; if (data3) @@ -589,7 +591,7 @@ static uint32_t sdhci_detect_card_insert(rt_uint32_t *base, bool data3) } } -static void sdhci_enable_card_clock(rt_uint32_t *base, bool enable) +static void sdhci_enable_card_clock(rt_ubase_t base, bool enable) { uintptr_t BASE = (uintptr_t)base; if (enable) @@ -602,7 +604,7 @@ static void sdhci_enable_card_clock(rt_uint32_t *base, bool enable) } } -static void sdhci_hw_reset(rt_uint32_t *base) +static void sdhci_hw_reset(rt_ubase_t base) { uintptr_t BASE = (uintptr_t)base; @@ -616,11 +618,11 @@ static void sdhci_hw_reset(rt_uint32_t *base) #define REG_TOP_SD_PWRSW_CTRL (0x1F4) -static void sdhci_pad_setting(rt_uint32_t *base) +static void sdhci_pad_setting(rt_ubase_t base) { uintptr_t BASE = (uintptr_t)base; - if (BASE == SDIO0_BASE) + if (BASE == (rt_ubase_t)SDIO0_BASE) { //set power for sd0 mmio_write_32(TOP_BASE + REG_TOP_SD_PWRSW_CTRL, 0x9); @@ -646,7 +648,7 @@ static void sdhci_pad_setting(rt_uint32_t *base) mmio_write_8(REG_SDIO0_DAT2_PIO_REG, REG_SDIO0_DAT2_PIO_VALUE); mmio_write_8(REG_SDIO0_DAT3_PIO_REG, REG_SDIO0_DAT3_PIO_VALUE); } - else if(BASE == SDIO1_BASE) + else if(BASE == (rt_ubase_t)SDIO1_BASE) { // set rtc sdio1 related register mmio_write_32(RTCSYS_CTRL, 0x1); @@ -671,7 +673,7 @@ static void sdhci_pad_setting(rt_uint32_t *base) mmio_write_8(REG_SDIO1_DAT2_PIO_REG, REG_SDIO1_DAT2_PIO_VALUE); mmio_write_8(REG_SDIO1_DAT3_PIO_REG, REG_SDIO1_DAT3_PIO_VALUE); } - else if(BASE == SDIO2_BASE) + else if(BASE == (rt_ubase_t)SDIO2_BASE) { //set pu/down mmio_write_32(REG_SDIO2_RSTN_PAD_REG, (mmio_read_32(REG_SDIO2_RSTN_PAD_REG) & REG_SDIO2_PAD_MASK) | REG_SDIO2_RSTN_PAD_VALUE << REG_SDIO2_PAD_SHIFT); @@ -693,7 +695,7 @@ static void sdhci_pad_setting(rt_uint32_t *base) } } -static void sdhci_phy_init(rt_uint32_t *base) +static void sdhci_phy_init(rt_ubase_t base) { uintptr_t BASE = (uintptr_t)base; @@ -705,7 +707,7 @@ static void sdhci_phy_init(rt_uint32_t *base) sdhci_pad_setting(base); - if (BASE == SDIO2_BASE) + if (BASE == (rt_ubase_t)SDIO2_BASE) { //reg_0x200[0] = 1 for sd2 mmio_write_32(vendor_base, mmio_read_32(vendor_base) | BIT(0)); @@ -714,7 +716,7 @@ static void sdhci_phy_init(rt_uint32_t *base) //reg_0x200[1] = 1 mmio_write_32(vendor_base, mmio_read_32(vendor_base) | BIT(1)); - if (BASE == SDIO1_BASE) + if (BASE == (rt_ubase_t)SDIO1_BASE) { //reg_0x200[16] = 1 for sd1 mmio_write_32(vendor_base, mmio_read_32(vendor_base) | BIT(16)); @@ -725,7 +727,7 @@ static void sdhci_phy_init(rt_uint32_t *base) mmio_write_32(vendor_base + SDIF_PHY_TX_RX_DLY, 0x1000100); } -static void sdhci_init(rt_uint32_t *base) +static void sdhci_init(rt_ubase_t base) { uintptr_t BASE = (uintptr_t)base; @@ -774,7 +776,7 @@ void rthw_sdhci_set_config(struct rthw_sdhci *sdhci) static bool sd1_clock_state = false; static bool sd2_clock_state = false; - if (BASE == SDIO0_BASE) + if (BASE == (rt_ubase_t)SDIO0_BASE) { LOG_D("MMC_FLAG_SDCARD."); if (sd0_clock_state == false) @@ -784,7 +786,7 @@ void rthw_sdhci_set_config(struct rthw_sdhci *sdhci) sd0_clock_state = true; } } - else if (BASE == SDIO1_BASE) + else if (BASE == (rt_ubase_t)SDIO1_BASE) { LOG_D("MMC_FLAG_SDIO."); if (sd1_clock_state == false) @@ -794,7 +796,7 @@ void rthw_sdhci_set_config(struct rthw_sdhci *sdhci) sd1_clock_state = true; } } - else if (BASE == SDIO2_BASE) + else if (BASE == (rt_ubase_t)SDIO2_BASE) { LOG_D("MMC_FLAG_EMMC."); if (sd2_clock_state == false) @@ -842,7 +844,7 @@ static void rthw_sdhci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req * struct rt_mmcsd_cmd *cmd = req->cmd; struct rt_mmcsd_data *data = req->data; - LOG_D("[%s%s%s%s%s]REQ: CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c addr:%08x, blks:%d, blksize:%d datalen:%d", + LOG_D("[%s%s%s%s%s]REQ: CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c addr:%p, blks:%d, blksize:%d datalen:%d", (host->card == RT_NULL) ? "Unknown" : "", (host->card) && (host->card->card_type == CARD_TYPE_MMC) ? "MMC" : "", (host->card) && (host->card->card_type == CARD_TYPE_SD) ? "SD" : "", @@ -995,7 +997,7 @@ static int rthw_sdhci_init(void) return ret; } - sdhci->base = (rt_uint32_t *)SDIO0_BASE; + sdhci->base = (rt_ubase_t)SDIO0_BASE; sdhci->irq = SDIO0_IRQ; strcpy(sdhci->name, "sdio0"); rthw_sdhci_set_config(sdhci); @@ -1026,7 +1028,7 @@ INIT_DEVICE_EXPORT(rthw_sdhci_init); void sdhci_reg_dump(uint8_t argc, char **argv) { - rt_uint32_t *base; + rt_ubase_t base; if (argc < 2) { rt_kprintf("Usage: sdhci_reg_dump 0/1/2\n"); @@ -1034,11 +1036,11 @@ void sdhci_reg_dump(uint8_t argc, char **argv) } if (0 == atoi(argv[1])) - base = (void *)(rt_uint32_t *)SDIO0_BASE; + base = (rt_ubase_t)SDIO0_BASE; else if (1 == atoi(argv[1])) - base = (void *)(rt_uint32_t *)SDIO1_BASE; + base = (rt_ubase_t)SDIO1_BASE; else - base = (void *)(rt_uint32_t *)SDIO2_BASE; + base = (rt_ubase_t)SDIO2_BASE; uintptr_t BASE = (uintptr_t)base; diff --git a/bsp/cvitek/drivers/drv_sdhci.h b/bsp/cvitek/drivers/drv_sdhci.h index e29cf93c03..64f1fdbbd5 100644 --- a/bsp/cvitek/drivers/drv_sdhci.h +++ b/bsp/cvitek/drivers/drv_sdhci.h @@ -32,7 +32,7 @@ typedef struct { sdhci_dma_mode_e mode; ///< define the DMA mode */ - uint32_t *dma_des_buffer_start_addr; ///< internal DMA descriptor start address + rt_ubase_t dma_des_buffer_start_addr; ///< internal DMA descriptor start address uint32_t dma_des_buffer_len; /// internal DMA buffer descriptor buffer len ,user need to pay attention to the /// dma descriptor buffer length if it is bigger enough for your transfer uint8_t dma_dws_skip_len; ///< define the descriptor skip length ,the length between two descriptor diff --git a/bsp/cvitek/drivers/drv_spi.c b/bsp/cvitek/drivers/drv_spi.c index 10d6c9011b..5b261b8b9b 100644 --- a/bsp/cvitek/drivers/drv_spi.c +++ b/bsp/cvitek/drivers/drv_spi.c @@ -17,6 +17,7 @@ #include "drv_spi.h" #include "drv_pinmux.h" +#include "drv_ioremap.h" #define DBG_LEVEL DBG_LOG #include @@ -334,6 +335,8 @@ int rt_hw_spi_init(void) for (rt_size_t i = 0; i < sizeof(_spi_obj) / sizeof(struct _device_spi); i++) { + _spi_obj[i].base_addr = (rt_ubase_t)DRV_IOREMAP((void *)_spi_obj[i].base_addr, 0x1000); + _spi_obj[i].spi_bus.parent.user_data = (void *)&_spi_obj[i]; ret = rt_spi_bus_register(&_spi_obj[i].spi_bus, _spi_obj[i].device_name, &_spi_ops); } diff --git a/bsp/cvitek/drivers/drv_timer.c b/bsp/cvitek/drivers/drv_timer.c index 957a643618..4028b77d17 100644 --- a/bsp/cvitek/drivers/drv_timer.c +++ b/bsp/cvitek/drivers/drv_timer.c @@ -17,6 +17,8 @@ #include "pinctrl.h" #include "mmio.h" +#include "drv_ioremap.h" + #define DW_NR_TIMERS 8 #define TIMER_FREQ 25000000 @@ -239,7 +241,10 @@ void hal_timer_set_disable(dw_timer_regs_t *timer_base) } uint32_t hal_timer_get_enable(dw_timer_regs_t *timer_base) { - return (((timer_base->TCR) & DW_TIMER_CTL_ENABLE_SEL_EN) ? (uint32_t)1 : (uint32_t)0); + if ((timer_base->TCR) & DW_TIMER_CTL_ENABLE_SEL_EN) + return 1; + + return 0; } void hal_timer_set_mode_free(dw_timer_regs_t *timer_base) { @@ -251,7 +256,10 @@ void hal_timer_set_mode_load(dw_timer_regs_t *timer_base) } uint32_t hal_timer_get_model(dw_timer_regs_t *timer_base) { - return (((timer_base->TCR) & DW_TIMER_CTL_MODE_SEL_EN) ? (uint32_t)1 : (uint32_t)0); + if ((timer_base->TCR) & DW_TIMER_CTL_MODE_SEL_EN) + return 1; + + return 0; } void hal_timer_set_mask(dw_timer_regs_t *timer_base) { @@ -263,7 +271,10 @@ void hal_timer_set_unmask(dw_timer_regs_t *timer_base) } uint32_t hal_timer_get_mask(dw_timer_regs_t *timer_base) { - return (((timer_base->TCR) & DW_TIMER_CTL_INT_MAKS_EN) ? (uint32_t)1 : (uint32_t)0); + if ((timer_base->TCR) & DW_TIMER_CTL_INT_MAKS_EN) + return 1; + + return 0; } void hal_timer_set_hardtrigger_en(dw_timer_regs_t *timer_base) { @@ -275,15 +286,24 @@ void hal_timer_set_hardtrigger_dis(dw_timer_regs_t *timer_base) } uint32_t hal_timer_get_hardtrigger(dw_timer_regs_t *timer_base) { - return (((timer_base->TCR) & DW_TIMER_CTL_HARD_TRIG_EN) ? (uint32_t)1 : (uint32_t)0); + if ((timer_base->TCR) & DW_TIMER_CTL_HARD_TRIG_EN) + return 1; + + return 0; } uint32_t hal_timer_clear_irq(dw_timer_regs_t *timer_base) { - return (((timer_base->TEOI) & DW_TIMER_EOI_REG_EN) ? (uint32_t)1 : (uint32_t)0); + if ((timer_base->TEOI) & DW_TIMER_EOI_REG_EN) + return 1; + + return 0; } uint32_t hal_timer_get_int_status(dw_timer_regs_t *timer_base) { - return (((timer_base->TIS) & DW_TIMER_INT_STATUS_EN) ? (uint32_t)1 : (uint32_t)0); + if ((timer_base->TIS) & DW_TIMER_INT_STATUS_EN) + return 1; + + return 0; } void hal_timer_reset_register(dw_timer_regs_t *timer_base) { @@ -404,9 +424,8 @@ int rt_hw_timer_init(void) for (uint32_t i = 0; i < sizeof(_timer_obj) / sizeof(_timer_obj[0]); i++) { -#if defined(ARCH_ARM) - _timer_obj[i].base = (dw_timer_regs_t *)rt_ioremap((void*)_timer_obj[i].base, 0x10000); -#endif /* defined(ARCH_ARM) */ + _timer_obj[i].base = (dw_timer_regs_t *)DRV_IOREMAP((void*)_timer_obj[i].base, 0x10000); + _timer_obj[i].timer.info = &_timer_info; _timer_obj[i].timer.ops = &_timer_ops; ret = rt_device_hwtimer_register(&_timer_obj[i].timer, _timer_obj[i].name, &_timer_obj[i]); diff --git a/bsp/cvitek/drivers/drv_uart.c b/bsp/cvitek/drivers/drv_uart.c index fb896b1635..45c8b587eb 100644 --- a/bsp/cvitek/drivers/drv_uart.c +++ b/bsp/cvitek/drivers/drv_uart.c @@ -14,6 +14,7 @@ #include "board.h" #include "drv_uart.h" #include "drv_pinmux.h" +#include "drv_ioremap.h" #define DBG_TAG "DRV.UART" #define DBG_LVL DBG_WARNING @@ -448,45 +449,40 @@ int rt_hw_uart_init(void) pinmux_config(BSP_UART0_RX_PINNAME, UART0_RX, pinname_whitelist_uart0_rx); pinmux_config(BSP_UART0_TX_PINNAME, UART0_TX, pinname_whitelist_uart0_tx); BSP_INSTALL_UART_DEVICE(0); -#if defined(ARCH_ARM) - uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); -#endif /* defined(ARCH_ARM) */ + + uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); #endif #ifdef BSP_USING_UART1 pinmux_config(BSP_UART1_RX_PINNAME, UART1_RX, pinname_whitelist_uart1_rx); pinmux_config(BSP_UART1_TX_PINNAME, UART1_TX, pinname_whitelist_uart1_tx); BSP_INSTALL_UART_DEVICE(1); -#if defined(ARCH_ARM) - uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); -#endif /* defined(ARCH_ARM) */ + + uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); #endif #ifdef BSP_USING_UART2 pinmux_config(BSP_UART2_RX_PINNAME, UART2_RX, pinname_whitelist_uart2_rx); pinmux_config(BSP_UART2_TX_PINNAME, UART2_TX, pinname_whitelist_uart2_tx); BSP_INSTALL_UART_DEVICE(2); -#if defined(ARCH_ARM) - uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); -#endif /* defined(ARCH_ARM) */ + + uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); #endif #ifdef BSP_USING_UART3 pinmux_config(BSP_UART3_RX_PINNAME, UART3_RX, pinname_whitelist_uart3_rx); pinmux_config(BSP_UART3_TX_PINNAME, UART3_TX, pinname_whitelist_uart3_tx); BSP_INSTALL_UART_DEVICE(3); -#if defined(ARCH_ARM) - uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); -#endif /* defined(ARCH_ARM) */ + + uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); #endif #ifdef BSP_USING_UART4 pinmux_config(BSP_UART4_RX_PINNAME, UART4_RX, pinname_whitelist_uart4_rx); pinmux_config(BSP_UART4_TX_PINNAME, UART4_TX, pinname_whitelist_uart4_tx); BSP_INSTALL_UART_DEVICE(4); -#if defined(ARCH_ARM) - uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); -#endif /* defined(ARCH_ARM) */ + + uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); #endif return 0; diff --git a/bsp/cvitek/drivers/drv_wdt.c b/bsp/cvitek/drivers/drv_wdt.c index 80d5203440..0ce21e9e56 100644 --- a/bsp/cvitek/drivers/drv_wdt.c +++ b/bsp/cvitek/drivers/drv_wdt.c @@ -10,6 +10,7 @@ #include #include #include "drv_wdt.h" +#include "drv_ioremap.h" #define DBG_LEVEL DBG_LOG #include @@ -21,13 +22,15 @@ rt_inline void cvi_wdt_top_setting() { uint32_t val; + rt_ubase_t base = (rt_ubase_t)DRV_IOREMAP((void *)(CV_TOP + CV_TOP_WDT_OFFSET), 0x1000); - mmio_write_32(CV_TOP + CV_TOP_WDT_OFFSET, CV_TOP_WDT_VAL); + mmio_write_32(base, CV_TOP_WDT_VAL); - val = mmio_read_32(CV_RST_REG); - mmio_write_32(CV_RST_REG, val & ~CV_RST_WDT); + base = (rt_ubase_t)DRV_IOREMAP((void *)CV_RST_REG, 0x1000); + val = mmio_read_32(base); + mmio_write_32(base, val & ~CV_RST_WDT); rt_hw_us_delay(10); - mmio_write_32(CV_RST_REG, val | CV_RST_WDT); + mmio_write_32(base, val | CV_RST_WDT); } rt_inline void cvi_wdt_start_en(unsigned long reg_base) @@ -91,7 +94,7 @@ struct _cvi_wdt_dev { struct rt_watchdog_device device; const char *name; - rt_uint32_t base; + rt_ubase_t base; rt_uint32_t timeout; }; @@ -227,6 +230,8 @@ int rt_hw_wdt_init(void) for (i = 0; i < sizeof(_wdt_dev) / sizeof(_wdt_dev[0]); i ++) { _wdt_dev[i].device.ops = &_wdt_ops; + _wdt_dev[i].base = (rt_ubase_t)DRV_IOREMAP((void *)_wdt_dev[i].base, 0x1000); + if (rt_hw_watchdog_register(&_wdt_dev[i].device, _wdt_dev[i].name, RT_DEVICE_FLAG_RDWR, RT_NULL) != RT_EOK) { LOG_E("%s register failed!", _wdt_dev[i].name); diff --git a/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h index 0e5c3c911c..8d0b45dfa8 100755 --- a/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h +++ b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h @@ -10,6 +10,7 @@ #include "cv180x_pinlist_swconfig.h" #include "cv180x_reg_fmux_gpio.h" +#include "drv_ioremap.h" #define PAD_MIPI_TXM4__MIPI_TXM4 0 #define PAD_MIPI_TXP4__MIPI_TXP4 0 @@ -22,7 +23,8 @@ #define PAD_MIPI_TXM0__MIPI_TXM0 0 #define PAD_MIPI_TXP0__MIPI_TXP0 0 -#define PINMUX_BASE 0x03001000 +#define PINMUX_BASE (uintptr_t)DRV_IOREMAP((void *)0x3001000, 0x1000) + #define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK #define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET #define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME diff --git a/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h index 7bec2f2dfb..262704c680 100644 --- a/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h +++ b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h @@ -8,9 +8,9 @@ #ifndef __PINCTRL_CV181X_H__ #define __PINCTRL_CV181X_H__ -//#include "../core.h" #include "cv181x_pinlist_swconfig.h" #include "cv181x_reg_fmux_gpio.h" +#include "drv_ioremap.h" #define PAD_MIPI_TXM4__MIPI_TXM4 0 #define PAD_MIPI_TXP4__MIPI_TXP4 0 @@ -23,12 +23,8 @@ #define PAD_MIPI_TXM0__MIPI_TXM0 0 #define PAD_MIPI_TXP0__MIPI_TXP0 0 -#if defined(ARCH_ARM) -extern rt_ubase_t pinmux_base_ioremap(void); -#define PINMUX_BASE pinmux_base_ioremap() -#else -#define PINMUX_BASE 0x03001000 -#endif /* defined(ARCH_ARM) */ +#define PINMUX_BASE (uintptr_t)DRV_IOREMAP((void *)0x3001000, 0x1000) + #define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK #define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET #define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME diff --git a/bsp/cvitek/drivers/libraries/eth/cvi_eth_phy.h b/bsp/cvitek/drivers/libraries/eth/cvi_eth_phy.h index 4494ac9d7f..9272476052 100644 --- a/bsp/cvitek/drivers/libraries/eth/cvi_eth_phy.h +++ b/bsp/cvitek/drivers/libraries/eth/cvi_eth_phy.h @@ -28,6 +28,7 @@ extern "C" { #include #include "mmio.h" +#include "drv_ioremap.h" /** \brief Ethernet link speed @@ -200,8 +201,8 @@ typedef enum eth_link_state /* 1000BASE-T Control register */ #define CVI_ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ #define CVI_ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ -#define CTL1000_AS_MASTER 0x0800 -#define CTL1000_ENABLE_MASTER 0x1000 +#define CTL1000_AS_MASTER 0x0800 +#define CTL1000_ENABLE_MASTER 0x1000 /* 1000BASE-T Status register */ #define CVI_LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ @@ -210,8 +211,8 @@ typedef enum eth_link_state #define CVI_LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define CVI_FLOW_CTRL_TX 0x01 -#define CVI_FLOW_CTRL_RX 0x02 +#define CVI_FLOW_CTRL_TX 0x01 +#define CVI_FLOW_CTRL_RX 0x02 /* MMD Access Control register fields */ #define CVI_MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ @@ -348,13 +349,13 @@ typedef struct { } eth_phy_dev_t; /* ethernet phy config */ -#define ETH_PHY_BASE 0x03009000 -#define ETH_PHY_INIT_MASK 0xFFFFFFF9 -#define ETH_PHY_SHUTDOWN (1 << 1) -#define ETH_PHY_POWERUP 0xFFFFFFFD -#define ETH_PHY_RESET 0xFFFFFFFB -#define ETH_PHY_RESET_N (1 << 2) -#define ETH_PHY_LED_LOW_ACTIVE (1 << 3) +#define ETH_PHY_BASE (uintptr_t)DRV_IOREMAP((void *)0x03009000, 0x1000) +#define ETH_PHY_INIT_MASK 0xFFFFFFF9 +#define ETH_PHY_SHUTDOWN (1 << 1) +#define ETH_PHY_POWERUP 0xFFFFFFFD +#define ETH_PHY_RESET 0xFFFFFFFB +#define ETH_PHY_RESET_N (1 << 2) +#define ETH_PHY_LED_LOW_ACTIVE (1 << 3) int generic_phy_config_aneg(eth_phy_dev_t *dev); int generic_phy_restart_aneg(eth_phy_dev_t *dev); diff --git a/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.c b/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.c index dad7fb3ff3..bbe4c1176a 100644 --- a/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.c +++ b/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.c @@ -14,10 +14,13 @@ * limitations under the License. */ #include +#include #include "dw_eth_mac.h" #include "cache.h" #include "string.h" +#include "drv_ioremap.h" + #define roundup(x, y) ( \ { \ @@ -80,10 +83,15 @@ static void tx_descs_init(eth_mac_handle_t handle) struct dmamacdescr *desc_p; uint32_t idx; - for (idx = 0; idx < CVI_CONFIG_TX_DESCR_NUM; idx++) { + for (idx = 0; idx < CVI_CONFIG_TX_DESCR_NUM; idx ++) { desc_p = &desc_table_p[idx]; +#ifdef RT_USING_SMART + desc_p->dmamac_addr = (unsigned long)rt_kmem_v2p((void *)&txbuffs[idx * CVI_CONFIG_ETH_BUFSIZE]); + desc_p->dmamac_next = (unsigned long)rt_kmem_v2p((void *)&desc_table_p[idx + 1]); +#else desc_p->dmamac_addr = (unsigned long)&txbuffs[idx * CVI_CONFIG_ETH_BUFSIZE]; desc_p->dmamac_next = (unsigned long)&desc_table_p[idx + 1]; +#endif #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status &= ~(CVI_DESC_TXSTS_TXINT | CVI_DESC_TXSTS_TXLAST | @@ -101,12 +109,20 @@ static void tx_descs_init(eth_mac_handle_t handle) } /* Correcting the last pointer of the chain */ + #ifdef RT_USING_SMART + desc_p->dmamac_next = (unsigned long)rt_kmem_v2p((void *)&desc_table_p[0]); + #else desc_p->dmamac_next = (unsigned long)&desc_table_p[0]; + #endif /* Flush all Tx buffer descriptors at once */ rt_hw_cpu_dcache_clean((void *)priv->tx_mac_descrtable, sizeof(priv->tx_mac_descrtable)); - dma_reg->txdesclistaddr = (unsigned long)&desc_table_p[0]; +#ifdef RT_USING_SMART + dma_reg->txdesclistaddr = (rt_ubase_t)rt_kmem_v2p((void *)&desc_table_p[0]); +#else + dma_reg->txdesclistaddr = (reg_type)&desc_table_p[0]; +#endif priv->tx_currdescnum = 0; } @@ -131,23 +147,34 @@ static void rx_descs_init(eth_mac_handle_t handle) for (idx = 0; idx < CVI_CONFIG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; +#ifdef RT_USING_SMART + desc_p->dmamac_addr = (unsigned long)rt_kmem_v2p((void *)&rxbuffs[idx * CVI_CONFIG_ETH_BUFSIZE]); + desc_p->dmamac_next = (unsigned long)rt_kmem_v2p((void *)&desc_table_p[idx + 1]); +#else desc_p->dmamac_addr = (unsigned long)&rxbuffs[idx * CVI_CONFIG_ETH_BUFSIZE]; desc_p->dmamac_next = (unsigned long)&desc_table_p[idx + 1]; +#endif - desc_p->dmamac_cntl = - (CVI_MAC_MAX_FRAME_SZ & CVI_DESC_RXCTRL_SIZE1MASK) | - CVI_DESC_RXCTRL_RXCHAIN; + desc_p->dmamac_cntl = (CVI_MAC_MAX_FRAME_SZ & CVI_DESC_RXCTRL_SIZE1MASK) | CVI_DESC_RXCTRL_RXCHAIN; desc_p->txrx_status = CVI_DESC_RXSTS_OWNBYDMA; } /* Correcting the last pointer of the chain */ +#ifdef RT_USING_SMART + desc_p->dmamac_next = (unsigned long)rt_kmem_v2p((void *)&desc_table_p[0]); +#else desc_p->dmamac_next = (unsigned long)&desc_table_p[0]; +#endif /* Flush all Rx buffer descriptors at once */ rt_hw_cpu_dcache_clean((void *)priv->rx_mac_descrtable, sizeof(priv->rx_mac_descrtable)); - dma_reg->rxdesclistaddr = (unsigned long)&desc_table_p[0]; +#ifdef RT_USING_SMART + dma_reg->rxdesclistaddr = (rt_ubase_t)rt_kmem_v2p((void *)&desc_table_p[0]); +#else + dma_reg->rxdesclistaddr = (reg_type)&desc_table_p[0]; +#endif priv->rx_currdescnum = 0; } @@ -318,7 +345,7 @@ static int32_t designware_eth_send(eth_mac_handle_t handle, const uint8_t *frame struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; uint64_t desc_start = (uint64_t)desc_p; uint64_t desc_end = desc_start + roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN); - uint64_t data_start = desc_p->dmamac_addr; + uint64_t data_start = (uint64_t)DRV_IOREMAP((void *)desc_p->dmamac_addr, 0x1000); uint64_t data_end = data_start + roundup(length, DW_GMAC_DMA_ALIGN); uint32_t count = 0; @@ -332,12 +359,16 @@ static int32_t designware_eth_send(eth_mac_handle_t handle, const uint8_t *frame */ /* Check if the descriptor is owned by CPU */ - while (1) { + while (1) + { rt_hw_cpu_dcache_invalidate((void *)desc_start, desc_end - desc_start); - if (!(desc_p->txrx_status & CVI_DESC_TXSTS_OWNBYDMA)) { + if (!(desc_p->txrx_status & CVI_DESC_TXSTS_OWNBYDMA)) + { break; } - if (count > 1000) { + + if (count > 1000) + { rt_kprintf("desc onwer is DMA\n"); return -1; } @@ -390,22 +421,23 @@ static int32_t designware_eth_recv(eth_mac_handle_t handle, uint8_t **packetp) struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; int32_t length = -1; uint64_t desc_start = (uint64_t)desc_p; - uint64_t desc_end = desc_start + - roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN); - uint64_t data_start = desc_p->dmamac_addr; + uint64_t desc_end = desc_start + roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN); + uint64_t data_start = (uint64_t)DRV_IOREMAP((void *)desc_p->dmamac_addr, 0x1000); uint64_t data_end; /* Invalidate entire buffer descriptor */ rt_hw_cpu_dcache_invalidate((void *)desc_start, desc_end - desc_start); status = desc_p->txrx_status; /* Check if the owner is the CPU */ - if (!(status & CVI_DESC_RXSTS_OWNBYDMA)) { - length = (status & CVI_DESC_RXSTS_FRMLENMSK) >> - CVI_DESC_RXSTS_FRMLENSHFT; + if (!(status & CVI_DESC_RXSTS_OWNBYDMA)) + { + length = (status & CVI_DESC_RXSTS_FRMLENMSK) >> CVI_DESC_RXSTS_FRMLENSHFT; + /* Invalidate received data */ data_end = data_start + roundup(length, DW_GMAC_DMA_ALIGN); + rt_hw_cpu_dcache_invalidate((void *)data_start, data_end - data_start); - *packetp = (uint8_t *)((uint64_t)desc_p->dmamac_addr); + *packetp = (uint8_t *)data_start; } return length; @@ -418,8 +450,7 @@ static int32_t designware_free_pkt(eth_mac_handle_t handle) uint32_t desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; uint64_t desc_start = (uint64_t)desc_p; - uint64_t desc_end = desc_start + - roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN); + uint64_t desc_end = desc_start + roundup(sizeof(*desc_p), DW_GMAC_DMA_ALIGN); /* * Make the current descriptor valid again and go to @@ -471,14 +502,15 @@ int32_t dw_eth_mac_phy_read(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t r uint16_t miiaddr; int32_t start; - miiaddr = ((phy_addr << CVI_MIIADDRSHIFT) & CVI_MII_ADDRMSK) | - ((reg_addr << CVI_MIIREGSHIFT) & CVI_MII_REGMSK); + miiaddr = ((phy_addr << CVI_MIIADDRSHIFT) & CVI_MII_ADDRMSK) | ((reg_addr << CVI_MIIREGSHIFT) & CVI_MII_REGMSK); mac_reg->miiaddr = (miiaddr | CVI_MII_CLKRANGE_150_250M | CVI_MII_BUSY); start = rt_tick_get_millisecond(); - while ((rt_tick_get_millisecond() - start) < CVI_CONFIG_MDIO_TIMEOUT) { - if (!(mac_reg->miiaddr & CVI_MII_BUSY)) { + while ((rt_tick_get_millisecond() - start) < CVI_CONFIG_MDIO_TIMEOUT) + { + if (!(mac_reg->miiaddr & CVI_MII_BUSY)) + { *data = mac_reg->miidata; return 0; } @@ -684,14 +716,12 @@ int32_t cvi_eth_mac_read_frame(eth_mac_handle_t handle, uint8_t *frame, uint32_t \param[in] cb callback to handle ethernet event \return return ethernet handle if success */ -eth_mac_handle_t cvi_eth_mac_init(unsigned int *base) +eth_mac_handle_t cvi_eth_mac_init(rt_ubase_t base) { gmac_dev_t *mac_dev = &gmac_instance[0]; struct dw_gmac_priv *priv, *priv_unalign; - mac_dev->base = (unsigned long)base; - // mac_dev->irq = (uint8_t)DW_MAC_IRQ; - // mac_dev->cb_event = cb_event; + mac_dev->base = base; priv = memalign(DW_GMAC_DMA_ALIGN, sizeof(struct dw_gmac_priv), (void **)&priv_unalign); if (!priv) diff --git a/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.h b/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.h index 275159ea9f..2f361ea78b 100644 --- a/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.h +++ b/bsp/cvitek/drivers/libraries/eth/dw_eth_mac.h @@ -37,23 +37,20 @@ typedef void *eth_mac_handle_t; #define DRV_ETH_MAC_ADJUST_LINK (0x07) ///< Adjust MAC link state according to phy state; arg: phy handle #define DRV_ETH_MAC_CONTROL_IRQ (0x08) ///< Interrupt request; arg: 0=disable, 1=enable -#define DW_GMAC_DMA_ALIGN 128 +#define DW_GMAC_DMA_ALIGN 128 #ifndef _DW_ETH_H #define _DW_ETH_H -#define GMAC_NULL_PARAM_CHK(para) CSI_PARAM_CHK(para, -1) -#define GMAC_NULL_PARAM_CHK_NORETVAL(para) CSI_PARAM_CHK_NORETVAL(para) - -#define CVI_CONFIG_SYS_HZ 1000 -#define CVI_CONFIG_TX_DESCR_NUM 16 -#define CVI_CONFIG_RX_DESCR_NUM 16 -#define CVI_CONFIG_ETH_BUFSIZE 2048 -#define CVI_TX_TOTAL_BUFSIZE (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_TX_DESCR_NUM) -#define CVI_RX_TOTAL_BUFSIZE (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_RX_DESCR_NUM) +#define CVI_CONFIG_SYS_HZ 1000 +#define CVI_CONFIG_TX_DESCR_NUM 16 +#define CVI_CONFIG_RX_DESCR_NUM 16 +#define CVI_CONFIG_ETH_BUFSIZE 2048 +#define CVI_TX_TOTAL_BUFSIZE (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_TX_DESCR_NUM) +#define CVI_RX_TOTAL_BUFSIZE (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_RX_DESCR_NUM) #define CVI_CONFIG_MACRESET_TIMEOUT (3 * CVI_CONFIG_SYS_HZ) -#define CVI_CONFIG_MDIO_TIMEOUT (3 * CVI_CONFIG_SYS_HZ) +#define CVI_CONFIG_MDIO_TIMEOUT (3 * CVI_CONFIG_SYS_HZ) struct dw_gmac_mac_regs { volatile uint32_t conf; /* 0x00 */ @@ -97,7 +94,8 @@ struct dw_gmac_mac_regs { #define CVI_MII_ADDRMSK (0x1F << 11) typedef uint32_t reg_type; -struct dw_gmac_dma_regs { +struct dw_gmac_dma_regs +{ volatile reg_type busmode; /* 0x00 */ volatile reg_type txpolldemand; /* 0x04 */ volatile reg_type rxpolldemand; /* 0x08 */ @@ -118,10 +116,10 @@ struct dw_gmac_dma_regs { }; /* Operation mode definitions */ -#define CVI_RXSTART (1 << 1) +#define CVI_RXSTART (1 << 1) #define CVI_TXSECONDFRAME (1 << 2) -#define CVI_TXSTART (1 << 13) -#define CVI_FLUSHTXFIFO (1 << 20) +#define CVI_TXSTART (1 << 13) +#define CVI_FLUSHTXFIFO (1 << 20) #define CVI_STOREFORWARD (1 << 21) #define CVI_DW_DMA_BASE_OFFSET (0x1000) @@ -152,7 +150,8 @@ struct dw_gmac_dma_regs { /* Descriptior related definitions */ #define CVI_MAC_MAX_FRAME_SZ (1600) -struct dmamacdescr { +struct dmamacdescr +{ unsigned int txrx_status; unsigned int dmamac_cntl; unsigned int dmamac_addr; @@ -166,46 +165,46 @@ struct dmamacdescr { /* tx status bits definitions */ #if defined(CONFIG_DW_ALTDESCRIPTOR) -#define CVI_DESC_TXSTS_OWNBYDMA (1 << 31) -#define CVI_DESC_TXSTS_TXINT (1 << 30) -#define CVI_DESC_TXSTS_TXLAST (1 << 29) -#define CVI_DESC_TXSTS_TXFIRST (1 << 28) -#define CVI_DESC_TXSTS_TXCRCDIS (1 << 27) +#define CVI_DESC_TXSTS_OWNBYDMA (1 << 31) +#define CVI_DESC_TXSTS_TXINT (1 << 30) +#define CVI_DESC_TXSTS_TXLAST (1 << 29) +#define CVI_DESC_TXSTS_TXFIRST (1 << 28) +#define CVI_DESC_TXSTS_TXCRCDIS (1 << 27) -#define CVI_DESC_TXSTS_TXPADDIS (1 << 26) +#define CVI_DESC_TXSTS_TXPADDIS (1 << 26) #define CVI_DESC_TXSTS_TXCHECKINSCTRL (3 << 22) #define CVI_DESC_TXSTS_TXRINGEND (1 << 21) -#define CVI_DESC_TXSTS_TXCHAIN (1 << 20) -#define CVI_DESC_TXSTS_MSK (0x1FFFF << 0) +#define CVI_DESC_TXSTS_TXCHAIN (1 << 20) +#define CVI_DESC_TXSTS_MSK (0x1FFFF << 0) #else -#define CVI_DESC_TXSTS_OWNBYDMA (1 << 31) -#define CVI_DESC_TXSTS_MSK (0x1FFFF << 0) +#define CVI_DESC_TXSTS_OWNBYDMA (1 << 31) +#define CVI_DESC_TXSTS_MSK (0x1FFFF << 0) #endif /* rx status bits definitions */ -#define CVI_DESC_RXSTS_OWNBYDMA (1 << 31) +#define CVI_DESC_RXSTS_OWNBYDMA (1 << 31) #define CVI_DESC_RXSTS_DAFILTERFAIL (1 << 30) #define CVI_DESC_RXSTS_FRMLENMSK (0x3FFF << 16) #define CVI_DESC_RXSTS_FRMLENSHFT (16) -#define CVI_DESC_RXSTS_ERROR (1 << 15) +#define CVI_DESC_RXSTS_ERROR (1 << 15) #define CVI_DESC_RXSTS_RXTRUNCATED (1 << 14) #define CVI_DESC_RXSTS_SAFILTERFAIL (1 << 13) #define CVI_DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) #define CVI_DESC_RXSTS_RXDAMAGED (1 << 11) #define CVI_DESC_RXSTS_RXVLANTAG (1 << 10) -#define CVI_DESC_RXSTS_RXFIRST (1 << 9) -#define CVI_DESC_RXSTS_RXLAST (1 << 8) +#define CVI_DESC_RXSTS_RXFIRST (1 << 9) +#define CVI_DESC_RXSTS_RXLAST (1 << 8) #define CVI_DESC_RXSTS_RXIPC_GIANT (1 << 7) #define CVI_DESC_RXSTS_RXCOLLISION (1 << 6) #define CVI_DESC_RXSTS_RXFRAMEETHER (1 << 5) #define CVI_DESC_RXSTS_RXWATCHDOG (1 << 4) #define CVI_DESC_RXSTS_RXMIIERROR (1 << 3) #define CVI_DESC_RXSTS_RXDRIBBLING (1 << 2) -#define CVI_DESC_RXSTS_RXCRC (1 << 1) +#define CVI_DESC_RXSTS_RXCRC (1 << 1) /* * dmamac_cntl definitions @@ -221,13 +220,13 @@ struct dmamacdescr { #else -#define CVI_DESC_TXCTRL_TXINT (1 << 31) -#define CVI_DESC_TXCTRL_TXLAST (1 << 30) -#define CVI_DESC_TXCTRL_TXFIRST (1 << 29) +#define CVI_DESC_TXCTRL_TXINT (1 << 31) +#define CVI_DESC_TXCTRL_TXLAST (1 << 30) +#define CVI_DESC_TXCTRL_TXFIRST (1 << 29) #define CVI_DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) #define CVI_DESC_TXCTRL_TXCRCDIS (1 << 26) #define CVI_DESC_TXCTRL_TXRINGEND (1 << 25) -#define CVI_DESC_TXCTRL_TXCHAIN (1 << 24) +#define CVI_DESC_TXCTRL_TXCHAIN (1 << 24) #define CVI_DESC_TXCTRL_SIZE1MASK (0x7FF << 0) #define CVI_DESC_TXCTRL_SIZE1SHFT (0) @@ -241,7 +240,7 @@ struct dmamacdescr { #define CVI_DESC_RXCTRL_RXINTDIS (1 << 31) #define CVI_DESC_RXCTRL_RXRINGEND (1 << 15) -#define CVI_DESC_RXCTRL_RXCHAIN (1 << 14) +#define CVI_DESC_RXCTRL_RXCHAIN (1 << 14) #define CVI_DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) #define CVI_DESC_RXCTRL_SIZE1SHFT (0) @@ -252,7 +251,7 @@ struct dmamacdescr { #define CVI_DESC_RXCTRL_RXINTDIS (1 << 31) #define CVI_DESC_RXCTRL_RXRINGEND (1 << 25) -#define CVI_DESC_RXCTRL_RXCHAIN (1 << 24) +#define CVI_DESC_RXCTRL_RXCHAIN (1 << 24) #define CVI_DESC_RXCTRL_SIZE1MASK (0x7FF << 0) #define CVI_DESC_RXCTRL_SIZE1SHFT (0) @@ -261,7 +260,8 @@ struct dmamacdescr { #endif -struct dw_gmac_priv { +struct dw_gmac_priv +{ struct dmamacdescr tx_mac_descrtable[CVI_CONFIG_TX_DESCR_NUM] __aligned(DW_GMAC_DMA_ALIGN); struct dmamacdescr rx_mac_descrtable[CVI_CONFIG_RX_DESCR_NUM] __aligned(DW_GMAC_DMA_ALIGN); char txbuffs[CVI_TX_TOTAL_BUFSIZE] __aligned(DW_GMAC_DMA_ALIGN); @@ -274,8 +274,6 @@ struct dw_gmac_priv { struct dw_gmac_mac_regs *mac_regs_p; struct dw_gmac_dma_regs *dma_regs_p; - - //struct gpio_desc reset_gpio; }; #ifdef CONFIG_DM_ETH @@ -283,7 +281,8 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev); int designware_eth_probe(struct udevice *dev); extern const struct eth_ops designware_eth_ops; -struct dw_eth_pdata { +struct dw_eth_pdata +{ struct eth_pdata eth_pdata; u32 reset_delays[3]; }; @@ -300,12 +299,11 @@ int designware_eth_write_hwaddr(struct udevice *dev); #endif -typedef struct { - // csi_dev_t dev; +typedef struct +{ eth_phy_dev_t *phy_dev; - unsigned long base; + rt_ubase_t base; uint8_t irq; - // eth_event_cb_t cb_event; uint8_t mac_addr[6]; struct dw_gmac_priv *priv_unalign; struct dw_gmac_priv *priv; @@ -314,7 +312,8 @@ typedef struct { /** \brief Ethernet MAC Address */ -typedef struct eth_mac_addr { +typedef struct eth_mac_addr +{ uint8_t b[6]; ///< MAC Address (6 bytes), MSB first } eth_mac_addr_t; @@ -415,7 +414,7 @@ int32_t cvi_eth_mac_read_frame(eth_mac_handle_t handle, uint8_t *frame, uint32_t \param[in] cb callback to handle ethernet event \return return ethernet handle if success */ -eth_mac_handle_t cvi_eth_mac_init(unsigned int *base); +eth_mac_handle_t cvi_eth_mac_init(rt_ubase_t base); #ifdef __cplusplus } diff --git a/bsp/cvitek/drivers/libraries/eth/eth_phy_cvitek.c b/bsp/cvitek/drivers/libraries/eth/eth_phy_cvitek.c index 0d6383b006..898eab808f 100644 --- a/bsp/cvitek/drivers/libraries/eth/eth_phy_cvitek.c +++ b/bsp/cvitek/drivers/libraries/eth/eth_phy_cvitek.c @@ -20,6 +20,7 @@ #include "cvi_eth_phy.h" #include "mii.h" +#include "drv_pinmux.h" // #define CVI_ETH_PHY_LOOPBACK #define LOOPBACK_XMII2MAC 0x8000 @@ -27,10 +28,11 @@ #define LOOPBACK_PMA2MAC 0x1000 #define LOOPBACK_RMII2PHY 0x0080 -#define EPHY_EFUSE_VALID_BIT_BASE 0x03050120 -#define EPHY_EFUSE_TXECHORC_FLAG 0x00000100 // bit 8 -#define EPHY_EFUSE_TXITUNE_FLAG 0x00000200 // bit 9 -#define EPHY_EFUSE_TXRXTERM_FLAG 0x00000800 // bit 11 +#define CVITEK_EFUSE_BASE (uintptr_t)DRV_IOREMAP((void *)0x03050000, 0x2000) +#define EPHY_EFUSE_VALID_BIT_BASE (CVITEK_EFUSE_BASE + 0x120) +#define EPHY_EFUSE_TXECHORC_FLAG 0x00000100 // bit 8 +#define EPHY_EFUSE_TXITUNE_FLAG 0x00000200 // bit 9 +#define EPHY_EFUSE_TXRXTERM_FLAG 0x00000800 // bit 11 static inline bool phy_if_mode_is_rgmii(phy_if_mode_t interface) { @@ -59,236 +61,242 @@ int32_t cv181x_config(eth_phy_handle_t handle) // eth_phy_reset(dev); // set rg_ephy_apb_rw_sel 0x0804@[0]=1/APB by using APB interface - mmio_write_32(0x03009804, 0x0001); + mmio_write_32(ETH_PHY_BASE + 0x804, 0x0001); // Release 0x0800[0]=0/shutdown - // mmio_write_32(0x03009800, 0x0900); + // mmio_write_32(ETH_PHY_BASE + 0x800, 0x0900); // Release 0x0800[2]=1/dig_rst_n, Let mii_reg can be accessabile - // mmio_write_32(0x03009800, 0x0904); + // mmio_write_32(ETH_PHY_BASE + 0x800, 0x0904); //mdelay(10); // ANA INIT (PD/EN), switch to MII-page5 - mmio_write_32(0x0300907c, 0x0500); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500); + // Release ANA_PD p5.0x10@[13:8] = 6'b001100 - mmio_write_32(0x03009040, 0x0c00); + mmio_write_32(ETH_PHY_BASE + 0x040, 0x0c00); + // Release ANA_EN p5.0x10@[7:0] = 8'b01111110 - mmio_write_32(0x03009040, 0x0c7e); + mmio_write_32(ETH_PHY_BASE + 0x040, 0x0c7e); // Wait PLL_Lock, Lock_Status p5.0x12@[15] = 1 //mdelay(1); // Release 0x0800[1] = 1/ana_rst_n - mmio_write_32(0x03009800, 0x0906); + mmio_write_32(ETH_PHY_BASE + 0x800, 0x0906); // ANA INIT // @Switch to MII-page5 - mmio_write_32(0x0300907c, 0x0500); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500); // Efuse register // Set Double Bias Current //Set rg_eth_txitune1 0x03009064 [15:8] //Set rg_eth_txitune0 0x03009064 [7:0] - if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXITUNE_FLAG) == - EPHY_EFUSE_TXITUNE_FLAG) { - val = ((mmio_read_32(0x03051024) >> 24) & 0xFF) | - (((mmio_read_32(0x03051024) >> 16) & 0xFF) << 8); - mmio_clrsetbits_32(0x03009064, 0xFFFF, val); - } else - mmio_write_32(0x03009064, 0x5a5a); + if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXITUNE_FLAG) == EPHY_EFUSE_TXITUNE_FLAG) + { + val = ((mmio_read_32(CVITEK_EFUSE_BASE + 0x1024) >> 24) & 0xFF) | (((mmio_read_32(CVITEK_EFUSE_BASE + 0x1024) >> 16) & 0xFF) << 8); + mmio_clrsetbits_32(ETH_PHY_BASE + 0x064, 0xFFFF, val); + } + else + mmio_write_32(ETH_PHY_BASE + 0x064, 0x5a5a); // Set Echo_I // Set rg_eth_txechoiadj 0x03009054 [15:8] - if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXECHORC_FLAG) == - EPHY_EFUSE_TXECHORC_FLAG) { - mmio_clrsetbits_32(0x03009054, 0xFF00, ((mmio_read_32(0x03051024) >> 8) & 0xFF) << 8); - } else - mmio_write_32(0x03009054, 0x0000); + if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXECHORC_FLAG) == EPHY_EFUSE_TXECHORC_FLAG) + { + mmio_clrsetbits_32(ETH_PHY_BASE + 0x054, 0xFF00, ((mmio_read_32(CVITEK_EFUSE_BASE + 0x1024) >> 8) & 0xFF) << 8); + } + else + mmio_write_32(ETH_PHY_BASE + 0x054, 0x0000); //Set TX_Rterm & Echo_RC_Delay // Set rg_eth_txrterm_p1 0x03009058 [11:8] // Set rg_eth_txrterm 0x03009058 [7:4] // Set rg_eth_txechorcadj 0x03009058 [3:0] - if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXRXTERM_FLAG) == - EPHY_EFUSE_TXRXTERM_FLAG) { - val = (((mmio_read_32(0x03051020) >> 28) & 0xF) << 4) | - (((mmio_read_32(0x03051020) >> 24) & 0xF) << 8); - mmio_clrsetbits_32(0x03009058, 0xFF0, val); - } else - mmio_write_32(0x03009058, 0x0bb0); + if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXRXTERM_FLAG) == EPHY_EFUSE_TXRXTERM_FLAG) + { + val = (((mmio_read_32(CVITEK_EFUSE_BASE + 0x1020) >> 28) & 0xF) << 4) | (((mmio_read_32(CVITEK_EFUSE_BASE + 0x1020) >> 24) & 0xF) << 8); + mmio_clrsetbits_32(ETH_PHY_BASE + 0x058, 0xFF0, val); + } + else + mmio_write_32(ETH_PHY_BASE + 0x058, 0x0bb0); -// ETH_100BaseT + // ETH_100BaseT // Set Rise update - mmio_write_32(0x0300905c, 0x0c10); + mmio_write_32(ETH_PHY_BASE + 0x05c, 0x0c10); // Set Falling phase - mmio_write_32(0x03009068, 0x0003); + mmio_write_32(ETH_PHY_BASE + 0x068, 0x0003); // Set Double TX Bias Current - mmio_write_32(0x03009054, 0x0000); + mmio_write_32(ETH_PHY_BASE + 0x054, 0x0000); // Switch to MII-page16 - mmio_write_32(0x0300907c, 0x1000); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1000); // Set MLT3 Positive phase code, Set MLT3 +0 - mmio_write_32(0x03009068, 0x1000); - mmio_write_32(0x0300906c, 0x3020); - mmio_write_32(0x03009070, 0x5040); - mmio_write_32(0x03009074, 0x7060); + mmio_write_32(ETH_PHY_BASE + 0x068, 0x1000); + mmio_write_32(ETH_PHY_BASE + 0x06c, 0x3020); + mmio_write_32(ETH_PHY_BASE + 0x070, 0x5040); + mmio_write_32(ETH_PHY_BASE + 0x074, 0x7060); // Set MLT3 +I - mmio_write_32(0x03009058, 0x1708); - mmio_write_32(0x0300905c, 0x3827); - mmio_write_32(0x03009060, 0x5748); - mmio_write_32(0x03009064, 0x7867); + mmio_write_32(ETH_PHY_BASE + 0x058, 0x1708); + mmio_write_32(ETH_PHY_BASE + 0x05c, 0x3827); + mmio_write_32(ETH_PHY_BASE + 0x060, 0x5748); + mmio_write_32(ETH_PHY_BASE + 0x064, 0x7867); // Switch to MII-page17 - mmio_write_32(0x0300907c, 0x1100); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1100); // Set MLT3 Negative phase code, Set MLT3 -0 - mmio_write_32(0x03009040, 0x9080); - mmio_write_32(0x03009044, 0xb0a0); - mmio_write_32(0x03009048, 0xd0c0); - mmio_write_32(0x0300904c, 0xf0e0); + mmio_write_32(ETH_PHY_BASE + 0x040, 0x9080); + mmio_write_32(ETH_PHY_BASE + 0x044, 0xb0a0); + mmio_write_32(ETH_PHY_BASE + 0x048, 0xd0c0); + mmio_write_32(ETH_PHY_BASE + 0x04c, 0xf0e0); // Set MLT3 -I - mmio_write_32(0x03009050, 0x9788); - mmio_write_32(0x03009054, 0xb8a7); - mmio_write_32(0x03009058, 0xd7c8); - mmio_write_32(0x0300905c, 0xf8e7); + mmio_write_32(ETH_PHY_BASE + 0x050, 0x9788); + mmio_write_32(ETH_PHY_BASE + 0x054, 0xb8a7); + mmio_write_32(ETH_PHY_BASE + 0x058, 0xd7c8); + mmio_write_32(ETH_PHY_BASE + 0x05c, 0xf8e7); // @Switch to MII-page5 - mmio_write_32(0x0300907c, 0x0500); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500); // En TX_Rterm - mmio_write_32(0x03009040, (0x0001 | mmio_read_32(0x03009040))); + mmio_write_32(ETH_PHY_BASE + 0x040, (0x0001 | mmio_read_32(ETH_PHY_BASE + 0x040))); // Link Pulse // Switch to MII-page10 - mmio_write_32(0x0300907c, 0x0a00); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0a00); // Set Link Pulse - mmio_write_32(0x03009040, 0x2000); - mmio_write_32(0x03009044, 0x3832); - mmio_write_32(0x03009048, 0x3132); - mmio_write_32(0x0300904c, 0x2d2f); - mmio_write_32(0x03009050, 0x2c2d); - mmio_write_32(0x03009054, 0x1b2b); - mmio_write_32(0x03009058, 0x94a0); - mmio_write_32(0x0300905c, 0x8990); - mmio_write_32(0x03009060, 0x8788); - mmio_write_32(0x03009064, 0x8485); - mmio_write_32(0x03009068, 0x8283); - mmio_write_32(0x0300906c, 0x8182); - mmio_write_32(0x03009070, 0x0081); + mmio_write_32(ETH_PHY_BASE + 0x040, 0x2000); + mmio_write_32(ETH_PHY_BASE + 0x044, 0x3832); + mmio_write_32(ETH_PHY_BASE + 0x048, 0x3132); + mmio_write_32(ETH_PHY_BASE + 0x04c, 0x2d2f); + mmio_write_32(ETH_PHY_BASE + 0x050, 0x2c2d); + mmio_write_32(ETH_PHY_BASE + 0x054, 0x1b2b); + mmio_write_32(ETH_PHY_BASE + 0x058, 0x94a0); + mmio_write_32(ETH_PHY_BASE + 0x05c, 0x8990); + mmio_write_32(ETH_PHY_BASE + 0x060, 0x8788); + mmio_write_32(ETH_PHY_BASE + 0x064, 0x8485); + mmio_write_32(ETH_PHY_BASE + 0x068, 0x8283); + mmio_write_32(ETH_PHY_BASE + 0x06c, 0x8182); + mmio_write_32(ETH_PHY_BASE + 0x070, 0x0081); // TP_IDLE // Switch to MII-page11 - mmio_write_32(0x0300907c, 0x0b00); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0b00); // Set TP_IDLE - mmio_write_32(0x03009040, 0x5252); - mmio_write_32(0x03009044, 0x5252); - mmio_write_32(0x03009048, 0x4B52); - mmio_write_32(0x0300904c, 0x3D47); - mmio_write_32(0x03009050, 0xAA99); - mmio_write_32(0x03009054, 0x989E); - mmio_write_32(0x03009058, 0x9395); - mmio_write_32(0x0300905C, 0x9091); - mmio_write_32(0x03009060, 0x8E8F); - mmio_write_32(0x03009064, 0x8D8E); - mmio_write_32(0x03009068, 0x8C8C); - mmio_write_32(0x0300906C, 0x8B8B); - mmio_write_32(0x03009070, 0x008A); + mmio_write_32(ETH_PHY_BASE + 0x040, 0x5252); + mmio_write_32(ETH_PHY_BASE + 0x044, 0x5252); + mmio_write_32(ETH_PHY_BASE + 0x048, 0x4B52); + mmio_write_32(ETH_PHY_BASE + 0x04c, 0x3D47); + mmio_write_32(ETH_PHY_BASE + 0x050, 0xAA99); + mmio_write_32(ETH_PHY_BASE + 0x054, 0x989E); + mmio_write_32(ETH_PHY_BASE + 0x058, 0x9395); + mmio_write_32(ETH_PHY_BASE + 0x05C, 0x9091); + mmio_write_32(ETH_PHY_BASE + 0x060, 0x8E8F); + mmio_write_32(ETH_PHY_BASE + 0x064, 0x8D8E); + mmio_write_32(ETH_PHY_BASE + 0x068, 0x8C8C); + mmio_write_32(ETH_PHY_BASE + 0x06C, 0x8B8B); + mmio_write_32(ETH_PHY_BASE + 0x070, 0x008A); // ETH 10BaseT Data // Switch to MII-page13 - mmio_write_32(0x0300907c, 0x0d00); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0d00); - mmio_write_32(0x03009040, 0x1E0A); - mmio_write_32(0x03009044, 0x3862); - mmio_write_32(0x03009048, 0x1E62); - mmio_write_32(0x0300904c, 0x2A08); - mmio_write_32(0x03009050, 0x244C); - mmio_write_32(0x03009054, 0x1A44); - mmio_write_32(0x03009058, 0x061C); + mmio_write_32(ETH_PHY_BASE + 0x040, 0x1E0A); + mmio_write_32(ETH_PHY_BASE + 0x044, 0x3862); + mmio_write_32(ETH_PHY_BASE + 0x048, 0x1E62); + mmio_write_32(ETH_PHY_BASE + 0x04c, 0x2A08); + mmio_write_32(ETH_PHY_BASE + 0x050, 0x244C); + mmio_write_32(ETH_PHY_BASE + 0x054, 0x1A44); + mmio_write_32(ETH_PHY_BASE + 0x058, 0x061C); // Switch to MII-page14 - mmio_write_32(0x0300907c, 0x0e00); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0e00); - mmio_write_32(0x03009040, 0x2D30); - mmio_write_32(0x03009044, 0x3470); - mmio_write_32(0x03009048, 0x0648); - mmio_write_32(0x0300904c, 0x261C); - mmio_write_32(0x03009050, 0x3160); - mmio_write_32(0x03009054, 0x2D5E); + mmio_write_32(ETH_PHY_BASE + 0x040, 0x2D30); + mmio_write_32(ETH_PHY_BASE + 0x044, 0x3470); + mmio_write_32(ETH_PHY_BASE + 0x048, 0x0648); + mmio_write_32(ETH_PHY_BASE + 0x04c, 0x261C); + mmio_write_32(ETH_PHY_BASE + 0x050, 0x3160); + mmio_write_32(ETH_PHY_BASE + 0x054, 0x2D5E); // Switch to MII-page15 - mmio_write_32(0x0300907c, 0x0f00); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0f00); - mmio_write_32(0x03009040, 0x2922); - mmio_write_32(0x03009044, 0x366E); - mmio_write_32(0x03009048, 0x0752); - mmio_write_32(0x0300904c, 0x2556); - mmio_write_32(0x03009050, 0x2348); - mmio_write_32(0x03009054, 0x0C30); + mmio_write_32(ETH_PHY_BASE + 0x040, 0x2922); + mmio_write_32(ETH_PHY_BASE + 0x044, 0x366E); + mmio_write_32(ETH_PHY_BASE + 0x048, 0x0752); + mmio_write_32(ETH_PHY_BASE + 0x04c, 0x2556); + mmio_write_32(ETH_PHY_BASE + 0x050, 0x2348); + mmio_write_32(ETH_PHY_BASE + 0x054, 0x0C30); // Switch to MII-page16 - mmio_write_32(0x0300907c, 0x1000); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1000); - mmio_write_32(0x03009040, 0x1E08); - mmio_write_32(0x03009044, 0x3868); - mmio_write_32(0x03009048, 0x1462); - mmio_write_32(0x0300904c, 0x1A0E); - mmio_write_32(0x03009050, 0x305E); - mmio_write_32(0x03009054, 0x2F62); + mmio_write_32(ETH_PHY_BASE + 0x040, 0x1E08); + mmio_write_32(ETH_PHY_BASE + 0x044, 0x3868); + mmio_write_32(ETH_PHY_BASE + 0x048, 0x1462); + mmio_write_32(ETH_PHY_BASE + 0x04c, 0x1A0E); + mmio_write_32(ETH_PHY_BASE + 0x050, 0x305E); + mmio_write_32(ETH_PHY_BASE + 0x054, 0x2F62); // LED PAD MUX - mmio_write_32(0x030010e0, 0x05); - mmio_write_32(0x030010e4, 0x05); + uintptr_t addr = (uintptr_t)DRV_IOREMAP((void *)0x03001000, 0x1000); + mmio_write_32((uintptr_t)(addr + 0xe0), 0x05); + mmio_write_32((uintptr_t)(addr + 0xe4), 0x05); + //(SD1_CLK selphy) - mmio_write_32(0x050270b0, 0x11111111); + addr = (uintptr_t)DRV_IOREMAP((void *)0x05027000, 0x1000); + mmio_write_32((intptr_t)(addr + 0xb0), 0x11111111); //(SD1_CMD selphy) - mmio_write_32(0x050270b4, 0x11111111); + mmio_write_32((intptr_t)(addr + 0xb4), 0x11111111); // LED // Switch to MII-page1 - mmio_write_32(0x0300907c, 0x0100); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0100); // select LED_LNK/SPD/DPX out to LED_PAD - mmio_write_32(0x03009068, (mmio_read_32(0x03009068) & ~0x0f00)); + mmio_write_32(ETH_PHY_BASE + 0x068, (mmio_read_32(ETH_PHY_BASE + 0x068) & ~0x0f00)); // @Switch to MII-page0 - mmio_write_32(0x0300907c, 0x0000); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0000); // PHY_ID - mmio_write_32(0x03009008, 0x0043); - mmio_write_32(0x0300900c, 0x5649); + mmio_write_32(ETH_PHY_BASE + 0x008, 0x0043); + mmio_write_32(ETH_PHY_BASE + 0x00c, 0x5649); // Switch to MII-page19 - mmio_write_32(0x0300907c, 0x1300); - mmio_write_32(0x03009058, 0x0012); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1300); + mmio_write_32(ETH_PHY_BASE + 0x058, 0x0012); // set agc max/min swing - mmio_write_32(0x0300905C, 0x6848); + mmio_write_32(ETH_PHY_BASE + 0x05C, 0x6848); // Switch to MII-page18 - mmio_write_32(0x0300907c, 0x1200); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1200); // p18.0x12, lpf - mmio_write_32(0x03009048, 0x0808); - mmio_write_32(0x0300904C, 0x0808); + mmio_write_32(ETH_PHY_BASE + 0x048, 0x0808); + mmio_write_32(ETH_PHY_BASE + 0x04C, 0x0808); // hpf //sean - mmio_write_32(0x03009050, 0x32f8); - mmio_write_32(0x03009054, 0xf8dc); + mmio_write_32(ETH_PHY_BASE + 0x050, 0x32f8); + mmio_write_32(ETH_PHY_BASE + 0x054, 0xf8dc); // Switch to MII-page0 - mmio_write_32(0x0300907c, 0x0000); + mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0000); // EPHY start auto-neg procedure - mmio_write_32(0x03009800, 0x090e); + mmio_write_32(ETH_PHY_BASE + 0x800, 0x090e); // switch to MDIO control by ETH_MAC - mmio_write_32(0x03009804, 0x0000); + mmio_write_32(ETH_PHY_BASE + 0x804, 0x0000); genphy_config(dev); diff --git a/bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h b/bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h index 157888c07e..702c82dbdc 100644 --- a/bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h +++ b/bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h @@ -8,6 +8,7 @@ #include #include #include +#include "drv_ioremap.h" #define TOP_BASE 0x03000000 #define DW_SDIO0_BASE 0x04320000 @@ -58,9 +59,9 @@ static inline int mmc_op_multi(uint32_t opcode) #define SDIO0_IRQ 36 #define SDIO1_IRQ 38 #define SDIO2_IRQ 34 -#define SDIO0_BASE DW_SDIO1_BASE -#define SDIO1_BASE DW_SDIO0_BASE -#define SDIO2_BASE DW_SDIO2_BASE +#define SDIO0_BASE DRV_IOREMAP((void *)DW_SDIO1_BASE, 0x1000) +#define SDIO1_BASE DRV_IOREMAP((void *)DW_SDIO0_BASE, 0x1000) +#define SDIO2_BASE DRV_IOREMAP((void *)DW_SDIO2_BASE, 0x1000) #define SDIF_DMA_ADDRESS 0x00 #define SDIF_BLOCK_SIZE 0x04 @@ -271,7 +272,7 @@ static inline int mmc_op_multi(uint32_t opcode) #define REG_SDIO0_DAT3_PIO_VALUE (0x0) /*SDIO 1 register and bit flag*/ -#define RTCIO_BASE (0x5027000) +#define RTCIO_BASE (uintptr_t)DRV_IOREMAP((void *)0x5027000, 0x1000) #define REG_SDIO1_PAD_MASK (0xFFFFFFF3) #define REG_SDIO1_PAD_SHIFT (2) @@ -311,13 +312,13 @@ static inline int mmc_op_multi(uint32_t opcode) #define REG_SDIO1_DAT3_PIO_REG (PINMUX_BASE + 0xD0) #define REG_SDIO1_DAT3_PIO_VALUE (0x0) -#define RTC_CTRL_BASE 0x5025000 +#define RTC_CTRL_BASE (uintptr_t)DRV_IOREMAP((void *)0x5025000, 0x1000) #define RTCSYS_CLKMUX (RTC_CTRL_BASE + 0x1C) #define RTCSYS_CLKBYP (RTC_CTRL_BASE + 0x30) #define RTCSYS_MCU51_ICTRL1 (RTC_CTRL_BASE + 0x7C) -#define RTCSYS_CTRL_BASE 0x03000000 -#define RTCSYS_CTRL (RTCSYS_CTRL_BASE + 0x248) +#define RTCSYS_CTRL_BASE (uintptr_t)DRV_IOREMAP((void *)0x03000000, 0x1000) +#define RTCSYS_CTRL (RTCSYS_CTRL_BASE + 0x248) /*SDIO 2 register and bit flag*/ #define REG_SDIO2_PAD_MASK (0xFFFFFFF3) @@ -365,10 +366,10 @@ static inline int mmc_op_multi(uint32_t opcode) #define REG_SDIO2_DAT3_PIO_REG (PINMUX_BASE + 0x58) #define REG_SDIO2_DAT3_PIO_VALUE (0x0) - -#define MMC_SDIO0_PLL_REGISTER 0x3002070 -#define MMC_SDIO1_PLL_REGISTER 0x300207C -#define MMC_SDIO2_PLL_REGISTER 0x3002064 +#define CLK_DIV_BASE (uintptr_t)DRV_IOREMAP((void *)0x3002000, 0x1000) +#define MMC_SDIO0_PLL_REGISTER (CLK_DIV_BASE + 0x70) +#define MMC_SDIO1_PLL_REGISTER (CLK_DIV_BASE + 0x7C) +#define MMC_SDIO2_PLL_REGISTER (CLK_DIV_BASE + 0x64) #define MMC_MAX_CLOCK_DIV_VALUE (0x40009) #define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)