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[bsp][gd32303e-eval]add gcc support

This commit is contained in:
luo jiao 2018-05-23 23:18:02 +08:00
parent da6f9e2dc0
commit 8d0328c784
16 changed files with 3346 additions and 234 deletions
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271
bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S Normal file
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@ -0,0 +1,271 @@
;/*
; * File : startup_gd32f30x_hd.s
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
; *
; * This program is free software; you can redistribute it and/or modify
; * it under the terms of the GNU General Public License as published by
; * the Free Software Foundation; either version 2 of the License, or
; * (at your option) any later version.
; *
; * This program is distributed in the hope that it will be useful,
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; * GNU General Public License for more details.
; *
; * You should have received a copy of the GNU General Public License along
; * with this program; if not, write to the Free Software Foundation, Inc.,
; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
; *
; * Change Logs:
; * Date Author Notes
; * 2018-05-22 tanek first implementation
; */
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
// external interrupts handler
.word WWDGT_IRQHandler // 16:Window Watchdog Timer
.word LVD_IRQHandler // 17:LVD through EXTI Line detect
.word TAMPER_IRQHandler // 18:Tamper through EXTI Line detect
.word RTC_IRQHandler // 19:RTC through EXTI Line
.word FMC_IRQHandler // 20:FMC
.word RCU_CTC_IRQHandler // 21:RCU and CTC
.word EXTI0_IRQHandler // 22:EXTI Line 0
.word EXTI1_IRQHandler // 23:EXTI Line 1
.word EXTI2_IRQHandler // 24:EXTI Line 2
.word EXTI3_IRQHandler // 25:EXTI Line 3
.word EXTI4_IRQHandler // 26:EXTI Line 4
.word DMA0_Channel0_IRQHandler // 27:DMA0 Channel0
.word DMA0_Channel1_IRQHandler // 28:DMA0 Channel1
.word DMA0_Channel2_IRQHandler // 29:DMA0 Channel2
.word DMA0_Channel3_IRQHandler // 30:DMA0 Channel3
.word DMA0_Channel4_IRQHandler // 31:DMA0 Channel4
.word DMA0_Channel5_IRQHandler // 32:DMA0 Channel5
.word DMA0_Channel6_IRQHandler // 33:DMA0 Channel6
.word ADC0_1_IRQHandler // 34:ADC0 and ADC1
.word USBD_HP_CAN0_TX_IRQHandler // 35:USBD HP and CAN0 TX
.word USBD_LP_CAN0_RX0_IRQHandler // 36:USBD LP and CAN0 RX0
.word CAN0_RX1_IRQHandler // 37:CAN0 RX1
.word CAN0_EWMC_IRQHandler // 38:CAN0 EWMC
.word EXTI5_9_IRQHandler // 39:EXTI5 to EXTI9
.word TIMER0_BRK_IRQHandler // 40:TIMER0 Break
.word TIMER0_UP_IRQHandler // 41:TIMER0 Update
.word TIMER0_TRG_CMT_IRQHandler // 42:TIMER0 Trigger and Commutation
.word TIMER0_Channel_IRQHandler // 43:TIMER0 Channel Capture Compare
.word TIMER1_IRQHandler // 44:TIMER1
.word TIMER2_IRQHandler // 45:TIMER2
.word TIMER3_IRQHandler // 46:TIMER3
.word I2C0_EV_IRQHandler // 47:I2C0 Event
.word I2C0_ER_IRQHandler // 48:I2C0 Error
.word I2C1_EV_IRQHandler // 49:I2C1 Event
.word I2C1_ER_IRQHandler // 50:I2C1 Error
.word SPI0_IRQHandler // 51:SPI0
.word SPI1_IRQHandler // 52:SPI1
.word USART0_IRQHandler // 53:USART0
.word USART1_IRQHandler // 54:USART1
.word USART2_IRQHandler // 55:USART2
.word EXTI10_15_IRQHandler // 56:EXTI10 to EXTI15
.word RTC_Alarm_IRQHandler // 57:RTC Alarm
.word USBD_WKUP_IRQHandler // 58:USBD Wakeup
.word TIMER7_BRK_IRQHandler // 59:TIMER7 Break
.word TIMER7_UP_IRQHandler // 60:TIMER7 Update
.word TIMER7_TRG_CMT_IRQHandler // 61:TIMER7 Trigger and Commutation
.word TIMER7_Channel_IRQHandler // 62:TIMER7 Channel Capture Compare
.word ADC2_IRQHandler // 63:ADC2
.word EXMC_IRQHandler // 64:EXMC
.word SDIO_IRQHandler // 65:SDIO
.word TIMER4_IRQHandler // 66:TIMER4
.word SPI2_IRQHandler // 67:SPI2
.word UART3_IRQHandler // 68:UART3
.word UART4_IRQHandler // 69:UART4
.word TIMER5_IRQHandler // 70:TIMER5
.word TIMER6_IRQHandler // 71:TIMER6
.word DMA1_Channel0_IRQHandler // 72:DMA1 Channel0
.word DMA1_Channel1_IRQHandler // 73:DMA1 Channel1
.word DMA1_Channel2_IRQHandler // 74:DMA1 Channel2
.word DMA1_Channel3_4_IRQHandler // 75:DMA1 Channel3 and Channel4
.size g_pfnVectors, .-g_pfnVectors
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r1, =_sidata
ldr r2, =_sdata
ldr r3, =_edata
subs r3, r2
ble fill_bss_start
loop_copy_data:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt loop_copy_data
fill_bss_start:
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble startup_enter
loop_fill_bss:
subs r2, #4
str r0, [r1, r2]
bgt loop_fill_bss
startup_enter:
bl SystemInit
bl entry
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
b .
.size NMI_Handler, . - NMI_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
b .
.size MemManage_Handler, . - MemManage_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
b .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
b .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
b .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
b .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
b .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
b .
.size SysTick_Handler, . - SysTick_Handler
/* IQR Handler */
.section .text.Default_Handler,"ax",%progbits
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ WWDGT_IRQHandler
IRQ LVD_IRQHandler
IRQ TAMPER_IRQHandler
IRQ RTC_IRQHandler
IRQ FMC_IRQHandler
IRQ RCU_CTC_IRQHandler
IRQ EXTI0_IRQHandler
IRQ EXTI1_IRQHandler
IRQ EXTI2_IRQHandler
IRQ EXTI3_IRQHandler
IRQ EXTI4_IRQHandler
IRQ DMA0_Channel0_IRQHandler
IRQ DMA0_Channel1_IRQHandler
IRQ DMA0_Channel2_IRQHandler
IRQ DMA0_Channel3_IRQHandler
IRQ DMA0_Channel4_IRQHandler
IRQ DMA0_Channel5_IRQHandler
IRQ DMA0_Channel6_IRQHandler
IRQ ADC0_1_IRQHandler
IRQ USBD_HP_CAN0_TX_IRQHandler
IRQ USBD_LP_CAN0_RX0_IRQHandler
IRQ CAN0_RX1_IRQHandler
IRQ CAN0_EWMC_IRQHandler
IRQ EXTI5_9_IRQHandler
IRQ TIMER0_BRK_IRQHandler
IRQ TIMER0_UP_IRQHandler
IRQ TIMER0_TRG_CMT_IRQHandler
IRQ TIMER0_Channel_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ TIMER3_IRQHandler
IRQ I2C0_EV_IRQHandler
IRQ I2C0_ER_IRQHandler
IRQ I2C1_EV_IRQHandler
IRQ I2C1_ER_IRQHandler
IRQ SPI0_IRQHandler
IRQ SPI1_IRQHandler
IRQ USART0_IRQHandler
IRQ USART1_IRQHandler
IRQ USART2_IRQHandler
IRQ EXTI10_15_IRQHandler
IRQ RTC_Alarm_IRQHandler
IRQ USBD_WKUP_IRQHandler
IRQ TIMER7_BRK_IRQHandler
IRQ TIMER7_UP_IRQHandler
IRQ TIMER7_TRG_CMT_IRQHandler
IRQ TIMER7_Channel_IRQHandler
IRQ ADC2_IRQHandler
IRQ EXMC_IRQHandler
IRQ SDIO_IRQHandler
IRQ TIMER4_IRQHandler
IRQ SPI2_IRQHandler
IRQ UART3_IRQHandler
IRQ UART4_IRQHandler
IRQ TIMER5_IRQHandler
IRQ TIMER6_IRQHandler
IRQ DMA1_Channel0_IRQHandler
IRQ DMA1_Channel1_IRQHandler
IRQ DMA1_Channel2_IRQHandler
IRQ DMA1_Channel3_4_IRQHandler

5
bsp/gd32303e-eval/Libraries/SConscript
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@ -11,10 +11,7 @@ src += [cwd + '/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
print('=================================================')
print('Not support gcc yet !')
print('=================================================')
exit(0)
src += [cwd + '/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += [cwd + '/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s']
elif rtconfig.CROSS_TOOL == 'iar':

3
bsp/gd32303e-eval/README.md
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@ -15,12 +15,13 @@
## 2. 编译说明
GD32303E-EVAL板级包支持MDK5和IAR。
GD32303E-EVAL板级包支持MDK5、IAR开发环境和GCC编译器，以下是具体版本信息：
| IDE/编译器 | 已测试版本 |
| -- | -- |
| MDK5 | MDK5.25 |
| IAR | IAR8.20 |
| GCC | GCC 5.4.1 20160919 (release) |
## 3. 烧写及执行

20
bsp/gd32303e-eval/RTE/_rt-thread_gd32f30x/RTE_Components.h Normal file
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@ -0,0 +1,20 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'project'
* Target: 'rt-thread_gd32f30x'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "gd32f30x.h"
#endif /* RTE_COMPONENTS_H */

4
bsp/gd32303e-eval/applications/main.c
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@ -16,9 +16,9 @@
int main(void)
{
/* user app entry */
/* user app entry */
return 0;
return 0;
}

18
bsp/gd32303e-eval/cconfig.h Normal file
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@ -0,0 +1,18 @@
#ifndef CCONFIG_H__
#define CCONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* compiler configure file for RT-Thread in GCC*/
#define HAVE_NEWLIB_H 1
#define LIBC_VERSION "newlib 2.4.0"
#define HAVE_SYS_SIGNAL_H 1
#define HAVE_SYS_SELECT_H 1
#define HAVE_PTHREAD_H 1
#define HAVE_FDSET 1
#define HAVE_SIGACTION 1
#define GCC_VERSION "5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]"
#define STDC "2011"
#endif

23
bsp/gd32303e-eval/drivers/board.c
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@ -23,12 +23,12 @@
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
}
/* USER CODE END Error_Handler */
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while (1)
{
}
/* USER CODE END Error_Handler */
}
/** System Clock Configuration
@ -54,13 +54,12 @@ void SysTick_Handler(void)
rt_interrupt_leave();
}
/**
* This function will initial GD32 board.
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
@ -69,17 +68,17 @@ void rt_hw_board_init()
/* Set the Vector Table base location at 0x08000000 */
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
#endif
SystemClock_Config();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(CONSOLE_DEVICE);
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
#endif

27
bsp/gd32303e-eval/drivers/board.h
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@ -42,33 +42,6 @@ extern int __bss_end;
#define HEAP_END GD32_SRAM_END
// <o> Console on USART:
// <127=> no console
// <0=>USART 0 <1=>USART 1 <2=>USART 2 <3=> USART 3
// <4=>USART 4
// <i>Default: 0
#define GD32_CONSOLE_USART 0
void rt_hw_board_init(void);
#if GD32_CONSOLE_USART == 127
#define CONSOLE_DEVICE "no"
#elif GD32_CONSOLE_USART == 0
#define CONSOLE_DEVICE "uart0"
#elif GD32_CONSOLE_USART == 1
#define CONSOLE_DEVICE "uart1"
#elif GD32_CONSOLE_USART == 2
#define CONSOLE_DEVICE "uart2"
#elif GD32_CONSOLE_USART == 3
#define CONSOLE_DEVICE "uart3"
#elif GD32_CONSOLE_USART == 4
#define CONSOLE_DEVICE "uart4"
#endif
#define FINSH_DEVICE_NAME CONSOLE_DEVICE
void Error_Handler(void);
#endif
//*** <<< end of configuration section >>> ***

4
bsp/gd32303e-eval/drivers/drv_gpio.c
View File

@ -459,7 +459,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
return RT_EINVAL;
}
rcu_periph_clock_enable(RCU_AF);
rcu_periph_clock_enable(RCU_AF);
/* enable and set interrupt priority */
nvic_irq_enable(irqmap->irqno, 5U, 0U);
@ -522,7 +522,7 @@ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line)))
{
pin_irq_hdr(exti_line);
exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
}
}
void EXTI0_IRQHandler(void)

298
bsp/gd32303e-eval/drivers/drv_i2c.c
View File

@ -46,189 +46,189 @@
struct gd32_i2c_bit_data
{
struct
{
rcu_periph_enum clk;
rt_uint32_t port;
rt_uint32_t pin;
}scl, sda;
struct
{
rcu_periph_enum clk;
rt_uint32_t port;
rt_uint32_t pin;
}scl, sda;
};
static void gpio_set_sda(void *data, rt_int32_t state)
{
struct gd32_i2c_bit_data* bd = data;
struct gd32_i2c_bit_data* bd = data;
if (state)
{
gpio_bit_set(bd->sda.port, bd->sda.pin);
}
else
{
gpio_bit_reset(bd->sda.port, bd->sda.pin);
}
if (state)
{
gpio_bit_set(bd->sda.port, bd->sda.pin);
}
else
{
gpio_bit_reset(bd->sda.port, bd->sda.pin);
}
}
static void gpio_set_scl(void *data, rt_int32_t state)
{
struct gd32_i2c_bit_data* bd = data;
if (state)
{
gpio_bit_set(bd->scl.port, bd->scl.pin);
}
else
{
gpio_bit_reset(bd->scl.port, bd->scl.pin);
}
struct gd32_i2c_bit_data* bd = data;
if (state)
{
gpio_bit_set(bd->scl.port, bd->scl.pin);
}
else
{
gpio_bit_reset(bd->scl.port, bd->scl.pin);
}
}
static rt_int32_t gpio_get_sda(void *data)
{
struct gd32_i2c_bit_data* bd = data;
struct gd32_i2c_bit_data* bd = data;
return gpio_input_bit_get(bd->sda.port, bd->sda.pin);
return gpio_input_bit_get(bd->sda.port, bd->sda.pin);
}
static rt_int32_t gpio_get_scl(void *data)
{
struct gd32_i2c_bit_data* bd = data;
struct gd32_i2c_bit_data* bd = data;
return gpio_input_bit_get(bd->scl.port, bd->scl.pin);
return gpio_input_bit_get(bd->scl.port, bd->scl.pin);
}
static void gpio_udelay(rt_uint32_t us)
{
int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us);
while(i)
{
i--;
}
int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us);
while(i)
{
i--;
}
}
static void drv_i2c_gpio_init(const struct gd32_i2c_bit_data* bd)
{
rcu_periph_clock_enable(bd->sda.clk);
rcu_periph_clock_enable(bd->scl.clk);
gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin);
gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin);
rcu_periph_clock_enable(bd->sda.clk);
rcu_periph_clock_enable(bd->scl.clk);
gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin);
gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin);
gpio_bit_set(bd->sda.port, bd->sda.pin);
gpio_bit_set(bd->scl.port, bd->scl.pin);
gpio_bit_set(bd->sda.port, bd->sda.pin);
gpio_bit_set(bd->scl.port, bd->scl.pin);
}
#else /* use hardware i2c */
struct gd32_i2c_bus
{
struct rt_i2c_bus_device parent;
rt_uint32_t i2c_periph;
struct rt_i2c_bus_device parent;
rt_uint32_t i2c_periph;
};
static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte)
{
{
/* wait until I2C bus is idle */
while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY));
/* send a start condition to I2C bus */
i2c_start_on_bus(i2c_periph);
/* wait until SBSEND bit is set */
while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND));
/* send slave address to I2C bus */
i2c_master_addressing(i2c_periph, slave_address<<1, I2C_RECEIVER);
/* wait until ADDSEND bit is set */
while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND));
/* clear the ADDSEND bit */
i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND);
if(1 == data_byte){
/* disable acknowledge */
i2c_ack_config(i2c_periph,I2C_ACK_DISABLE);
/* send a stop condition to I2C bus */
i2c_stop_on_bus(i2c_periph);
}
if(1 == data_byte){
/* disable acknowledge */
i2c_ack_config(i2c_periph,I2C_ACK_DISABLE);
/* send a stop condition to I2C bus */
i2c_stop_on_bus(i2c_periph);
}
/* while there is data to be read */
while(data_byte)
{
{
/* wait until the RBNE bit is set and clear it */
if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE))
{
/* read a byte from the EEPROM */
*p_buffer = i2c_data_receive(i2c_periph);
/* point to the next location where the byte read will be saved */
p_buffer++;
/* decrement the read bytes counter */
data_byte--;
if(1 == data_byte)
if(1 == data_byte)
{
/* disable acknowledge */
i2c_ack_config(i2c_periph,I2C_ACK_DISABLE);
/* send a stop condition to I2C bus */
i2c_stop_on_bus(i2c_periph);
}
/* disable acknowledge */
i2c_ack_config(i2c_periph,I2C_ACK_DISABLE);
/* send a stop condition to I2C bus */
i2c_stop_on_bus(i2c_periph);
}
}
}
/* wait until the stop condition is finished */
while(I2C_CTL0(i2c_periph)&0x0200);
/* enable acknowledge */
i2c_ack_config(i2c_periph,I2C_ACK_ENABLE);
i2c_ackpos_config(i2c_periph,I2C_ACKPOS_CURRENT);
return 0;
}
static int gd32_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte)
{
{
/* wait until I2C bus is idle */
while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY));
/* send a start condition to I2C bus */
i2c_start_on_bus(i2c_periph);
/* wait until SBSEND bit is set */
while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND));
/* send slave address to I2C bus */
i2c_master_addressing(i2c_periph, slave_address<<1, I2C_TRANSMITTER);
/* wait until ADDSEND bit is set */
while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND));
/* clear the ADDSEND bit */
i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND);
/* wait until the transmit data buffer is empty */
while(SET != i2c_flag_get( i2c_periph , I2C_FLAG_TBE));
/* while there is data to be read */
while(data_byte)
{
{
i2c_data_transmit(i2c_periph, *p_buffer);
/* point to the next byte to be written */
p_buffer++;
/* decrement the write bytes counter */
data_byte --;
/* decrement the write bytes counter */
data_byte --;
/* wait until BTC bit is set */
while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC));
}
/* send a stop condition to I2C bus */
/* send a stop condition to I2C bus */
i2c_stop_on_bus(i2c_periph);
/* wait until the stop condition is finished */
while(I2C_CTL0(i2c_periph)&0x0200);
return 0;
}
@ -244,14 +244,14 @@ static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg
{
msg = &msgs[i];
if (msg->flags & RT_I2C_ADDR_10BIT)
{
i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0);
}
else
{
i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0);
}
if (msg->flags & RT_I2C_ADDR_10BIT)
{
i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0);
}
else
{
i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0);
}
if (msg->flags & RT_I2C_RD)
{
if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0)
@ -282,7 +282,7 @@ static const struct rt_i2c_bus_device_ops i2c_ops =
{
gd32_i2c_xfer,
RT_NULL,
RT_NULL
RT_NULL
};
#endif /* RT_USING_I2C_BITOPS */
@ -290,89 +290,89 @@ static const struct rt_i2c_bus_device_ops i2c_ops =
int rt_hw_i2c_init(void)
{
#ifdef RT_USING_I2C_BITOPS
{
static struct rt_i2c_bus_device i2c_device;
static const struct gd32_i2c_bit_data _i2c_bdata =
{
/* SCL */
{ I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN},
/* SDA */
{ I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN},
};
{
static struct rt_i2c_bus_device i2c_device;
static const struct gd32_i2c_bit_data _i2c_bdata =
{
/* SCL */
{ I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN},
/* SDA */
{ I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN},
};
static const struct rt_i2c_bit_ops _i2c_bit_ops =
{
(void*)&_i2c_bdata,
gpio_set_sda,
gpio_set_scl,
gpio_get_sda,
gpio_get_scl,
gpio_udelay,
1,
100
};
static const struct rt_i2c_bit_ops _i2c_bit_ops =
{
(void*)&_i2c_bdata,
gpio_set_sda,
gpio_set_scl,
gpio_get_sda,
gpio_get_scl,
gpio_udelay,
1,
100
};
drv_i2c_gpio_init(&_i2c_bdata);
drv_i2c_gpio_init(&_i2c_bdata);
i2c_device.priv = (void *)&_i2c_bit_ops;
rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME);
}
i2c_device.priv = (void *)&_i2c_bit_ops;
rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME);
}
#else /* register hardware I2C */
#ifdef RT_USING_I2C0
#define I2C0_SPEED 100000
static struct gd32_i2c_bus gd32_i2c0;
/* enable GPIOB clock */
rcu_periph_clock_enable(RCU_GPIOB);
static struct gd32_i2c_bus gd32_i2c0;
/* enable GPIOB clock */
rcu_periph_clock_enable(RCU_GPIOB);
/* connect PB6 to I2C0_SCL, PB7 to I2C0_SDA */
gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7);
/* connect PB6 to I2C0_SCL, PB7 to I2C0_SDA */
gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7);
/* enable I2C clock */
rcu_periph_clock_enable(RCU_I2C0);
/* configure I2C clock */
i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2);
/* enable I2C clock */
rcu_periph_clock_enable(RCU_I2C0);
/* configure I2C clock */
i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2);
i2c_enable(I2C0);
/* enable acknowledge */
i2c_ack_config(I2C0,I2C_ACK_ENABLE);
i2c_enable(I2C0);
/* enable acknowledge */
i2c_ack_config(I2C0,I2C_ACK_ENABLE);
rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus));
gd32_i2c0.parent.ops = &i2c_ops;
gd32_i2c0.i2c_periph = I2C0;
rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0");
rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus));
gd32_i2c0.parent.ops = &i2c_ops;
gd32_i2c0.i2c_periph = I2C0;
rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0");
#endif
#ifdef RT_USING_I2C1
#define I2C1_SPEED 100000
static struct gd32_i2c_bus gd32_i2c1;
/* enable GPIOB clock */
rcu_periph_clock_enable(RCU_GPIOB);
static struct gd32_i2c_bus gd32_i2c1;
/* enable GPIOB clock */
rcu_periph_clock_enable(RCU_GPIOB);
/* connect PB10 to I2C1_SCL, PB11 to I2C1_SDA */
gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11);
/* connect PB10 to I2C1_SCL, PB11 to I2C1_SDA */
gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11);
/* enable I2C clock */
rcu_periph_clock_enable(RCU_I2C1);
/* configure I2C clock */
i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2);
/* enable I2C clock */
rcu_periph_clock_enable(RCU_I2C1);
/* configure I2C clock */
i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2);
i2c_enable(I2C1);
/* enable acknowledge */
i2c_ack_config(I2C1,I2C_ACK_ENABLE);
i2c_enable(I2C1);
/* enable acknowledge */
i2c_ack_config(I2C1,I2C_ACK_ENABLE);
rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus));
gd32_i2c1.parent.ops = &i2c_ops;
gd32_i2c1.i2c_periph = I2C1;
rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1");
rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus));
gd32_i2c1.parent.ops = &i2c_ops;
gd32_i2c1.i2c_periph = I2C1;
rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1");
#endif
#endif /* RT_USING_I2C_BITOPS */
return 0;
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_i2c_init);

20
bsp/gd32303e-eval/drivers/drv_spi.c
View File

@ -29,7 +29,7 @@
#ifdef DEBUG
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define DEBUG_PRINTF(...)
#define DEBUG_PRINTF(...)
#endif
/* private rt-thread spi ops function */
@ -48,8 +48,8 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
if(configuration->data_width <= 8)
{
@ -127,10 +127,10 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
break;
case RT_SPI_MODE_1:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
break;
break;
case RT_SPI_MODE_2:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
break;
break;
case RT_SPI_MODE_3:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
break;
@ -260,9 +260,9 @@ int gd32_hw_spi_init(void)
#ifdef RT_USING_SPI0
static struct rt_spi_bus spi_bus0;
spi_bus0.parent.user_data = (void *)SPI0;
result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops);
rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_SPI0);
/* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */
@ -274,8 +274,8 @@ int gd32_hw_spi_init(void)
static struct rt_spi_bus spi_bus1;
spi_bus1.parent.user_data = (void *)SPI1;
result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops);
result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops);
rcu_periph_clock_enable(RCU_SPI1);
rcu_periph_clock_enable(RCU_GPIOB);
@ -291,7 +291,7 @@ int gd32_hw_spi_init(void)
rcu_periph_clock_enable(RCU_SPI2);
rcu_periph_clock_enable(RCU_GPIOB);
/* SPI2_SCK(PB3), SPI2_MISO(PB4) and SPI2_MOSI(PB5) GPIO pin configuration */
gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_5);
gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4);

45
bsp/gd32303e-eval/drivers/drv_usart.c
View File

@ -36,17 +36,17 @@
// Todo: compress uart info
struct gd32_uart
{
uint32_t uart_periph;
IRQn_Type irqn;
rcu_periph_enum per_clk;
rcu_periph_enum tx_gpio_clk;
rcu_periph_enum rx_gpio_clk;
uint32_t tx_port;
uint16_t tx_pin;
uint32_t rx_port;
uint16_t rx_pin;
uint32_t uart_periph;
IRQn_Type irqn;
rcu_periph_enum per_clk;
rcu_periph_enum tx_gpio_clk;
rcu_periph_enum rx_gpio_clk;
uint32_t tx_port;
uint16_t tx_pin;
uint32_t rx_port;
uint16_t rx_pin;
struct rt_serial_device * serial;
struct rt_serial_device * serial;
char *device_name;
};
@ -137,8 +137,8 @@ static const struct gd32_uart uarts[] = {
USART0, // uart peripheral index
USART0_IRQn, // uart iqrn
RCU_USART0, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock
GPIOA, GPIO_PIN_9, // tx port, tx pin
GPIOA, GPIO_PIN_10, // rx port, rx pin
GPIOA, GPIO_PIN_9, // tx port, tx pin
GPIOA, GPIO_PIN_10, // rx port, rx pin
&serial0,
"uart0",
},
@ -149,8 +149,8 @@ static const struct gd32_uart uarts[] = {
USART1, // uart peripheral index
USART1_IRQn, // uart iqrn
RCU_USART1, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock
GPIOA, GPIO_PIN_2, // tx port, tx pin
GPIOA, GPIO_PIN_3, // rx port, rx pin
GPIOA, GPIO_PIN_2, // tx port, tx pin
GPIOA, GPIO_PIN_3, // rx port, rx pin
&serial1,
"uart1",
},
@ -161,8 +161,8 @@ static const struct gd32_uart uarts[] = {
USART2, // uart peripheral index
USART2_IRQn, // uart iqrn
RCU_USART2, RCU_GPIOB, RCU_GPIOB, // periph clock, tx gpio clock, rt gpio clock
GPIOB, GPIO_PIN_10, // tx port, tx alternate, tx pin
GPIOB, GPIO_PIN_11, // rx port, rx alternate, rx pin
GPIOB, GPIO_PIN_10, // tx port, tx alternate, tx pin
GPIOB, GPIO_PIN_11, // rx port, rx alternate, rx pin
&serial2,
"uart2",
},
@ -173,8 +173,8 @@ static const struct gd32_uart uarts[] = {
UART3, // uart peripheral index
UART3_IRQn, // uart iqrn
RCU_UART3, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock
GPIOC, GPIO_PIN_10, // tx port, tx alternate, tx pin
GPIOC, GPIO_PIN_11, // rx port, rx alternate, rx pin
GPIOC, GPIO_PIN_10, // tx port, tx alternate, tx pin
GPIOC, GPIO_PIN_11, // rx port, rx alternate, rx pin
&serial3,
"uart3",
},
@ -185,8 +185,8 @@ static const struct gd32_uart uarts[] = {
UART4, // uart peripheral index
UART4_IRQn, // uart iqrn
RCU_UART4, RCU_GPIOC, RCU_GPIOD, // periph clock, tx gpio clock, rt gpio clock
GPIOC, GPIO_PIN_12, // tx port, tx alternate, tx pin
GPIOD, GPIO_PIN_2, // rx port, rx alternate, rx pin
GPIOC, GPIO_PIN_12, // tx port, tx alternate, tx pin
GPIOD, GPIO_PIN_2, // rx port, rx alternate, rx pin
&serial4,
"uart4",
},
@ -296,7 +296,6 @@ static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg
/* enable interrupt */
usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE);
break;
}
return RT_EOK;
@ -355,14 +354,14 @@ static const struct rt_uart_ops gd32_uart_ops =
gd32_configure,
gd32_control,
gd32_putc,
gd32_getc,
gd32_getc
};
int gd32_hw_usart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
int i;
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{
uarts[i].serial->ops = &gd32_uart_ops;

2
bsp/gd32303e-eval/gd32_rom.ld
View File

@ -1,5 +1,5 @@
/*
* linker script for GD32F4xx with GNU ld
* linker script for GD32F30x with GNU ld
* bernard.xiong 2009-10-14
*/

2834
bsp/gd32303e-eval/project.ewd Normal file
View File

File diff suppressed because it is too large Load Diff

2
bsp/gd32303e-eval/project.uvoptx
View File

@ -196,7 +196,7 @@
<Group>
<GroupName>Drivers</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>

4
bsp/gd32303e-eval/rtconfig.py
View File

@ -11,8 +11,8 @@ if os.getenv('RTT_CC'):
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'D:/ArdaArmTools/GNUARM_4.9_2015q1/bin'
PLATFORM = 'gcc'
EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'