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修改汇编rt_hw_context_switch_to处关于时间槽的使用；修改格式
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Huang bo
parent
bed7dac514
commit
8ab19db7fa
@ -136,15 +136,14 @@ rt_hw_context_switch_to:
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;
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; this maybe do better
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;
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MVC .S2 B11,RILC ; Restore RILC
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MVC .S2 B10,ILC ; Restore ILC
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MV B13,B3 ; Restore PC
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MVC .S2 B12,CSR ; Restore CSR
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LDDW .D2T2 *++SP[1],B11:B10
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|| MVC .S2 B11,RILC ; Restore RILC
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LDDW .D2T2 *++SP[1],B13:B12
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|| MVC .S2 B10,ILC ; Restore ILC
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LDDW .D2T1 *++SP[1],A11:A10
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|| MV B13,B3 ; Restore PC
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LDDW .D2T1 *++SP[1],A13:A12
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|| MVC .S2 B12,CSR ; Restore CSR
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LDDW .D2T1 *++SP[1],A15:A14
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B B3 ; Return to caller
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ADDAW .D2 SP,2,SP
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@ -236,7 +235,6 @@ _reswitch:
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.global rt_interrupt_context_restore
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rt_interrupt_context_restore:
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;{
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; if rt_switch_interrupt_flag set, jump to rt_hw_context_switch_interrupt and don't return
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MVKL rt_thread_switch_interrupt_flag,A3
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MVKH rt_thread_switch_interrupt_flag,A3
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LDW *A3,A1
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@ -19,7 +19,7 @@ SAVE_ALL .macro __rp, __tsr
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NOP 3
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STW .D2T2 B1,*+SP[1] ; save original B1
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XOR .D2 SP,B1,B0 ; (SP ^ KSP, check current stack types)
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XOR .D2 SP,B1,B0 ; check current stack types
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LDW .D2T2 *+SP[1],B1 ; restore B0/B1
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LDW .D2T2 *++SP[2],B0
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SHR .S2 B0,12,B0 ; 0 if already using system stack
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@ -75,7 +75,7 @@ SAVE_ALL .macro __rp, __tsr
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STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
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STDW .D2T2 B11:B10,*SP--[1] ; save RILC and ILC
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STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4
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STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
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.endm
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RESTORE_ALL .macro __rp, __tsr
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@ -183,5 +183,5 @@ THREAD_SAVE_ALL .macro __rp, __tsr
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STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
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STDW .D2T2 B11:B10,*SP--[1] ; save RILC and ILC
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STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4
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STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
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.endm
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@ -9,7 +9,7 @@
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;
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;-----------------------------------------------------------
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; interrupt and execption handler for C000 DSP
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; interrupt and execption handler for C6000 DSP
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;-----------------------------------------------------------
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;-----------------------------------------------------------
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@ -94,7 +94,7 @@ RT_EXECPTION_ENTRY .macro
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RT_EXECPTION_EXIT .macro
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RESTORE_ALL NRP,NTSR
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B .S2 NRP ; return from interruption
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B .S2 NRP ; return from execption
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NOP 5
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.endm
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@ -137,7 +137,7 @@ ret_from_trap:
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[!B0] MVKH .S2 ret_from_exception,B3
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[!B0] BNOP .S2 B3,5
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;
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; return from trap£¬restore exception context
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; return from trap restore exception context
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;
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ret_from_exception:
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RT_EXECPTION_EXIT
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@ -35,73 +35,73 @@ ADDRESS_MSK .set 0xFFFFFFF0
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;{
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.global rt_hw_stack_init
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rt_hw_stack_init:
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SUB A6,1,B1 ;
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MVKL ADDRESS_MSK,A1 ;
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MVKH ADDRESS_MSK,A1 ; Build address mask
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MVC CSR,B0 ;
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AND -2,B0,B0 ; Clear GIE bit
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OR 2,B0,B0 ; Set PGIE bit for interrupt return
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AND A1,B1,B1 ; Ensure alignment
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SUB A6,1,B1 ;
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MVKL .S1 ADDRESS_MSK,A1 ;
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MVKH .S1 ADDRESS_MSK,A1 ; Build address mask
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MVC .S2 CSR,B0 ;
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AND -2,B0,B0 ; Clear GIE bit
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OR 2,B0,B0 ; Set PGIE bit for interrupt return
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AND A1,B1,B1 ; Ensure alignment
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;
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; Actually build the stack frame.
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;
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MV B1,A3
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MV B14,A2
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STDW A3:A2,*--B1[1] ; Initial B15:B14
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MV .S1 B1,A3
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MV .S1 B14,A2
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STDW .D2T1 A3:A2,*--B1[1] ; Initial B15:B14
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SUBAW .D2 B1,2,B1
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ZERO A2
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ZERO A3 ; Clear value
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STDW A3:A2,*B1--[1] ; Initial A15:A14
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STDW A3:A2,*B1--[1] ; Initial A13:A12
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STDW A3:A2,*B1--[1] ; Initial A11:A10
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STDW A3:A2,*B1--[1] ; Initial A9:A8
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STDW A3:A2,*B1--[1] ; Initial A7:A6
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MV B4,A2
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STDW A3:A2,*B1--[1] ; Initial A5:A4
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ZERO A3 ; Clear value
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A15:A14
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A13:A12
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A11:A10
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A9:A8
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A7:A6
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MV .S1 B4,A2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A5:A4
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ZERO A2
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STDW A3:A2,*B1--[1] ; Initial A3:A2
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STDW A3:A2,*B1--[1] ; Initial A1:A0
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A3:A2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A1:A0
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STDW A3:A2,*B1--[1] ; Initial A31:A30
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STDW A3:A2,*B1--[1] ; Initial A29:A28
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STDW A3:A2,*B1--[1] ; Initial A27:A26
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STDW A3:A2,*B1--[1] ; Initial A25:A24
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STDW A3:A2,*B1--[1] ; Initial A23:A22
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STDW A3:A2,*B1--[1] ; Initial A21:A20
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STDW A3:A2,*B1--[1] ; Initial A19:A18
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STDW A3:A2,*B1--[1] ; Initial A17:A16
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A31:A30
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A29:A28
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A27:A26
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A25:A24
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A23:A22
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A21:A20
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A19:A18
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A17:A16
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STDW A3:A2,*B1--[1] ; Initial B13:B12
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STDW A3:A2,*B1--[1] ; Initial B11:B10
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STDW A3:A2,*B1--[1] ; Initial B9:B8
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STDW A3:A2,*B1--[1] ; Initial B7:B6
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STDW A3:A2,*B1--[1] ; Initial B5:B4
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MV B6,A3
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STDW A3:A2,*B1--[1] ; Initial B3:B2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B13:B12
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B11:B10
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B9:B8
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B7:B6
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B5:B4
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MV .S1 B6,A3
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B3:B2
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ZERO A3
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STDW A3:A2,*B1--[1] ; Initial B1:B0
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B1:B0
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STDW A3:A2,*B1--[1] ; Initial B31:B30
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STDW A3:A2,*B1--[1] ; Initial B29:B28
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STDW A3:A2,*B1--[1] ; Initial B27:B26
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STDW A3:A2,*B1--[1] ; Initial B25:B24
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STDW A3:A2,*B1--[1] ; Initial B23:B22
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STDW A3:A2,*B1--[1] ; Initial B21:B20
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STDW A3:A2,*B1--[1] ; Initial B19:B18
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STDW A3:A2,*B1--[1] ; Initial B17:B16
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B31:B30
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B29:B28
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B27:B26
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B25:B24
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B23:B22
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B21:B20
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B19:B18
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B17:B16
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MV A4,A3
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MV B0,A2
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STDW A3:A2,*B1--[1] ; Initial PC:CSR
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MV .S1 A4,A3
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MV .S1 B0,A2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial PC:CSR
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ZERO A2
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ZERO A3
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STDW A3:A2,*B1--[1] ; Initial ILC:RILC
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STDW .D2T1 A3:A2,*B1--[1] ; Initial ILC:RILC
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B B3
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MVKL 0x3,B0
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MV B0,A3
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MVKL 1,A2
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STDW A3:A2,*B1--[1] ; Initial TSR:stack type
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MV B1,A4 ; Save to TCB
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MVKL .S2 0x3,B0
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MV .S1 B0,A3
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MVKL .S1 1,A2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial TSR:stack type
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MV .S1 B1,A4 ; Save to TCB
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;}
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.end
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