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Merge pull request #3295 from ChazJin/patch-3
Fix bug for synopsys_emac.c
This commit is contained in:
Bernard Xiong
GitHub
commit
891e4794c0
@ -18,6 +18,10 @@
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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*/
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#include "synopsys_emac.h"
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#include "synopsys_emac.h"
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#include "gd32f4xx_enet.h"
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/* The state of enet initialization */
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volatile uint32_t enet_init_state = 0;
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/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
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/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
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extern EMAC_DMADESCTypeDef *DMATxDescToSet;
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extern EMAC_DMADESCTypeDef *DMATxDescToSet;
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@ -28,139 +32,15 @@ extern EMAC_DMADESCTypeDef *DMARxDescToGet;
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*/
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*/
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rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock)
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rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock)
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{
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{
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rt_uint32_t value = 0;
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/*-------------------------------- Reset ethernet -------------------------------*/
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enet_deinit();
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enet_software_reset();
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/*-------------------------------- MAC Config ------------------------------*/
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/* configure the parameters which are usually less cared for enet initialization */
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/*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
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enet_initpara_config(HALFDUPLEX_OPTION, ENET_CARRIERSENSE_DISABLE|ENET_RECEIVEOWN_ENABLE|ENET_RETRYTRANSMISSION_DISABLE|ENET_BACKOFFLIMIT_10|ENET_DEFERRALCHECK_DISABLE);
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/* Get the ETHERNET MACMIIAR value */
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value = ETHERNET_MAC->GAR;
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/* Clear CSR Clock Range CR[2:0] bits */
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value &= MACMIIAR_CR_MASK;
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/* Get hclk frequency value */
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/*-------------------------------- Initialize ENET ------------------------------*/
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/* Set CR bits depending on hclk value */
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enet_init_state = enet_init(ENET_AUTO_NEGOTIATION, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_BROADCAST_FRAMES_PASS);
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if((SystemCoreClock >= 20000000)&&(SystemCoreClock < 35000000))
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{
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/* CSR Clock Range between 20-35 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div16;
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}
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else if((SystemCoreClock >= 35000000)&&(SystemCoreClock < 60000000))
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{
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/* CSR Clock Range between 35-60 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div26;
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}
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else if((SystemCoreClock >= 60000000)&&(SystemCoreClock <= 100000000))
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{
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/* CSR Clock Range between 60-100 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div42;
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}
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else if((SystemCoreClock >= 100000000)&&(SystemCoreClock <= 150000000))
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{
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/* CSR Clock Range between 100-150 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div62;
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}
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else if((SystemCoreClock >= 150000000)&&(SystemCoreClock <= 250000000))
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{
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/* CSR Clock Range between 150-250 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div102;
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}
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else /* if((SystemCoreClock >= 250000000)&&(SystemCoreClock <= 300000000)) */
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{
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/* CSR Clock Range between 250-300 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div122;
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}
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/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
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ETHERNET_MAC->GAR = (rt_uint32_t)value;
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/*------------------------ ETHERNET MACCR Configuration --------------------*/
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/* Get the ETHERNET MACCR value */
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value = ETHERNET_MAC->MCR;
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/* Clear WD, PCE, PS, TE and RE bits */
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value &= MACCR_CLEAR_MASK;
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value |= (rt_uint32_t)(EMAC_Watchdog_Enable |
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EMAC_Jabber_Enable |
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EMAC_InterFrameGap_96Bit |
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EMAC_CarrierSense_Enable |
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EMAC_Speed_100M |
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EMAC_ReceiveOwn_Enable |
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EMAC_LoopbackMode_Disable |
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EMAC_Mode_FullDuplex |
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EMAC_ChecksumOffload_Enable |
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EMAC_RetryTransmission_Disable |
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EMAC_AutomaticPadCRCStrip_Disable |
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EMAC_BackOffLimit_10 |
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EMAC_DeferralCheck_Disable);
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/* Write to ETHERNET MACCR */
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value |= (1<<15);
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value &= ~(1<<25);
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value &= ~(1<<24);
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ETHERNET_MAC->MCR = (rt_uint32_t)value;
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/*----------------------- ETHERNET MACFFR Configuration --------------------*/
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/* Write to ETHERNET MACFFR */
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ETHERNET_MAC->MFFR = (rt_uint32_t)(EMAC_ReceiveAll_Enable |
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EMAC_SourceAddrFilter_Disable |
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EMAC_PassControlFrames_BlockAll |
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EMAC_BroadcastFramesReception_Disable |
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EMAC_DestinationAddrFilter_Normal |
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EMAC_PromiscuousMode_Disable |
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EMAC_MulticastFramesFilter_Perfect |
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EMAC_UnicastFramesFilter_Perfect);
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/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
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/* Write to ETHERNET MACHTHR */
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ETHERNET_MAC->MHTRH = 0;
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/* Write to ETHERNET MACHTLR */
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ETHERNET_MAC->MHTRL = 0;
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/*----------------------- ETHERNET MACFCR Configuration --------------------*/
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/* Get the ETHERNET MACFCR value */
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value = ETHERNET_MAC->FCR;
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/* Clear xx bits */
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value &= MACFCR_CLEAR_MASK;
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value |= (rt_uint32_t)((0 << 16) |
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EMAC_ZeroQuantaPause_Disable |
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EMAC_PauseLowThreshold_Minus4 |
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EMAC_UnicastPauseFrameDetect_Disable |
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EMAC_ReceiveFlowControl_Disable |
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EMAC_TransmitFlowControl_Disable);
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/* Write to ETHERNET MACFCR */
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ETHERNET_MAC->FCR = (rt_uint32_t)value;
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/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
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ETHERNET_MAC->VTR = (rt_uint32_t)(EMAC_VLANTagComparison_16Bit |
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0);
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/*-------------------------------- DMA Config ------------------------------*/
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/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
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/* Get the ETHERNET DMAOMR value */
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value = ETHERNET_MAC->OMR;
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/* Clear xx bits */
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value &= DMAOMR_CLEAR_MASK;
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value |= (rt_uint32_t)(EMAC_DropTCPIPChecksumErrorFrame_Disable |
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EMAC_ReceiveStoreForward_Enable |
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EMAC_FlushReceivedFrame_Enable |
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EMAC_TransmitStoreForward_Enable |
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EMAC_TransmitThresholdControl_64Bytes |
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EMAC_ForwardErrorFrames_Disable |
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EMAC_ForwardUndersizedGoodFrames_Disable |
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EMAC_ReceiveThresholdControl_64Bytes |
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EMAC_SecondFrameOperate_Disable);
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/* Write to ETHERNET DMAOMR */
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ETHERNET_MAC->OMR = (rt_uint32_t)value;
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/*----------------------- ETHERNET DMABMR Configuration --------------------*/
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ETHERNET_MAC->BMR = (rt_uint32_t)(EMAC_AddressAlignedBeats_Enable |
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EMAC_FixedBurst_Enable |
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EMAC_RxDMABurstLength_32Beat | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
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EMAC_TxDMABurstLength_32Beat |
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(0 << 2) |
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EMAC_DMAArbitration_RoundRobin_RxTx_2_1 |
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EMAC_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
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/* Return Ethernet configuration success */
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/* Return Ethernet configuration success */
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return EMAC_SUCCESS;
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return EMAC_SUCCESS;
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@ -288,7 +168,7 @@ void EMAC_start(struct rt_synopsys_eth * ETHERNET_MAC)
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/* Enable transmit state machine of the MAC for transmission on the MII */
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/* Enable transmit state machine of the MAC for transmission on the MII */
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EMAC_MACTransmissionCmd(ETHERNET_MAC, RT_TRUE);
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EMAC_MACTransmissionCmd(ETHERNET_MAC, RT_TRUE);
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/* Flush Transmit FIFO */
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/* Flush Transmit FIFO */
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EMAC_FlushTransmitFIFO(ETHERNET_MAC);
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enet_txfifo_flush();
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/* Enable receive state machine of the MAC for reception from the MII */
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/* Enable receive state machine of the MAC for reception from the MII */
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EMAC_MACReceptionCmd(ETHERNET_MAC, RT_TRUE);
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EMAC_MACReceptionCmd(ETHERNET_MAC, RT_TRUE);
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