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This commit is contained in:
Huang bo 2021-11-17 18:44:00 +08:00
parent cbc0e1ffcf
commit 87598c7b43
5 changed files with 7 additions and 14 deletions
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4
bsp/ti-tms320c6678/applications/board.c
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@ -27,11 +27,11 @@ void rt_hw_board_init(void)
rt_hw_interrupt_init();
// initial system timer
hw_system_timer_init();
rt_hw_system_timer_init();
/* initialize memory system */
rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
hw_system_timer_start();
rt_hw_system_timer_start();
}

4
bsp/ti-tms320c6678/driver/drv_timer.c
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@ -32,7 +32,7 @@ void rt_hw_systick_isr(void)
/**
* The function initial system timer interrupt.
*/
void hw_system_timer_init(void)
void rt_hw_system_timer_init(void)
{
// initial system timer interrupt, map local timer interrupt to INT14
gpCGEM_regs->INTMUX3 = (CSL_GEM_TINTLN<<CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
@ -47,7 +47,7 @@ void hw_system_timer_init(void)
* Use local timer (==DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
*
*/
void hw_system_timer_start(void)
void rt_hw_system_timer_start(void)
{
Timer64_Config tmrCfg;

4
bsp/ti-tms320c6678/driver/drv_timer.h
View File

@ -11,9 +11,9 @@
#ifndef __SYS_TIMER_H__
#define __SYS_TIMER_H__
void hw_system_timer_init(void);
void rt_hw_system_timer_init(void);
void hw_system_timer_start(void);
void rt_hw_system_timer_start(void);
#endif /* __SYS_TIMER_H__ */

7
libcpu/ti-dsp/c6x/c66xx.h
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@ -19,13 +19,6 @@
#define REG_PAIR(odd, even) unsigned long even; unsigned long odd
#endif
/*
* this struct defines the way the registers are stored on the
* stack during a system call. fields defined with REG_PAIR
* are saved and restored using double-word memory operations
* which means the word ordering of the pair depends on endianess.
*/
struct rt_hw_register
{
REG_PAIR(b17, b16);

2
libcpu/ti-dsp/c6x/context.asm
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@ -45,7 +45,7 @@ rt_hw_enable_exception:
DINT
MVC .S2 TSR,B0
MVC .S2 B3,NRP
MVK .L2 0xc,B1
MVK .L2 0xC,B1
OR .D2 B0,B1,B0
MVC .S2 B0,TSR ; Set GEE and XEN in TSR
B .S2 NRP