[fixup] aarch64 UMP compiler error (#8677)
Signed-off-by: Shell <smokewood@qq.com>
This commit is contained in:
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6d1bc9b2f8
commit
864055bf18
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@ -1474,7 +1474,7 @@ static const char *ofw_get_prop_fuzzy_name(const struct rt_ofw_node *np, const c
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char *sf, split_field[64];
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char *sf, split_field[64];
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rt_size_t len = 0, max_ak = 0;
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rt_size_t len = 0, max_ak = 0;
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const char *str, *result = RT_NULL;
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const char *str, *result = RT_NULL;
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RT_BITMAP_DECLARE(ak, sizeof(split_field));
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RT_BITMAP_DECLARE(ak, sizeof(split_field)) = {0};
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struct rt_ofw_prop *prop;
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struct rt_ofw_prop *prop;
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/*
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/*
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@ -624,7 +624,7 @@ int rt_ofw_get_irq(struct rt_ofw_node *np, int index)
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if ((rt_int64_t)cpuid >= 0)
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if ((rt_int64_t)cpuid >= 0)
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{
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{
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RT_DECLARE_BITMAP(affinity, RT_CPUS_NR) = { 0 };
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RT_BITMAP_DECLARE(affinity, RT_CPUS_NR) = { 0 };
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rt_bitmap_set_bit(affinity, cpuid);
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rt_bitmap_set_bit(affinity, cpuid);
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@ -66,7 +66,7 @@ void rt_hw_interrupt_uninstall(int vector, rt_isr_handler_t handler, void *param
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#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
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#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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{
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{
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RT_DECLARE_BITMAP(cpu_masks, RT_CPUS_NR) = { cpu_mask };
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RT_BITMAP_DECLARE(cpu_masks, RT_CPUS_NR) = { cpu_mask };
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rt_pic_irq_send_ipi(ipi_vector, cpu_masks);
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rt_pic_irq_send_ipi(ipi_vector, cpu_masks);
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}
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}
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@ -879,7 +879,8 @@ static void rtthread_timer_wrapper(void *timerobj)
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}
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}
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#ifdef RT_USING_SMART
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#ifdef RT_USING_SMART
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/* this field is named as tid in musl */
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/* this field is named as tid in musl */
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int tid = *(int *)&timer->sigev_notify_function;
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void *ptid = &timer->sigev_notify_function;
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int tid = *(int *)ptid;
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struct lwp_timer_event_param *data = rt_container_of(timer->work, struct lwp_timer_event_param, work);
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struct lwp_timer_event_param *data = rt_container_of(timer->work, struct lwp_timer_event_param, work);
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data->signo = timer->sigev_signo;
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data->signo = timer->sigev_signo;
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@ -89,7 +89,7 @@ static rt_err_t _mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, int flags)
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}
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}
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else
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else
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{
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{
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rc = -RT_EINVAL;
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rc = -RT_ERROR;
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LOG_W("%s: mtx should not be NULL", __func__);
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LOG_W("%s: mtx should not be NULL", __func__);
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RT_ASSERT(0);
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RT_ASSERT(0);
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}
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}
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@ -2700,7 +2700,7 @@ sysret_t sys_execve(const char *path, char *const argv[], char *const envp[])
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*/
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*/
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RT_ASSERT(rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling) == thread);
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RT_ASSERT(rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling) == thread);
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strncpy(thread->parent.name, run_name + last_backslash, RT_NAME_MAX);
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strncpy(thread->parent.name, run_name + last_backslash, RT_NAME_MAX - 1);
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strncpy(lwp->cmd, new_lwp->cmd, RT_NAME_MAX);
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strncpy(lwp->cmd, new_lwp->cmd, RT_NAME_MAX);
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rt_free(lwp->exe_file);
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rt_free(lwp->exe_file);
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lwp->exe_file = strndup(new_lwp->exe_file, DFS_PATH_MAX);
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lwp->exe_file = strndup(new_lwp->exe_file, DFS_PATH_MAX);
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@ -109,7 +109,7 @@ static void _collect()
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rt_page_t page = _trace_head;
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rt_page_t page = _trace_head;
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if (!page)
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if (!page)
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{
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{
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LOG_RAW("ok! ALLOC CNT %ld\n", _alloc_cnt);
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rt_kprintf("ok! ALLOC CNT %ld\n", _alloc_cnt);
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}
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}
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else
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else
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{
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{
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@ -159,7 +159,7 @@ void _report(rt_page_t page, size_t size_bits, char *msg)
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{
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{
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void *pg_va = rt_page_page2addr(page);
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void *pg_va = rt_page_page2addr(page);
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LOG_W("%s: %p, allocator: %p, size bits: %lx", msg, pg_va, page->caller, page->trace_size);
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LOG_W("%s: %p, allocator: %p, size bits: %lx", msg, pg_va, page->caller, page->trace_size);
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LOG_RAW("backtrace\n");
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rt_kprintf("backtrace\n");
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rt_backtrace();
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rt_backtrace();
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}
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}
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@ -175,7 +175,7 @@ static void _trace_free(rt_page_t page, void *caller, size_t size_bits)
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}
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}
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else if (page->trace_size != size_bits)
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else if (page->trace_size != size_bits)
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{
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{
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LOG_RAW("free with size bits %lx\n", size_bits);
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rt_kprintf("free with size bits %lx\n", size_bits);
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_report(page, size_bits, "incompatible size bits parameter");
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_report(page, size_bits, "incompatible size bits parameter");
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return ;
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return ;
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}
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}
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@ -636,7 +636,7 @@ void list_page(void)
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rt_kprintf("[0x%08p]", rt_page_page2addr(hp));
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rt_kprintf("[0x%08p]", rt_page_page2addr(hp));
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hp = hp->next;
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hp = hp->next;
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}
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}
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LOG_RAW("\n");
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rt_kprintf("\n");
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}
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}
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rt_spin_unlock_irqrestore(&_spinlock, level);
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rt_spin_unlock_irqrestore(&_spinlock, level);
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@ -12,8 +12,8 @@ if GetDepend('RT_USING_OFW') == False:
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SrcRemove(src, ['setup.c', 'cpu_psci.c', 'psci.c'])
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SrcRemove(src, ['setup.c', 'cpu_psci.c', 'psci.c'])
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if GetDepend('RT_USING_PIC') == True:
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if GetDepend('RT_USING_PIC') == True:
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SrcRemove(src, ['gicv3.c', 'gic.c', 'interrupt.c', 'gtimer.c'])
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SrcRemove(src, ['gicv3.c', 'gic.c', 'gtimer.c'])
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group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
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group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
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# build for sub-directory
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# build for sub-directory
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@ -16,10 +16,6 @@
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#include "gicv3.h"
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#include "gicv3.h"
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#include "ioremap.h"
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#include "ioremap.h"
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/* exception and interrupt handler table */
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struct rt_irq_desc isr_table[MAX_HANDLERS];
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#ifndef RT_USING_SMP
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#ifndef RT_USING_SMP
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/* Those variables will be accessed in ISR, so we need to share them. */
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/* Those variables will be accessed in ISR, so we need to share them. */
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rt_ubase_t rt_interrupt_from_thread = 0;
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rt_ubase_t rt_interrupt_from_thread = 0;
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@ -27,6 +23,11 @@ rt_ubase_t rt_interrupt_to_thread = 0;
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rt_ubase_t rt_thread_switch_interrupt_flag = 0;
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rt_ubase_t rt_thread_switch_interrupt_flag = 0;
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#endif
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#endif
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#ifndef RT_USING_PIC
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/* exception and interrupt handler table */
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struct rt_irq_desc isr_table[MAX_HANDLERS];
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#ifndef RT_CPUS_NR
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#ifndef RT_CPUS_NR
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#define RT_CPUS_NR 1
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#define RT_CPUS_NR 1
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#endif
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#endif
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@ -138,17 +139,17 @@ void rt_hw_interrupt_mask(int vector)
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#ifdef SOC_BCM283x
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#ifdef SOC_BCM283x
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if (vector < 32)
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if (vector < 32)
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{
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{
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IRQ_DISABLE1 = (1 << vector);
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IRQ_DISABLE1 = (1UL << vector);
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}
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}
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else if (vector < 64)
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else if (vector < 64)
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{
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{
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vector = vector % 32;
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vector = vector % 32;
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IRQ_DISABLE2 = (1 << vector);
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IRQ_DISABLE2 = (1UL << vector);
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}
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}
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else
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else
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{
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{
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vector = vector - 64;
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vector = vector - 64;
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IRQ_DISABLE_BASIC = (1 << vector);
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IRQ_DISABLE_BASIC = (1UL << vector);
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}
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}
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#else
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#else
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arm_gic_mask(0, vector);
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arm_gic_mask(0, vector);
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@ -164,17 +165,17 @@ void rt_hw_interrupt_umask(int vector)
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#ifdef SOC_BCM283x
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#ifdef SOC_BCM283x
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if (vector < 32)
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if (vector < 32)
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{
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{
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IRQ_ENABLE1 = (1 << vector);
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IRQ_ENABLE1 = (1UL << vector);
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}
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}
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else if (vector < 64)
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else if (vector < 64)
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{
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{
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vector = vector % 32;
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vector = vector % 32;
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IRQ_ENABLE2 = (1 << vector);
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IRQ_ENABLE2 = (1UL << vector);
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}
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}
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else
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else
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{
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{
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vector = vector - 64;
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vector = vector - 64;
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IRQ_ENABLE_BASIC = (1 << vector);
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IRQ_ENABLE_BASIC = (1UL << vector);
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}
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}
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#else
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#else
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arm_gic_umask(0, vector);
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arm_gic_umask(0, vector);
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@ -416,6 +417,8 @@ void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
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}
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}
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#endif
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#endif
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#endif /* RT_USING_PIC */
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#if defined(FINSH_USING_MSH) && defined(RT_USING_INTERRUPT_INFO)
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#if defined(FINSH_USING_MSH) && defined(RT_USING_INTERRUPT_INFO)
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int list_isr()
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int list_isr()
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{
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{
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@ -688,6 +688,7 @@ static unsigned long *_query(rt_aspace_t aspace, void *vaddr, int *plvl_shf)
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if (!(cur_lv_tbl[off] & MMU_TYPE_USED))
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if (!(cur_lv_tbl[off] & MMU_TYPE_USED))
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{
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{
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*plvl_shf = level_shift;
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return (void *)0;
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return (void *)0;
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}
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}
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@ -707,11 +708,11 @@ static unsigned long *_query(rt_aspace_t aspace, void *vaddr, int *plvl_shf)
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off &= MMU_LEVEL_MASK;
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off &= MMU_LEVEL_MASK;
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page = cur_lv_tbl[off];
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page = cur_lv_tbl[off];
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*plvl_shf = level_shift;
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if (!(page & MMU_TYPE_USED))
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if (!(page & MMU_TYPE_USED))
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{
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{
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return (void *)0;
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return (void *)0;
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}
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}
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*plvl_shf = level_shift;
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return &cur_lv_tbl[off];
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return &cur_lv_tbl[off];
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}
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}
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@ -27,9 +27,10 @@ class CPPCheck:
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[
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[
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'cppcheck',
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'cppcheck',
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'-DRT_ASSERT(x)=',
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'-DRT_ASSERT(x)=',
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'-Drt_list_for_each_entry(a,b,c)=a=(void*)b',
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'-Drt_list_for_each_entry(a,b,c)=a=(void*)b;',
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'-I include',
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'-I include',
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'-I thread/components/finsh',
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'-I thread/components/finsh',
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# it's okay because CI will do the real compilation to check this
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'--suppress=syntaxError',
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'--suppress=syntaxError',
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'--enable=warning',
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'--enable=warning',
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'performance',
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'performance',
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