libs/rt-thread-official
libs
/
rt-thread-official
mirror of https://github.com/RT-Thread/rt-thread.git
4
0
Fork 0
Code Issues Releases Wiki Activity

Merge pull request #2978 from Liufeilong66/master 

龙芯1c部分问题
This commit is contained in:
Bernard Xiong 2019-08-21 17:16:54 +08:00 committed by GitHub
parent d682c35441 ab818cda30
commit 863c549497
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 139 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
bsp/ls1cdev/drivers/drv_gpio.c
View File

@ -73,8 +73,24 @@ rt_err_t ls1c_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
{
unsigned int gpio = pin;
char irq_name[10];
gpio_set_irq_type(gpio, mode);
rt_uint32_t type;
switch (mode)
{
case PIN_IRQ_MODE_RISING:
type=IRQ_TYPE_EDGE_RISING;
break;
case PIN_IRQ_MODE_FALLING:
type=IRQ_TYPE_EDGE_FALLING;
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
type=IRQ_TYPE_LEVEL_HIGH;
break;
case PIN_IRQ_MODE_LOW_LEVEL:
type=IRQ_TYPE_LEVEL_LOW;
break;
}
gpio_set_irq_type(gpio, type);
rt_sprintf(irq_name, "PIN_%d", gpio);
rt_hw_interrupt_install(LS1C_GPIO_TO_IRQ(gpio), (rt_isr_handler_t)hdr, args, irq_name);

55
bsp/ls1cdev/drivers/drv_spi.c
View File

@ -25,13 +25,14 @@
#include <rtthread.h>
#include <drivers/spi.h>
#include <rthw.h>
#include "drv_spi.h"
#include "ls1c_public.h"
#include "spi_msd.h"
#include "dfs_fs.h"
#include "../libraries/ls1c_pin.h"
#ifdef RT_USING_SPI
//#define DEBUG
#ifdef DEBUG
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
@ -265,20 +266,24 @@ int ls1c_hw_spi_init(void)
#ifdef RT_USING_SPI0
/* attach cs */
{
static struct rt_spi_device spi_device0;
static struct rt_spi_device spi_device1;
static struct rt_spi_device spi_device2;
static struct ls1c_spi_cs spi_cs0;
static struct ls1c_spi_cs spi_cs1;
static struct ls1c_spi_cs spi_cs2;
/* spi02: CS2 SD Card*/
spi_cs2.cs = LS1C_SPI_CS_2;
rt_spi_bus_attach_device(&spi_device2, "spi02", "spi0", (void *)&spi_cs2);
spi_cs1.cs = LS1C_SPI_CS_1;
rt_spi_bus_attach_device(&spi_device1, "spi01", "spi0", (void *)&spi_cs1);
spi_cs0.cs = LS1C_SPI_CS_0;
rt_spi_bus_attach_device(&spi_device0, "spi00", "spi0", (void *)&spi_cs0);
static struct rt_spi_device spi_device0;
static struct rt_spi_device spi_device1;
static struct rt_spi_device spi_device2;
static struct rt_spi_device spi_device3;
static struct ls1c_spi_cs spi_cs0;
static struct ls1c_spi_cs spi_cs1;
static struct ls1c_spi_cs spi_cs2;
static struct ls1c_spi_cs spi_cs3;
/* spi02: CS2 SD Card*/
spi_cs2.cs = LS1C_SPI_CS_2;
rt_spi_bus_attach_device(&spi_device2, "spi02", "spi0", (void *)&spi_cs2);
spi_cs1.cs = LS1C_SPI_CS_1;
rt_spi_bus_attach_device(&spi_device1, "spi01", "spi0", (void *)&spi_cs1);
spi_cs0.cs = LS1C_SPI_CS_0;
rt_spi_bus_attach_device(&spi_device0, "spi00", "spi0", (void *)&spi_cs0);
spi_cs3.cs = LS1C_SPI_CS_3;
rt_spi_bus_attach_device(&spi_device3, "spi03", "spi0", (void*)&spi_cs3);
msd_init("sd0", "spi02");
}
#endif
#ifdef RT_USING_SPI1
@ -296,5 +301,21 @@ int ls1c_hw_spi_init(void)
INIT_BOARD_EXPORT(ls1c_hw_spi_init);
static int board_sd_init(void)
{
#if defined(RT_USING_DFS) && defined(RT_USING_DFS_ELMFAT)
/* mount sd card fat partition 1 as root directory */
if( dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
{
rt_kprintf("File System initialzation failed!\n");
}
#endif /* RT_USING_DFS && RT_USING_DFS_ELMFAT */
}
INIT_APP_EXPORT(board_sd_init);
#endif

28
bsp/ls1cdev/drivers/net/synopGMAC.c
View File

@ -572,22 +572,16 @@ struct pbuf *rt_eth_rx(rt_device_t device)
}
/*Handle the Receive Descriptors*/
do
{
desc_index = synopGMAC_get_rx_qptr(gmacdev, &status, &dma_addr1, NULL, &data1, &dma_addr2, NULL, &data2);
if (desc_index >= 0 && data1 != 0)
desc_index = synopGMAC_get_rx_qptr(gmacdev, &status, &dma_addr1, NULL, &data1, &dma_addr2, NULL, &data2);
if (desc_index >= 0 && data1 != 0)
{
DEBUG_MES("Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x\n", desc_index, dma_addr1, status);
if (synopGMAC_is_rx_desc_valid(status) || SYNOP_PHY_LOOPBACK)
DEBUG_MES("Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x\n", desc_index, dma_addr1, status);
if (synopGMAC_is_rx_desc_valid(status) || SYNOP_PHY_LOOPBACK)
{
pbuf = pbuf_alloc(PBUF_LINK, MAX_ETHERNET_PAYLOAD, PBUF_RAM);
if (pbuf == 0) rt_kprintf("===error in pbuf_alloc\n");
dma_addr1 = plat_dma_map_single(gmacdev, (void *)data1, RX_BUF_SIZE);
len = synopGMAC_get_rx_desc_frame_length(status); //Not interested in Ethernet CRC bytes
len = synopGMAC_get_rx_desc_frame_length(status)-4; //Not interested in Ethernet CRC bytes
pbuf = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
if (pbuf == 0) rt_kprintf("===error in pbuf_alloc\n");
rt_memcpy(pbuf->payload, (char *)data1, len);
DEBUG_MES("==get pkg len: %d\n", len);
}
@ -600,19 +594,15 @@ struct pbuf *rt_eth_rx(rt_device_t device)
adapter->synopGMACNetStats.rx_frame_errors += synopGMAC_is_frame_dribbling_errors(status);
adapter->synopGMACNetStats.rx_length_errors += synopGMAC_is_rx_frame_length_errors(status);
}
desc_index = synopGMAC_set_rx_qptr(gmacdev, dma_addr1, RX_BUF_SIZE, (u32)data1, 0, 0, 0);
if (desc_index < 0)
{
#if SYNOP_RX_DEBUG
#if SYNOP_RX_DEBUG
rt_kprintf("Cannot set Rx Descriptor for data1 %08x\n", (u32)data1);
#endif
#endif
plat_free_memory((void *)data1);
}
}
}while(desc_index >= 0);
rt_sem_release(&sem_lock);
DEBUG_MES("%s : before return \n", __FUNCTION__);
return pbuf;

148
libcpu/mips/loongson_1c/ls1c.h
View File

@ -18,36 +18,36 @@
#include "../common/mipsregs.h"
#define LS1C_ACPI_IRQ 0
#define LS1C_HPET_IRQ 1
//#define LS1C_UART0_IRQ 3 // linux中是3，v1.4版本的1c手册中是2，暂屏蔽，待确认
#define LS1C_UART1_IRQ 4
#define LS1C_UART2_IRQ 5
#define LS1C_CAN0_IRQ 6
#define LS1C_CAN1_IRQ 7
#define LS1C_SPI0_IRQ 8
#define LS1C_SPI1_IRQ 9
#define LS1C_AC97_IRQ 10
#define LS1C_MS_IRQ 11
#define LS1C_KB_IRQ 12
#define LS1C_DMA0_IRQ 13
#define LS1C_DMA1_IRQ 14
#define LS1C_DMA2_IRQ 15
#define LS1C_NAND_IRQ 16
#define LS1C_PWM0_IRQ 17
#define LS1C_PWM1_IRQ 18
#define LS1C_PWM2_IRQ 19
#define LS1C_PWM3_IRQ 20
#define LS1C_ACPI_IRQ 0
#define LS1C_HPET_IRQ 1
//#define LS1C_UART0_IRQ 3 // linux中是3，v1.4版本的1c手册中是2，暂屏蔽，待确认
#define LS1C_UART1_IRQ 4
#define LS1C_UART2_IRQ 5
#define LS1C_CAN0_IRQ 6
#define LS1C_CAN1_IRQ 7
#define LS1C_SPI0_IRQ 8
#define LS1C_SPI1_IRQ 9
#define LS1C_AC97_IRQ 10
#define LS1C_MS_IRQ 11
#define LS1C_KB_IRQ 12
#define LS1C_DMA0_IRQ 13
#define LS1C_DMA1_IRQ 14
#define LS1C_DMA2_IRQ 15
#define LS1C_NAND_IRQ 16
#define LS1C_PWM0_IRQ 17
#define LS1C_PWM1_IRQ 18
#define LS1C_PWM2_IRQ 19
#define LS1C_PWM3_IRQ 20
#define LS1C_RTC_INT0_IRQ 21
#define LS1C_RTC_INT1_IRQ 22
#define LS1C_RTC_INT2_IRQ 23
#define LS1C_UART3_IRQ 29
#define LS1C_ADC_IRQ 30
#define LS1C_SDIO_IRQ 31
#define LS1C_UART3_IRQ 29
#define LS1C_ADC_IRQ 30
#define LS1C_SDIO_IRQ 31
#define LS1C_EHCI_IRQ (32+0)
#define LS1C_OHCI_IRQ (32+1)
#define LS1C_EHCI_IRQ (32+0)
#define LS1C_OHCI_IRQ (32+1)
#define LS1C_OTG_IRQ (32+2)
#define LS1C_MAC_IRQ (32+3)
#define LS1C_CAM_IRQ (32+4)
@ -64,7 +64,7 @@
#define LS1C_I2C0_IRQ (32+19)
#define LS1C_GPIO_IRQ 64
#define LS1C_GPIO_IRQ 64
#define LS1C_GPIO_FIRST_IRQ 64
#define LS1C_GPIO_IRQ_COUNT 96
#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
@ -84,72 +84,72 @@
struct ls1c_intc_regs
{
volatile unsigned int int_isr;
volatile unsigned int int_en;
volatile unsigned int int_set;
volatile unsigned int int_clr; /* offset 0x10*/
volatile unsigned int int_pol;
volatile unsigned int int_edge; /* offset 0 */
volatile unsigned int int_isr;
volatile unsigned int int_en;
volatile unsigned int int_set;
volatile unsigned int int_clr; /* offset 0x10*/
volatile unsigned int int_pol;
volatile unsigned int int_edge; /* offset 0 */
};
struct ls1c_cop_global_regs
{
volatile unsigned int control;
volatile unsigned int rd_inten;
volatile unsigned int wr_inten;
volatile unsigned int rd_intisr; /* offset 0x10*/
volatile unsigned int wr_intisr;
unsigned int unused[11];
volatile unsigned int control;
volatile unsigned int rd_inten;
volatile unsigned int wr_inten;
volatile unsigned int rd_intisr; /* offset 0x10*/
volatile unsigned int wr_intisr;
unsigned int unused[11];
} ;
struct ls1c_cop_channel_regs
{
volatile unsigned int rd_control;
volatile unsigned int rd_src;
volatile unsigned int rd_cnt;
volatile unsigned int rd_status; /* offset 0x10*/
volatile unsigned int wr_control;
volatile unsigned int wr_src;
volatile unsigned int wr_cnt;
volatile unsigned int wr_status; /* offset 0x10*/
volatile unsigned int rd_control;
volatile unsigned int rd_src;
volatile unsigned int rd_cnt;
volatile unsigned int rd_status; /* offset 0x10*/
volatile unsigned int wr_control;
volatile unsigned int wr_src;
volatile unsigned int wr_cnt;
volatile unsigned int wr_status; /* offset 0x10*/
} ;
struct ls1c_cop_regs
{
struct ls1c_cop_global_regs global;
struct ls1c_cop_channel_regs chan[8][2];
struct ls1c_cop_global_regs global;
struct ls1c_cop_channel_regs chan[8][2];
} ;
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define GMAC0_BASE 0xBFE10000
#define GMAC0_DMA_BASE 0xBFE11000
#define GMAC1_BASE 0xBFE20000
#define GMAC1_DMA_BASE 0xBFE21000
#define I2C0_BASE 0xBFE58000
#define PWM0_BASE 0xBFE5C000
#define PWM1_BASE 0xBFE5C010
#define PWM2_BASE 0xBFE5C020
#define PWM3_BASE 0xBFE5C030
#define WDT_BASE 0xBFE5C060
#define RTC_BASE 0xBFE64000
#define I2C1_BASE 0xBFE68000
#define I2C2_BASE 0xBFE70000
#define AC97_BASE 0xBFE74000
#define NAND_BASE 0xBFE78000
#define SPI_BASE 0xBFE80000
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
#define GMAC0_BASE 0xBFE10000
#define GMAC0_DMA_BASE 0xBFE11000
#define GMAC1_BASE 0xBFE20000
#define GMAC1_DMA_BASE 0xBFE21000
#define I2C0_BASE 0xBFE58000
#define PWM0_BASE 0xBFE5C000
#define PWM1_BASE 0xBFE5C010
#define PWM2_BASE 0xBFE5C020
#define PWM3_BASE 0xBFE5C030
#define WDT_BASE 0xBFE5C060
#define RTC_BASE 0xBFE64000
#define I2C1_BASE 0xBFE68000
#define I2C2_BASE 0xBFE70000
#define AC97_BASE 0xBFE74000
#define NAND_BASE 0xBFE78000
#define SPI_BASE 0xBFE80000
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
/* Watch Dog registers */
#define WDT_EN __REG32(WDT_BASE + 0x00)
#define WDT_SET __REG32(WDT_BASE + 0x04)
#define WDT_TIMER __REG32(WDT_BASE + 0x08)
#define WDT_EN __REG32(WDT_BASE + 0x00)
#define WDT_SET __REG32(WDT_BASE + 0x08)
#define WDT_TIMER __REG32(WDT_BASE + 0x04)
#define PLL_FREQ __REG32(0xbfe78030)
#define PLL_DIV_PARAM __REG32(0xbfe78034)
#define PLL_FREQ __REG32(0xbfe78030)
#define PLL_DIV_PARAM __REG32(0xbfe78034)
#endif