螺丝松掉的人
GitHub
parent
1632ad083a
commit
84af32db34
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@ -15,8 +15,8 @@ if GetDepend(['RT_USING_SERIAL']):
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else:
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src += ['drv_uart.c']
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# if GetDepend('RT_USING_PIN'):
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# src += ['drv_gpio.c']
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if GetDepend('RT_USING_PIN'):
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src += ['drv_gpio.c']
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# if GetDepend('BSP_USING_LCD'):
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# src += ['drv_lcd.c']
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@ -76,6 +76,11 @@ void rt_hw_board_init(void)
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rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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#endif
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/* GPIO driver initialization is open by default */
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#ifdef RT_USING_PIN
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rt_hw_pin_init();
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#endif
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/* UART driver initialization is open by default */
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#ifdef RT_USING_SERIAL
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rt_hw_uart_init();
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@ -0,0 +1,208 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023/01/5 chushicheng first version
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*
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*/
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#include "drv_gpio.h"
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#include <stdbool.h>
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#include "bl808_gpio.h"
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#include "bl808_glb.h"
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#include "bl808.h"
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#ifdef RT_USING_PIN
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#define DBG_TAG "drv.gpio"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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static void GPIO0_IRQHandler(void);
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struct gpio_int_cfg_private
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{
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slist_t list;
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uint32_t pin;
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void (*hdr)(uint32_t pin);
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};
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static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head);
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static void bl808_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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GLB_GPIO_Write(pin, value);
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}
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static int bl808_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int value;
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value = GLB_GPIO_Read(pin);;
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return value;
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}
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static void bl808_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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GLB_GPIO_Cfg_Type gpio_cfg;
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gpio_cfg.gpioFun = GPIO_FUN_GPIO;
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gpio_cfg.gpioPin = pin;
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gpio_cfg.drive = 0;
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gpio_cfg.smtCtrl = 1;
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gpio_cfg.outputMode = 0;
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switch (mode)
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{
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case GPIO_OUTPUT_MODE:
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gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
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gpio_cfg.pullType = GPIO_PULL_NONE;
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break;
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case GPIO_OUTPUT_PP_MODE:
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gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
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gpio_cfg.pullType = GPIO_PULL_UP;
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break;
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case GPIO_OUTPUT_PD_MODE:
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gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
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gpio_cfg.pullType = GPIO_PULL_DOWN;
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break;
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case GPIO_INPUT_MODE:
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gpio_cfg.gpioMode = GPIO_MODE_INPUT;
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gpio_cfg.pullType = GPIO_PULL_NONE;
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break;
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case GPIO_INPUT_PP_MODE:
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gpio_cfg.gpioMode = GPIO_MODE_INPUT;
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gpio_cfg.pullType = GPIO_PULL_UP;
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break;
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case GPIO_INPUT_PD_MODE:
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gpio_cfg.gpioMode = GPIO_MODE_INPUT;
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gpio_cfg.pullType = GPIO_PULL_DOWN;
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break;
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case GPIO_HZ_MODE:
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GLB_GPIO_Set_HZ(pin);
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default:
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CPU_Interrupt_Disable(GPIO_INT0_IRQn);
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GLB_GPIO_IntMask(pin, MASK);
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GLB_GPIO_INT_Cfg_Type intCfg;
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intCfg.gpioPin = pin;
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intCfg.intMask = MASK;
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gpio_cfg.gpioMode = GPIO_MODE_INPUT;
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if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE)
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{
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gpio_cfg.pullType = GPIO_PULL_DOWN;
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intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE;
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}
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else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE)
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{
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gpio_cfg.pullType = GPIO_PULL_UP;
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intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE;
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}
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else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE)
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{
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gpio_cfg.pullType = GPIO_PULL_DOWN;
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intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL;
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}
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else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE)
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{
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gpio_cfg.pullType = GPIO_PULL_UP;
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intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL;
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}
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else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE)
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{
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gpio_cfg.pullType = GPIO_PULL_DOWN;
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intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE;
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}
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else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE)
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{
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gpio_cfg.pullType = GPIO_PULL_UP;
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intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE;
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}
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else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE)
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{
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gpio_cfg.pullType = GPIO_PULL_NONE;
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intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE;
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}
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else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE)
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{
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gpio_cfg.pullType = GPIO_PULL_DOWN;
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intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL;
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}
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else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE)
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{
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gpio_cfg.pullType = GPIO_PULL_UP;
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intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL;
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}
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GLB_GPIO_Int_Init(&intCfg);
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break;
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}
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GLB_GPIO_Init(&gpio_cfg);
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}
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static rt_err_t bl808_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t irq_mode, void (*hdr)(void *args), void *args)
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{
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struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private));
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int_cfg->hdr = hdr;
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int_cfg->pin = pin;
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slist_add_tail(&gpio_int_head, &int_cfg->list);
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CPU_Interrupt_Disable(GPIO_INT0_IRQn);
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Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO0_IRQHandler);
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CPU_Interrupt_Enable(GPIO_INT0_IRQn);
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return RT_EOK;
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}
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static rt_err_t bl808_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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if (enabled)
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{
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GLB_GPIO_IntMask(pin, UNMASK);
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}
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else
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{
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GLB_GPIO_IntMask(pin, MASK);
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}
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return RT_EOK;
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}
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const static struct rt_pin_ops _bl808_pin_ops =
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{
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bl808_pin_mode,
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bl808_pin_write,
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bl808_pin_read,
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bl808_pin_attach_irq,
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bl808_pin_irq_enable,
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NULL,
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};
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int rt_hw_pin_init(void)
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{
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return rt_device_pin_register("pin", &_bl808_pin_ops, RT_NULL);
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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/* irq handle */
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void GPIO0_IRQHandler(void)
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{
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rt_interrupt_enter();
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// GPIO_INT0_IRQHandler();
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rt_interrupt_leave();
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}
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#endif /* RT_USING_PIN */
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023/01/5 chushicheng first version
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*
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*/
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#ifndef __DRV_GPIO_H__
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#define __DRV_GPIO_H__
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#include <board.h>
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#include <rtdevice.h>
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#include "drv_device.h"
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#define GPIO_OUTPUT_MODE 0
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#define GPIO_OUTPUT_PP_MODE 1
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#define GPIO_OUTPUT_PD_MODE 2
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#define GPIO_INPUT_MODE 3
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#define GPIO_INPUT_PP_MODE 4
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#define GPIO_INPUT_PD_MODE 5
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#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6
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#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7
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#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8
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#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9
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#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10
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#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11
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#define GPIO_SYNC_RISING_FALLING_TRIGER_INT_MODE 12
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#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 13
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#define GPIO_SYNC_LOW_LEVEL_INT_MODE 14
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#define GPIO_HZ_MODE 15
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int rt_hw_pin_init(void);
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#endif /* __DRV_GPIO_H__ */
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@ -91,6 +91,8 @@ src += Split("""
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""")
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path += [cwd + r'/platform/hosal/bl808_e907_hal']
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path += [cwd + r'/platform/soc/bl808/bl808_e907_std/common/device',
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cwd + r'/platform/soc/bl808/bl808_e907_std/common/list']
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libpath = []
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libs = []
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@ -85,7 +85,7 @@ static int __hw_init(bl_audio_dev_t *p_dev)
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AUIDO_RAMP_RATE_2_FS,
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AUIDO_ZERO_CROSS_RATE_2_FS,
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};
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GLB_Config_AUDIO_PLL(GLB_XTAL_40M, audioPllCfg_451P584M);
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/* ungate audio */
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GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_AUDIO);
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@ -202,7 +202,7 @@ static int __hw_init(bl_audio_dev_t *p_dev)
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static void __audio_lli_init(bl_audio_dev_t *p_dev)
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{
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p_dev->lli_tx_buffer_size = p_dev->lli_tx_buffer_size / 2;
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switch (p_dev->playBitWidth) {
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case AUDIO_BIT_WIDTH_16:
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dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_16BITS;
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@ -230,7 +230,7 @@ static void __audio_lli_init(bl_audio_dev_t *p_dev)
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//private_bflb_platform_printf("BIT WIDTH Is Invaild\r\n");
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break;
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}
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p_dev->lli_tx_list[0].srcDmaAddr = (uint32_t)p_dev->lli_tx_buffer;
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p_dev->lli_tx_list[0].destDmaAddr = AUDIO_TX_FIFO_ADDR;
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p_dev->lli_tx_list[0].nextLLI = (uint32_t)&p_dev->lli_tx_list[1];
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@ -246,7 +246,7 @@ static void __audio_lli_init(bl_audio_dev_t *p_dev)
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if (p_dev->rx_enable) {
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p_dev->lli_rx_buffer_size = p_dev->lli_rx_buffer_size / 2;
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switch (p_dev->playBitWidth) {
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case AUDIO_BIT_WIDTH_16:
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dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_16BITS;
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@ -47,14 +47,14 @@ PtTable_Error_Type PtTable_Update_Entry(const SPI_Flash_Cfg_Type *pFlashCfg,
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if(ptEntry==NULL||ptStuff==NULL){
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return PT_ERROR_PARAMETER;
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}
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ptTable=&ptStuff->ptTable;
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ptEntries=ptStuff->ptEntries;
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if(targetTableID==PT_TABLE_ID_INVALID){
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return PT_ERROR_TABLE_NOT_VALID;
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}
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if(targetTableID==PT_TABLE_ID_0){
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writeAddr=BFLB_PT_TABLE0_ADDRESS;
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}else{
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@ -75,17 +75,17 @@ PtTable_Error_Type PtTable_Update_Entry(const SPI_Flash_Cfg_Type *pFlashCfg,
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return PT_ERROR_ENTRY_UPDATE_FAIL;
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}
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}
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/* Prepare write back to flash */
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/* Update age */
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ptTable->age++;
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ptTable->crc32=BFLB_Soft_CRC32((uint8_t*)ptTable,sizeof(PtTable_Config)-4);
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/* Update entries CRC */
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entriesLen=ptTable->entryCnt*sizeof(PtTable_Entry_Config);
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pCrc32=(uint32_t *)((uint32_t)ptEntries+entriesLen);
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*pCrc32=BFLB_Soft_CRC32((uint8_t *)&ptEntries[0],entriesLen);
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/* Write back to flash */
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/* Erase flash first */
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ret=bl_flash_erase(writeAddr,sizeof(PtTable_Config)+entriesLen+4);
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@ -108,7 +108,7 @@ PtTable_Error_Type PtTable_Get_Active_Entries(PtTable_Stuff_Config *ptStuff,
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PtTable_Entry_Config *ptEntry)
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{
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uint32_t i=0;
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if(ptStuff==NULL||ptEntry==NULL){
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return PT_ERROR_PARAMETER;
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}
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@ -130,16 +130,16 @@ PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptSt
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if(ptStuff==NULL||ptEntry==NULL){
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return PT_ERROR_PARAMETER;
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}
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}
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for (i=0; i < ptStuff->ptTable.entryCnt; i++) {
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if (strlen((char *)ptStuff->ptEntries[i].name) == len &&
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memcmp((char *)ptStuff->ptEntries[i].name,(char *)name,len) == 0){
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memcmp((char *)ptStuff->ptEntries[i].name,(char *)name,len) == 0){
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//BL602_MemCpy_Fast(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config));
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/*FIXME :need fast memory copy*/
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memcpy(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config));
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return PT_ERROR_SUCCESS;
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}
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}
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}
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}
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return PT_ERROR_ENTRY_NOT_FOUND;
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}
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@ -184,8 +184,8 @@ PtTable_ID_Type targetTableID,
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PtTable_Stuff_Config *ptStuff,
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PtTable_Entry_Config *ptEntry);
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PtTable_Error_Type PtTable_Create(const SPI_Flash_Cfg_Type *pFlashCfg,PtTable_ID_Type ptID);
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PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptStuff,
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uint8_t *name,
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PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptStuff,
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uint8_t *name,
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PtTable_Entry_Config *ptEntry);
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/*@} end of group PARTITION_Public_Functions */
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@ -75,9 +75,9 @@ int bl_efuse_ctrl_program_R0(uint32_t index, uint32_t *data, uint32_t len)
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bdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV);
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HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
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EF_Ctrl_Program_Direct_R0(index, data, len);
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GLB_Set_System_CLK_Div(hdiv, bdiv);
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HBN_Set_MCU_Root_CLK_Sel(rtClk);
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@ -96,9 +96,9 @@ int bl_efuse_ctrl_read_R0(uint32_t index, uint32_t *data, uint32_t len)
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HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
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EF_Ctrl_Read_Direct_R0(index, data, len);
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GLB_Set_System_CLK_Div(hdiv, bdiv);
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HBN_Set_MCU_Root_CLK_Sel(rtClk);
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@ -116,8 +116,8 @@ int bl_efuse_read_mac_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
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bdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV);
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HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
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// EF_Ctrl_Read_MAC_Address_Opt(slot, mac, reload);
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// EF_Ctrl_Read_MAC_Address_Opt(slot, mac, reload);
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EF_Ctrl_Read_MAC_Address_Raw(mac);
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GLB_Set_System_CLK_Div(hdiv, bdiv);
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@ -338,12 +338,12 @@ static struct pbuf *low_level_input(struct netif *netif)
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uint16_t max_len, min_len;
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struct pbuf *h = NULL;
|
||||
EMAC_BD_Desc_Type *bd;
|
||||
bd = &thiz->bd[thiz->rxIndexCPU];
|
||||
if(bd->C_S_L & EMAC_BD_FIELD_MSK(RX_E)){
|
||||
bd = &thiz->bd[thiz->rxIndexCPU];
|
||||
if(bd->C_S_L & EMAC_BD_FIELD_MSK(RX_E)){
|
||||
// MSG("RX BD is empty\r\n");
|
||||
h = NULL;
|
||||
} else {
|
||||
emac_get_fram_len(&max_len, &min_len);
|
||||
} else {
|
||||
emac_get_fram_len(&max_len, &min_len);
|
||||
pkt_len = (bd->C_S_L & EMAC_BD_FIELD_MSK(RX_LEN)) >> BD_RX_LEN_POS;
|
||||
//check length
|
||||
if (pkt_len > max_len) {
|
||||
|
|
|
|||
|
|
@ -166,7 +166,7 @@ static void _dump_flash_config()
|
|||
extern uint8_t __boot2_flashCfg_src;
|
||||
|
||||
USER_UNUSED(__boot2_flashCfg_src);
|
||||
|
||||
|
||||
blog_info("======= FlashCfg magiccode @%p=======\r\n", &__boot2_flashCfg_src);
|
||||
blog_info("mid \t\t0x%X\r\n", g_flash_cfg.mid);
|
||||
blog_info("clkDelay \t0x%X\r\n", g_flash_cfg.clkDelay);
|
||||
|
|
|
|||
|
|
@ -116,7 +116,7 @@ void bl_irq_default(void)
|
|||
}
|
||||
|
||||
static void (*handler_list[2][16 + 64])(void) = {
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -139,7 +139,7 @@ void bl_irq_register_with_ctx(int irqnum, void *handler, void *ctx)
|
|||
handler_list[0][irqnum]
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
if (handler == NULL) {
|
||||
blog_error("handler is NULL pointer! \r\n");
|
||||
return;
|
||||
|
|
@ -155,7 +155,7 @@ void bl_irq_register_with_ctx(int irqnum, void *handler, void *ctx)
|
|||
}
|
||||
|
||||
return;
|
||||
|
||||
|
||||
}
|
||||
|
||||
void bl_irq_ctx_get(int irqnum, void **ctx)
|
||||
|
|
@ -177,8 +177,8 @@ void bl_irq_ctx_count_cost(int irqnum, uint64_t cost)
|
|||
struct irq_ctx *ctx;
|
||||
_irq_num_check(irqnum);
|
||||
if(handler_list[0][irqnum] != NULL) {
|
||||
ctx = (struct irq_ctx *)(handler_list[1][irqnum]);
|
||||
ctx->irq_run_time += cost;
|
||||
ctx = (struct irq_ctx *)(handler_list[1][irqnum]);
|
||||
ctx->irq_run_time += cost;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -206,7 +206,7 @@ void bl_irq_unregister(int irqnum, void *handler)
|
|||
#endif
|
||||
}
|
||||
|
||||
void interrupt_entry(uint32_t mcause)
|
||||
void interrupt_entry(uint32_t mcause)
|
||||
{
|
||||
void *handler = NULL;
|
||||
mcause &= 0x7FFFFFF;
|
||||
|
|
@ -342,9 +342,9 @@ extern void misaligned_store_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t m
|
|||
|
||||
#ifdef DBG_RECORD_EXCEP_VAL
|
||||
struct{
|
||||
uint32_t mcause;
|
||||
uint32_t mepc;
|
||||
uint32_t mtval;
|
||||
uint32_t mcause;
|
||||
uint32_t mepc;
|
||||
uint32_t mtval;
|
||||
}rval[4];
|
||||
int rval_idx;
|
||||
#endif /* DBG_RECORD_EXCEP_VAL */
|
||||
|
|
@ -358,24 +358,24 @@ void exception_entry(uint32_t mcause, uint32_t mepc, uint32_t mtval, uintptr_t *
|
|||
rval_idx++;
|
||||
#endif /* DBG_RECORD_EXCEP_VAL */
|
||||
if ((mcause & 0x3ff) == EXCPT_LOAD_MISALIGNED) {
|
||||
//misaligned_load_trap(regs, mcause, mepc);
|
||||
//misaligned_load_trap(regs, mcause, mepc);
|
||||
} else if ((mcause & 0x3ff) == EXCPT_STORE_MISALIGNED){
|
||||
//misaligned_store_trap(regs, mcause, mepc);
|
||||
//misaligned_store_trap(regs, mcause, mepc);
|
||||
}
|
||||
{
|
||||
//registerdump(tasksp);
|
||||
puts("Exception Entry--->>>\r\n");
|
||||
blog_info("mcause %08lx, mepc %08lx, mtval %08lx\r\n",
|
||||
mcause,
|
||||
mepc,
|
||||
mtval
|
||||
);
|
||||
//registerdump(tasksp);
|
||||
puts("Exception Entry--->>>\r\n");
|
||||
blog_info("mcause %08lx, mepc %08lx, mtval %08lx\r\n",
|
||||
mcause,
|
||||
mepc,
|
||||
mtval
|
||||
);
|
||||
__dump_exception_code_str(mcause & 0xFFFF);
|
||||
//backtrace_now_task((int (*)(const char *s))puts, regs);
|
||||
//backtrace_now_task((int (*)(const char *s))puts, regs);
|
||||
while (1) {
|
||||
/*Deap loop now*/
|
||||
/*Deap loop now*/
|
||||
#ifdef SYS_ENABLE_COREDUMP
|
||||
/* For stack check */
|
||||
/* For stack check */
|
||||
extern uintptr_t _sp_main, _sp_base;
|
||||
|
||||
/* XXX change sp to irq stack base */
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ static void get_mm_cpu_pll_clk(uint32_t reg_val)
|
|||
static void dump_mm_cpu_clk(void)
|
||||
{
|
||||
uint32_t tmpVal = 0, cpu_root_clk = 0;
|
||||
|
||||
|
||||
tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU);
|
||||
cpu_root_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL);
|
||||
switch (cpu_root_clk) {
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ static int pm_env_init(void)
|
|||
INIT_UTILS_DLIST_HEAD(&(gp_pm_env->pm_list)[i]);
|
||||
}
|
||||
|
||||
gp_pm_env->state = PM_STATE_INITED;
|
||||
gp_pm_env->state = PM_STATE_INITED;
|
||||
|
||||
///for debug
|
||||
gp_pm_env->bt_capacity.cap = 0xffff;
|
||||
|
|
@ -136,13 +136,13 @@ static int pm_deinit(void)
|
|||
|
||||
vPortFree(gp_pm_env->pm_list);
|
||||
gp_pm_env->pm_list = NULL;
|
||||
|
||||
|
||||
vSemaphoreDelete(gp_pm_env->pm_mux);
|
||||
gp_pm_env->pm_mux = NULL;
|
||||
|
||||
|
||||
vPortFree(gp_pm_env);
|
||||
gp_pm_env = NULL;
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -180,7 +180,7 @@ static void pm_node_add(struct pm_node *pnode, utils_dlist_t *queue)
|
|||
utils_dlist_add(&(pnode->dlist_item), pre_save);
|
||||
xSemaphoreGive(gp_pm_env->pm_mux);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pre_save = &(node->dlist_item);
|
||||
}
|
||||
|
|
@ -225,7 +225,7 @@ static int pm_pmlist_traverse(enum PM_EVEMT event, utils_dlist_t *queue, uint32_
|
|||
}
|
||||
|
||||
utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) {
|
||||
if ((node->enable) && (code == node->code) && (gp_pm_env->wlan_capacity.cap & node->cap_bit) &&
|
||||
if ((node->enable) && (code == node->code) && (gp_pm_env->wlan_capacity.cap & node->cap_bit) &&
|
||||
(gp_pm_env->bt_capacity.cap & node->cap_bit)) {
|
||||
|
||||
if (pm_state_exec_func_check(event, code)) {
|
||||
|
|
@ -286,8 +286,8 @@ static int pm_internal_process_event(enum PM_EVEMT event, uint32_t code)
|
|||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -296,7 +296,7 @@ int pm_post_event(enum PM_EVEMT event, uint32_t code, uint32_t *retval)
|
|||
if (!gp_pm_env) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
pm_pmlist_traverse(event, &(gp_pm_env->pm_list)[event], code, retval);
|
||||
pm_internal_process_event(event, code);
|
||||
|
||||
|
|
@ -322,9 +322,9 @@ int bl_pm_event_register(enum PM_EVEMT event, uint32_t code, uint32_t cap_bit, u
|
|||
p_node->ops = ops;
|
||||
p_node->ctx = arg;
|
||||
p_node->enable = enable;
|
||||
|
||||
|
||||
pm_node_add(p_node, &(gp_pm_env->pm_list)[event]);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -344,7 +344,7 @@ int bl_pm_event_switch(enum PM_EVEMT event, uint32_t code, enum PM_EVENT_ABLE en
|
|||
utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) {
|
||||
if (code == node->code) {
|
||||
node->enable = enable;
|
||||
|
||||
|
||||
ret = 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -396,8 +396,8 @@ int bl_pm_state_run(void)
|
|||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -467,7 +467,7 @@ int bl_pm_capacity_set(enum PM_LEVEL level)
|
|||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pm_set_wlan_capacity(capacity);
|
||||
|
||||
|
|
|
|||
|
|
@ -261,7 +261,7 @@ void SDH_CMDTransferFinished_CallBack(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type
|
|||
*******************************************************************************/
|
||||
static void SDH_INT_Init(void)
|
||||
{
|
||||
System_NVIC_SetPriority(SDH_SDCARD_IRQn, 7, 1);
|
||||
System_NVIC_SetPriority(SDH_SDCARD_IRQn, 7, 1);
|
||||
CPU_Interrupt_Enable(SDH_SDCARD_IRQn);
|
||||
|
||||
SDH_EnableIntStatus(SDH_INT_ALL);
|
||||
|
|
@ -1272,10 +1272,10 @@ status_t SDH_Init(uint32_t bus_wide, sd_card_t *pOutCardInfo)
|
|||
/* gpio init */
|
||||
SDH_GPIO_Init(bus_wide);
|
||||
|
||||
/* config sdh clock */
|
||||
GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SDH);
|
||||
/* config sdh clock */
|
||||
GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SDH);
|
||||
GLB_Set_SDH_CLK(1, GLB_SDH_CLK_WIFIPLL_96M, 0);
|
||||
SDH_ClockSet(400000, 96000000, 96000000);
|
||||
SDH_ClockSet(400000, 96000000, 96000000);
|
||||
|
||||
#if SDIO_SDCARD_INT_MODE
|
||||
SDH_INT_Init();
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ int bl_sha_finish(bl_sha_ctx_t *ctx, uint8_t *hash);
|
|||
int bl_sec_ccm_encrypt_and_tag(const uint8_t *key, unsigned int key_bytelen, size_t length, const unsigned char *iv, size_t iv_len, const unsigned char *add, size_t add_len,
|
||||
const unsigned char *input, unsigned char *output, unsigned char *tag, size_t tag_len);
|
||||
int bl_sec_ccm_auth_decrypt(const uint8_t *key, unsigned int key_bytelen, size_t length,const unsigned char *iv, size_t iv_len, const unsigned char *add,
|
||||
size_t add_len, const unsigned char *input, unsigned char *output, const unsigned char *tag, size_t tag_len);
|
||||
size_t add_len, const unsigned char *input, unsigned char *output, const unsigned char *tag, size_t tag_len);
|
||||
int bl_sec_aes_ecb_encrypt(const uint8_t *key, unsigned int key_bytelen, size_t length, const unsigned char *input, unsigned char *output);
|
||||
int bl_sec_aes_ecb_decrypt(const uint8_t *key, unsigned int key_bytelen, size_t length, const unsigned char *input, unsigned char *output);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -125,10 +125,10 @@ void sha256_test_case0(void)
|
|||
.linkCfg.shaMsgLen = 1,
|
||||
.linkCfg.shaSrcAddr = 0x50020000,
|
||||
};
|
||||
static const uint8_t sha256_test_result[] =
|
||||
static const uint8_t sha256_test_result[] =
|
||||
{
|
||||
0x31, 0x38, 0xbb, 0x9b, 0xc7, 0x8d, 0xf2, 0x7c, 0x47, 0x3e, 0xcf, 0xd1, 0x41, 0x0f, 0x7b, 0xd4,
|
||||
0x5e, 0xba, 0xc1, 0xf5, 0x9c, 0xf3, 0xff, 0x9c, 0xfe, 0x4d, 0xb7, 0x7a, 0xab, 0x7a, 0xed, 0xd3,
|
||||
0x5e, 0xba, 0xc1, 0xf5, 0x9c, 0xf3, 0xff, 0x9c, 0xfe, 0x4d, 0xb7, 0x7a, 0xab, 0x7a, 0xed, 0xd3,
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -213,7 +213,7 @@ int bl_sys_early_init(void)
|
|||
|
||||
extern void freertos_risc_v_trap_handler(void); //freertos_riscv_ram/portable/GCC/RISC-V/portASM.S
|
||||
write_csr(mtvec, &freertos_risc_v_trap_handler);
|
||||
|
||||
|
||||
/* reset here for use wtd first then init hwtimer later*/
|
||||
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_TMR);
|
||||
/*debuger may NOT ready don't print anything*/
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ int bl_wifi_power_table_set(bl_tx_pwr_tbl_t* tx_pwr_tbl)
|
|||
}
|
||||
#endif
|
||||
|
||||
int bl_wifi_ap_info_set(uint8_t* ssid, uint8_t ssid_len,
|
||||
int bl_wifi_ap_info_set(uint8_t* ssid, uint8_t ssid_len,
|
||||
uint8_t* psk, uint8_t psk_len,
|
||||
uint8_t chan)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ int bl_wifi_sta_mac_addr_set(uint8_t mac[6]);
|
|||
int bl_wifi_ap_mac_addr_set(uint8_t mac[6]);
|
||||
int bl_wifi_mac_addr_set(uint8_t mac[6]);
|
||||
int bl_wifi_country_code_set(uint8_t country_code);
|
||||
int bl_wifi_ap_info_set(uint8_t* ssid, uint8_t ssid_len,
|
||||
int bl_wifi_ap_info_set(uint8_t* ssid, uint8_t ssid_len,
|
||||
uint8_t* psk, uint8_t psk_len,
|
||||
uint8_t chan);
|
||||
int bl_wifi_mac_addr_get(uint8_t mac[6]);
|
||||
|
|
|
|||
|
|
@ -27,4 +27,4 @@
|
|||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include "phy_8720.c"
|
||||
#include "phy_8720.c"
|
||||
|
|
|
|||
|
|
@ -337,7 +337,7 @@ static void update_xtal_config_rftv(uint32_t tlv_addr)
|
|||
uint8_t buffer[20] = {0};
|
||||
uint32_t capcode[5] = {0};
|
||||
char xtal_mode[3] = {0};
|
||||
|
||||
|
||||
if (rftlv_get(tlv_addr, RFTLV_API_TYPE_XTAL_MODE, 3, xtal_mode) > 0) {
|
||||
xtal_mode[sizeof(xtal_mode) - 1] = '\0';
|
||||
blog_info("xtal_mode is %s\r\n", xtal_mode);
|
||||
|
|
@ -505,7 +505,7 @@ break_scan:
|
|||
log_buf_int8(poweroffset, sizeof(poweroffset));
|
||||
#ifdef CFG_BLE_ENABLE
|
||||
extern void ble_rf_set_pwr_offset_table(int8_t *poweroffset_table);
|
||||
ble_rf_set_pwr_offset_table(poweroffset);
|
||||
ble_rf_set_pwr_offset_table(poweroffset);
|
||||
#endif
|
||||
//zys phy_powroffset_set(poweroffset);
|
||||
}
|
||||
|
|
@ -608,7 +608,7 @@ break_scan:
|
|||
log_buf_int8(poweroffset, sizeof(poweroffset));
|
||||
#ifdef CFG_BLE_ENABLE
|
||||
extern void ble_rf_set_pwr_offset_table(int8_t *poweroffset_table);
|
||||
ble_rf_set_pwr_offset_table(poweroffset);
|
||||
ble_rf_set_pwr_offset_table(poweroffset);
|
||||
#endif
|
||||
//zys phy_powroffset_set(poweroffset);
|
||||
}
|
||||
|
|
@ -671,7 +671,7 @@ static int update_ap_field(const void *fdt, int wifi_offset, const char *name)
|
|||
int countindex = 0, lentmp = 0;
|
||||
const char *result = 0;
|
||||
const uint8_t *addr_prop = 0;
|
||||
|
||||
|
||||
/* set ssid pwd */
|
||||
uint8_t ap_ssid[32];
|
||||
uint8_t ap_ssid_len = 0;
|
||||
|
|
@ -764,8 +764,8 @@ static int update_rf_temp_field(const void *fdt, int wifi_offset, const char *na
|
|||
}
|
||||
|
||||
addr_prop = fdt_getprop(fdt, offset1, "Tchannels", &lentmp);
|
||||
if (lentmp == TCAL_PARA_CHANNELS*4) {
|
||||
memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4);
|
||||
if (lentmp == TCAL_PARA_CHANNELS*4) {
|
||||
memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4);
|
||||
blog_info_user(dts, "Tchannels:");
|
||||
for (i = 0; i < TCAL_PARA_CHANNELS; i++){
|
||||
tcal_param_tmp.Tchannels[i]=fdt32_to_cpu(tmp[i]);
|
||||
|
|
@ -778,8 +778,8 @@ static int update_rf_temp_field(const void *fdt, int wifi_offset, const char *na
|
|||
}
|
||||
|
||||
addr_prop = fdt_getprop(fdt, offset1, "Tchannel_os", &lentmp);
|
||||
if (lentmp == TCAL_PARA_CHANNELS*4) {
|
||||
memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4);
|
||||
if (lentmp == TCAL_PARA_CHANNELS*4) {
|
||||
memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4);
|
||||
blog_info_user(dts, "Tchannel_os:");
|
||||
for (i = 0; i < TCAL_PARA_CHANNELS; i++){
|
||||
tcal_param_tmp.Tchannel_os[i]=fdt32_to_cpu(tmp[i]);
|
||||
|
|
@ -792,8 +792,8 @@ static int update_rf_temp_field(const void *fdt, int wifi_offset, const char *na
|
|||
}
|
||||
|
||||
addr_prop = fdt_getprop(fdt, offset1, "Tchannel_os_low", &lentmp);
|
||||
if (lentmp == TCAL_PARA_CHANNELS*4) {
|
||||
memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4);
|
||||
if (lentmp == TCAL_PARA_CHANNELS*4) {
|
||||
memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4);
|
||||
blog_info_user(dts, "Tchannel_os_low:");
|
||||
for (i = 0; i < TCAL_PARA_CHANNELS; i++){
|
||||
tcal_param_tmp.Tchannel_os_low[i]=fdt32_to_cpu(tmp[i]);
|
||||
|
|
@ -828,7 +828,7 @@ static int hal_board_load_rftv_info(uint32_t rftlv_addr)
|
|||
int8_t pwr_table[24];
|
||||
|
||||
int pwr_table_ble = 0;
|
||||
|
||||
|
||||
if (!rftlv_valid(rftlv_addr)) {
|
||||
return -2;
|
||||
}
|
||||
|
|
@ -910,7 +910,7 @@ static int hal_board_load_rftv_info(uint32_t rftlv_addr)
|
|||
#endif
|
||||
|
||||
vPortFree(p_buffer);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ uint32_t hal_boot2_get_flash_addr(void)
|
|||
{
|
||||
extern uint8_t __boot2_flashCfg_src;
|
||||
|
||||
return (uint32_t)(&__boot2_flashCfg_src +
|
||||
return (uint32_t)(&__boot2_flashCfg_src +
|
||||
(sizeof(boot2_partition_table.table.ptEntries[0]) * boot2_partition_table.table.ptTable.entryCnt));
|
||||
}
|
||||
|
||||
|
|
@ -247,12 +247,12 @@ uint8_t hal_boot2_get_active_partition(void)
|
|||
return boot2_partition_table.partition_active_idx;
|
||||
}
|
||||
|
||||
int hal_boot2_get_active_entries_byname(uint8_t *name, HALPartition_Entry_Config *ptEntry_hal)
|
||||
int hal_boot2_get_active_entries_byname(uint8_t *name, HALPartition_Entry_Config *ptEntry_hal)
|
||||
{
|
||||
PtTable_Entry_Config *ptEntry = (PtTable_Entry_Config*)ptEntry_hal;
|
||||
if (PtTable_Get_Active_Entries_By_Name(&boot2_partition_table.table, name, ptEntry)) {
|
||||
return -1;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -286,7 +286,7 @@ int hal_boot2_init(void)
|
|||
}
|
||||
|
||||
#if 0
|
||||
#define PT_OTA_TYPE_NAME "FW"
|
||||
#define PT_OTA_TYPE_NAME "FW"
|
||||
#define PT_MEDIA_TYPE_NAME "mfg"
|
||||
void hal_update_mfg_ptable(void)
|
||||
{
|
||||
|
|
@ -298,14 +298,14 @@ void hal_update_mfg_ptable(void)
|
|||
if (0 == hal_boot2_get_active_entries_byname((uint8_t *)PT_OTA_TYPE_NAME, (HALPartition_Entry_Config *)(&ptEntry_fw))) { // ota
|
||||
if (0 == hal_boot2_get_active_entries_byname((uint8_t *)PT_MEDIA_TYPE_NAME, (HALPartition_Entry_Config *)(&ptEntry_media))) { // media
|
||||
if (ptEntry_fw.Address[1] == ptEntry_media.Address[0]) {
|
||||
|
||||
|
||||
memset(ptEntry_media.name, 0, sizeof(ptEntry_media.name));
|
||||
PtTable_Update_Entry(NULL, !boot2_partition_table.partition_active_idx, &boot2_partition_table.table, &ptEntry_media);
|
||||
|
||||
|
||||
printf("===== update mfg partition =====\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
printf("====================\r\n");
|
||||
printf("update mfg table.\r\n");
|
||||
|
|
|
|||
|
|
@ -60,9 +60,9 @@ typedef enum {
|
|||
/**
|
||||
* @brief Error type definition
|
||||
*/
|
||||
typedef enum
|
||||
typedef enum
|
||||
{
|
||||
HAL_SUCCESS = 0,
|
||||
HAL_SUCCESS = 0,
|
||||
HAL_ERROR = 1,
|
||||
} HAL_Err_Type;
|
||||
|
||||
|
|
|
|||
|
|
@ -332,9 +332,9 @@ void emac_irq_process(void)
|
|||
EMAC_ID_Type emacId = EMAC_USED_ID;
|
||||
uint32_t tmpVal;
|
||||
uint32_t EMACx = emacAddr[emacId];
|
||||
|
||||
|
||||
tmpVal = BL_RD_REG(EMACx,EMAC_INT_MASK);
|
||||
|
||||
|
||||
if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_TX_DONE) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_TXB_M)) {
|
||||
EMAC_ClrIntStatus(emacId,EMAC_INT_TX_DONE);
|
||||
EMAC_IntMask(emacId, EMAC_INT_TX_DONE, MASK);
|
||||
|
|
@ -499,7 +499,7 @@ int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in)
|
|||
}
|
||||
|
||||
/* following two lines is for cache test since tmpbuf is in cache range */
|
||||
//ARCH_MemCpy_Fast(tmpbuf, data_in, len);
|
||||
//ARCH_MemCpy_Fast(tmpbuf, data_in, len);
|
||||
//DMADesc->Buffer = (uint32_t)tmpbuf;
|
||||
#ifdef EMAC_DO_FLUSH_DATA
|
||||
if(L1C_Is_DCache_Range((uintptr_t)DMADesc->Buffer)){
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ static void uart_dev_setdef(uart_dev_t **pdev, uint8_t id)
|
|||
|
||||
(*pdev)->port = id;
|
||||
(*pdev)->read_block_flag = UART_READ_CFG_NOBLOCK;
|
||||
|
||||
|
||||
(*pdev)->config.baud_rate = 2000000;
|
||||
(*pdev)->config.data_width = DATA_WIDTH_8BIT;
|
||||
(*pdev)->config.parity = NO_PARITY;
|
||||
|
|
@ -231,7 +231,7 @@ int32_t hal_uart_send(uart_dev_t *uart, const void *data, uint32_t size, uint32_
|
|||
|
||||
int32_t hal_uart_send_flush(uart_dev_t *uart, uint32_t timeout)
|
||||
{
|
||||
bl_uart_flush(uart->port);
|
||||
bl_uart_flush(uart->port);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ static int adc_get_channel_by_gpio(GLB_GPIO_Type pin)
|
|||
case GLB_GPIO_PIN_40:
|
||||
channel = 5;
|
||||
break;
|
||||
|
||||
|
||||
default :
|
||||
channel = -1;
|
||||
break;
|
||||
|
|
@ -170,7 +170,7 @@ static void adc_freq_init(hosal_adc_sample_mode_t mode, uint32_t freq)
|
|||
}
|
||||
|
||||
if (div > 64) {
|
||||
div = 64;
|
||||
div = 64;
|
||||
}
|
||||
|
||||
/*adc clk can not more than 2M*/
|
||||
|
|
@ -201,7 +201,7 @@ static void adc_dma_lli_init(DMA_LLI_Ctrl_Type *pstlli, uint32_t *buf, uint32_t
|
|||
|
||||
pstlli[0].srcDmaAddr = GPIP_BASE+GPIP_GPADC_DMA_RDATA_OFFSET;
|
||||
pstlli[0].destDmaAddr = (uint32_t)&buf[0];
|
||||
pstlli[0].nextLLI = (uint32_t)&pstlli[1];
|
||||
pstlli[0].nextLLI = (uint32_t)&pstlli[1];
|
||||
pstlli[0].dmaCtrl= dma_ctrl_reg;
|
||||
|
||||
pstlli[1].srcDmaAddr = GPIP_BASE+GPIP_GPADC_DMA_RDATA_OFFSET;
|
||||
|
|
@ -219,7 +219,7 @@ static int adc_dma_init(hosal_adc_dev_t *adc, uint32_t data_num)
|
|||
.srcPeriph = DMA_REQ_GPADC_RX,
|
||||
.dstPeriph = DMA_REQ_NONE,
|
||||
};
|
||||
|
||||
|
||||
hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv;
|
||||
|
||||
if (data_num < 1) {
|
||||
|
|
@ -262,7 +262,7 @@ static void adc_init(hosal_adc_dev_t *adc)
|
|||
{
|
||||
int i, chan;
|
||||
uint8_t channel_table[ADC_CHANNEL_MAX] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};
|
||||
|
||||
|
||||
hosal_adc_sample_mode_t mode = adc->config.mode;
|
||||
GLB_GPIO_Type pin = adc->config.pin;
|
||||
|
||||
|
|
@ -301,7 +301,7 @@ static void adc_init(hosal_adc_dev_t *adc)
|
|||
ADC_Reset();
|
||||
|
||||
ADC_Init(&adccfg);
|
||||
|
||||
|
||||
if (mode == HOSAL_ADC_ONE_SHOT) {
|
||||
for (i = 0; i < ADC_CHANNEL_MAX; i++) {
|
||||
pos_chlist_single[i] = channel_table[i];;
|
||||
|
|
@ -309,7 +309,7 @@ static void adc_init(hosal_adc_dev_t *adc)
|
|||
}
|
||||
|
||||
ADC_Scan_Channel_Config(pos_chlist_single, neg_chlist_single, ADC_CHANNEL_MAX, ENABLE);
|
||||
}
|
||||
}
|
||||
else {
|
||||
chan = adc_get_channel_by_gpio(pin);
|
||||
ADC_Channel_Config(chan, ADC_CHAN_GND, ENABLE);
|
||||
|
|
@ -340,7 +340,7 @@ static int adc_parse_data(uint32_t *parr, int data_size, int channel)
|
|||
|
||||
return data;
|
||||
}
|
||||
}
|
||||
}
|
||||
blog_error("error!\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -366,7 +366,7 @@ int hosal_adc_init(hosal_adc_dev_t *adc)
|
|||
blog_error("pin is error!\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
pstctx = (hosal_adc_ctx_t *)pvPortMalloc(sizeof(hosal_adc_ctx_t));
|
||||
if (NULL == pstctx) {
|
||||
blog_error("not have enough memory!\r\n");
|
||||
|
|
@ -381,7 +381,7 @@ int hosal_adc_init(hosal_adc_dev_t *adc)
|
|||
blog_error("illegal freq. for mode0, freq 20HZ ~ 1250HZ \r\n");
|
||||
return -1;
|
||||
}
|
||||
/* init gpio */
|
||||
/* init gpio */
|
||||
GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, &pin, 1);
|
||||
|
||||
/* init freq */
|
||||
|
|
@ -393,7 +393,7 @@ int hosal_adc_init(hosal_adc_dev_t *adc)
|
|||
blog_error("not support continue mode!\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
pgdevice = adc;
|
||||
|
||||
return 0;
|
||||
|
|
@ -450,22 +450,22 @@ int hosal_adc_value_get(hosal_adc_dev_t *adc, uint32_t channel, uint32_t timeout
|
|||
{
|
||||
int val = -1;
|
||||
hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv;
|
||||
|
||||
|
||||
if (NULL == adc) {
|
||||
blog_error("parameter is error!\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
if (channel > 11) {
|
||||
blog_error("channel is error!\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
if (((1 << channel) & pstctx->chan_init_table) == 0) {
|
||||
blog_error("channel = %d not init as adc \r\n", channel);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
if (pstctx->channel_data == NULL) {
|
||||
blog_error("adc sampling not finish. \r\n");
|
||||
return -1;
|
||||
|
|
@ -479,13 +479,13 @@ int hosal_adc_value_get(hosal_adc_dev_t *adc, uint32_t channel, uint32_t timeout
|
|||
}
|
||||
vTaskDelay(1);
|
||||
}
|
||||
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
int hosal_adc_tsen_value_get(hosal_adc_dev_t *adc)
|
||||
{
|
||||
blog_error("not support now!\r\n");
|
||||
blog_error("not support now!\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
@ -503,7 +503,7 @@ int hosal_adc_start(hosal_adc_dev_t *adc, void *data, uint32_t size)
|
|||
|
||||
int hosal_adc_stop(hosal_adc_dev_t *adc)
|
||||
{
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hosal_adc_finalize(hosal_adc_dev_t *adc)
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ static void __dma_irq_process(void *p_arg)
|
|||
pfn = gp_hosal_dma_dev->used_chan[ch].callback;
|
||||
parg = gp_hosal_dma_dev->used_chan[ch].p_arg;
|
||||
if (pfn) {
|
||||
pfn(parg, HOSAL_DMA_INT_TRANS_COMPLETE);
|
||||
pfn(parg, HOSAL_DMA_INT_TRANS_COMPLETE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -94,7 +94,7 @@ static void __dma_irq_process(void *p_arg)
|
|||
pfn = gp_hosal_dma_dev->used_chan[ch].callback;
|
||||
parg = gp_hosal_dma_dev->used_chan[ch].p_arg;
|
||||
if (pfn) {
|
||||
pfn(parg, HOSAL_DMA_INT_TRANS_ERROR);
|
||||
pfn(parg, HOSAL_DMA_INT_TRANS_ERROR);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -144,16 +144,16 @@ static void hosal_spi_gpio_init(hosal_spi_dev_t *arg)
|
|||
GLB_GPIO_Func_Init(GPIO_FUN_SPI0, gpiopins, sizeof(gpiopins)/sizeof(gpiopins[0]));
|
||||
|
||||
if (arg->config.mode == 0) {
|
||||
if(arg->port == SPI0_ID) {
|
||||
GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER);
|
||||
} else {
|
||||
GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER);
|
||||
if(arg->port == SPI0_ID) {
|
||||
GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER);
|
||||
} else {
|
||||
GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER);
|
||||
}
|
||||
} else {
|
||||
if(arg->port == SPI0_ID) {
|
||||
GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_SLAVE);
|
||||
} else {
|
||||
GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_SLAVE);
|
||||
if(arg->port == SPI0_ID) {
|
||||
GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_SLAVE);
|
||||
} else {
|
||||
GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_SLAVE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -103,11 +103,11 @@ static void __uart_rx_dma_irq(void *p_arg, uint32_t flag)
|
|||
hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg;
|
||||
|
||||
if (flag != HOSAL_DMA_INT_TRANS_COMPLETE) {
|
||||
blog_error("DMA RX TRANS ERROR\r\n");
|
||||
blog_error("DMA RX TRANS ERROR\r\n");
|
||||
}
|
||||
|
||||
if (uart->rxdma_cb) {
|
||||
uart->rxdma_cb(uart->p_rxdma_arg);
|
||||
uart->rxdma_cb(uart->p_rxdma_arg);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -116,34 +116,34 @@ static void __uart_tx_dma_irq(void *p_arg, uint32_t flag)
|
|||
hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg;
|
||||
|
||||
if (flag != HOSAL_DMA_INT_TRANS_COMPLETE) {
|
||||
blog_error("DMA TX TRANS ERROR\r\n");
|
||||
blog_error("DMA TX TRANS ERROR\r\n");
|
||||
}
|
||||
|
||||
if (uart->txdma_cb) {
|
||||
uart->txdma_cb(uart->p_txdma_arg);
|
||||
uart->txdma_cb(uart->p_txdma_arg);
|
||||
}
|
||||
}
|
||||
|
||||
static int __uart_dma_txcfg(hosal_uart_dev_t *uart, hosal_uart_dma_cfg_t *dma_cfg)
|
||||
{
|
||||
if (dma_cfg->dma_buf == NULL || dma_cfg->dma_buf_size == 0) {
|
||||
return -1;
|
||||
}
|
||||
DMA_Channel_Cfg_Type txchCfg = {
|
||||
(uint32_t)dma_cfg->dma_buf,
|
||||
g_uart_addr[uart->port] + UART_FIFO_WDATA_OFFSET,
|
||||
dma_cfg->dma_buf_size,
|
||||
DMA_TRNS_M2P,
|
||||
DMA_CH0,
|
||||
DMA_TRNS_WIDTH_8BITS,
|
||||
DMA_TRNS_WIDTH_8BITS,
|
||||
DMA_BURST_SIZE_4,
|
||||
DMA_BURST_SIZE_4,
|
||||
DMA_MINC_ENABLE,
|
||||
DMA_PINC_DISABLE,
|
||||
DMA_REQ_NONE,
|
||||
DMA_REQ_UART0_TX,
|
||||
};
|
||||
if (dma_cfg->dma_buf == NULL || dma_cfg->dma_buf_size == 0) {
|
||||
return -1;
|
||||
}
|
||||
DMA_Channel_Cfg_Type txchCfg = {
|
||||
(uint32_t)dma_cfg->dma_buf,
|
||||
g_uart_addr[uart->port] + UART_FIFO_WDATA_OFFSET,
|
||||
dma_cfg->dma_buf_size,
|
||||
DMA_TRNS_M2P,
|
||||
DMA_CH0,
|
||||
DMA_TRNS_WIDTH_8BITS,
|
||||
DMA_TRNS_WIDTH_8BITS,
|
||||
DMA_BURST_SIZE_4,
|
||||
DMA_BURST_SIZE_4,
|
||||
DMA_MINC_ENABLE,
|
||||
DMA_PINC_DISABLE,
|
||||
DMA_REQ_NONE,
|
||||
DMA_REQ_UART0_TX,
|
||||
};
|
||||
UART_FifoCfg_Type fifoCfg =
|
||||
{
|
||||
.txFifoDmaThreshold = 0x10,
|
||||
|
|
@ -153,52 +153,52 @@ static int __uart_dma_txcfg(hosal_uart_dev_t *uart, hosal_uart_dma_cfg_t *dma_cf
|
|||
};
|
||||
|
||||
if (uart->dma_tx_chan >= 0) {
|
||||
DMA_Channel_Update_SrcMemcfg(uart->dma_tx_chan,
|
||||
(uint32_t)dma_cfg->dma_buf, dma_cfg->dma_buf_size);
|
||||
return 0;
|
||||
DMA_Channel_Update_SrcMemcfg(uart->dma_tx_chan,
|
||||
(uint32_t)dma_cfg->dma_buf, dma_cfg->dma_buf_size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
uart->dma_tx_chan = hosal_dma_chan_request(0);
|
||||
if (uart->dma_tx_chan < 0) {
|
||||
blog_error("dma_tx_chan request failed !\r\n");
|
||||
return -1;
|
||||
}
|
||||
uart->dma_tx_chan = hosal_dma_chan_request(0);
|
||||
if (uart->dma_tx_chan < 0) {
|
||||
blog_error("dma_tx_chan request failed !\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
hosal_dma_chan_stop(uart->dma_tx_chan);
|
||||
hosal_dma_chan_stop(uart->dma_tx_chan);
|
||||
|
||||
/* FIFO Config*/
|
||||
fifoCfg.rxFifoDmaEnable = (uart->dma_rx_chan < 0) ? DISABLE : ENABLE;
|
||||
fifoCfg.rxFifoDmaEnable = (uart->dma_rx_chan < 0) ? DISABLE : ENABLE;
|
||||
UART_FifoConfig(uart->port, &fifoCfg);
|
||||
|
||||
txchCfg.ch = uart->dma_tx_chan;
|
||||
txchCfg.dstPeriph = (uart->port == 0) ? DMA_REQ_UART0_TX : DMA_REQ_UART1_TX;
|
||||
DMA_Channel_Init(&txchCfg);
|
||||
hosal_dma_irq_callback_set(uart->dma_tx_chan, __uart_tx_dma_irq, (void *)uart);
|
||||
txchCfg.ch = uart->dma_tx_chan;
|
||||
txchCfg.dstPeriph = (uart->port == 0) ? DMA_REQ_UART0_TX : DMA_REQ_UART1_TX;
|
||||
DMA_Channel_Init(&txchCfg);
|
||||
hosal_dma_irq_callback_set(uart->dma_tx_chan, __uart_tx_dma_irq, (void *)uart);
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __uart_dma_rxcfg(hosal_uart_dev_t *uart, hosal_uart_dma_cfg_t *dma_cfg)
|
||||
{
|
||||
if (dma_cfg->dma_buf == NULL || dma_cfg->dma_buf_size == 0) {
|
||||
return -1;
|
||||
}
|
||||
if (dma_cfg->dma_buf == NULL || dma_cfg->dma_buf_size == 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
DMA_Channel_Cfg_Type rxchCfg = {
|
||||
g_uart_addr[uart->port] + UART_FIFO_RDATA_OFFSET,
|
||||
(uint32_t)dma_cfg->dma_buf,
|
||||
dma_cfg->dma_buf_size,
|
||||
DMA_TRNS_P2M,
|
||||
DMA_CH0,
|
||||
DMA_TRNS_WIDTH_8BITS,
|
||||
DMA_TRNS_WIDTH_8BITS,
|
||||
DMA_BURST_SIZE_16,
|
||||
DMA_BURST_SIZE_16,
|
||||
DMA_PINC_DISABLE,
|
||||
DMA_MINC_ENABLE,
|
||||
DMA_REQ_UART0_RX,
|
||||
DMA_REQ_NONE,
|
||||
};
|
||||
DMA_Channel_Cfg_Type rxchCfg = {
|
||||
g_uart_addr[uart->port] + UART_FIFO_RDATA_OFFSET,
|
||||
(uint32_t)dma_cfg->dma_buf,
|
||||
dma_cfg->dma_buf_size,
|
||||
DMA_TRNS_P2M,
|
||||
DMA_CH0,
|
||||
DMA_TRNS_WIDTH_8BITS,
|
||||
DMA_TRNS_WIDTH_8BITS,
|
||||
DMA_BURST_SIZE_16,
|
||||
DMA_BURST_SIZE_16,
|
||||
DMA_PINC_DISABLE,
|
||||
DMA_MINC_ENABLE,
|
||||
DMA_REQ_UART0_RX,
|
||||
DMA_REQ_NONE,
|
||||
};
|
||||
UART_FifoCfg_Type fifoCfg =
|
||||
{
|
||||
.txFifoDmaThreshold = 0x10,
|
||||
|
|
@ -208,30 +208,30 @@ static int __uart_dma_rxcfg(hosal_uart_dev_t *uart, hosal_uart_dma_cfg_t *dma_cf
|
|||
};
|
||||
|
||||
if (uart->dma_rx_chan >= 0) {
|
||||
DMA_Channel_Update_DstMemcfg(uart->dma_rx_chan,
|
||||
(uint32_t)dma_cfg->dma_buf, dma_cfg->dma_buf_size);
|
||||
return 0;
|
||||
DMA_Channel_Update_DstMemcfg(uart->dma_rx_chan,
|
||||
(uint32_t)dma_cfg->dma_buf, dma_cfg->dma_buf_size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
uart->dma_rx_chan = hosal_dma_chan_request(0);
|
||||
if (uart->dma_rx_chan < 0) {
|
||||
blog_error("dma_rx_chan request failed !\r\n");
|
||||
return -1;
|
||||
}
|
||||
uart->dma_rx_chan = hosal_dma_chan_request(0);
|
||||
if (uart->dma_rx_chan < 0) {
|
||||
blog_error("dma_rx_chan request failed !\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
hosal_dma_chan_stop(uart->dma_rx_chan);
|
||||
hosal_dma_chan_stop(uart->dma_rx_chan);
|
||||
|
||||
/* FIFO Config*/
|
||||
fifoCfg.txFifoDmaEnable = (uart->dma_tx_chan < 0) ? DISABLE : ENABLE;
|
||||
fifoCfg.txFifoDmaEnable = (uart->dma_tx_chan < 0) ? DISABLE : ENABLE;
|
||||
UART_FifoConfig(uart->port, &fifoCfg);
|
||||
|
||||
rxchCfg.ch = uart->dma_rx_chan;
|
||||
rxchCfg.srcPeriph = (uart->port == 0) ? DMA_REQ_UART0_RX : DMA_REQ_UART1_RX;
|
||||
rxchCfg.ch = uart->dma_rx_chan;
|
||||
rxchCfg.srcPeriph = (uart->port == 0) ? DMA_REQ_UART0_RX : DMA_REQ_UART1_RX;
|
||||
|
||||
DMA_Channel_Init(&rxchCfg);
|
||||
hosal_dma_irq_callback_set(uart->dma_rx_chan, __uart_rx_dma_irq, (void *)uart);
|
||||
DMA_Channel_Init(&rxchCfg);
|
||||
hosal_dma_irq_callback_set(uart->dma_rx_chan, __uart_rx_dma_irq, (void *)uart);
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
static void __uart_config_set(hosal_uart_dev_t *uart, const hosal_uart_config_t *cfg)
|
||||
|
|
@ -258,17 +258,17 @@ static void __uart_config_set(hosal_uart_dev_t *uart, const hosal_uart_config_t
|
|||
uartCfg.parity = (UART_Parity_Type)cfg->parity;
|
||||
|
||||
if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS) {
|
||||
uartCfg.ctsFlowControl = 1;
|
||||
uartCfg.rtsSoftwareControl = 0;
|
||||
uartCfg.ctsFlowControl = 1;
|
||||
uartCfg.rtsSoftwareControl = 0;
|
||||
} else if (cfg->flow_control == HOSAL_FLOW_CONTROL_RTS) {
|
||||
uartCfg.ctsFlowControl = 0;
|
||||
uartCfg.rtsSoftwareControl = 1;
|
||||
uartCfg.ctsFlowControl = 0;
|
||||
uartCfg.rtsSoftwareControl = 1;
|
||||
} else if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS_RTS) {
|
||||
uartCfg.ctsFlowControl = 1;
|
||||
uartCfg.rtsSoftwareControl = 1;
|
||||
uartCfg.ctsFlowControl = 1;
|
||||
uartCfg.rtsSoftwareControl = 1;
|
||||
} else {
|
||||
uartCfg.ctsFlowControl = 0;
|
||||
uartCfg.rtsSoftwareControl = 0;
|
||||
uartCfg.ctsFlowControl = 0;
|
||||
uartCfg.rtsSoftwareControl = 0;
|
||||
}
|
||||
|
||||
//uartCfg.uartClk = (160 * 1000 * 1000) / (uart_div + 1);
|
||||
|
|
@ -280,12 +280,12 @@ static void __uart_config_set(hosal_uart_dev_t *uart, const hosal_uart_config_t
|
|||
UART_Init(id, &uartCfg);
|
||||
#endif
|
||||
if (cfg->mode == HOSAL_UART_MODE_INT) {
|
||||
bl_uart_int_tx_notify_register(uart->port, __uart_tx_irq, uart);
|
||||
bl_uart_int_rx_notify_register(uart->port, __uart_rx_irq, uart);
|
||||
bl_uart_int_enable(uart->port);
|
||||
bl_uart_int_tx_disable(uart->port);
|
||||
bl_uart_int_tx_notify_register(uart->port, __uart_tx_irq, uart);
|
||||
bl_uart_int_rx_notify_register(uart->port, __uart_rx_irq, uart);
|
||||
bl_uart_int_enable(uart->port);
|
||||
bl_uart_int_tx_disable(uart->port);
|
||||
} else {
|
||||
bl_uart_int_disable(uart->port);
|
||||
bl_uart_int_disable(uart->port);
|
||||
}
|
||||
|
||||
/* Enable uart */
|
||||
|
|
@ -341,17 +341,17 @@ int hosal_uart_init(hosal_uart_dev_t *uart)
|
|||
uartCfg.parity = (UART_Parity_Type)cfg->parity;
|
||||
|
||||
if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS) {
|
||||
uartCfg.ctsFlowControl = 1;
|
||||
uartCfg.rtsSoftwareControl = 0;
|
||||
uartCfg.ctsFlowControl = 1;
|
||||
uartCfg.rtsSoftwareControl = 0;
|
||||
} else if (cfg->flow_control == HOSAL_FLOW_CONTROL_RTS) {
|
||||
uartCfg.ctsFlowControl = 0;
|
||||
uartCfg.rtsSoftwareControl = 1;
|
||||
uartCfg.ctsFlowControl = 0;
|
||||
uartCfg.rtsSoftwareControl = 1;
|
||||
} else if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS_RTS) {
|
||||
uartCfg.ctsFlowControl = 1;
|
||||
uartCfg.rtsSoftwareControl = 1;
|
||||
uartCfg.ctsFlowControl = 1;
|
||||
uartCfg.rtsSoftwareControl = 1;
|
||||
} else {
|
||||
uartCfg.ctsFlowControl = 0;
|
||||
uartCfg.rtsSoftwareControl = 0;
|
||||
uartCfg.ctsFlowControl = 0;
|
||||
uartCfg.rtsSoftwareControl = 0;
|
||||
}
|
||||
|
||||
//uartCfg.uartClk = (40 * 1000 * 1000) / (uart_div + 1);
|
||||
|
|
@ -376,12 +376,12 @@ int hosal_uart_init(hosal_uart_dev_t *uart)
|
|||
UART_FifoConfig(id, &fifoCfg);
|
||||
|
||||
if (cfg->mode == HOSAL_UART_MODE_INT) {
|
||||
bl_uart_int_tx_notify_register(uart->port, __uart_tx_irq, uart);
|
||||
bl_uart_int_rx_notify_register(uart->port, __uart_rx_irq, uart);
|
||||
bl_uart_int_enable(uart->port);
|
||||
bl_uart_int_tx_disable(uart->port);
|
||||
bl_uart_int_tx_notify_register(uart->port, __uart_tx_irq, uart);
|
||||
bl_uart_int_rx_notify_register(uart->port, __uart_rx_irq, uart);
|
||||
bl_uart_int_enable(uart->port);
|
||||
bl_uart_int_tx_disable(uart->port);
|
||||
} else {
|
||||
bl_uart_int_disable(uart->port);
|
||||
bl_uart_int_disable(uart->port);
|
||||
}
|
||||
|
||||
/* Enable uart */
|
||||
|
|
@ -418,7 +418,7 @@ int hosal_uart_send(hosal_uart_dev_t *uart, const void *data, uint32_t size)
|
|||
int hosal_uart_ioctl(hosal_uart_dev_t *uart, int ctl, void *p_arg)
|
||||
{
|
||||
#if 0
|
||||
hosal_uart_dma_cfg_t *dma_cfg;
|
||||
hosal_uart_dma_cfg_t *dma_cfg;
|
||||
#endif
|
||||
|
||||
switch (ctl) {
|
||||
|
|
@ -490,26 +490,26 @@ int hosal_uart_ioctl(hosal_uart_dev_t *uart, int ctl, void *p_arg)
|
|||
bl_uart_flush(uart->port);
|
||||
break;
|
||||
case HOSAL_UART_TX_TRIGGER_ON:
|
||||
bl_uart_int_tx_enable(uart->port);
|
||||
break;
|
||||
bl_uart_int_tx_enable(uart->port);
|
||||
break;
|
||||
case HOSAL_UART_TX_TRIGGER_OFF:
|
||||
bl_uart_int_tx_disable(uart->port);
|
||||
break;
|
||||
bl_uart_int_tx_disable(uart->port);
|
||||
break;
|
||||
#if 0
|
||||
case HOSAL_UART_DMA_TX_START:
|
||||
dma_cfg = (hosal_uart_dma_cfg_t *)p_arg;
|
||||
if (__uart_dma_txcfg(uart, dma_cfg) != 0) {
|
||||
return -1;
|
||||
}
|
||||
hosal_dma_chan_start(uart->dma_tx_chan);
|
||||
break;
|
||||
dma_cfg = (hosal_uart_dma_cfg_t *)p_arg;
|
||||
if (__uart_dma_txcfg(uart, dma_cfg) != 0) {
|
||||
return -1;
|
||||
}
|
||||
hosal_dma_chan_start(uart->dma_tx_chan);
|
||||
break;
|
||||
case HOSAL_UART_DMA_RX_START:
|
||||
dma_cfg = (hosal_uart_dma_cfg_t *)p_arg;
|
||||
if (__uart_dma_rxcfg(uart, dma_cfg) != 0) {
|
||||
return -1;
|
||||
}
|
||||
hosal_dma_chan_start(uart->dma_rx_chan);
|
||||
break;
|
||||
dma_cfg = (hosal_uart_dma_cfg_t *)p_arg;
|
||||
if (__uart_dma_rxcfg(uart, dma_cfg) != 0) {
|
||||
return -1;
|
||||
}
|
||||
hosal_dma_chan_start(uart->dma_rx_chan);
|
||||
break;
|
||||
#endif
|
||||
default :
|
||||
return -1;
|
||||
|
|
@ -547,10 +547,10 @@ int hosal_uart_finalize(hosal_uart_dev_t *uart)
|
|||
UART_Disable(uart->port, UART_TXRX);
|
||||
#if 0
|
||||
if (uart->dma_rx_chan > 0) {
|
||||
hosal_dma_chan_release(uart->dma_rx_chan);
|
||||
hosal_dma_chan_release(uart->dma_rx_chan);
|
||||
}
|
||||
if (uart->dma_tx_chan > 0) {
|
||||
hosal_dma_chan_release(uart->dma_tx_chan);
|
||||
hosal_dma_chan_release(uart->dma_tx_chan);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@ typedef void (*hosal_adc_irq_t)(void *parg);
|
|||
typedef struct {
|
||||
uint8_t port; /**< @brief adc port */
|
||||
hosal_adc_config_t config; /**< @brief adc config */
|
||||
hosal_dma_chan_t dma_chan; /**< @brief adc dma channel */
|
||||
hosal_dma_chan_t dma_chan; /**< @brief adc dma channel */
|
||||
hosal_adc_irq_t cb; /**< @brief adc callback */
|
||||
void *p_arg; /**< @brief p_arg data */
|
||||
void *priv; /**< @brief priv data */
|
||||
|
|
@ -116,9 +116,9 @@ typedef void (*hosal_adc_cb_t)(hosal_adc_event_t event, void *data, uint32_t siz
|
|||
*
|
||||
* @param[in] adc the interface which should be initialised
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_adc_init(hosal_adc_dev_t *adc);
|
||||
|
||||
|
|
@ -128,9 +128,9 @@ int hosal_adc_init(hosal_adc_dev_t *adc);
|
|||
* @param[in] adc the interface which should be sampled
|
||||
* @param[in] channel adc channel
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_adc_add_channel(hosal_adc_dev_t *adc, uint32_t channel);
|
||||
|
||||
|
|
@ -140,18 +140,18 @@ int hosal_adc_add_channel(hosal_adc_dev_t *adc, uint32_t channel);
|
|||
* @param[in] adc the interface which should be sampled
|
||||
* @param[in] channel adc channel
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_adc_remove_channel(hosal_adc_dev_t *adc, uint32_t channel);
|
||||
|
||||
/**
|
||||
* @brief Takes adc device handle from an ADC interface
|
||||
*
|
||||
* @return
|
||||
* - other get adc device success
|
||||
* - NULL if an error occurred with any step
|
||||
* @return
|
||||
* - other get adc device success
|
||||
* - NULL if an error occurred with any step
|
||||
*/
|
||||
hosal_adc_dev_t *hosal_adc_device_get(void);
|
||||
|
||||
|
|
@ -162,9 +162,9 @@ hosal_adc_dev_t *hosal_adc_device_get(void);
|
|||
* @param[in] channel adc channel
|
||||
* @param[in] timeout ms timeout
|
||||
*
|
||||
* @return
|
||||
* - other get adc data success
|
||||
* - -1 if an error occurred with any step
|
||||
* @return
|
||||
* - other get adc data success
|
||||
* - -1 if an error occurred with any step
|
||||
*/
|
||||
int hosal_adc_value_get(hosal_adc_dev_t *adc, uint32_t channel, uint32_t timeout);
|
||||
|
||||
|
|
@ -173,9 +173,9 @@ int hosal_adc_value_get(hosal_adc_dev_t *adc, uint32_t channel, uint32_t timeout
|
|||
*
|
||||
* @param[in] adc the interface which should be sampled
|
||||
*
|
||||
* @return
|
||||
* - other get adc data success
|
||||
* - -1 if an error occurred with any step
|
||||
* @return
|
||||
* - other get adc data success
|
||||
* - -1 if an error occurred with any step
|
||||
*/
|
||||
int hosal_adc_tsen_value_get(hosal_adc_dev_t *adc);
|
||||
|
||||
|
|
@ -188,9 +188,9 @@ int hosal_adc_tsen_value_get(hosal_adc_dev_t *adc);
|
|||
* adc in cb must be the same pointer with adc pointer passed to hosal_adc_sample_cb_reg
|
||||
* driver must notify upper layer by calling cb if ADC data is ready in HW or memory(DMA)
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_adc_sample_cb_reg(hosal_adc_dev_t *adc, hosal_adc_cb_t cb);
|
||||
|
||||
|
|
@ -201,9 +201,9 @@ int hosal_adc_sample_cb_reg(hosal_adc_dev_t *adc, hosal_adc_cb_t cb);
|
|||
* @param[in] data adc data buffer
|
||||
* @param[in] size data buffer size aligned with resolution (until the next power of two)
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_adc_start(hosal_adc_dev_t *adc, void *data, uint32_t size);
|
||||
|
||||
|
|
@ -212,9 +212,9 @@ int hosal_adc_start(hosal_adc_dev_t *adc, void *data, uint32_t size);
|
|||
*
|
||||
* @param[in] adc the ADC interface
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_adc_stop(hosal_adc_dev_t *adc);
|
||||
|
||||
|
|
@ -223,9 +223,9 @@ int hosal_adc_stop(hosal_adc_dev_t *adc);
|
|||
*
|
||||
* @param[in] adc the interface which should be de-initialised
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_adc_finalize(hosal_adc_dev_t *adc);
|
||||
|
||||
|
|
|
|||
|
|
@ -78,9 +78,9 @@ typedef struct {
|
|||
*
|
||||
* @param[in] dac the interface which should be initialised
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_dac_init(hosal_dac_dev_t *dac);
|
||||
|
||||
|
|
@ -89,9 +89,9 @@ int hosal_dac_init(hosal_dac_dev_t *dac);
|
|||
*
|
||||
* @param[in] dac the interface which should be de-initialised
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_dac_finalize(hosal_dac_dev_t *dac);
|
||||
|
||||
|
|
@ -100,9 +100,9 @@ int hosal_dac_finalize(hosal_dac_dev_t *dac);
|
|||
*
|
||||
* @param[in] dac the interface which should be started
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_dac_start(hosal_dac_dev_t *dac);
|
||||
|
||||
|
|
@ -111,9 +111,9 @@ int hosal_dac_start(hosal_dac_dev_t *dac);
|
|||
*
|
||||
* @param[in] dac the interface which should be stopped
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_dac_stop(hosal_dac_dev_t *dac);
|
||||
|
||||
|
|
@ -122,11 +122,11 @@ int hosal_dac_stop(hosal_dac_dev_t *dac);
|
|||
*
|
||||
* @param[in] dac the interface to set value
|
||||
*
|
||||
* @param[in] data the value to output, output unit: μV
|
||||
* @param[in] data the value to output, output unit: μV
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_dac_set_value(hosal_dac_dev_t *dac, uint32_t data);
|
||||
|
||||
|
|
@ -145,23 +145,23 @@ int hosal_dac_get_value(hosal_dac_dev_t *dac);
|
|||
* @param [in] dac the DAC interface
|
||||
* @param [in] callback callback handler
|
||||
* @param [in] arg callback arg
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_dac_dma_cb_reg(hosal_dac_dev_t *dac, hosal_dac_cb_t callback, void *arg);
|
||||
|
||||
/**
|
||||
* @brief DAC use DMA mode
|
||||
*
|
||||
*
|
||||
* @param[in] adc the DAC interface
|
||||
* @param[in] data dac data buffer
|
||||
* @param[in] size data buffer size
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_dac_dma_start(hosal_dac_dev_t *dac, uint32_t *data, uint32_t size);
|
||||
|
||||
|
|
@ -170,9 +170,9 @@ int hosal_dac_dma_start(hosal_dac_dev_t *dac, uint32_t *data, uint32_t size);
|
|||
*
|
||||
* @param[in] dac the interface which should be stopped
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_dac_dma_stop(hosal_dac_dev_t *dac);
|
||||
|
||||
|
|
|
|||
|
|
@ -40,11 +40,11 @@ extern "C" {
|
|||
*
|
||||
* @param[in] addr efuse address
|
||||
* @param[in] data store data
|
||||
* @param[in] len data length
|
||||
* @param[in] len data length
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_efuse_read(uint32_t addr, uint32_t *data, uint32_t len);
|
||||
|
||||
|
|
@ -53,11 +53,11 @@ int hosal_efuse_read(uint32_t addr, uint32_t *data, uint32_t len);
|
|||
*
|
||||
* @param[in] addr efuse address
|
||||
* @param[in] data store data
|
||||
* @param[in] len data length
|
||||
* @param[in] len data length
|
||||
*
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
int hosal_efuse_write(uint32_t addr, uint32_t *data, uint32_t len);
|
||||
|
||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@ int hosal_flash_raw_write(void *buffer, uint32_t address, uint32_t length);
|
|||
* - 0 On success
|
||||
* - otherwise is error
|
||||
*/
|
||||
int hosal_flash_raw_erase(uint32_t start_addr, uint32_t length);
|
||||
int hosal_flash_raw_erase(uint32_t start_addr, uint32_t length);
|
||||
|
||||
/** @} */
|
||||
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ typedef struct {
|
|||
*
|
||||
* @param[in] i2c the device for which the i2c port should be initialised
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 on success
|
||||
* - EIO if an error occurred with any step
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ typedef struct {
|
|||
*
|
||||
* @param[in] pwm the PWM device
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
@ -77,9 +77,9 @@ int hosal_pwm_init(hosal_pwm_dev_t *pwm);
|
|||
*
|
||||
* @param[in] pwm the PWM device
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : fail
|
||||
* - other : fail
|
||||
*/
|
||||
int hosal_pwm_start(hosal_pwm_dev_t *pwm);
|
||||
|
||||
|
|
@ -88,7 +88,7 @@ int hosal_pwm_start(hosal_pwm_dev_t *pwm);
|
|||
*
|
||||
* @param[in] pwm the PWM device
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
@ -100,7 +100,7 @@ int hosal_pwm_stop(hosal_pwm_dev_t *pwm);
|
|||
* @param[in] pwm the PWM device
|
||||
* @param[in] para the para of pwm
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
@ -112,7 +112,7 @@ int hosal_pwm_para_chg(hosal_pwm_dev_t *pwm, hosal_pwm_config_t para);
|
|||
* @param[in] pwm the PWM device
|
||||
* @param[in] freq the PWM frequency (0~40M under limited duty)
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
@ -124,7 +124,7 @@ int hosal_pwm_freq_set(hosal_pwm_dev_t *pwm, uint32_t freq);
|
|||
* @param[in] pwm the PWM device
|
||||
* @param[out] p_freq the pointer to memory frequency
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
@ -136,7 +136,7 @@ int hosal_pwm_freq_get(hosal_pwm_dev_t *pwm, uint32_t *p_freq);
|
|||
* @param[in] pwm the PWM device
|
||||
* @param[in] duty the PWM duty (original duty * 100)
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
@ -148,7 +148,7 @@ int hosal_pwm_duty_set(hosal_pwm_dev_t *pwm, uint32_t duty);
|
|||
* @param[in] pwm the PWM device
|
||||
* @param[out] p_duty the pointer to memory duty(original duty * 100)
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
@ -159,7 +159,7 @@ int hosal_pwm_duty_get(hosal_pwm_dev_t *pwm, uint32_t *p_duty);
|
|||
*
|
||||
* @param[in] pwm the interface which should be de-initialised
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ extern "C" {
|
|||
/**
|
||||
* @brief init rng
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
@ -58,7 +58,7 @@ int hosal_rng_init(void);
|
|||
* in this memory with random numbers after executed
|
||||
* @param[in] bytes Length of the memory buffer (bytes)
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -75,9 +75,9 @@ typedef struct {
|
|||
*
|
||||
* @param[in] rtc rtc device
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : fail
|
||||
* - other : fail
|
||||
*/
|
||||
int hosal_rtc_init(hosal_rtc_dev_t *rtc);
|
||||
|
||||
|
|
@ -87,9 +87,9 @@ int hosal_rtc_init(hosal_rtc_dev_t *rtc);
|
|||
* @param[in] rtc rtc device
|
||||
* @param[in] time pointer to a time structure
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : fail
|
||||
* - other : fail
|
||||
*/
|
||||
int hosal_rtc_set_time(hosal_rtc_dev_t *rtc, const hosal_rtc_time_t *time);
|
||||
|
||||
|
|
@ -99,9 +99,9 @@ int hosal_rtc_set_time(hosal_rtc_dev_t *rtc, const hosal_rtc_time_t *time);
|
|||
* @param[in] rtc rtc device
|
||||
* @param[out] time pointer to a time structure
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : fail
|
||||
* - other : fail
|
||||
*/
|
||||
int hosal_rtc_get_time(hosal_rtc_dev_t *rtc, hosal_rtc_time_t *time);
|
||||
|
||||
|
|
@ -111,9 +111,9 @@ int hosal_rtc_get_time(hosal_rtc_dev_t *rtc, hosal_rtc_time_t *time);
|
|||
* @param[in] rtc rtc device
|
||||
* @param[in] time_stamp new time value
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : fail
|
||||
* - other : fail
|
||||
*/
|
||||
int hosal_rtc_set_count(hosal_rtc_dev_t *rtc, uint64_t *time_stamp);
|
||||
|
||||
|
|
@ -121,11 +121,11 @@ int hosal_rtc_set_count(hosal_rtc_dev_t *rtc, uint64_t *time_stamp);
|
|||
* @brief This function will return the value of time read from the on board CPU real time clock.
|
||||
*
|
||||
* @param[in] rtc rtc device
|
||||
* @param[in] time_stamp new time value
|
||||
* @param[in] time_stamp new time value
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : fail
|
||||
* - other : fail
|
||||
*/
|
||||
int hosal_rtc_get_count(hosal_rtc_dev_t *rtc, uint64_t *time_stamp);
|
||||
|
||||
|
|
@ -134,9 +134,9 @@ int hosal_rtc_get_count(hosal_rtc_dev_t *rtc, uint64_t *time_stamp);
|
|||
*
|
||||
* @param[in] RTC the interface which should be de-initialised
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : fail
|
||||
* - other : fail
|
||||
*/
|
||||
int hosal_rtc_finalize(hosal_rtc_dev_t *rtc);
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup hosal_spi SPI
|
||||
/** @addtogroup hosal_spi SPI
|
||||
* HOSAL SPI API
|
||||
*
|
||||
* @{
|
||||
|
|
@ -50,8 +50,8 @@ extern "C" {
|
|||
|
||||
typedef void (*hosal_spi_irq_t)(void *parg); /**< spi irq callback function */
|
||||
|
||||
/**
|
||||
* @brief Define spi config args
|
||||
/**
|
||||
* @brief Define spi config args
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t mode; /**< spi communication mode */
|
||||
|
|
@ -63,7 +63,7 @@ typedef struct {
|
|||
uint8_t pin_miso; /**< spi miso pin */
|
||||
} hosal_spi_config_t;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Define spi dev handle
|
||||
*/
|
||||
typedef struct {
|
||||
|
|
@ -79,8 +79,8 @@ typedef struct {
|
|||
*
|
||||
* @param[in] spi the spi device
|
||||
*
|
||||
* @return
|
||||
* - 0 : on success
|
||||
* @return
|
||||
* - 0 : on success
|
||||
* - other : error
|
||||
*/
|
||||
int hosal_spi_init(hosal_spi_dev_t *spi);
|
||||
|
|
@ -94,8 +94,8 @@ int hosal_spi_init(hosal_spi_dev_t *spi);
|
|||
* @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER
|
||||
* if you want to wait forever
|
||||
*
|
||||
* @return
|
||||
* - 0 : on success
|
||||
* @return
|
||||
* - 0 : on success
|
||||
* - other : error
|
||||
*/
|
||||
int hosal_spi_send(hosal_spi_dev_t *spi, const uint8_t *data, uint32_t size, uint32_t timeout);
|
||||
|
|
@ -109,7 +109,7 @@ int hosal_spi_send(hosal_spi_dev_t *spi, const uint8_t *data, uint32_t size, uin
|
|||
* @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER
|
||||
* if you want to wait forever
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : error
|
||||
*/
|
||||
|
|
@ -125,8 +125,8 @@ int hosal_spi_recv(hosal_spi_dev_t *spi, uint8_t *data, uint16_t size, uint32_t
|
|||
* @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER
|
||||
* if you want to wait forever
|
||||
*
|
||||
* @return
|
||||
* - 0 : success
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : error
|
||||
*/
|
||||
int hosal_spi_send_recv(hosal_spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data, uint16_t size, uint32_t timeout);
|
||||
|
|
@ -138,7 +138,7 @@ int hosal_spi_send_recv(hosal_spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data
|
|||
* @param pfn callback function
|
||||
* @param p_arg callback function parameter
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - othe : error
|
||||
*/
|
||||
|
|
@ -150,7 +150,7 @@ int hosal_spi_irq_callback_set(hosal_spi_dev_t *spi, hosal_spi_irq_t pfn, void *
|
|||
* @param[in] pin cs pin
|
||||
* @param[in] value 0 or 1
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : error
|
||||
*/
|
||||
|
|
@ -162,8 +162,8 @@ int hosal_spi_set_cs(uint8_t pin, uint8_t value);
|
|||
*
|
||||
* @param[in] spi the SPI device to be de-initialised
|
||||
*
|
||||
* @return
|
||||
* - 0 : success
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : error
|
||||
*/
|
||||
int hosal_spi_finalize(hosal_spi_dev_t *spi);
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ extern "C" {
|
|||
typedef void (*hosal_timer_cb_t)(void *arg); /**< Define timer handle function type */
|
||||
|
||||
/**
|
||||
* Define timer config args
|
||||
* Define timer config args
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t period; /**< timer period, us */
|
||||
|
|
@ -57,8 +57,8 @@ typedef struct {
|
|||
void *arg; /**< timer handle args */
|
||||
} hosal_timer_config_t;
|
||||
|
||||
/**
|
||||
* Define timer dev handle
|
||||
/**
|
||||
* Define timer dev handle
|
||||
*/
|
||||
typedef struct {
|
||||
int8_t port; /**< timer port */
|
||||
|
|
@ -71,8 +71,8 @@ typedef struct {
|
|||
*
|
||||
* @param[in] tim timer device
|
||||
*
|
||||
* @return
|
||||
* - 0 : success
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other :error
|
||||
*/
|
||||
int hosal_timer_init(hosal_timer_dev_t *tim);
|
||||
|
|
@ -83,7 +83,7 @@ int hosal_timer_init(hosal_timer_dev_t *tim);
|
|||
* @param[in] tim timer device
|
||||
*
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - 0 : success
|
||||
* - other : error
|
||||
*/
|
||||
int hosal_timer_start(hosal_timer_dev_t *tim);
|
||||
|
|
@ -102,7 +102,7 @@ void hosal_timer_stop(hosal_timer_dev_t *tim);
|
|||
*
|
||||
* @param[in] tim timer device
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other : error
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup hosal_wdg WATCHDOG
|
||||
/** @addtogroup hosal_wdg WATCHDOG
|
||||
* HOSAL WATCHDOG API
|
||||
*
|
||||
* @{
|
||||
|
|
@ -65,7 +65,7 @@ typedef struct {
|
|||
*
|
||||
* @param[in] wdg the watch dog device
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
@ -83,7 +83,7 @@ void hosal_wdg_reload(hosal_wdg_dev_t *wdg);
|
|||
*
|
||||
* @param[in] wdg the watch dog device
|
||||
*
|
||||
* @return
|
||||
* @return
|
||||
* - 0 : success
|
||||
* - other: fail
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -30,16 +30,16 @@
|
|||
#include <stdio.h>
|
||||
#include <platform_hal_device.h>
|
||||
|
||||
extern "C" void* operator new(size_t size)
|
||||
extern "C" void* operator new(size_t size)
|
||||
{
|
||||
/* printf("[C++] new %d\r\n", size); */
|
||||
return pvPortMalloc(size);
|
||||
return pvPortMalloc(size);
|
||||
}
|
||||
|
||||
extern "C" void* operator new[](size_t size)
|
||||
extern "C" void* operator new[](size_t size)
|
||||
{
|
||||
/* printf("[C++] new[] %d\r\n", size); */
|
||||
return pvPortMalloc(size);
|
||||
return pvPortMalloc(size);
|
||||
}
|
||||
|
||||
extern "C" void operator delete(void* ptr) {
|
||||
|
|
@ -52,7 +52,7 @@ extern "C" void operator delete[](void* ptr) {
|
|||
vPortFree(ptr);
|
||||
}
|
||||
|
||||
BLLinkedItem::BLLinkedItem()
|
||||
BLLinkedItem::BLLinkedItem()
|
||||
{
|
||||
this->next = NULL;
|
||||
}
|
||||
|
|
@ -81,13 +81,13 @@ BLLinkedItem* BLLinkedItem::detach()
|
|||
return tmp;
|
||||
}
|
||||
|
||||
BLLinkedList::BLLinkedList()
|
||||
BLLinkedList::BLLinkedList()
|
||||
{
|
||||
this->head = NULL;
|
||||
this->tail = NULL;
|
||||
}
|
||||
|
||||
BLLinkedList* BLLinkedList::push(class BLLinkedItem &item)
|
||||
BLLinkedList* BLLinkedList::push(class BLLinkedItem &item)
|
||||
{
|
||||
printf("[BLLinkedList] push %p\r\n", &item);
|
||||
|
||||
|
|
@ -107,7 +107,7 @@ BLLinkedList* BLLinkedList::push(class BLLinkedItem &item)
|
|||
return this;
|
||||
}
|
||||
|
||||
BLLinkedItem* BLLinkedList::pop()
|
||||
BLLinkedItem* BLLinkedList::pop()
|
||||
{
|
||||
BLLinkedItem *item;
|
||||
|
||||
|
|
@ -173,7 +173,7 @@ int BLAesRequest::done_set()
|
|||
int BLAesRequest::done_set_auto()
|
||||
{
|
||||
this->done = 1;
|
||||
//TODO
|
||||
//TODO
|
||||
printf("[C++] [%s] ongoing...\r\n", __PRETTY_FUNCTION__);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -295,9 +295,9 @@ bool tc_sha1()
|
|||
};
|
||||
|
||||
const uint8_t z_2047_expected[][32] = {
|
||||
{0xe3, 0x59, 0x9e, 0xf5, 0x8f, 0x6c, 0x1b, 0x77, 0x66, 0xf0, 0x45, 0x31, 0xb5, 0x01, 0xec, 0x24, 0x97, 0xb2, 0xa8, 0x2e, },
|
||||
{0xe6, 0xdb, 0x06, 0x25, 0xba, 0xb0, 0x0a, 0x65, 0xeb, 0x25, 0xeb, 0xcb, 0xe6, 0xd5, 0xc3, 0xb6, 0x6b, 0x04, 0xad, 0x12, 0xc8, 0x91, 0x25, 0xa3, 0x4e, 0x10, 0xfe, 0x6c, },
|
||||
{0xa6, 0xb4, 0xc4, 0x6a, 0xa0, 0xaa, 0xce, 0x53, 0x8f, 0x48, 0x4c, 0x2c, 0x7d, 0x3c, 0x96, 0x4b, 0x2c, 0x10, 0xb1, 0x95, 0x9b, 0xe4, 0xf9, 0xc6, 0x57, 0xa2, 0x7b, 0x37, 0xb6, 0xe7, 0x00, 0xe5, },
|
||||
{0xe3, 0x59, 0x9e, 0xf5, 0x8f, 0x6c, 0x1b, 0x77, 0x66, 0xf0, 0x45, 0x31, 0xb5, 0x01, 0xec, 0x24, 0x97, 0xb2, 0xa8, 0x2e, },
|
||||
{0xe6, 0xdb, 0x06, 0x25, 0xba, 0xb0, 0x0a, 0x65, 0xeb, 0x25, 0xeb, 0xcb, 0xe6, 0xd5, 0xc3, 0xb6, 0x6b, 0x04, 0xad, 0x12, 0xc8, 0x91, 0x25, 0xa3, 0x4e, 0x10, 0xfe, 0x6c, },
|
||||
{0xa6, 0xb4, 0xc4, 0x6a, 0xa0, 0xaa, 0xce, 0x53, 0x8f, 0x48, 0x4c, 0x2c, 0x7d, 0x3c, 0x96, 0x4b, 0x2c, 0x10, 0xb1, 0x95, 0x9b, 0xe4, 0xf9, 0xc6, 0x57, 0xa2, 0x7b, 0x37, 0xb6, 0xe7, 0x00, 0xe5, },
|
||||
};
|
||||
|
||||
while (1) {
|
||||
|
|
|
|||
|
|
@ -3,12 +3,12 @@
|
|||
* @file bflb_bsp_driver_glue.h
|
||||
* @version 0.1
|
||||
* @date 2020-07-08
|
||||
* @brief
|
||||
* @brief
|
||||
* *****************************************************************************
|
||||
* @attention
|
||||
*
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*
|
||||
* *****************************************************************************
|
||||
*/
|
||||
#ifndef __bBFLB_BSP_DRIVER_GLUE_H__
|
||||
|
|
|
|||
|
|
@ -3,12 +3,12 @@
|
|||
* @file bflb_stub.c
|
||||
* @version 0.1
|
||||
* @date 2020-07-08
|
||||
* @brief
|
||||
* @brief
|
||||
* *****************************************************************************
|
||||
* @attention
|
||||
*
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*
|
||||
* *****************************************************************************
|
||||
*/
|
||||
#include "bflb_stub.h"
|
||||
|
|
@ -157,4 +157,4 @@ void BFLB_BSP_Delay_Ms(uint32_t time)
|
|||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,12 +3,12 @@
|
|||
* @file bflb_stub.h
|
||||
* @version 0.1
|
||||
* @date 2020-07-08
|
||||
* @brief
|
||||
* @brief
|
||||
* *****************************************************************************
|
||||
* @attention
|
||||
*
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*
|
||||
* *****************************************************************************
|
||||
*/
|
||||
#ifndef __BFLB_STUB__
|
||||
|
|
@ -51,4 +51,4 @@ void BFLB_BSP_Set_Alarm_Time(uint64_t time);
|
|||
void BFLB_BSP_Deinit_Time(void);
|
||||
void BFLB_BSP_Delay_Ms(uint32_t time);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,4 +14,4 @@
|
|||
#define ADC_OFFSET_CALIB_EN (0) /*!< Offset calibration enable */
|
||||
#define ADC_OFFSER_CALIB_VAL (0) /*!< Offset calibration value */
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,4 +11,4 @@
|
|||
*/
|
||||
#define DAC_REF_RNG_DEFAULT_SELECT (0x3) /*!< ADC 1.8V select */
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -8,4 +8,4 @@
|
|||
#define I2S_FS_INVERT DISABLE
|
||||
#define I2S_BCLK_INVERT DISABLE
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,4 +14,4 @@
|
|||
#define UART_FIFO_MAX_LEN 32
|
||||
#define UART_DEFAULT_RTO_TIMEOUT 100
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -173,4 +173,4 @@ float adc_get_tsen(uint16_t tsen_offset);
|
|||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -258,4 +258,4 @@ typedef struct audio_device {
|
|||
#define DEVICE_CTRL_GET_RECORD_PONG_BUF 0x17
|
||||
|
||||
int audio_register(enum audio_index_type index, const char *name);
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -69,4 +69,4 @@ void system_clock_init(void);
|
|||
void peripheral_clock_init(void);
|
||||
void system_mtimer_clock_init(void);
|
||||
void system_mtimer_clock_reinit(void);
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -57,300 +57,300 @@ struct drm_dsc_picture_parameter_set;
|
|||
*/
|
||||
struct drm_dsc_picture_parameter_set {
|
||||
/**
|
||||
* @dsc_version:
|
||||
* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
|
||||
* PPS0[7:4] - dsc_version_major: Contains major version of DSC
|
||||
*/
|
||||
* @dsc_version:
|
||||
* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
|
||||
* PPS0[7:4] - dsc_version_major: Contains major version of DSC
|
||||
*/
|
||||
u8 dsc_version;
|
||||
/**
|
||||
* @pps_identifier:
|
||||
* PPS1[7:0] - Application specific identifier that can be
|
||||
* used to differentiate between different PPS tables.
|
||||
*/
|
||||
* @pps_identifier:
|
||||
* PPS1[7:0] - Application specific identifier that can be
|
||||
* used to differentiate between different PPS tables.
|
||||
*/
|
||||
u8 pps_identifier;
|
||||
/**
|
||||
* @pps_reserved:
|
||||
* PPS2[7:0]- RESERVED Byte
|
||||
*/
|
||||
* @pps_reserved:
|
||||
* PPS2[7:0]- RESERVED Byte
|
||||
*/
|
||||
u8 pps_reserved;
|
||||
/**
|
||||
* @pps_3:
|
||||
* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
|
||||
* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
|
||||
* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
|
||||
* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
|
||||
* PPS3[7:4] - bits_per_component: Bits per component for the original
|
||||
* pixels of the encoded picture.
|
||||
* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
|
||||
* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
|
||||
* allowed only when dsc_minor_version = 0x2)
|
||||
*/
|
||||
* @pps_3:
|
||||
* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
|
||||
* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
|
||||
* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
|
||||
* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
|
||||
* PPS3[7:4] - bits_per_component: Bits per component for the original
|
||||
* pixels of the encoded picture.
|
||||
* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
|
||||
* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
|
||||
* allowed only when dsc_minor_version = 0x2)
|
||||
*/
|
||||
u8 pps_3;
|
||||
/**
|
||||
* @pps_4:
|
||||
* PPS4[1:0] -These are the most significant 2 bits of
|
||||
* compressed BPP bits_per_pixel[9:0] syntax element.
|
||||
* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
|
||||
* PPS4[3] - simple_422: Indicates if decoder drops samples to
|
||||
* reconstruct the 4:2:2 picture.
|
||||
* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
|
||||
* active.
|
||||
* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
|
||||
* groups in picture
|
||||
* PPS4[7:6] - Reseved bits
|
||||
*/
|
||||
* @pps_4:
|
||||
* PPS4[1:0] -These are the most significant 2 bits of
|
||||
* compressed BPP bits_per_pixel[9:0] syntax element.
|
||||
* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
|
||||
* PPS4[3] - simple_422: Indicates if decoder drops samples to
|
||||
* reconstruct the 4:2:2 picture.
|
||||
* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
|
||||
* active.
|
||||
* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
|
||||
* groups in picture
|
||||
* PPS4[7:6] - Reseved bits
|
||||
*/
|
||||
u8 pps_4;
|
||||
/**
|
||||
* @bits_per_pixel_low:
|
||||
* PPS5[7:0] - This indicates the lower significant 8 bits of
|
||||
* the compressed BPP bits_per_pixel[9:0] element.
|
||||
*/
|
||||
* @bits_per_pixel_low:
|
||||
* PPS5[7:0] - This indicates the lower significant 8 bits of
|
||||
* the compressed BPP bits_per_pixel[9:0] element.
|
||||
*/
|
||||
u8 bits_per_pixel_low;
|
||||
/**
|
||||
* @pic_height:
|
||||
* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
|
||||
* within the raster.
|
||||
*/
|
||||
* @pic_height:
|
||||
* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
|
||||
* within the raster.
|
||||
*/
|
||||
__be16 pic_height;
|
||||
/**
|
||||
* @pic_width:
|
||||
* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
|
||||
* the raster.
|
||||
*/
|
||||
* @pic_width:
|
||||
* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
|
||||
* the raster.
|
||||
*/
|
||||
__be16 pic_width;
|
||||
/**
|
||||
* @slice_height:
|
||||
* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
|
||||
*/
|
||||
* @slice_height:
|
||||
* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
|
||||
*/
|
||||
__be16 slice_height;
|
||||
/**
|
||||
* @slice_width:
|
||||
* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
|
||||
*/
|
||||
* @slice_width:
|
||||
* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
|
||||
*/
|
||||
__be16 slice_width;
|
||||
/**
|
||||
* @chunk_size:
|
||||
* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
|
||||
* that are used for slice multiplexing.
|
||||
*/
|
||||
* @chunk_size:
|
||||
* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
|
||||
* that are used for slice multiplexing.
|
||||
*/
|
||||
__be16 chunk_size;
|
||||
/**
|
||||
* @initial_xmit_delay_high:
|
||||
* PPS16[1:0] - Most Significant two bits of initial transmission delay.
|
||||
* It specifies the number of pixel times that the encoder waits before
|
||||
* transmitting data from its rate buffer.
|
||||
* PPS16[7:2] - Reserved
|
||||
*/
|
||||
* @initial_xmit_delay_high:
|
||||
* PPS16[1:0] - Most Significant two bits of initial transmission delay.
|
||||
* It specifies the number of pixel times that the encoder waits before
|
||||
* transmitting data from its rate buffer.
|
||||
* PPS16[7:2] - Reserved
|
||||
*/
|
||||
u8 initial_xmit_delay_high;
|
||||
/**
|
||||
* @initial_xmit_delay_low:
|
||||
* PPS17[7:0] - Least significant 8 bits of initial transmission delay.
|
||||
*/
|
||||
* @initial_xmit_delay_low:
|
||||
* PPS17[7:0] - Least significant 8 bits of initial transmission delay.
|
||||
*/
|
||||
u8 initial_xmit_delay_low;
|
||||
/**
|
||||
* @initial_dec_delay:
|
||||
*
|
||||
* PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
|
||||
* of pixel times that the decoder accumulates data in its rate buffer
|
||||
* before starting to decode and output pixels.
|
||||
*/
|
||||
* @initial_dec_delay:
|
||||
*
|
||||
* PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
|
||||
* of pixel times that the decoder accumulates data in its rate buffer
|
||||
* before starting to decode and output pixels.
|
||||
*/
|
||||
__be16 initial_dec_delay;
|
||||
/**
|
||||
* @pps20_reserved:
|
||||
*
|
||||
* PPS20[7:0] - Reserved
|
||||
*/
|
||||
* @pps20_reserved:
|
||||
*
|
||||
* PPS20[7:0] - Reserved
|
||||
*/
|
||||
u8 pps20_reserved;
|
||||
/**
|
||||
* @initial_scale_value:
|
||||
* PPS21[5:0] - Initial rcXformScale factor used at beginning
|
||||
* of a slice.
|
||||
* PPS21[7:6] - Reserved
|
||||
*/
|
||||
* @initial_scale_value:
|
||||
* PPS21[5:0] - Initial rcXformScale factor used at beginning
|
||||
* of a slice.
|
||||
* PPS21[7:6] - Reserved
|
||||
*/
|
||||
u8 initial_scale_value;
|
||||
/**
|
||||
* @scale_increment_interval:
|
||||
* PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
|
||||
* the rcXformScale factor at end of a slice.
|
||||
*/
|
||||
* @scale_increment_interval:
|
||||
* PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
|
||||
* the rcXformScale factor at end of a slice.
|
||||
*/
|
||||
__be16 scale_increment_interval;
|
||||
/**
|
||||
* @scale_decrement_interval_high:
|
||||
* PPS24[3:0] - Higher 4 bits indicating number of group times between
|
||||
* decrementing the rcXformScale factor at beginning of a slice.
|
||||
* PPS24[7:4] - Reserved
|
||||
*/
|
||||
* @scale_decrement_interval_high:
|
||||
* PPS24[3:0] - Higher 4 bits indicating number of group times between
|
||||
* decrementing the rcXformScale factor at beginning of a slice.
|
||||
* PPS24[7:4] - Reserved
|
||||
*/
|
||||
u8 scale_decrement_interval_high;
|
||||
/**
|
||||
* @scale_decrement_interval_low:
|
||||
* PPS25[7:0] - Lower 8 bits of scale decrement interval
|
||||
*/
|
||||
* @scale_decrement_interval_low:
|
||||
* PPS25[7:0] - Lower 8 bits of scale decrement interval
|
||||
*/
|
||||
u8 scale_decrement_interval_low;
|
||||
/**
|
||||
* @pps26_reserved:
|
||||
* PPS26[7:0]
|
||||
*/
|
||||
* @pps26_reserved:
|
||||
* PPS26[7:0]
|
||||
*/
|
||||
u8 pps26_reserved;
|
||||
/**
|
||||
* @first_line_bpg_offset:
|
||||
* PPS27[4:0] - Number of additional bits that are allocated
|
||||
* for each group on first line of a slice.
|
||||
* PPS27[7:5] - Reserved
|
||||
*/
|
||||
* @first_line_bpg_offset:
|
||||
* PPS27[4:0] - Number of additional bits that are allocated
|
||||
* for each group on first line of a slice.
|
||||
* PPS27[7:5] - Reserved
|
||||
*/
|
||||
u8 first_line_bpg_offset;
|
||||
/**
|
||||
* @nfl_bpg_offset:
|
||||
* PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
|
||||
* deallocated for each group for groups after the first line of slice.
|
||||
*/
|
||||
* @nfl_bpg_offset:
|
||||
* PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
|
||||
* deallocated for each group for groups after the first line of slice.
|
||||
*/
|
||||
__be16 nfl_bpg_offset;
|
||||
/**
|
||||
* @slice_bpg_offset:
|
||||
* PPS30, PPS31[7:0] - Number of bits that are deallocated for each
|
||||
* group to enforce the slice constraint.
|
||||
*/
|
||||
* @slice_bpg_offset:
|
||||
* PPS30, PPS31[7:0] - Number of bits that are deallocated for each
|
||||
* group to enforce the slice constraint.
|
||||
*/
|
||||
__be16 slice_bpg_offset;
|
||||
/**
|
||||
* @initial_offset:
|
||||
* PPS32,33[7:0] - Initial value for rcXformOffset
|
||||
*/
|
||||
* @initial_offset:
|
||||
* PPS32,33[7:0] - Initial value for rcXformOffset
|
||||
*/
|
||||
__be16 initial_offset;
|
||||
/**
|
||||
* @final_offset:
|
||||
* PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
|
||||
*/
|
||||
* @final_offset:
|
||||
* PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
|
||||
*/
|
||||
__be16 final_offset;
|
||||
/**
|
||||
* @flatness_min_qp:
|
||||
* PPS36[4:0] - Minimum QP at which flatness is signaled and
|
||||
* flatness QP adjustment is made.
|
||||
* PPS36[7:5] - Reserved
|
||||
*/
|
||||
* @flatness_min_qp:
|
||||
* PPS36[4:0] - Minimum QP at which flatness is signaled and
|
||||
* flatness QP adjustment is made.
|
||||
* PPS36[7:5] - Reserved
|
||||
*/
|
||||
u8 flatness_min_qp;
|
||||
/**
|
||||
* @flatness_max_qp:
|
||||
* PPS37[4:0] - Max QP at which flatness is signalled and
|
||||
* the flatness adjustment is made.
|
||||
* PPS37[7:5] - Reserved
|
||||
*/
|
||||
* @flatness_max_qp:
|
||||
* PPS37[4:0] - Max QP at which flatness is signalled and
|
||||
* the flatness adjustment is made.
|
||||
* PPS37[7:5] - Reserved
|
||||
*/
|
||||
u8 flatness_max_qp;
|
||||
/**
|
||||
* @rc_model_size:
|
||||
* PPS38,39[7:0] - Number of bits within RC Model.
|
||||
*/
|
||||
* @rc_model_size:
|
||||
* PPS38,39[7:0] - Number of bits within RC Model.
|
||||
*/
|
||||
__be16 rc_model_size;
|
||||
/**
|
||||
* @rc_edge_factor:
|
||||
* PPS40[3:0] - Ratio of current activity vs, previous
|
||||
* activity to determine presence of edge.
|
||||
* PPS40[7:4] - Reserved
|
||||
*/
|
||||
* @rc_edge_factor:
|
||||
* PPS40[3:0] - Ratio of current activity vs, previous
|
||||
* activity to determine presence of edge.
|
||||
* PPS40[7:4] - Reserved
|
||||
*/
|
||||
u8 rc_edge_factor;
|
||||
/**
|
||||
* @rc_quant_incr_limit0:
|
||||
* PPS41[4:0] - QP threshold used in short term RC
|
||||
* PPS41[7:5] - Reserved
|
||||
*/
|
||||
* @rc_quant_incr_limit0:
|
||||
* PPS41[4:0] - QP threshold used in short term RC
|
||||
* PPS41[7:5] - Reserved
|
||||
*/
|
||||
u8 rc_quant_incr_limit0;
|
||||
/**
|
||||
* @rc_quant_incr_limit1:
|
||||
* PPS42[4:0] - QP threshold used in short term RC
|
||||
* PPS42[7:5] - Reserved
|
||||
*/
|
||||
* @rc_quant_incr_limit1:
|
||||
* PPS42[4:0] - QP threshold used in short term RC
|
||||
* PPS42[7:5] - Reserved
|
||||
*/
|
||||
u8 rc_quant_incr_limit1;
|
||||
/**
|
||||
* @rc_tgt_offset:
|
||||
* PPS43[3:0] - Lower end of the variability range around the target
|
||||
* bits per group that is allowed by short term RC.
|
||||
* PPS43[7:4]- Upper end of the variability range around the target
|
||||
* bits per group that i allowed by short term rc.
|
||||
*/
|
||||
* @rc_tgt_offset:
|
||||
* PPS43[3:0] - Lower end of the variability range around the target
|
||||
* bits per group that is allowed by short term RC.
|
||||
* PPS43[7:4]- Upper end of the variability range around the target
|
||||
* bits per group that i allowed by short term rc.
|
||||
*/
|
||||
u8 rc_tgt_offset;
|
||||
/**
|
||||
* @rc_buf_thresh:
|
||||
* PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
|
||||
* the 15 ranges defined by 14 thresholds.
|
||||
*/
|
||||
* @rc_buf_thresh:
|
||||
* PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
|
||||
* the 15 ranges defined by 14 thresholds.
|
||||
*/
|
||||
u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
|
||||
/**
|
||||
* @rc_range_parameters:
|
||||
* PPS58[7:0] - PPS87[7:0]
|
||||
* Parameters that correspond to each of the 15 ranges.
|
||||
*/
|
||||
* @rc_range_parameters:
|
||||
* PPS58[7:0] - PPS87[7:0]
|
||||
* Parameters that correspond to each of the 15 ranges.
|
||||
*/
|
||||
__be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
|
||||
/**
|
||||
* @native_422_420:
|
||||
* PPS88[0] - 0 = Native 4:2:2 not used
|
||||
* 1 = Native 4:2:2 used
|
||||
* PPS88[1] - 0 = Native 4:2:0 not use
|
||||
* 1 = Native 4:2:0 used
|
||||
* PPS88[7:2] - Reserved 6 bits
|
||||
*/
|
||||
* @native_422_420:
|
||||
* PPS88[0] - 0 = Native 4:2:2 not used
|
||||
* 1 = Native 4:2:2 used
|
||||
* PPS88[1] - 0 = Native 4:2:0 not use
|
||||
* 1 = Native 4:2:0 used
|
||||
* PPS88[7:2] - Reserved 6 bits
|
||||
*/
|
||||
u8 native_422_420;
|
||||
/**
|
||||
* @second_line_bpg_offset:
|
||||
* PPS89[4:0] - Additional bits/group budget for the
|
||||
* second line of a slice in Native 4:2:0 mode.
|
||||
* Set to 0 if DSC minor version is 1 or native420 is 0.
|
||||
* PPS89[7:5] - Reserved
|
||||
*/
|
||||
* @second_line_bpg_offset:
|
||||
* PPS89[4:0] - Additional bits/group budget for the
|
||||
* second line of a slice in Native 4:2:0 mode.
|
||||
* Set to 0 if DSC minor version is 1 or native420 is 0.
|
||||
* PPS89[7:5] - Reserved
|
||||
*/
|
||||
u8 second_line_bpg_offset;
|
||||
/**
|
||||
* @nsl_bpg_offset:
|
||||
* PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
|
||||
* for each group that is not in the second line of a slice.
|
||||
*/
|
||||
* @nsl_bpg_offset:
|
||||
* PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
|
||||
* for each group that is not in the second line of a slice.
|
||||
*/
|
||||
__be16 nsl_bpg_offset;
|
||||
/**
|
||||
* @second_line_offset_adj:
|
||||
* PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
|
||||
* line in Native 4:2:0 mode.
|
||||
*/
|
||||
* @second_line_offset_adj:
|
||||
* PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
|
||||
* line in Native 4:2:0 mode.
|
||||
*/
|
||||
__be16 second_line_offset_adj;
|
||||
/**
|
||||
* @pps_long_94_reserved:
|
||||
* PPS 94, 95, 96, 97 - Reserved
|
||||
*/
|
||||
* @pps_long_94_reserved:
|
||||
* PPS 94, 95, 96, 97 - Reserved
|
||||
*/
|
||||
u32 pps_long_94_reserved;
|
||||
/**
|
||||
* @pps_long_98_reserved:
|
||||
* PPS 98, 99, 100, 101 - Reserved
|
||||
*/
|
||||
* @pps_long_98_reserved:
|
||||
* PPS 98, 99, 100, 101 - Reserved
|
||||
*/
|
||||
u32 pps_long_98_reserved;
|
||||
/**
|
||||
* @pps_long_102_reserved:
|
||||
* PPS 102, 103, 104, 105 - Reserved
|
||||
*/
|
||||
* @pps_long_102_reserved:
|
||||
* PPS 102, 103, 104, 105 - Reserved
|
||||
*/
|
||||
u32 pps_long_102_reserved;
|
||||
/**
|
||||
* @pps_long_106_reserved:
|
||||
* PPS 106, 107, 108, 109 - reserved
|
||||
*/
|
||||
* @pps_long_106_reserved:
|
||||
* PPS 106, 107, 108, 109 - reserved
|
||||
*/
|
||||
u32 pps_long_106_reserved;
|
||||
/**
|
||||
* @pps_long_110_reserved:
|
||||
* PPS 110, 111, 112, 113 - reserved
|
||||
*/
|
||||
* @pps_long_110_reserved:
|
||||
* PPS 110, 111, 112, 113 - reserved
|
||||
*/
|
||||
u32 pps_long_110_reserved;
|
||||
/**
|
||||
* @pps_long_114_reserved:
|
||||
* PPS 114 - 117 - reserved
|
||||
*/
|
||||
* @pps_long_114_reserved:
|
||||
* PPS 114 - 117 - reserved
|
||||
*/
|
||||
u32 pps_long_114_reserved;
|
||||
/**
|
||||
* @pps_long_118_reserved:
|
||||
* PPS 118 - 121 - reserved
|
||||
*/
|
||||
* @pps_long_118_reserved:
|
||||
* PPS 118 - 121 - reserved
|
||||
*/
|
||||
u32 pps_long_118_reserved;
|
||||
/**
|
||||
* @pps_long_122_reserved:
|
||||
* PPS 122- 125 - reserved
|
||||
*/
|
||||
* @pps_long_122_reserved:
|
||||
* PPS 122- 125 - reserved
|
||||
*/
|
||||
u32 pps_long_122_reserved;
|
||||
/**
|
||||
* @pps_short_126_reserved:
|
||||
* PPS 126, 127 - reserved
|
||||
*/
|
||||
* @pps_short_126_reserved:
|
||||
* PPS 126, 127 - reserved
|
||||
*/
|
||||
__be16 pps_short_126_reserved;
|
||||
} __attribute__((packed));
|
||||
|
||||
|
|
@ -571,4 +571,4 @@ int mipi_dsi_dcs_set_display_brightness(const struct mipi_dsi_device *dsi,
|
|||
int mipi_dsi_dcs_get_display_brightness(const struct mipi_dsi_device *dsi,
|
||||
u16 *brightness);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -74,4 +74,4 @@ typedef struct i2c_device {
|
|||
int i2c_register(enum i2c_index_type index, const char *name);
|
||||
int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -114,4 +114,4 @@ typedef struct i2s_device {
|
|||
|
||||
int i2s_register(enum i2s_index_type index, const char *name);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -40,4 +40,4 @@ void mtimer_delay_us(uint32_t time);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -54,4 +54,4 @@ int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, s
|
|||
int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out);
|
||||
int sec_aes_deinit(sec_aes_handle_t *handle);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -54,4 +54,4 @@ int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, u
|
|||
int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s);
|
||||
int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -59,4 +59,4 @@ int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t si
|
|||
|
||||
#define SEC_CODEPATH_STATE_SIGN 0x48672386
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -61,4 +61,4 @@ int sec_hash_finish(sec_hash_handle_t *handle, void *buffer);
|
|||
int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name);
|
||||
int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -126,4 +126,4 @@ typedef struct spi_device {
|
|||
|
||||
int spi_register(enum spi_index_type index, const char *name);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -91,4 +91,4 @@ typedef struct timer_device {
|
|||
|
||||
int timer_register(enum timer_index_type index, const char *name);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -128,4 +128,4 @@ typedef struct uart_device {
|
|||
|
||||
int uart_register(enum uart_index_type index, const char *name);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -6,44 +6,44 @@
|
|||
*/
|
||||
struct drm_panel {
|
||||
/**
|
||||
* @dev:
|
||||
*
|
||||
* Parent device of the panel.
|
||||
*/
|
||||
* @dev:
|
||||
*
|
||||
* Parent device of the panel.
|
||||
*/
|
||||
struct device *dev;
|
||||
|
||||
/**
|
||||
* @backlight:
|
||||
*
|
||||
* Backlight device, used to turn on backlight after the call
|
||||
* to enable(), and to turn off backlight before the call to
|
||||
* disable().
|
||||
* backlight is set by drm_panel_of_backlight() and drivers
|
||||
* shall not assign it.
|
||||
*/
|
||||
* @backlight:
|
||||
*
|
||||
* Backlight device, used to turn on backlight after the call
|
||||
* to enable(), and to turn off backlight before the call to
|
||||
* disable().
|
||||
* backlight is set by drm_panel_of_backlight() and drivers
|
||||
* shall not assign it.
|
||||
*/
|
||||
struct backlight_device *backlight;
|
||||
|
||||
/**
|
||||
* @funcs:
|
||||
*
|
||||
* Operations that can be performed on the panel.
|
||||
*/
|
||||
* @funcs:
|
||||
*
|
||||
* Operations that can be performed on the panel.
|
||||
*/
|
||||
const struct drm_panel_funcs *funcs;
|
||||
|
||||
/**
|
||||
* @connector_type:
|
||||
*
|
||||
* Type of the panel as a DRM_MODE_CONNECTOR_* value. This is used to
|
||||
* initialise the drm_connector corresponding to the panel with the
|
||||
* correct connector type.
|
||||
*/
|
||||
* @connector_type:
|
||||
*
|
||||
* Type of the panel as a DRM_MODE_CONNECTOR_* value. This is used to
|
||||
* initialise the drm_connector corresponding to the panel with the
|
||||
* correct connector type.
|
||||
*/
|
||||
int connector_type;
|
||||
|
||||
/**
|
||||
* @list:
|
||||
*
|
||||
* Panel entry in registry.
|
||||
*/
|
||||
* @list:
|
||||
*
|
||||
* Panel entry in registry.
|
||||
*/
|
||||
//struct list_head list;
|
||||
};
|
||||
|
||||
|
|
@ -184,4 +184,4 @@ enum {
|
|||
#define MIPI_DCS_PIXEL_FMT_8BIT 2
|
||||
#define MIPI_DCS_PIXEL_FMT_3BIT 1
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -380,4 +380,4 @@ void ADC_IRQ(void)
|
|||
{
|
||||
adc_isr(&adcx_device[ADC0_INDEX]);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -599,4 +599,4 @@ uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void)
|
|||
uint32_t hal_boot2_get_bootheader_offset(void)
|
||||
{
|
||||
return 0x0;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -138,4 +138,4 @@ void ATTR_TCM_SECTION hal_dcache_clean_invalidate_byaddr(uintptr_t addr, uint32_
|
|||
}
|
||||
|
||||
__DSB();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -929,4 +929,4 @@ int mipi_dsi_dcs_get_display_brightness(const struct mipi_dsi_device *dsi,
|
|||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -224,4 +224,4 @@ static void GPIO_IRQ(void)
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -128,4 +128,4 @@ int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num)
|
|||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -121,10 +121,10 @@ int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, con
|
|||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 };
|
||||
#endif
|
||||
/* 0:c
|
||||
* 4:a
|
||||
* 5:number
|
||||
* 6&7:temp
|
||||
*/
|
||||
* 4:a
|
||||
* 5:number
|
||||
* 6&7:temp
|
||||
*/
|
||||
|
||||
/* base = a */
|
||||
Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0);
|
||||
|
|
@ -201,13 +201,13 @@ int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint
|
|||
uint32_t dataSize = (size >> 3) >> 2;
|
||||
|
||||
/* 0:c
|
||||
* 1:NPrime_c
|
||||
* 2:invR_c
|
||||
* 4:a(mont domain)
|
||||
* 5:b
|
||||
* 6:a^b%c(mont domain)
|
||||
* 7:a^b%c(gf domain)
|
||||
* 10&11:2^size for GF2Mont*/
|
||||
* 1:NPrime_c
|
||||
* 2:invR_c
|
||||
* 4:a(mont domain)
|
||||
* 5:b
|
||||
* 6:a^b%c(mont domain)
|
||||
* 7:a^b%c(gf domain)
|
||||
* 10&11:2^size for GF2Mont*/
|
||||
Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0);
|
||||
Sec_Eng_PKA_Write_Data(nregType, 1, (uint32_t *)primeN_c, dataSize, 1);
|
||||
Sec_Eng_PKA_Write_Data(nregType, 2, (uint32_t *)invR_c, dataSize, 1);
|
||||
|
|
@ -250,38 +250,38 @@ int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint
|
|||
int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r)
|
||||
{
|
||||
/*
|
||||
* m1 = pow(c, dP, p)
|
||||
* m2 = pow(c, dQ, q)
|
||||
* h = (qInv * (m1 - m2)) % p
|
||||
* m = m2 + h * q
|
||||
* */
|
||||
* m1 = pow(c, dP, p)
|
||||
* m2 = pow(c, dQ, q)
|
||||
* h = (qInv * (m1 - m2)) % p
|
||||
* m = m2 + h * q
|
||||
* */
|
||||
SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
|
||||
SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
|
||||
uint32_t dataSize = (size >> 3) >> 2;
|
||||
#if 0
|
||||
uint8_t m1[64] = {0x11, 0xdd, 0x19, 0x7e, 0x69, 0x1a, 0x40, 0x0a, 0x28, 0xfc, 0x3b, 0x31, 0x47, 0xa2, 0x6c, 0x14,
|
||||
0x4e, 0xf6, 0xb0, 0xe6, 0xcd, 0x89, 0x0b, 0x4f, 0x02, 0xe4, 0x86, 0xe2, 0xe5, 0xbe, 0xe1, 0xaf,
|
||||
0x91, 0xd1, 0x7b, 0x59, 0x8d, 0xdc, 0xb3, 0x57, 0x18, 0xcb, 0x80, 0x05, 0x1c, 0xb5, 0xa4, 0x07,
|
||||
0xde, 0x31, 0x94, 0xa4, 0x2f, 0x45, 0xc7, 0x95, 0x75, 0x0f, 0x91, 0xf0, 0x37, 0x91, 0x85, 0xa5
|
||||
};
|
||||
uint8_t m2[64] = {0x63, 0x89, 0xa3, 0xbb, 0x64, 0x63, 0x87, 0x4f, 0x38, 0xbd, 0x9e, 0x0e, 0x93, 0x29, 0x58, 0xee,
|
||||
0xf8, 0xe2, 0x20, 0x2d, 0xe5, 0x38, 0x0a, 0x7f, 0x18, 0x38, 0x2f, 0xa3, 0xf5, 0x48, 0xf8, 0xfd,
|
||||
0xe5, 0x78, 0x4a, 0x10, 0x62, 0x01, 0x09, 0x29, 0xe3, 0xe3, 0x9f, 0xad, 0x9b, 0xbe, 0x20, 0xd2,
|
||||
0x68, 0x90, 0x57, 0x97, 0xfc, 0x78, 0xd5, 0xdb, 0x07, 0x5b, 0xfe, 0x21, 0x0a, 0x2d, 0x7f, 0xc1
|
||||
};
|
||||
uint8_t m1[64] = {0x11, 0xdd, 0x19, 0x7e, 0x69, 0x1a, 0x40, 0x0a, 0x28, 0xfc, 0x3b, 0x31, 0x47, 0xa2, 0x6c, 0x14,
|
||||
0x4e, 0xf6, 0xb0, 0xe6, 0xcd, 0x89, 0x0b, 0x4f, 0x02, 0xe4, 0x86, 0xe2, 0xe5, 0xbe, 0xe1, 0xaf,
|
||||
0x91, 0xd1, 0x7b, 0x59, 0x8d, 0xdc, 0xb3, 0x57, 0x18, 0xcb, 0x80, 0x05, 0x1c, 0xb5, 0xa4, 0x07,
|
||||
0xde, 0x31, 0x94, 0xa4, 0x2f, 0x45, 0xc7, 0x95, 0x75, 0x0f, 0x91, 0xf0, 0x37, 0x91, 0x85, 0xa5
|
||||
};
|
||||
uint8_t m2[64] = {0x63, 0x89, 0xa3, 0xbb, 0x64, 0x63, 0x87, 0x4f, 0x38, 0xbd, 0x9e, 0x0e, 0x93, 0x29, 0x58, 0xee,
|
||||
0xf8, 0xe2, 0x20, 0x2d, 0xe5, 0x38, 0x0a, 0x7f, 0x18, 0x38, 0x2f, 0xa3, 0xf5, 0x48, 0xf8, 0xfd,
|
||||
0xe5, 0x78, 0x4a, 0x10, 0x62, 0x01, 0x09, 0x29, 0xe3, 0xe3, 0x9f, 0xad, 0x9b, 0xbe, 0x20, 0xd2,
|
||||
0x68, 0x90, 0x57, 0x97, 0xfc, 0x78, 0xd5, 0xdb, 0x07, 0x5b, 0xfe, 0x21, 0x0a, 0x2d, 0x7f, 0xc1
|
||||
};
|
||||
#else
|
||||
uint32_t m1[32];
|
||||
uint32_t m2[32];
|
||||
#endif
|
||||
/*
|
||||
* 4:m1
|
||||
* 5:m2
|
||||
* 6:qInv
|
||||
* 7:p
|
||||
* 8:q
|
||||
* 9:h
|
||||
* 10&11:qInv*(m1-m2)
|
||||
*/
|
||||
* 4:m1
|
||||
* 5:m2
|
||||
* 6:qInv
|
||||
* 7:p
|
||||
* 8:q
|
||||
* 9:h
|
||||
* 10&11:qInv*(m1-m2)
|
||||
*/
|
||||
sec_dsa_mexp_mont(size, c, crtCfg->dP, crtCfg->p, crtCfg->invR_p, crtCfg->primeN_p, m1);
|
||||
sec_dsa_mexp_mont(size, c, crtCfg->dQ, crtCfg->q, crtCfg->invR_q, crtCfg->primeN_q, m2);
|
||||
|
||||
|
|
|
|||
|
|
@ -930,7 +930,7 @@ int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle)
|
|||
|
||||
__WEAK void sec_ecdsa_verify_suss_callback(uint32_t state, uint8_t is_en)
|
||||
{
|
||||
|
||||
|
||||
}
|
||||
|
||||
int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *r, const uint32_t *s)
|
||||
|
|
@ -1240,7 +1240,7 @@ int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t
|
|||
#endif
|
||||
|
||||
sec_ecdsa_verify_suss_callback(SEC_CODEPATH_STATE_SIGN, 1);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -384,4 +384,4 @@ void sec_hash_isr(void)
|
|||
void SEC_SHA_IRQ(void)
|
||||
{
|
||||
sec_hash_isr();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -491,4 +491,4 @@ void SPI1_IRQ_Function()
|
|||
{
|
||||
spi_isr(&spix_device[SPI1_INDEX]);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -694,21 +694,21 @@ __STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
|
|||
|
||||
#if 0
|
||||
|
||||
if(value)
|
||||
{
|
||||
value = value + (uint64_t)ticks;
|
||||
CORET->MTIMECMPH0 = (uint32_t)(value >> 32);
|
||||
CORET->MTIMECMPL0 = (uint32_t)value;
|
||||
}
|
||||
else
|
||||
{
|
||||
uint64_t result;
|
||||
__ASM volatile("csrr %0, 0xc01" : "=r"(result));
|
||||
if(value)
|
||||
{
|
||||
value = value + (uint64_t)ticks;
|
||||
CORET->MTIMECMPH0 = (uint32_t)(value >> 32);
|
||||
CORET->MTIMECMPL0 = (uint32_t)value;
|
||||
}
|
||||
else
|
||||
{
|
||||
uint64_t result;
|
||||
__ASM volatile("csrr %0, 0xc01" : "=r"(result));
|
||||
|
||||
value = result + (uint64_t)ticks;
|
||||
CORET->MTIMECMPH0 = (uint32_t)(value >> 32);
|
||||
CORET->MTIMECMPL0 = (uint32_t)value;
|
||||
}
|
||||
value = result + (uint64_t)ticks;
|
||||
CORET->MTIMECMPH0 = (uint32_t)(value >> 32);
|
||||
CORET->MTIMECMPL0 = (uint32_t)value;
|
||||
}
|
||||
|
||||
#else
|
||||
value = value + (uint64_t)ticks;
|
||||
|
|
|
|||
|
|
@ -178,45 +178,45 @@
|
|||
#define asm __asm
|
||||
|
||||
#define read_fpu(reg) ({ unsigned long __tmp; \
|
||||
asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \
|
||||
__tmp; })
|
||||
asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \
|
||||
__tmp; })
|
||||
|
||||
#define write_fpu(reg, val) ({ \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \
|
||||
else \
|
||||
asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); })
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \
|
||||
else \
|
||||
asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); })
|
||||
|
||||
#define read_csr(reg) ({ unsigned long __tmp; \
|
||||
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
|
||||
__tmp; })
|
||||
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
|
||||
__tmp; })
|
||||
|
||||
#define write_csr(reg, val) ({ \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
|
||||
else \
|
||||
asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
|
||||
else \
|
||||
asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
|
||||
|
||||
#define swap_csr(reg, val) ({ unsigned long __tmp; \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
|
||||
else \
|
||||
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
|
||||
__tmp; })
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
|
||||
else \
|
||||
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
|
||||
__tmp; })
|
||||
|
||||
#define set_csr(reg, bit) ({ unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; })
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; })
|
||||
|
||||
#define clear_csr(reg, bit) ({ unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; })
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; })
|
||||
|
||||
#define rdtime() read_csr(time)
|
||||
#define rdcycle() read_csr(cycle)
|
||||
|
|
|
|||
|
|
@ -44,8 +44,8 @@ extern "C"
|
|||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#define F64_MAX ((float64_t)DBL_MAX)
|
||||
#define F32_MAX ((float32_t)FLT_MAX)
|
||||
|
|
@ -396,9 +396,9 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
|||
* @brief definition to pack four 8 bit values.
|
||||
*/
|
||||
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
|
||||
(((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
|
||||
(((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
|
||||
(((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
|
||||
(((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
|
||||
(((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
|
||||
(((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
|
||||
|
||||
/**
|
||||
* @brief Clips Q63 to Q31 values.
|
||||
|
|
|
|||
|
|
@ -4038,7 +4038,7 @@ csi_status csi_sqrt_q15(
|
|||
- \ref CSI_MATH_SUCCESS : input value is positive
|
||||
- \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
#ifdef __riscv
|
||||
#ifdef __riscv
|
||||
__STATIC_FORCEINLINE csi_status csi_sqrt_f32(
|
||||
float32_t in,
|
||||
float32_t * pOut)
|
||||
|
|
@ -4075,12 +4075,12 @@ csi_status csi_sqrt_f32(
|
|||
|
||||
|
||||
/**
|
||||
@brief Q31 square root function.
|
||||
@param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
|
||||
@param[out] pOut points to square root of input value
|
||||
@return execution status
|
||||
- \ref CSI_MATH_SUCCESS : input value is positive
|
||||
- \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
@brief Q31 square root function.
|
||||
@param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
|
||||
@param[out] pOut points to square root of input value
|
||||
@return execution status
|
||||
- \ref CSI_MATH_SUCCESS : input value is positive
|
||||
- \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
csi_status csi_sqrt_q31(
|
||||
q31_t in,
|
||||
|
|
@ -4102,19 +4102,19 @@ void csi_vsqrt_f32(
|
|||
uint16_t len);
|
||||
|
||||
void csi_vsqrt_q15(
|
||||
q15_t * pIn,
|
||||
q15_t * pOut,
|
||||
uint16_t len);
|
||||
q15_t * pIn,
|
||||
q15_t * pOut,
|
||||
uint16_t len);
|
||||
|
||||
void csi_vsqrt_q31(
|
||||
q31_t * pIn,
|
||||
q31_t * pOut,
|
||||
uint16_t len);
|
||||
q31_t * pIn,
|
||||
q31_t * pOut,
|
||||
uint16_t len);
|
||||
|
||||
void csi_vsqrt_q7(
|
||||
q7_t * pIn,
|
||||
q7_t * pOut,
|
||||
uint16_t len);
|
||||
q7_t * pIn,
|
||||
q7_t * pOut,
|
||||
uint16_t len);
|
||||
|
||||
|
||||
#else
|
||||
|
|
@ -4129,9 +4129,9 @@ __STATIC_FORCEINLINE void csi_vsqrt_f32(
|
|||
}
|
||||
|
||||
__STATIC_FORCEINLINE void csi_vsqrt_q15(
|
||||
q15_t * pIn,
|
||||
q15_t * pOut,
|
||||
uint16_t len
|
||||
q15_t * pIn,
|
||||
q15_t * pOut,
|
||||
uint16_t len
|
||||
)
|
||||
{
|
||||
for (int i = 0; i < len; i++) {
|
||||
|
|
@ -4139,9 +4139,9 @@ __STATIC_FORCEINLINE void csi_vsqrt_q15(
|
|||
}
|
||||
}
|
||||
__STATIC_FORCEINLINE void csi_vsqrt_q31(
|
||||
q31_t * pIn,
|
||||
q31_t * pOut,
|
||||
uint16_t len
|
||||
q31_t * pIn,
|
||||
q31_t * pOut,
|
||||
uint16_t len
|
||||
)
|
||||
{
|
||||
for (int i = 0; i < len; i++) {
|
||||
|
|
|
|||
|
|
@ -112,10 +112,10 @@ rv_hart_switch_mode_from_M(uintptr_t arg0, uintptr_t arg1,
|
|||
write_csr(satp, 0);
|
||||
} else if (next_mode == PRV_U) {
|
||||
/* un-implemented
|
||||
write_csr(utvec, next_addr);
|
||||
write_csr(uscratch, 0);
|
||||
write_csr(uie, 0);
|
||||
*/
|
||||
write_csr(utvec, next_addr);
|
||||
write_csr(uscratch, 0);
|
||||
write_csr(uie, 0);
|
||||
*/
|
||||
}
|
||||
|
||||
register unsigned long a0 __asm("a0") = arg0;
|
||||
|
|
|
|||
|
|
@ -80,13 +80,13 @@ void start_load(void)
|
|||
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
pDest = &__bss_start__;
|
||||
|
||||
for (; pDest < &__bss_end__;) {
|
||||
|
|
|
|||
|
|
@ -74,13 +74,13 @@ void start_load(void)
|
|||
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
pDest = &__bss_start__;
|
||||
|
||||
for (; pDest < &__bss_end__;) {
|
||||
|
|
|
|||
|
|
@ -29,58 +29,58 @@ void Interrupt_Default_Handler(void)
|
|||
}
|
||||
|
||||
#if 0
|
||||
extern void Trap_Handler(void);
|
||||
extern void Interrupt_Handler(void);
|
||||
void Interrupt_Handler_Stub(void);
|
||||
extern void Trap_Handler(void);
|
||||
extern void Interrupt_Handler(void);
|
||||
void Interrupt_Handler_Stub(void);
|
||||
|
||||
void clic_msip_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void clic_mtimer_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void clic_mext_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void clic_csoft_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void L1C_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void L1C_BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void RF_TOP_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void RF_TOP_INT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SDIO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void DMA_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_GMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_CDET_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_PKA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_TRNG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_SHA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void DMA_ALL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void IRTX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void IRRX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SF_CTRL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void GPADC_DMA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void EFUSE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SPI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void UART0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void UART1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void I2C_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void PWM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void TIMER_CH0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void TIMER_CH1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void TIMER_WDT_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void GPIO_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void PDS_WAKEUP_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void HBN_OUT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void HBN_OUT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BOR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void WIFI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BZ_PHY_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BLE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_TXRX_TIMER_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_TXRX_MISC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_RX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_TX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_GEN_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_PORT_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void WIFI_IPC_PUBLIC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void clic_msip_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void clic_mtimer_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void clic_mext_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void clic_csoft_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void L1C_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void L1C_BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void RF_TOP_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void RF_TOP_INT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SDIO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void DMA_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_GMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_CDET_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_PKA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_TRNG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SEC_SHA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void DMA_ALL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void IRTX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void IRRX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SF_CTRL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void GPADC_DMA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void EFUSE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void SPI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void UART0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void UART1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void I2C_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void PWM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void TIMER_CH0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void TIMER_CH1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void TIMER_WDT_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void GPIO_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void PDS_WAKEUP_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void HBN_OUT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void HBN_OUT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BOR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void WIFI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BZ_PHY_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void BLE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_TXRX_TIMER_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_TXRX_MISC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_RX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_TX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_GEN_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void MAC_PORT_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
void WIFI_IPC_PUBLIC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler")));
|
||||
#endif
|
||||
|
||||
const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = {
|
||||
|
|
|
|||
|
|
@ -80,13 +80,13 @@ void start_load(void)
|
|||
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
pDest = &__bss_start__;
|
||||
|
||||
for (; pDest < &__bss_end__;) {
|
||||
|
|
|
|||
|
|
@ -450,8 +450,8 @@ typedef struct {
|
|||
Auido_VAD_IRQ_Source_Type vadIRQSource; /*!< select witch VAD output as final IRQ */
|
||||
BL_Fun_Type vadNoisyBufferMonitorEnable; /*!< enable or not noisy buffer monitor */
|
||||
Auido_VAD_NoisyBufferLen_Type vadNoisyBufferLen; /*!< noise buffer length control */
|
||||
Auido_VAD_NoisyBufferMonitor_Type vadNoisyBufferMonitor; /*!< this monit function is designed in case that VAD is locked into active state and noise buffer
|
||||
no longer refreshes itself. this will happen when audio-background-noise suddenly changes from a
|
||||
Auido_VAD_NoisyBufferMonitor_Type vadNoisyBufferMonitor; /*!< this monit function is designed in case that VAD is locked into active state and noise buffer
|
||||
no longer refreshes itself. this will happen when audio-background-noise suddenly changes from a
|
||||
relative low level to a much higher one */
|
||||
uint32_t noisyBufferThr; /*!< vad_noise_th */
|
||||
uint8_t noisyBufferDiscardNumber; /*!< noise buffer discard number: */
|
||||
|
|
@ -461,9 +461,9 @@ typedef struct {
|
|||
BL_Fun_Type vadNoisyMaxLimitEnable; /*!< noise threshold max limitation enable signal */
|
||||
uint16_t vadNoisyMinLimit; /*!< noise threshold min limitation */
|
||||
BL_Fun_Type vadNoisyMinLimitEnable; /*!< noise threshold min limitation enable signal */
|
||||
uint16_t vadSmoothRise; /*!< VAD output debouce, remove the positive pulse whose width is smaller than Register Value, the
|
||||
uint16_t vadSmoothRise; /*!< VAD output debouce, remove the positive pulse whose width is smaller than Register Value, the
|
||||
real debouce time = Resister Vale * framing-shift */
|
||||
uint16_t vadSmoothFall; /*!< VAD output debouce, remove the negative pulse whose width is smaller than Register Value, the
|
||||
uint16_t vadSmoothFall; /*!< VAD output debouce, remove the negative pulse whose width is smaller than Register Value, the
|
||||
real debouce time = Resister Vale * framing-shift */
|
||||
} Audio_VAD_Cfg_Type;
|
||||
|
||||
|
|
@ -491,7 +491,7 @@ typedef struct {
|
|||
uint8_t agc_noise_enter_time_ms; /*!< agc noise enter time //default 0 NORMAL_SILENCE_DEBOUNCE_TIME_MS 0/1/2/4/8/16/32/64/96/128 */
|
||||
uint8_t agc_noise_exit_time_ms; /*!< agc noise exit time(ms) //default 0 SILENCE_NORMAL_DEBOUNCE_TIME_MS 0/1/2/4/8/16/32/64/96/128 */
|
||||
uint8_t agc_dbv_settle_time; /*!< agc dbv settle time */
|
||||
Audio_AGC_Src_Type agc_src_select; /*!< agc source select 0 ch0 absolute value, 1 ch1 absolute value, 2 ch2 absolute value, 3 maximum
|
||||
Audio_AGC_Src_Type agc_src_select; /*!< agc source select 0 ch0 absolute value, 1 ch1 absolute value, 2 ch2 absolute value, 3 maximum
|
||||
value of ch0/1/2 */
|
||||
Audio_AGC_Detect_Mode agc_detect_mode; /*!< 0 detect by peak, 1 detect by average */
|
||||
uint8_t agc_attack_time; /*!< agc peak filter attack time */
|
||||
|
|
|
|||
|
|
@ -333,7 +333,7 @@ typedef struct {
|
|||
DSP2_MISC_Active_Level_Type hSyncLevel; /*!< Input H-Sync active level */
|
||||
DSP2_MISC_Active_Level_Type vSyncLevel; /*!< Input V-Sync active level */
|
||||
DSP2_MISC_2X_Data_Order_Type dataOrder; /*!< Input data order */
|
||||
uint16_t fifoThreshold; /*!< Fifo threshold for each DVP line to start to
|
||||
uint16_t fifoThreshold; /*!< Fifo threshold for each DVP line to start to
|
||||
output,((Width-Fifo_th)*T_in*2)<(Width*T_out)<((Width-Fifo_th)*T_in*2+Blank*T_in) */
|
||||
}DSP2_MISC_2X_Cfg_Type;
|
||||
|
||||
|
|
|
|||
|
|
@ -38,9 +38,9 @@ enum {
|
|||
UHS_LATENCY_CODE_200 = 3, //"7"
|
||||
};
|
||||
|
||||
// function call
|
||||
void uhs_phy_init(uint32_t datarate);
|
||||
// function call
|
||||
void uhs_phy_init(uint32_t datarate);
|
||||
void uhs_phy_pwr_down(void);
|
||||
void soft_reset(void);
|
||||
|
||||
#endif // __UHS_PHY_H__
|
||||
#endif // __UHS_PHY_H__
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ void CAN_Mode_Set(CAN_MODE_Type type, CAN_MODE_VALUE_Type value)
|
|||
/* Set mode value */
|
||||
tmpVal = BL_RD_REG(CAN_BASE, CAN_MODE);
|
||||
tmpVal &= ~(1 << type);
|
||||
tmpVal |= (value << type);
|
||||
tmpVal |= (value << type);
|
||||
|
||||
/* Write back */
|
||||
BL_WR_REG(CAN_BASE, CAN_MODE, tmpVal);
|
||||
|
|
@ -244,7 +244,7 @@ BL_Err_Type CAN_Transmit(const CAN_CFG_Type *cfg)
|
|||
uint32_t tmpVal;
|
||||
uint32_t i;
|
||||
volatile uint32_t *pData;
|
||||
|
||||
|
||||
/* Check the parameters */
|
||||
CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->dataAddr));
|
||||
CHECK_PARAM(IS_CAN_FRAME_TYPE(cfg->frameType));
|
||||
|
|
|
|||
|
|
@ -102,11 +102,11 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t
|
|||
case GLB_XTAL_24M:
|
||||
/* 960000000 */
|
||||
vcoFreq = tmpVal / calculationDiv * 24 * 1000 * 1000;
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_32M:
|
||||
/* 960000000 */
|
||||
vcoFreq = tmpVal / calculationDiv * 32 * 1000 * (1000 / 2);
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_38P4M:
|
||||
/* 960000000 */
|
||||
vcoFreq = tmpVal / calculationDiv * 384 * 100 * (1000 / 2);
|
||||
|
|
@ -122,7 +122,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t
|
|||
case GLB_XTAL_RC32M:
|
||||
/* 960000000 */
|
||||
vcoFreq = tmpVal / calculationDiv * 32 * 1000 * (1000 / 2);
|
||||
break;
|
||||
break;
|
||||
default:
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -156,14 +156,14 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t
|
|||
case GLB_XTAL_24M:
|
||||
/* 480000000;399996000;379998000 */
|
||||
vcoFreq = 24 * 1000 * tmpVal / calculationDiv * (1000 / 2);
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_32M:
|
||||
/* 480000000;400000000;380000000 */
|
||||
vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_38P4M:
|
||||
/* 480000000;399998250;379996750 */
|
||||
vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
|
||||
vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
|
||||
break;
|
||||
case GLB_XTAL_40M:
|
||||
/* 480000000;400000000;380000000 */
|
||||
|
|
@ -176,7 +176,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t
|
|||
case GLB_XTAL_RC32M:
|
||||
/* 480000000;400000000;380000000 */
|
||||
vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
|
||||
break;
|
||||
break;
|
||||
default:
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -216,14 +216,14 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL
|
|||
case GLB_XTAL_24M:
|
||||
/* 442365000;451582000 */
|
||||
vcoFreq = 24 * 1000 * tmpVal / calculationDiv * (1000 / 2);
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_32M:
|
||||
/* 442367000;451582000 */
|
||||
vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_38P4M:
|
||||
/* 442364000;451579500; */
|
||||
vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
|
||||
vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
|
||||
break;
|
||||
case GLB_XTAL_40M:
|
||||
/* 442368000;451582000 */
|
||||
|
|
@ -236,7 +236,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL
|
|||
case GLB_XTAL_RC32M:
|
||||
/* 442367000;451582000 */
|
||||
vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
|
||||
break;
|
||||
break;
|
||||
default:
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -285,7 +285,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output()
|
|||
tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG1), CCI_AUPLL_POSTDIV);
|
||||
|
||||
return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1) / tmpVal;
|
||||
|
||||
|
||||
}
|
||||
|
||||
__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
|
||||
|
|
@ -306,14 +306,14 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
|
|||
case GLB_XTAL_24M:
|
||||
/* 1500000000 */
|
||||
vcoFreq = 24 * 1000 * tmpVal / calculationDiv * 1000;
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_32M:
|
||||
/* 1500000000 */
|
||||
vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000 / 2);
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_38P4M:
|
||||
/* 1500000000 */
|
||||
vcoFreq = 384 * 50 * tmpVal / calculationDiv * (2000 / 2);
|
||||
vcoFreq = 384 * 50 * tmpVal / calculationDiv * (2000 / 2);
|
||||
break;
|
||||
case GLB_XTAL_40M:
|
||||
/* 1500000000 */
|
||||
|
|
@ -326,7 +326,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
|
|||
case GLB_XTAL_RC32M:
|
||||
/* 1500000000 */
|
||||
vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000 / 2);
|
||||
break;
|
||||
break;
|
||||
default:
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -360,14 +360,14 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
|
|||
case GLB_XTAL_24M:
|
||||
/* 2299992000;2199996000;2100000000;1999992000;1599996000;1500000000;1399992000;1065996000;799992000;666996000;399996000 */
|
||||
vcoFreq = 24 * 500 * tmpVal / calculationDiv * 2000;
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_32M:
|
||||
/* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1066000000;800000000;667000000;400000000 */
|
||||
vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000 / 2);
|
||||
break;
|
||||
break;
|
||||
case GLB_XTAL_38P4M:
|
||||
/* 2299996000;2199992000;2100000000;1999996000;1599992000;1500000000;1399996000;1065992000;799996000;666992000;399992000 */
|
||||
vcoFreq = 384 * 25 * tmpVal / calculationDiv * (4000 / 2);
|
||||
vcoFreq = 384 * 25 * tmpVal / calculationDiv * (4000 / 2);
|
||||
break;
|
||||
case GLB_XTAL_40M:
|
||||
/* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1065996000;800000000;666992000;400000000 */
|
||||
|
|
@ -380,7 +380,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
|
|||
case GLB_XTAL_RC32M:
|
||||
/* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1066000000;800000000;667000000;400000000 */
|
||||
vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000 / 2);
|
||||
break;
|
||||
break;
|
||||
default:
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -1146,7 +1146,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MIPI_Div_Val(void)
|
|||
}
|
||||
|
||||
__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_MIPI_Clk_Mux_Output(void)
|
||||
{
|
||||
{
|
||||
return Clock_Get_MIPI_PLL_Output();
|
||||
}
|
||||
|
||||
|
|
@ -1809,7 +1809,7 @@ uint32_t ATTR_CLOCK_SECTION Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
|
|||
|
||||
/*!< PSRAMA clock */
|
||||
case BL_PERIPHERAL_CLOCK_PSRAMA:
|
||||
return Clock_Get_UHS_PLL_Output();
|
||||
return Clock_Get_UHS_PLL_Output();
|
||||
|
||||
/*!< PSRAMB clock */
|
||||
case BL_PERIPHERAL_CLOCK_PSRAMB:
|
||||
|
|
|
|||
|
|
@ -692,7 +692,7 @@ void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliLis
|
|||
|
||||
if (DMA_Channel_Is_Busy(dmaPpBuf->dmaId, dmaPpBuf->dmaChan) == RESET) {
|
||||
/* DMA stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable)
|
||||
or has already stopped before this function is called */
|
||||
or has already stopped before this function is called */
|
||||
if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) {
|
||||
/* DMA has already stopped before this function is called */
|
||||
DMA_LLI_PpBuf_Start_New_Transmit(dmaPpBuf);
|
||||
|
|
|
|||
|
|
@ -483,7 +483,7 @@ void DSI_Set_VSA_VFP(DSI_ID_Type dsiId, uint8_t vsa, uint8_t vfp)
|
|||
|
||||
/* Check the parameters */
|
||||
CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));
|
||||
|
||||
|
||||
tmpVal = BL_RD_REG(DSIx, DSI_CONFIG);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VFP, vfp);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VSA, vsa);
|
||||
|
|
@ -860,7 +860,7 @@ void DSI_PHY_Set_Clock_Lane(DSI_ID_Type dsiId, DSI_Clock_Lane_Opt_Type opt)
|
|||
if (opt & DSI_CLOCK_LANE_OPT_HS_REQ) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXREQUESTHS);
|
||||
}
|
||||
|
||||
|
||||
if (opt & DSI_CLOCK_LANE_OPT_HS_EXIT) {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_TXREQUESTHS);
|
||||
}
|
||||
|
|
@ -914,7 +914,7 @@ void DSI_PHY_HS_Mode_Stop(DSI_ID_Type dsiId)
|
|||
uint32_t tmpVal;
|
||||
uint32_t DSIx = dsiAddr[dsiId];
|
||||
DSI_Lane_State_Type state = 0;
|
||||
|
||||
|
||||
/* Check the parameters */
|
||||
CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));
|
||||
|
||||
|
|
@ -1015,14 +1015,14 @@ BL_Err_Type DSI_LPDT_Start_Tx(DSI_ID_Type dsiId)
|
|||
|
||||
/****************************************************************************//**
|
||||
* @brief DSI wait for send done
|
||||
*
|
||||
*
|
||||
* @param dsiId: DSI ID type
|
||||
*
|
||||
*
|
||||
* @return SUCCESS
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type DSI_Wait_For_Esc_Tx_Done(DSI_ID_Type dsiId)
|
||||
{
|
||||
{
|
||||
DSI_INT_Type intStatus;
|
||||
|
||||
/* wait for Tx finished */
|
||||
|
|
|
|||
|
|
@ -372,12 +372,12 @@ void DSP2_Set_TG_Cfg(const DSP2_TG_Cfg_Type *cfg)
|
|||
dsp2_tg_reg->dvp_mode.BF.fhblk_line_on_w = DSP2_FHBLK_LINE_OFF;
|
||||
|
||||
/* note: if vsync invert, vcnt reset mode set 0, means falling
|
||||
else if vsync not invert, vcont reset mode set 1, also means falling
|
||||
this value will not open to user now.
|
||||
*/
|
||||
else if vsync not invert, vcont reset mode set 1, also means falling
|
||||
this value will not open to user now.
|
||||
*/
|
||||
if (DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE == cfg->sync_mode_value) {
|
||||
/* hcnt reset in rising edge, so H blanking is put after valid line
|
||||
vcnt reset mode must be 0, to make sure vcnt is reset to 4095 instead of 0. */
|
||||
vcnt reset mode must be 0, to make sure vcnt is reset to 4095 instead of 0. */
|
||||
dsp2_tg_reg->dvp_mode.BF.hcnt_rst_mode_w = DSP2_HCNT_RST_RISING;
|
||||
dsp2_tg_reg->dvp_mode.BF.vcnt_rst_mode_w = DSP2_VCNT_RST_RISING;
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -100,12 +100,12 @@ static intCallback_Type *dsp2MiscIntCbfArra[DSP2_MISC_INT_ALL] = {
|
|||
void DSP2_MISC_2X_Init(DSP2_MISC_2X_Cfg_Type *dvp2xCfg)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
|
||||
/* Check the parameters */
|
||||
CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(dvp2xCfg->hSyncLevel));
|
||||
CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(dvp2xCfg->vSyncLevel));
|
||||
CHECK_PARAM(IS_DSP2_MISC_2X_DATA_ORDER_TYPE(dvp2xCfg->dataOrder));
|
||||
|
||||
|
||||
tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_HS_INV, dvp2xCfg->hSyncLevel);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_VS_INV, dvp2xCfg->vSyncLevel);
|
||||
|
|
@ -125,7 +125,7 @@ void DSP2_MISC_2X_Init(DSP2_MISC_2X_Cfg_Type *dvp2xCfg)
|
|||
void DSP2_MISC_2X_Enable(void)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
|
||||
tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG);
|
||||
BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DVPAS_ENABLE));
|
||||
}
|
||||
|
|
@ -141,7 +141,7 @@ void DSP2_MISC_2X_Enable(void)
|
|||
void DSP2_MISC_2X_Disable(void)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
|
||||
tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG);
|
||||
BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DVPAS_ENABLE));
|
||||
}
|
||||
|
|
@ -516,10 +516,10 @@ void DSP2_MISC_Scaler_Shadow(DSP2_MISC_Scaler_ID_Type scalerId)
|
|||
{
|
||||
uint32_t tmpVal;
|
||||
uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId;
|
||||
|
||||
|
||||
/* Check the parameters */
|
||||
CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId));
|
||||
|
||||
|
||||
tmpVal = BL_RD_WORD(scalerAddr);
|
||||
BL_WR_WORD(scalerAddr, BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SCLRA_SW_SH));
|
||||
}
|
||||
|
|
@ -1216,11 +1216,11 @@ void DSP2_MISC_SEOF_Set_Edge(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Edge_Typ
|
|||
void DSP2_MISC_Reshape_Init(DSP2_MISC_Reshape_Cfg_Type *reshapeCfg)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
|
||||
/* Check the parameters */
|
||||
CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(reshapeCfg->hSyncLevel));
|
||||
CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(reshapeCfg->vSyncLevel));
|
||||
|
||||
|
||||
tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_TGL_COUNT, reshapeCfg->vsyncNumber & 0x1f);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_HSYNC_INV, reshapeCfg->hSyncLevel);
|
||||
|
|
@ -1240,7 +1240,7 @@ void DSP2_MISC_Reshape_Init(DSP2_MISC_Reshape_Cfg_Type *reshapeCfg)
|
|||
void DSP2_MISC_Reshape_Counter_Clear(void)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
|
||||
tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE);
|
||||
BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_RSHP_CLR));
|
||||
}
|
||||
|
|
@ -1273,7 +1273,7 @@ void DSP2_MISC_DE_As_Hsync(BL_Fun_Type enable)
|
|||
void DSP2_MISC_TSRC_Source_Select(DSP2_MISC_TSRC_Source_Type sourceType)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
|
||||
tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DSP2_DTSRC_SRC, sourceType);
|
||||
BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL, tmpVal);
|
||||
|
|
|
|||
|
|
@ -178,7 +178,7 @@ void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_1(void)
|
|||
}
|
||||
|
||||
/* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |
|
||||
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
|
||||
(EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
|
||||
|
|
@ -267,7 +267,7 @@ void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_1(void)
|
|||
|
||||
/* Select auto mode and select ef clock */
|
||||
/* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |
|
||||
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
|
||||
(EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
|
||||
|
|
@ -288,7 +288,7 @@ void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_1(void)
|
|||
|
||||
/* Program */
|
||||
/* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |
|
||||
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
|
||||
(EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
|
||||
|
|
@ -403,7 +403,7 @@ void EF_Ctrl_Load_Efuse_R1(void)
|
|||
|
||||
/* Trigger read */
|
||||
/* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |
|
||||
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
|
||||
(EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
|
||||
|
|
@ -443,7 +443,7 @@ void EF_Ctrl_Load_Efuse_R1(void)
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|||
|
||||
/* Switch to AHB clock since often read efuse data after load */
|
||||
/* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
so we select it(them) in ef_if_ctrl_0 */
|
||||
tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |
|
||||
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
|
||||
(EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
|
||||
|
|
@ -1328,7 +1328,7 @@ void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8
|
|||
uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C);
|
||||
uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80);
|
||||
|
||||
/* slot_w0~slot_w3,slot_w11 in ef_data0
|
||||
/* slot_w0~slot_w3,slot_w11 in ef_data0
|
||||
slot_w4~slot_w10,in ef_data1 */
|
||||
|
||||
if ((index <= 3) || (index == 11)) {
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ static void EMAC_SetMACAddress(EMAC_ID_Type emacId, uint8_t macAddr[6])
|
|||
void EMAC_Phy_SetAddress(EMAC_ID_Type emacId, uint16_t phyAddress)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
uint32_t EMACx = emacAddr[emacId];
|
||||
uint32_t EMACx = emacAddr[emacId];
|
||||
|
||||
/* Set Phy Address */
|
||||
tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS);
|
||||
|
|
@ -134,7 +134,7 @@ void EMAC_Phy_SetAddress(EMAC_ID_Type emacId, uint16_t phyAddress)
|
|||
void EMAC_Phy_Set_Full_Duplex(EMAC_ID_Type emacId, uint8_t fullDuplex)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
uint32_t EMACx = emacAddr[emacId];
|
||||
uint32_t EMACx = emacAddr[emacId];
|
||||
|
||||
/* Set MAC duplex config */
|
||||
tmpVal = BL_RD_REG(EMACx, EMAC_MODE);
|
||||
|
|
@ -773,7 +773,7 @@ BL_Err_Type EMAC_GetFramLen(EMAC_ID_Type emacId, uint16_t * max, uint16_t *min)
|
|||
BL_Err_Type EMAC_GetBD(EMAC_ID_Type emacId, uint32_t *bd)
|
||||
{
|
||||
uint32_t EMACx = emacAddr[emacId];
|
||||
|
||||
|
||||
*bd = BL_RD_REG(EMACx, EMAC_TX_BD_NUM);
|
||||
|
||||
return SUCCESS;
|
||||
|
|
|
|||
|
|
@ -5819,17 +5819,17 @@ BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Typ
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL);
|
||||
GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk);
|
||||
GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 1);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -5845,17 +5845,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL);
|
||||
GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk);
|
||||
GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 1);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -5871,17 +5871,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, cons
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL);
|
||||
GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk);
|
||||
GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 1);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -5897,17 +5897,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL);
|
||||
GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk);
|
||||
GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 1);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -5924,14 +5924,14 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t di
|
|||
{
|
||||
uint32_t REG_PLL_BASE_ADDRESS = 0;
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
|
||||
REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;
|
||||
|
||||
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -5947,17 +5947,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t di
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);
|
||||
GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);
|
||||
GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 1);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2377,17 +2377,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Clr_EMI_Reset_Gate(void)
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL);
|
||||
GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk);
|
||||
GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 0);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -2403,17 +2403,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL);
|
||||
GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk);
|
||||
GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 0);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -2429,17 +2429,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, cons
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL);
|
||||
GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk);
|
||||
GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 0);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -2455,17 +2455,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL);
|
||||
GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk);
|
||||
GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 0);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -2482,14 +2482,14 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t di
|
|||
{
|
||||
uint32_t REG_PLL_BASE_ADDRESS = 0;
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
|
||||
REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;
|
||||
|
||||
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -2505,17 +2505,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t di
|
|||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)
|
||||
{
|
||||
GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
|
||||
if (xtalType == GLB_XTAL_RC32M) {
|
||||
refClk = GLB_PLL_REFCLK_RC32M;
|
||||
} else {
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
}
|
||||
|
||||
|
||||
GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);
|
||||
GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);
|
||||
GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 0);
|
||||
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -332,7 +332,7 @@ void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cf
|
|||
GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2C);
|
||||
} else if (I2C1_ID == i2cNo) {
|
||||
GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2C1);
|
||||
}
|
||||
}
|
||||
|
||||
/* I2C write config */
|
||||
tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
|
||||
|
|
|
|||
|
|
@ -204,7 +204,7 @@ void IPC_M0_Clear_Int_By_Word(uint32_t src)
|
|||
* @brief CPUx trigger IPC interrupt to M0
|
||||
*
|
||||
* @param src: IPC interrupt source
|
||||
*
|
||||
*
|
||||
* @param cpuxOffset: CPU interrupt offset
|
||||
*
|
||||
* @return None
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ void ISO11898_Mode_Set(ISO11898_MODE_Type type, ISO11898_MODE_VALUE_Type value)
|
|||
/* Set mode value */
|
||||
tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_MODE);
|
||||
tmpVal &= ~(1 << type);
|
||||
tmpVal |= (value << type);
|
||||
tmpVal |= (value << type);
|
||||
|
||||
/* Write back */
|
||||
BL_WR_REG(ISO11898_BASE, ISO11898_MODE, tmpVal);
|
||||
|
|
@ -244,7 +244,7 @@ BL_Err_Type ISO11898_Transmit(const ISO11898_CFG_Type *cfg)
|
|||
uint32_t tmpVal;
|
||||
uint32_t i;
|
||||
volatile uint32_t *pData;
|
||||
|
||||
|
||||
/* Check the parameters */
|
||||
CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->dataAddr));
|
||||
CHECK_PARAM(IS_ISO11898_FRAME_TYPE(cfg->frameType));
|
||||
|
|
|
|||
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Reference in New Issue