[bsp][tms320f28379d] Fix c28x_getc() problem
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@ -147,8 +147,25 @@ static int c28x_putc(struct rt_serial_device *serial, char c)
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static int c28x_getc(struct rt_serial_device *serial)
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{
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char ch;
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SCI_read(0, &ch, 1);
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return ch;
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if(SCI_read(0, &ch, 1))
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return ch;
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else
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return -1;
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}
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/**
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* Uart common interrupt process. This need add to uart ISR.
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*
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* @param serial serial device
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*/
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static void uart_isr(struct rt_serial_device *serial) {
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struct c28x_uart *uart = (struct c28x_uart *) serial->parent.user_data;
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RT_ASSERT(uart != RT_NULL);
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
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SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear Interrupt flag
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PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ack
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}
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static const struct rt_uart_ops c28x_uart_ops =
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@ -159,6 +176,20 @@ static const struct rt_uart_ops c28x_uart_ops =
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.getc = c28x_getc,
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};
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//
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// sciaRxFifoIsr - SCIA Receive FIFO ISR
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//
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interrupt void sciaRxFifoIsr(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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uart_isr(&uart_obj[0].serial);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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int rt_hw_sci_init(void)
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{
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EALLOW;
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@ -182,8 +213,20 @@ int rt_hw_sci_init(void)
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CpuSysRegs.PCLKCR7.bit.SCI_B = 1;
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CpuSysRegs.PCLKCR7.bit.SCI_C = 1;
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PieVectTable.SCIA_RX_INT = &sciaRxFifoIsr;
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//PieVectTable.SCIA_TX_INT = &sciaTxFifoIsr;
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EDIS;
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//
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// Enable interrupts required for this example
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//
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PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
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PieCtrlRegs.PIEIER9.bit.INTx1 = 1; // PIE Group 9, INT1
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//PieCtrlRegs.PIEIER9.bit.INTx2 = 1; // PIE Group 9, INT2
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IER = 0x100; // Enable CPU INT
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EINT;
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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rt_err_t result = 0;
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@ -202,7 +245,6 @@ int rt_hw_sci_init(void)
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uart_obj[2].name = "scic";
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uart_obj[2].sci_regs = &ScicRegs;
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/* register UART device */
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result = rt_hw_serial_register(&uart_obj[0].serial, uart_obj[0].name,
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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