From 40136146de3db939996dee979ca668e9891a9772 Mon Sep 17 00:00:00 2001 From: Dozingfiretruck <1473454180@qq.com> Date: Fri, 31 Jul 2020 17:57:08 +0800 Subject: [PATCH 1/5] bsp:stm32f407-armfly-v5 --- bsp/stm32/stm32f407-armfly-v5/.config | 351 ++ bsp/stm32/stm32f407-armfly-v5/.gitignore | 42 + bsp/stm32/stm32f407-armfly-v5/Kconfig | 21 + bsp/stm32/stm32f407-armfly-v5/README.md | 125 + bsp/stm32/stm32f407-armfly-v5/SConscript | 15 + bsp/stm32/stm32f407-armfly-v5/SConstruct | 60 + .../applications/SConscript | 12 + .../stm32f407-armfly-v5/applications/main.c | 33 + .../board/CubeMX_Config/.mxproject | 19 + .../board/CubeMX_Config/CubeMX_Config.ioc | 234 ++ .../board/CubeMX_Config/Inc/main.h | 73 + .../CubeMX_Config/Inc/stm32f4xx_hal_conf.h | 443 +++ .../board/CubeMX_Config/Inc/stm32f4xx_it.h | 69 + .../board/CubeMX_Config/Src/main.c | 708 ++++ .../CubeMX_Config/Src/stm32f4xx_hal_msp.c | 721 +++++ .../board/CubeMX_Config/Src/stm32f4xx_it.c | 203 ++ .../CubeMX_Config/Src/system_stm32f4xx.c | 727 +++++ bsp/stm32/stm32f407-armfly-v5/board/Kconfig | 199 ++ .../stm32f407-armfly-v5/board/SConscript | 44 + bsp/stm32/stm32f407-armfly-v5/board/board.c | 61 + bsp/stm32/stm32f407-armfly-v5/board/board.h | 50 + .../board/linker_scripts/link.icf | 28 + .../board/linker_scripts/link.lds | 157 + .../board/linker_scripts/link.sct | 15 + .../stm32f407-armfly-v5/board/ports/fal_cfg.h | 48 + .../board/ports/sdcard_port.c | 62 + .../board/ports/spi_flash_init.c | 31 + .../stm32f407-armfly-v5/figures/board.png | Bin 0 -> 404490 bytes bsp/stm32/stm32f407-armfly-v5/project.ewd | 2834 +++++++++++++++++ bsp/stm32/stm32f407-armfly-v5/project.ewp | 2410 ++++++++++++++ bsp/stm32/stm32f407-armfly-v5/project.eww | 10 + bsp/stm32/stm32f407-armfly-v5/project.uvopt | 162 + bsp/stm32/stm32f407-armfly-v5/project.uvoptx | 191 ++ bsp/stm32/stm32f407-armfly-v5/project.uvproj | 1189 +++++++ bsp/stm32/stm32f407-armfly-v5/project.uvprojx | 753 +++++ bsp/stm32/stm32f407-armfly-v5/rtconfig.h | 173 + bsp/stm32/stm32f407-armfly-v5/rtconfig.py | 150 + bsp/stm32/stm32f407-armfly-v5/template.ewp | 2031 ++++++++++++ bsp/stm32/stm32f407-armfly-v5/template.eww | 10 + bsp/stm32/stm32f407-armfly-v5/template.uvopt | 199 ++ bsp/stm32/stm32f407-armfly-v5/template.uvoptx | 187 ++ bsp/stm32/stm32f407-armfly-v5/template.uvproj | 438 +++ .../stm32f407-armfly-v5/template.uvprojx | 411 +++ 43 files changed, 15699 insertions(+) create mode 100644 bsp/stm32/stm32f407-armfly-v5/.config create mode 100644 bsp/stm32/stm32f407-armfly-v5/.gitignore create mode 100644 bsp/stm32/stm32f407-armfly-v5/Kconfig create mode 100644 bsp/stm32/stm32f407-armfly-v5/README.md create mode 100644 bsp/stm32/stm32f407-armfly-v5/SConscript create mode 100644 bsp/stm32/stm32f407-armfly-v5/SConstruct create mode 100644 bsp/stm32/stm32f407-armfly-v5/applications/SConscript create mode 100644 bsp/stm32/stm32f407-armfly-v5/applications/main.c create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/Kconfig create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/SConscript create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/board.c create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/board.h create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c create mode 100644 bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c create mode 100644 bsp/stm32/stm32f407-armfly-v5/figures/board.png create mode 100644 bsp/stm32/stm32f407-armfly-v5/project.ewd create mode 100644 bsp/stm32/stm32f407-armfly-v5/project.ewp create mode 100644 bsp/stm32/stm32f407-armfly-v5/project.eww create mode 100644 bsp/stm32/stm32f407-armfly-v5/project.uvopt create mode 100644 bsp/stm32/stm32f407-armfly-v5/project.uvoptx create mode 100644 bsp/stm32/stm32f407-armfly-v5/project.uvproj create mode 100644 bsp/stm32/stm32f407-armfly-v5/project.uvprojx create mode 100644 bsp/stm32/stm32f407-armfly-v5/rtconfig.h create mode 100644 bsp/stm32/stm32f407-armfly-v5/rtconfig.py create mode 100644 bsp/stm32/stm32f407-armfly-v5/template.ewp create mode 100644 bsp/stm32/stm32f407-armfly-v5/template.eww create mode 100644 bsp/stm32/stm32f407-armfly-v5/template.uvopt create mode 100644 bsp/stm32/stm32f407-armfly-v5/template.uvoptx create mode 100644 bsp/stm32/stm32f407-armfly-v5/template.uvproj create mode 100644 bsp/stm32/stm32f407-armfly-v5/template.uvprojx diff --git a/bsp/stm32/stm32f407-armfly-v5/.config b/bsp/stm32/stm32f407-armfly-v5/.config new file mode 100644 index 0000000000..13a4d62a3a --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/.config @@ -0,0 +1,351 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +# CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F407ZG=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32f407-armfly-v5/.gitignore b/bsp/stm32/stm32f407-armfly-v5/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32f407-armfly-v5/Kconfig b/bsp/stm32/stm32f407-armfly-v5/Kconfig new file mode 100644 index 0000000000..8cbc7b71a8 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32f407-armfly-v5/README.md b/bsp/stm32/stm32f407-armfly-v5/README.md new file mode 100644 index 0000000000..4f2f74f36b --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/README.md @@ -0,0 +1,125 @@ +# STM32F429 armfly-v5 开发板 BSP 说明 + +## 简介 + +本文档为 STM32F429 armfly-v5 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +armfly-v5 STM32F407 是安富莱推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 168Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F407 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32F407IGT6，主频 168MHz，1024KB FLASH ，196KB RAM +- 外部 RAM：IS61WV102416BLL-10TL（SRAM，20MB，16bit） +- 外部 FLASH：W25Q64BVSSIG（SPI，8MB）、HY27UF081G2A（NAND，128MB） +- 常用外设 + - LED：4个， LED1 - LED4 + - 按键：4个，k1（PI8），K2（PC13），k3（PI11），五向摇杆 +- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口 +- 调试接口，SWD + +开发板更多详细信息请参考【安富莱】 [STM32 v5开发板介绍](http://www.armbbs.cn/forum.php?mod=viewthread&tid=1285)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| USB 转串口 | 支持 | UART1/2 | +| SPI Flash | 支持 | W25Q64BVSSIG 8M FLASH SPI3 | +| MPU6050 | 支持 | 软件 I2C2 | +| SD卡 | 支持 | | +| CAN | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 | +| UART | 支持 | UART1 | +| SPI | 支持 | SPI3 | +| I2C | 支持 | 软件 I2C2 | +| ADC | 支持 | | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| WDT | 支持 | | +| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | +| SDIO | 支持 | | +| PWM | 支持 | | +| USB Device | 暂不支持 | 即将支持 | +| USB Host | 暂不支持 | 即将支持 | +| **扩展模块** | **支持情况** | **备注** | +| ad7606 | 暂不支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 STLink 仿真器下载程序，在通过 STLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Jul 13 2020 + 2006 - 2019 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 暂无 + +## 联系人信息 + +维护人: + +- [Dozingfiretruck](https://gitee.com/Dozingfiretruck), 邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f407-armfly-v5/SConscript b/bsp/stm32/stm32f407-armfly-v5/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32f407-armfly-v5/SConstruct b/bsp/stm32/stm32f407-armfly-v5/SConstruct new file mode 100644 index 0000000000..945cb55a52 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32F4xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f407-armfly-v5/applications/SConscript b/bsp/stm32/stm32f407-armfly-v5/applications/SConscript new file mode 100644 index 0000000000..6f66f7ab73 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32f407-armfly-v5/applications/main.c b/bsp/stm32/stm32f407-armfly-v5/applications/main.c new file mode 100644 index 0000000000..297573866c --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include +#include +#include + +/* defined the LED4 pin: PC2 */ +#define LED0_PIN GET_PIN(C, 2) + +int main(void) +{ + int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000..4638fb8888 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/.mxproject @@ -0,0 +1,19 @@ +[PreviousGenFiles] +HeaderPath=C:/Users/qq147/Desktop/rt-thread/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc +HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; +SourcePath=C:/Users/qq147/Desktop/rt-thread/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src +SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; + +[PreviousUsedIarFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousUsedKeilFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 0000000000..0777302023 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,234 @@ +#MicroXplorer Configuration settings - do not modify +ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_9 +ADC1.IPParameters=Rank-3\#ChannelRegularConversion,master,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,NbrOfConversionFlag +ADC1.NbrOfConversionFlag=1 +ADC1.Rank-3\#ChannelRegularConversion=1 +ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC1.master=1 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +I2S2.ErrorAudioFreq=-0.27 % +I2S2.FullDuplexMode=I2S_FULLDUPLEXMODE_ENABLE +I2S2.IPParameters=Instance,VirtualMode,FullDuplexMode,RealAudioFreq,ErrorAudioFreq +I2S2.Instance=SPI$Index +I2S2.RealAudioFreq=7.978 KHz +I2S2.VirtualMode=I2S_MODE_MASTER +KeepUserPlacement=false +Mcu.Family=STM32F4 +Mcu.IP0=ADC1 +Mcu.IP1=I2S2 +Mcu.IP10=TIM10 +Mcu.IP11=TIM11 +Mcu.IP12=TIM13 +Mcu.IP13=TIM14 +Mcu.IP14=USART1 +Mcu.IP15=USART2 +Mcu.IP2=IWDG +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=RNG +Mcu.IP6=RTC +Mcu.IP7=SDIO +Mcu.IP8=SPI3 +Mcu.IP9=SYS +Mcu.IPNb=16 +Mcu.Name=STM32F407I(E-G)Tx +Mcu.Package=LQFP176 +Mcu.Pin0=PC14-OSC32_IN +Mcu.Pin1=PC15-OSC32_OUT +Mcu.Pin10=PB15 +Mcu.Pin11=PC6 +Mcu.Pin12=PC8 +Mcu.Pin13=PC9 +Mcu.Pin14=PA9 +Mcu.Pin15=PA10 +Mcu.Pin16=PA13 +Mcu.Pin17=PI2 +Mcu.Pin18=PA14 +Mcu.Pin19=PC10 +Mcu.Pin2=PF6 +Mcu.Pin20=PC11 +Mcu.Pin21=PC12 +Mcu.Pin22=PD2 +Mcu.Pin23=PB3 +Mcu.Pin24=PB4 +Mcu.Pin25=PB5 +Mcu.Pin26=VP_IWDG_VS_IWDG +Mcu.Pin27=VP_RNG_VS_RNG +Mcu.Pin28=VP_RTC_VS_RTC_Activate +Mcu.Pin29=VP_SYS_VS_Systick +Mcu.Pin3=PH0-OSC_IN +Mcu.Pin30=VP_TIM10_VS_ClockSourceINT +Mcu.Pin31=VP_TIM11_VS_ClockSourceINT +Mcu.Pin32=VP_TIM13_VS_ClockSourceINT +Mcu.Pin33=VP_TIM14_VS_ClockSourceINT +Mcu.Pin4=PH1-OSC_OUT +Mcu.Pin5=PA2 +Mcu.Pin6=PA3 +Mcu.Pin7=PB1 +Mcu.Pin8=PB12 +Mcu.Pin9=PB13 +Mcu.PinsNb=34 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F407IGTx +MxCube.Version=5.6.1 +MxDb.Version=DB.5.0.60 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB1.Signal=ADCx_IN9 +PB12.Mode=Full_Duplex_Master +PB12.Signal=I2S2_WS +PB13.Locked=true +PB13.Mode=Full_Duplex_Master +PB13.Signal=I2S2_CK +PB15.Mode=Full_Duplex_Master +PB15.Signal=I2S2_SD +PB3.Mode=Full_Duplex_Master +PB3.Signal=SPI3_SCK +PB4.Mode=Full_Duplex_Master +PB4.Signal=SPI3_MISO +PB5.Mode=Full_Duplex_Master +PB5.Signal=SPI3_MOSI +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK +PC14-OSC32_IN.Mode=LSE-External-Oscillator +PC14-OSC32_IN.Signal=RCC_OSC32_IN +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PC6.Mode=Master_Clock_Activated +PC6.Signal=I2S2_MCK +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD +PF6.Signal=S_TIM10_CH1 +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PI2.Locked=true +PI2.Mode=Full_Duplex_Master +PI2.Signal=I2S2_ext_SD +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F407IGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5.27 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_I2S2_Init-I2S2-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_RTC_Init-RTC-false-HAL-true,8-MX_SDIO_SD_Init-SDIO-false-HAL-true,9-MX_SPI3_Init-SPI3-false-HAL-true,10-MX_TIM10_Init-TIM10-false-HAL-true,11-MX_TIM11_Init-TIM11-false-HAL-true,12-MX_TIM13_Init-TIM13-false-HAL-true,13-MX_TIM14_Init-TIM14-false-HAL-true,14-MX_RNG_Init-RNG-false-HAL-true,15-MX_USART2_UART_Init-USART2-false-HAL-true +RCC.48MHZClocksFreq_Value=48000000 +RCC.AHBFreq_Value=168000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=168000000 +RCC.CortexFreq_Value=168000000 +RCC.EthernetFreq_Value=168000000 +RCC.FCLKCortexFreq_Value=168000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=168000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2SClocksFreq_Value=96000000 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=168000000 +RCC.PLLCLKFreq_Value=168000000 +RCC.PLLM=25 +RCC.PLLN=336 +RCC.PLLQ=7 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE +RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE +RCC.RTCFreq_Value=32768 +RCC.RTCHSEDivFreq_Value=12500000 +RCC.SYSCLKFreq_VALUE=168000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.VCOI2SOutputFreq_Value=192000000 +RCC.VCOInputFreq_Value=1000000 +RCC.VCOOutputFreq_Value=336000000 +RCC.VcooutputI2S=96000000 +SH.ADCx_IN9.0=ADC1_IN9,IN9 +SH.ADCx_IN9.ConfNb=1 +SH.S_TIM10_CH1.0=TIM10_CH1,PWM Generation1 CH1 +SH.S_TIM10_CH1.ConfNb=1 +SPI3.CalculateBaudRate=21.0 MBits/s +SPI3.Direction=SPI_DIRECTION_2LINES +SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI3.Mode=SPI_MODE_MASTER +SPI3.VirtualType=VM_MASTER +TIM10.Channel=TIM_CHANNEL_1 +TIM10.IPParameters=Channel +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +USART2.IPParameters=VirtualMode +USART2.VirtualMode=VM_ASYNC +VP_IWDG_VS_IWDG.Mode=IWDG_Activate +VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +VP_RNG_VS_RNG.Mode=RNG_Activate +VP_RNG_VS_RNG.Signal=RNG_VS_RNG +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM10_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM10_VS_ClockSourceINT.Signal=TIM10_VS_ClockSourceINT +VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT +VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +board=custom diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000..71f8e09516 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000..9638f92d62 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -0,0 +1,443 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + #define HAL_ADC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h new file mode 100644 index 0000000000..ab2ae38f21 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000..b2659cd456 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/main.c @@ -0,0 +1,708 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; + +I2S_HandleTypeDef hi2s2; + +IWDG_HandleTypeDef hiwdg; + +RNG_HandleTypeDef hrng; + +RTC_HandleTypeDef hrtc; + +SD_HandleTypeDef hsd; + +SPI_HandleTypeDef hspi3; + +TIM_HandleTypeDef htim10; +TIM_HandleTypeDef htim11; +TIM_HandleTypeDef htim13; +TIM_HandleTypeDef htim14; + +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_ADC1_Init(void); +static void MX_I2S2_Init(void); +static void MX_IWDG_Init(void); +static void MX_RTC_Init(void); +static void MX_SDIO_SD_Init(void); +static void MX_SPI3_Init(void); +static void MX_TIM10_Init(void); +static void MX_TIM11_Init(void); +static void MX_TIM13_Init(void); +static void MX_TIM14_Init(void); +static void MX_RNG_Init(void); +static void MX_USART2_UART_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART1_UART_Init(); + MX_ADC1_Init(); + MX_I2S2_Init(); + MX_IWDG_Init(); + MX_RTC_Init(); + MX_SDIO_SD_Init(); + MX_SPI3_Init(); + MX_TIM10_Init(); + MX_TIM11_Init(); + MX_TIM13_Init(); + MX_TIM14_Init(); + MX_RNG_Init(); + MX_USART2_UART_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.ScanConvMode = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_9; + sConfig.Rank = 1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief I2S2 Initialization Function + * @param None + * @retval None + */ +static void MX_I2S2_Init(void) +{ + + /* USER CODE BEGIN I2S2_Init 0 */ + + /* USER CODE END I2S2_Init 0 */ + + /* USER CODE BEGIN I2S2_Init 1 */ + + /* USER CODE END I2S2_Init 1 */ + hi2s2.Instance = SPI2; + hi2s2.Init.Mode = I2S_MODE_MASTER_TX; + hi2s2.Init.Standard = I2S_STANDARD_PHILIPS; + hi2s2.Init.DataFormat = I2S_DATAFORMAT_16B; + hi2s2.Init.MCLKOutput = I2S_MCLKOUTPUT_ENABLE; + hi2s2.Init.AudioFreq = I2S_AUDIOFREQ_8K; + hi2s2.Init.CPOL = I2S_CPOL_LOW; + hi2s2.Init.ClockSource = I2S_CLOCK_PLL; + hi2s2.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_ENABLE; + if (HAL_I2S_Init(&hi2s2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2S2_Init 2 */ + + /* USER CODE END I2S2_Init 2 */ + +} + +/** + * @brief IWDG Initialization Function + * @param None + * @retval None + */ +static void MX_IWDG_Init(void) +{ + + /* USER CODE BEGIN IWDG_Init 0 */ + + /* USER CODE END IWDG_Init 0 */ + + /* USER CODE BEGIN IWDG_Init 1 */ + + /* USER CODE END IWDG_Init 1 */ + hiwdg.Instance = IWDG; + hiwdg.Init.Prescaler = IWDG_PRESCALER_4; + hiwdg.Init.Reload = 4095; + if (HAL_IWDG_Init(&hiwdg) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN IWDG_Init 2 */ + + /* USER CODE END IWDG_Init 2 */ + +} + +/** + * @brief RNG Initialization Function + * @param None + * @retval None + */ +static void MX_RNG_Init(void) +{ + + /* USER CODE BEGIN RNG_Init 0 */ + + /* USER CODE END RNG_Init 0 */ + + /* USER CODE BEGIN RNG_Init 1 */ + + /* USER CODE END RNG_Init 1 */ + hrng.Instance = RNG; + if (HAL_RNG_Init(&hrng) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RNG_Init 2 */ + + /* USER CODE END RNG_Init 2 */ + +} + +/** + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + +/** + * @brief SPI3 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI3_Init(void) +{ + + /* USER CODE BEGIN SPI3_Init 0 */ + + /* USER CODE END SPI3_Init 0 */ + + /* USER CODE BEGIN SPI3_Init 1 */ + + /* USER CODE END SPI3_Init 1 */ + /* SPI3 parameter configuration*/ + hspi3.Instance = SPI3; + hspi3.Init.Mode = SPI_MODE_MASTER; + hspi3.Init.Direction = SPI_DIRECTION_2LINES; + hspi3.Init.DataSize = SPI_DATASIZE_8BIT; + hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi3.Init.NSS = SPI_NSS_SOFT; + hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi3.Init.TIMode = SPI_TIMODE_DISABLE; + hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi3.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI3_Init 2 */ + + /* USER CODE END SPI3_Init 2 */ + +} + +/** + * @brief TIM10 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM10_Init(void) +{ + + /* USER CODE BEGIN TIM10_Init 0 */ + + /* USER CODE END TIM10_Init 0 */ + + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM10_Init 1 */ + + /* USER CODE END TIM10_Init 1 */ + htim10.Instance = TIM10; + htim10.Init.Prescaler = 0; + htim10.Init.CounterMode = TIM_COUNTERMODE_UP; + htim10.Init.Period = 0; + htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim10) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim10) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim10, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM10_Init 2 */ + + /* USER CODE END TIM10_Init 2 */ + HAL_TIM_MspPostInit(&htim10); + +} + +/** + * @brief TIM11 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM11_Init(void) +{ + + /* USER CODE BEGIN TIM11_Init 0 */ + + /* USER CODE END TIM11_Init 0 */ + + /* USER CODE BEGIN TIM11_Init 1 */ + + /* USER CODE END TIM11_Init 1 */ + htim11.Instance = TIM11; + htim11.Init.Prescaler = 0; + htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + htim11.Init.Period = 0; + htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM11_Init 2 */ + + /* USER CODE END TIM11_Init 2 */ + +} + +/** + * @brief TIM13 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM13_Init(void) +{ + + /* USER CODE BEGIN TIM13_Init 0 */ + + /* USER CODE END TIM13_Init 0 */ + + /* USER CODE BEGIN TIM13_Init 1 */ + + /* USER CODE END TIM13_Init 1 */ + htim13.Instance = TIM13; + htim13.Init.Prescaler = 0; + htim13.Init.CounterMode = TIM_COUNTERMODE_UP; + htim13.Init.Period = 0; + htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim13) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM13_Init 2 */ + + /* USER CODE END TIM13_Init 2 */ + +} + +/** + * @brief TIM14 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM14_Init(void) +{ + + /* USER CODE BEGIN TIM14_Init 0 */ + + /* USER CODE END TIM14_Init 0 */ + + /* USER CODE BEGIN TIM14_Init 1 */ + + /* USER CODE END TIM14_Init 1 */ + htim14.Instance = TIM14; + htim14.Init.Prescaler = 0; + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + htim14.Init.Period = 0; + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM14_Init 2 */ + + /* USER CODE END TIM14_Init 2 */ + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c new file mode 100644 index 0000000000..ab8078f4b0 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -0,0 +1,721 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f4xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PB1 ------> ADC1_IN9 + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + +/** +* @brief I2S MSP Initialization +* This function configures the hardware resources used in this example +* @param hi2s: I2S handle pointer +* @retval None +*/ +void HAL_I2S_MspInit(I2S_HandleTypeDef* hi2s) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hi2s->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + /**I2S2 GPIO Configuration + PB12 ------> I2S2_WS + PB13 ------> I2S2_CK + PB15 ------> I2S2_SD + PC6 ------> I2S2_MCK + PI2 ------> I2S2_ext_SD + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_I2S2ext; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + +/** +* @brief I2S MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hi2s: I2S handle pointer +* @retval None +*/ +void HAL_I2S_MspDeInit(I2S_HandleTypeDef* hi2s) +{ + if(hi2s->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**I2S2 GPIO Configuration + PB12 ------> I2S2_WS + PB13 ------> I2S2_CK + PB15 ------> I2S2_SD + PC6 ------> I2S2_MCK + PI2 ------> I2S2_ext_SD + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_2); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspInit 0 */ + + /* USER CODE END RNG_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RNG_CLK_ENABLE(); + /* USER CODE BEGIN RNG_MspInit 1 */ + + /* USER CODE END RNG_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspDeInit 0 */ + + /* USER CODE END RNG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG_CLK_DISABLE(); + /* USER CODE BEGIN RNG_MspDeInit 1 */ + + /* USER CODE END RNG_MspDeInit 1 */ + } + +} + +/** +* @brief RTC MSP Initialization +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + +/** +* @brief RTC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } + +} + +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspInit 0 */ + + /* USER CODE END SPI3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI3_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI3 GPIO Configuration + PB3 ------> SPI3_SCK + PB4 ------> SPI3_MISO + PB5 ------> SPI3_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI3_MspInit 1 */ + + /* USER CODE END SPI3_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspDeInit 0 */ + + /* USER CODE END SPI3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI3_CLK_DISABLE(); + + /**SPI3 GPIO Configuration + PB3 ------> SPI3_SCK + PB4 ------> SPI3_MISO + PB5 ------> SPI3_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); + + /* USER CODE BEGIN SPI3_MspDeInit 1 */ + + /* USER CODE END SPI3_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspInit 0 */ + + /* USER CODE END TIM10_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM10_CLK_ENABLE(); + /* USER CODE BEGIN TIM10_MspInit 1 */ + + /* USER CODE END TIM10_MspInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspInit 0 */ + + /* USER CODE END TIM11_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM11_CLK_ENABLE(); + /* USER CODE BEGIN TIM11_MspInit 1 */ + + /* USER CODE END TIM11_MspInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspInit 0 */ + + /* USER CODE END TIM13_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM13_CLK_ENABLE(); + /* USER CODE BEGIN TIM13_MspInit 1 */ + + /* USER CODE END TIM13_MspInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspInit 0 */ + + /* USER CODE END TIM14_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM14_CLK_ENABLE(); + /* USER CODE BEGIN TIM14_MspInit 1 */ + + /* USER CODE END TIM14_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspPostInit 0 */ + + /* USER CODE END TIM10_MspPostInit 0 */ + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**TIM10 GPIO Configuration + PF6 ------> TIM10_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF3_TIM10; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM10_MspPostInit 1 */ + + /* USER CODE END TIM10_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspDeInit 0 */ + + /* USER CODE END TIM10_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM10_CLK_DISABLE(); + /* USER CODE BEGIN TIM10_MspDeInit 1 */ + + /* USER CODE END TIM10_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspDeInit 0 */ + + /* USER CODE END TIM11_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM11_CLK_DISABLE(); + /* USER CODE BEGIN TIM11_MspDeInit 1 */ + + /* USER CODE END TIM11_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspDeInit 0 */ + + /* USER CODE END TIM13_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM13_CLK_DISABLE(); + /* USER CODE BEGIN TIM13_MspDeInit 1 */ + + /* USER CODE END TIM13_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspDeInit 0 */ + + /* USER CODE END TIM14_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM14_CLK_DISABLE(); + /* USER CODE BEGIN TIM14_MspDeInit 1 */ + + /* USER CODE END TIM14_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c new file mode 100644 index 0000000000..84413fb5f2 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c new file mode 100644 index 0000000000..bcb2b9f4a5 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/CubeMX_Config/Src/system_stm32f4xx.c @@ -0,0 +1,727 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/Kconfig b/bsp/stm32/stm32f407-armfly-v5/board/Kconfig new file mode 100644 index 0000000000..7c6b8a97f0 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/Kconfig @@ -0,0 +1,199 @@ +menu "Hardware Drivers Config" + +config SOC_STM32F407IG + bool + select SOC_SERIES_STM32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_RS232_TO_USART + bool "Enable RS232 TO USART (uart1)" + select BSP_USING_UART + select BSP_USING_UART1 + default y + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (W25Q64 spi3)" + select BSP_USING_SPI + select BSP_USING_SPI3 + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + + config BSP_USING_MPU6050 + bool "Enable MPU6050(i2c2)" + select BSP_USING_I2C2 + select PKG_USING_SENSORS_DRIVERS + select PKG_USING_MPU6XXX + select PKG_USING_MPU6XXX_SAMPLE + select PKG_USING_MPU6XXX_LATEST_VERSION + default n + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default y + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C2 + comment "Notice: PH4 --> 116; PH5 --> 117" + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 1 143 + default 116 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 1 143 + default 117 + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + + config BSP_USING_TIM14 + bool "Enable TIM14" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM10 + bool "Enable timer10 output pwm" + default n + if BSP_USING_PWM10 + config BSP_USING_PWM10_CH1 + bool "Enable PWM10 channel1" + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32f407-armfly-v5/board/SConscript b/bsp/stm32/stm32f407-armfly-v5/board/SConscript new file mode 100644 index 0000000000..2528db7cee --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/SConscript @@ -0,0 +1,44 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32f4xx_hal_msp.c +''') + +if GetDepend(['BSP_USING_SPI_FLASH']): + src += Glob('ports/spi_flash_init.c') + +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s'] + +# STM32F405xx) || STM32F415xx) || STM32F407xx) || STM32F417xx) +# STM32F427xx) || STM32F437xx) || STM32F429xx) || STM32F439xx) +# STM32F401xC) || STM32F401xE) || STM32F410Tx) || STM32F410Cx) +# STM32F410Rx) || STM32F411xE) || STM32F446xx) || STM32F469xx) +# STM32F479xx) || STM32F412Cx) || STM32F412Rx) || STM32F412Vx) +# STM32F412Zx) || STM32F413xx) || STM32F423xx) +# You can select chips from the list above +CPPDEFINES = ['STM32F407xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32f407-armfly-v5/board/board.c b/bsp/stm32/stm32f407-armfly-v5/board/board.c new file mode 100644 index 0000000000..e64882e5e1 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/board.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include "board.h" + +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32f407-armfly-v5/board/board.h b/bsp/stm32/stm32f407-armfly-v5/board/board.h new file mode 100644 index 0000000000..68016d18bd --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/board.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (1024 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM_SIZE 128 +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf new file mode 100644 index 0000000000..067691151f --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds new file mode 100644 index 0000000000..00a1f08cf1 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for STM32F4xx with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct new file mode 100644 index 0000000000..0d7c47992d --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h b/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h new file mode 100644 index 0000000000..20bcf9e11a --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#define FLASH_SIZE_GRANULARITY_16K (4 * 16 * 1024) +#define FLASH_SIZE_GRANULARITY_64K (64 * 1024) +#define FLASH_SIZE_GRANULARITY_128K (7 * 128 * 1024) + +#define STM32_FLASH_START_ADRESS_16K STM32_FLASH_START_ADRESS +#define STM32_FLASH_START_ADRESS_64K (STM32_FLASH_START_ADRESS_16K + FLASH_SIZE_GRANULARITY_16K) +#define STM32_FLASH_START_ADRESS_128K (STM32_FLASH_START_ADRESS_64K + FLASH_SIZE_GRANULARITY_64K) + +extern const struct fal_flash_dev stm32_onchip_flash_16k; +extern const struct fal_flash_dev stm32_onchip_flash_64k; +extern const struct fal_flash_dev stm32_onchip_flash_128k; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &stm32_onchip_flash_16k, \ + &stm32_onchip_flash_64k, \ + &stm32_onchip_flash_128k, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "bootloader", "onchip_flash_16k", 0 , FLASH_SIZE_GRANULARITY_16K , 0}, \ + {FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, \ +} + +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c new file mode 100644 index 0000000000..5eead223c3 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include + +#ifdef BSP_USING_SDCARD + +#include +#include +#include + +#define DBG_TAG "app.card" +#define DBG_LVL DBG_INFO +#include + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(stm32_sdcard_mount); + +#endif /* BSP_USING_SDCARD */ + diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c b/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c new file mode 100644 index 0000000000..9aa8f95c13 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-13 Dozingfiretruck first version + */ + +#include +#include "spi_flash.h" +#include "spi_flash_sfud.h" +#include "drv_spi.h" + +#if defined(BSP_USING_SPI_FLASH) +static int rt_hw_spi_flash_init(void) +{ + __HAL_RCC_GPIOF_CLK_ENABLE(); + rt_hw_spi_device_attach("spi3", "spi30", GPIOF, GPIO_PIN_8); + + if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi30")) + { + return -RT_ERROR; + }; + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); +#endif + diff --git a/bsp/stm32/stm32f407-armfly-v5/figures/board.png b/bsp/stm32/stm32f407-armfly-v5/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..94de91c01206c957bbc2607b86579fb7d1508a41 GIT binary patch literal 404490 zcmdpdV|OLn_jPb$+h)f(F*;Vqwr$%sJ4PoRblkCRvt!%#2|9UlfA{{s#Pgy?jjB3l zjM{sxxofVu=8jU7mqdcchX(@#L;5BqrVIuK;Rgl=-USQ&dFSw`PWtl%un?9L1_P^& z_kC4L{=6nNky4fe1B*Zb1B?AU{(k-`NC*tf&kGFfBnAwO{{RdOZ^DH?%mWMzp2td5 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$PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + CORTEX-M4 + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + + + finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\symbol.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_file.c + + + + STM32_HAL + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dfsdm.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_eth.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_irda.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nand.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nor.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pccard.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.eww b/bsp/stm32/stm32f407-armfly-v5/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvopt b/bsp/stm32/stm32f407-armfly-v5/project.uvopt new file mode 100644 index 0000000000..b53d69d5df --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +

### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvoptx b/bsp/stm32/stm32f407-armfly-v5/project.uvoptx new file mode 100644 index 0000000000..f8c4606a9e --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvoptx @@ -0,0 +1,191 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvproj b/bsp/stm32/stm32f407-armfly-v5/project.uvproj new file mode 100644 index 0000000000..a2c80e0594 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvproj @@ -0,0 +1,1189 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + + + STM32F407ZG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6105 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + USE_HAL_DRIVER, STM32F407xx + + applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + + + startup_stm32f407xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + symbol.c + 1 + ..\..\..\components\finsh\symbol.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_cmd.c + 1 + ..\..\..\components\finsh\msh_cmd.c + + + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + + + STM32_HAL + + + system_stm32f4xx.c + 1 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + + + stm32f4xx_hal.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + + + stm32f4xx_hal_adc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c + + + + + stm32f4xx_hal_adc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c + + + + + stm32f4xx_hal_can.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c + + + + + stm32f4xx_hal_cec.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + + + stm32f4xx_hal_cortex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + + + stm32f4xx_hal_crc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + + + stm32f4xx_hal_cryp.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + + + stm32f4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + + + stm32f4xx_hal_dac.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c + + + + + stm32f4xx_hal_dac_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c + + + + + stm32f4xx_hal_dcmi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi.c + + + + + stm32f4xx_hal_dcmi_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi_ex.c + + + + + stm32f4xx_hal_dfsdm.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dfsdm.c + + + + + stm32f4xx_hal_dma.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + + + stm32f4xx_hal_dma2d.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c + + + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + + + stm32f4xx_hal_dsi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c + + + + + stm32f4xx_hal_eth.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_eth.c + + + + + stm32f4xx_hal_flash.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c + + + + + stm32f4xx_hal_flash_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c + + + + + stm32f4xx_hal_flash_ramfunc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c + + + + + stm32f4xx_hal_fmpi2c.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c.c + + + + + stm32f4xx_hal_fmpi2c_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c_ex.c + + + + + stm32f4xx_hal_gpio.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + + + stm32f4xx_hal_hash.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash.c + + + + + stm32f4xx_hal_hash_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash_ex.c + + + + + stm32f4xx_hal_hcd.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c + + + + + stm32f4xx_hal_i2c.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c + + + + + stm32f4xx_hal_i2c_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + + + + + stm32f4xx_hal_i2s.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s.c + + + + + stm32f4xx_hal_i2s_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s_ex.c + + + + + stm32f4xx_hal_irda.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_irda.c + + + + + stm32f4xx_hal_iwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + + + + + stm32f4xx_hal_lptim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c + + + + + stm32f4xx_hal_ltdc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c + + + + + stm32f4xx_hal_ltdc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c + + + + + stm32f4xx_hal_nand.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nand.c + + + + + stm32f4xx_hal_nor.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nor.c + + + + + stm32f4xx_hal_pccard.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pccard.c + + + + + stm32f4xx_hal_pcd.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c + + + + + stm32f4xx_hal_pcd_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c + + + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + + + stm32f4xx_hal_qspi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c + + + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + + + stm32f4xx_hal_rtc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c + + + + + stm32f4xx_hal_rtc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c + + + + + stm32f4xx_hal_sai.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c + + + + + stm32f4xx_hal_sai_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c + + + + + stm32f4xx_hal_sd.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c + + + + + stm32f4xx_hal_sdram.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c + + + + + stm32f4xx_hal_smartcard.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c + + + + + stm32f4xx_hal_spdifrx.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c + + + + + stm32f4xx_hal_spi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + + + + + stm32f4xx_hal_sram.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c + + + + + stm32f4xx_hal_tim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + + + + + stm32f4xx_hal_tim_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + + + + stm32f4xx_hal_uart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + + + stm32f4xx_hal_usart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + + + stm32f4xx_hal_wwdg.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + + + + + stm32f4xx_ll_fmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c + + + + + stm32f4xx_ll_fsmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c + + + + + stm32f4xx_ll_sdmmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c + + + + + stm32f4xx_ll_usb.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c + + + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvprojx b/bsp/stm32/stm32f407-armfly-v5/project.uvprojx new file mode 100644 index 0000000000..793a467224 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvprojx @@ -0,0 +1,753 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407IGTx + STMicroelectronics + Keil.STM32F4xx_DFP.2.14.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407IGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407IGTx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER, STM32F407xx + + .;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + startup_stm32f407xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + drv_hwtimer.c + 1 + ..\libraries\HAL_Drivers\drv_hwtimer.c + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + hwtimer.c + 1 + ..\..\..\components\drivers\hwtimer\hwtimer.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + STM32_HAL + + + system_stm32f4xx.c + 1 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + stm32f4xx_hal.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + stm32f4xx_hal_cec.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + stm32f4xx_hal_cortex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + stm32f4xx_hal_crc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + stm32f4xx_hal_cryp.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + stm32f4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + stm32f4xx_hal_dma.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + stm32f4xx_hal_gpio.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + stm32f4xx_hal_uart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + stm32f4xx_hal_usart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + stm32f4xx_hal_tim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + + + stm32f4xx_hal_tim_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + + stm32f4xx_hal_lptim.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/rtconfig.h b/bsp/stm32/stm32f407-armfly-v5/rtconfig.h new file mode 100644 index 0000000000..7d83eb4f99 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/rtconfig.h @@ -0,0 +1,173 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F4 + +/* Hardware Drivers Config */ + +#define SOC_STM32F407ZG + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32f407-armfly-v5/rtconfig.py b/bsp/stm32/stm32f407-armfly-v5/rtconfig.py new file mode 100644 index 0000000000..00d5d737ac --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32f407-armfly-v5/template.ewp b/bsp/stm32/stm32f407-armfly-v5/template.ewp new file mode 100644 index 0000000000..21c66ca0d0 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.ewp @@ -0,0 +1,2031 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.eww b/bsp/stm32/stm32f407-armfly-v5/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvopt b/bsp/stm32/stm32f407-armfly-v5/template.uvopt new file mode 100644 index 0000000000..5cc5956b4f --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvopt @@ -0,0 +1,199 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + + 0 + Datasheet + DATASHTS\ST\STM32F4xx\DM00037051.pdf + + + 1 + Reference Manual + DATASHTS\ST\STM32F4xx\DM00031020.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvoptx b/bsp/stm32/stm32f407-armfly-v5/template.uvoptx new file mode 100644 index 0000000000..904af41f77 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvoptx @@ -0,0 +1,187 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 24000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F407IGTx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvproj b/bsp/stm32/stm32f407-armfly-v5/template.uvproj new file mode 100644 index 0000000000..73d0b32956 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvproj @@ -0,0 +1,438 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 0 + + + STM32F407IG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6104 + stm32f4xx.h + + + + + + + -DSTM32F40_41xxx + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 6 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f407-armfly-v5/template.uvprojx b/bsp/stm32/stm32f407-armfly-v5/template.uvprojx new file mode 100644 index 0000000000..4c3ec18c73 --- /dev/null +++ b/bsp/stm32/stm32f407-armfly-v5/template.uvprojx @@ -0,0 +1,411 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407IGTx + STMicroelectronics + Keil.STM32F4xx_DFP.2.14.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407IGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407IGTx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + From 020a82a65ab6d92d352c24a2e9b9c2013447cb16 Mon Sep 17 00:00:00 2001 From: gouqs0615 Date: Mon, 2 Nov 2020 16:44:13 +0800 Subject: [PATCH 2/5] fix at_server_getchar spelling error --- components/net/at/src/at_server.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/net/at/src/at_server.c b/components/net/at/src/at_server.c index 81d00951f5..e67ea9a620 100644 --- a/components/net/at/src/at_server.c +++ b/components/net/at/src/at_server.c @@ -412,7 +412,7 @@ static rt_err_t at_cmd_get_name(const char *cmd_buffer, char *cmd_name) return -RT_ERROR; } -static rt_err_t at_server_gerchar(at_server_t server, char *ch, rt_int32_t timeout) +static rt_err_t at_server_getchar(at_server_t server, char *ch, rt_int32_t timeout) { rt_err_t result = RT_EOK; @@ -595,7 +595,7 @@ int at_server_init(void) goto __exit; } - at_server_local->get_char = at_server_gerchar; + at_server_local->get_char = at_server_getchar; memcpy(at_server_local->end_mark, AT_CMD_END_MARK, sizeof(AT_CMD_END_MARK)); at_server_local->parser_entry = server_parser; From ad41afbc65abc334bcfb6064a90e992356877977 Mon Sep 17 00:00:00 2001 From: ZhaoJiasheng <18535861947@163.com> Date: Tue, 22 Dec 2020 17:33:49 +0800 Subject: [PATCH 3/5] Fix bsp/k210/driver/drv_gpio.c error --- bsp/k210/driver/drv_gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bsp/k210/driver/drv_gpio.c b/bsp/k210/driver/drv_gpio.c index a6eaaf197d..05ca8fd934 100644 --- a/bsp/k210/driver/drv_gpio.c +++ b/bsp/k210/driver/drv_gpio.c @@ -180,10 +180,10 @@ static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_int32_t pin, switch (mode) { case PIN_IRQ_MODE_RISING: - irq_table[pin_channel].edge = GPIO_PE_FALLING; + irq_table[pin_channel].edge = GPIO_PE_RISING; break; case PIN_IRQ_MODE_FALLING: - irq_table[pin_channel].edge = GPIO_PE_RISING; + irq_table[pin_channel].edge = GPIO_PE_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: irq_table[pin_channel].edge = GPIO_PE_BOTH; From 66e7465c5a202bf0cc37b3daf2991a4e3edc3b19 Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 4 Jun 2021 18:58:22 +0800 Subject: [PATCH 4/5] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=BA=86=E8=AE=B8?= =?UTF-8?q?=E5=8F=AF=E8=AF=81=E8=AF=B4=E6=98=8E=E5=92=8Cbsp=E9=85=8D?= =?UTF-8?q?=E7=BD=AE=E7=9A=84=E6=8E=A5=E5=8F=A3=EF=BC=8C=E4=BC=98=E5=8C=96?= =?UTF-8?q?=E4=BA=86=E9=A9=B1=E5=8A=A8=E5=8F=8A=E7=94=A8=E4=BE=8B=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/essemi/es32f0654/.config | 49 +- bsp/essemi/es32f0654/drivers/ES/Kconfig | 160 + .../es32f0654/drivers/ES/es_conf_info_adc.h | 97 + .../es32f0654/drivers/ES/es_conf_info_can.h | 73 + .../es32f0654/drivers/ES/es_conf_info_cmu.h | 87 + .../es32f0654/drivers/ES/es_conf_info_gpio.h | 5158 +++++++++++++++++ .../drivers/ES/es_conf_info_hwtimer.h | 103 + .../es32f0654/drivers/ES/es_conf_info_i2c.h | 95 + .../es32f0654/drivers/ES/es_conf_info_map.h | 2691 +++++++++ .../es32f0654/drivers/ES/es_conf_info_pm.h | 32 + .../es32f0654/drivers/ES/es_conf_info_pwm.h | 72 + .../es32f0654/drivers/ES/es_conf_info_rtc.h | 43 + .../drivers/ES/es_conf_info_select.h | 44 + .../es32f0654/drivers/ES/es_conf_info_spi.h | 132 + .../es32f0654/drivers/ES/es_conf_info_uart.h | 206 + bsp/essemi/es32f0654/drivers/Kconfig | 146 +- bsp/essemi/es32f0654/drivers/SConscript | 52 +- bsp/essemi/es32f0654/drivers/board.c | 91 +- bsp/essemi/es32f0654/drivers/board.h | 18 +- .../bsp_driver_example/adc_vol_sample.c | 5 + .../drivers/bsp_driver_example/can_sample.c | 6 +- .../bsp_driver_example/hwtimer_sample.c | 6 +- .../bsp_driver_example/i2c_e2_sample.c | 109 + .../drivers/bsp_driver_example/i2c_sample.c | 22 +- .../drivers/bsp_driver_example/pm_sample.c | 43 +- .../bsp_driver_example/pwm_led_sample.c | 8 +- .../drivers/bsp_driver_example/rtc_sample.c | 4 + .../drivers/bsp_driver_example/spi_sample.c | 36 +- bsp/essemi/es32f0654/drivers/drv_adc.c | 100 +- bsp/essemi/es32f0654/drivers/drv_adc.h | 15 + bsp/essemi/es32f0654/drivers/drv_can.c | 265 +- bsp/essemi/es32f0654/drivers/drv_can.h | 27 +- bsp/essemi/es32f0654/drivers/drv_gpio.c | 298 +- bsp/essemi/es32f0654/drivers/drv_gpio.h | 15 + bsp/essemi/es32f0654/drivers/drv_hwtimer.c | 408 +- bsp/essemi/es32f0654/drivers/drv_hwtimer.h | 16 +- bsp/essemi/es32f0654/drivers/drv_i2c.c | 93 +- bsp/essemi/es32f0654/drivers/drv_i2c.h | 19 +- bsp/essemi/es32f0654/drivers/drv_pm.c | 53 +- bsp/essemi/es32f0654/drivers/drv_pm.h | 19 + bsp/essemi/es32f0654/drivers/drv_pwm.c | 230 +- bsp/essemi/es32f0654/drivers/drv_pwm.h | 12 + bsp/essemi/es32f0654/drivers/drv_rtc.c | 36 +- bsp/essemi/es32f0654/drivers/drv_rtc.h | 16 +- bsp/essemi/es32f0654/drivers/drv_spi.c | 180 +- bsp/essemi/es32f0654/drivers/drv_spi.h | 17 +- bsp/essemi/es32f0654/drivers/drv_spiflash.c | 10 +- bsp/essemi/es32f0654/drivers/drv_uart.c | 567 +- bsp/essemi/es32f0654/drivers/drv_uart.h | 12 + .../Include/ald_acmp.h | 14 + .../Include/ald_adc.h | 14 + .../Include/ald_bkpc.h | 14 + .../Include/ald_calc.h | 14 + .../Include/ald_can.h | 14 + .../Include/ald_cmu.h | 14 + .../Include/ald_conf.h | 14 + .../Include/ald_crc.h | 14 + .../Include/ald_crypt.h | 14 + .../Include/ald_dbgc.h | 14 + .../Include/ald_dma.h | 14 + .../Include/ald_flash.h | 14 + .../Include/ald_gpio.h | 14 + .../Include/ald_i2c.h | 14 + .../Include/ald_iap.h | 14 + .../Include/ald_pis.h | 14 + .../Include/ald_pmu.h | 14 + .../Include/ald_rmu.h | 14 + .../Include/ald_rtc.h | 14 + .../Include/ald_smartcard.h | 14 + .../Include/ald_spi.h | 14 + .../Include/ald_syscfg.h | 14 + .../Include/ald_timer.h | 14 + .../Include/ald_trng.h | 14 + .../Include/ald_tsense.h | 14 + .../Include/ald_uart.h | 14 + .../Include/ald_usart.h | 14 + .../Include/ald_wdt.h | 14 + .../Include/type.h | 15 + .../Include/utils.h | 14 + .../Source/ald_acmp.c | 14 + .../Source/ald_adc.c | 14 + .../Source/ald_bkpc.c | 14 + .../Source/ald_calc.c | 14 + .../Source/ald_can.c | 14 + .../Source/ald_cmu.c | 14 + .../Source/ald_crc.c | 14 + .../Source/ald_crypt.c | 14 + .../Source/ald_dma.c | 14 + .../Source/ald_flash.c | 14 + .../Source/ald_flash_ext.c | 14 + .../Source/ald_gpio.c | 14 + .../Source/ald_i2c.c | 14 + .../Source/ald_iap.c | 14 + .../Source/ald_pis.c | 14 + .../Source/ald_pmu.c | 14 + .../Source/ald_rmu.c | 14 + .../Source/ald_rtc.c | 14 + .../Source/ald_smartcard.c | 14 + .../Source/ald_spi.c | 14 + .../Source/ald_timer.c | 14 + .../Source/ald_trng.c | 14 + .../Source/ald_tsense.c | 14 + .../Source/ald_uart.c | 14 + .../Source/ald_usart.c | 14 + .../Source/ald_wdt.c | 14 + .../Source/utils.c | 14 + bsp/essemi/es32f0654/project.uvprojx | 513 +- bsp/essemi/es32f0654/rtconfig.h | 9 - bsp/essemi/es32f369x/.config | 90 +- bsp/essemi/es32f369x/drivers/ES/Kconfig | 197 + .../es32f369x/drivers/ES/es_conf_info_adc.h | 97 + .../es32f369x/drivers/ES/es_conf_info_can.h | 73 + .../es32f369x/drivers/ES/es_conf_info_cmu.h | 89 + .../es32f369x/drivers/ES/es_conf_info_gpio.h | 5157 ++++++++++++++++ .../drivers/ES/es_conf_info_hwtimer.h | 102 + .../es32f369x/drivers/ES/es_conf_info_i2c.h | 95 + .../es32f369x/drivers/ES/es_conf_info_map.h | 2876 +++++++++ .../es32f369x/drivers/ES/es_conf_info_pm.h | 32 + .../es32f369x/drivers/ES/es_conf_info_pwm.h | 78 + .../es32f369x/drivers/ES/es_conf_info_rtc.h | 43 + .../drivers/ES/es_conf_info_select.h | 43 + .../es32f369x/drivers/ES/es_conf_info_spi.h | 159 + .../es32f369x/drivers/ES/es_conf_info_uart.h | 205 + bsp/essemi/es32f369x/drivers/Kconfig | 154 +- bsp/essemi/es32f369x/drivers/SConscript | 26 +- bsp/essemi/es32f369x/drivers/board.c | 93 +- bsp/essemi/es32f369x/drivers/board.h | 18 +- .../bsp_driver_example/adc_vol_sample.c | 6 + .../drivers/bsp_driver_example/can_sample.c | 6 +- .../bsp_driver_example/hwtimer_sample.c | 4 + .../bsp_driver_example/i2c_e2_sample.c | 109 + .../drivers/bsp_driver_example/i2c_sample.c | 18 +- .../drivers/bsp_driver_example/pm_sample.c | 53 +- .../bsp_driver_example/pwm_led_sample.c | 9 +- .../drivers/bsp_driver_example/rtc_sample.c | 6 +- .../drivers/bsp_driver_example/spi_sample.c | 36 +- bsp/essemi/es32f369x/drivers/drv_adc.c | 131 +- bsp/essemi/es32f369x/drivers/drv_adc.h | 17 +- bsp/essemi/es32f369x/drivers/drv_can.c | 279 +- bsp/essemi/es32f369x/drivers/drv_can.h | 27 +- bsp/essemi/es32f369x/drivers/drv_gpio.c | 310 +- bsp/essemi/es32f369x/drivers/drv_gpio.h | 17 +- bsp/essemi/es32f369x/drivers/drv_hwtimer.c | 379 +- bsp/essemi/es32f369x/drivers/drv_hwtimer.h | 16 +- bsp/essemi/es32f369x/drivers/drv_i2c.c | 88 +- bsp/essemi/es32f369x/drivers/drv_i2c.h | 19 +- bsp/essemi/es32f369x/drivers/drv_pm.c | 60 +- bsp/essemi/es32f369x/drivers/drv_pm.h | 20 +- bsp/essemi/es32f369x/drivers/drv_pwm.c | 328 +- bsp/essemi/es32f369x/drivers/drv_rtc.c | 39 +- bsp/essemi/es32f369x/drivers/drv_rtc.h | 16 +- bsp/essemi/es32f369x/drivers/drv_spi.c | 212 +- bsp/essemi/es32f369x/drivers/drv_spi.h | 17 +- bsp/essemi/es32f369x/drivers/drv_spiflash.c | 34 + bsp/essemi/es32f369x/drivers/drv_spiflash.h | 19 + bsp/essemi/es32f369x/drivers/drv_uart.c | 448 +- bsp/essemi/es32f369x/drivers/drv_uart.h | 12 + .../EastSoft/ES32F36xx/Include/es32f36xx.h | 14 + .../ES32F36xx/Startup/gcc/startup_es32f36xx.S | 438 ++ .../Startup/keil/startup_es32f36xx.s | 14 + .../Include/ald_acmp.h | 14 + .../Include/ald_adc.h | 14 + .../Include/ald_bkpc.h | 14 + .../Include/ald_calc.h | 14 + .../Include/ald_can.h | 14 + .../Include/ald_cmu.h | 14 + .../Include/ald_conf.h | 14 + .../Include/ald_crc.h | 14 + .../Include/ald_crypt.h | 16 +- .../Include/ald_dac.h | 14 + .../Include/ald_dbgc.h | 15 + .../Include/ald_dma.h | 14 + .../Include/ald_ebi.h | 14 + .../Include/ald_flash.h | 14 + .../Include/ald_gpio.h | 16 +- .../Include/ald_i2c.h | 14 + .../Include/ald_i2s.h | 14 + .../Include/ald_iap.h | 14 + .../Include/ald_nand.h | 14 + .../Include/ald_nor_lcd.h | 14 + .../Include/ald_pis.h | 14 + .../Include/ald_pmu.h | 14 + .../Include/ald_qspi.h | 14 + .../Include/ald_rmu.h | 16 +- .../Include/ald_rtc.h | 14 + .../Include/ald_rtchw.h | 14 + .../Include/ald_spi.h | 14 + .../Include/ald_sram.h | 14 + .../Include/ald_syscfg.h | 14 + .../Include/ald_timer.h | 14 + .../Include/ald_trng.h | 16 +- .../Include/ald_tsense.h | 14 + .../Include/ald_uart.h | 16 +- .../Include/ald_usb.h | 16 +- .../Include/ald_wdt.h | 16 +- .../Include/type.h | 16 +- .../Include/utils.h | 14 + .../Source/ald_acmp.c | 14 + .../Source/ald_adc.c | 14 + .../Source/ald_bkpc.c | 14 + .../Source/ald_calc.c | 16 +- .../Source/ald_can.c | 14 + .../Source/ald_cmu.c | 16 +- .../Source/ald_crc.c | 14 + .../Source/ald_crypt.c | 14 + .../Source/ald_dac.c | 14 + .../Source/ald_dma.c | 14 + .../Source/ald_ebi.c | 14 + .../Source/ald_flash.c | 14 + .../Source/ald_flash_ext.c | 14 + .../Source/ald_gpio.c | 16 +- .../Source/ald_i2c.c | 14 + .../Source/ald_i2s.c | 14 + .../Source/ald_iap.c | 14 + .../Source/ald_nand.c | 14 + .../Source/ald_nor_lcd.c | 14 + .../Source/ald_pis.c | 14 + .../Source/ald_pmu.c | 14 + .../Source/ald_qspi.c | 14 + .../Source/ald_rmu.c | 14 + .../Source/ald_rtc.c | 14 + .../Source/ald_rtchw.c | 14 + .../Source/ald_spi.c | 14 + .../Source/ald_sram.c | 14 + .../Source/ald_timer.c | 14 + .../Source/ald_trng.c | 14 + .../Source/ald_tsense.c | 14 + .../Source/ald_uart.c | 14 + .../Source/ald_usb.c | 14 + .../Source/ald_wdt.c | 14 + .../Source/utils.c | 14 + bsp/essemi/es32f369x/project.uvoptx | 1180 ++-- bsp/essemi/es32f369x/project.uvprojx | 506 +- bsp/essemi/es32f369x/rtconfig.h | 21 +- bsp/essemi/es32f369x/template.uvoptx | 8 +- bsp/essemi/es32f369x/template.uvprojx | 6 +- 236 files changed, 25721 insertions(+), 3162 deletions(-) create mode 100644 bsp/essemi/es32f0654/drivers/ES/Kconfig create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_adc.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_can.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_cmu.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_gpio.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_i2c.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_map.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_pm.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_pwm.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_rtc.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_select.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_spi.h create mode 100644 bsp/essemi/es32f0654/drivers/ES/es_conf_info_uart.h create mode 100644 bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_e2_sample.c create mode 100644 bsp/essemi/es32f369x/drivers/ES/Kconfig create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h create mode 100644 bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_e2_sample.c create mode 100644 bsp/essemi/es32f369x/drivers/drv_spiflash.c create mode 100644 bsp/essemi/es32f369x/drivers/drv_spiflash.h create mode 100644 bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S diff --git a/bsp/essemi/es32f0654/.config b/bsp/essemi/es32f0654/.config index 3a014cefdd..cab1975d8a 100644 --- a/bsp/essemi/es32f0654/.config +++ b/bsp/essemi/es32f0654/.config @@ -19,7 +19,7 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y @@ -114,26 +114,26 @@ CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_CAN=y +# CONFIG_RT_USING_CAN is not set # CONFIG_RT_CAN_USING_HDR is not set -CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y +# CONFIG_RT_USING_I2C is not set # CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_USING_I2C_BITOPS is not set # CONFIG_RT_I2C_BITOPS_DEBUG is not set CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set # CONFIG_RT_USING_SFUD is not set @@ -159,7 +159,8 @@ CONFIG_RT_USING_SPI=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_LIBC_USING_TIME is not set +CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # # Network @@ -468,6 +469,8 @@ CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_USING_UART1 is not set CONFIG_BSP_USING_UART2=y # CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_USART0 is not set +# CONFIG_BSP_USING_USART1 is not set # # SPI Drivers @@ -484,23 +487,26 @@ CONFIG_BSP_USING_UART2=y # # CAN Drivers # -# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_CAN0 is not set # # PWM Drivers # -# CONFIG_BSP_USING_PWM0 is not set -# CONFIG_BSP_USING_PWM1 is not set -# CONFIG_BSP_USING_PWM2 is not set -# CONFIG_BSP_USING_PWM3 is not set +# CONFIG_BSP_USING_AD16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C2T0_PWM is not set +# CONFIG_BSP_USING_GP16C2T1_PWM is not set # # HWtimer Drivers # -# CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set -# CONFIG_BSP_USING_HWTIMER2 is not set -# CONFIG_BSP_USING_HWTIMER3 is not set +# CONFIG_BSP_USING_AD16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C2T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C2T1_HWTIMER is not set +# CONFIG_BSP_USING_BS16T0_HWTIMER is not set +# CONFIG_BSP_USING_BS16T2_HWTIMER is not set +# CONFIG_BSP_USING_BS16T3_HWTIMER is not set # # RTC Drivers @@ -515,7 +521,7 @@ CONFIG_BSP_USING_UART2=y # # ADC Drivers # -# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ADC0 is not set # # Onboard Peripheral Drivers @@ -532,6 +538,7 @@ CONFIG_BSP_USING_UART2=y # CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set # CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set # CONFIG_BSP_USING_EXAMPLE_I2C is not set +# CONFIG_BSP_USING_EXAMPLE_I2C_E2PROM is not set # CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set # CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set # CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set diff --git a/bsp/essemi/es32f0654/drivers/ES/Kconfig b/bsp/essemi/es32f0654/drivers/ES/Kconfig new file mode 100644 index 0000000000..1f3b0a4e96 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/Kconfig @@ -0,0 +1,160 @@ +menu "UART Drivers" + + config BSP_USING_UART0 + bool "Register UART0" + select RT_USING_SERIAL + default n + + config BSP_USING_UART1 + bool "Register UART1" + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Register UART2" + select RT_USING_SERIAL + default y + + config BSP_USING_UART3 + bool "Register UART3" + select RT_USING_SERIAL + default n + + config BSP_USING_USART0 + bool "Register USART0" + select RT_USING_SERIAL + default n + + config BSP_USING_USART1 + bool "Register USART1" + select RT_USING_SERIAL + default n +endmenu + +menu "SPI Drivers" + + config BSP_USING_SPI0 + bool "Register SPI0" + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Register SPI1" + select RT_USING_SPI + select RT_USING_PIN + default n +endmenu + +menu "I2C Drivers" + config BSP_USING_I2C0 + bool "Register I2C0" + select RT_USING_I2C + default n + + config BSP_USING_I2C1 + bool "Register I2C1" + select RT_USING_I2C + default n +endmenu + +menu "CAN Drivers" + config BSP_USING_CAN0 + bool "Register CAN0" + select RT_USING_CAN + select RT_CAN_USING_HDR + default n +endmenu + +menu "PWM Drivers" + config BSP_USING_AD16C4T0_PWM + bool "Register pwm0" + select RT_USING_PWM + default n + + config BSP_USING_GP16C4T0_PWM + bool "Register pwm1" + select RT_USING_PWM + default n + + config BSP_USING_GP16C2T0_PWM + bool "Register pwm2" + select RT_USING_PWM + default n + + config BSP_USING_GP16C2T1_PWM + bool "Register pwm3" + select RT_USING_PWM + default n +endmenu + +menu "HWtimer Drivers" + config BSP_USING_AD16C4T0_HWTIMER + bool "Register timer0" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_AD16C4T0_PWM + + config BSP_USING_GP16C4T0_HWTIMER + bool "Register timer1" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_GP16C4T0_PWM + + config BSP_USING_GP16C2T0_HWTIMER + bool "Register timer2" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_GP16C2T0_PWM + + config BSP_USING_GP16C2T1_HWTIMER + bool "Register timer3" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_GP16C2T1_PWM + + config BSP_USING_BS16T0_HWTIMER + bool "Register timer4" + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T1_HWTIMER + bool "Register timer5" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_UART2 + + config BSP_USING_BS16T2_HWTIMER + bool "Register timer6" + select RT_USING_HWTIMER + default n + depends on !BSP_USING_UART3 + + config BSP_USING_BS16T3_HWTIMER + bool "Register timer7" + select RT_USING_HWTIMER + default n +endmenu + +menu "RTC Drivers" + config BSP_USING_RTC + bool "Register RTC" + select RT_USING_RTC + default n +endmenu + +menu "PM Drivers" + config BSP_USING_PM + bool "Using PM" + select RT_USING_PM + default n +endmenu + +menu "ADC Drivers" + config BSP_USING_ADC0 + bool "Using ADC" + select RT_USING_ADC + select BSP_USING_ADC + default n +endmenu + diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_adc.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_adc.h new file mode 100644 index 0000000000..772f7a0df0 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_adc.h @@ -0,0 +1,97 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_ADC_H__ +#define __ES_CONF_INFO_ADC_H__ + +#include "es_conf_info_map.h" + +#include + + +#define ES_C_ADC_CLK_DIV_1 ADC_CKDIV_1 +#define ES_C_ADC_CLK_DIV_2 ADC_CKDIV_2 +#define ES_C_ADC_CLK_DIV_4 ADC_CKDIV_4 +#define ES_C_ADC_CLK_DIV_8 ADC_CKDIV_8 +#define ES_C_ADC_CLK_DIV_16 ADC_CKDIV_16 +#define ES_C_ADC_CLK_DIV_32 ADC_CKDIV_32 +#define ES_C_ADC_CLK_DIV_64 ADC_CKDIV_64 +#define ES_C_ADC_CLK_DIV_128 ADC_CKDIV_128 + +#define ES_C_ADC_ALIGN_RIGHT ADC_DATAALIGN_RIGHT +#define ES_C_ADC_ALIGN_LEFT ADC_DATAALIGN_LEFT + +#define ES_C_ADC_CONV_BIT_6 ADC_CONV_BIT_6 +#define ES_C_ADC_CONV_BIT_8 ADC_CONV_BIT_8 +#define ES_C_ADC_CONV_BIT_10 ADC_CONV_BIT_10 +#define ES_C_ADC_CONV_BIT_12 ADC_CONV_BIT_12 + +#define ES_C_ADC_SAMPLE_TIME_1 ADC_SAMPLETIME_1 +#define ES_C_ADC_SAMPLE_TIME_2 ADC_SAMPLETIME_2 +#define ES_C_ADC_SAMPLE_TIME_4 ADC_SAMPLETIME_4 +#define ES_C_ADC_SAMPLE_TIME_15 ADC_SAMPLETIME_15 + +/* ADC 配置 */ + +/* codes_main */ + + +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 + +#ifndef ES_DEVICE_NAME_ADC0 +#define ES_DEVICE_NAME_ADC0 "adc0" +#endif +#ifndef ES_DEVICE_NAME_ADC1 +#define ES_DEVICE_NAME_ADC1 "adc1" +#endif + +#ifndef ES_ADC0_CLK_DIV +#define ES_ADC0_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC0_ALIGN +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC0_DATA_BIT +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC0_NCH_SAMPLETIME +#define ES_ADC0_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#ifndef ES_ADC1_CLK_DIV +#define ES_ADC1_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC1_ALIGN +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC1_DATA_BIT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC1_NCH_SAMPLETIME +#define ES_ADC1_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_can.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_can.h new file mode 100644 index 0000000000..46df1ed054 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_can.h @@ -0,0 +1,73 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CAN_H__ +#define __ES_CONF_INFO_CAN_H__ + +#include "es_conf_info_map.h" +#include +#include + + +/*默认的CAN硬件过滤器的编号 0 */ +#define ES_C_CAN_DEFAULT_FILTER_NUMBER 0 + +/*硬件过滤器，过滤帧类型*/ +#define ES_C_CAN_FILTER_FRAME_TYPE 0 + + +#define ES_C_CAN_SJW_NUM_1 CAN_SJW_1 +#define ES_C_CAN_SJW_NUM_2 CAN_SJW_2 +#define ES_C_CAN_SJW_NUM_3 CAN_SJW_3 +#define ES_C_CAN_SJW_NUM_4 CAN_SJW_4 + + + +/* CAN 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_CAN0 +#define ES_DEVICE_NAME_CAN0 "can0" +#endif + +#ifndef ES_CAN0_AUTO_BAN_RE_T +#define ES_CAN0_AUTO_BAN_RE_T ES_C_ENABLE +#endif +#ifndef ES_CAN0_SPEED +#define ES_CAN0_SPEED 1000000 +#endif +#ifndef ES_CAN0_SJW +#define ES_CAN0_SJW ES_C_CAN_SJW_NUM_4 +#endif + +#define ES_CAN0_CONFIG \ +{ \ + ES_CAN0_SPEED, \ + RT_CANMSG_BOX_SZ, \ + RT_CANSND_BOX_NUM, \ + RT_CAN_MODE_NORMAL, \ +}; +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_cmu.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_cmu.h new file mode 100644 index 0000000000..f82c1d2b6b --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_cmu.h @@ -0,0 +1,87 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CMU_H__ +#define __ES_CONF_INFO_CMU_H__ + + +#include + + +/* 时钟树 配置 */ + +#define ES_C_MUL_9 CMU_PLL1_OUTPUT_36M +#define ES_C_MUL_12 CMU_PLL1_OUTPUT_48M + +#define ES_C_DIV_1 CMU_DIV_1 +#define ES_C_DIV_2 CMU_DIV_2 +#define ES_C_DIV_4 CMU_DIV_4 +#define ES_C_DIV_8 CMU_DIV_8 +#define ES_C_DIV_16 CMU_DIV_16 +#define ES_C_DIV_32 CMU_DIV_32 +#define ES_C_DIV_64 CMU_DIV_64 +#define ES_C_DIV_128 CMU_DIV_128 +#define ES_C_DIV_256 CMU_DIV_256 +#define ES_C_DIV_512 CMU_DIV_512 +#define ES_C_DIV_1024 CMU_DIV_1024 +#define ES_C_DIV_2048 CMU_DIV_2048 +#define ES_C_DIV_4096 CMU_DIV_4096 + +#define ES_C_HOSC_DIV_1 CMU_PLL1_INPUT_HOSC +#define ES_C_HOSC_DIV_2 CMU_PLL1_INPUT_HOSC_2 +#define ES_C_HOSC_DIV_3 CMU_PLL1_INPUT_HOSC_3 +#define ES_C_HOSC_DIV_4 CMU_PLL1_INPUT_HOSC_4 +#define ES_C_HOSC_DIV_5 CMU_PLL1_INPUT_HOSC_5 +#define ES_C_HOSC_DIV_6 CMU_PLL1_INPUT_HOSC_6 +#define ES_C_HRC_DIV_6 CMU_PLL1_INPUT_HRC_6 + + + + + +#define ES_PLL1_REFER_CLK ES_C_HOSC_DIV_3 +#define ES_PLL1_OUT_CLK ES_C_MUL_12 +#define ES_CMU_PLL1_EN ES_C_ENABLE +#define ES_CMU_PLL1_SAFE_EN ES_C_DISABLE +#define ES_CMU_LOSC_EN ES_C_ENABLE +#define ES_CMU_LRC_EN ES_C_ENABLE +#define ES_CMU_HOSC_EN ES_C_ENABLE +#define ES_CMU_HRC_EN ES_C_ENABLE +#define ES_CMU_SYS_DIV ES_C_DIV_1 +#define ES_CMU_HCLK_1_DIV ES_C_DIV_1 +#define ES_CMU_PCLK_1_DIV ES_C_DIV_1 +#define ES_CMU_PCLK_2_DIV ES_C_DIV_1 +#define ES_SYS_CLK_SOURSE CMU_CLOCK_PLL1 +#define ES_PLL_CLK 48000000 +#define ES_SYS_SOURCE_CLK 48000000 +#define ES_SYS_CLK 48000000 +#define ES_PCLK1_CLK 48000000 +#define ES_PCLK2_CLK 48000000 +#define ES_HCLK1_CLK 48000000 +#define ES_CMU_EXTERN_CLK_LOSC 32768 +#define ES_CMU_EXTERN_CLK_HOSC 12000000 + + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_gpio.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_gpio.h new file mode 100644 index 0000000000..dc3fde3020 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_gpio.h @@ -0,0 +1,5158 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_GPIO_H__ +#define __ES_CONF_INFO_GPIO_H__ + +#include "es_conf_info_map.h" + +#include +#include +#include + +/* GPIO 配置 */ + +typedef struct { + uint8_t pin; + uint8_t pin_mode; + uint8_t pin_level; + uint8_t irq_en; + uint8_t irq_mode; + void (*callback)(void *arg); +} gpio_conf_t; + +/*参数的定义*/ + +#define ES_C_GPIO_LEVEL_HIGH PIN_HIGH +#define ES_C_GPIO_LEVEL_LOW PIN_LOW + +#define ES_C_GPIO_MODE_OUTPUT PIN_MODE_OUTPUT +#define ES_C_GPIO_MODE_INPUT PIN_MODE_INPUT +#define ES_C_GPIO_MODE_INPUT_PULLUP PIN_MODE_INPUT_PULLUP +#define ES_C_GPIO_MODE_INPUT_PULLDOWN PIN_MODE_INPUT_PULLDOWN +#define ES_C_GPIO_MODE_OUTPUT_OD PIN_MODE_OUTPUT_OD + +#define ES_C_GPIO_IRQ_ENABLE PIN_IRQ_ENABLE +#define ES_C_GPIO_IRQ_DISABLE PIN_IRQ_DISABLE + +#define ES_C_GPIO_IRQ_MODE_FALL PIN_IRQ_MODE_FALLING +#define ES_C_GPIO_IRQ_MODE_RISE PIN_IRQ_MODE_RISING +#define ES_C_GPIO_IRQ_MODE_R_F PIN_IRQ_MODE_RISING_FALLING + + + + + +/* codes_main */ +//#define ES_INIT_PIN_GPIO_C_8 +//#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_ENABLE + + + +#ifndef ES_DEVICE_NAME_PIN +#define ES_DEVICE_NAME_PIN "pin" +#endif + +/*GPIO外部中断回调函数控制需要，补充是否中断*/ +#if 11111 + +#ifndef ES_INIT_GPIO_A_0_IRQ_EN +#define ES_INIT_GPIO_A_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_1_IRQ_EN +#define ES_INIT_GPIO_A_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_2_IRQ_EN +#define ES_INIT_GPIO_A_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_3_IRQ_EN +#define ES_INIT_GPIO_A_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_4_IRQ_EN +#define ES_INIT_GPIO_A_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_5_IRQ_EN +#define ES_INIT_GPIO_A_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_6_IRQ_EN +#define ES_INIT_GPIO_A_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_7_IRQ_EN +#define ES_INIT_GPIO_A_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_8_IRQ_EN +#define ES_INIT_GPIO_A_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_9_IRQ_EN +#define ES_INIT_GPIO_A_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_10_IRQ_EN +#define ES_INIT_GPIO_A_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_11_IRQ_EN +#define ES_INIT_GPIO_A_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_12_IRQ_EN +#define ES_INIT_GPIO_A_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_13_IRQ_EN +#define ES_INIT_GPIO_A_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_14_IRQ_EN +#define ES_INIT_GPIO_A_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_15_IRQ_EN +#define ES_INIT_GPIO_A_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_0_IRQ_EN +#define ES_INIT_GPIO_B_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_1_IRQ_EN +#define ES_INIT_GPIO_B_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_2_IRQ_EN +#define ES_INIT_GPIO_B_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_3_IRQ_EN +#define ES_INIT_GPIO_B_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_4_IRQ_EN +#define ES_INIT_GPIO_B_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_5_IRQ_EN +#define ES_INIT_GPIO_B_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_6_IRQ_EN +#define ES_INIT_GPIO_B_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_7_IRQ_EN +#define ES_INIT_GPIO_B_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_8_IRQ_EN +#define ES_INIT_GPIO_B_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_9_IRQ_EN +#define ES_INIT_GPIO_B_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_10_IRQ_EN +#define ES_INIT_GPIO_B_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_11_IRQ_EN +#define ES_INIT_GPIO_B_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_12_IRQ_EN +#define ES_INIT_GPIO_B_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_13_IRQ_EN +#define ES_INIT_GPIO_B_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_14_IRQ_EN +#define ES_INIT_GPIO_B_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_15_IRQ_EN +#define ES_INIT_GPIO_B_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_0_IRQ_EN +#define ES_INIT_GPIO_C_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_1_IRQ_EN +#define ES_INIT_GPIO_C_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_2_IRQ_EN +#define ES_INIT_GPIO_C_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_3_IRQ_EN +#define ES_INIT_GPIO_C_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_4_IRQ_EN +#define ES_INIT_GPIO_C_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_5_IRQ_EN +#define ES_INIT_GPIO_C_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_6_IRQ_EN +#define ES_INIT_GPIO_C_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_7_IRQ_EN +#define ES_INIT_GPIO_C_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_8_IRQ_EN +#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_9_IRQ_EN +#define ES_INIT_GPIO_C_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_10_IRQ_EN +#define ES_INIT_GPIO_C_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_11_IRQ_EN +#define ES_INIT_GPIO_C_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_12_IRQ_EN +#define ES_INIT_GPIO_C_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_13_IRQ_EN +#define ES_INIT_GPIO_C_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_14_IRQ_EN +#define ES_INIT_GPIO_C_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_15_IRQ_EN +#define ES_INIT_GPIO_C_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_0_IRQ_EN +#define ES_INIT_GPIO_D_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_1_IRQ_EN +#define ES_INIT_GPIO_D_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_2_IRQ_EN +#define ES_INIT_GPIO_D_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_3_IRQ_EN +#define ES_INIT_GPIO_D_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_4_IRQ_EN +#define ES_INIT_GPIO_D_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_5_IRQ_EN +#define ES_INIT_GPIO_D_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_6_IRQ_EN +#define ES_INIT_GPIO_D_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_7_IRQ_EN +#define ES_INIT_GPIO_D_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_8_IRQ_EN +#define ES_INIT_GPIO_D_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_9_IRQ_EN +#define ES_INIT_GPIO_D_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_10_IRQ_EN +#define ES_INIT_GPIO_D_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_11_IRQ_EN +#define ES_INIT_GPIO_D_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_12_IRQ_EN +#define ES_INIT_GPIO_D_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_13_IRQ_EN +#define ES_INIT_GPIO_D_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_14_IRQ_EN +#define ES_INIT_GPIO_D_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_15_IRQ_EN +#define ES_INIT_GPIO_D_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_0_IRQ_EN +#define ES_INIT_GPIO_E_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_1_IRQ_EN +#define ES_INIT_GPIO_E_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_2_IRQ_EN +#define ES_INIT_GPIO_E_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_3_IRQ_EN +#define ES_INIT_GPIO_E_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_4_IRQ_EN +#define ES_INIT_GPIO_E_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_5_IRQ_EN +#define ES_INIT_GPIO_E_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_6_IRQ_EN +#define ES_INIT_GPIO_E_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_7_IRQ_EN +#define ES_INIT_GPIO_E_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_8_IRQ_EN +#define ES_INIT_GPIO_E_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_9_IRQ_EN +#define ES_INIT_GPIO_E_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_10_IRQ_EN +#define ES_INIT_GPIO_E_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_11_IRQ_EN +#define ES_INIT_GPIO_E_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_12_IRQ_EN +#define ES_INIT_GPIO_E_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_13_IRQ_EN +#define ES_INIT_GPIO_E_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_14_IRQ_EN +#define ES_INIT_GPIO_E_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_15_IRQ_EN +#define ES_INIT_GPIO_E_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_0_IRQ_EN +#define ES_INIT_GPIO_F_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_1_IRQ_EN +#define ES_INIT_GPIO_F_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_2_IRQ_EN +#define ES_INIT_GPIO_F_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_3_IRQ_EN +#define ES_INIT_GPIO_F_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_4_IRQ_EN +#define ES_INIT_GPIO_F_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_5_IRQ_EN +#define ES_INIT_GPIO_F_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_6_IRQ_EN +#define ES_INIT_GPIO_F_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_7_IRQ_EN +#define ES_INIT_GPIO_F_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_8_IRQ_EN +#define ES_INIT_GPIO_F_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_9_IRQ_EN +#define ES_INIT_GPIO_F_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_10_IRQ_EN +#define ES_INIT_GPIO_F_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_11_IRQ_EN +#define ES_INIT_GPIO_F_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_12_IRQ_EN +#define ES_INIT_GPIO_F_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_13_IRQ_EN +#define ES_INIT_GPIO_F_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_14_IRQ_EN +#define ES_INIT_GPIO_F_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_15_IRQ_EN +#define ES_INIT_GPIO_F_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_0_IRQ_EN +#define ES_INIT_GPIO_G_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_1_IRQ_EN +#define ES_INIT_GPIO_G_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_2_IRQ_EN +#define ES_INIT_GPIO_G_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_3_IRQ_EN +#define ES_INIT_GPIO_G_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_4_IRQ_EN +#define ES_INIT_GPIO_G_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_5_IRQ_EN +#define ES_INIT_GPIO_G_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_6_IRQ_EN +#define ES_INIT_GPIO_G_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_7_IRQ_EN +#define ES_INIT_GPIO_G_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_8_IRQ_EN +#define ES_INIT_GPIO_G_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_9_IRQ_EN +#define ES_INIT_GPIO_G_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_10_IRQ_EN +#define ES_INIT_GPIO_G_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_11_IRQ_EN +#define ES_INIT_GPIO_G_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_12_IRQ_EN +#define ES_INIT_GPIO_G_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_13_IRQ_EN +#define ES_INIT_GPIO_G_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_14_IRQ_EN +#define ES_INIT_GPIO_G_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_15_IRQ_EN +#define ES_INIT_GPIO_G_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_0_IRQ_EN +#define ES_INIT_GPIO_H_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_1_IRQ_EN +#define ES_INIT_GPIO_H_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_2_IRQ_EN +#define ES_INIT_GPIO_H_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_3_IRQ_EN +#define ES_INIT_GPIO_H_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_4_IRQ_EN +#define ES_INIT_GPIO_H_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_5_IRQ_EN +#define ES_INIT_GPIO_H_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_6_IRQ_EN +#define ES_INIT_GPIO_H_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_7_IRQ_EN +#define ES_INIT_GPIO_H_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_8_IRQ_EN +#define ES_INIT_GPIO_H_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_9_IRQ_EN +#define ES_INIT_GPIO_H_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_10_IRQ_EN +#define ES_INIT_GPIO_H_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_11_IRQ_EN +#define ES_INIT_GPIO_H_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_12_IRQ_EN +#define ES_INIT_GPIO_H_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_13_IRQ_EN +#define ES_INIT_GPIO_H_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_14_IRQ_EN +#define ES_INIT_GPIO_H_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_15_IRQ_EN +#define ES_INIT_GPIO_H_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#endif //11111 + + + +/*是否需要 GPIO外部中断回调函数 （控制函数本体+声明）*/ +#if 11111 + +#if (ES_INIT_GPIO_A_0_IRQ_EN)||(ES_INIT_GPIO_B_0_IRQ_EN)||(ES_INIT_GPIO_C_0_IRQ_EN)||(ES_INIT_GPIO_D_0_IRQ_EN)|| \ + (ES_INIT_GPIO_E_0_IRQ_EN)||(ES_INIT_GPIO_F_0_IRQ_EN)||(ES_INIT_GPIO_G_0_IRQ_EN)||(ES_INIT_GPIO_H_0_IRQ_EN) +#define ES_CONF_EXTI_IRQ_0 +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN)||(ES_INIT_GPIO_B_1_IRQ_EN)||(ES_INIT_GPIO_C_1_IRQ_EN)||(ES_INIT_GPIO_D_1_IRQ_EN)|| \ + (ES_INIT_GPIO_E_1_IRQ_EN)||(ES_INIT_GPIO_F_1_IRQ_EN)||(ES_INIT_GPIO_G_1_IRQ_EN)||(ES_INIT_GPIO_H_1_IRQ_EN) +#define ES_CONF_EXTI_IRQ_1 +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN)||(ES_INIT_GPIO_B_2_IRQ_EN)||(ES_INIT_GPIO_C_2_IRQ_EN)||(ES_INIT_GPIO_D_2_IRQ_EN)|| \ + (ES_INIT_GPIO_E_2_IRQ_EN)||(ES_INIT_GPIO_F_2_IRQ_EN)||(ES_INIT_GPIO_G_2_IRQ_EN)||(ES_INIT_GPIO_H_2_IRQ_EN) +#define ES_CONF_EXTI_IRQ_2 +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN)||(ES_INIT_GPIO_B_3_IRQ_EN)||(ES_INIT_GPIO_C_3_IRQ_EN)||(ES_INIT_GPIO_D_3_IRQ_EN)|| \ + (ES_INIT_GPIO_E_3_IRQ_EN)||(ES_INIT_GPIO_F_3_IRQ_EN)||(ES_INIT_GPIO_G_3_IRQ_EN)||(ES_INIT_GPIO_H_3_IRQ_EN) +#define ES_CONF_EXTI_IRQ_3 +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN)||(ES_INIT_GPIO_B_4_IRQ_EN)||(ES_INIT_GPIO_C_4_IRQ_EN)||(ES_INIT_GPIO_D_4_IRQ_EN)|| \ + (ES_INIT_GPIO_E_4_IRQ_EN)||(ES_INIT_GPIO_F_4_IRQ_EN)||(ES_INIT_GPIO_G_4_IRQ_EN)||(ES_INIT_GPIO_H_4_IRQ_EN) +#define ES_CONF_EXTI_IRQ_4 +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN)||(ES_INIT_GPIO_B_5_IRQ_EN)||(ES_INIT_GPIO_C_5_IRQ_EN)||(ES_INIT_GPIO_D_5_IRQ_EN)|| \ + (ES_INIT_GPIO_E_5_IRQ_EN)||(ES_INIT_GPIO_F_5_IRQ_EN)||(ES_INIT_GPIO_G_5_IRQ_EN)||(ES_INIT_GPIO_H_5_IRQ_EN) +#define ES_CONF_EXTI_IRQ_5 +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN)||(ES_INIT_GPIO_B_6_IRQ_EN)||(ES_INIT_GPIO_C_6_IRQ_EN)||(ES_INIT_GPIO_D_6_IRQ_EN)|| \ + (ES_INIT_GPIO_E_6_IRQ_EN)||(ES_INIT_GPIO_F_6_IRQ_EN)||(ES_INIT_GPIO_G_6_IRQ_EN)||(ES_INIT_GPIO_H_6_IRQ_EN) +#define ES_CONF_EXTI_IRQ_6 +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN)||(ES_INIT_GPIO_B_7_IRQ_EN)||(ES_INIT_GPIO_C_7_IRQ_EN)||(ES_INIT_GPIO_D_7_IRQ_EN)|| \ + (ES_INIT_GPIO_E_7_IRQ_EN)||(ES_INIT_GPIO_F_7_IRQ_EN)||(ES_INIT_GPIO_G_7_IRQ_EN)||(ES_INIT_GPIO_H_7_IRQ_EN) +#define ES_CONF_EXTI_IRQ_7 +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN)||(ES_INIT_GPIO_B_8_IRQ_EN)||(ES_INIT_GPIO_C_8_IRQ_EN)||(ES_INIT_GPIO_D_8_IRQ_EN)|| \ + (ES_INIT_GPIO_E_8_IRQ_EN)||(ES_INIT_GPIO_F_8_IRQ_EN)||(ES_INIT_GPIO_G_8_IRQ_EN)||(ES_INIT_GPIO_H_8_IRQ_EN) +#define ES_CONF_EXTI_IRQ_8 +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN)||(ES_INIT_GPIO_B_9_IRQ_EN)||(ES_INIT_GPIO_C_9_IRQ_EN)||(ES_INIT_GPIO_D_9_IRQ_EN)|| \ + (ES_INIT_GPIO_E_9_IRQ_EN)||(ES_INIT_GPIO_F_9_IRQ_EN)||(ES_INIT_GPIO_G_9_IRQ_EN)||(ES_INIT_GPIO_H_9_IRQ_EN) +#define ES_CONF_EXTI_IRQ_9 +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN)||(ES_INIT_GPIO_B_10_IRQ_EN)||(ES_INIT_GPIO_C_10_IRQ_EN)||(ES_INIT_GPIO_D_10_IRQ_EN)|| \ + (ES_INIT_GPIO_E_10_IRQ_EN)||(ES_INIT_GPIO_F_10_IRQ_EN)||(ES_INIT_GPIO_G_10_IRQ_EN)||(ES_INIT_GPIO_H_10_IRQ_EN) +#define ES_CONF_EXTI_IRQ_10 +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN)||(ES_INIT_GPIO_B_11_IRQ_EN)||(ES_INIT_GPIO_C_11_IRQ_EN)||(ES_INIT_GPIO_D_11_IRQ_EN)|| \ + (ES_INIT_GPIO_E_11_IRQ_EN)||(ES_INIT_GPIO_F_11_IRQ_EN)||(ES_INIT_GPIO_G_11_IRQ_EN)||(ES_INIT_GPIO_H_11_IRQ_EN) +#define ES_CONF_EXTI_IRQ_11 +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN)||(ES_INIT_GPIO_B_12_IRQ_EN)||(ES_INIT_GPIO_C_12_IRQ_EN)||(ES_INIT_GPIO_D_12_IRQ_EN)|| \ + (ES_INIT_GPIO_E_12_IRQ_EN)||(ES_INIT_GPIO_F_12_IRQ_EN)||(ES_INIT_GPIO_G_12_IRQ_EN)||(ES_INIT_GPIO_H_12_IRQ_EN) +#define ES_CONF_EXTI_IRQ_12 +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN)||(ES_INIT_GPIO_B_13_IRQ_EN)||(ES_INIT_GPIO_C_13_IRQ_EN)||(ES_INIT_GPIO_D_13_IRQ_EN)|| \ + (ES_INIT_GPIO_E_13_IRQ_EN)||(ES_INIT_GPIO_F_13_IRQ_EN)||(ES_INIT_GPIO_G_13_IRQ_EN)||(ES_INIT_GPIO_H_13_IRQ_EN) +#define ES_CONF_EXTI_IRQ_13 +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN)||(ES_INIT_GPIO_B_14_IRQ_EN)||(ES_INIT_GPIO_C_14_IRQ_EN)||(ES_INIT_GPIO_D_14_IRQ_EN)|| \ + (ES_INIT_GPIO_E_14_IRQ_EN)||(ES_INIT_GPIO_F_14_IRQ_EN)||(ES_INIT_GPIO_G_14_IRQ_EN)||(ES_INIT_GPIO_H_14_IRQ_EN) +#define ES_CONF_EXTI_IRQ_14 +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN)||(ES_INIT_GPIO_B_15_IRQ_EN)||(ES_INIT_GPIO_C_15_IRQ_EN)||(ES_INIT_GPIO_D_15_IRQ_EN)|| \ + (ES_INIT_GPIO_E_15_IRQ_EN)||(ES_INIT_GPIO_F_15_IRQ_EN)||(ES_INIT_GPIO_G_15_IRQ_EN)||(ES_INIT_GPIO_H_15_IRQ_EN) +#define ES_CONF_EXTI_IRQ_15 +#endif + +#endif //11111 + + +/*GPIO外部中断 声明*/ +#if 11111 + +#ifdef ES_CONF_EXTI_IRQ_0 +void irq_pin0_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 +void irq_pin1_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 +void irq_pin2_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 +void irq_pin3_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 +void irq_pin4_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 +void irq_pin5_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 +void irq_pin6_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 +void irq_pin7_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 +void irq_pin8_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 +void irq_pin9_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 +void irq_pin10_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 +void irq_pin11_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 +void irq_pin12_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 +void irq_pin13_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 +void irq_pin14_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 +void irq_pin15_callback(void* arg); +#endif + + +#endif //11111 + + + + +/*是否有配置的管脚*/ +#if defined(ES_INIT_PIN_GPIO_A_0) || defined(ES_INIT_PIN_GPIO_A_1) || defined(ES_INIT_PIN_GPIO_A_2) || defined(ES_INIT_PIN_GPIO_A_3) || \ + defined(ES_INIT_PIN_GPIO_A_4) || defined(ES_INIT_PIN_GPIO_A_5) || defined(ES_INIT_PIN_GPIO_A_6) || defined(ES_INIT_PIN_GPIO_A_7) || \ + defined(ES_INIT_PIN_GPIO_A_8) || defined(ES_INIT_PIN_GPIO_A_9) || defined(ES_INIT_PIN_GPIO_A_10) || defined(ES_INIT_PIN_GPIO_A_11) || \ + defined(ES_INIT_PIN_GPIO_A_12) || defined(ES_INIT_PIN_GPIO_A_13) || defined(ES_INIT_PIN_GPIO_A_14) || defined(ES_INIT_PIN_GPIO_A_15) || \ + defined(ES_INIT_PIN_GPIO_B_0) || defined(ES_INIT_PIN_GPIO_B_1) || defined(ES_INIT_PIN_GPIO_B_2) || defined(ES_INIT_PIN_GPIO_B_3) || \ + defined(ES_INIT_PIN_GPIO_B_4) || defined(ES_INIT_PIN_GPIO_B_5) || defined(ES_INIT_PIN_GPIO_B_6) || defined(ES_INIT_PIN_GPIO_B_7) || \ + defined(ES_INIT_PIN_GPIO_B_8) || defined(ES_INIT_PIN_GPIO_B_9) || defined(ES_INIT_PIN_GPIO_B_10) || defined(ES_INIT_PIN_GPIO_B_11) || \ + defined(ES_INIT_PIN_GPIO_B_12) || defined(ES_INIT_PIN_GPIO_B_13) || defined(ES_INIT_PIN_GPIO_B_14) || defined(ES_INIT_PIN_GPIO_B_15) || \ + defined(ES_INIT_PIN_GPIO_C_0) || defined(ES_INIT_PIN_GPIO_C_1) || defined(ES_INIT_PIN_GPIO_C_2) || defined(ES_INIT_PIN_GPIO_C_3) || \ + defined(ES_INIT_PIN_GPIO_C_4) || defined(ES_INIT_PIN_GPIO_C_5) || defined(ES_INIT_PIN_GPIO_C_6) || defined(ES_INIT_PIN_GPIO_C_7) || \ + defined(ES_INIT_PIN_GPIO_C_8) || defined(ES_INIT_PIN_GPIO_C_9) || defined(ES_INIT_PIN_GPIO_C_10) || defined(ES_INIT_PIN_GPIO_C_11) || \ + defined(ES_INIT_PIN_GPIO_C_12) || defined(ES_INIT_PIN_GPIO_C_13) || defined(ES_INIT_PIN_GPIO_C_14) || defined(ES_INIT_PIN_GPIO_C_15) || \ + defined(ES_INIT_PIN_GPIO_D_0) || defined(ES_INIT_PIN_GPIO_D_1) || defined(ES_INIT_PIN_GPIO_D_2) || defined(ES_INIT_PIN_GPIO_D_3) || \ + defined(ES_INIT_PIN_GPIO_D_4) || defined(ES_INIT_PIN_GPIO_D_5) || defined(ES_INIT_PIN_GPIO_D_6) || defined(ES_INIT_PIN_GPIO_D_7) || \ + defined(ES_INIT_PIN_GPIO_D_8) || defined(ES_INIT_PIN_GPIO_D_9) || defined(ES_INIT_PIN_GPIO_D_10) || defined(ES_INIT_PIN_GPIO_D_11) || \ + defined(ES_INIT_PIN_GPIO_D_12) || defined(ES_INIT_PIN_GPIO_D_13) || defined(ES_INIT_PIN_GPIO_D_14) || defined(ES_INIT_PIN_GPIO_D_15) || \ + defined(ES_INIT_PIN_GPIO_E_0) || defined(ES_INIT_PIN_GPIO_E_1) || defined(ES_INIT_PIN_GPIO_E_2) || defined(ES_INIT_PIN_GPIO_E_3) || \ + defined(ES_INIT_PIN_GPIO_E_4) || defined(ES_INIT_PIN_GPIO_E_5) || defined(ES_INIT_PIN_GPIO_E_6) || defined(ES_INIT_PIN_GPIO_E_7) || \ + defined(ES_INIT_PIN_GPIO_E_8) || defined(ES_INIT_PIN_GPIO_E_9) || defined(ES_INIT_PIN_GPIO_E_10) || defined(ES_INIT_PIN_GPIO_E_11) || \ + defined(ES_INIT_PIN_GPIO_E_12) || defined(ES_INIT_PIN_GPIO_E_13) || defined(ES_INIT_PIN_GPIO_E_14) || defined(ES_INIT_PIN_GPIO_E_15) || \ + defined(ES_INIT_PIN_GPIO_F_0) || defined(ES_INIT_PIN_GPIO_F_1) || defined(ES_INIT_PIN_GPIO_F_2) || defined(ES_INIT_PIN_GPIO_F_3) || \ + defined(ES_INIT_PIN_GPIO_F_4) || defined(ES_INIT_PIN_GPIO_F_5) || defined(ES_INIT_PIN_GPIO_F_6) || defined(ES_INIT_PIN_GPIO_F_7) || \ + defined(ES_INIT_PIN_GPIO_F_8) || defined(ES_INIT_PIN_GPIO_F_9) || defined(ES_INIT_PIN_GPIO_F_10) || defined(ES_INIT_PIN_GPIO_F_11) || \ + defined(ES_INIT_PIN_GPIO_F_12) || defined(ES_INIT_PIN_GPIO_F_13) || defined(ES_INIT_PIN_GPIO_F_14) || defined(ES_INIT_PIN_GPIO_F_15) || \ + defined(ES_INIT_PIN_GPIO_G_0) || defined(ES_INIT_PIN_GPIO_G_1) || defined(ES_INIT_PIN_GPIO_G_2) || defined(ES_INIT_PIN_GPIO_G_3) || \ + defined(ES_INIT_PIN_GPIO_G_4) || defined(ES_INIT_PIN_GPIO_G_5) || defined(ES_INIT_PIN_GPIO_G_6) || defined(ES_INIT_PIN_GPIO_G_7) || \ + defined(ES_INIT_PIN_GPIO_G_8) || defined(ES_INIT_PIN_GPIO_G_9) || defined(ES_INIT_PIN_GPIO_G_10) || defined(ES_INIT_PIN_GPIO_G_11) || \ + defined(ES_INIT_PIN_GPIO_G_12) || defined(ES_INIT_PIN_GPIO_G_13) || defined(ES_INIT_PIN_GPIO_G_14) || defined(ES_INIT_PIN_GPIO_G_15) || \ + defined(ES_INIT_PIN_GPIO_H_0) || defined(ES_INIT_PIN_GPIO_H_1) || defined(ES_INIT_PIN_GPIO_H_2) || defined(ES_INIT_PIN_GPIO_H_3) || \ + defined(ES_INIT_PIN_GPIO_H_4) || defined(ES_INIT_PIN_GPIO_H_5) || defined(ES_INIT_PIN_GPIO_H_6) || defined(ES_INIT_PIN_GPIO_H_7) || \ + defined(ES_INIT_PIN_GPIO_H_8) || defined(ES_INIT_PIN_GPIO_H_9) || defined(ES_INIT_PIN_GPIO_H_10) || defined(ES_INIT_PIN_GPIO_H_11) || \ + defined(ES_INIT_PIN_GPIO_H_12) || defined(ES_INIT_PIN_GPIO_H_13) || defined(ES_INIT_PIN_GPIO_H_14) || defined(ES_INIT_PIN_GPIO_H_15) + +#define ES_INIT_GPIOS + +#endif + + +#ifdef ES_INIT_GPIOS + +static gpio_conf_t gpio_conf_all[] = +{ + +#ifdef ES_INIT_PIN_GPIO_A_0 + + { + ES_PIN_GPIO_A_0 , + +#ifdef ES_INIT_GPIO_A_0_MODE + ES_INIT_GPIO_A_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_0_LEVEL + ES_INIT_GPIO_A_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_0_IRQ_MODE + ES_INIT_GPIO_A_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_1 + + { + ES_PIN_GPIO_A_1 , + +#ifdef ES_INIT_GPIO_A_1_MODE + ES_INIT_GPIO_A_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_1_LEVEL + ES_INIT_GPIO_A_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_1_IRQ_MODE + ES_INIT_GPIO_A_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_2 + + { + ES_PIN_GPIO_A_2 , + +#ifdef ES_INIT_GPIO_A_2_MODE + ES_INIT_GPIO_A_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_2_LEVEL + ES_INIT_GPIO_A_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_2_IRQ_MODE + ES_INIT_GPIO_A_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_3 + + { + ES_PIN_GPIO_A_3 , + +#ifdef ES_INIT_GPIO_A_3_MODE + ES_INIT_GPIO_A_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_3_LEVEL + ES_INIT_GPIO_A_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_3_IRQ_MODE + ES_INIT_GPIO_A_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_4 + + { + ES_PIN_GPIO_A_4 , + +#ifdef ES_INIT_GPIO_A_4_MODE + ES_INIT_GPIO_A_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_4_LEVEL + ES_INIT_GPIO_A_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_4_IRQ_MODE + ES_INIT_GPIO_A_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_5 + + { + ES_PIN_GPIO_A_5 , + +#ifdef ES_INIT_GPIO_A_5_MODE + ES_INIT_GPIO_A_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_5_LEVEL + ES_INIT_GPIO_A_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_5_IRQ_MODE + ES_INIT_GPIO_A_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_6 + + { + ES_PIN_GPIO_A_6 , + +#ifdef ES_INIT_GPIO_A_6_MODE + ES_INIT_GPIO_A_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_6_LEVEL + ES_INIT_GPIO_A_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_6_IRQ_MODE + ES_INIT_GPIO_A_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_7 + + { + ES_PIN_GPIO_A_7 , + +#ifdef ES_INIT_GPIO_A_7_MODE + ES_INIT_GPIO_A_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_7_LEVEL + ES_INIT_GPIO_A_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_7_IRQ_MODE + ES_INIT_GPIO_A_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_8 + + { + ES_PIN_GPIO_A_8 , + +#ifdef ES_INIT_GPIO_A_8_MODE + ES_INIT_GPIO_A_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_8_LEVEL + ES_INIT_GPIO_A_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_8_IRQ_MODE + ES_INIT_GPIO_A_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_9 + + { + ES_PIN_GPIO_A_9 , + +#ifdef ES_INIT_GPIO_A_9_MODE + ES_INIT_GPIO_A_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_9_LEVEL + ES_INIT_GPIO_A_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_9_IRQ_MODE + ES_INIT_GPIO_A_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_10 + + { + ES_PIN_GPIO_A_10 , + +#ifdef ES_INIT_GPIO_A_10_MODE + ES_INIT_GPIO_A_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_10_LEVEL + ES_INIT_GPIO_A_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_10_IRQ_MODE + ES_INIT_GPIO_A_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_11 + + { + ES_PIN_GPIO_A_11 , + +#ifdef ES_INIT_GPIO_A_11_MODE + ES_INIT_GPIO_A_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_11_LEVEL + ES_INIT_GPIO_A_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_11_IRQ_MODE + ES_INIT_GPIO_A_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_12 + + { + ES_PIN_GPIO_A_12 , + +#ifdef ES_INIT_GPIO_A_12_MODE + ES_INIT_GPIO_A_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_12_LEVEL + ES_INIT_GPIO_A_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_12_IRQ_MODE + ES_INIT_GPIO_A_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_13 + + { + ES_PIN_GPIO_A_13 , + +#ifdef ES_INIT_GPIO_A_13_MODE + ES_INIT_GPIO_A_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_13_LEVEL + ES_INIT_GPIO_A_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_13_IRQ_MODE + ES_INIT_GPIO_A_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_14 + + { + ES_PIN_GPIO_A_14 , + +#ifdef ES_INIT_GPIO_A_14_MODE + ES_INIT_GPIO_A_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_14_LEVEL + ES_INIT_GPIO_A_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_14_IRQ_MODE + ES_INIT_GPIO_A_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_15 + + { + ES_PIN_GPIO_A_15 , + +#ifdef ES_INIT_GPIO_A_15_MODE + ES_INIT_GPIO_A_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_15_LEVEL + ES_INIT_GPIO_A_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_15_IRQ_MODE + ES_INIT_GPIO_A_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_0 + + { + ES_PIN_GPIO_B_0 , + +#ifdef ES_INIT_GPIO_B_0_MODE + ES_INIT_GPIO_B_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_0_LEVEL + ES_INIT_GPIO_B_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_0_IRQ_MODE + ES_INIT_GPIO_B_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_1 + + { + ES_PIN_GPIO_B_1 , + +#ifdef ES_INIT_GPIO_B_1_MODE + ES_INIT_GPIO_B_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_1_LEVEL + ES_INIT_GPIO_B_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_1_IRQ_MODE + ES_INIT_GPIO_B_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_2 + + { + ES_PIN_GPIO_B_2 , + +#ifdef ES_INIT_GPIO_B_2_MODE + ES_INIT_GPIO_B_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_2_LEVEL + ES_INIT_GPIO_B_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_2_IRQ_MODE + ES_INIT_GPIO_B_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_3 + + { + ES_PIN_GPIO_B_3 , + +#ifdef ES_INIT_GPIO_B_3_MODE + ES_INIT_GPIO_B_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_3_LEVEL + ES_INIT_GPIO_B_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_3_IRQ_MODE + ES_INIT_GPIO_B_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_4 + + { + ES_PIN_GPIO_B_4 , + +#ifdef ES_INIT_GPIO_B_4_MODE + ES_INIT_GPIO_B_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_4_LEVEL + ES_INIT_GPIO_B_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_4_IRQ_MODE + ES_INIT_GPIO_B_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_5 + + { + ES_PIN_GPIO_B_5 , + +#ifdef ES_INIT_GPIO_B_5_MODE + ES_INIT_GPIO_B_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_5_LEVEL + ES_INIT_GPIO_B_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_5_IRQ_MODE + ES_INIT_GPIO_B_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_6 + + { + ES_PIN_GPIO_B_6 , + +#ifdef ES_INIT_GPIO_B_6_MODE + ES_INIT_GPIO_B_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_6_LEVEL + ES_INIT_GPIO_B_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_6_IRQ_MODE + ES_INIT_GPIO_B_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_7 + + { + ES_PIN_GPIO_B_7 , + +#ifdef ES_INIT_GPIO_B_7_MODE + ES_INIT_GPIO_B_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_7_LEVEL + ES_INIT_GPIO_B_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_7_IRQ_MODE + ES_INIT_GPIO_B_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_8 + + { + ES_PIN_GPIO_B_8 , + +#ifdef ES_INIT_GPIO_B_8_MODE + ES_INIT_GPIO_B_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_8_LEVEL + ES_INIT_GPIO_B_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_8_IRQ_MODE + ES_INIT_GPIO_B_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_9 + + { + ES_PIN_GPIO_B_9 , + +#ifdef ES_INIT_GPIO_B_9_MODE + ES_INIT_GPIO_B_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_9_LEVEL + ES_INIT_GPIO_B_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_9_IRQ_MODE + ES_INIT_GPIO_B_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_10 + + { + ES_PIN_GPIO_B_10 , + +#ifdef ES_INIT_GPIO_B_10_MODE + ES_INIT_GPIO_B_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_10_LEVEL + ES_INIT_GPIO_B_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_10_IRQ_MODE + ES_INIT_GPIO_B_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_11 + + { + ES_PIN_GPIO_B_11 , + +#ifdef ES_INIT_GPIO_B_11_MODE + ES_INIT_GPIO_B_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_11_LEVEL + ES_INIT_GPIO_B_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_11_IRQ_MODE + ES_INIT_GPIO_B_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_12 + + { + ES_PIN_GPIO_B_12 , + +#ifdef ES_INIT_GPIO_B_12_MODE + ES_INIT_GPIO_B_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_12_LEVEL + ES_INIT_GPIO_B_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_12_IRQ_MODE + ES_INIT_GPIO_B_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_13 + + { + ES_PIN_GPIO_B_13 , + +#ifdef ES_INIT_GPIO_B_13_MODE + ES_INIT_GPIO_B_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_13_LEVEL + ES_INIT_GPIO_B_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_13_IRQ_MODE + ES_INIT_GPIO_B_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_14 + + { + ES_PIN_GPIO_B_14 , + +#ifdef ES_INIT_GPIO_B_14_MODE + ES_INIT_GPIO_B_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_14_LEVEL + ES_INIT_GPIO_B_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_14_IRQ_MODE + ES_INIT_GPIO_B_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_15 + + { + ES_PIN_GPIO_B_15 , + +#ifdef ES_INIT_GPIO_B_15_MODE + ES_INIT_GPIO_B_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_15_LEVEL + ES_INIT_GPIO_B_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_15_IRQ_MODE + ES_INIT_GPIO_B_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_0 + + { + ES_PIN_GPIO_C_0 , + +#ifdef ES_INIT_GPIO_C_0_MODE + ES_INIT_GPIO_C_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_0_LEVEL + ES_INIT_GPIO_C_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_0_IRQ_MODE + ES_INIT_GPIO_C_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_1 + + { + ES_PIN_GPIO_C_1 , + +#ifdef ES_INIT_GPIO_C_1_MODE + ES_INIT_GPIO_C_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_1_LEVEL + ES_INIT_GPIO_C_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_1_IRQ_MODE + ES_INIT_GPIO_C_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_2 + + { + ES_PIN_GPIO_C_2 , + +#ifdef ES_INIT_GPIO_C_2_MODE + ES_INIT_GPIO_C_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_2_LEVEL + ES_INIT_GPIO_C_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_2_IRQ_MODE + ES_INIT_GPIO_C_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_3 + + { + ES_PIN_GPIO_C_3 , + +#ifdef ES_INIT_GPIO_C_3_MODE + ES_INIT_GPIO_C_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_3_LEVEL + ES_INIT_GPIO_C_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_3_IRQ_MODE + ES_INIT_GPIO_C_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_4 + + { + ES_PIN_GPIO_C_4 , + +#ifdef ES_INIT_GPIO_C_4_MODE + ES_INIT_GPIO_C_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_4_LEVEL + ES_INIT_GPIO_C_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_4_IRQ_MODE + ES_INIT_GPIO_C_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_5 + + { + ES_PIN_GPIO_C_5 , + +#ifdef ES_INIT_GPIO_C_5_MODE + ES_INIT_GPIO_C_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_5_LEVEL + ES_INIT_GPIO_C_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_5_IRQ_MODE + ES_INIT_GPIO_C_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_6 + + { + ES_PIN_GPIO_C_6 , + +#ifdef ES_INIT_GPIO_C_6_MODE + ES_INIT_GPIO_C_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_6_LEVEL + ES_INIT_GPIO_C_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_6_IRQ_MODE + ES_INIT_GPIO_C_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_7 + + { + ES_PIN_GPIO_C_7 , + +#ifdef ES_INIT_GPIO_C_7_MODE + ES_INIT_GPIO_C_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_7_LEVEL + ES_INIT_GPIO_C_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_7_IRQ_MODE + ES_INIT_GPIO_C_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_8 + + { + ES_PIN_GPIO_C_8 , + +#ifdef ES_INIT_GPIO_C_8_MODE + ES_INIT_GPIO_C_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_8_LEVEL + ES_INIT_GPIO_C_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_8_IRQ_MODE + ES_INIT_GPIO_C_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_9 + + { + ES_PIN_GPIO_C_9 , + +#ifdef ES_INIT_GPIO_C_9_MODE + ES_INIT_GPIO_C_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_9_LEVEL + ES_INIT_GPIO_C_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_9_IRQ_MODE + ES_INIT_GPIO_C_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_10 + + { + ES_PIN_GPIO_C_10 , + +#ifdef ES_INIT_GPIO_C_10_MODE + ES_INIT_GPIO_C_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_10_LEVEL + ES_INIT_GPIO_C_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_10_IRQ_MODE + ES_INIT_GPIO_C_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_11 + + { + ES_PIN_GPIO_C_11 , + +#ifdef ES_INIT_GPIO_C_11_MODE + ES_INIT_GPIO_C_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_11_LEVEL + ES_INIT_GPIO_C_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_11_IRQ_MODE + ES_INIT_GPIO_C_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_12 + + { + ES_PIN_GPIO_C_12 , + +#ifdef ES_INIT_GPIO_C_12_MODE + ES_INIT_GPIO_C_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_12_LEVEL + ES_INIT_GPIO_C_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_12_IRQ_MODE + ES_INIT_GPIO_C_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_13 + + { + ES_PIN_GPIO_C_13 , + +#ifdef ES_INIT_GPIO_C_13_MODE + ES_INIT_GPIO_C_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_13_LEVEL + ES_INIT_GPIO_C_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_13_IRQ_MODE + ES_INIT_GPIO_C_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_14 + + { + ES_PIN_GPIO_C_14 , + +#ifdef ES_INIT_GPIO_C_14_MODE + ES_INIT_GPIO_C_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_14_LEVEL + ES_INIT_GPIO_C_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_14_IRQ_MODE + ES_INIT_GPIO_C_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_15 + + { + ES_PIN_GPIO_C_15 , + +#ifdef ES_INIT_GPIO_C_15_MODE + ES_INIT_GPIO_C_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_15_LEVEL + ES_INIT_GPIO_C_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_15_IRQ_MODE + ES_INIT_GPIO_C_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_0 + + { + ES_PIN_GPIO_D_0 , + +#ifdef ES_INIT_GPIO_D_0_MODE + ES_INIT_GPIO_D_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_0_LEVEL + ES_INIT_GPIO_D_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_0_IRQ_MODE + ES_INIT_GPIO_D_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_1 + + { + ES_PIN_GPIO_D_1 , + +#ifdef ES_INIT_GPIO_D_1_MODE + ES_INIT_GPIO_D_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_1_LEVEL + ES_INIT_GPIO_D_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_1_IRQ_MODE + ES_INIT_GPIO_D_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_2 + + { + ES_PIN_GPIO_D_2 , + +#ifdef ES_INIT_GPIO_D_2_MODE + ES_INIT_GPIO_D_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_2_LEVEL + ES_INIT_GPIO_D_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_2_IRQ_MODE + ES_INIT_GPIO_D_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_3 + + { + ES_PIN_GPIO_D_3 , + +#ifdef ES_INIT_GPIO_D_3_MODE + ES_INIT_GPIO_D_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_3_LEVEL + ES_INIT_GPIO_D_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_3_IRQ_MODE + ES_INIT_GPIO_D_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_4 + + { + ES_PIN_GPIO_D_4 , + +#ifdef ES_INIT_GPIO_D_4_MODE + ES_INIT_GPIO_D_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_4_LEVEL + ES_INIT_GPIO_D_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_4_IRQ_MODE + ES_INIT_GPIO_D_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_5 + + { + ES_PIN_GPIO_D_5 , + +#ifdef ES_INIT_GPIO_D_5_MODE + ES_INIT_GPIO_D_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_5_LEVEL + ES_INIT_GPIO_D_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_5_IRQ_MODE + ES_INIT_GPIO_D_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_6 + + { + ES_PIN_GPIO_D_6 , + +#ifdef ES_INIT_GPIO_D_6_MODE + ES_INIT_GPIO_D_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_6_LEVEL + ES_INIT_GPIO_D_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_6_IRQ_MODE + ES_INIT_GPIO_D_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_7 + + { + ES_PIN_GPIO_D_7 , + +#ifdef ES_INIT_GPIO_D_7_MODE + ES_INIT_GPIO_D_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_7_LEVEL + ES_INIT_GPIO_D_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_7_IRQ_MODE + ES_INIT_GPIO_D_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_8 + + { + ES_PIN_GPIO_D_8 , + +#ifdef ES_INIT_GPIO_D_8_MODE + ES_INIT_GPIO_D_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_8_LEVEL + ES_INIT_GPIO_D_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_8_IRQ_MODE + ES_INIT_GPIO_D_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_9 + + { + ES_PIN_GPIO_D_9 , + +#ifdef ES_INIT_GPIO_D_9_MODE + ES_INIT_GPIO_D_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_9_LEVEL + ES_INIT_GPIO_D_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_9_IRQ_MODE + ES_INIT_GPIO_D_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_10 + + { + ES_PIN_GPIO_D_10 , + +#ifdef ES_INIT_GPIO_D_10_MODE + ES_INIT_GPIO_D_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_10_LEVEL + ES_INIT_GPIO_D_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_10_IRQ_MODE + ES_INIT_GPIO_D_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_11 + + { + ES_PIN_GPIO_D_11 , + +#ifdef ES_INIT_GPIO_D_11_MODE + ES_INIT_GPIO_D_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_11_LEVEL + ES_INIT_GPIO_D_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_11_IRQ_MODE + ES_INIT_GPIO_D_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_12 + + { + ES_PIN_GPIO_D_12 , + +#ifdef ES_INIT_GPIO_D_12_MODE + ES_INIT_GPIO_D_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_12_LEVEL + ES_INIT_GPIO_D_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_12_IRQ_MODE + ES_INIT_GPIO_D_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_13 + + { + ES_PIN_GPIO_D_13 , + +#ifdef ES_INIT_GPIO_D_13_MODE + ES_INIT_GPIO_D_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_13_LEVEL + ES_INIT_GPIO_D_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_13_IRQ_MODE + ES_INIT_GPIO_D_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_14 + + { + ES_PIN_GPIO_D_14 , + +#ifdef ES_INIT_GPIO_D_14_MODE + ES_INIT_GPIO_D_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_14_LEVEL + ES_INIT_GPIO_D_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_14_IRQ_MODE + ES_INIT_GPIO_D_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_15 + + { + ES_PIN_GPIO_D_15 , + +#ifdef ES_INIT_GPIO_D_15_MODE + ES_INIT_GPIO_D_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_15_LEVEL + ES_INIT_GPIO_D_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_15_IRQ_MODE + ES_INIT_GPIO_D_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_0 + + { + ES_PIN_GPIO_E_0 , + +#ifdef ES_INIT_GPIO_E_0_MODE + ES_INIT_GPIO_E_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_0_LEVEL + ES_INIT_GPIO_E_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_0_IRQ_MODE + ES_INIT_GPIO_E_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_1 + + { + ES_PIN_GPIO_E_1 , + +#ifdef ES_INIT_GPIO_E_1_MODE + ES_INIT_GPIO_E_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_1_LEVEL + ES_INIT_GPIO_E_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_1_IRQ_MODE + ES_INIT_GPIO_E_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_2 + + { + ES_PIN_GPIO_E_2 , + +#ifdef ES_INIT_GPIO_E_2_MODE + ES_INIT_GPIO_E_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_2_LEVEL + ES_INIT_GPIO_E_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_2_IRQ_MODE + ES_INIT_GPIO_E_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_3 + + { + ES_PIN_GPIO_E_3 , + +#ifdef ES_INIT_GPIO_E_3_MODE + ES_INIT_GPIO_E_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_3_LEVEL + ES_INIT_GPIO_E_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_3_IRQ_MODE + ES_INIT_GPIO_E_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_4 + + { + ES_PIN_GPIO_E_4 , + +#ifdef ES_INIT_GPIO_E_4_MODE + ES_INIT_GPIO_E_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_4_LEVEL + ES_INIT_GPIO_E_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_4_IRQ_MODE + ES_INIT_GPIO_E_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_5 + + { + ES_PIN_GPIO_E_5 , + +#ifdef ES_INIT_GPIO_E_5_MODE + ES_INIT_GPIO_E_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_5_LEVEL + ES_INIT_GPIO_E_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_5_IRQ_MODE + ES_INIT_GPIO_E_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_6 + + { + ES_PIN_GPIO_E_6 , + +#ifdef ES_INIT_GPIO_E_6_MODE + ES_INIT_GPIO_E_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_6_LEVEL + ES_INIT_GPIO_E_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_6_IRQ_MODE + ES_INIT_GPIO_E_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_7 + + { + ES_PIN_GPIO_E_7 , + +#ifdef ES_INIT_GPIO_E_7_MODE + ES_INIT_GPIO_E_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_7_LEVEL + ES_INIT_GPIO_E_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_7_IRQ_MODE + ES_INIT_GPIO_E_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_8 + + { + ES_PIN_GPIO_E_8 , + +#ifdef ES_INIT_GPIO_E_8_MODE + ES_INIT_GPIO_E_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_8_LEVEL + ES_INIT_GPIO_E_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_8_IRQ_MODE + ES_INIT_GPIO_E_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_9 + + { + ES_PIN_GPIO_E_9 , + +#ifdef ES_INIT_GPIO_E_9_MODE + ES_INIT_GPIO_E_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_9_LEVEL + ES_INIT_GPIO_E_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_9_IRQ_MODE + ES_INIT_GPIO_E_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_10 + + { + ES_PIN_GPIO_E_10 , + +#ifdef ES_INIT_GPIO_E_10_MODE + ES_INIT_GPIO_E_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_10_LEVEL + ES_INIT_GPIO_E_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_10_IRQ_MODE + ES_INIT_GPIO_E_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_11 + + { + ES_PIN_GPIO_E_11 , + +#ifdef ES_INIT_GPIO_E_11_MODE + ES_INIT_GPIO_E_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_11_LEVEL + ES_INIT_GPIO_E_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_11_IRQ_MODE + ES_INIT_GPIO_E_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_12 + + { + ES_PIN_GPIO_E_12 , + +#ifdef ES_INIT_GPIO_E_12_MODE + ES_INIT_GPIO_E_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_12_LEVEL + ES_INIT_GPIO_E_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_12_IRQ_MODE + ES_INIT_GPIO_E_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_13 + + { + ES_PIN_GPIO_E_13 , + +#ifdef ES_INIT_GPIO_E_13_MODE + ES_INIT_GPIO_E_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_13_LEVEL + ES_INIT_GPIO_E_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_13_IRQ_MODE + ES_INIT_GPIO_E_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_14 + + { + ES_PIN_GPIO_E_14 , + +#ifdef ES_INIT_GPIO_E_14_MODE + ES_INIT_GPIO_E_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_14_LEVEL + ES_INIT_GPIO_E_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_14_IRQ_MODE + ES_INIT_GPIO_E_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_15 + + { + ES_PIN_GPIO_E_15 , + +#ifdef ES_INIT_GPIO_E_15_MODE + ES_INIT_GPIO_E_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_15_LEVEL + ES_INIT_GPIO_E_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_15_IRQ_MODE + ES_INIT_GPIO_E_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_0 + + { + ES_PIN_GPIO_F_0 , + +#ifdef ES_INIT_GPIO_F_0_MODE + ES_INIT_GPIO_F_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_0_LEVEL + ES_INIT_GPIO_F_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_0_IRQ_MODE + ES_INIT_GPIO_F_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_1 + + { + ES_PIN_GPIO_F_1 , + +#ifdef ES_INIT_GPIO_F_1_MODE + ES_INIT_GPIO_F_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_1_LEVEL + ES_INIT_GPIO_F_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_1_IRQ_MODE + ES_INIT_GPIO_F_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_2 + + { + ES_PIN_GPIO_F_2 , + +#ifdef ES_INIT_GPIO_F_2_MODE + ES_INIT_GPIO_F_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_2_LEVEL + ES_INIT_GPIO_F_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_2_IRQ_MODE + ES_INIT_GPIO_F_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_3 + + { + ES_PIN_GPIO_F_3 , + +#ifdef ES_INIT_GPIO_F_3_MODE + ES_INIT_GPIO_F_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_3_LEVEL + ES_INIT_GPIO_F_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_3_IRQ_MODE + ES_INIT_GPIO_F_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_4 + + { + ES_PIN_GPIO_F_4 , + +#ifdef ES_INIT_GPIO_F_4_MODE + ES_INIT_GPIO_F_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_4_LEVEL + ES_INIT_GPIO_F_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_4_IRQ_MODE + ES_INIT_GPIO_F_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_5 + + { + ES_PIN_GPIO_F_5 , + +#ifdef ES_INIT_GPIO_F_5_MODE + ES_INIT_GPIO_F_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_5_LEVEL + ES_INIT_GPIO_F_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_5_IRQ_MODE + ES_INIT_GPIO_F_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_6 + + { + ES_PIN_GPIO_F_6 , + +#ifdef ES_INIT_GPIO_F_6_MODE + ES_INIT_GPIO_F_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_6_LEVEL + ES_INIT_GPIO_F_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_6_IRQ_MODE + ES_INIT_GPIO_F_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_7 + + { + ES_PIN_GPIO_F_7 , + +#ifdef ES_INIT_GPIO_F_7_MODE + ES_INIT_GPIO_F_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_7_LEVEL + ES_INIT_GPIO_F_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_7_IRQ_MODE + ES_INIT_GPIO_F_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_8 + + { + ES_PIN_GPIO_F_8 , + +#ifdef ES_INIT_GPIO_F_8_MODE + ES_INIT_GPIO_F_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_8_LEVEL + ES_INIT_GPIO_F_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_8_IRQ_MODE + ES_INIT_GPIO_F_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_9 + + { + ES_PIN_GPIO_F_9 , + +#ifdef ES_INIT_GPIO_F_9_MODE + ES_INIT_GPIO_F_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_9_LEVEL + ES_INIT_GPIO_F_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_9_IRQ_MODE + ES_INIT_GPIO_F_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_10 + + { + ES_PIN_GPIO_F_10 , + +#ifdef ES_INIT_GPIO_F_10_MODE + ES_INIT_GPIO_F_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_10_LEVEL + ES_INIT_GPIO_F_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_10_IRQ_MODE + ES_INIT_GPIO_F_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_11 + + { + ES_PIN_GPIO_F_11 , + +#ifdef ES_INIT_GPIO_F_11_MODE + ES_INIT_GPIO_F_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_11_LEVEL + ES_INIT_GPIO_F_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_11_IRQ_MODE + ES_INIT_GPIO_F_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_12 + + { + ES_PIN_GPIO_F_12 , + +#ifdef ES_INIT_GPIO_F_12_MODE + ES_INIT_GPIO_F_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_12_LEVEL + ES_INIT_GPIO_F_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_12_IRQ_MODE + ES_INIT_GPIO_F_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_13 + + { + ES_PIN_GPIO_F_13 , + +#ifdef ES_INIT_GPIO_F_13_MODE + ES_INIT_GPIO_F_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_13_LEVEL + ES_INIT_GPIO_F_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_13_IRQ_MODE + ES_INIT_GPIO_F_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_14 + + { + ES_PIN_GPIO_F_14 , + +#ifdef ES_INIT_GPIO_F_14_MODE + ES_INIT_GPIO_F_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_14_LEVEL + ES_INIT_GPIO_F_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_14_IRQ_MODE + ES_INIT_GPIO_F_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_15 + + { + ES_PIN_GPIO_F_15 , + +#ifdef ES_INIT_GPIO_F_15_MODE + ES_INIT_GPIO_F_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_15_LEVEL + ES_INIT_GPIO_F_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_15_IRQ_MODE + ES_INIT_GPIO_F_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_0 + + { + ES_PIN_GPIO_G_0 , + +#ifdef ES_INIT_GPIO_G_0_MODE + ES_INIT_GPIO_G_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_0_LEVEL + ES_INIT_GPIO_G_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_0_IRQ_MODE + ES_INIT_GPIO_G_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_1 + + { + ES_PIN_GPIO_G_1 , + +#ifdef ES_INIT_GPIO_G_1_MODE + ES_INIT_GPIO_G_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_1_LEVEL + ES_INIT_GPIO_G_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_1_IRQ_MODE + ES_INIT_GPIO_G_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_2 + + { + ES_PIN_GPIO_G_2 , + +#ifdef ES_INIT_GPIO_G_2_MODE + ES_INIT_GPIO_G_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_2_LEVEL + ES_INIT_GPIO_G_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_2_IRQ_MODE + ES_INIT_GPIO_G_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_3 + + { + ES_PIN_GPIO_G_3 , + +#ifdef ES_INIT_GPIO_G_3_MODE + ES_INIT_GPIO_G_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_3_LEVEL + ES_INIT_GPIO_G_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_3_IRQ_MODE + ES_INIT_GPIO_G_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_4 + + { + ES_PIN_GPIO_G_4 , + +#ifdef ES_INIT_GPIO_G_4_MODE + ES_INIT_GPIO_G_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_4_LEVEL + ES_INIT_GPIO_G_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_4_IRQ_MODE + ES_INIT_GPIO_G_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_5 + + { + ES_PIN_GPIO_G_5 , + +#ifdef ES_INIT_GPIO_G_5_MODE + ES_INIT_GPIO_G_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_5_LEVEL + ES_INIT_GPIO_G_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_5_IRQ_MODE + ES_INIT_GPIO_G_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_6 + + { + ES_PIN_GPIO_G_6 , + +#ifdef ES_INIT_GPIO_G_6_MODE + ES_INIT_GPIO_G_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_6_LEVEL + ES_INIT_GPIO_G_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_6_IRQ_MODE + ES_INIT_GPIO_G_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_7 + + { + ES_PIN_GPIO_G_7 , + +#ifdef ES_INIT_GPIO_G_7_MODE + ES_INIT_GPIO_G_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_7_LEVEL + ES_INIT_GPIO_G_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_7_IRQ_MODE + ES_INIT_GPIO_G_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_8 + + { + ES_PIN_GPIO_G_8 , + +#ifdef ES_INIT_GPIO_G_8_MODE + ES_INIT_GPIO_G_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_8_LEVEL + ES_INIT_GPIO_G_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_8_IRQ_MODE + ES_INIT_GPIO_G_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_9 + + { + ES_PIN_GPIO_G_9 , + +#ifdef ES_INIT_GPIO_G_9_MODE + ES_INIT_GPIO_G_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_9_LEVEL + ES_INIT_GPIO_G_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_9_IRQ_MODE + ES_INIT_GPIO_G_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_10 + + { + ES_PIN_GPIO_G_10 , + +#ifdef ES_INIT_GPIO_G_10_MODE + ES_INIT_GPIO_G_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_10_LEVEL + ES_INIT_GPIO_G_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_10_IRQ_MODE + ES_INIT_GPIO_G_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_11 + + { + ES_PIN_GPIO_G_11 , + +#ifdef ES_INIT_GPIO_G_11_MODE + ES_INIT_GPIO_G_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_11_LEVEL + ES_INIT_GPIO_G_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_11_IRQ_MODE + ES_INIT_GPIO_G_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_12 + + { + ES_PIN_GPIO_G_12 , + +#ifdef ES_INIT_GPIO_G_12_MODE + ES_INIT_GPIO_G_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_12_LEVEL + ES_INIT_GPIO_G_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_12_IRQ_MODE + ES_INIT_GPIO_G_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_13 + + { + ES_PIN_GPIO_G_13 , + +#ifdef ES_INIT_GPIO_G_13_MODE + ES_INIT_GPIO_G_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_13_LEVEL + ES_INIT_GPIO_G_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_13_IRQ_MODE + ES_INIT_GPIO_G_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_14 + + { + ES_PIN_GPIO_G_14 , + +#ifdef ES_INIT_GPIO_G_14_MODE + ES_INIT_GPIO_G_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_14_LEVEL + ES_INIT_GPIO_G_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_14_IRQ_MODE + ES_INIT_GPIO_G_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_15 + + { + ES_PIN_GPIO_G_15 , + +#ifdef ES_INIT_GPIO_G_15_MODE + ES_INIT_GPIO_G_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_15_LEVEL + ES_INIT_GPIO_G_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_15_IRQ_MODE + ES_INIT_GPIO_G_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_0 + + { + ES_PIN_GPIO_H_0 , + +#ifdef ES_INIT_GPIO_H_0_MODE + ES_INIT_GPIO_H_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_0_LEVEL + ES_INIT_GPIO_H_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_0_IRQ_MODE + ES_INIT_GPIO_H_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_1 + + { + ES_PIN_GPIO_H_1 , + +#ifdef ES_INIT_GPIO_H_1_MODE + ES_INIT_GPIO_H_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_1_LEVEL + ES_INIT_GPIO_H_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_1_IRQ_MODE + ES_INIT_GPIO_H_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_2 + + { + ES_PIN_GPIO_H_2 , + +#ifdef ES_INIT_GPIO_H_2_MODE + ES_INIT_GPIO_H_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_2_LEVEL + ES_INIT_GPIO_H_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_2_IRQ_MODE + ES_INIT_GPIO_H_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_3 + + { + ES_PIN_GPIO_H_3 , + +#ifdef ES_INIT_GPIO_H_3_MODE + ES_INIT_GPIO_H_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_3_LEVEL + ES_INIT_GPIO_H_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_3_IRQ_MODE + ES_INIT_GPIO_H_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_4 + + { + ES_PIN_GPIO_H_4 , + +#ifdef ES_INIT_GPIO_H_4_MODE + ES_INIT_GPIO_H_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_4_LEVEL + ES_INIT_GPIO_H_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_4_IRQ_MODE + ES_INIT_GPIO_H_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_5 + + { + ES_PIN_GPIO_H_5 , + +#ifdef ES_INIT_GPIO_H_5_MODE + ES_INIT_GPIO_H_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_5_LEVEL + ES_INIT_GPIO_H_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_5_IRQ_MODE + ES_INIT_GPIO_H_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_6 + + { + ES_PIN_GPIO_H_6 , + +#ifdef ES_INIT_GPIO_H_6_MODE + ES_INIT_GPIO_H_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_6_LEVEL + ES_INIT_GPIO_H_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_6_IRQ_MODE + ES_INIT_GPIO_H_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_7 + + { + ES_PIN_GPIO_H_7 , + +#ifdef ES_INIT_GPIO_H_7_MODE + ES_INIT_GPIO_H_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_7_LEVEL + ES_INIT_GPIO_H_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_7_IRQ_MODE + ES_INIT_GPIO_H_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_8 + + { + ES_PIN_GPIO_H_8 , + +#ifdef ES_INIT_GPIO_H_8_MODE + ES_INIT_GPIO_H_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_8_LEVEL + ES_INIT_GPIO_H_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_8_IRQ_MODE + ES_INIT_GPIO_H_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_9 + + { + ES_PIN_GPIO_H_9 , + +#ifdef ES_INIT_GPIO_H_9_MODE + ES_INIT_GPIO_H_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_9_LEVEL + ES_INIT_GPIO_H_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_9_IRQ_MODE + ES_INIT_GPIO_H_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_10 + + { + ES_PIN_GPIO_H_10 , + +#ifdef ES_INIT_GPIO_H_10_MODE + ES_INIT_GPIO_H_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_10_LEVEL + ES_INIT_GPIO_H_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_10_IRQ_MODE + ES_INIT_GPIO_H_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_11 + + { + ES_PIN_GPIO_H_11 , + +#ifdef ES_INIT_GPIO_H_11_MODE + ES_INIT_GPIO_H_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_11_LEVEL + ES_INIT_GPIO_H_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_11_IRQ_MODE + ES_INIT_GPIO_H_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_12 + + { + ES_PIN_GPIO_H_12 , + +#ifdef ES_INIT_GPIO_H_12_MODE + ES_INIT_GPIO_H_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_12_LEVEL + ES_INIT_GPIO_H_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_12_IRQ_MODE + ES_INIT_GPIO_H_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_13 + + { + ES_PIN_GPIO_H_13 , + +#ifdef ES_INIT_GPIO_H_13_MODE + ES_INIT_GPIO_H_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_13_LEVEL + ES_INIT_GPIO_H_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_13_IRQ_MODE + ES_INIT_GPIO_H_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_14 + + { + ES_PIN_GPIO_H_14 , + +#ifdef ES_INIT_GPIO_H_14_MODE + ES_INIT_GPIO_H_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_14_LEVEL + ES_INIT_GPIO_H_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_14_IRQ_MODE + ES_INIT_GPIO_H_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_15 + + { + ES_PIN_GPIO_H_15 , + +#ifdef ES_INIT_GPIO_H_15_MODE + ES_INIT_GPIO_H_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_15_LEVEL + ES_INIT_GPIO_H_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_15_IRQ_MODE + ES_INIT_GPIO_H_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + + + +}; + +#endif + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h new file mode 100644 index 0000000000..d829c68f93 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h @@ -0,0 +1,103 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_HWTIMER_H__ +#define __ES_CONF_INFO_HWTIMER_H__ + +#include +#include + +#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP +#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW + +/* HWTIMER 配置 */ + +/* codes_main */ + + + +#ifndef ES_AD16C4T0_HWTIMER_MODE +#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + +#ifndef ES_GP16C4T0_HWTIMER_MODE +#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C2T0_HWTIMER_MODE +#define ES_GP16C2T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP1624T1_HWTIMER_MODE +#define ES_GP16C2T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T0_HWTIMER_MODE +#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T1_HWTIMER_MODE +#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T2_HWTIMER_MODE +#define ES_BS16T2_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T3_HWTIMER_MODE +#define ES_BS16T3_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + + + + +#define ES_AD16C4T0_HWTIMER_PRES 1 +#define ES_GP16C4T0_HWTIMER_PRES 1 +#define ES_GP16C2T0_HWTIMER_PRES 1 +#define ES_GP16C2T1_HWTIMER_PRES 1 +#define ES_BS16T0_HWTIMER_PRES 1 +#define ES_BS16T1_HWTIMER_PRES 1 +#define ES_BS16T2_HWTIMER_PRES 1 +#define ES_BS16T3_HWTIMER_PRES 1 + +#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER +#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER +#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer1" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T0_HWTIMER +#define ES_DEVICE_NAME_GP16C2T0_HWTIMER "timer2" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T1_HWTIMER +#define ES_DEVICE_NAME_GP16C2T1_HWTIMER "timer3" +#endif +#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER +#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer4" +#endif +#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER +#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer5" +#endif +#ifndef ES_DEVICE_NAME_BS16T2_HWTIMER +#define ES_DEVICE_NAME_BS16T2_HWTIMER "timer6" +#endif +#ifndef ES_DEVICE_NAME_BS16T3_HWTIMER +#define ES_DEVICE_NAME_BS16T3_HWTIMER "timer7" +#endif + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_i2c.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_i2c.h new file mode 100644 index 0000000000..65310fce01 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_i2c.h @@ -0,0 +1,95 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_I2C_H__ +#define __ES_CONF_INFO_I2C_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +#define ES_C_I2C_STRETCH I2C_NOSTRETCH_DISABLE +#define ES_C_I2C_NO_STRETCH I2C_NOSTRETCH_ENABLE + +#define ES_C_I2C_GENERALCALL I2C_GENERALCALL_ENABLE +#define ES_C_I2C_NO_GENERALCALL I2C_GENERALCALL_DISABLE + + +#define ES_C_I2C_ADDR_7_MODE I2C_ADDR_7BIT +#define ES_C_I2C_ADDR_10_MODE I2C_ADDR_10BIT + + +/* I2C 配置 */ + + + +/* codes_main */ + + + + + +#ifndef ES_DEVICE_NAME_I2C0 +#define ES_DEVICE_NAME_I2C0 "i2c0" +#endif + +#ifndef ES_DEVICE_NAME_I2C1 +#define ES_DEVICE_NAME_I2C1 "i2c1" +#endif + +#ifndef ES_I2C0_CLK_SPEED +#define ES_I2C0_CLK_SPEED 100000 +#endif +#ifndef ES_I2C0_OWN_ADDR1 +#define ES_I2C0_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C0_GENERAL_CALL +#define ES_I2C0_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C0_STRETCH +#define ES_I2C0_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C0_ADDR_MODE +#define ES_I2C0_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + +#ifndef ES_I2C1_CLK_SPEED +#define ES_I2C1_CLK_SPEED 100000 +#endif +#ifndef ES_I2C1_OWN_ADDR1 +#define ES_I2C1_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C1_GENERAL_CALL +#define ES_I2C1_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C1_STRETCH +#define ES_I2C1_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C1_ADDR_MODE +#define ES_I2C1_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_map.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_map.h new file mode 100644 index 0000000000..62274d122f --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_map.h @@ -0,0 +1,2691 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __es_conf_info_map_H__ +#define __es_conf_info_map_H__ + +#include + + +#define __ES_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} +#define __ES_PIN_DEFAULT {-1, 0, 0} + +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +static const struct pin_index pins[] = +{ + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(2, C, 13), + __ES_PIN(3, C, 14), + __ES_PIN(4, C, 15), + __ES_PIN(5, H, 0), + __ES_PIN(6, H, 1), + __ES_PIN_DEFAULT, + __ES_PIN(8, C, 0), + __ES_PIN(9, C, 1), + __ES_PIN(10, C, 2), + __ES_PIN(11, C, 3), + __ES_PIN(12, H, 3), + __ES_PIN(13, H, 4), + __ES_PIN(14, A, 0), + __ES_PIN(15, A, 1), + __ES_PIN(16, A, 2), + __ES_PIN(17, A, 3), + __ES_PIN(18, F, 0), + __ES_PIN(19, F, 1), + __ES_PIN(20, A, 4), + __ES_PIN(21, A, 5), + __ES_PIN(22, A, 6), + __ES_PIN(23, A, 7), + __ES_PIN(24, C, 4), + __ES_PIN(25, C, 5), + __ES_PIN(26, B, 0), + __ES_PIN(27, B, 1), + __ES_PIN(28, B, 2), + __ES_PIN(29, B, 10), + __ES_PIN(30, B, 11), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(33, B, 12), + __ES_PIN(34, B, 13), + __ES_PIN(35, B, 14), + __ES_PIN(36, B, 15), + __ES_PIN(37, C, 6), + __ES_PIN(38, C, 7), + __ES_PIN(39, C, 8), + __ES_PIN(40, C, 9), + __ES_PIN(41, A, 8), + __ES_PIN(42, A, 9), + __ES_PIN(43, A, 10), + __ES_PIN(44, A, 11), + __ES_PIN(45, A, 12), + __ES_PIN(46, A, 13), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(49, A, 14), + __ES_PIN(50, A, 15), + __ES_PIN(51, C, 10), + __ES_PIN(52, C, 11), + __ES_PIN(53, C, 12), + __ES_PIN(54, D, 2), + __ES_PIN(55, B, 3), + __ES_PIN(56, B, 4), + __ES_PIN(57, B, 5), + __ES_PIN(58, B, 6), + __ES_PIN(59, B, 7), + __ES_PIN(60, H, 2), + __ES_PIN(61, B, 8), + __ES_PIN(62, B, 9), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, +}; + +#define ES_GPIO_ADC_CH0_GPIO GPIOC +#define ES_GPIO_ADC_CH1_GPIO GPIOC +#define ES_GPIO_ADC_CH2_GPIO GPIOC +#define ES_GPIO_ADC_CH3_GPIO GPIOC +#define ES_GPIO_ADC_CH4_GPIO GPIOA +#define ES_GPIO_ADC_CH5_GPIO GPIOA +#define ES_GPIO_ADC_CH6_GPIO GPIOA +#define ES_GPIO_ADC_CH7_GPIO GPIOA +#define ES_GPIO_ADC_CH8_GPIO GPIOA +#define ES_GPIO_ADC_CH9_GPIO GPIOA +#define ES_GPIO_ADC_CH10_GPIO GPIOA +#define ES_GPIO_ADC_CH11_GPIO GPIOA +#define ES_GPIO_ADC_CH12_GPIO GPIOC +#define ES_GPIO_ADC_CH13_GPIO GPIOC +#define ES_GPIO_ADC_CH14_GPIO GPIOB +#define ES_GPIO_ADC_CH15_GPIO GPIOB + +#define ES_GPIO_ADC_CH0_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH1_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH2_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH3_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH4_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH5_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH6_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH7_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH8_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH9_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH10_PIN GPIO_PIN_6 +#define ES_GPIO_ADC_CH11_PIN GPIO_PIN_7 +#define ES_GPIO_ADC_CH12_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH13_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH14_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH15_PIN GPIO_PIN_1 + + + + +#define ES_PIN_GPIO_C_13 2 +#define ES_PIN_GPIO_C_14 3 +#define ES_PIN_GPIO_C_15 4 +#define ES_PIN_GPIO_H_0 5 +#define ES_PIN_GPIO_H_1 6 +#define ES_PIN_GPIO_C_0 8 +#define ES_PIN_GPIO_C_1 9 +#define ES_PIN_GPIO_C_2 10 +#define ES_PIN_GPIO_C_3 11 +#define ES_PIN_GPIO_H_3 12 +#define ES_PIN_GPIO_H_4 13 +#define ES_PIN_GPIO_A_0 14 +#define ES_PIN_GPIO_A_1 15 +#define ES_PIN_GPIO_A_2 16 +#define ES_PIN_GPIO_A_3 17 +#define ES_PIN_GPIO_F_0 18 +#define ES_PIN_GPIO_F_1 19 +#define ES_PIN_GPIO_A_4 20 +#define ES_PIN_GPIO_A_5 21 +#define ES_PIN_GPIO_A_6 22 +#define ES_PIN_GPIO_A_7 23 +#define ES_PIN_GPIO_C_4 24 +#define ES_PIN_GPIO_C_5 25 +#define ES_PIN_GPIO_B_0 26 +#define ES_PIN_GPIO_B_1 27 +#define ES_PIN_GPIO_B_2 28 +#define ES_PIN_GPIO_B_10 29 +#define ES_PIN_GPIO_B_11 30 +#define ES_PIN_GPIO_B_12 33 +#define ES_PIN_GPIO_B_13 34 +#define ES_PIN_GPIO_B_14 35 +#define ES_PIN_GPIO_B_15 36 +#define ES_PIN_GPIO_C_6 37 +#define ES_PIN_GPIO_C_7 38 +#define ES_PIN_GPIO_C_8 39 +#define ES_PIN_GPIO_C_9 40 +#define ES_PIN_GPIO_A_8 41 +#define ES_PIN_GPIO_A_9 42 +#define ES_PIN_GPIO_A_10 43 +#define ES_PIN_GPIO_A_11 44 +#define ES_PIN_GPIO_A_12 45 +#define ES_PIN_GPIO_A_13 46 +#define ES_PIN_GPIO_A_14 49 +#define ES_PIN_GPIO_A_15 50 +#define ES_PIN_GPIO_C_10 51 +#define ES_PIN_GPIO_C_11 52 +#define ES_PIN_GPIO_C_12 53 +#define ES_PIN_GPIO_D_2 54 +#define ES_PIN_GPIO_B_3 55 +#define ES_PIN_GPIO_B_4 56 +#define ES_PIN_GPIO_B_5 57 +#define ES_PIN_GPIO_B_6 58 +#define ES_PIN_GPIO_B_7 59 +#define ES_PIN_GPIO_H_2 60 +#define ES_PIN_GPIO_B_8 61 +#define ES_PIN_GPIO_B_9 62 + + + +/* UART_TX */ + + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_UART0_TX_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_A_9 +#define ES_UART0_TX_PIN ES_PIN_GPIO_A_9 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_UART0_TX_PIN ES_PIN_GPIO_H_0 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_D_8 +#define ES_UART0_TX_PIN ES_PIN_GPIO_D_8 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_A_13 +#define ES_UART1_TX_PIN ES_PIN_GPIO_A_13 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_UART1_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART2_TX_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_UART2_TX_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_E_2 +#define ES_UART2_TX_PIN ES_PIN_GPIO_E_2 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_UART3_TX_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_UART3_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_UART3_TX_PIN ES_PIN_GPIO_D_14 +#endif +#endif + + +/* UART_RX */ + + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_A_10 +#define ES_UART0_RX_PIN ES_PIN_GPIO_A_10 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_UART0_RX_PIN ES_PIN_GPIO_H_1 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_UART0_RX_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_D_9 +#define ES_UART0_RX_PIN ES_PIN_GPIO_D_9 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_1 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_A_14 +#define ES_UART1_RX_PIN ES_PIN_GPIO_A_14 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_UART1_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART2_RX_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_UART2_RX_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_E_3 +#define ES_UART2_RX_PIN ES_PIN_GPIO_E_3 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_UART3_RX_PIN ES_PIN_GPIO_C_5 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_UART3_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_UART3_RX_PIN ES_PIN_GPIO_D_13 +#endif +#endif + + +/* UART_RTS */ + + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_A_12 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_A_12 +#endif +#endif + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_D_12 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_3 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_E_5 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_E_5 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_B_1 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + + +/* UART_CTS */ + + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_A_11 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_A_11 +#endif +#endif + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_D_11 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_D_11 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_E_4 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_E_4 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + + +/* UART_CK */ + + + +/* USART_TX */ + + +#ifndef ES_USART0_TX_GPIO_FUNC +#define ES_USART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_TX_GPIO_PORT +#define ES_USART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_USART0_TX_GPIO_PIN +#define ES_USART0_TX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_USART0_TX_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_USART0_TX_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_USART0_TX_GPIO_FUNC +#define ES_USART0_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_TX_GPIO_PORT +#define ES_USART0_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_TX_GPIO_PIN +#define ES_USART0_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_USART0_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_USART0_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_USART1_TX_GPIO_FUNC +#define ES_USART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_TX_GPIO_PORT +#define ES_USART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_USART1_TX_GPIO_PIN +#define ES_USART1_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_USART1_TX_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_USART1_TX_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_USART1_TX_GPIO_FUNC +#define ES_USART1_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART1_TX_GPIO_PORT +#define ES_USART1_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_USART1_TX_GPIO_PIN +#define ES_USART1_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_USART1_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_USART1_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_USART1_TX_GPIO_FUNC +#define ES_USART1_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_TX_GPIO_PORT +#define ES_USART1_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_TX_GPIO_PIN +#define ES_USART1_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_USART1_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_USART1_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + + +/* USART_RX */ + + +#ifndef ES_USART0_RX_GPIO_FUNC +#define ES_USART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_RX_GPIO_PORT +#define ES_USART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_USART0_RX_GPIO_PIN +#define ES_USART0_RX_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_USART0_RX_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_USART0_RX_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_USART0_RX_GPIO_FUNC +#define ES_USART0_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_RX_GPIO_PORT +#define ES_USART0_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_RX_GPIO_PIN +#define ES_USART0_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_USART0_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_USART0_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_USART1_RX_GPIO_FUNC +#define ES_USART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_RX_GPIO_PORT +#define ES_USART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_USART1_RX_GPIO_PIN +#define ES_USART1_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_USART1_RX_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_USART1_RX_PIN ES_PIN_GPIO_A_3 +#endif +#endif + +#ifndef ES_USART1_RX_GPIO_FUNC +#define ES_USART1_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_RX_GPIO_PORT +#define ES_USART1_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_RX_GPIO_PIN +#define ES_USART1_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_USART1_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_USART1_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + +#ifndef ES_USART1_RX_GPIO_FUNC +#define ES_USART1_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART1_RX_GPIO_PORT +#define ES_USART1_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_USART1_RX_GPIO_PIN +#define ES_USART1_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_USART1_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_USART1_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* USART_RTS */ + + +#ifndef ES_USART0_RTS_GPIO_FUNC +#define ES_USART0_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_RTS_GPIO_PORT +#define ES_USART0_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_RTS_GPIO_PIN +#define ES_USART0_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_USART0_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_USART0_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_USART0_RTS_GPIO_FUNC +#define ES_USART0_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_RTS_GPIO_PORT +#define ES_USART0_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_RTS_GPIO_PIN +#define ES_USART0_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_USART0_RTS_PIN +#ifdef ES_PIN_GPIO_E_1 +#define ES_USART0_RTS_PIN ES_PIN_GPIO_E_1 +#endif +#endif + +#ifndef ES_USART1_RTS_GPIO_FUNC +#define ES_USART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_RTS_GPIO_PORT +#define ES_USART1_RTS_GPIO_PORT GPIOA +#endif +#ifndef ES_USART1_RTS_GPIO_PIN +#define ES_USART1_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_USART1_RTS_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_USART1_RTS_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_USART1_RTS_GPIO_FUNC +#define ES_USART1_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_RTS_GPIO_PORT +#define ES_USART1_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_RTS_GPIO_PIN +#define ES_USART1_RTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_USART1_RTS_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_USART1_RTS_PIN ES_PIN_GPIO_D_4 +#endif +#endif + + +/* USART_CTS */ + + +#ifndef ES_USART0_CTS_GPIO_FUNC +#define ES_USART0_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_CTS_GPIO_PORT +#define ES_USART0_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_CTS_GPIO_PIN +#define ES_USART0_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_USART0_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_USART0_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_USART0_CTS_GPIO_FUNC +#define ES_USART0_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_CTS_GPIO_PORT +#define ES_USART0_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_CTS_GPIO_PIN +#define ES_USART0_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_USART0_CTS_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_USART0_CTS_PIN ES_PIN_GPIO_E_0 +#endif +#endif + +#ifndef ES_USART1_CTS_GPIO_FUNC +#define ES_USART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_CTS_GPIO_PORT +#define ES_USART1_CTS_GPIO_PORT GPIOF +#endif +#ifndef ES_USART1_CTS_GPIO_PIN +#define ES_USART1_CTS_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_USART1_CTS_PIN +#ifdef ES_PIN_GPIO_F_7 +#define ES_USART1_CTS_PIN ES_PIN_GPIO_F_7 +#endif +#endif + +#ifndef ES_USART1_CTS_GPIO_FUNC +#define ES_USART1_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_CTS_GPIO_PORT +#define ES_USART1_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_CTS_GPIO_PIN +#define ES_USART1_CTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_USART1_CTS_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_USART1_CTS_PIN ES_PIN_GPIO_D_3 +#endif +#endif + + +/* USART_CK */ + + +#ifndef ES_USART0_CK_GPIO_FUNC +#define ES_USART0_CK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART0_CK_GPIO_PORT +#define ES_USART0_CK_GPIO_PORT GPIOA +#endif +#ifndef ES_USART0_CK_GPIO_PIN +#define ES_USART0_CK_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_USART0_CK_PIN +#ifdef ES_PIN_GPIO_A_8 +#define ES_USART0_CK_PIN ES_PIN_GPIO_A_8 +#endif +#endif + +#ifndef ES_USART0_CK_GPIO_FUNC +#define ES_USART0_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART0_CK_GPIO_PORT +#define ES_USART0_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_CK_GPIO_PIN +#define ES_USART0_CK_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_USART0_CK_PIN +#ifdef ES_PIN_GPIO_E_6 +#define ES_USART0_CK_PIN ES_PIN_GPIO_E_6 +#endif +#endif + +#ifndef ES_USART0_CK_GPIO_FUNC +#define ES_USART0_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART0_CK_GPIO_PORT +#define ES_USART0_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_USART0_CK_GPIO_PIN +#define ES_USART0_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_USART0_CK_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_USART0_CK_PIN ES_PIN_GPIO_E_7 +#endif +#endif + +#ifndef ES_USART1_CK_GPIO_FUNC +#define ES_USART1_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_USART1_CK_GPIO_PORT +#define ES_USART1_CK_GPIO_PORT GPIOA +#endif +#ifndef ES_USART1_CK_GPIO_PIN +#define ES_USART1_CK_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_USART1_CK_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_USART1_CK_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_USART1_CK_GPIO_FUNC +#define ES_USART1_CK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_USART1_CK_GPIO_PORT +#define ES_USART1_CK_GPIO_PORT GPIOD +#endif +#ifndef ES_USART1_CK_GPIO_PIN +#define ES_USART1_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_USART1_CK_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_USART1_CK_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_USART1_CK_GPIO_FUNC +#define ES_USART1_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_USART1_CK_GPIO_PORT +#define ES_USART1_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_USART1_CK_GPIO_PIN +#define ES_USART1_CK_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_USART1_CK_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_USART1_CK_PIN ES_PIN_GPIO_E_0 +#endif +#endif + + +/* I2C_SCL */ + + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_H_0 +#endif +#endif + + +/* I2C_SDA */ + + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_H_1 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_B_11 +#endif +#endif + + +/* SPI_MISO */ + + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_D_4 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_B_14 +#endif +#endif + + +/* SPI_MOSI */ + + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_A_7 +#endif +#endif + + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_C_3 +#endif +#endif + + +/* SPI_SCK */ + + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_D_3 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_C_1 +#endif +#endif + + +/* SPI_NSS */ + + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_B_12 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_B_12 +#endif +#endif + + +/* CAN_TX */ + + +#ifndef ES_CAN0_TX_GPIO_FUNC +#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_CAN0_TX_GPIO_PORT +#define ES_CAN0_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_CAN0_TX_GPIO_PIN +#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_CAN0_TX_PIN +#ifdef ES_PIN_GPIO_A_12 +#define ES_CAN0_TX_PIN ES_PIN_GPIO_A_12 +#endif +#endif + +#ifndef ES_CAN0_TX_GPIO_FUNC +#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_TX_GPIO_PORT +#define ES_CAN0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_TX_GPIO_PIN +#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_CAN0_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_CAN0_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + + +/* CAN_RX */ + + +#ifndef ES_CAN0_RX_GPIO_FUNC +#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_CAN0_RX_GPIO_PORT +#define ES_CAN0_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_CAN0_RX_GPIO_PIN +#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_CAN0_RX_PIN +#ifdef ES_PIN_GPIO_A_11 +#define ES_CAN0_RX_PIN ES_PIN_GPIO_A_11 +#endif +#endif + +#ifndef ES_CAN0_RX_GPIO_FUNC +#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_RX_GPIO_PORT +#define ES_CAN0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_RX_GPIO_PIN +#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_CAN0_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_CAN0_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* AD16C4T_CH1 */ + + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_8 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_A_8 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_E_9 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_E_9 +#endif +#endif + + +/* AD16C4T_CH2 */ + + +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_9 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_A_9 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_E_11 +#endif +#endif + + +/* AD16C4T_CH3 */ + + +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_A_10 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_A_10 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_E_13 +#endif +#endif + + +/* AD16C4T_CH4 */ + + +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_E_14 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_E_14 +#endif +#endif + +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_A_11 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_A_11 +#endif +#endif + + +/* AD16C4T_CH1N */ + + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_E_8 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_E_8 +#endif +#endif + + +/* AD16C4T_CH2N */ + + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_E_10 +#endif +#endif + + +/* AD16C4T_CH3N */ + + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_1 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_E_12 +#endif +#endif + + +/* AD16C4T_CH4N */ + + + +/* AD16C4T_ET */ + + +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_AD16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_12 +#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_A_12 +#endif +#endif + +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_E_7 +#endif +#endif + + +/* GP32C4T_CH1 */ + + + +/* GP32C4T_CH2 */ + + + +/* GP32C4T_CH3 */ + + + +/* GP32C4T_CH4 */ + + + +/* GP32C4T_ET */ + + + +/* GP16C4T_CH1 */ + + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_D_12 +#endif +#endif + + +/* GP16C4T_CH2 */ + + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_D_13 +#endif +#endif + + +/* GP16C4T_CH3 */ + + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_D_14 +#endif +#endif + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* GP16C4T_CH4 */ + + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_D_15 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_D_15 +#endif +#endif + + +/* GP16C4T_ET */ + + +#ifndef ES_GP16C4T0_ET_GPIO_FUNC +#define ES_GP16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PORT +#define ES_GP16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PIN +#define ES_GP16C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_GP16C4T0_ET_PIN ES_PIN_GPIO_E_0 +#endif +#endif + + +/* GP16C2T_CH1 */ + + +#ifndef ES_GP16C2T0_CH1_GPIO_FUNC +#define ES_GP16C2T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T0_CH1_GPIO_PORT +#define ES_GP16C2T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T0_CH1_GPIO_PIN +#define ES_GP16C2T0_CH1_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP16C2T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP16C2T0_CH1_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_GP16C2T0_CH1_GPIO_FUNC +#define ES_GP16C2T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T0_CH1_GPIO_PORT +#define ES_GP16C2T0_CH1_GPIO_PORT GPIOF +#endif +#ifndef ES_GP16C2T0_CH1_GPIO_PIN +#define ES_GP16C2T0_CH1_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C2T0_CH1_PIN +#ifdef ES_PIN_GPIO_F_7 +#define ES_GP16C2T0_CH1_PIN ES_PIN_GPIO_F_7 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1_GPIO_FUNC +#define ES_GP16C2T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PORT +#define ES_GP16C2T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PIN +#define ES_GP16C2T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP16C2T1_CH1_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_GP16C2T1_CH1_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1_GPIO_FUNC +#define ES_GP16C2T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PORT +#define ES_GP16C2T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PIN +#define ES_GP16C2T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP16C2T1_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_GP16C2T1_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1_GPIO_FUNC +#define ES_GP16C2T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PORT +#define ES_GP16C2T1_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C2T1_CH1_GPIO_PIN +#define ES_GP16C2T1_CH1_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_GP16C2T1_CH1_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_GP16C2T1_CH1_PIN ES_PIN_GPIO_B_4 +#endif +#endif + + +/* GP16C2T_CH2 */ + + +#ifndef ES_GP16C2T0_CH2_GPIO_FUNC +#define ES_GP16C2T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T0_CH2_GPIO_PORT +#define ES_GP16C2T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T0_CH2_GPIO_PIN +#define ES_GP16C2T0_CH2_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP16C2T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_GP16C2T0_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_GP16C2T0_CH2_GPIO_FUNC +#define ES_GP16C2T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T0_CH2_GPIO_PORT +#define ES_GP16C2T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C2T0_CH2_GPIO_PIN +#define ES_GP16C2T0_CH2_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP16C2T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_GP16C2T0_CH2_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_GP16C2T1_CH2_GPIO_FUNC +#define ES_GP16C2T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PORT +#define ES_GP16C2T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PIN +#define ES_GP16C2T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C2T1_CH2_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_GP16C2T1_CH2_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_GP16C2T1_CH2_GPIO_FUNC +#define ES_GP16C2T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PORT +#define ES_GP16C2T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PIN +#define ES_GP16C2T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C2T1_CH2_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_GP16C2T1_CH2_PIN ES_PIN_GPIO_C_7 +#endif +#endif + +#ifndef ES_GP16C2T1_CH2_GPIO_FUNC +#define ES_GP16C2T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PORT +#define ES_GP16C2T1_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C2T1_CH2_GPIO_PIN +#define ES_GP16C2T1_CH2_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_GP16C2T1_CH2_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_GP16C2T1_CH2_PIN ES_PIN_GPIO_B_5 +#endif +#endif + + +/* GP16C2T_CH1N */ + + +#ifndef ES_GP16C2T0_CH1N_GPIO_FUNC +#define ES_GP16C2T0_CH1N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP16C2T0_CH1N_GPIO_PORT +#define ES_GP16C2T0_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C2T0_CH1N_GPIO_PIN +#define ES_GP16C2T0_CH1N_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP16C2T0_CH1N_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_GP16C2T0_CH1N_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_GP16C2T0_CH1N_GPIO_FUNC +#define ES_GP16C2T0_CH1N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP16C2T0_CH1N_GPIO_PORT +#define ES_GP16C2T0_CH1N_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C2T0_CH1N_GPIO_PIN +#define ES_GP16C2T0_CH1N_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_GP16C2T0_CH1N_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_GP16C2T0_CH1N_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1N_GPIO_FUNC +#define ES_GP16C2T1_CH1N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP16C2T1_CH1N_GPIO_PORT +#define ES_GP16C2T1_CH1N_GPIO_PORT GPIOC +#endif +#ifndef ES_GP16C2T1_CH1N_GPIO_PIN +#define ES_GP16C2T1_CH1N_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_GP16C2T1_CH1N_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_GP16C2T1_CH1N_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_GP16C2T1_CH1N_GPIO_FUNC +#define ES_GP16C2T1_CH1N_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP16C2T1_CH1N_GPIO_PORT +#define ES_GP16C2T1_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C2T1_CH1N_GPIO_PIN +#define ES_GP16C2T1_CH1N_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP16C2T1_CH1N_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_GP16C2T1_CH1N_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* GP16C2T_CH2N */ + + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pm.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pm.h new file mode 100644 index 0000000000..580268312c --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pm.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PM_H__ +#define __ES_CONF_INFO_PM_H__ + +#include +#include + +#define ES_PMU_SAVE_LOAD_UART + +/* PM 配置 */ + + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pwm.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pwm.h new file mode 100644 index 0000000000..bb0c034da9 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_pwm.h @@ -0,0 +1,72 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PWM_H__ +#define __ES_CONF_INFO_PWM_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + + +#define ES_C_PWM_OC_POL_HIGH TIMER_OC_POLARITY_HIGH +#define ES_C_PWM_OC_POL_LOW TIMER_OC_POLARITY_LOW + +#define ES_C_PWM_OC_MODE_PWM1 TIMER_OC_MODE_PWM1 +#define ES_C_PWM_OC_MODE_PWM2 TIMER_OC_MODE_PWM2 + + + +/* PWM 配置 */ + + +/* codes_main */ + + + +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM1 + +#ifndef ES_PWM_OC_POLARITY +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#endif +#ifndef ES_PWM_OC_MODE +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 +#endif + +#ifndef ES_DEVICE_NAME_AD16C4T0_PWM +#define ES_DEVICE_NAME_AD16C4T0_PWM "pwm0" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_PWM +#define ES_DEVICE_NAME_GP16C4T0_PWM "pwm1" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T0_PWM +#define ES_DEVICE_NAME_GP16C2T0_PWM "pwm2" +#endif +#ifndef ES_DEVICE_NAME_GP16C2T1_PWM +#define ES_DEVICE_NAME_GP16C2T1_PWM "pwm3" +#endif + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_rtc.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_rtc.h new file mode 100644 index 0000000000..2aa8faf9d7 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_rtc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_RTC_H__ +#define __ES_CONF_INFO_RTC_H__ + +#include +#include + +/* RTC 配置 */ + +#define ES_C_RTC_SOURCE_LRC RTC_SOURCE_LRC +#define ES_C_RTC_SOURCE_LOSC RTC_SOURCE_LOSC + +#define ES_RTC_CLK_SOURCE ES_C_RTC_SOURCE_LOSC + + + + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_RTC +#define ES_DEVICE_NAME_RTC "rtc" +#endif + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_select.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_select.h new file mode 100644 index 0000000000..47ac7c4e6a --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_select.h @@ -0,0 +1,44 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SELECT_H__ +#define __ES_CONF_INFO_SELECT_H__ + + +#define ES_C_ENABLE 1 +#define ES_C_DISABLE 0 + + +/* codes_main */ +//#define ES_USE_ASSERT ES_C_ENABLE + +#ifndef ES_USE_ASSERT +#define ES_USE_ASSERT ES_C_DISABLE +#endif + + +#if ES_USE_ASSERT + #define USE_ASSERT +#endif + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_spi.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_spi.h new file mode 100644 index 0000000000..182bc4c44c --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_spi.h @@ -0,0 +1,132 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SPI_H__ +#define __ES_CONF_INFO_SPI_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +/* SPI 配置 */ + +#define SPI_BUS_CONFIG(_CONF_,_I_) do{_CONF_.mode = 0U; \ + _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE | \ + ES_SPI##_I_##_WIRE_3_4 | \ + ES_SPI##_I_##_CPHA_1_2 | \ + ES_SPI##_I_##_CPOL_H_L | \ + ES_SPI##_I_##_CS | \ + ES_SPI##_I_##_M_L_SB ); \ + _CONF_.data_width = ES_SPI##_I_##_DATA_W; \ + _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ; \ + }while(0) + + +// spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ +// spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ +// spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ +// spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ +// spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ +// spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ +// spi_config.data_width = 8; /* 数据长度：8 */ +// spi_config.max_hz = 2000000; /* 最快时钟频率 */ + +#define ES_C_SPI_CLK_POL_HIGH RT_SPI_CPOL +#define ES_C_SPI_CLK_POL_LOW !RT_SPI_CPOL + +#define ES_C_SPI_CLK_PHA_FIRST !RT_SPI_CPHA +#define ES_C_SPI_CLK_PHA_SECOND RT_SPI_CPHA + +#define ES_C_SPI_MSB RT_SPI_MSB +#define ES_C_SPI_LSB RT_SPI_LSB + +#define ES_C_SPI_CS_LOW_LEVEL 0 +#define ES_C_SPI_CS_HIGH_LEVEL 1 + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_SPI0_BUS +#define ES_DEVICE_NAME_SPI0_BUS "spi0" +#endif +#ifndef ES_DEVICE_NAME_SPI0_DEV0 +#define ES_DEVICE_NAME_SPI0_DEV0 "spi00" +#endif + +#ifndef ES_DEVICE_NAME_SPI1_BUS +#define ES_DEVICE_NAME_SPI1_BUS "spi1" +#endif +#ifndef ES_DEVICE_NAME_SPI1_DEV0 +#define ES_DEVICE_NAME_SPI1_DEV0 "spi10" +#endif + + +#define ES_SPI_CS_LEVEL ES_C_SPI_CS_LOW_LEVEL + +#ifndef ES_SPI0_CPHA_1_2 +#define ES_SPI0_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI0_CPOL_H_L +#define ES_SPI0_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI0_M_L_SB +#define ES_SPI0_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI0_MAX_HZ +#define ES_SPI0_MAX_HZ 2000000 +#endif +#ifndef ES_SPI0_NSS_PIN +#define ES_SPI0_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI1_CPHA_1_2 +#define ES_SPI1_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI1_CPOL_H_L +#define ES_SPI1_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI1_M_L_SB +#define ES_SPI1_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI1_MAX_HZ +#define ES_SPI1_MAX_HZ 2000000 +#endif +#ifndef ES_SPI1_NSS_PIN +#define ES_SPI1_NSS_PIN 0xFFFFFFFF +#endif + + + +#define ES_SPI0_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI0_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI0_CS RT_SPI_NO_CS +#define ES_SPI0_DATA_W 8 + +#define ES_SPI1_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI1_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI1_CS RT_SPI_NO_CS +#define ES_SPI1_DATA_W 8 + + +#endif diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_uart.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_uart.h new file mode 100644 index 0000000000..2dd32aa220 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_uart.h @@ -0,0 +1,206 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_UART_H__ +#define __ES_CONF_INFO_UART_H__ + +#include "es_conf_info_map.h" +#include +#include +#include +#include + + + +#define ES_C_UART_PARITY_NONE PARITY_NONE +#define ES_C_UART_PARITY_ODD PARITY_ODD +#define ES_C_UART_PARITY_EVEN PARITY_EVEN + +#define ES_C_UART_STOP_1 STOP_BITS_1 +#define ES_C_UART_STOP_2 STOP_BITS_2 + + +/* UART 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_UART0 +#define ES_DEVICE_NAME_UART0 "uart0" +#endif +#ifndef ES_DEVICE_NAME_UART1 +#define ES_DEVICE_NAME_UART1 "uart1" +#endif +#ifndef ES_DEVICE_NAME_UART2 +#define ES_DEVICE_NAME_UART2 "uart2" +#endif +#ifndef ES_DEVICE_NAME_UART3 +#define ES_DEVICE_NAME_UART3 "uart3" +#endif +#ifndef ES_DEVICE_NAME_USART0 +#define ES_DEVICE_NAME_USART0 "usart0" +#endif +#ifndef ES_DEVICE_NAME_USART1 +#define ES_DEVICE_NAME_USART1 "usart1" +#endif + +#ifndef ES_CONF_UART0_BAUD_RATE +#define ES_CONF_UART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART0_PARITY +#define ES_CONF_UART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART0_STOP_BITS +#define ES_CONF_UART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART1_BAUD_RATE +#define ES_CONF_UART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART1_PARITY +#define ES_CONF_UART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART1_STOP_BITS +#define ES_CONF_UART1_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART2_BAUD_RATE +#define ES_CONF_UART2_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART2_PARITY +#define ES_CONF_UART2_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART2_STOP_BITS +#define ES_CONF_UART2_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART3_BAUD_RATE +#define ES_CONF_UART3_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART3_PARITY +#define ES_CONF_UART3_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART3_STOP_BITS +#define ES_CONF_UART3_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_USART0_BAUD_RATE +#define ES_CONF_USART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_USART0_PARITY +#define ES_CONF_USART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_USART0_STOP_BITS +#define ES_CONF_USART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_USART1_BAUD_RATE +#define ES_CONF_USART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_USART1_PARITY +#define ES_CONF_USART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_USART1_STOP_BITS +#define ES_CONF_USART1_STOP_BITS ES_C_UART_STOP_1 +#endif + + +#define ES_UART0_CONFIG \ +{ \ + ES_CONF_UART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART0_STOP_BITS, \ + ES_CONF_UART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART1_CONFIG \ +{ \ + ES_CONF_UART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART1_STOP_BITS, \ + ES_CONF_UART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART2_CONFIG \ +{ \ + ES_CONF_UART2_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART2_STOP_BITS, \ + ES_CONF_UART2_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART3_CONFIG \ +{ \ + ES_CONF_UART3_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART3_STOP_BITS, \ + ES_CONF_UART3_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_USART0_CONFIG \ +{ \ + ES_CONF_USART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_USART0_STOP_BITS, \ + ES_CONF_USART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_USART1_CONFIG \ +{ \ + ES_CONF_USART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_USART1_STOP_BITS, \ + ES_CONF_USART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + +#endif diff --git a/bsp/essemi/es32f0654/drivers/Kconfig b/bsp/essemi/es32f0654/drivers/Kconfig index 3c3cf9e9e5..75d678805d 100644 --- a/bsp/essemi/es32f0654/drivers/Kconfig +++ b/bsp/essemi/es32f0654/drivers/Kconfig @@ -6,129 +6,7 @@ menu "Hardware Drivers Config" select RT_USING_PIN default y - menu "UART Drivers" - config BSP_USING_UART0 - bool "Enable UART0 PB10/PB11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART1 - bool "Enable UART1 PC10/PC11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART2 - bool "Enable UART2 PC12/PD02(T/R)" - select RT_USING_SERIAL - default y - depends on !BSP_USING_HWTIMER1 - - config BSP_USING_UART3 - bool "Enable UART3 PC04/PC05(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_HWTIMER2 - endmenu - - menu "SPI Drivers" - config BSP_USING_SPI0 - bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI1 - bool "Enable SPI1 BUS PB13/PB14/PB15(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - endmenu - - menu "I2C Drivers" - config BSP_USING_I2C0 - bool "Enable I2C0 BUS PB08/PB09(SCL/SDA)" - select RT_USING_I2C - default n - - config BSP_USING_I2C1 - bool "Enable I2C1 BUS PB10/PB11(SCL/SDA)" - select RT_USING_I2C - default n - endmenu - - menu "CAN Drivers" - config BSP_USING_CAN - bool "Enable CAN BUS PA11/PA12(RX/TX)" - select RT_USING_CAN - default n - endmenu - - menu "PWM Drivers" - config BSP_USING_PWM0 - bool "Using PWM0 PA08/PA09/PA10/PA11" - select RT_USING_PWM - default n - - config BSP_USING_PWM1 - bool "Using PWM1 PB06/PB07/PB08/PB09" - select RT_USING_PWM - default n - - config BSP_USING_PWM2 - bool "Using PWM2 PA00/PA01" - select RT_USING_PWM - default n - - config BSP_USING_PWM3 - bool "Using PWM3 PC06/PC07" - select RT_USING_PWM - default n - endmenu - - menu "HWtimer Drivers" - config BSP_USING_HWTIMER0 - bool "Using timer0" - select RT_USING_HWTIMER - default n - - config BSP_USING_HWTIMER1 - bool "Using timer1" - select RT_USING_HWTIMER - default n - depends on !BSP_USING_UART2 - - config BSP_USING_HWTIMER2 - bool "Using timer2" - select RT_USING_HWTIMER - default n - depends on !BSP_USING_UART3 - - config BSP_USING_HWTIMER3 - bool "Using timer3" - select RT_USING_HWTIMER - default n - endmenu - - menu "RTC Drivers" - config BSP_USING_RTC - bool "Using RTC" - select RT_USING_RTC - default n - endmenu - - menu "PM Drivers" - config BSP_USING_PM - bool "Using PM" - select RT_USING_PM - default n - endmenu - - menu "ADC Drivers" - config BSP_USING_ADC - bool "Using ADC" - select RT_USING_ADC - default n - endmenu + source "drivers/ES/Kconfig" endmenu @@ -137,11 +15,21 @@ menu "Hardware Drivers Config" config BSP_USING_SPI_FLASH bool "Enable SPI FLASH (W25Q64 spi0)" select BSP_USING_SPI - select BSP_USING_SPI0 select RT_USING_SFUD select RT_SFUD_USING_SFDP default n +if BSP_USING_SPI_FLASH + + config ES_DEVICE_NAME_SPI_DEV + string "The name of spi device (registered)" + default "spi00" + + config ES_DEVICE_NAME_SPI_FALSH_DEV + string "The name of spi flash device" + default "W25Q64" +endif + endmenu menu "Offboard Peripheral Drivers" @@ -163,13 +51,17 @@ menu "Hardware Drivers Config" bool "BSP_USING_EXAMPLE_I2C" default n + config BSP_USING_EXAMPLE_I2C_E2PROM + bool "BSP_USING_EXAMPLE_I2C_E2PROM" + default n + config BSP_USING_EXAMPLE_LED_BLINK bool "BSP_USING_EXAMPLE_LED_BLINK" - default y + default n config BSP_USING_EXAMPLE_PIN_BEEP bool "BSP_USING_EXAMPLE_PIN_BEEP" - default y + default n config BSP_USING_EXAMPLE_PWM_LED bool "BSP_USING_EXAMPLE_PWM_LED" @@ -185,7 +77,7 @@ menu "Hardware Drivers Config" config BSP_USING_EXAMPLE_UART bool "BSP_USING_EXAMPLE_UART" - default y + default n config BSP_USING_EXAMPLE_CAN bool "BSP_USING_EXAMPLE_CAN" diff --git a/bsp/essemi/es32f0654/drivers/SConscript b/bsp/essemi/es32f0654/drivers/SConscript index 280c6f5c90..0e34f50b2f 100644 --- a/bsp/essemi/es32f0654/drivers/SConscript +++ b/bsp/essemi/es32f0654/drivers/SConscript @@ -14,7 +14,10 @@ if GetDepend('RT_USING_PIN'): src += ['drv_gpio.c'] # add serial driver code -if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \ + GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5') or \ + GetDepend('BSP_USING_USART0') or GetDepend('BSP_USING_USART1') or GetDepend('BSP_USING_USART2') or GetDepend('BSP_USING_USART3') or \ + GetDepend('BSP_USING_USART4') or GetDepend('BSP_USING_USART5'): src += ['drv_uart.c'] # add spi driver code @@ -26,40 +29,50 @@ if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): src += ['drv_i2c.c'] # add can driver code -if GetDepend('BSP_USING_CAN'): +if GetDepend('BSP_USING_CAN') or GetDepend('BSP_USING_CAN0') or GetDepend('RT_USING_CAN'): src += ['drv_can.c'] -# add spi flash driver code -if GetDepend('BSP_USING_SPI_FLASH'): - src += ['drv_spiflash.c'] -# add pwm driver code -if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3'): - src += ['drv_pwm.c'] - -# add hwtimer driver code -if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1') or GetDepend('BSP_USING_HWTIMER2') or GetDepend('BSP_USING_HWTIMER3'): - src += ['drv_hwtimer.c'] +# add adc driver code +if GetDepend(['BSP_USING_ADC0']) or GetDepend('BSP_USING_ADC'): + src += ['drv_adc.c'] # add rtc driver code if GetDepend(['BSP_USING_RTC']): src += ['drv_rtc.c'] +# add spi flash driver code +if GetDepend('BSP_USING_SPI_FLASH'): + src += ['drv_spiflash.c'] + +# add hwtimer driver code +if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C2T0_HWTIMER') or GetDepend('BSP_USING_GP16C2T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMERIMER') or \ + GetDepend('BSP_USING_BS16T2_HWTIMER') or GetDepend('BSP_USING_BS16T3_HWTIMER'): + src += ['drv_hwtimer.c'] + +# add pwm driver code +if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C2T0__PWM') or GetDepend('BSP_USING_GP16C2T1_PWM') or \ + GetDepend('BSP_USING_GP32C4T0_PWM') or GetDepend('BSP_USING_GP32C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM'): + src += ['drv_pwm.c'] + # add pm driver code if GetDepend(['BSP_USING_PM']): src += ['drv_pm.c'] - -# add adc driver code -if GetDepend(['BSP_USING_ADC']): - src += ['drv_adc.c'] - CPPPATH = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) objs = objs + group src = [] cwd = GetCurrentDir() -include_path = [cwd] +include_path = [cwd + '/ES'] if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): src += ['bsp_driver_example/adc_vol_sample.c'] @@ -70,6 +83,9 @@ if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): if GetDepend('BSP_USING_EXAMPLE_I2C'): src += ['bsp_driver_example/i2c_sample.c'] +if GetDepend('BSP_USING_EXAMPLE_I2C_E2PROM'): + src += ['bsp_driver_example/i2c_e2_sample.c'] + if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'): src += ['bsp_driver_example/led_blink_sample.c'] diff --git a/bsp/essemi/es32f0654/drivers/board.c b/bsp/essemi/es32f0654/drivers/board.c index 94b259e485..7411168324 100644 --- a/bsp/essemi/es32f0654/drivers/board.c +++ b/bsp/essemi/es32f0654/drivers/board.c @@ -1,12 +1,25 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include @@ -14,7 +27,6 @@ #include "board.h" #include "drv_uart.h" #include "drv_gpio.h" -#include #include /** @@ -43,11 +55,65 @@ void NVIC_Configuration(void) *******************************************************************************/ void SystemClock_Config(void) { - /* hosc 12MHz, from hosc/3 pll to 48MHz */ - ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M); + SYSCFG_UNLOCK(); +#if ES_CMU_LRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#endif /*ES_CMU_LRC_EN*/ + +#if ES_CMU_LOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#endif /*ES_CMU_LOSC_EN*/ + +#if ES_CMU_HRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#endif /*ES_CMU_HRC_EN*/ + +#if ES_CMU_HOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#endif /*ES_CMU_HOSC_EN*/ - /* MCLK 48MHz*/ - ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000); + SYSCFG_LOCK(); + +#if ES_CMU_PLL1_EN + /*PLL的源必须是4M*/ + ald_cmu_pll1_config(ES_PLL1_REFER_CLK, ES_PLL1_OUT_CLK); + + #if ES_CMU_PLL1_SAFE_EN + ald_cmu_pll_safe_config(ENABLE); + #else + ald_cmu_pll_safe_config(DISABLE); + #endif + +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); +#endif /*ES_CMU_PLL1_EN*/ + + ald_cmu_clock_config(ES_SYS_CLK_SOURSE, ES_SYS_CLK); + + ald_cmu_div_config(CMU_SYS,ES_CMU_SYS_DIV); + ald_cmu_div_config(CMU_HCLK_1,ES_CMU_HCLK_1_DIV); + ald_cmu_div_config(CMU_PCLK_1,ES_CMU_PCLK_1_DIV); + ald_cmu_div_config(CMU_PCLK_2,ES_CMU_PCLK_2_DIV); + + ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE); + +/*低功耗时钟使能*/ +#ifdef RT_USING_PM + SYSCFG_UNLOCK(); + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); + SYSCFG_LOCK(); +#endif } /******************************************************************************* @@ -71,13 +137,22 @@ void SysTick_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - + ald_inc_tick(); rt_tick_increase(); /* leave interrupt */ rt_interrupt_leave(); } +/** + * This is the cmu interrupt service. + * + */ +void CMU_Handler(void) +{ + ald_cmu_irq_handler(); +} + /*@}*/ /** * This function will initial ES32F0 board. diff --git a/bsp/essemi/es32f0654/drivers/board.h b/bsp/essemi/es32f0654/drivers/board.h index 5b969142ac..a6fdd9e909 100644 --- a/bsp/essemi/es32f0654/drivers/board.h +++ b/bsp/essemi/es32f0654/drivers/board.h @@ -1,11 +1,24 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2019-01-23 wangyq the first version + * 2019-01-23 wangyq the first version + * 2021-04-20 liuhy the second version */ // <<< Use Configuration Wizard in Context Menu >>> @@ -13,6 +26,7 @@ #define __BOARD_H__ #include +#include "es_conf_info_cmu.h" #define ES32F0_SRAM_SIZE 0x8000 #define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE) diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c index 19eed3f35d..7d67c94070 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c @@ -18,6 +18,9 @@ #include #include + +#ifdef RT_USING_ADC + #define ADC_DEV_NAME "adc0" /* ADC 设备名称 */ #define ADC_DEV_CHANNEL 5 /* PA1 ADC 通道 */ #define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ @@ -55,3 +58,5 @@ static int adc_vol_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c index 4c16d1d555..17f8f2007f 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c @@ -18,7 +18,9 @@ #include #include "rtdevice.h" -#define CAN_DEV_NAME "can" /* CAN 设备名称 */ +#ifdef RT_USING_CAN + +#define CAN_DEV_NAME "can0" /* CAN 设备名称 */ static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */ static rt_device_t can_dev; /* CAN 设备句柄 */ @@ -142,3 +144,5 @@ int can_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(can_sample, can device sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c index e2e39664f3..cc0b790643 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c @@ -17,7 +17,9 @@ #include #include -#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ +#ifdef RT_USING_HWTIMER + +#define HWTIMER_DEV_NAME "timer1" /* 定时器名称 */ /* 定时器超时回调函数 */ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) @@ -83,3 +85,5 @@ static int hwtimer_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_e2_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_e2_sample.c new file mode 100644 index 0000000000..3bfd005e67 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_e2_sample.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 I2C 设备使用例程 + * 例程导出了 i2c_e2_sample 命令到控制终端 + * 命令调用格式：i2c_e2_sample + * 命令解释：使用默认的I2C总线设备i2c0 + * 程序功能：通过 I2C 设备写读e2prom，ST24C04WP。 +*/ + +/*ST24C04WP 有2个Block ：Block0 的从机地址为：0x50,Block1 的从机地址为：0x51 + 一个Block有 256字节，一页16字节,写只可在一页内(超过一页的范围后,会回到页的开始),读无页限制*/ +#include +#include + +#ifdef RT_USING_I2C + +#define I2C_BUS_NAME "i2c0" /*I2C总线设备名称 */ +#define SLAVE_ADDR 0x50 /*从机地址*/ +#define MEM_ADDR 0x00 /*从机的起始储存地址,范围：0x00到0xEF(例程写读范围：2页)*/ +#define ADDR_LEN 1 /*定义从机储存地址的长度，默认8位,1字节*/ +#define STR_LEN 16 /*接收发送的页数据长度 ,最大16*/ + +static rt_uint8_t mem_addr,rx_buffer[33] = { 0U }; /*读两页,需要32字节，字符串结束'\0'*/ +/*第一个字节' '用来放 E2PROM 的内存地址,最后一个字节'\0'作为子串的结束，不存入e2prom*/ +static rt_uint8_t tx_buffer1[STR_LEN + ADDR_LEN + 1] = " e2prom example !\0"; +static rt_uint8_t tx_buffer2[STR_LEN + ADDR_LEN + 1] = " ABCDEFGH12345678\0"; + +static void i2c_e2_sample(int argc, char *argv[]) +{ + struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */ + struct rt_i2c_msg i2c_msg[2]; /* I2C消息 */ + rt_size_t s_stat; + + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */ + + if( i2c_bus == RT_NULL) + { + rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME); + return; + } + + /*写T24C04WP + 如果 (MEM_ADDR & 0x0F) + STR_LEN <= 16, 写的范围为：(MEM_ADDR , MEM_ADDR + STR_LEN ) + (0x10 + MEM_ADDR , 0x10 + MEM_ADDR + STR_LEN ) + 如果 (MEM_ADDR & 0x0F) + STR_LEN > 16, 超出范围的部分会在页内循环写。*/ + tx_buffer1[0] = MEM_ADDR; + + /*初始化消息*/ + i2c_msg[0].addr = SLAVE_ADDR; /* 从机地址 */ + i2c_msg[0].len = ADDR_LEN + STR_LEN ; /* 写入的长度，地址+数据 */ + i2c_msg[0].buf = tx_buffer1; /* 待写入第一段数据 */ + i2c_msg[0].flags = RT_I2C_WR; /* I2C写 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1); /* 写入第一段数据 */ + + if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer1[1]); + else rt_kprintf("device %s write fail \n",I2C_BUS_NAME); + + tx_buffer2[0] = MEM_ADDR + 0x10; /*加一页*/ + i2c_msg[0].buf = tx_buffer2; /* 待写入第二段数据 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1); /* 写入第二段数据 */ + + if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer2[1]); + else rt_kprintf("device %s write fail \n",I2C_BUS_NAME); + + /*读T24C04WP 读2页的数据。读数据需要2条消息：第一条消息：发送读取的地址。 + 第二条消息：读取具体的数据。*/ + + mem_addr = MEM_ADDR & 0xF0; /*从页的开始读*/ + + i2c_msg[0].len = ADDR_LEN; + i2c_msg[0].buf = &mem_addr; + + i2c_msg[1].addr = SLAVE_ADDR; /* 从机地址 */ + i2c_msg[1].len = 32; /* 读取的数据长度：2*16 */ + i2c_msg[1].buf = rx_buffer; /* 数据存放地址 */ + i2c_msg[1].flags = RT_I2C_RD; /* I2C读 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,2); /* 读已写的2页 */ + + if( s_stat == 2 )rt_kprintf(" read successful \n messege : %s \n",rx_buffer); + else + rt_kprintf("read fail \n"); + + return; + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(i2c_e2_sample, i2c e2prom sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c index 2d386433c6..c8a666609d 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -11,14 +23,16 @@ * 程序清单：这是一个 I2C 设备使用例程 * 例程导出了 i2c_io_sample 命令到控制终端 * 命令调用格式：i2c_io_sample - * 命令解释：使用默认的I2C总线设备 + * 命令解释：使用默认的I2C总线设备i2c0 * 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。 */ #include #include -#define I2C_BUS_NAME "i2c1" /* I2C总线设备名称 */ +#ifdef RT_USING_I2C + +#define I2C_BUS_NAME "i2c0" /* I2C总线设备名称 */ #define SLAVE_ADDR 0x2D /* 从机地址 */ #define STR_LEN 16 /* 接收发送的数据长度 */ @@ -95,3 +109,5 @@ static void i2c_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(i2c_io_sample, i2c io sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c index f7287e36ac..78358e421c 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -11,15 +23,18 @@ * 程序清单：这是一个 pm睡眠唤醒的使用例程 * 例程导出了 pm_sample 命令到控制终端 * 命令调用格式：pm_sample - * 命令解释：进入不同的睡眠模式，然后用按键唤醒 + * 命令解释：进入不同的睡眠模式，然后用按键唤醒。 * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。 + * 注意：进入睡眠前，如果有中断挂起（SYSTICK、UART、EXTI等），睡眠将被瞬间唤醒。 */ #include #include + +#ifdef RT_USING_PM #define PM_NAME "pm" /* 设备名称 */ -#define WAKE_UP_PIN 18 /* 唤醒源 */ +#define WAKE_UP_PIN 19 /* 唤醒源 */ #define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ @@ -65,8 +80,9 @@ void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data) break; /*睡眠唤醒后*/ case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/ + /*从深睡眠唤醒后，等待UART时钟未恢复稳定，输出可能丢失*/ rt_kprintf("\n\rEXIT\n\r"); - rt_pm_release(mode); /*释放休眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); /*进无休眠模式*/ return; default: break; @@ -125,6 +141,9 @@ static void pm_test(void *parameter) g_pm_data.flag = 2; } + + /*彻底释放无休眠模式*/ + rt_pm_release_all(PM_SLEEP_MODE_NONE); /*请求选择的休眠模式*/ rt_pm_request(in_mode[i%6]); @@ -137,15 +156,21 @@ static void pm_test(void *parameter) rt_thread_mdelay(500); } - /*释放选择的休眠模式*/ - rt_pm_release(in_mode[i%6]); + /*释放选择的休眠模式 ，彻底释放*/ + rt_pm_release_all(in_mode[i%6]); i++; } - /*清除回调函数和私有数据*/ + + /*切换为无睡眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); + + /*清除回调函数和私有数据*/ rt_pm_notify_set(RT_NULL,RT_NULL); - rt_kprintf("thread pm_test close\n\r"); + + rt_kprintf("thread pm_test close\n\r"); + } /*按键唤醒的回调函数*/ @@ -181,3 +206,5 @@ static int pm_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pm_sample, pm sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c index ce1573aa55..23ecfd227e 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c @@ -17,9 +17,12 @@ #include #include + +#ifdef RT_USING_PWM + #define LED_PIN_NUM 16 /* LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ #define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ -#define PWM_DEV_CHANNEL 4 /* PB9 PWM通道 */ +#define PWM_DEV_CHANNEL 1 /* PA8 PWM通道 */ struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ @@ -70,3 +73,6 @@ static int pwm_led_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pwm_led_sample, pwm sample); + +#endif + diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c index 711a3a0ebb..6f732806f5 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c @@ -17,6 +17,8 @@ #include #include +#ifdef RT_USING_RTC + static int rtc_sample(int argc, char *argv[]) { rt_err_t ret = RT_EOK; @@ -49,3 +51,5 @@ static int rtc_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(rtc_sample, rtc sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c index 994888cdb0..6f6e730288 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -17,13 +29,14 @@ #include #include +#ifdef RT_USING_SPI + #define SPI_DEVICE_NAME "spi00" #define BUF_LEN 16 static void spi_io_sample(int argc, char *argv[]) { struct rt_spi_device * spi_dev; /* spi设备的句柄 */ - struct rt_spi_configuration spi_config; rt_uint8_t i,buffer[BUF_LEN] = { 0U }; rt_err_t s_stat; rt_err_t result; @@ -37,23 +50,8 @@ static void spi_io_sample(int argc, char *argv[]) return; } - - /* 清空配置结构体 */ - rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration)); - - spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ - spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ - spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ - spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ - spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ - spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ - - spi_config.data_width = 8; /* 数据长度：8 */ - - spi_config.max_hz = 2000000; /* 最快时钟频率 */ - /* 配置SPI设备 */ - s_stat = rt_spi_configure(spi_dev,&spi_config); + s_stat = rt_spi_configure(spi_dev,&(spi_dev->config)); if(s_stat != RT_EOK) { @@ -150,3 +148,5 @@ static void spi_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(spi_io_sample, spi sample); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/drv_adc.c b/bsp/essemi/es32f0654/drivers/drv_adc.c index bc26b05802..bb1575c4a0 100644 --- a/bsp/essemi/es32f0654/drivers/drv_adc.c +++ b/bsp/essemi/es32f0654/drivers/drv_adc.c @@ -1,12 +1,25 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-04-03 wangyq the first version * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include @@ -59,77 +72,69 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel) { case 0: es32f0_channel = ADC_CHANNEL_0; - ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH0_GPIO, ES_GPIO_ADC_CH0_PIN, &gpio_initstruct); break; case 1: es32f0_channel = ADC_CHANNEL_1; - ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH1_GPIO, ES_GPIO_ADC_CH1_PIN, &gpio_initstruct); break; case 2: es32f0_channel = ADC_CHANNEL_2; - ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH2_GPIO, ES_GPIO_ADC_CH2_PIN, &gpio_initstruct); break; case 3: es32f0_channel = ADC_CHANNEL_3; - ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH3_GPIO, ES_GPIO_ADC_CH3_PIN, &gpio_initstruct); break; case 4: es32f0_channel = ADC_CHANNEL_4; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH4_GPIO, ES_GPIO_ADC_CH4_PIN, &gpio_initstruct); break; case 5: es32f0_channel = ADC_CHANNEL_5; - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH5_GPIO, ES_GPIO_ADC_CH5_PIN, &gpio_initstruct); break; case 6: es32f0_channel = ADC_CHANNEL_6; - ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH6_GPIO, ES_GPIO_ADC_CH6_PIN, &gpio_initstruct); break; case 7: es32f0_channel = ADC_CHANNEL_7; - ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH7_GPIO, ES_GPIO_ADC_CH7_PIN, &gpio_initstruct); break; case 8: es32f0_channel = ADC_CHANNEL_8; - ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH8_GPIO, ES_GPIO_ADC_CH8_PIN, &gpio_initstruct); break; case 9: es32f0_channel = ADC_CHANNEL_9; - ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH9_GPIO, ES_GPIO_ADC_CH9_PIN, &gpio_initstruct); break; case 10: es32f0_channel = ADC_CHANNEL_10; - ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH10_GPIO, ES_GPIO_ADC_CH10_PIN, &gpio_initstruct); break; case 11: es32f0_channel = ADC_CHANNEL_11; - ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH11_GPIO, ES_GPIO_ADC_CH11_PIN, &gpio_initstruct); break; case 12: es32f0_channel = ADC_CHANNEL_12; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH12_GPIO, ES_GPIO_ADC_CH12_PIN, &gpio_initstruct); break; case 13: es32f0_channel = ADC_CHANNEL_13; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH13_GPIO, ES_GPIO_ADC_CH13_PIN, &gpio_initstruct); break; case 14: es32f0_channel = ADC_CHANNEL_14; - ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH14_GPIO, ES_GPIO_ADC_CH14_PIN, &gpio_initstruct); break; case 15: es32f0_channel = ADC_CHANNEL_15; - ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); - break; - case 16: - es32f0_channel = ADC_CHANNEL_16; - break; - case 17: - es32f0_channel = ADC_CHANNEL_17; - break; - case 18: - es32f0_channel = ADC_CHANNEL_18; + ald_gpio_init(ES_GPIO_ADC_CH15_GPIO, ES_GPIO_ADC_CH15_PIN, &gpio_initstruct); break; + default: break; } @@ -148,6 +153,9 @@ static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t c /* config adc channel */ nm_config.ch = es32f0_adc_get_channel(channel); nm_config.idx = ADC_NCH_IDX_1; + +/*aaabbbccc*/ + nm_config.samp = ES_ADC0_NCH_SAMPLETIME; nm_config.samp = ADC_SAMPLETIME_4; ald_adc_normal_channel_config(_hadc, &nm_config); @@ -168,24 +176,34 @@ static const struct rt_adc_ops es32f0_adc_ops = int rt_hw_adc_init(void) { int result = RT_EOK; + + adc_handle_t _h_adc; + + _h_adc.init.scan = DISABLE; + _h_adc.init.cont = DISABLE; + _h_adc.init.disc = ADC_ALL_DISABLE; + _h_adc.init.disc_nr = ADC_DISC_NR_1; + _h_adc.init.nche_sel = ADC_NCHESEL_MODE_ALL; + _h_adc.init.n_ref = ADC_NEG_REF_VSS; + _h_adc.init.p_ref = ADC_POS_REF_VDD; + _h_adc.init.nch_nr = ADC_NCH_NR_16; + +#ifdef BSP_USING_ADC0 + static adc_handle_t _h_adc0; - - /* adc function initialization */ + + _h_adc0.init = _h_adc.init; + _h_adc0.perh = ADC0; - _h_adc0.init.align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan = DISABLE; - _h_adc0.init.cont = DISABLE; - _h_adc0.init.disc = ADC_ALL_DISABLE; - _h_adc0.init.disc_nr = ADC_DISC_NR_1; - _h_adc0.init.data_bit = ADC_CONV_BIT_12; - _h_adc0.init.div = ADC_CKDIV_128; - _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; - _h_adc0.init.n_ref = ADC_NEG_REF_VSS; - _h_adc0.init.p_ref = ADC_POS_REF_VDD; + _h_adc0.init.align = ES_ADC0_ALIGN; + _h_adc0.init.data_bit = ES_ADC0_DATA_BIT; + _h_adc0.init.div = ES_ADC0_CLK_DIV; ald_adc_init(&_h_adc0); - - rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0); - + + result = rt_hw_adc_register(&_device_adc0, ES_DEVICE_NAME_ADC0, &es32f0_adc_ops, &_h_adc0); + +#endif /*BSP_USING_ADC0*/ + return result; } INIT_BOARD_EXPORT(rt_hw_adc_init); diff --git a/bsp/essemi/es32f0654/drivers/drv_adc.h b/bsp/essemi/es32f0654/drivers/drv_adc.h index eaddd67407..fa51cdbb21 100644 --- a/bsp/essemi/es32f0654/drivers/drv_adc.h +++ b/bsp/essemi/es32f0654/drivers/drv_adc.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-04-03 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_ADC_H__ #define DRV_ADC_H__ +#include "es_conf_info_adc.h" + int rt_hw_adc_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_can.c b/bsp/essemi/es32f0654/drivers/drv_can.c index cefddd997c..7c73acd0cf 100644 --- a/bsp/essemi/es32f0654/drivers/drv_can.c +++ b/bsp/essemi/es32f0654/drivers/drv_can.c @@ -1,51 +1,94 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2019-11-09 wangyq the first version + * 2019-11-09 wangyq the first version + * 2021-04-20 liuhy the second version */ #include "drv_can.h" -#ifdef BSP_USING_CAN +#ifdef RT_USING_CAN + static struct es32f0_can can; -/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc) 48 / ((1 + 3 + 2) * 8) = 1MHz */ -static const struct es32f0_baud_rate_tab can_baud_rate_tab[] = -{ - {CAN1MBaud, 8}, - {CAN800kBaud, 10}, - {CAN500kBaud, 16}, - {CAN250kBaud, 32}, - {CAN125kBaud, 64}, - {CAN100kBaud, 80}, - {CAN50kBaud, 160}, - {CAN20kBaud, 400}, - {CAN10kBaud, 800} -}; -static rt_uint32_t get_can_baud_index(rt_uint32_t baud) -{ - rt_uint32_t len, index; - - len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); - for (index = 0; index < len; index++) +static rt_uint32_t get_can_baud_index(rt_uint32_t baud,can_init_t * init) +{ +/* attention !!! baud calculation example: Pclk / ((1 + seg1 + seg2) * psc) Pclk=48 / ((1 + seg1=3 + seg2=2) * 8) = 1MHz */ + double target,temp,min; + uint32_t i,j,j_max,near = 0; + target = (double)(ald_cmu_get_pclk1_clock()); + target/= baud; /*1*/ + + min = 0xFFFFFFFF; + + for(i = 1 + 16 + 8 ;i > 2;i--) /*SYNC_SEG + SEG1 + SEG2*/ { - if (can_baud_rate_tab[index].baud_rate == baud) - return index; + j_max = target/i/(0.98) + 1; /*СΧ*/ + j_max = (j_max > 1024) ? (1024) : (j_max); + + for(j = target/i/1.02 ;j < j_max;j++) + { + temp = target/i/j; /*2*/ + temp = (temp > 1) ? (temp - 1) : (1 - temp); + temp+= ((1.0 * i * j) / 0xFFFFFFFF) ; + + if(temp < min) + { + if(temp > 0.000001) + { + near = (i<<16) + j; + min = temp; + } + else + { + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + } + } } - return 0; /* default baud is CAN1MBaud */ + if(min < 0.01) + { + i = near>>16; + j = near % (1<<16); + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + else + { + return 1; + } } + static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg) { struct es32f0_can *drv_can; - rt_uint32_t baud_index; RT_ASSERT(can_device); RT_ASSERT(cfg); @@ -56,7 +99,7 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.ttcm = DISABLE; drv_can->CanHandle.init.abom = ENABLE; drv_can->CanHandle.init.awk = DISABLE; - drv_can->CanHandle.init.artx = DISABLE; + drv_can->CanHandle.init.artx = (type_func_t)ES_CAN0_AUTO_BAN_RE_T; drv_can->CanHandle.init.rfom = DISABLE; drv_can->CanHandle.init.txmp = ENABLE; @@ -75,12 +118,20 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK; break; } + /*ò*/ + if(get_can_baud_index(cfg->baud_rate,&(drv_can->CanHandle.init))) + { + return -RT_ERROR; + } + drv_can->CanHandle.init.sjw = (can_sjw_t)(cfg->reserved); + + /* init can */ - baud_index = get_can_baud_index(cfg->baud_rate); - drv_can->CanHandle.init.sjw = CAN_SJW_1; - drv_can->CanHandle.init.seg1 = CAN_SEG1_3; - drv_can->CanHandle.init.seg2 = CAN_SEG2_2; - drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; + // baud_index = get_can_baud_index(cfg->baud_rate); + //drv_can->CanHandle.init.sjw = CAN_SJW_1; + // drv_can->CanHandle.init.seg1 = CAN_SEG1_3; + // drv_can->CanHandle.init.seg2 = CAN_SEG2_2; + // drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; /* init can */ if (ald_can_init(&drv_can->CanHandle) != OK) { @@ -96,7 +147,10 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar { rt_uint32_t argval; struct es32f0_can *drv_can; + +#ifdef RT_CAN_USING_HDR struct rt_can_filter_config *filter_cfg; +#endif RT_ASSERT(can_device != RT_NULL); drv_can = (struct es32f0_can *)can_device->parent.user_data; @@ -108,8 +162,12 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar argval = (rt_uint32_t) arg; if (argval == RT_DEVICE_FLAG_INT_RX) { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | - CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, DISABLE); } else if (argval == RT_DEVICE_FLAG_INT_TX) { @@ -117,8 +175,11 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar } else if (argval == RT_DEVICE_CAN_INT_ERR) { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, DISABLE); } break; case RT_DEVICE_CTRL_SET_INT: @@ -127,8 +188,14 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar { NVIC_SetPriority(CAN0_IRQn, 1); NVIC_EnableIRQ(CAN0_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FP1), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, ENABLE); + } else if (argval == RT_DEVICE_FLAG_INT_TX) { @@ -141,11 +208,16 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar { NVIC_SetPriority(CAN0_IRQn, 1); NVIC_EnableIRQ(CAN0_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, ENABLE); + } break; +#ifdef RT_CAN_USING_HDR case RT_CAN_CMD_SET_FILTER: if (RT_NULL == arg) { @@ -157,8 +229,55 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar filter_cfg = (struct rt_can_filter_config *)arg; /* get default filter */ for (int i = 0; i < filter_cfg->count; i++) - { - drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + { + + /*ĬϹ˱ж*/ + if(filter_cfg->items[i].hdr < drv_can->device.config.maxhdr) + drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + else + drv_can->FilterConfig.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; + + if(filter_cfg->items[i].mode) + { + /*ʶбģʽ ƥ idƥΪյid = õid + = õmask ͨ*/ + /*չ֡*/ + if(filter_cfg->items[i].ide) + { +// filter_cfg->items[i].id = filter_cfg->items[i].id ; /*id 29 λ*/ + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 3) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + else /*׼֡*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id << 18); + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 21) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + } + else + { + /*ʶģʽ*/ + /*չ֡*/ + if(filter_cfg->items[i].ide) + { + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<3; + } + else /*׼֡*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id)<<18; + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<21; + } + +#if ES_C_CAN_FILTER_FRAME_TYPE + /*ƥ*/ + filter_cfg->items[i].mask |= 0x6; +#endif + + } + drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF; drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) | (filter_cfg->items[i].ide << 2) | @@ -171,6 +290,8 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar } } break; + +#endif case RT_CAN_CMD_SET_MODE: argval = (rt_uint32_t) arg; if (argval != RT_CAN_MODE_NORMAL && @@ -188,18 +309,7 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar break; case RT_CAN_CMD_SET_BAUD: argval = (rt_uint32_t) arg; - if (argval != CAN1MBaud && - argval != CAN800kBaud && - argval != CAN500kBaud && - argval != CAN250kBaud && - argval != CAN125kBaud && - argval != CAN100kBaud && - argval != CAN50kBaud && - argval != CAN20kBaud && - argval != CAN10kBaud) - { - return -RT_ERROR; - } + if (argval != drv_can->device.config.baud_rate) { drv_can->device.config.baud_rate = argval; @@ -423,8 +533,11 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO0) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK); @@ -441,8 +554,11 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO1) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK); @@ -549,20 +665,12 @@ void CAN0_Handler(void) can.device.status.errcode = errtype & 0x07; h_can->perh->IFC |= CAN_IFC_ERRIFC_MSK; } - rt_interrupt_leave(); } int rt_hw_can_init(void) { gpio_init_t h_gpio; - struct can_configure config = CANDEFAULTCONFIG; - - config.privmode = RT_CAN_MODE_NOPRIV; - config.ticks = 50; -#ifdef RT_CAN_USING_HDR - config.maxhdr = 14; -#endif /* Initialize can common pin */ h_gpio.odos = GPIO_PUSH_PULL; @@ -570,15 +678,22 @@ int rt_hw_can_init(void) h_gpio.odrv = GPIO_OUT_DRIVE_NORMAL; h_gpio.flt = GPIO_FILTER_DISABLE; h_gpio.type = GPIO_TYPE_TTL; - h_gpio.func = GPIO_FUNC_4; +#if defined(ES_CAN0_RX_GPIO_FUNC)&&defined(ES_CAN0_RX_GPIO_PORT)&&defined(ES_CAN0_RX_GPIO_PIN) /* Initialize can rx pin */ - h_gpio.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOA, GPIO_PIN_11, &h_gpio); - + h_gpio.mode = GPIO_MODE_INPUT; + h_gpio.func = ES_CAN0_RX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_RX_GPIO_PORT, ES_CAN0_RX_GPIO_PIN, &h_gpio); +#endif + + +#if defined(ES_CAN0_TX_GPIO_FUNC)&&defined(ES_CAN0_TX_GPIO_PORT)&&defined(ES_CAN0_TX_GPIO_PIN) /* Initialize can tx pin */ - h_gpio.mode = GPIO_MODE_OUTPUT; - ald_gpio_init(GPIOA, GPIO_PIN_12, &h_gpio); + h_gpio.mode = GPIO_MODE_OUTPUT; + h_gpio.func = ES_CAN0_TX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_TX_GPIO_PORT, ES_CAN0_TX_GPIO_PIN, &h_gpio); +#endif + /* config default filter */ can_filter_t filter = {0}; @@ -587,15 +702,21 @@ int rt_hw_can_init(void) filter.mask_id_high = 0x0000; filter.mask_id_low = 0x0000; filter.fifo = CAN_FILTER_FIFO0; - filter.number = 0; + filter.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; filter.mode = CAN_FILTER_MODE_MASK; filter.scale = CAN_FILTER_SCALE_32; filter.active = ENABLE; can.FilterConfig = filter; - can.device.config = config; + can.device.config = (struct can_configure)ES_CAN0_CONFIG; +#ifdef RT_CAN_USING_HDR + can.device.config.maxhdr = 14; +#endif + can.device.config.privmode = RT_CAN_MODE_NOPRIV; + can.device.config.ticks = 50; + can.device.config.reserved = ES_CAN0_SJW; /* register CAN1 device */ - rt_hw_can_register(&can.device, "can", &_can_ops, &can); + rt_hw_can_register(&can.device, ES_DEVICE_NAME_CAN0, &_can_ops, &can); return 0; } diff --git a/bsp/essemi/es32f0654/drivers/drv_can.h b/bsp/essemi/es32f0654/drivers/drv_can.h index 798a3a8653..c89f2bb2ae 100644 --- a/bsp/essemi/es32f0654/drivers/drv_can.h +++ b/bsp/essemi/es32f0654/drivers/drv_can.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-11-09 wangyq the first version + * 2019-11-09 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_CAN_H__ @@ -14,16 +27,9 @@ #include #include #include +#include "es_conf_info_can.h" -#include -#include - -struct es32f0_baud_rate_tab -{ - rt_uint32_t baud_rate; - rt_uint32_t config_data; -}; - +#ifdef RT_USING_CAN /* es32f0 can device */ struct es32f0_can { @@ -34,4 +40,5 @@ struct es32f0_can int rt_hw_can_init(void); +#endif #endif /*DRV_CAN_H__ */ diff --git a/bsp/essemi/es32f0654/drivers/drv_gpio.c b/bsp/essemi/es32f0654/drivers/drv_gpio.c index 142fcce7fc..00050866e5 100644 --- a/bsp/essemi/es32f0654/drivers/drv_gpio.c +++ b/bsp/essemi/es32f0654/drivers/drv_gpio.c @@ -1,103 +1,34 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ -#include -#include #include "board.h" #include "drv_gpio.h" -#include -#include + +/*管脚映射在 es_conf_info_map.h 的 pins[] 中*/ #ifdef RT_USING_PIN -#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} -#define __ES32F0_PIN_DEFAULT {-1, 0, 0} - -/* ES32F0 GPIO driver */ -struct pin_index -{ - int index; - GPIO_TypeDef *gpio; - uint32_t pin; -}; - -static const struct pin_index pins[] = -{ - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(2, C, 13), - __ES32F0_PIN(3, C, 14), - __ES32F0_PIN(4, C, 15), - __ES32F0_PIN(5, H, 0), - __ES32F0_PIN(6, H, 1), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(8, C, 0), - __ES32F0_PIN(9, C, 1), - __ES32F0_PIN(10, C, 2), - __ES32F0_PIN(11, C, 3), - __ES32F0_PIN(12, H, 3), - __ES32F0_PIN(13, H, 4), - __ES32F0_PIN(14, A, 0), - __ES32F0_PIN(15, A, 1), - __ES32F0_PIN(16, A, 2), - __ES32F0_PIN(17, A, 3), - __ES32F0_PIN(18, F, 0), - __ES32F0_PIN(19, F, 1), - __ES32F0_PIN(20, A, 4), - __ES32F0_PIN(21, A, 5), - __ES32F0_PIN(22, A, 6), - __ES32F0_PIN(23, A, 7), - __ES32F0_PIN(24, C, 4), - __ES32F0_PIN(25, C, 5), - __ES32F0_PIN(26, B, 0), - __ES32F0_PIN(27, B, 1), - __ES32F0_PIN(28, B, 2), - __ES32F0_PIN(29, B, 10), - __ES32F0_PIN(30, B, 11), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(33, B, 12), - __ES32F0_PIN(34, B, 13), - __ES32F0_PIN(35, B, 14), - __ES32F0_PIN(36, B, 15), - __ES32F0_PIN(37, C, 6), - __ES32F0_PIN(38, C, 7), - __ES32F0_PIN(39, C, 8), - __ES32F0_PIN(40, C, 9), - __ES32F0_PIN(41, A, 8), - __ES32F0_PIN(42, A, 9), - __ES32F0_PIN(43, A, 10), - __ES32F0_PIN(44, A, 11), - __ES32F0_PIN(45, A, 12), - __ES32F0_PIN(46, A, 13), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(49, A, 14), - __ES32F0_PIN(50, A, 15), - __ES32F0_PIN(51, C, 10), - __ES32F0_PIN(52, C, 11), - __ES32F0_PIN(53, C, 12), - __ES32F0_PIN(54, D, 2), - __ES32F0_PIN(55, B, 3), - __ES32F0_PIN(56, B, 4), - __ES32F0_PIN(57, B, 5), - __ES32F0_PIN(58, B, 6), - __ES32F0_PIN(59, B, 7), - __ES32F0_PIN(60, H, 2), - __ES32F0_PIN(61, B, 8), - __ES32F0_PIN(62, B, 9), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, -}; - struct pin_irq_map { rt_uint16_t pinbit; @@ -143,6 +74,150 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { -1, 0, RT_NULL, RT_NULL}, }; +#ifdef ES_CONF_EXTI_IRQ_0 + +RT_WEAK void irq_pin0_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 0\r\n"); +} +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 + +RT_WEAK void irq_pin1_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 1\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 + + RT_WEAK void irq_pin2_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 2\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 + +RT_WEAK void irq_pin3_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 3\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 + +RT_WEAK void irq_pin4_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 4\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 + +RT_WEAK void irq_pin5_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 5\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 + +RT_WEAK void irq_pin6_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 6\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 + +RT_WEAK void irq_pin7_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 7\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 + +RT_WEAK void irq_pin8_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 8\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 + +RT_WEAK void irq_pin9_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 9\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 + +RT_WEAK void irq_pin10_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 10\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 + +RT_WEAK void irq_pin11_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 11\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 + +RT_WEAK void irq_pin12_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 12\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 + +RT_WEAK void irq_pin13_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 13\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 + +RT_WEAK void irq_pin14_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 14\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 + +RT_WEAK void irq_pin15_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 15\r\n"); +} + +#endif + + #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) const struct pin_index *get_pin(uint8_t pin) { @@ -408,18 +483,9 @@ const static struct rt_pin_ops _es32f0_pin_ops = es32f0_pin_attach_irq, es32f0_pin_detach_irq, es32f0_pin_irq_enable, - RT_NULL, + /*RT_NULL,*/ }; -int rt_hw_pin_init(void) -{ - int result; - ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); - result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) { uint16_t irqno; @@ -488,4 +554,44 @@ void EXTI12_15_Handler(void) rt_interrupt_leave(); } +int rt_hw_pin_init(void) +{ + int result; + + +#ifdef ES_INIT_GPIOS + + rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t); + +#endif + + ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); + + result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f0_pin_ops, RT_NULL); + + if(result != RT_EOK)return result; + +#ifdef ES_INIT_GPIOS + + for(i = 0;i < gpio_conf_num;i++) + { + rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode); + + if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD)) + rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level); + + if(!gpio_conf_all[i].irq_en)continue; + + rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL); + rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en); + } + +#endif + + + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_gpio.h b/bsp/essemi/es32f0654/drivers/drv_gpio.h index 3032af51ba..b0b68714d3 100644 --- a/bsp/essemi/es32f0654/drivers/drv_gpio.h +++ b/bsp/essemi/es32f0654/drivers/drv_gpio.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_GPIO_H__ #define DRV_GPIO_H__ +#include "es_conf_info_gpio.h" + int rt_hw_pin_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_hwtimer.c b/bsp/essemi/es32f0654/drivers/drv_hwtimer.c index 4d7614a323..83d3d9c87a 100644 --- a/bsp/essemi/es32f0654/drivers/drv_hwtimer.c +++ b/bsp/essemi/es32f0654/drivers/drv_hwtimer.c @@ -1,21 +1,33 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-3-19 wangyq the first version * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include + #ifdef RT_USING_HWTIMER @@ -26,93 +38,172 @@ struct es32f0_hwtimer_dev IRQn_Type IRQn; }; -#ifdef BSP_USING_HWTIMER0 -static struct es32f0_hwtimer_dev hwtimer0; +#ifdef BSP_USING_AD16C4T0_HWTIMER +static struct es32f0_hwtimer_dev ad16c4t0_hwtimer; + +static struct rt_hwtimer_info ad16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T0_HWTIMER_MODE +}; + +void AD16C4T0_BRK_UP_TRIG_COM_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_GP16C4T0_HWTIMER + +static struct es32f0_hwtimer_dev gp16c4t0_hwtimer; + +static struct rt_hwtimer_info gp16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T0_HWTIMER_MODE +}; + +void GP16C4T0_LCD_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_GP16C2T0_HWTIMER + +static struct es32f0_hwtimer_dev gp16c2t0_hwtimer; + +static struct rt_hwtimer_info gp16c2t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C2T0_HWTIMER_MODE +}; + +void GP16C2T0_Handler(void) +{ + ald_timer_clear_flag_status(gp16c2t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c2t0_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_GP16C2T1_HWTIMER + +static struct es32f0_hwtimer_dev gp16c2t1_hwtimer; + +static struct rt_hwtimer_info gp16c2t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C2T1_HWTIMER_MODE +}; + +void GP16C2T1_Handler(void) +{ + ald_timer_clear_flag_status(gp16c2t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c2t1_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_BS16T0_HWTIMER + +static struct es32f0_hwtimer_dev bs16t0_hwtimer; + +static struct rt_hwtimer_info bs16t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T0_HWTIMER_MODE +}; void BS16T0_Handler(void) { - ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer0.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) - { - ald_timer_base_stop(hwtimer0.hwtimer_periph); - } + ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t0_hwtimer.parent); } + #endif -#ifdef BSP_USING_HWTIMER1 -static struct es32f0_hwtimer_dev hwtimer1; -/* can not use when UART2 Handler is enabled */ +#ifdef BSP_USING_BS16T1_HWTIMER + +static struct es32f0_hwtimer_dev bs16t1_hwtimer; + +static struct rt_hwtimer_info bs16t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T1_HWTIMER_MODE +}; + void BS16T1_UART2_Handler(void) { - /* if BS16T1 it */ - if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer1.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) - { - ald_timer_base_stop(hwtimer1.hwtimer_periph); - } - } + ald_timer_clear_flag_status(bs16t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t1_hwtimer.parent); } + #endif -#ifdef BSP_USING_HWTIMER2 -static struct es32f0_hwtimer_dev hwtimer2; -/* can not use when UART3 Handler is enabled */ +#ifdef BSP_USING_BS16T2_HWTIMER + +static struct es32f0_hwtimer_dev bs16t2_hwtimer; + +static struct rt_hwtimer_info bs16t2_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T2_HWTIMER_MODE +}; + void BS16T2_UART3_Handler(void) { - /* if BS16T2 it */ - if (ald_timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer2.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode) - { - ald_timer_base_stop(hwtimer2.hwtimer_periph); - } - } + ald_timer_clear_flag_status(bs16t2_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t2_hwtimer.parent); } + #endif -#ifdef BSP_USING_HWTIMER3 -static struct es32f0_hwtimer_dev hwtimer3; -/* can not use when DAC0 Handler is enabled */ +#ifdef BSP_USING_BS16T3_HWTIMER + +static struct es32f0_hwtimer_dev bs16t3_hwtimer; + +static struct rt_hwtimer_info bs16t3_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T3_HWTIMER_MODE +}; + void BS16T3_DAC0_Handler(void) { - /* if BS16T3 it */ - if (ald_timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer3.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode) - { - ald_timer_base_stop(hwtimer3.hwtimer_periph); - } - } + ald_timer_clear_flag_status(bs16t3_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t3_hwtimer.parent); } -#endif -static struct rt_hwtimer_info es32f0_hwtimer_info = -{ - 48000000, /* maximum count frequency */ - 1, /* minimum count frequency */ - 65535, /* counter maximum value */ - HWTIMER_CNTMODE_UP -}; +#endif static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) { struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info; + + RT_ASSERT(hwtimer != RT_NULL); if (1 == state) @@ -121,9 +212,10 @@ static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); NVIC_EnableIRQ(hwtimer->IRQn); } - hwtimer->parent.freq = ald_cmu_get_pclk1_clock(); - es32f0_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock(); - es32f0_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock(); + + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + hwtimer_info->maxfreq = hwtimer->parent.freq; + hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF; } static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, @@ -175,10 +267,37 @@ static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, { case HWTIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; - if (freq != ald_cmu_get_pclk1_clock()) - { - ret = -RT_ERROR; + + ret = -RT_ERROR; + + if(freq) + { + double temp,target; + temp = (double)ald_cmu_get_pclk1_clock(); + target = temp/freq; + + if(target < 0x10001) /*Ƶ = max(PRES)+1*/ + { + temp = target - (int)(target); + + if((temp > 0.998)&&(target < 0x10000)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target; + ret = RT_EOK; + } + if((temp < 0.002)&&(target >= 0x1)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1; + ret = RT_EOK; + } + + } + + if(ret == RT_EOK) /*Ϣ*/ + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + } + break; case HWTIMER_CTRL_STOP: @@ -206,46 +325,127 @@ int rt_hw_hwtimer_init(void) { rt_err_t ret = RT_EOK; -#ifdef BSP_USING_HWTIMER0 - static timer_handle_t _hwtimer_periph0; - _hwtimer_periph0.perh = BS16T0; - hwtimer0.IRQn = BS16T0_IRQn; - hwtimer0.hwtimer_periph = &_hwtimer_periph0; - hwtimer0.parent.info = &es32f0_hwtimer_info; - hwtimer0.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); +#ifdef BSP_USING_AD16C4T0_HWTIMER + static timer_handle_t ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer_periph.perh = AD16C4T0; + ad16c4t0_hwtimer.IRQn = AD16C4T0_BRK_UP_TRIG_COM_IRQn; + + ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1; + ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer.parent.info = &ad16c4t0_info; + ad16c4t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer); #endif -#ifdef BSP_USING_HWTIMER1 - static timer_handle_t _hwtimer_periph1; - _hwtimer_periph1.perh = BS16T1; - hwtimer1.IRQn = BS16T1_UART2_IRQn; - hwtimer1.hwtimer_periph = &_hwtimer_periph1; - hwtimer1.parent.info = &es32f0_hwtimer_info; - hwtimer1.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); +#ifdef BSP_USING_GP16C4T0_HWTIMER + static timer_handle_t gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer_periph.perh = GP16C4T0; + gp16c4t0_hwtimer.IRQn = GP16C4T0_LCD_IRQn; + + gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1; + gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer.parent.info = &gp16c4t0_info; + gp16c4t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer); #endif -#ifdef BSP_USING_HWTIMER2 - static timer_handle_t _hwtimer_periph2; - _hwtimer_periph2.perh = BS16T2; - hwtimer2.IRQn = BS16T2_UART3_IRQn; - hwtimer2.hwtimer_periph = &_hwtimer_periph2; - hwtimer2.parent.info = &es32f0_hwtimer_info; - hwtimer2.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer2.parent, "timer2", &hwtimer2); +#ifdef BSP_USING_GP16C2T0_HWTIMER + static timer_handle_t gp16c2t0_hwtimer_periph; + + gp16c2t0_hwtimer_periph.perh = GP16C2T0; + gp16c2t0_hwtimer.IRQn = GP16C2T0_IRQn; + + gp16c2t0_hwtimer_periph.init.prescaler = ES_GP16C2T0_HWTIMER_PRES - 1; + gp16c2t0_hwtimer_periph.init.mode = ( ES_GP16C2T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c2t0_hwtimer.hwtimer_periph = &gp16c2t0_hwtimer_periph; + + gp16c2t0_hwtimer.parent.info = &gp16c2t0_info; + gp16c2t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c2t0_hwtimer.parent, ES_DEVICE_NAME_GP16C2T0_HWTIMER, &gp16c2t0_hwtimer); #endif -#ifdef BSP_USING_HWTIMER3 - static timer_handle_t _hwtimer_periph3; - _hwtimer_periph3.perh = BS16T3; - hwtimer3.IRQn = BS16T3_DAC0_IRQn; - hwtimer3.hwtimer_periph = &_hwtimer_periph3; - hwtimer3.parent.info = &es32f0_hwtimer_info; - hwtimer3.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer3.parent, "timer3", &hwtimer3); +#ifdef BSP_USING_GP16C2T1_HWTIMER + static timer_handle_t gp16c2t1_hwtimer_periph; + + gp16c2t1_hwtimer_periph.perh = GP16C2T1; + gp16c2t1_hwtimer.IRQn = GP16C2T1_IRQn; + + gp16c2t1_hwtimer_periph.init.prescaler = ES_GP16C2T1_HWTIMER_PRES - 1; + gp16c2t1_hwtimer_periph.init.mode = ( ES_GP16C2T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c2t1_hwtimer.hwtimer_periph = &gp16c2t1_hwtimer_periph; + + gp16c2t1_hwtimer.parent.info = &gp16c2t1_info; + gp16c2t1_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c2t1_hwtimer.parent, ES_DEVICE_NAME_GP16C2T1_HWTIMER, &gp16c2t1_hwtimer); #endif +#ifdef BSP_USING_BS16T0_HWTIMER + static timer_handle_t bs16t0_hwtimer_periph; + + bs16t0_hwtimer_periph.perh = BS16T0; + bs16t0_hwtimer.IRQn = BS16T0_IRQn; + + bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1; + bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph; + + bs16t0_hwtimer.parent.info = &bs16t0_info; + bs16t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer); +#endif + +#ifdef BSP_USING_BS16T1_HWTIMER + static timer_handle_t bs16t1_hwtimer_periph; + + bs16t1_hwtimer_periph.perh = BS16T1; + bs16t1_hwtimer.IRQn = BS16T1_UART2_IRQn; + + bs16t1_hwtimer_periph.init.prescaler = ES_BS16T1_HWTIMER_PRES - 1; + bs16t1_hwtimer_periph.init.mode = ( ES_BS16T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t1_hwtimer.hwtimer_periph = &bs16t1_hwtimer_periph; + + bs16t1_hwtimer.parent.info = &bs16t1_info; + bs16t1_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t1_hwtimer.parent, ES_DEVICE_NAME_BS16T1_HWTIMER, &bs16t1_hwtimer); +#endif + +#ifdef BSP_USING_BS16T2_HWTIMER + static timer_handle_t bs16t2_hwtimer_periph; + + bs16t2_hwtimer_periph.perh = BS16T2; + bs16t2_hwtimer.IRQn = BS16T2_UART3_IRQn; + + bs16t2_hwtimer_periph.init.prescaler = ES_BS16T2_HWTIMER_PRES - 1; + bs16t2_hwtimer_periph.init.mode = ( ES_BS16T2_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t2_hwtimer.hwtimer_periph = &bs16t2_hwtimer_periph; + + bs16t2_hwtimer.parent.info = &bs16t2_info; + bs16t2_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t2_hwtimer.parent, ES_DEVICE_NAME_BS16T2_HWTIMER, &bs16t2_hwtimer); +#endif + +#ifdef BSP_USING_BS16T3_HWTIMER + static timer_handle_t bs16t3_hwtimer_periph; + + bs16t3_hwtimer_periph.perh = BS16T3; + bs16t3_hwtimer.IRQn = BS16T3_DAC0_IRQn; + + bs16t3_hwtimer_periph.init.prescaler = ES_BS16T3_HWTIMER_PRES - 1; + bs16t3_hwtimer_periph.init.mode = ( ES_BS16T3_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t3_hwtimer.hwtimer_periph = &bs16t3_hwtimer_periph; + + bs16t3_hwtimer.parent.info = &bs16t3_info; + bs16t3_hwtimer.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t3_hwtimer.parent, ES_DEVICE_NAME_BS16T3_HWTIMER, &bs16t3_hwtimer); +#endif + + return ret; } INIT_BOARD_EXPORT(rt_hw_hwtimer_init); diff --git a/bsp/essemi/es32f0654/drivers/drv_hwtimer.h b/bsp/essemi/es32f0654/drivers/drv_hwtimer.h index e18d580fbd..46e307a5c3 100644 --- a/bsp/essemi/es32f0654/drivers/drv_hwtimer.h +++ b/bsp/essemi/es32f0654/drivers/drv_hwtimer.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-3-19 wangyq the first version + * 2019-3-19 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_HWTIMER_H__ #define DRV_HWTIMER_H__ +#include "es_conf_info_hwtimer.h" int rt_hw_hwtimer_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_i2c.c b/bsp/essemi/es32f0654/drivers/drv_i2c.c index 399e1427ef..1109b7f641 100644 --- a/bsp/essemi/es32f0654/drivers/drv_i2c.c +++ b/bsp/essemi/es32f0654/drivers/drv_i2c.c @@ -1,8 +1,19 @@ /* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-24 wangyq the first version @@ -10,19 +21,24 @@ * 2020-12-15 liuhy update libraries */ +#include #include #include -#include #include "board.h" #include "drv_i2c.h" -#include -#include + #ifdef RT_USING_I2C #define TIMEOUT 0x0FFF /* I2C struct definition */ -static i2c_handle_t _h_i2c0, _h_i2c1; +#ifdef BSP_USING_I2C0 + static i2c_handle_t _h_i2c0; +#endif + +#ifdef BSP_USING_I2C1 + static i2c_handle_t _h_i2c1; +#endif static void _i2c_init(void) { @@ -38,35 +54,55 @@ static void _i2c_init(void) gpio_instruct.func = GPIO_FUNC_5; #ifdef BSP_USING_I2C0 + +#if defined(ES_I2C0_SCL_GPIO_FUNC)&&defined(ES_I2C0_SCL_GPIO_PORT)&&defined(ES_I2C0_SCL_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SCL_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SCL_GPIO_PORT, ES_I2C0_SCL_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C0_SDA_GPIO_FUNC)&&defined(ES_I2C0_SDA_GPIO_PORT)&&defined(ES_I2C0_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SDA_GPIO_PORT, ES_I2C0_SDA_GPIO_PIN, &gpio_instruct); +#endif + /* Initialize I2C Function */ _h_i2c0.perh = I2C0; - _h_i2c0.init.clk_speed = 100000; _h_i2c0.init.duty = I2C_DUTYCYCLE_2; - _h_i2c0.init.own_addr1 = 0x0A; - _h_i2c0.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE; + _h_i2c0.init.clk_speed = ES_I2C0_CLK_SPEED; + _h_i2c0.init.own_addr1 = ES_I2C0_OWN_ADDR1; + _h_i2c0.init.addr_mode = ES_I2C0_ADDR_MODE; + _h_i2c0.init.general_call = ES_I2C0_GENERAL_CALL; + _h_i2c0.init.no_stretch = ES_I2C0_STRETCH; ald_i2c_reset(&_h_i2c0); ald_i2c_init(&_h_i2c0); - /* I2C0_SCL->PB8, I2C0_SDA->PB9 */ - ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct); + #endif #ifdef BSP_USING_I2C1 + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + /* Initialize i2c function */ _h_i2c1.perh = I2C1; - _h_i2c1.init.clk_speed = 100000; - _h_i2c1.init.duty = I2C_DUTYCYCLE_2; - _h_i2c1.init.own_addr1 = 0xA0; - _h_i2c1.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE; - + _h_i2c1.init.duty = I2C_DUTYCYCLE_2; + _h_i2c1.init.clk_speed = ES_I2C1_CLK_SPEED; + _h_i2c1.init.own_addr1 = ES_I2C1_OWN_ADDR1; + _h_i2c1.init.addr_mode = ES_I2C1_ADDR_MODE; + _h_i2c1.init.general_call = ES_I2C1_GENERAL_CALL; + _h_i2c1.init.no_stretch = ES_I2C1_STRETCH; + ald_i2c_reset(&_h_i2c1); ald_i2c_init(&_h_i2c1); - /* I2C1_SCL->PB10, I2C1_SDA->PB11 */ - ald_gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct); + #endif } @@ -116,6 +152,8 @@ const struct rt_i2c_bus_device_ops es32f0_i2c_ops = int rt_hw_i2c_init(void) { + int result = RT_EOK; + _i2c_init(); #ifdef BSP_USING_I2C0 @@ -124,16 +162,25 @@ int rt_hw_i2c_init(void) rt_memset((void *)&_i2c_device0, 0, sizeof(struct rt_i2c_bus_device)); _i2c_device0.ops = &es32f0_i2c_ops; _i2c_device0.priv = &_h_i2c0; - rt_i2c_bus_device_register(&_i2c_device0, "i2c0"); + result = rt_i2c_bus_device_register(&_i2c_device0, ES_DEVICE_NAME_I2C0); + if (result != RT_EOK) + { + return result; + } #endif #ifdef BSP_USING_I2C1 /* define i2c Instance */ static struct rt_i2c_bus_device _i2c_device1; rt_memset((void *)&_i2c_device1, 0, sizeof(struct rt_i2c_bus_device)); + _i2c_device1.ops = &es32f0_i2c_ops; _i2c_device1.priv = &_h_i2c1; - rt_i2c_bus_device_register(&_i2c_device1, "i2c1"); + rt_i2c_bus_device_register(&_i2c_device1, ES_DEVICE_NAME_I2C1); + if (result != RT_EOK) + { + return result; + } #endif return RT_EOK; diff --git a/bsp/essemi/es32f0654/drivers/drv_i2c.h b/bsp/essemi/es32f0654/drivers/drv_i2c.h index 84c32561c8..b5cc316ee7 100644 --- a/bsp/essemi/es32f0654/drivers/drv_i2c.h +++ b/bsp/essemi/es32f0654/drivers/drv_i2c.h @@ -1,16 +1,31 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2019-01-24 wangyq the first version + * 2019-01-24 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_I2C_H__ #define DRV_I2C_H__ +#include "es_conf_info_i2c.h" + int rt_hw_i2c_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_pm.c b/bsp/essemi/es32f0654/drivers/drv_pm.c index 669514c7b8..c1b4c41237 100644 --- a/bsp/essemi/es32f0654/drivers/drv_pm.c +++ b/bsp/essemi/es32f0654/drivers/drv_pm.c @@ -3,20 +3,30 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-04-08 wangyq the first version * 2019-11-01 wangyq adapt to the new power management interface + * 2020-12-15 liuhy the first version */ -#include -#include -#include -#include -#include +#include "drv_pm.h" #ifdef RT_USING_PM + static void uart_console_reconfig(void) { struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; @@ -24,26 +34,14 @@ static void uart_console_reconfig(void) rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); } -static void delay(void) -{ - long i; - rt_base_t level; - - level = rt_hw_interrupt_disable(); - i = 0; - do{ - i++; - } - while (i < 10000); - - rt_hw_interrupt_enable(level); -} - /** - * This function will put ES32F033x into sleep mode. + * This function will put ES32F065x into sleep mode. * * @param pm pointer to power manage structure */ + + +/* 注意：进入睡眠前，如果有中断挂起（SYSTICK、PENDSV、UART、EXTI等），睡眠将被瞬间唤醒。*/ static void sleep(struct rt_pm *pm, uint8_t mode) { switch (mode) @@ -52,31 +50,26 @@ static void sleep(struct rt_pm *pm, uint8_t mode) break; case PM_SLEEP_MODE_IDLE: - //__WFI(); break; case PM_SLEEP_MODE_LIGHT: /* Enter SLEEP Mode, Main regulator is ON */ ald_pmu_stop1_enter(); - delay(); break; - case PM_SLEEP_MODE_DEEP: - /* Enter STOP 2 mode */ + case PM_SLEEP_MODE_DEEP: + /* Enter STOP 2 mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_STANDBY: - /* Enter STANDBY mode */ + /* Enter STANDBY mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_SHUTDOWN: - /* Enter SHUTDOWNN mode */ + /* Enter SHUTDOWNN mode */ ald_pmu_stop2_enter(); - delay(); break; default: diff --git a/bsp/essemi/es32f0654/drivers/drv_pm.h b/bsp/essemi/es32f0654/drivers/drv_pm.h index a4f6cc84ee..e43ba09c26 100644 --- a/bsp/essemi/es32f0654/drivers/drv_pm.h +++ b/bsp/essemi/es32f0654/drivers/drv_pm.h @@ -3,7 +3,20 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: + * Date Author Notes * 2019-04-01 wangyq the first version */ @@ -11,6 +24,12 @@ #ifndef DRV_PM_H__ #define DRV_PM_H__ +#include +#include +#include +#include "es_conf_info_pm.h" +#include + int rt_hw_pm_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_pwm.c b/bsp/essemi/es32f0654/drivers/drv_pwm.c index d324e2bbbb..59e8494241 100644 --- a/bsp/essemi/es32f0654/drivers/drv_pwm.c +++ b/bsp/essemi/es32f0654/drivers/drv_pwm.c @@ -3,28 +3,33 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-11 wangyq the first version * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include "es_conf_info_pwm.h" -static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) -{ - uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / - (timer_initstruct->init.prescaler + 1); - WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); - timer_initstruct->init.period = (uint32_t)_arr; -} +#ifdef RT_USING_PWM static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns) { @@ -44,7 +49,8 @@ static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, u static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { rt_err_t ret = RT_EOK; - uint32_t _ccep; + uint64_t _arr,bus_speed,tmp; + uint32_t _maxcnt,_ccep_ch_en = 0U; timer_channel_t pwm_channel; timer_oc_init_t tim_ocinit; timer_handle_t *timer_initstruct = (timer_handle_t *)device->parent.user_data; @@ -52,39 +58,30 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void * RT_ASSERT(timer_initstruct != RT_NULL); - tim_ocinit.oc_mode = TIMER_OC_MODE_PWM1; - tim_ocinit.oc_polarity = TIMER_OC_POLARITY_HIGH; - tim_ocinit.oc_fast_en = DISABLE; - tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; - tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; - tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; - /* select pwm output channel */ if (1 == cfg->channel) { pwm_channel = TIMER_CHANNEL_1; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC1EN_MSK; } - else if (2 == cfg->channel) + else if (2 == cfg->channel) { pwm_channel = TIMER_CHANNEL_2; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC2EN_MSK; } - else if (3 == cfg->channel) + else if (3 == cfg->channel) { - if (timer_initstruct->perh == GP16C2T0 || timer_initstruct->perh == GP16C2T1) - return RT_EINVAL; pwm_channel = TIMER_CHANNEL_3; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC3EN_MSK; } - else if (4 == cfg->channel) + else if (4 == cfg->channel) { - if (timer_initstruct->perh == GP16C2T0 || timer_initstruct->perh == GP16C2T1) - return RT_EINVAL; pwm_channel = TIMER_CHANNEL_4; + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK; } else - { return RT_EINVAL; - } - + switch (cmd) { case PWM_CMD_ENABLE: @@ -96,19 +93,44 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void * break; case PWM_CMD_SET: - _ccep = timer_initstruct->perh->CCEP; - /* count registers max 0xFFFF, auto adjust prescaler */ + + /*当通道没开的时候：关通道，设置输出模式和极性，初始化通道*/ + if(!_ccep_ch_en) + { + tim_ocinit.oc_mode = ES_PWM_OC_MODE; + tim_ocinit.oc_polarity = ES_PWM_OC_POLARITY; + tim_ocinit.oc_fast_en = DISABLE; + tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; + tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; + ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + } + + bus_speed = (uint64_t)ald_cmu_get_pclk1_clock(); + + /*外设的计数器最大值*/ + _maxcnt = 0xFFFF; + + /*当最大分频 <= _maxcnt时：估计大概的分频，加快速度 */ + tmp = bus_speed * (cfg->period)/1000000000/_maxcnt; + timer_initstruct->init.prescaler = (tmp > 2U) ? (tmp - 2U) : 0U ; /*bus_speed < 500000000*/ + + /* count registers max , auto adjust prescaler */ do { - pwm_set_freq(timer_initstruct, cfg->period); - timer_initstruct->init.prescaler ++; + _arr = bus_speed * (cfg->period) / 1000000000 /(++timer_initstruct->init.prescaler); + } - while (timer_initstruct->init.period > 0xFFFF); + while (_arr > _maxcnt); + + WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); + timer_initstruct->init.period = (uint32_t)_arr; + /* update prescaler */ WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler); - ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse); - timer_initstruct->perh->CCEP = _ccep; + break; case PWM_CMD_GET: @@ -139,74 +161,124 @@ int rt_hw_pwm_init(void) gpio_initstructure.flt = GPIO_FILTER_DISABLE; gpio_initstructure.type = GPIO_TYPE_TTL; -#ifdef BSP_USING_PWM0 /* 4 channels */ - static struct rt_device_pwm pwm_dev0; - static timer_handle_t timer_initstruct0; +#ifdef BSP_USING_AD16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t0_pwm_dev; + static timer_handle_t ad16c4t0_timer_initstruct; - timer_initstruct0.perh = AD16C4T0; - ald_timer_pwm_init(&timer_initstruct0); + ad16c4t0_timer_initstruct.perh = AD16C4T0; + ald_timer_pwm_init(&ad16c4t0_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure); - ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f0_pwm_ops, - &timer_initstruct0); +#if defined(ES_AD16C4T0_CH1_GPIO_FUNC)&&defined(ES_AD16C4T0_CH1_GPIO_PORT)&&defined(ES_AD16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH1_GPIO_PORT, ES_AD16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH2_GPIO_FUNC)&&defined(ES_AD16C4T0_CH2_GPIO_PORT)&&defined(ES_AD16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH2_GPIO_PORT, ES_AD16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH3_GPIO_FUNC)&&defined(ES_AD16C4T0_CH3_GPIO_PORT)&&defined(ES_AD16C4T0_CH3_GPIO_FUNC) + gpio_initstructure.func = ES_AD16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH3_GPIO_PORT, ES_AD16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH4_GPIO_FUNC)&&defined(ES_AD16C4T0_CH4_GPIO_PORT)&&defined(ES_AD16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH4_GPIO_PORT, ES_AD16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T0_PWM, &es32f0_pwm_ops, + &ad16c4t0_timer_initstruct); #endif -#ifdef BSP_USING_PWM1 /* 4 channels */ - static struct rt_device_pwm pwm_dev1; - static timer_handle_t timer_initstruct1; +#ifdef BSP_USING_GP16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t0_pwm_dev; + static timer_handle_t gp16c4t0_timer_initstruct; - timer_initstruct1.perh = GP16C4T0; - ald_timer_pwm_init(&timer_initstruct1); + gp16c4t0_timer_initstruct.perh = GP16C4T0; + ald_timer_pwm_init(&gp16c4t0_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); + +#if defined(ES_GP16C4T0_CH1_GPIO_FUNC)&&defined(ES_GP16C4T0_CH1_GPIO_PORT)&&defined(ES_GP16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH1_GPIO_PORT, ES_GP16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH2_GPIO_FUNC)&&defined(ES_GP16C4T0_CH2_GPIO_PORT)&&defined(ES_GP16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH2_GPIO_PORT, ES_GP16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif - ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f0_pwm_ops, - &timer_initstruct1); +#if defined(ES_GP16C4T0_CH3_GPIO_FUNC)&&defined(ES_GP16C4T0_CH3_GPIO_PORT)&&defined(ES_GP16C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH3_GPIO_PORT, ES_GP16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH4_GPIO_FUNC)&&defined(ES_GP16C4T0_CH4_GPIO_PORT)&&defined(ES_GP16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH4_GPIO_PORT, ES_GP16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t0_pwm_dev, ES_DEVICE_NAME_GP16C4T0_PWM, &es32f0_pwm_ops, + &gp16c4t0_timer_initstruct); #endif -#ifdef BSP_USING_PWM2 /* 2 channels */ - static struct rt_device_pwm pwm_dev2; - static timer_handle_t timer_initstruct2; - timer_initstruct2.perh = GP16C2T0; - ald_timer_pwm_init(&timer_initstruct2); +#ifdef BSP_USING_GP16C2T0_PWM /* 2 channels */ + static struct rt_device_pwm gp16c2t0_pwm_dev; + static timer_handle_t gp16c2t0_timer_initstruct; + + gp16c2t0_timer_initstruct.perh = GP16C2T0; + ald_timer_pwm_init(&gp16c2t0_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); + +#if defined(ES_GP16C2T0_CH1_GPIO_FUNC)&&defined(ES_GP16C2T0_CH1_GPIO_PORT)&&defined(ES_GP16C2T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C2T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C2T0_CH1_GPIO_PORT, ES_GP16C2T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C2T0_CH2_GPIO_FUNC)&&defined(ES_GP16C2T0_CH2_GPIO_PORT)&&defined(ES_GP16C2T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C2T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C2T0_CH2_GPIO_PORT, ES_GP16C2T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif - ret = rt_device_pwm_register(&pwm_dev2, "pwm2", &es32f0_pwm_ops, - &timer_initstruct2); + ret = rt_device_pwm_register(&gp16c2t0_pwm_dev, ES_DEVICE_NAME_GP16C2T0_PWM, &es32f0_pwm_ops, + &gp16c2t0_timer_initstruct); #endif -#ifdef BSP_USING_PWM3 /* 2 channels */ - static struct rt_device_pwm pwm_dev3; - static timer_handle_t timer_initstruct3; - timer_initstruct3.perh = GP16C2T1; - ald_timer_pwm_init(&timer_initstruct3); +#ifdef BSP_USING_GP16C2T1_PWM /* 2 channels */ + static struct rt_device_pwm gp16c2t1_pwm_dev; + static timer_handle_t gp16c2t1_timer_initstruct; + + gp16c2t1_timer_initstruct.perh = GP16C2T1; + ald_timer_pwm_init(&gp16c2t1_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure); - ald_gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure); + +#if defined(ES_GP16C2T1_CH1_GPIO_FUNC)&&defined(ES_GP16C2T1_CH1_GPIO_PORT)&&defined(ES_GP16C2T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C2T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C2T1_CH1_GPIO_PORT, ES_GP16C2T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C2T1_CH2_GPIO_FUNC)&&defined(ES_GP16C2T1_CH2_GPIO_PORT)&&defined(ES_GP16C2T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C2T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C2T1_CH2_GPIO_PORT, ES_GP16C2T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif - ret = rt_device_pwm_register(&pwm_dev3, "pwm3", &es32f0_pwm_ops, - &timer_initstruct3); + ret = rt_device_pwm_register(&gp16c2t1_pwm_dev, ES_DEVICE_NAME_GP16C2T1_PWM, &es32f0_pwm_ops, + &gp16c2t1_timer_initstruct); #endif + + return ret; } INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif diff --git a/bsp/essemi/es32f0654/drivers/drv_pwm.h b/bsp/essemi/es32f0654/drivers/drv_pwm.h index f4fcfe7cff..3383e7ba1c 100644 --- a/bsp/essemi/es32f0654/drivers/drv_pwm.h +++ b/bsp/essemi/es32f0654/drivers/drv_pwm.h @@ -3,6 +3,18 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-11 wangyq the first version diff --git a/bsp/essemi/es32f0654/drivers/drv_rtc.c b/bsp/essemi/es32f0654/drivers/drv_rtc.c index cab5b8b61b..ee7589090b 100644 --- a/bsp/essemi/es32f0654/drivers/drv_rtc.c +++ b/bsp/essemi/es32f0654/drivers/drv_rtc.c @@ -3,26 +3,38 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-22 wangyq the first version * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include -#include +#include #include #include #include "board.h" -#include "drv_rtc.h" -#include -#include +#include "drv_rtc.h" #ifdef RT_USING_RTC static void __rtc_init(rtc_init_t *init) { + assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); assert_param(IS_RTC_OUTPUT_SEL(init->output)); assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); @@ -117,10 +129,16 @@ int rt_hw_rtc_init(void) rt_err_t ret = RT_EOK; static struct rt_device rtc_dev; rtc_init_t rtc_initstruct; + + /* enable clk */ + ald_rtc_source_select(ES_RTC_CLK_SOURCE); - /* enable external 32.768kHz */ - CMU_LOSC_ENABLE(); - ald_cmu_losc_safe_config(ENABLE); + if(ES_RTC_CLK_SOURCE == ES_C_RTC_SOURCE_LOSC) + { + CMU_LOSC_ENABLE(); + ald_cmu_losc_safe_config(ENABLE); + } + /* set default time */ RTC_UNLOCK(); WRITE_REG(RTC->TIME, 0x134251); @@ -131,6 +149,8 @@ int rt_hw_rtc_init(void) rtc_initstruct.asynch_pre_div = 0; rtc_initstruct.synch_pre_div = 32767; rtc_initstruct.output = RTC_OUTPUT_DISABLE; + rtc_initstruct.output_polarity = RTC_OUTPUT_POLARITY_HIGH; + __rtc_init(&rtc_initstruct); rtc_dev.type = RT_Device_Class_RTC; @@ -150,7 +170,7 @@ int rt_hw_rtc_init(void) rtc_dev.user_data = RTC; - ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); + ret = rt_device_register(&rtc_dev, ES_DEVICE_NAME_RTC, RT_DEVICE_FLAG_RDWR); return ret; } diff --git a/bsp/essemi/es32f0654/drivers/drv_rtc.h b/bsp/essemi/es32f0654/drivers/drv_rtc.h index fe0264fb51..76e5b24d85 100644 --- a/bsp/essemi/es32f0654/drivers/drv_rtc.h +++ b/bsp/essemi/es32f0654/drivers/drv_rtc.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-03-22 wangyq the first version + * 2019-03-22 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_RTC_H__ #define DRV_RTC_H__ +#include "es_conf_info_rtc.h" int rt_hw_rtc_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_spi.c b/bsp/essemi/es32f0654/drivers/drv_spi.c index dd37691125..6ea5c1a705 100644 --- a/bsp/essemi/es32f0654/drivers/drv_spi.c +++ b/bsp/essemi/es32f0654/drivers/drv_spi.c @@ -3,11 +3,23 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-24 wangyq the first version * 2019-11-01 wangyq update libraries - * 2020-12-15 liuhy update libraries + * 2021-04-20 liuhy the second version */ #include @@ -16,9 +28,7 @@ #include #include "board.h" #include "drv_spi.h" -#include -#include -#include + #ifdef RT_USING_SPI @@ -30,6 +40,9 @@ rt_err_t spi_configure(struct rt_spi_device *device, spi_handle_t *hspi; hspi = (spi_handle_t *)device->bus->parent.user_data; + hspi->init.ss_en = DISABLE; + hspi->init.crc_calc = DISABLE; + /* config spi mode */ if (cfg->mode & RT_SPI_SLAVE) { @@ -64,6 +77,16 @@ rt_err_t spi_configure(struct rt_spi_device *device, { hspi->init.phase = SPI_CPHA_FIRST; } + + if (cfg->mode & RT_SPI_MSB) + { + hspi->init.first_bit = SPI_FIRSTBIT_MSB; + } + else + { + hspi->init.first_bit = SPI_FIRSTBIT_LSB; + } + if (cfg->mode & RT_SPI_CPOL) { hspi->init.polarity = SPI_CPOL_HIGH; @@ -72,6 +95,7 @@ rt_err_t spi_configure(struct rt_spi_device *device, { hspi->init.polarity = SPI_CPOL_LOW; } + if (cfg->mode & RT_SPI_NO_CS) { hspi->init.ss_en = DISABLE; @@ -150,74 +174,54 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * hspi = (spi_handle_t *)device->bus->parent.user_data; cs = device->parent.user_data; + + if (message->cs_take) + { + rt_pin_write(cs->pin, ES_SPI_CS_LEVEL); + } if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) { /* send & receive */ if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } else { /* only send data */ if (message->recv_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } /* only receive data */ if (message->send_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } } - + + if (message->cs_release) + { + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); + } + + if (res != RT_EOK) + return RT_ERROR; + else + return message->length; + } else { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } - + if (message->cs_release) { - rt_pin_write(cs->pin, 1); + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); } return RT_EOK; } - return message->length; } @@ -230,6 +234,7 @@ const struct rt_spi_ops es32f0_spi_ops = rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) { + int result; /* define spi Instance */ struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); @@ -238,7 +243,17 @@ rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const c cs_pin->pin = pin; rt_pin_mode(pin, PIN_MODE_OUTPUT); rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + +#ifdef BSP_USING_SPI0 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI0_BUS)))SPI_BUS_CONFIG(spi_device->config,0); +#endif +#ifdef BSP_USING_SPI1 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI1_BUS)))SPI_BUS_CONFIG(spi_device->config,1); +#endif + + return result; } #ifdef BSP_USING_SPI0 @@ -259,77 +274,84 @@ int rt_hw_spi_init(void) spi_handle_t *spi; gpio_init_t gpio_instruct; + gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.type = GPIO_TYPE_CMOS; + gpio_instruct.flt = GPIO_FILTER_DISABLE; + gpio_instruct.odrv = GPIO_OUT_DRIVE_NORMAL; #ifdef BSP_USING_SPI0 _spi0.perh = SPI0; spi_bus = &_spi_bus0; spi = &_spi0; - rt_device_t spi_bus_dev0; /* SPI0 gpio init */ - gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.flt = GPIO_FILTER_DISABLE; + gpio_instruct.mode = GPIO_MODE_OUTPUT; - /* PB3->SPI0_SCK, PB5->SPI0_MOSI */ - ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); +#if defined(ES_SPI0_SCK_GPIO_FUNC)&&defined(ES_SPI0_SCK_GPIO_PORT)&&defined(ES_SPI0_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI0_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI0_SCK_GPIO_PORT, ES_SPI0_SCK_GPIO_PIN, &gpio_instruct); +#endif - /* PB4->SPI0_MISO */ - gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); +#if defined(ES_SPI0_MOSI_GPIO_FUNC)&&defined(ES_SPI0_MOSI_GPIO_PORT)&&defined(ES_SPI0_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MOSI_GPIO_PORT, ES_SPI0_MOSI_GPIO_PIN, &gpio_instruct); +#endif + + gpio_instruct.mode = GPIO_MODE_INPUT; + +#if defined(ES_SPI0_MISO_GPIO_FUNC)&&defined(ES_SPI0_MISO_GPIO_PORT)&&defined(ES_SPI0_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MISO_GPIO_PORT, ES_SPI0_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi0", &es32f0_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f0_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR); - - /* SPI0_NSS = PA15 = PIN 50 */ - result = es32f0_spi_device_attach(50, "spi0", "spi00"); + result = es32f0_spi_device_attach(ES_SPI0_NSS_PIN, ES_DEVICE_NAME_SPI0_BUS, ES_DEVICE_NAME_SPI0_DEV0); if (result != RT_EOK) { return result; } - + #endif #ifdef BSP_USING_SPI1 _spi1.perh = SPI1; spi_bus = &_spi_bus1; spi = &_spi1; - rt_device_t spi_bus_dev0; /* SPI1 gpio init */ - gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PB13->SPI1_SCK, PB15->SPI1_MOSI */ - ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct); - - /* PB14->SPI1_MISO */ - gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct); + gpio_instruct.mode = GPIO_MODE_OUTPUT; + +#if defined(ES_SPI1_SCK_GPIO_FUNC)&&defined(ES_SPI1_SCK_GPIO_PORT)&&defined(ES_SPI1_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI1_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI1_SCK_GPIO_PORT, ES_SPI1_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI1_MOSI_GPIO_FUNC)&&defined(ES_SPI1_MOSI_GPIO_PORT)&&defined(ES_SPI1_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MOSI_GPIO_PORT, ES_SPI1_MOSI_GPIO_PIN, &gpio_instruct); +#endif + + gpio_instruct.mode = GPIO_MODE_INPUT; + +#if defined(ES_SPI1_MISO_GPIO_FUNC)&&defined(ES_SPI1_MISO_GPIO_PORT)&&defined(ES_SPI1_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MISO_GPIO_PORT, ES_SPI1_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi1", &es32f0_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f0_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR); - - /* SPI1_NSS = PC00 = PIN 8 */ - result = es32f0_spi_device_attach(8, "spi1", "spi10"); - + result = es32f0_spi_device_attach((ES_SPI1_NSS_PIN, ES_DEVICE_NAME_SPI1_BUS, ES_DEVICE_NAME_SPI1_DEV0); if (result != RT_EOK) { return result; diff --git a/bsp/essemi/es32f0654/drivers/drv_spi.h b/bsp/essemi/es32f0654/drivers/drv_spi.h index 991ff35c7a..df7932d570 100644 --- a/bsp/essemi/es32f0654/drivers/drv_spi.h +++ b/bsp/essemi/es32f0654/drivers/drv_spi.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-01-24 wangyq the first version + * 2019-01-24 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_SPI_H__ @@ -14,6 +27,8 @@ #include #include #include + +#include "es_conf_info_spi.h" struct es32f0_hw_spi_cs { diff --git a/bsp/essemi/es32f0654/drivers/drv_spiflash.c b/bsp/essemi/es32f0654/drivers/drv_spiflash.c index c84fe1be78..d8176257d1 100644 --- a/bsp/essemi/es32f0654/drivers/drv_spiflash.c +++ b/bsp/essemi/es32f0654/drivers/drv_spiflash.c @@ -9,18 +9,20 @@ * 2019-11-01 wangyq update libraries */ +#include "board.h" #include + +#if defined(BSP_USING_SPI_FLASH) + #include "spi_flash.h" #include "drv_spiflash.h" #include "spi_flash_sfud.h" #include "drv_spi.h" -#if defined(BSP_USING_SPI_FLASH) int rt_hw_spi_flash_init(void) { - es32f0_spi_device_attach(50, "spi0", "spi00"); - - if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi00")) + + if (RT_NULL == rt_sfud_flash_probe(ES_DEVICE_NAME_SPI_FALSH_DEV, ES_DEVICE_NAME_SPI_DEV)) { return -RT_ERROR; }; diff --git a/bsp/essemi/es32f0654/drivers/drv_uart.c b/bsp/essemi/es32f0654/drivers/drv_uart.c index 4ebd18f826..45f42eed78 100644 --- a/bsp/essemi/es32f0654/drivers/drv_uart.c +++ b/bsp/essemi/es32f0654/drivers/drv_uart.c @@ -3,19 +3,30 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include "board.h" -#include "drv_uart.h" -#include -#include +#include "es_conf_info_uart.h" #ifdef RT_USING_SERIAL @@ -24,151 +35,13 @@ struct es32_uart { uart_handle_t huart; IRQn_Type irq; -}; +}; -static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +/* es32 usart driver */ +struct es32_usart { - gpio_init_t gpio_initstructure; - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - /* Initialize tx pin */ - gpio_initstructure.mode = GPIO_MODE_OUTPUT; - gpio_initstructure.odos = GPIO_PUSH_PULL; - gpio_initstructure.pupd = GPIO_PUSH_UP; - gpio_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL; - gpio_initstructure.flt = GPIO_FILTER_DISABLE; - gpio_initstructure.type = GPIO_TYPE_TTL; - -#ifdef BSP_USING_UART0 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); -#endif /* uart0 gpio init */ - -#ifdef BSP_USING_UART1 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); -#endif /* uart1 gpio init */ - -#ifdef BSP_USING_UART2 - gpio_initstructure.func = GPIO_FUNC_5; - ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); -#endif /* uart2 gpio init */ - -#ifdef BSP_USING_UART3 - gpio_initstructure.func = GPIO_FUNC_4; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); -#endif /* uart3 gpio init */ - - uart->huart.init.mode = UART_MODE_UART; - uart->huart.init.baud = cfg->baud_rate; - uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5); - uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); - uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; - ald_uart_init(&uart->huart); - - if (cfg->bit_order == BIT_ORDER_MSB) - { - UART_MSB_FIRST_ENABLE(&uart->huart); - } - else - { - UART_MSB_FIRST_DISABLE(&uart->huart); - } - - if (cfg->invert == NRZ_INVERTED) - { - UART_DATA_INV_ENABLE(&uart->huart); - } - else - { - UART_DATA_INV_DISABLE(&uart->huart); - } - - /* enable rx int */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); - - return RT_EOK; -} - -static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct es32_uart *)serial->parent.user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); - /* disable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); - break; - - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); - break; - } - - return RT_EOK; -} - -static int es32f0x_putc(struct rt_serial_device *serial, char c) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - while (!(uart->huart.perh->SR & 0x40)) ; - WRITE_REG(uart->huart.perh->TBR, c); - - return 1; -} - -static int es32f0x_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct es32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - if (uart->huart.perh->SR & 0x01) - { - ch = (uint8_t)(uart->huart.perh->RBR & 0xFF); - } - - return ch; -} - -static const struct rt_uart_ops es32f0x_uart_ops = -{ - es32f0x_configure, - es32f0x_control, - es32f0x_putc, - es32f0x_getc, + usart_handle_t huart; + IRQn_Type irq; }; #ifdef BSP_USING_UART0 @@ -266,19 +139,380 @@ void BS16T2_UART3_Handler(void) rt_interrupt_leave(); } #endif /* BSP_USING_UART3 */ + +#ifdef BSP_USING_USART0 +/* USART0 device driver structure */ +struct es32_usart usart0 = +{ + {USART0}, + USART0_IRQn +}; + +struct rt_serial_device serial4; + +void USART0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (USART0->STAT & USART_FLAG_RXNE) + { + rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_USART0 */ + +#ifdef BSP_USING_USART1 +/* USART1 device driver structure */ +struct es32_usart usart1 = +{ + {USART1}, + USART1_IRQn +}; + +struct rt_serial_device serial5; + +void USART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (USART1->STAT & USART_FLAG_RXNE) + { + rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_USART1 */ + +static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + gpio_init_t gpio_initstructure; + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Initialize tx pin */ + gpio_initstructure.mode = GPIO_MODE_OUTPUT; + gpio_initstructure.odos = GPIO_PUSH_PULL; + gpio_initstructure.pupd = GPIO_PUSH_UP; + gpio_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL; + gpio_initstructure.flt = GPIO_FILTER_DISABLE; + gpio_initstructure.type = GPIO_TYPE_TTL; + + if((uint32_t)(uart->huart.perh) > (uint32_t)UART3) /*根据外设物理地址区分UART和USART*/ + { + /*USART*/ + struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data; + +#ifdef BSP_USING_USART0 + if(usart == (&usart0)) + { +#if defined(ES_USART0_TX_GPIO_FUNC)&&defined(ES_USART0_TX_GPIO_PORT)&&defined(ES_USART0_TX_GPIO_PIN) + gpio_initstructure.func = ES_USART0_TX_GPIO_FUNC; + ald_gpio_init(ES_USART0_TX_GPIO_PORT, ES_USART0_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_USART0_RX_GPIO_FUNC)&&defined(ES_USART0_RX_GPIO_PORT)&&defined(ES_USART0_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_USART0_RX_GPIO_FUNC; + ald_gpio_init(ES_USART0_RX_GPIO_PORT, ES_USART0_RX_GPIO_PIN, &gpio_initstructure); +#endif + ald_cmu_perh_clock_config(CMU_PERH_USART0, ENABLE); + } + +#endif /* usart0 gpio init */ + +#ifdef BSP_USING_USART1 + if(usart == (&usart1)) + { +#if defined(ES_USART1_TX_GPIO_FUNC)&&defined(ES_USART1_TX_GPIO_PORT)&&defined(ES_USART1_TX_GPIO_PIN) + gpio_initstructure.func = ES_USART1_TX_GPIO_FUNC; + ald_gpio_init(ES_USART1_TX_GPIO_PORT, ES_USART1_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_USART1_RX_GPIO_FUNC)&&defined(ES_USART1_RX_GPIO_PORT)&&defined(ES_USART1_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_USART1_RX_GPIO_FUNC; + ald_gpio_init(ES_USART1_RX_GPIO_PORT, ES_USART1_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_USART1, ENABLE); + } +#endif /* usart1 gpio init */ + + usart->huart.init.mode = USART_MODE_TX_RX; + usart->huart.init.baud = cfg->baud_rate; + usart->huart.init.word_length = (usart_word_length_t)(cfg->data_bits - 8); + usart->huart.init.stop_bits = ((cfg->stop_bits == STOP_BITS_1) ? USART_STOP_BITS_1 : USART_STOP_BITS_2); + usart->huart.init.parity = (usart_parity_t)(cfg->parity == PARITY_NONE ? cfg->parity : (4 - cfg->parity) ); + usart->huart.init.fctl = USART_HW_FLOW_CTL_NONE; + + ald_usart_init(&usart->huart); + + /* + BIT_ORDER_LSB BIT_ORDER_MSB + NRZ_NORMAL NRZ_INVERTED + 无相关寄存器*/ + + /* enable rx int */ + ald_usart_interrupt_config(&usart->huart, USART_IT_RXNE, ENABLE); + + } + else + { + /*UART*/ + +#ifdef BSP_USING_UART0 + if(uart == (&uart0)) + { +#if defined(ES_UART0_TX_GPIO_FUNC)&&defined(ES_UART0_TX_GPIO_PORT)&&defined(ES_UART0_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART0_TX_GPIO_FUNC; + ald_gpio_init(ES_UART0_TX_GPIO_PORT, ES_UART0_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART0_RX_GPIO_FUNC)&&defined(ES_UART0_RX_GPIO_PORT)&&defined(ES_UART0_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART0_RX_GPIO_FUNC; + ald_gpio_init(ES_UART0_RX_GPIO_PORT, ES_UART0_RX_GPIO_PIN, &gpio_initstructure); +#endif + ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE); + } + +#endif /* uart0 gpio init */ + +#ifdef BSP_USING_UART1 + if(uart == (&uart1)) + { +#if defined(ES_UART1_TX_GPIO_FUNC)&&defined(ES_UART1_TX_GPIO_PORT)&&defined(ES_UART1_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART1_TX_GPIO_FUNC; + ald_gpio_init(ES_UART1_TX_GPIO_PORT, ES_UART1_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART1_RX_GPIO_FUNC)&&defined(ES_UART1_RX_GPIO_PORT)&&defined(ES_UART1_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART1_RX_GPIO_FUNC; + ald_gpio_init(ES_UART1_RX_GPIO_PORT, ES_UART1_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE); + } +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_UART2 + if(uart == (&uart2)) + { +#if defined(ES_UART2_TX_GPIO_FUNC)&&defined(ES_UART2_TX_GPIO_PORT)&&defined(ES_UART2_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART2_TX_GPIO_FUNC; + ald_gpio_init(ES_UART2_TX_GPIO_PORT, ES_UART2_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART2_RX_GPIO_FUNC)&&defined(ES_UART2_RX_GPIO_PORT)&&defined(ES_UART2_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART2_RX_GPIO_FUNC; + ald_gpio_init(ES_UART2_RX_GPIO_PORT, ES_UART2_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE); + } +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_UART3 + if(uart == (&uart3)) + { +#if defined(ES_UART3_TX_GPIO_FUNC)&&defined(ES_UART3_TX_GPIO_PORT)&&defined(ES_UART3_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART3_TX_GPIO_FUNC; + ald_gpio_init(ES_UART3_TX_GPIO_PORT, ES_UART3_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART3_RX_GPIO_FUNC)&&defined(ES_UART3_RX_GPIO_PORT)&&defined(ES_UART3_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART3_RX_GPIO_FUNC; + ald_gpio_init(ES_UART3_RX_GPIO_PORT, ES_UART3_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE); + } +#endif /* uart3 gpio init */ + + uart->huart.init.mode = UART_MODE_UART; + uart->huart.init.baud = cfg->baud_rate; + uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5); + uart->huart.init.stop_bits = (uart_stop_bits_t)cfg->stop_bits; + uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); + uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; + + ald_uart_init(&uart->huart); + + if (cfg->bit_order == BIT_ORDER_MSB) + { + UART_MSB_FIRST_ENABLE(&uart->huart); + } + else + { + UART_MSB_FIRST_DISABLE(&uart->huart); + } + + if (cfg->invert == NRZ_INVERTED) + { + UART_DATA_INV_ENABLE(&uart->huart); + } + else + { + UART_DATA_INV_DISABLE(&uart->huart); + } + + /* enable rx int */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + + } + + + return RT_EOK; +} + +static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + + if((uint32_t)(uart->huart.perh) > (uint32_t)UART3) /*根据外设物理地址区分UART和USART*/ + { + /*USART*/ + struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(usart->irq); + /* disable interrupt */ + ald_usart_interrupt_config(&usart->huart, USART_IT_RXNE, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(usart->irq); + /* enable interrupt */ + ald_usart_interrupt_config(&usart->huart, USART_IT_RXNE, ENABLE); + break; + } + + } + else + { + /*UART*/ + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + break; + } + } + + + return RT_EOK; +} + +static int es32f0x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if((uint32_t)(uart->huart.perh) > (uint32_t)UART3) /*根据外设物理地址区分UART和USART*/ + { + /*USART*/ + struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data; + while (!(usart->huart.perh->STAT & USART_STAT_TXEMPIF_MSK)) ; + WRITE_REG(usart->huart.perh->DATA, c); + } + else + { + /*UART*/ + while (!(uart->huart.perh->SR & 0x40)) ; + WRITE_REG(uart->huart.perh->TBR, c); + } + + return 1; +} + +static int es32f0x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if((uint32_t)(uart->huart.perh) > (uint32_t)UART3) /*根据外设物理地址区分UART和USART*/ + { + /*USART*/ + struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data; + if (usart->huart.perh->STAT & USART_STAT_RXNEIF_MSK) + { + ch = (uint8_t)(usart->huart.perh->DATA & 0xFF); + } + } + else + { + /*UART*/ + if (uart->huart.perh->SR & 0x01) + { + ch = (uint8_t)(uart->huart.perh->RBR & 0xFF); + } + } + + return ch; +} + +static const struct rt_uart_ops es32f0x_uart_ops = +{ + es32f0x_configure, + es32f0x_control, + es32f0x_putc, + es32f0x_getc, +}; int rt_hw_uart_init(void) { +#if (defined(BSP_USING_UART0)||defined(BSP_USING_UART1)||defined(BSP_USING_UART2)||defined(BSP_USING_UART3)) struct es32_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#endif +#if (defined(BSP_USING_USART0)||defined(BSP_USING_USART1)) + struct es32_usart *usart; +#endif #ifdef BSP_USING_UART0 uart = &uart0; serial0.ops = &es32f0x_uart_ops; - serial0.config = config; + serial0.config = (struct serial_configure)ES_UART0_CONFIG; /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", + rt_hw_serial_register(&serial0, ES_DEVICE_NAME_UART0, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART0 */ @@ -286,10 +520,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART1 uart = &uart1; serial1.ops = &es32f0x_uart_ops; - serial1.config = config; + serial1.config = (struct serial_configure)ES_UART1_CONFIG; /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", + rt_hw_serial_register(&serial1, ES_DEVICE_NAME_UART1, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART1 */ @@ -297,10 +531,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART2 uart = &uart2; serial2.ops = &es32f0x_uart_ops; - serial2.config = config; + serial2.config = (struct serial_configure)ES_UART2_CONFIG; /* register UART2 device */ - rt_hw_serial_register(&serial2, "uart2", + rt_hw_serial_register(&serial2, ES_DEVICE_NAME_UART2, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART2 */ @@ -308,14 +542,35 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART3 uart = &uart3; serial3.ops = &es32f0x_uart_ops; - serial3.config = config; + serial3.config = (struct serial_configure)ES_UART3_CONFIG; /* register UART3 device */ - rt_hw_serial_register(&serial3, "uart3", + rt_hw_serial_register(&serial3, ES_DEVICE_NAME_UART3, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART3 */ + +#ifdef BSP_USING_USART0 + usart = &usart0; + serial4.ops = &es32f0x_uart_ops; + serial4.config = (struct serial_configure)ES_USART0_CONFIG; + /* register USART0 device */ + rt_hw_serial_register(&serial4, ES_DEVICE_NAME_USART0, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + usart); +#endif /* BSP_USING_USART0 */ + +#ifdef BSP_USING_USART1 + usart = &usart1; + serial5.ops = &es32f0x_uart_ops; + serial5.config = (struct serial_configure)ES_USART1_CONFIG; + + /* register USART1 device */ + rt_hw_serial_register(&serial5, ES_DEVICE_NAME_USART1, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + usart); +#endif /* BSP_USING_USART1 */ return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/essemi/es32f0654/drivers/drv_uart.h b/bsp/essemi/es32f0654/drivers/drv_uart.h index e68d67ca1e..a7eb0de41d 100644 --- a/bsp/essemi/es32f0654/drivers/drv_uart.h +++ b/bsp/essemi/es32f0654/drivers/drv_uart.h @@ -3,6 +3,18 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h index 2bbe7437d0..535d7c2770 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h index b5f9532f8d..efad62ab26 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -9,6 +9,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ****************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h index cbaa1c88f8..038ddf635b 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h index 283417d843..870c5b536d 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h index 196094eaaa..04a5d5ef5e 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ****************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h index 648b3c2b50..314c585a8a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h index 2a91282ab6..673782173a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h index 3ea24ea927..d40e22fcf9 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h index 483c15a31e..00be4131f3 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h index 3f695b7e8f..a4e2d75621 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h index 1fbebd56bf..4d7f6b9787 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h index 8858b8b707..ad3148382f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h index 336c90f977..01df5fd138 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h index f421ff168e..27527104ba 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h index a777fca4a9..2fa6a4f6ec 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h index c17b03cfd9..5b63193f46 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h index 264c185b81..be93e204ba 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h index 164ebb5e3f..6cc63fab8a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h index dd5d8ad7ee..fbb6799c17 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h index 74401fecc1..291908e6d5 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h index 1a7c7c7e5e..5820deadf2 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h index 35844c887e..3df2492432 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h index 538fc0ca0b..e6f4986947 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h index 635cb1a90a..202e6f2af8 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h index 410dcb7ff6..dc78ce56cc 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h index 10a351ca19..a240a91b36 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h index 4f30e2c2a4..b3cd4bf421 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h index 619f777324..2473a8ebb2 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h index 54082f3f21..a892c69bd4 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ @@ -22,6 +36,7 @@ extern "C" { #endif #include +#include "es_conf_info_select.h" #if defined (__CC_ARM) diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h index 5ad1dc36a7..165cec6306 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c index e480de1697..cec11372c3 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c index 7f1f522c7a..bf0215740b 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -24,6 +24,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c index a3852bdb22..b459fba045 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c index ec2400453d..2196ffb99f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c index fb551abdf1..b665165077 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c @@ -14,6 +14,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c index e43b12c7d1..b6473dc432 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c index bf6fde037c..2a69489158 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c index ff8f92d9d5..1381bd416f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c index f3c125578d..080dff3045 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c index 44d25a7f76..224843cb01 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include "ald_flash.h" diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 44e8fe7d9c..4087b71b01 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * ********************************************************************************* diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c index 08366e9350..153a21d8a6 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -16,6 +16,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c index 82faa31502..a442d73428 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * @verbatim ============================================================================== ##### How to use this driver ##### diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c index ccb9b5170b..61cee32739 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c index d9067499ea..c83907e0c2 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c index f8b4b94e27..976bae4334 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c index 2b04f2719c..ec2ec312b6 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c index 7391045a62..4863178005 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -18,6 +18,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c index 2b3552ab77..5a18e4ed27 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c @@ -16,6 +16,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c index f756f6785d..fd154c6c73 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c index dc0a285368..77d3b14c8f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c index 8e4d13a4d0..81a62e6127 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c index 5fcd8311f1..9200f5a33f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c index 59c2489bfa..3a13a5ea04 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c index 1e9ed5c501..8c9c2ef8f1 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c index d19a0397ab..fe21244fe7 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c index e406c53afc..e74f9d3f7f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f0654/project.uvprojx b/bsp/essemi/es32f0654/project.uvprojx index 70c93b4c8e..569397deb8 100644 --- a/bsp/essemi/es32f0654/project.uvprojx +++ b/bsp/essemi/es32f0654/project.uvprojx @@ -336,9 +336,9 @@ 0 - ES32F065x + ES32F065x, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include + applications;.;drivers\ES;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include @@ -390,8 +390,13 @@ - cpu + CPU + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + backtrace.c 1 @@ -403,168 +408,34 @@ ..\..\..\libcpu\arm\common\div0.c - showmem.c - 1 - ..\..\..\libcpu\arm\common\showmem.c + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S cpuport.c 1 ..\..\..\libcpu\arm\cortex-m0\cpuport.c - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m0\context_rvds.S - DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - can.c - 1 - ..\..\..\components\drivers\can\can.c - - - hwtimer.c - 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c - - - i2c_core.c - 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - i2c-bit-ops.c - 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - adc.c - 1 - ..\..\..\components\drivers\misc\adc.c - - - rt_drv_pwm.c - 1 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - - - pm.c - 1 - ..\..\..\components\drivers\pm\pm.c - - - rtc.c - 1 - ..\..\..\components\drivers\rtc\rtc.c - serial.c 1 ..\..\..\components\drivers\serial\serial.c - spi_core.c + waitqueue.c 1 - ..\..\..\components\drivers\spi\spi_core.c - - - spi_dev.c - 1 - ..\..\..\components\drivers\spi\spi_dev.c - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c + ..\..\..\components\drivers\src\waitqueue.c pipe.c @@ -572,9 +443,9 @@ ..\..\..\components\drivers\src\pipe.c - ringblk_buf.c + dataqueue.c 1 - ..\..\..\components\drivers\src\ringblk_buf.c + ..\..\..\components\drivers\src\dataqueue.c ringbuffer.c @@ -582,25 +453,25 @@ ..\..\..\components\drivers\src\ringbuffer.c - waitqueue.c + ringblk_buf.c 1 - ..\..\..\components\drivers\src\waitqueue.c + ..\..\..\components\drivers\src\ringblk_buf.c workqueue.c 1 ..\..\..\components\drivers\src\workqueue.c + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + Drivers - - board.c - 1 - drivers\board.c - drv_gpio.c 1 @@ -611,6 +482,11 @@ 1 drivers\drv_uart.c + + board.c + 1 + drivers\board.c + @@ -621,30 +497,25 @@ 1 ..\..\..\components\finsh\shell.c - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - msh.c 1 ..\..\..\components\finsh\msh.c + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + Kernel - clock.c + ipc.c 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c + ..\..\..\src\ipc.c device.c @@ -652,19 +523,9 @@ ..\..\..\src\device.c - idle.c + object.c 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - irq.c - 1 - ..\..\..\src\irq.c + ..\..\..\src\object.c kservice.c @@ -672,9 +533,29 @@ ..\..\..\src\kservice.c - mem.c + scheduler.c 1 - ..\..\..\src\mem.c + ..\..\..\src\scheduler.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + components.c + 1 + ..\..\..\src\components.c + + + timer.c + 1 + ..\..\..\src\timer.c mempool.c @@ -682,19 +563,9 @@ ..\..\..\src\mempool.c - object.c + mem.c 1 - ..\..\..\src\object.c - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - signal.c - 1 - ..\..\..\src\signal.c + ..\..\..\src\mem.c thread.c @@ -702,20 +573,155 @@ ..\..\..\src\thread.c - timer.c + clock.c 1 - ..\..\..\src\timer.c + ..\..\..\src\clock.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c Libraries + + ald_dma.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c + + + ald_crc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c + + + utils.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c + + + ald_flash_ext.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + + + ald_trng.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c + + + ald_pmu.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c + + + ald_i2c.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c + + + ald_can.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c + + + ald_crypt.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c + + + ald_spi.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c + + + ald_rtc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c + + + ald_iap.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c + + + startup_es32f065x.s + 2 + libraries\CMSIS\Device\EastSoft\ES32F065x\Startup\keil\startup_es32f065x.s + + + ald_usart.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c + + + ald_uart.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c + + + ald_tsense.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c + + + ald_wdt.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c + + + ald_flash.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c + + + ald_smartcard.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c + + + ald_pis.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c + + + ald_cmu.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c + + + ald_rmu.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c + ald_acmp.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_acmp.c + + ald_calc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c + + + ald_gpio.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c + + + ald_timer.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c + ald_adc.c 1 @@ -726,131 +732,6 @@ 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_bkpc.c - - ald_calc.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c - - - ald_can.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c - - - ald_cmu.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c - - - ald_crc.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c - - - ald_crypt.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c - - - ald_dma.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c - - - ald_flash.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c - - - ald_flash_ext.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - - - ald_gpio.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c - - - ald_i2c.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c - - - ald_iap.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c - - - ald_pis.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c - - - ald_pmu.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c - - - ald_rmu.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c - - - ald_rtc.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c - - - ald_smartcard.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c - - - ald_spi.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c - - - ald_timer.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c - - - ald_trng.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c - - - ald_tsense.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c - - - ald_uart.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c - - - ald_usart.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c - - - ald_wdt.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c - - - utils.c - 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c - - - startup_es32f065x.s - 2 - libraries\CMSIS\Device\EastSoft\ES32F065x\Startup\keil\startup_es32f065x.s - diff --git a/bsp/essemi/es32f0654/rtconfig.h b/bsp/essemi/es32f0654/rtconfig.h index 3a173aaa59..9b50643265 100644 --- a/bsp/essemi/es32f0654/rtconfig.h +++ b/bsp/essemi/es32f0654/rtconfig.h @@ -76,16 +76,7 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_CAN -#define RT_USING_HWTIMER -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS #define RT_USING_PIN -#define RT_USING_ADC -#define RT_USING_PWM -#define RT_USING_PM -#define RT_USING_RTC -#define RT_USING_SPI /* Using USB */ diff --git a/bsp/essemi/es32f369x/.config b/bsp/essemi/es32f369x/.config index af456dc765..5e47c69c47 100644 --- a/bsp/essemi/es32f369x/.config +++ b/bsp/essemi/es32f369x/.config @@ -19,8 +19,9 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_KSERVICE_USING_STDLIB is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -42,7 +43,7 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set +CONFIG_RT_USING_SIGNALS=y # # Memory Management @@ -52,6 +53,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -114,31 +116,21 @@ CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_CAN=y -# CONFIG_RT_CAN_USING_HDR is not set -CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -159,7 +151,7 @@ CONFIG_RT_USING_SPI=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_LIBC_USING_TIME is not set +CONFIG_RT_LIBC_USING_TIME=y # # Network @@ -305,6 +297,8 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set # CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -319,6 +313,7 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set @@ -326,6 +321,10 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set # CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set # # system packages @@ -352,7 +351,16 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_RAMDISK is not set # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set # @@ -408,6 +416,10 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set # # miscellaneous packages @@ -417,6 +429,7 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -437,17 +450,23 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_NNOM is not set # CONFIG_PKG_USING_LIBANN is not set # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_LWGPS is not set # CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set CONFIG_SOC_ES32F3696LT=y @@ -487,12 +506,13 @@ CONFIG_BSP_USING_UART0=y # # CAN Drivers # -# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_CAN0 is not set # # ADC Drivers # -# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ADC0 is not set +# CONFIG_BSP_USING_ADC1 is not set # # RTC Drivers @@ -500,16 +520,26 @@ CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_RTC is not set # -# HWtimer Drivers +# HWTIMER Drivers # -# CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set +# CONFIG_BSP_USING_AD16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_AD16C4T1_HWTIMER is not set +# CONFIG_BSP_USING_GP32C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP32C4T1_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T1_HWTIMER is not set +# CONFIG_BSP_USING_BS16T0_HWTIMER is not set +# CONFIG_BSP_USING_BS16T1_HWTIMER is not set # # PWM Drivers # -# CONFIG_BSP_USING_PWM0 is not set -# CONFIG_BSP_USING_PWM1 is not set +# CONFIG_BSP_USING_AD16C4T0_PWM is not set +# CONFIG_BSP_USING_AD16C4T1_PWM is not set +# CONFIG_BSP_USING_GP32C4T0_PWM is not set +# CONFIG_BSP_USING_GP32C4T1_PWM is not set +# CONFIG_BSP_USING_GP16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C4T1_PWM is not set # # PM Drivers diff --git a/bsp/essemi/es32f369x/drivers/ES/Kconfig b/bsp/essemi/es32f369x/drivers/ES/Kconfig new file mode 100644 index 0000000000..9ba55d110e --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/Kconfig @@ -0,0 +1,197 @@ +menu "UART Drivers" + + config BSP_USING_UART0 + bool "Register UART0 " + select RT_USING_SERIAL + default y + + config BSP_USING_UART1 + bool "Register UART1 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Register UART2 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART3 + bool "Register UART3 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART4 + bool "Register UART4 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART5 + bool "Register UART5 " + select RT_USING_SERIAL + default n + +endmenu + +menu "SPI Drivers" + + config BSP_USING_SPI0 + bool "Register SPI0 " + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Register SPI1 " + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI2 + bool "Register SPI2 " + select RT_USING_SPI + select RT_USING_PIN + default n + +endmenu + +menu "I2C Drivers" + + config BSP_USING_I2C0 + bool "Register I2C0 " + select RT_USING_I2C + default n + + config BSP_USING_I2C1 + bool "Register I2C1 " + select RT_USING_I2C + default n + +endmenu + +menu "CAN Drivers" + + config BSP_USING_CAN0 + bool "Register CAN0 " + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_CAN + default n + +endmenu + +menu "ADC Drivers" + + config BSP_USING_ADC0 + bool "Register ADC0 " + select RT_USING_ADC + default n + + config BSP_USING_ADC1 + bool "Register ADC1 " + select RT_USING_ADC + default n + +endmenu + +menu "RTC Drivers" + + config BSP_USING_RTC + bool "Register RTC " + select RT_USING_RTC + default n + +endmenu + +menu "HWTIMER Drivers" + + config BSP_USING_AD16C4T0_HWTIMER + bool "Register HWTIMER0 " + select RT_USING_HWTIMER + default n + + config BSP_USING_AD16C4T1_HWTIMER + bool "Register HWTIMER1 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP32C4T0_HWTIMER + bool "Register HWTIMER2 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP32C4T1_HWTIMER + bool "Register HWTIMER3 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T0_HWTIMER + bool "Register HWTIMER4 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T1_HWTIMER + bool "Register HWTIMER5 " + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T0_HWTIMER + bool "Register HWTIMER6 " + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T1_HWTIMER + bool "Register HWTIMER7 " + select RT_USING_HWTIMER + default n + +endmenu + +menu "PWM Drivers" + + config BSP_USING_AD16C4T0_PWM + bool "Register PWM0 " + select RT_USING_PWM + default n + depends on !BSP_USING_AD16C4T0_HWTIMER + + config BSP_USING_AD16C4T1_PWM + bool "Register PWM1 " + select RT_USING_PWM + default n + depends on !BSP_USING_AD16C4T1_HWTIMER + + config BSP_USING_GP32C4T0_PWM + bool "Register PWM2 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP32C4T0_HWTIMER + + config BSP_USING_GP32C4T1_PWM + bool "Register PWM3 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP32C4T1_HWTIMER + + config BSP_USING_GP16C4T0_PWM + bool "Register PWM4 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T0_HWTIMER + + config BSP_USING_GP16C4T1_PWM + bool "Register PWM5 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T1_HWTIMER + +endmenu + +menu "PM Drivers" + + config BSP_USING_PM + bool "Register PM " + select RT_USING_PM + default n + +endmenu + diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h new file mode 100644 index 0000000000..772f7a0df0 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h @@ -0,0 +1,97 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_ADC_H__ +#define __ES_CONF_INFO_ADC_H__ + +#include "es_conf_info_map.h" + +#include + + +#define ES_C_ADC_CLK_DIV_1 ADC_CKDIV_1 +#define ES_C_ADC_CLK_DIV_2 ADC_CKDIV_2 +#define ES_C_ADC_CLK_DIV_4 ADC_CKDIV_4 +#define ES_C_ADC_CLK_DIV_8 ADC_CKDIV_8 +#define ES_C_ADC_CLK_DIV_16 ADC_CKDIV_16 +#define ES_C_ADC_CLK_DIV_32 ADC_CKDIV_32 +#define ES_C_ADC_CLK_DIV_64 ADC_CKDIV_64 +#define ES_C_ADC_CLK_DIV_128 ADC_CKDIV_128 + +#define ES_C_ADC_ALIGN_RIGHT ADC_DATAALIGN_RIGHT +#define ES_C_ADC_ALIGN_LEFT ADC_DATAALIGN_LEFT + +#define ES_C_ADC_CONV_BIT_6 ADC_CONV_BIT_6 +#define ES_C_ADC_CONV_BIT_8 ADC_CONV_BIT_8 +#define ES_C_ADC_CONV_BIT_10 ADC_CONV_BIT_10 +#define ES_C_ADC_CONV_BIT_12 ADC_CONV_BIT_12 + +#define ES_C_ADC_SAMPLE_TIME_1 ADC_SAMPLETIME_1 +#define ES_C_ADC_SAMPLE_TIME_2 ADC_SAMPLETIME_2 +#define ES_C_ADC_SAMPLE_TIME_4 ADC_SAMPLETIME_4 +#define ES_C_ADC_SAMPLE_TIME_15 ADC_SAMPLETIME_15 + +/* ADC 配置 */ + +/* codes_main */ + + +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 + +#ifndef ES_DEVICE_NAME_ADC0 +#define ES_DEVICE_NAME_ADC0 "adc0" +#endif +#ifndef ES_DEVICE_NAME_ADC1 +#define ES_DEVICE_NAME_ADC1 "adc1" +#endif + +#ifndef ES_ADC0_CLK_DIV +#define ES_ADC0_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC0_ALIGN +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC0_DATA_BIT +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC0_NCH_SAMPLETIME +#define ES_ADC0_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#ifndef ES_ADC1_CLK_DIV +#define ES_ADC1_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC1_ALIGN +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC1_DATA_BIT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC1_NCH_SAMPLETIME +#define ES_ADC1_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h new file mode 100644 index 0000000000..46df1ed054 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h @@ -0,0 +1,73 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CAN_H__ +#define __ES_CONF_INFO_CAN_H__ + +#include "es_conf_info_map.h" +#include +#include + + +/*默认的CAN硬件过滤器的编号 0 */ +#define ES_C_CAN_DEFAULT_FILTER_NUMBER 0 + +/*硬件过滤器，过滤帧类型*/ +#define ES_C_CAN_FILTER_FRAME_TYPE 0 + + +#define ES_C_CAN_SJW_NUM_1 CAN_SJW_1 +#define ES_C_CAN_SJW_NUM_2 CAN_SJW_2 +#define ES_C_CAN_SJW_NUM_3 CAN_SJW_3 +#define ES_C_CAN_SJW_NUM_4 CAN_SJW_4 + + + +/* CAN 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_CAN0 +#define ES_DEVICE_NAME_CAN0 "can0" +#endif + +#ifndef ES_CAN0_AUTO_BAN_RE_T +#define ES_CAN0_AUTO_BAN_RE_T ES_C_ENABLE +#endif +#ifndef ES_CAN0_SPEED +#define ES_CAN0_SPEED 1000000 +#endif +#ifndef ES_CAN0_SJW +#define ES_CAN0_SJW ES_C_CAN_SJW_NUM_4 +#endif + +#define ES_CAN0_CONFIG \ +{ \ + ES_CAN0_SPEED, \ + RT_CANMSG_BOX_SZ, \ + RT_CANSND_BOX_NUM, \ + RT_CAN_MODE_NORMAL, \ +}; +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h new file mode 100644 index 0000000000..1c5e6a829a --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h @@ -0,0 +1,89 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CMU_H__ +#define __ES_CONF_INFO_CMU_H__ + + +#include + + +/* 时钟树 配置 */ + +#define ES_C_MUL_9 CMU_PLL1_OUTPUT_36M +#define ES_C_MUL_12 CMU_PLL1_OUTPUT_48M +#define ES_C_MUL_18 CMU_PLL1_OUTPUT_72M +#define ES_C_MUL_24 CMU_PLL1_OUTPUT_96M + +#define ES_C_DIV_1 CMU_DIV_1 +#define ES_C_DIV_2 CMU_DIV_2 +#define ES_C_DIV_4 CMU_DIV_4 +#define ES_C_DIV_8 CMU_DIV_8 +#define ES_C_DIV_16 CMU_DIV_16 +#define ES_C_DIV_32 CMU_DIV_32 +#define ES_C_DIV_64 CMU_DIV_64 +#define ES_C_DIV_128 CMU_DIV_128 +#define ES_C_DIV_256 CMU_DIV_256 +#define ES_C_DIV_512 CMU_DIV_512 +#define ES_C_DIV_1024 CMU_DIV_1024 +#define ES_C_DIV_2048 CMU_DIV_2048 +#define ES_C_DIV_4096 CMU_DIV_4096 + +#define ES_C_HOSC_DIV_1 CMU_PLL1_INPUT_HOSC +#define ES_C_HOSC_DIV_2 CMU_PLL1_INPUT_HOSC_2 +#define ES_C_HOSC_DIV_3 CMU_PLL1_INPUT_HOSC_3 +#define ES_C_HOSC_DIV_4 CMU_PLL1_INPUT_HOSC_4 +#define ES_C_HOSC_DIV_5 CMU_PLL1_INPUT_HOSC_5 +#define ES_C_HOSC_DIV_6 CMU_PLL1_INPUT_HOSC_6 +#define ES_C_HRC_DIV_6 CMU_PLL1_INPUT_HRC_6 + + + + + +#define ES_PLL1_REFER_CLK ES_C_HOSC_DIV_3 +#define ES_PLL1_OUT_CLK ES_C_MUL_18 +#define ES_CMU_PLL1_EN ES_C_ENABLE +#define ES_CMU_PLL1_SAFE_EN ES_C_DISABLE +#define ES_CMU_LOSC_EN ES_C_ENABLE +#define ES_CMU_LRC_EN ES_C_ENABLE +#define ES_CMU_HOSC_EN ES_C_ENABLE +#define ES_CMU_HRC_EN ES_C_ENABLE +#define ES_CMU_SYS_DIV ES_C_DIV_1 +#define ES_CMU_HCLK_1_DIV ES_C_DIV_2 +#define ES_CMU_HCLK_2_DIV ES_C_DIV_2 +#define ES_CMU_PCLK_1_DIV ES_C_DIV_2 +#define ES_CMU_PCLK_2_DIV ES_C_DIV_4 +#define ES_SYS_CLK_SOURSE CMU_CLOCK_PLL1 +#define ES_PLL_CLK 72000000 +#define ES_SYS_SOURCE_CLK 72000000 +#define ES_SYS_CLK 72000000 +#define ES_PCLK1_CLK 36000000 +#define ES_PCLK2_CLK 18000000 +#define ES_HCLK1_CLK 36000000 +#define ES_HCLK2_CLK 36000000 +#define ES_CMU_EXTERN_CLK_LOSC 32768 +#define ES_CMU_EXTERN_CLK_HOSC 12000000 + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h new file mode 100644 index 0000000000..7748e5fda2 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h @@ -0,0 +1,5157 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_GPIO_H__ +#define __ES_CONF_INFO_GPIO_H__ + +#include "es_conf_info_map.h" + +#include +#include +#include + +/* GPIO 配置 */ + +typedef struct { + uint8_t pin; + uint8_t pin_mode; + uint8_t pin_level; + uint8_t irq_en; + uint8_t irq_mode; + void (*callback)(void *arg); +} gpio_conf_t; + +/*参数的定义*/ + +#define ES_C_GPIO_LEVEL_HIGH PIN_HIGH +#define ES_C_GPIO_LEVEL_LOW PIN_LOW + +#define ES_C_GPIO_MODE_OUTPUT PIN_MODE_OUTPUT +#define ES_C_GPIO_MODE_INPUT PIN_MODE_INPUT +#define ES_C_GPIO_MODE_INPUT_PULLUP PIN_MODE_INPUT_PULLUP +#define ES_C_GPIO_MODE_INPUT_PULLDOWN PIN_MODE_INPUT_PULLDOWN +#define ES_C_GPIO_MODE_OUTPUT_OD PIN_MODE_OUTPUT_OD + +#define ES_C_GPIO_IRQ_ENABLE PIN_IRQ_ENABLE +#define ES_C_GPIO_IRQ_DISABLE PIN_IRQ_DISABLE + +#define ES_C_GPIO_IRQ_MODE_FALL PIN_IRQ_MODE_FALLING +#define ES_C_GPIO_IRQ_MODE_RISE PIN_IRQ_MODE_RISING +#define ES_C_GPIO_IRQ_MODE_R_F PIN_IRQ_MODE_RISING_FALLING + + + + + +/* codes_main */ + + + + +#ifndef ES_DEVICE_NAME_PIN +#define ES_DEVICE_NAME_PIN "pin" +#endif + +/*GPIO外部中断回调函数控制需要，补充是否中断*/ +#if 11111 + +#ifndef ES_INIT_GPIO_A_0_IRQ_EN +#define ES_INIT_GPIO_A_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_1_IRQ_EN +#define ES_INIT_GPIO_A_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_2_IRQ_EN +#define ES_INIT_GPIO_A_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_3_IRQ_EN +#define ES_INIT_GPIO_A_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_4_IRQ_EN +#define ES_INIT_GPIO_A_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_5_IRQ_EN +#define ES_INIT_GPIO_A_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_6_IRQ_EN +#define ES_INIT_GPIO_A_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_7_IRQ_EN +#define ES_INIT_GPIO_A_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_8_IRQ_EN +#define ES_INIT_GPIO_A_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_9_IRQ_EN +#define ES_INIT_GPIO_A_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_10_IRQ_EN +#define ES_INIT_GPIO_A_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_11_IRQ_EN +#define ES_INIT_GPIO_A_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_12_IRQ_EN +#define ES_INIT_GPIO_A_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_13_IRQ_EN +#define ES_INIT_GPIO_A_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_14_IRQ_EN +#define ES_INIT_GPIO_A_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_15_IRQ_EN +#define ES_INIT_GPIO_A_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_0_IRQ_EN +#define ES_INIT_GPIO_B_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_1_IRQ_EN +#define ES_INIT_GPIO_B_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_2_IRQ_EN +#define ES_INIT_GPIO_B_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_3_IRQ_EN +#define ES_INIT_GPIO_B_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_4_IRQ_EN +#define ES_INIT_GPIO_B_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_5_IRQ_EN +#define ES_INIT_GPIO_B_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_6_IRQ_EN +#define ES_INIT_GPIO_B_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_7_IRQ_EN +#define ES_INIT_GPIO_B_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_8_IRQ_EN +#define ES_INIT_GPIO_B_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_9_IRQ_EN +#define ES_INIT_GPIO_B_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_10_IRQ_EN +#define ES_INIT_GPIO_B_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_11_IRQ_EN +#define ES_INIT_GPIO_B_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_12_IRQ_EN +#define ES_INIT_GPIO_B_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_13_IRQ_EN +#define ES_INIT_GPIO_B_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_14_IRQ_EN +#define ES_INIT_GPIO_B_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_15_IRQ_EN +#define ES_INIT_GPIO_B_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_0_IRQ_EN +#define ES_INIT_GPIO_C_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_1_IRQ_EN +#define ES_INIT_GPIO_C_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_2_IRQ_EN +#define ES_INIT_GPIO_C_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_3_IRQ_EN +#define ES_INIT_GPIO_C_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_4_IRQ_EN +#define ES_INIT_GPIO_C_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_5_IRQ_EN +#define ES_INIT_GPIO_C_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_6_IRQ_EN +#define ES_INIT_GPIO_C_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_7_IRQ_EN +#define ES_INIT_GPIO_C_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_8_IRQ_EN +#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_9_IRQ_EN +#define ES_INIT_GPIO_C_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_10_IRQ_EN +#define ES_INIT_GPIO_C_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_11_IRQ_EN +#define ES_INIT_GPIO_C_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_12_IRQ_EN +#define ES_INIT_GPIO_C_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_13_IRQ_EN +#define ES_INIT_GPIO_C_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_14_IRQ_EN +#define ES_INIT_GPIO_C_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_15_IRQ_EN +#define ES_INIT_GPIO_C_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_0_IRQ_EN +#define ES_INIT_GPIO_D_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_1_IRQ_EN +#define ES_INIT_GPIO_D_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_2_IRQ_EN +#define ES_INIT_GPIO_D_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_3_IRQ_EN +#define ES_INIT_GPIO_D_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_4_IRQ_EN +#define ES_INIT_GPIO_D_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_5_IRQ_EN +#define ES_INIT_GPIO_D_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_6_IRQ_EN +#define ES_INIT_GPIO_D_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_7_IRQ_EN +#define ES_INIT_GPIO_D_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_8_IRQ_EN +#define ES_INIT_GPIO_D_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_9_IRQ_EN +#define ES_INIT_GPIO_D_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_10_IRQ_EN +#define ES_INIT_GPIO_D_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_11_IRQ_EN +#define ES_INIT_GPIO_D_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_12_IRQ_EN +#define ES_INIT_GPIO_D_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_13_IRQ_EN +#define ES_INIT_GPIO_D_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_14_IRQ_EN +#define ES_INIT_GPIO_D_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_15_IRQ_EN +#define ES_INIT_GPIO_D_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_0_IRQ_EN +#define ES_INIT_GPIO_E_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_1_IRQ_EN +#define ES_INIT_GPIO_E_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_2_IRQ_EN +#define ES_INIT_GPIO_E_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_3_IRQ_EN +#define ES_INIT_GPIO_E_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_4_IRQ_EN +#define ES_INIT_GPIO_E_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_5_IRQ_EN +#define ES_INIT_GPIO_E_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_6_IRQ_EN +#define ES_INIT_GPIO_E_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_7_IRQ_EN +#define ES_INIT_GPIO_E_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_8_IRQ_EN +#define ES_INIT_GPIO_E_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_9_IRQ_EN +#define ES_INIT_GPIO_E_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_10_IRQ_EN +#define ES_INIT_GPIO_E_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_11_IRQ_EN +#define ES_INIT_GPIO_E_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_12_IRQ_EN +#define ES_INIT_GPIO_E_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_13_IRQ_EN +#define ES_INIT_GPIO_E_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_14_IRQ_EN +#define ES_INIT_GPIO_E_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_15_IRQ_EN +#define ES_INIT_GPIO_E_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_0_IRQ_EN +#define ES_INIT_GPIO_F_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_1_IRQ_EN +#define ES_INIT_GPIO_F_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_2_IRQ_EN +#define ES_INIT_GPIO_F_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_3_IRQ_EN +#define ES_INIT_GPIO_F_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_4_IRQ_EN +#define ES_INIT_GPIO_F_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_5_IRQ_EN +#define ES_INIT_GPIO_F_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_6_IRQ_EN +#define ES_INIT_GPIO_F_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_7_IRQ_EN +#define ES_INIT_GPIO_F_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_8_IRQ_EN +#define ES_INIT_GPIO_F_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_9_IRQ_EN +#define ES_INIT_GPIO_F_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_10_IRQ_EN +#define ES_INIT_GPIO_F_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_11_IRQ_EN +#define ES_INIT_GPIO_F_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_12_IRQ_EN +#define ES_INIT_GPIO_F_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_13_IRQ_EN +#define ES_INIT_GPIO_F_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_14_IRQ_EN +#define ES_INIT_GPIO_F_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_15_IRQ_EN +#define ES_INIT_GPIO_F_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_0_IRQ_EN +#define ES_INIT_GPIO_G_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_1_IRQ_EN +#define ES_INIT_GPIO_G_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_2_IRQ_EN +#define ES_INIT_GPIO_G_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_3_IRQ_EN +#define ES_INIT_GPIO_G_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_4_IRQ_EN +#define ES_INIT_GPIO_G_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_5_IRQ_EN +#define ES_INIT_GPIO_G_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_6_IRQ_EN +#define ES_INIT_GPIO_G_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_7_IRQ_EN +#define ES_INIT_GPIO_G_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_8_IRQ_EN +#define ES_INIT_GPIO_G_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_9_IRQ_EN +#define ES_INIT_GPIO_G_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_10_IRQ_EN +#define ES_INIT_GPIO_G_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_11_IRQ_EN +#define ES_INIT_GPIO_G_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_12_IRQ_EN +#define ES_INIT_GPIO_G_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_13_IRQ_EN +#define ES_INIT_GPIO_G_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_14_IRQ_EN +#define ES_INIT_GPIO_G_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_15_IRQ_EN +#define ES_INIT_GPIO_G_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_0_IRQ_EN +#define ES_INIT_GPIO_H_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_1_IRQ_EN +#define ES_INIT_GPIO_H_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_2_IRQ_EN +#define ES_INIT_GPIO_H_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_3_IRQ_EN +#define ES_INIT_GPIO_H_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_4_IRQ_EN +#define ES_INIT_GPIO_H_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_5_IRQ_EN +#define ES_INIT_GPIO_H_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_6_IRQ_EN +#define ES_INIT_GPIO_H_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_7_IRQ_EN +#define ES_INIT_GPIO_H_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_8_IRQ_EN +#define ES_INIT_GPIO_H_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_9_IRQ_EN +#define ES_INIT_GPIO_H_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_10_IRQ_EN +#define ES_INIT_GPIO_H_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_11_IRQ_EN +#define ES_INIT_GPIO_H_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_12_IRQ_EN +#define ES_INIT_GPIO_H_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_13_IRQ_EN +#define ES_INIT_GPIO_H_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_14_IRQ_EN +#define ES_INIT_GPIO_H_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_15_IRQ_EN +#define ES_INIT_GPIO_H_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#endif //11111 + + + +/*是否需要 GPIO外部中断回调函数 （控制函数本体+声明）*/ +#if 11111 + +#if (ES_INIT_GPIO_A_0_IRQ_EN)||(ES_INIT_GPIO_B_0_IRQ_EN)||(ES_INIT_GPIO_C_0_IRQ_EN)||(ES_INIT_GPIO_D_0_IRQ_EN)|| \ + (ES_INIT_GPIO_E_0_IRQ_EN)||(ES_INIT_GPIO_F_0_IRQ_EN)||(ES_INIT_GPIO_G_0_IRQ_EN)||(ES_INIT_GPIO_H_0_IRQ_EN) +#define ES_CONF_EXTI_IRQ_0 +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN)||(ES_INIT_GPIO_B_1_IRQ_EN)||(ES_INIT_GPIO_C_1_IRQ_EN)||(ES_INIT_GPIO_D_1_IRQ_EN)|| \ + (ES_INIT_GPIO_E_1_IRQ_EN)||(ES_INIT_GPIO_F_1_IRQ_EN)||(ES_INIT_GPIO_G_1_IRQ_EN)||(ES_INIT_GPIO_H_1_IRQ_EN) +#define ES_CONF_EXTI_IRQ_1 +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN)||(ES_INIT_GPIO_B_2_IRQ_EN)||(ES_INIT_GPIO_C_2_IRQ_EN)||(ES_INIT_GPIO_D_2_IRQ_EN)|| \ + (ES_INIT_GPIO_E_2_IRQ_EN)||(ES_INIT_GPIO_F_2_IRQ_EN)||(ES_INIT_GPIO_G_2_IRQ_EN)||(ES_INIT_GPIO_H_2_IRQ_EN) +#define ES_CONF_EXTI_IRQ_2 +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN)||(ES_INIT_GPIO_B_3_IRQ_EN)||(ES_INIT_GPIO_C_3_IRQ_EN)||(ES_INIT_GPIO_D_3_IRQ_EN)|| \ + (ES_INIT_GPIO_E_3_IRQ_EN)||(ES_INIT_GPIO_F_3_IRQ_EN)||(ES_INIT_GPIO_G_3_IRQ_EN)||(ES_INIT_GPIO_H_3_IRQ_EN) +#define ES_CONF_EXTI_IRQ_3 +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN)||(ES_INIT_GPIO_B_4_IRQ_EN)||(ES_INIT_GPIO_C_4_IRQ_EN)||(ES_INIT_GPIO_D_4_IRQ_EN)|| \ + (ES_INIT_GPIO_E_4_IRQ_EN)||(ES_INIT_GPIO_F_4_IRQ_EN)||(ES_INIT_GPIO_G_4_IRQ_EN)||(ES_INIT_GPIO_H_4_IRQ_EN) +#define ES_CONF_EXTI_IRQ_4 +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN)||(ES_INIT_GPIO_B_5_IRQ_EN)||(ES_INIT_GPIO_C_5_IRQ_EN)||(ES_INIT_GPIO_D_5_IRQ_EN)|| \ + (ES_INIT_GPIO_E_5_IRQ_EN)||(ES_INIT_GPIO_F_5_IRQ_EN)||(ES_INIT_GPIO_G_5_IRQ_EN)||(ES_INIT_GPIO_H_5_IRQ_EN) +#define ES_CONF_EXTI_IRQ_5 +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN)||(ES_INIT_GPIO_B_6_IRQ_EN)||(ES_INIT_GPIO_C_6_IRQ_EN)||(ES_INIT_GPIO_D_6_IRQ_EN)|| \ + (ES_INIT_GPIO_E_6_IRQ_EN)||(ES_INIT_GPIO_F_6_IRQ_EN)||(ES_INIT_GPIO_G_6_IRQ_EN)||(ES_INIT_GPIO_H_6_IRQ_EN) +#define ES_CONF_EXTI_IRQ_6 +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN)||(ES_INIT_GPIO_B_7_IRQ_EN)||(ES_INIT_GPIO_C_7_IRQ_EN)||(ES_INIT_GPIO_D_7_IRQ_EN)|| \ + (ES_INIT_GPIO_E_7_IRQ_EN)||(ES_INIT_GPIO_F_7_IRQ_EN)||(ES_INIT_GPIO_G_7_IRQ_EN)||(ES_INIT_GPIO_H_7_IRQ_EN) +#define ES_CONF_EXTI_IRQ_7 +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN)||(ES_INIT_GPIO_B_8_IRQ_EN)||(ES_INIT_GPIO_C_8_IRQ_EN)||(ES_INIT_GPIO_D_8_IRQ_EN)|| \ + (ES_INIT_GPIO_E_8_IRQ_EN)||(ES_INIT_GPIO_F_8_IRQ_EN)||(ES_INIT_GPIO_G_8_IRQ_EN)||(ES_INIT_GPIO_H_8_IRQ_EN) +#define ES_CONF_EXTI_IRQ_8 +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN)||(ES_INIT_GPIO_B_9_IRQ_EN)||(ES_INIT_GPIO_C_9_IRQ_EN)||(ES_INIT_GPIO_D_9_IRQ_EN)|| \ + (ES_INIT_GPIO_E_9_IRQ_EN)||(ES_INIT_GPIO_F_9_IRQ_EN)||(ES_INIT_GPIO_G_9_IRQ_EN)||(ES_INIT_GPIO_H_9_IRQ_EN) +#define ES_CONF_EXTI_IRQ_9 +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN)||(ES_INIT_GPIO_B_10_IRQ_EN)||(ES_INIT_GPIO_C_10_IRQ_EN)||(ES_INIT_GPIO_D_10_IRQ_EN)|| \ + (ES_INIT_GPIO_E_10_IRQ_EN)||(ES_INIT_GPIO_F_10_IRQ_EN)||(ES_INIT_GPIO_G_10_IRQ_EN)||(ES_INIT_GPIO_H_10_IRQ_EN) +#define ES_CONF_EXTI_IRQ_10 +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN)||(ES_INIT_GPIO_B_11_IRQ_EN)||(ES_INIT_GPIO_C_11_IRQ_EN)||(ES_INIT_GPIO_D_11_IRQ_EN)|| \ + (ES_INIT_GPIO_E_11_IRQ_EN)||(ES_INIT_GPIO_F_11_IRQ_EN)||(ES_INIT_GPIO_G_11_IRQ_EN)||(ES_INIT_GPIO_H_11_IRQ_EN) +#define ES_CONF_EXTI_IRQ_11 +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN)||(ES_INIT_GPIO_B_12_IRQ_EN)||(ES_INIT_GPIO_C_12_IRQ_EN)||(ES_INIT_GPIO_D_12_IRQ_EN)|| \ + (ES_INIT_GPIO_E_12_IRQ_EN)||(ES_INIT_GPIO_F_12_IRQ_EN)||(ES_INIT_GPIO_G_12_IRQ_EN)||(ES_INIT_GPIO_H_12_IRQ_EN) +#define ES_CONF_EXTI_IRQ_12 +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN)||(ES_INIT_GPIO_B_13_IRQ_EN)||(ES_INIT_GPIO_C_13_IRQ_EN)||(ES_INIT_GPIO_D_13_IRQ_EN)|| \ + (ES_INIT_GPIO_E_13_IRQ_EN)||(ES_INIT_GPIO_F_13_IRQ_EN)||(ES_INIT_GPIO_G_13_IRQ_EN)||(ES_INIT_GPIO_H_13_IRQ_EN) +#define ES_CONF_EXTI_IRQ_13 +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN)||(ES_INIT_GPIO_B_14_IRQ_EN)||(ES_INIT_GPIO_C_14_IRQ_EN)||(ES_INIT_GPIO_D_14_IRQ_EN)|| \ + (ES_INIT_GPIO_E_14_IRQ_EN)||(ES_INIT_GPIO_F_14_IRQ_EN)||(ES_INIT_GPIO_G_14_IRQ_EN)||(ES_INIT_GPIO_H_14_IRQ_EN) +#define ES_CONF_EXTI_IRQ_14 +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN)||(ES_INIT_GPIO_B_15_IRQ_EN)||(ES_INIT_GPIO_C_15_IRQ_EN)||(ES_INIT_GPIO_D_15_IRQ_EN)|| \ + (ES_INIT_GPIO_E_15_IRQ_EN)||(ES_INIT_GPIO_F_15_IRQ_EN)||(ES_INIT_GPIO_G_15_IRQ_EN)||(ES_INIT_GPIO_H_15_IRQ_EN) +#define ES_CONF_EXTI_IRQ_15 +#endif + +#endif //11111 + + +/*GPIO外部中断 声明*/ +#if 11111 + +#ifdef ES_CONF_EXTI_IRQ_0 +void irq_pin0_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 +void irq_pin1_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 +void irq_pin2_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 +void irq_pin3_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 +void irq_pin4_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 +void irq_pin5_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 +void irq_pin6_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 +void irq_pin7_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 +void irq_pin8_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 +void irq_pin9_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 +void irq_pin10_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 +void irq_pin11_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 +void irq_pin12_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 +void irq_pin13_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 +void irq_pin14_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 +void irq_pin15_callback(void* arg); +#endif + + +#endif //11111 + + + + +/*是否有配置的管脚*/ +#if defined(ES_INIT_PIN_GPIO_A_0) || defined(ES_INIT_PIN_GPIO_A_1) || defined(ES_INIT_PIN_GPIO_A_2) || defined(ES_INIT_PIN_GPIO_A_3) || \ + defined(ES_INIT_PIN_GPIO_A_4) || defined(ES_INIT_PIN_GPIO_A_5) || defined(ES_INIT_PIN_GPIO_A_6) || defined(ES_INIT_PIN_GPIO_A_7) || \ + defined(ES_INIT_PIN_GPIO_A_8) || defined(ES_INIT_PIN_GPIO_A_9) || defined(ES_INIT_PIN_GPIO_A_10) || defined(ES_INIT_PIN_GPIO_A_11) || \ + defined(ES_INIT_PIN_GPIO_A_12) || defined(ES_INIT_PIN_GPIO_A_13) || defined(ES_INIT_PIN_GPIO_A_14) || defined(ES_INIT_PIN_GPIO_A_15) || \ + defined(ES_INIT_PIN_GPIO_B_0) || defined(ES_INIT_PIN_GPIO_B_1) || defined(ES_INIT_PIN_GPIO_B_2) || defined(ES_INIT_PIN_GPIO_B_3) || \ + defined(ES_INIT_PIN_GPIO_B_4) || defined(ES_INIT_PIN_GPIO_B_5) || defined(ES_INIT_PIN_GPIO_B_6) || defined(ES_INIT_PIN_GPIO_B_7) || \ + defined(ES_INIT_PIN_GPIO_B_8) || defined(ES_INIT_PIN_GPIO_B_9) || defined(ES_INIT_PIN_GPIO_B_10) || defined(ES_INIT_PIN_GPIO_B_11) || \ + defined(ES_INIT_PIN_GPIO_B_12) || defined(ES_INIT_PIN_GPIO_B_13) || defined(ES_INIT_PIN_GPIO_B_14) || defined(ES_INIT_PIN_GPIO_B_15) || \ + defined(ES_INIT_PIN_GPIO_C_0) || defined(ES_INIT_PIN_GPIO_C_1) || defined(ES_INIT_PIN_GPIO_C_2) || defined(ES_INIT_PIN_GPIO_C_3) || \ + defined(ES_INIT_PIN_GPIO_C_4) || defined(ES_INIT_PIN_GPIO_C_5) || defined(ES_INIT_PIN_GPIO_C_6) || defined(ES_INIT_PIN_GPIO_C_7) || \ + defined(ES_INIT_PIN_GPIO_C_8) || defined(ES_INIT_PIN_GPIO_C_9) || defined(ES_INIT_PIN_GPIO_C_10) || defined(ES_INIT_PIN_GPIO_C_11) || \ + defined(ES_INIT_PIN_GPIO_C_12) || defined(ES_INIT_PIN_GPIO_C_13) || defined(ES_INIT_PIN_GPIO_C_14) || defined(ES_INIT_PIN_GPIO_C_15) || \ + defined(ES_INIT_PIN_GPIO_D_0) || defined(ES_INIT_PIN_GPIO_D_1) || defined(ES_INIT_PIN_GPIO_D_2) || defined(ES_INIT_PIN_GPIO_D_3) || \ + defined(ES_INIT_PIN_GPIO_D_4) || defined(ES_INIT_PIN_GPIO_D_5) || defined(ES_INIT_PIN_GPIO_D_6) || defined(ES_INIT_PIN_GPIO_D_7) || \ + defined(ES_INIT_PIN_GPIO_D_8) || defined(ES_INIT_PIN_GPIO_D_9) || defined(ES_INIT_PIN_GPIO_D_10) || defined(ES_INIT_PIN_GPIO_D_11) || \ + defined(ES_INIT_PIN_GPIO_D_12) || defined(ES_INIT_PIN_GPIO_D_13) || defined(ES_INIT_PIN_GPIO_D_14) || defined(ES_INIT_PIN_GPIO_D_15) || \ + defined(ES_INIT_PIN_GPIO_E_0) || defined(ES_INIT_PIN_GPIO_E_1) || defined(ES_INIT_PIN_GPIO_E_2) || defined(ES_INIT_PIN_GPIO_E_3) || \ + defined(ES_INIT_PIN_GPIO_E_4) || defined(ES_INIT_PIN_GPIO_E_5) || defined(ES_INIT_PIN_GPIO_E_6) || defined(ES_INIT_PIN_GPIO_E_7) || \ + defined(ES_INIT_PIN_GPIO_E_8) || defined(ES_INIT_PIN_GPIO_E_9) || defined(ES_INIT_PIN_GPIO_E_10) || defined(ES_INIT_PIN_GPIO_E_11) || \ + defined(ES_INIT_PIN_GPIO_E_12) || defined(ES_INIT_PIN_GPIO_E_13) || defined(ES_INIT_PIN_GPIO_E_14) || defined(ES_INIT_PIN_GPIO_E_15) || \ + defined(ES_INIT_PIN_GPIO_F_0) || defined(ES_INIT_PIN_GPIO_F_1) || defined(ES_INIT_PIN_GPIO_F_2) || defined(ES_INIT_PIN_GPIO_F_3) || \ + defined(ES_INIT_PIN_GPIO_F_4) || defined(ES_INIT_PIN_GPIO_F_5) || defined(ES_INIT_PIN_GPIO_F_6) || defined(ES_INIT_PIN_GPIO_F_7) || \ + defined(ES_INIT_PIN_GPIO_F_8) || defined(ES_INIT_PIN_GPIO_F_9) || defined(ES_INIT_PIN_GPIO_F_10) || defined(ES_INIT_PIN_GPIO_F_11) || \ + defined(ES_INIT_PIN_GPIO_F_12) || defined(ES_INIT_PIN_GPIO_F_13) || defined(ES_INIT_PIN_GPIO_F_14) || defined(ES_INIT_PIN_GPIO_F_15) || \ + defined(ES_INIT_PIN_GPIO_G_0) || defined(ES_INIT_PIN_GPIO_G_1) || defined(ES_INIT_PIN_GPIO_G_2) || defined(ES_INIT_PIN_GPIO_G_3) || \ + defined(ES_INIT_PIN_GPIO_G_4) || defined(ES_INIT_PIN_GPIO_G_5) || defined(ES_INIT_PIN_GPIO_G_6) || defined(ES_INIT_PIN_GPIO_G_7) || \ + defined(ES_INIT_PIN_GPIO_G_8) || defined(ES_INIT_PIN_GPIO_G_9) || defined(ES_INIT_PIN_GPIO_G_10) || defined(ES_INIT_PIN_GPIO_G_11) || \ + defined(ES_INIT_PIN_GPIO_G_12) || defined(ES_INIT_PIN_GPIO_G_13) || defined(ES_INIT_PIN_GPIO_G_14) || defined(ES_INIT_PIN_GPIO_G_15) || \ + defined(ES_INIT_PIN_GPIO_H_0) || defined(ES_INIT_PIN_GPIO_H_1) || defined(ES_INIT_PIN_GPIO_H_2) || defined(ES_INIT_PIN_GPIO_H_3) || \ + defined(ES_INIT_PIN_GPIO_H_4) || defined(ES_INIT_PIN_GPIO_H_5) || defined(ES_INIT_PIN_GPIO_H_6) || defined(ES_INIT_PIN_GPIO_H_7) || \ + defined(ES_INIT_PIN_GPIO_H_8) || defined(ES_INIT_PIN_GPIO_H_9) || defined(ES_INIT_PIN_GPIO_H_10) || defined(ES_INIT_PIN_GPIO_H_11) || \ + defined(ES_INIT_PIN_GPIO_H_12) || defined(ES_INIT_PIN_GPIO_H_13) || defined(ES_INIT_PIN_GPIO_H_14) || defined(ES_INIT_PIN_GPIO_H_15) + +#define ES_INIT_GPIOS + +#endif + + +#ifdef ES_INIT_GPIOS + +static gpio_conf_t gpio_conf_all[] = +{ + +#ifdef ES_INIT_PIN_GPIO_A_0 + + { + ES_PIN_GPIO_A_0 , + +#ifdef ES_INIT_GPIO_A_0_MODE + ES_INIT_GPIO_A_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_0_LEVEL + ES_INIT_GPIO_A_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_0_IRQ_MODE + ES_INIT_GPIO_A_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_1 + + { + ES_PIN_GPIO_A_1 , + +#ifdef ES_INIT_GPIO_A_1_MODE + ES_INIT_GPIO_A_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_1_LEVEL + ES_INIT_GPIO_A_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_1_IRQ_MODE + ES_INIT_GPIO_A_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_2 + + { + ES_PIN_GPIO_A_2 , + +#ifdef ES_INIT_GPIO_A_2_MODE + ES_INIT_GPIO_A_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_2_LEVEL + ES_INIT_GPIO_A_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_2_IRQ_MODE + ES_INIT_GPIO_A_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_3 + + { + ES_PIN_GPIO_A_3 , + +#ifdef ES_INIT_GPIO_A_3_MODE + ES_INIT_GPIO_A_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_3_LEVEL + ES_INIT_GPIO_A_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_3_IRQ_MODE + ES_INIT_GPIO_A_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_4 + + { + ES_PIN_GPIO_A_4 , + +#ifdef ES_INIT_GPIO_A_4_MODE + ES_INIT_GPIO_A_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_4_LEVEL + ES_INIT_GPIO_A_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_4_IRQ_MODE + ES_INIT_GPIO_A_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_5 + + { + ES_PIN_GPIO_A_5 , + +#ifdef ES_INIT_GPIO_A_5_MODE + ES_INIT_GPIO_A_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_5_LEVEL + ES_INIT_GPIO_A_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_5_IRQ_MODE + ES_INIT_GPIO_A_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_6 + + { + ES_PIN_GPIO_A_6 , + +#ifdef ES_INIT_GPIO_A_6_MODE + ES_INIT_GPIO_A_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_6_LEVEL + ES_INIT_GPIO_A_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_6_IRQ_MODE + ES_INIT_GPIO_A_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_7 + + { + ES_PIN_GPIO_A_7 , + +#ifdef ES_INIT_GPIO_A_7_MODE + ES_INIT_GPIO_A_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_7_LEVEL + ES_INIT_GPIO_A_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_7_IRQ_MODE + ES_INIT_GPIO_A_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_8 + + { + ES_PIN_GPIO_A_8 , + +#ifdef ES_INIT_GPIO_A_8_MODE + ES_INIT_GPIO_A_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_8_LEVEL + ES_INIT_GPIO_A_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_8_IRQ_MODE + ES_INIT_GPIO_A_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_9 + + { + ES_PIN_GPIO_A_9 , + +#ifdef ES_INIT_GPIO_A_9_MODE + ES_INIT_GPIO_A_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_9_LEVEL + ES_INIT_GPIO_A_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_9_IRQ_MODE + ES_INIT_GPIO_A_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_10 + + { + ES_PIN_GPIO_A_10 , + +#ifdef ES_INIT_GPIO_A_10_MODE + ES_INIT_GPIO_A_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_10_LEVEL + ES_INIT_GPIO_A_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_10_IRQ_MODE + ES_INIT_GPIO_A_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_11 + + { + ES_PIN_GPIO_A_11 , + +#ifdef ES_INIT_GPIO_A_11_MODE + ES_INIT_GPIO_A_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_11_LEVEL + ES_INIT_GPIO_A_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_11_IRQ_MODE + ES_INIT_GPIO_A_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_12 + + { + ES_PIN_GPIO_A_12 , + +#ifdef ES_INIT_GPIO_A_12_MODE + ES_INIT_GPIO_A_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_12_LEVEL + ES_INIT_GPIO_A_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_12_IRQ_MODE + ES_INIT_GPIO_A_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_13 + + { + ES_PIN_GPIO_A_13 , + +#ifdef ES_INIT_GPIO_A_13_MODE + ES_INIT_GPIO_A_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_13_LEVEL + ES_INIT_GPIO_A_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_13_IRQ_MODE + ES_INIT_GPIO_A_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_14 + + { + ES_PIN_GPIO_A_14 , + +#ifdef ES_INIT_GPIO_A_14_MODE + ES_INIT_GPIO_A_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_14_LEVEL + ES_INIT_GPIO_A_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_14_IRQ_MODE + ES_INIT_GPIO_A_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_15 + + { + ES_PIN_GPIO_A_15 , + +#ifdef ES_INIT_GPIO_A_15_MODE + ES_INIT_GPIO_A_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_15_LEVEL + ES_INIT_GPIO_A_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_15_IRQ_MODE + ES_INIT_GPIO_A_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_0 + + { + ES_PIN_GPIO_B_0 , + +#ifdef ES_INIT_GPIO_B_0_MODE + ES_INIT_GPIO_B_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_0_LEVEL + ES_INIT_GPIO_B_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_0_IRQ_MODE + ES_INIT_GPIO_B_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_1 + + { + ES_PIN_GPIO_B_1 , + +#ifdef ES_INIT_GPIO_B_1_MODE + ES_INIT_GPIO_B_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_1_LEVEL + ES_INIT_GPIO_B_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_1_IRQ_MODE + ES_INIT_GPIO_B_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_2 + + { + ES_PIN_GPIO_B_2 , + +#ifdef ES_INIT_GPIO_B_2_MODE + ES_INIT_GPIO_B_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_2_LEVEL + ES_INIT_GPIO_B_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_2_IRQ_MODE + ES_INIT_GPIO_B_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_3 + + { + ES_PIN_GPIO_B_3 , + +#ifdef ES_INIT_GPIO_B_3_MODE + ES_INIT_GPIO_B_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_3_LEVEL + ES_INIT_GPIO_B_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_3_IRQ_MODE + ES_INIT_GPIO_B_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_4 + + { + ES_PIN_GPIO_B_4 , + +#ifdef ES_INIT_GPIO_B_4_MODE + ES_INIT_GPIO_B_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_4_LEVEL + ES_INIT_GPIO_B_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_4_IRQ_MODE + ES_INIT_GPIO_B_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_5 + + { + ES_PIN_GPIO_B_5 , + +#ifdef ES_INIT_GPIO_B_5_MODE + ES_INIT_GPIO_B_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_5_LEVEL + ES_INIT_GPIO_B_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_5_IRQ_MODE + ES_INIT_GPIO_B_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_6 + + { + ES_PIN_GPIO_B_6 , + +#ifdef ES_INIT_GPIO_B_6_MODE + ES_INIT_GPIO_B_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_6_LEVEL + ES_INIT_GPIO_B_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_6_IRQ_MODE + ES_INIT_GPIO_B_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_7 + + { + ES_PIN_GPIO_B_7 , + +#ifdef ES_INIT_GPIO_B_7_MODE + ES_INIT_GPIO_B_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_7_LEVEL + ES_INIT_GPIO_B_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_7_IRQ_MODE + ES_INIT_GPIO_B_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_8 + + { + ES_PIN_GPIO_B_8 , + +#ifdef ES_INIT_GPIO_B_8_MODE + ES_INIT_GPIO_B_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_8_LEVEL + ES_INIT_GPIO_B_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_8_IRQ_MODE + ES_INIT_GPIO_B_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_9 + + { + ES_PIN_GPIO_B_9 , + +#ifdef ES_INIT_GPIO_B_9_MODE + ES_INIT_GPIO_B_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_9_LEVEL + ES_INIT_GPIO_B_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_9_IRQ_MODE + ES_INIT_GPIO_B_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_10 + + { + ES_PIN_GPIO_B_10 , + +#ifdef ES_INIT_GPIO_B_10_MODE + ES_INIT_GPIO_B_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_10_LEVEL + ES_INIT_GPIO_B_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_10_IRQ_MODE + ES_INIT_GPIO_B_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_11 + + { + ES_PIN_GPIO_B_11 , + +#ifdef ES_INIT_GPIO_B_11_MODE + ES_INIT_GPIO_B_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_11_LEVEL + ES_INIT_GPIO_B_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_11_IRQ_MODE + ES_INIT_GPIO_B_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_12 + + { + ES_PIN_GPIO_B_12 , + +#ifdef ES_INIT_GPIO_B_12_MODE + ES_INIT_GPIO_B_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_12_LEVEL + ES_INIT_GPIO_B_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_12_IRQ_MODE + ES_INIT_GPIO_B_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_13 + + { + ES_PIN_GPIO_B_13 , + +#ifdef ES_INIT_GPIO_B_13_MODE + ES_INIT_GPIO_B_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_13_LEVEL + ES_INIT_GPIO_B_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_13_IRQ_MODE + ES_INIT_GPIO_B_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_14 + + { + ES_PIN_GPIO_B_14 , + +#ifdef ES_INIT_GPIO_B_14_MODE + ES_INIT_GPIO_B_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_14_LEVEL + ES_INIT_GPIO_B_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_14_IRQ_MODE + ES_INIT_GPIO_B_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_15 + + { + ES_PIN_GPIO_B_15 , + +#ifdef ES_INIT_GPIO_B_15_MODE + ES_INIT_GPIO_B_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_15_LEVEL + ES_INIT_GPIO_B_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_15_IRQ_MODE + ES_INIT_GPIO_B_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_0 + + { + ES_PIN_GPIO_C_0 , + +#ifdef ES_INIT_GPIO_C_0_MODE + ES_INIT_GPIO_C_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_0_LEVEL + ES_INIT_GPIO_C_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_0_IRQ_MODE + ES_INIT_GPIO_C_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_1 + + { + ES_PIN_GPIO_C_1 , + +#ifdef ES_INIT_GPIO_C_1_MODE + ES_INIT_GPIO_C_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_1_LEVEL + ES_INIT_GPIO_C_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_1_IRQ_MODE + ES_INIT_GPIO_C_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_2 + + { + ES_PIN_GPIO_C_2 , + +#ifdef ES_INIT_GPIO_C_2_MODE + ES_INIT_GPIO_C_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_2_LEVEL + ES_INIT_GPIO_C_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_2_IRQ_MODE + ES_INIT_GPIO_C_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_3 + + { + ES_PIN_GPIO_C_3 , + +#ifdef ES_INIT_GPIO_C_3_MODE + ES_INIT_GPIO_C_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_3_LEVEL + ES_INIT_GPIO_C_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_3_IRQ_MODE + ES_INIT_GPIO_C_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_4 + + { + ES_PIN_GPIO_C_4 , + +#ifdef ES_INIT_GPIO_C_4_MODE + ES_INIT_GPIO_C_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_4_LEVEL + ES_INIT_GPIO_C_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_4_IRQ_MODE + ES_INIT_GPIO_C_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_5 + + { + ES_PIN_GPIO_C_5 , + +#ifdef ES_INIT_GPIO_C_5_MODE + ES_INIT_GPIO_C_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_5_LEVEL + ES_INIT_GPIO_C_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_5_IRQ_MODE + ES_INIT_GPIO_C_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_6 + + { + ES_PIN_GPIO_C_6 , + +#ifdef ES_INIT_GPIO_C_6_MODE + ES_INIT_GPIO_C_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_6_LEVEL + ES_INIT_GPIO_C_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_6_IRQ_MODE + ES_INIT_GPIO_C_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_7 + + { + ES_PIN_GPIO_C_7 , + +#ifdef ES_INIT_GPIO_C_7_MODE + ES_INIT_GPIO_C_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_7_LEVEL + ES_INIT_GPIO_C_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_7_IRQ_MODE + ES_INIT_GPIO_C_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_8 + + { + ES_PIN_GPIO_C_8 , + +#ifdef ES_INIT_GPIO_C_8_MODE + ES_INIT_GPIO_C_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_8_LEVEL + ES_INIT_GPIO_C_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_8_IRQ_MODE + ES_INIT_GPIO_C_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_9 + + { + ES_PIN_GPIO_C_9 , + +#ifdef ES_INIT_GPIO_C_9_MODE + ES_INIT_GPIO_C_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_9_LEVEL + ES_INIT_GPIO_C_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_9_IRQ_MODE + ES_INIT_GPIO_C_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_10 + + { + ES_PIN_GPIO_C_10 , + +#ifdef ES_INIT_GPIO_C_10_MODE + ES_INIT_GPIO_C_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_10_LEVEL + ES_INIT_GPIO_C_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_10_IRQ_MODE + ES_INIT_GPIO_C_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_11 + + { + ES_PIN_GPIO_C_11 , + +#ifdef ES_INIT_GPIO_C_11_MODE + ES_INIT_GPIO_C_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_11_LEVEL + ES_INIT_GPIO_C_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_11_IRQ_MODE + ES_INIT_GPIO_C_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_12 + + { + ES_PIN_GPIO_C_12 , + +#ifdef ES_INIT_GPIO_C_12_MODE + ES_INIT_GPIO_C_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_12_LEVEL + ES_INIT_GPIO_C_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_12_IRQ_MODE + ES_INIT_GPIO_C_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_13 + + { + ES_PIN_GPIO_C_13 , + +#ifdef ES_INIT_GPIO_C_13_MODE + ES_INIT_GPIO_C_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_13_LEVEL + ES_INIT_GPIO_C_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_13_IRQ_MODE + ES_INIT_GPIO_C_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_14 + + { + ES_PIN_GPIO_C_14 , + +#ifdef ES_INIT_GPIO_C_14_MODE + ES_INIT_GPIO_C_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_14_LEVEL + ES_INIT_GPIO_C_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_14_IRQ_MODE + ES_INIT_GPIO_C_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_15 + + { + ES_PIN_GPIO_C_15 , + +#ifdef ES_INIT_GPIO_C_15_MODE + ES_INIT_GPIO_C_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_15_LEVEL + ES_INIT_GPIO_C_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_15_IRQ_MODE + ES_INIT_GPIO_C_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_0 + + { + ES_PIN_GPIO_D_0 , + +#ifdef ES_INIT_GPIO_D_0_MODE + ES_INIT_GPIO_D_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_0_LEVEL + ES_INIT_GPIO_D_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_0_IRQ_MODE + ES_INIT_GPIO_D_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_1 + + { + ES_PIN_GPIO_D_1 , + +#ifdef ES_INIT_GPIO_D_1_MODE + ES_INIT_GPIO_D_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_1_LEVEL + ES_INIT_GPIO_D_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_1_IRQ_MODE + ES_INIT_GPIO_D_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_2 + + { + ES_PIN_GPIO_D_2 , + +#ifdef ES_INIT_GPIO_D_2_MODE + ES_INIT_GPIO_D_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_2_LEVEL + ES_INIT_GPIO_D_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_2_IRQ_MODE + ES_INIT_GPIO_D_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_3 + + { + ES_PIN_GPIO_D_3 , + +#ifdef ES_INIT_GPIO_D_3_MODE + ES_INIT_GPIO_D_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_3_LEVEL + ES_INIT_GPIO_D_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_3_IRQ_MODE + ES_INIT_GPIO_D_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_4 + + { + ES_PIN_GPIO_D_4 , + +#ifdef ES_INIT_GPIO_D_4_MODE + ES_INIT_GPIO_D_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_4_LEVEL + ES_INIT_GPIO_D_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_4_IRQ_MODE + ES_INIT_GPIO_D_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_5 + + { + ES_PIN_GPIO_D_5 , + +#ifdef ES_INIT_GPIO_D_5_MODE + ES_INIT_GPIO_D_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_5_LEVEL + ES_INIT_GPIO_D_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_5_IRQ_MODE + ES_INIT_GPIO_D_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_6 + + { + ES_PIN_GPIO_D_6 , + +#ifdef ES_INIT_GPIO_D_6_MODE + ES_INIT_GPIO_D_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_6_LEVEL + ES_INIT_GPIO_D_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_6_IRQ_MODE + ES_INIT_GPIO_D_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_7 + + { + ES_PIN_GPIO_D_7 , + +#ifdef ES_INIT_GPIO_D_7_MODE + ES_INIT_GPIO_D_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_7_LEVEL + ES_INIT_GPIO_D_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_7_IRQ_MODE + ES_INIT_GPIO_D_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_8 + + { + ES_PIN_GPIO_D_8 , + +#ifdef ES_INIT_GPIO_D_8_MODE + ES_INIT_GPIO_D_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_8_LEVEL + ES_INIT_GPIO_D_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_8_IRQ_MODE + ES_INIT_GPIO_D_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_9 + + { + ES_PIN_GPIO_D_9 , + +#ifdef ES_INIT_GPIO_D_9_MODE + ES_INIT_GPIO_D_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_9_LEVEL + ES_INIT_GPIO_D_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_9_IRQ_MODE + ES_INIT_GPIO_D_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_10 + + { + ES_PIN_GPIO_D_10 , + +#ifdef ES_INIT_GPIO_D_10_MODE + ES_INIT_GPIO_D_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_10_LEVEL + ES_INIT_GPIO_D_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_10_IRQ_MODE + ES_INIT_GPIO_D_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_11 + + { + ES_PIN_GPIO_D_11 , + +#ifdef ES_INIT_GPIO_D_11_MODE + ES_INIT_GPIO_D_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_11_LEVEL + ES_INIT_GPIO_D_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_11_IRQ_MODE + ES_INIT_GPIO_D_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_12 + + { + ES_PIN_GPIO_D_12 , + +#ifdef ES_INIT_GPIO_D_12_MODE + ES_INIT_GPIO_D_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_12_LEVEL + ES_INIT_GPIO_D_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_12_IRQ_MODE + ES_INIT_GPIO_D_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_13 + + { + ES_PIN_GPIO_D_13 , + +#ifdef ES_INIT_GPIO_D_13_MODE + ES_INIT_GPIO_D_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_13_LEVEL + ES_INIT_GPIO_D_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_13_IRQ_MODE + ES_INIT_GPIO_D_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_14 + + { + ES_PIN_GPIO_D_14 , + +#ifdef ES_INIT_GPIO_D_14_MODE + ES_INIT_GPIO_D_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_14_LEVEL + ES_INIT_GPIO_D_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_14_IRQ_MODE + ES_INIT_GPIO_D_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_15 + + { + ES_PIN_GPIO_D_15 , + +#ifdef ES_INIT_GPIO_D_15_MODE + ES_INIT_GPIO_D_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_15_LEVEL + ES_INIT_GPIO_D_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_15_IRQ_MODE + ES_INIT_GPIO_D_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_0 + + { + ES_PIN_GPIO_E_0 , + +#ifdef ES_INIT_GPIO_E_0_MODE + ES_INIT_GPIO_E_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_0_LEVEL + ES_INIT_GPIO_E_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_0_IRQ_MODE + ES_INIT_GPIO_E_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_1 + + { + ES_PIN_GPIO_E_1 , + +#ifdef ES_INIT_GPIO_E_1_MODE + ES_INIT_GPIO_E_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_1_LEVEL + ES_INIT_GPIO_E_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_1_IRQ_MODE + ES_INIT_GPIO_E_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_2 + + { + ES_PIN_GPIO_E_2 , + +#ifdef ES_INIT_GPIO_E_2_MODE + ES_INIT_GPIO_E_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_2_LEVEL + ES_INIT_GPIO_E_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_2_IRQ_MODE + ES_INIT_GPIO_E_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_3 + + { + ES_PIN_GPIO_E_3 , + +#ifdef ES_INIT_GPIO_E_3_MODE + ES_INIT_GPIO_E_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_3_LEVEL + ES_INIT_GPIO_E_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_3_IRQ_MODE + ES_INIT_GPIO_E_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_4 + + { + ES_PIN_GPIO_E_4 , + +#ifdef ES_INIT_GPIO_E_4_MODE + ES_INIT_GPIO_E_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_4_LEVEL + ES_INIT_GPIO_E_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_4_IRQ_MODE + ES_INIT_GPIO_E_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_5 + + { + ES_PIN_GPIO_E_5 , + +#ifdef ES_INIT_GPIO_E_5_MODE + ES_INIT_GPIO_E_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_5_LEVEL + ES_INIT_GPIO_E_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_5_IRQ_MODE + ES_INIT_GPIO_E_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_6 + + { + ES_PIN_GPIO_E_6 , + +#ifdef ES_INIT_GPIO_E_6_MODE + ES_INIT_GPIO_E_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_6_LEVEL + ES_INIT_GPIO_E_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_6_IRQ_MODE + ES_INIT_GPIO_E_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_7 + + { + ES_PIN_GPIO_E_7 , + +#ifdef ES_INIT_GPIO_E_7_MODE + ES_INIT_GPIO_E_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_7_LEVEL + ES_INIT_GPIO_E_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_7_IRQ_MODE + ES_INIT_GPIO_E_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_8 + + { + ES_PIN_GPIO_E_8 , + +#ifdef ES_INIT_GPIO_E_8_MODE + ES_INIT_GPIO_E_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_8_LEVEL + ES_INIT_GPIO_E_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_8_IRQ_MODE + ES_INIT_GPIO_E_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_9 + + { + ES_PIN_GPIO_E_9 , + +#ifdef ES_INIT_GPIO_E_9_MODE + ES_INIT_GPIO_E_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_9_LEVEL + ES_INIT_GPIO_E_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_9_IRQ_MODE + ES_INIT_GPIO_E_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_10 + + { + ES_PIN_GPIO_E_10 , + +#ifdef ES_INIT_GPIO_E_10_MODE + ES_INIT_GPIO_E_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_10_LEVEL + ES_INIT_GPIO_E_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_10_IRQ_MODE + ES_INIT_GPIO_E_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_11 + + { + ES_PIN_GPIO_E_11 , + +#ifdef ES_INIT_GPIO_E_11_MODE + ES_INIT_GPIO_E_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_11_LEVEL + ES_INIT_GPIO_E_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_11_IRQ_MODE + ES_INIT_GPIO_E_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_12 + + { + ES_PIN_GPIO_E_12 , + +#ifdef ES_INIT_GPIO_E_12_MODE + ES_INIT_GPIO_E_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_12_LEVEL + ES_INIT_GPIO_E_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_12_IRQ_MODE + ES_INIT_GPIO_E_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_13 + + { + ES_PIN_GPIO_E_13 , + +#ifdef ES_INIT_GPIO_E_13_MODE + ES_INIT_GPIO_E_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_13_LEVEL + ES_INIT_GPIO_E_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_13_IRQ_MODE + ES_INIT_GPIO_E_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_14 + + { + ES_PIN_GPIO_E_14 , + +#ifdef ES_INIT_GPIO_E_14_MODE + ES_INIT_GPIO_E_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_14_LEVEL + ES_INIT_GPIO_E_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_14_IRQ_MODE + ES_INIT_GPIO_E_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_15 + + { + ES_PIN_GPIO_E_15 , + +#ifdef ES_INIT_GPIO_E_15_MODE + ES_INIT_GPIO_E_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_15_LEVEL + ES_INIT_GPIO_E_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_15_IRQ_MODE + ES_INIT_GPIO_E_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_0 + + { + ES_PIN_GPIO_F_0 , + +#ifdef ES_INIT_GPIO_F_0_MODE + ES_INIT_GPIO_F_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_0_LEVEL + ES_INIT_GPIO_F_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_0_IRQ_MODE + ES_INIT_GPIO_F_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_1 + + { + ES_PIN_GPIO_F_1 , + +#ifdef ES_INIT_GPIO_F_1_MODE + ES_INIT_GPIO_F_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_1_LEVEL + ES_INIT_GPIO_F_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_1_IRQ_MODE + ES_INIT_GPIO_F_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_2 + + { + ES_PIN_GPIO_F_2 , + +#ifdef ES_INIT_GPIO_F_2_MODE + ES_INIT_GPIO_F_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_2_LEVEL + ES_INIT_GPIO_F_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_2_IRQ_MODE + ES_INIT_GPIO_F_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_3 + + { + ES_PIN_GPIO_F_3 , + +#ifdef ES_INIT_GPIO_F_3_MODE + ES_INIT_GPIO_F_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_3_LEVEL + ES_INIT_GPIO_F_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_3_IRQ_MODE + ES_INIT_GPIO_F_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_4 + + { + ES_PIN_GPIO_F_4 , + +#ifdef ES_INIT_GPIO_F_4_MODE + ES_INIT_GPIO_F_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_4_LEVEL + ES_INIT_GPIO_F_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_4_IRQ_MODE + ES_INIT_GPIO_F_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_5 + + { + ES_PIN_GPIO_F_5 , + +#ifdef ES_INIT_GPIO_F_5_MODE + ES_INIT_GPIO_F_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_5_LEVEL + ES_INIT_GPIO_F_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_5_IRQ_MODE + ES_INIT_GPIO_F_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_6 + + { + ES_PIN_GPIO_F_6 , + +#ifdef ES_INIT_GPIO_F_6_MODE + ES_INIT_GPIO_F_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_6_LEVEL + ES_INIT_GPIO_F_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_6_IRQ_MODE + ES_INIT_GPIO_F_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_7 + + { + ES_PIN_GPIO_F_7 , + +#ifdef ES_INIT_GPIO_F_7_MODE + ES_INIT_GPIO_F_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_7_LEVEL + ES_INIT_GPIO_F_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_7_IRQ_MODE + ES_INIT_GPIO_F_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_8 + + { + ES_PIN_GPIO_F_8 , + +#ifdef ES_INIT_GPIO_F_8_MODE + ES_INIT_GPIO_F_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_8_LEVEL + ES_INIT_GPIO_F_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_8_IRQ_MODE + ES_INIT_GPIO_F_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_9 + + { + ES_PIN_GPIO_F_9 , + +#ifdef ES_INIT_GPIO_F_9_MODE + ES_INIT_GPIO_F_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_9_LEVEL + ES_INIT_GPIO_F_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_9_IRQ_MODE + ES_INIT_GPIO_F_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_10 + + { + ES_PIN_GPIO_F_10 , + +#ifdef ES_INIT_GPIO_F_10_MODE + ES_INIT_GPIO_F_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_10_LEVEL + ES_INIT_GPIO_F_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_10_IRQ_MODE + ES_INIT_GPIO_F_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_11 + + { + ES_PIN_GPIO_F_11 , + +#ifdef ES_INIT_GPIO_F_11_MODE + ES_INIT_GPIO_F_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_11_LEVEL + ES_INIT_GPIO_F_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_11_IRQ_MODE + ES_INIT_GPIO_F_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_12 + + { + ES_PIN_GPIO_F_12 , + +#ifdef ES_INIT_GPIO_F_12_MODE + ES_INIT_GPIO_F_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_12_LEVEL + ES_INIT_GPIO_F_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_12_IRQ_MODE + ES_INIT_GPIO_F_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_13 + + { + ES_PIN_GPIO_F_13 , + +#ifdef ES_INIT_GPIO_F_13_MODE + ES_INIT_GPIO_F_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_13_LEVEL + ES_INIT_GPIO_F_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_13_IRQ_MODE + ES_INIT_GPIO_F_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_14 + + { + ES_PIN_GPIO_F_14 , + +#ifdef ES_INIT_GPIO_F_14_MODE + ES_INIT_GPIO_F_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_14_LEVEL + ES_INIT_GPIO_F_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_14_IRQ_MODE + ES_INIT_GPIO_F_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_15 + + { + ES_PIN_GPIO_F_15 , + +#ifdef ES_INIT_GPIO_F_15_MODE + ES_INIT_GPIO_F_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_15_LEVEL + ES_INIT_GPIO_F_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_15_IRQ_MODE + ES_INIT_GPIO_F_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_0 + + { + ES_PIN_GPIO_G_0 , + +#ifdef ES_INIT_GPIO_G_0_MODE + ES_INIT_GPIO_G_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_0_LEVEL + ES_INIT_GPIO_G_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_0_IRQ_MODE + ES_INIT_GPIO_G_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_1 + + { + ES_PIN_GPIO_G_1 , + +#ifdef ES_INIT_GPIO_G_1_MODE + ES_INIT_GPIO_G_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_1_LEVEL + ES_INIT_GPIO_G_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_1_IRQ_MODE + ES_INIT_GPIO_G_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_2 + + { + ES_PIN_GPIO_G_2 , + +#ifdef ES_INIT_GPIO_G_2_MODE + ES_INIT_GPIO_G_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_2_LEVEL + ES_INIT_GPIO_G_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_2_IRQ_MODE + ES_INIT_GPIO_G_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_3 + + { + ES_PIN_GPIO_G_3 , + +#ifdef ES_INIT_GPIO_G_3_MODE + ES_INIT_GPIO_G_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_3_LEVEL + ES_INIT_GPIO_G_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_3_IRQ_MODE + ES_INIT_GPIO_G_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_4 + + { + ES_PIN_GPIO_G_4 , + +#ifdef ES_INIT_GPIO_G_4_MODE + ES_INIT_GPIO_G_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_4_LEVEL + ES_INIT_GPIO_G_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_4_IRQ_MODE + ES_INIT_GPIO_G_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_5 + + { + ES_PIN_GPIO_G_5 , + +#ifdef ES_INIT_GPIO_G_5_MODE + ES_INIT_GPIO_G_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_5_LEVEL + ES_INIT_GPIO_G_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_5_IRQ_MODE + ES_INIT_GPIO_G_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_6 + + { + ES_PIN_GPIO_G_6 , + +#ifdef ES_INIT_GPIO_G_6_MODE + ES_INIT_GPIO_G_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_6_LEVEL + ES_INIT_GPIO_G_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_6_IRQ_MODE + ES_INIT_GPIO_G_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_7 + + { + ES_PIN_GPIO_G_7 , + +#ifdef ES_INIT_GPIO_G_7_MODE + ES_INIT_GPIO_G_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_7_LEVEL + ES_INIT_GPIO_G_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_7_IRQ_MODE + ES_INIT_GPIO_G_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_8 + + { + ES_PIN_GPIO_G_8 , + +#ifdef ES_INIT_GPIO_G_8_MODE + ES_INIT_GPIO_G_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_8_LEVEL + ES_INIT_GPIO_G_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_8_IRQ_MODE + ES_INIT_GPIO_G_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_9 + + { + ES_PIN_GPIO_G_9 , + +#ifdef ES_INIT_GPIO_G_9_MODE + ES_INIT_GPIO_G_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_9_LEVEL + ES_INIT_GPIO_G_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_9_IRQ_MODE + ES_INIT_GPIO_G_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_10 + + { + ES_PIN_GPIO_G_10 , + +#ifdef ES_INIT_GPIO_G_10_MODE + ES_INIT_GPIO_G_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_10_LEVEL + ES_INIT_GPIO_G_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_10_IRQ_MODE + ES_INIT_GPIO_G_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_11 + + { + ES_PIN_GPIO_G_11 , + +#ifdef ES_INIT_GPIO_G_11_MODE + ES_INIT_GPIO_G_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_11_LEVEL + ES_INIT_GPIO_G_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_11_IRQ_MODE + ES_INIT_GPIO_G_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_12 + + { + ES_PIN_GPIO_G_12 , + +#ifdef ES_INIT_GPIO_G_12_MODE + ES_INIT_GPIO_G_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_12_LEVEL + ES_INIT_GPIO_G_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_12_IRQ_MODE + ES_INIT_GPIO_G_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_13 + + { + ES_PIN_GPIO_G_13 , + +#ifdef ES_INIT_GPIO_G_13_MODE + ES_INIT_GPIO_G_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_13_LEVEL + ES_INIT_GPIO_G_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_13_IRQ_MODE + ES_INIT_GPIO_G_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_14 + + { + ES_PIN_GPIO_G_14 , + +#ifdef ES_INIT_GPIO_G_14_MODE + ES_INIT_GPIO_G_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_14_LEVEL + ES_INIT_GPIO_G_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_14_IRQ_MODE + ES_INIT_GPIO_G_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_15 + + { + ES_PIN_GPIO_G_15 , + +#ifdef ES_INIT_GPIO_G_15_MODE + ES_INIT_GPIO_G_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_15_LEVEL + ES_INIT_GPIO_G_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_15_IRQ_MODE + ES_INIT_GPIO_G_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_0 + + { + ES_PIN_GPIO_H_0 , + +#ifdef ES_INIT_GPIO_H_0_MODE + ES_INIT_GPIO_H_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_0_LEVEL + ES_INIT_GPIO_H_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_0_IRQ_MODE + ES_INIT_GPIO_H_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_1 + + { + ES_PIN_GPIO_H_1 , + +#ifdef ES_INIT_GPIO_H_1_MODE + ES_INIT_GPIO_H_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_1_LEVEL + ES_INIT_GPIO_H_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_1_IRQ_MODE + ES_INIT_GPIO_H_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_2 + + { + ES_PIN_GPIO_H_2 , + +#ifdef ES_INIT_GPIO_H_2_MODE + ES_INIT_GPIO_H_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_2_LEVEL + ES_INIT_GPIO_H_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_2_IRQ_MODE + ES_INIT_GPIO_H_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_3 + + { + ES_PIN_GPIO_H_3 , + +#ifdef ES_INIT_GPIO_H_3_MODE + ES_INIT_GPIO_H_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_3_LEVEL + ES_INIT_GPIO_H_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_3_IRQ_MODE + ES_INIT_GPIO_H_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_4 + + { + ES_PIN_GPIO_H_4 , + +#ifdef ES_INIT_GPIO_H_4_MODE + ES_INIT_GPIO_H_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_4_LEVEL + ES_INIT_GPIO_H_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_4_IRQ_MODE + ES_INIT_GPIO_H_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_5 + + { + ES_PIN_GPIO_H_5 , + +#ifdef ES_INIT_GPIO_H_5_MODE + ES_INIT_GPIO_H_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_5_LEVEL + ES_INIT_GPIO_H_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_5_IRQ_MODE + ES_INIT_GPIO_H_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_6 + + { + ES_PIN_GPIO_H_6 , + +#ifdef ES_INIT_GPIO_H_6_MODE + ES_INIT_GPIO_H_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_6_LEVEL + ES_INIT_GPIO_H_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_6_IRQ_MODE + ES_INIT_GPIO_H_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_7 + + { + ES_PIN_GPIO_H_7 , + +#ifdef ES_INIT_GPIO_H_7_MODE + ES_INIT_GPIO_H_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_7_LEVEL + ES_INIT_GPIO_H_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_7_IRQ_MODE + ES_INIT_GPIO_H_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_8 + + { + ES_PIN_GPIO_H_8 , + +#ifdef ES_INIT_GPIO_H_8_MODE + ES_INIT_GPIO_H_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_8_LEVEL + ES_INIT_GPIO_H_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_8_IRQ_MODE + ES_INIT_GPIO_H_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_9 + + { + ES_PIN_GPIO_H_9 , + +#ifdef ES_INIT_GPIO_H_9_MODE + ES_INIT_GPIO_H_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_9_LEVEL + ES_INIT_GPIO_H_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_9_IRQ_MODE + ES_INIT_GPIO_H_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_10 + + { + ES_PIN_GPIO_H_10 , + +#ifdef ES_INIT_GPIO_H_10_MODE + ES_INIT_GPIO_H_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_10_LEVEL + ES_INIT_GPIO_H_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_10_IRQ_MODE + ES_INIT_GPIO_H_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_11 + + { + ES_PIN_GPIO_H_11 , + +#ifdef ES_INIT_GPIO_H_11_MODE + ES_INIT_GPIO_H_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_11_LEVEL + ES_INIT_GPIO_H_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_11_IRQ_MODE + ES_INIT_GPIO_H_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_12 + + { + ES_PIN_GPIO_H_12 , + +#ifdef ES_INIT_GPIO_H_12_MODE + ES_INIT_GPIO_H_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_12_LEVEL + ES_INIT_GPIO_H_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_12_IRQ_MODE + ES_INIT_GPIO_H_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_13 + + { + ES_PIN_GPIO_H_13 , + +#ifdef ES_INIT_GPIO_H_13_MODE + ES_INIT_GPIO_H_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_13_LEVEL + ES_INIT_GPIO_H_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_13_IRQ_MODE + ES_INIT_GPIO_H_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_14 + + { + ES_PIN_GPIO_H_14 , + +#ifdef ES_INIT_GPIO_H_14_MODE + ES_INIT_GPIO_H_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_14_LEVEL + ES_INIT_GPIO_H_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_14_IRQ_MODE + ES_INIT_GPIO_H_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_15 + + { + ES_PIN_GPIO_H_15 , + +#ifdef ES_INIT_GPIO_H_15_MODE + ES_INIT_GPIO_H_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_15_LEVEL + ES_INIT_GPIO_H_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_15_IRQ_MODE + ES_INIT_GPIO_H_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + + + +}; + +#endif + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h new file mode 100644 index 0000000000..f71afb3b95 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h @@ -0,0 +1,102 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_HWTIMER_H__ +#define __ES_CONF_INFO_HWTIMER_H__ + +#include +#include + +#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP +#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW + +/* HWTIMER 配置 */ + +/* codes_main */ + + + +#ifndef ES_AD16C4T0_HWTIMER_MODE +#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_AD16C4T1_HWTIMER_MODE +#define ES_AD16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP32C4T0_HWTIMER_MODE +#define ES_GP32C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP32C4T1_HWTIMER_MODE +#define ES_GP32C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T0_HWTIMER_MODE +#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T1_HWTIMER_MODE +#define ES_GP16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T0_HWTIMER_MODE +#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T1_HWTIMER_MODE +#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + + + + +#define ES_AD16C4T0_HWTIMER_PRES 1 +#define ES_AD16C4T1_HWTIMER_PRES 1 +#define ES_GP16C4T0_HWTIMER_PRES 1 +#define ES_GP16C4T1_HWTIMER_PRES 1 +#define ES_GP32C4T0_HWTIMER_PRES 1 +#define ES_GP32C4T1_HWTIMER_PRES 1 +#define ES_BS16T0_HWTIMER_PRES 1 +#define ES_BS16T1_HWTIMER_PRES 1 + +#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER +#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#endif +#ifndef ES_DEVICE_NAME_AD16C4T1_HWTIMER +#define ES_DEVICE_NAME_AD16C4T1_HWTIMER "timer1" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T0_HWTIMER +#define ES_DEVICE_NAME_GP32C4T0_HWTIMER "timer2" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T1_HWTIMER +#define ES_DEVICE_NAME_GP32C4T1_HWTIMER "timer3" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER +#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer4" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T1_HWTIMER +#define ES_DEVICE_NAME_GP16C4T1_HWTIMER "timer5" +#endif +#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER +#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer6" +#endif +#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER +#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer7" +#endif + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h new file mode 100644 index 0000000000..65310fce01 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h @@ -0,0 +1,95 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_I2C_H__ +#define __ES_CONF_INFO_I2C_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +#define ES_C_I2C_STRETCH I2C_NOSTRETCH_DISABLE +#define ES_C_I2C_NO_STRETCH I2C_NOSTRETCH_ENABLE + +#define ES_C_I2C_GENERALCALL I2C_GENERALCALL_ENABLE +#define ES_C_I2C_NO_GENERALCALL I2C_GENERALCALL_DISABLE + + +#define ES_C_I2C_ADDR_7_MODE I2C_ADDR_7BIT +#define ES_C_I2C_ADDR_10_MODE I2C_ADDR_10BIT + + +/* I2C 配置 */ + + + +/* codes_main */ + + + + + +#ifndef ES_DEVICE_NAME_I2C0 +#define ES_DEVICE_NAME_I2C0 "i2c0" +#endif + +#ifndef ES_DEVICE_NAME_I2C1 +#define ES_DEVICE_NAME_I2C1 "i2c1" +#endif + +#ifndef ES_I2C0_CLK_SPEED +#define ES_I2C0_CLK_SPEED 100000 +#endif +#ifndef ES_I2C0_OWN_ADDR1 +#define ES_I2C0_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C0_GENERAL_CALL +#define ES_I2C0_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C0_STRETCH +#define ES_I2C0_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C0_ADDR_MODE +#define ES_I2C0_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + +#ifndef ES_I2C1_CLK_SPEED +#define ES_I2C1_CLK_SPEED 100000 +#endif +#ifndef ES_I2C1_OWN_ADDR1 +#define ES_I2C1_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C1_GENERAL_CALL +#define ES_I2C1_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C1_STRETCH +#define ES_I2C1_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C1_ADDR_MODE +#define ES_I2C1_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h new file mode 100644 index 0000000000..f25123227b --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h @@ -0,0 +1,2876 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __es_conf_info_map_H__ +#define __es_conf_info_map_H__ + +#include + + + +#define __ES_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} +#define __ES_PIN_DEFAULT {-1, 0, 0} + +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + + +#define ES_GPIO_ADC_CH0_GPIO GPIOC +#define ES_GPIO_ADC_CH1_GPIO GPIOC +#define ES_GPIO_ADC_CH2_GPIO GPIOC +#define ES_GPIO_ADC_CH3_GPIO GPIOC +#define ES_GPIO_ADC_CH4_GPIO GPIOA +#define ES_GPIO_ADC_CH5_GPIO GPIOA +#define ES_GPIO_ADC_CH6_GPIO GPIOA +#define ES_GPIO_ADC_CH7_GPIO GPIOA +#define ES_GPIO_ADC_CH8_GPIO GPIOA +#define ES_GPIO_ADC_CH9_GPIO GPIOA +#define ES_GPIO_ADC_CH10_GPIO GPIOA +#define ES_GPIO_ADC_CH11_GPIO GPIOA +#define ES_GPIO_ADC_CH12_GPIO GPIOC +#define ES_GPIO_ADC_CH13_GPIO GPIOC +#define ES_GPIO_ADC_CH14_GPIO GPIOB +#define ES_GPIO_ADC_CH15_GPIO GPIOB + +#define ES_GPIO_ADC_CH0_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH1_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH2_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH3_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH4_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH5_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH6_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH7_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH8_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH9_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH10_PIN GPIO_PIN_6 +#define ES_GPIO_ADC_CH11_PIN GPIO_PIN_7 +#define ES_GPIO_ADC_CH12_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH13_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH14_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH15_PIN GPIO_PIN_1 + + + +static const struct pin_index pins[] = +{ + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(2, C, 13), + __ES_PIN(3, C, 14), + __ES_PIN(4, C, 15), + __ES_PIN(5, H, 0), + __ES_PIN(6, H, 1), + __ES_PIN_DEFAULT, + __ES_PIN(8, C, 0), + __ES_PIN(9, C, 1), + __ES_PIN(10, C, 2), + __ES_PIN(11, C, 3), + __ES_PIN(12, H, 3), + __ES_PIN(13, H, 4), + __ES_PIN(14, A, 0), + __ES_PIN(15, A, 1), + __ES_PIN(16, A, 2), + __ES_PIN(17, A, 3), + __ES_PIN(18, F, 0), + __ES_PIN(19, F, 1), + __ES_PIN(20, A, 4), + __ES_PIN(21, A, 5), + __ES_PIN(22, A, 6), + __ES_PIN(23, A, 7), + __ES_PIN(24, C, 4), + __ES_PIN(25, C, 5), + __ES_PIN(26, B, 0), + __ES_PIN(27, B, 1), + __ES_PIN(28, B, 2), + __ES_PIN(29, B, 10), + __ES_PIN(30, B, 11), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(33, B, 12), + __ES_PIN(34, B, 13), + __ES_PIN(35, B, 14), + __ES_PIN(36, B, 15), + __ES_PIN(37, C, 6), + __ES_PIN(38, C, 7), + __ES_PIN(39, C, 8), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(46, A, 13), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(49, A, 14), + __ES_PIN(50, A, 15), + __ES_PIN(51, C, 10), + __ES_PIN(52, C, 11), + __ES_PIN(53, C, 12), + __ES_PIN(54, D, 2), + __ES_PIN(55, B, 3), + __ES_PIN(56, B, 4), + __ES_PIN(57, B, 5), + __ES_PIN(58, B, 6), + __ES_PIN(59, B, 7), + __ES_PIN(60, H, 2), + __ES_PIN(61, B, 8), + __ES_PIN(62, B, 9), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, +}; + +#define ES_PIN_GPIO_C_13 2 +#define ES_PIN_GPIO_C_14 3 +#define ES_PIN_GPIO_C_15 4 +#define ES_PIN_GPIO_H_0 5 +#define ES_PIN_GPIO_H_1 6 +#define ES_PIN_GPIO_C_0 8 +#define ES_PIN_GPIO_C_1 9 +#define ES_PIN_GPIO_C_2 10 +#define ES_PIN_GPIO_C_3 11 +#define ES_PIN_GPIO_H_3 12 +#define ES_PIN_GPIO_H_4 13 +#define ES_PIN_GPIO_A_0 14 +#define ES_PIN_GPIO_A_1 15 +#define ES_PIN_GPIO_A_2 16 +#define ES_PIN_GPIO_A_3 17 +#define ES_PIN_GPIO_F_0 18 +#define ES_PIN_GPIO_F_1 19 +#define ES_PIN_GPIO_A_4 20 +#define ES_PIN_GPIO_A_5 21 +#define ES_PIN_GPIO_A_6 22 +#define ES_PIN_GPIO_A_7 23 +#define ES_PIN_GPIO_C_4 24 +#define ES_PIN_GPIO_C_5 25 +#define ES_PIN_GPIO_B_0 26 +#define ES_PIN_GPIO_B_1 27 +#define ES_PIN_GPIO_B_2 28 +#define ES_PIN_GPIO_B_10 29 +#define ES_PIN_GPIO_B_11 30 +#define ES_PIN_GPIO_B_12 33 +#define ES_PIN_GPIO_B_13 34 +#define ES_PIN_GPIO_B_14 35 +#define ES_PIN_GPIO_B_15 36 +#define ES_PIN_GPIO_C_6 37 +#define ES_PIN_GPIO_C_7 38 +#define ES_PIN_GPIO_C_8 39 +#define ES_PIN_GPIO_A_13 46 +#define ES_PIN_GPIO_A_14 49 +#define ES_PIN_GPIO_A_15 50 +#define ES_PIN_GPIO_C_10 51 +#define ES_PIN_GPIO_C_11 52 +#define ES_PIN_GPIO_C_12 53 +#define ES_PIN_GPIO_D_2 54 +#define ES_PIN_GPIO_B_3 55 +#define ES_PIN_GPIO_B_4 56 +#define ES_PIN_GPIO_B_5 57 +#define ES_PIN_GPIO_B_6 58 +#define ES_PIN_GPIO_B_7 59 +#define ES_PIN_GPIO_H_2 60 +#define ES_PIN_GPIO_B_8 61 +#define ES_PIN_GPIO_B_9 62 + + + +/* UART_TX */ + + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_UART0_TX_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_UART0_TX_PIN ES_PIN_GPIO_H_0 +#endif +#endif + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_UART0_TX_PIN +#ifdef ES_PIN_GPIO_D_8 +#define ES_UART0_TX_PIN ES_PIN_GPIO_D_8 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_A_13 +#define ES_UART1_TX_PIN ES_PIN_GPIO_A_13 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART1_TX_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART1_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_UART1_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_E_2 +#define ES_UART2_TX_PIN ES_PIN_GPIO_E_2 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART2_TX_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_TX_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_UART2_TX_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_UART3_TX_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_UART3_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART3_TX_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_UART3_TX_PIN ES_PIN_GPIO_D_14 +#endif +#endif + +#ifndef ES_UART4_TX_GPIO_FUNC +#define ES_UART4_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_TX_GPIO_PORT +#define ES_UART4_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART4_TX_GPIO_PIN +#define ES_UART4_TX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART4_TX_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_UART4_TX_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_UART4_TX_GPIO_FUNC +#define ES_UART4_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_TX_GPIO_PORT +#define ES_UART4_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_TX_GPIO_PIN +#define ES_UART4_TX_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART4_TX_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_UART4_TX_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART5_TX_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_UART5_TX_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART5_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_UART5_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART5_TX_PIN +#ifdef ES_PIN_GPIO_D_5 +#define ES_UART5_TX_PIN ES_PIN_GPIO_D_5 +#endif +#endif + + +/* UART_RX */ + + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_UART0_RX_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_UART0_RX_PIN ES_PIN_GPIO_H_1 +#endif +#endif + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_UART0_RX_PIN +#ifdef ES_PIN_GPIO_D_9 +#define ES_UART0_RX_PIN ES_PIN_GPIO_D_9 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_1 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_A_14 +#define ES_UART1_RX_PIN ES_PIN_GPIO_A_14 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART1_RX_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART1_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_UART1_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_UART2_RX_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_E_3 +#define ES_UART2_RX_PIN ES_PIN_GPIO_E_3 +#endif +#endif + +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART2_RX_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART2_RX_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_UART3_RX_PIN ES_PIN_GPIO_C_5 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_UART3_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RX_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_UART3_RX_PIN ES_PIN_GPIO_D_13 +#endif +#endif + +#ifndef ES_UART4_RX_GPIO_FUNC +#define ES_UART4_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_RX_GPIO_PORT +#define ES_UART4_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART4_RX_GPIO_PIN +#define ES_UART4_RX_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_UART4_RX_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_UART4_RX_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_UART4_RX_GPIO_FUNC +#define ES_UART4_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_RX_GPIO_PORT +#define ES_UART4_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RX_GPIO_PIN +#define ES_UART4_RX_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART4_RX_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_UART4_RX_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_UART5_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_UART5_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART5_RX_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_UART5_RX_PIN ES_PIN_GPIO_A_3 +#endif +#endif + +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART5_RX_PIN +#ifdef ES_PIN_GPIO_D_6 +#define ES_UART5_RX_PIN ES_PIN_GPIO_D_6 +#endif +#endif + + +/* UART_RTS */ + + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART0_RTS_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_UART0_RTS_PIN ES_PIN_GPIO_D_12 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_3 +#endif +#endif + +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART1_RTS_PIN +#ifdef ES_PIN_GPIO_C_12 +#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_12 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_E_5 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_E_5 +#endif +#endif + +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_UART2_RTS_PIN +#ifdef ES_PIN_GPIO_C_10 +#define ES_UART2_RTS_PIN ES_PIN_GPIO_C_10 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_B_1 +#endif +#endif + +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART3_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_UART3_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_UART4_RTS_GPIO_FUNC +#define ES_UART4_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_RTS_GPIO_PORT +#define ES_UART4_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RTS_GPIO_PIN +#define ES_UART4_RTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART4_RTS_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_UART4_RTS_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_UART4_RTS_GPIO_FUNC +#define ES_UART4_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_RTS_GPIO_PORT +#define ES_UART4_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RTS_GPIO_PIN +#define ES_UART4_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART4_RTS_PIN +#ifdef ES_PIN_GPIO_E_1 +#define ES_UART4_RTS_PIN ES_PIN_GPIO_E_1 +#endif +#endif + +#ifndef ES_UART5_RTS_GPIO_FUNC +#define ES_UART5_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_RTS_GPIO_PORT +#define ES_UART5_RTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_RTS_GPIO_PIN +#define ES_UART5_RTS_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_UART5_RTS_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_UART5_RTS_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_UART5_RTS_GPIO_FUNC +#define ES_UART5_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_RTS_GPIO_PORT +#define ES_UART5_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_RTS_GPIO_PIN +#define ES_UART5_RTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART5_RTS_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_UART5_RTS_PIN ES_PIN_GPIO_D_4 +#endif +#endif + + +/* UART_CTS */ + + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART0_CTS_PIN +#ifdef ES_PIN_GPIO_D_11 +#define ES_UART0_CTS_PIN ES_PIN_GPIO_D_11 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_UART1_CTS_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_UART1_CTS_PIN ES_PIN_GPIO_D_2 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_E_4 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_E_4 +#endif +#endif + +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_UART2_CTS_PIN +#ifdef ES_PIN_GPIO_C_11 +#define ES_UART2_CTS_PIN ES_PIN_GPIO_C_11 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART3_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_UART3_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_UART4_CTS_GPIO_FUNC +#define ES_UART4_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_CTS_GPIO_PORT +#define ES_UART4_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CTS_GPIO_PIN +#define ES_UART4_CTS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_UART4_CTS_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_UART4_CTS_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_UART4_CTS_GPIO_FUNC +#define ES_UART4_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_CTS_GPIO_PORT +#define ES_UART4_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CTS_GPIO_PIN +#define ES_UART4_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART4_CTS_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_UART4_CTS_PIN ES_PIN_GPIO_E_0 +#endif +#endif + +#ifndef ES_UART5_CTS_GPIO_FUNC +#define ES_UART5_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_CTS_GPIO_PORT +#define ES_UART5_CTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_CTS_GPIO_PIN +#define ES_UART5_CTS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART5_CTS_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_UART5_CTS_PIN ES_PIN_GPIO_A_0 +#endif +#endif + +#ifndef ES_UART5_CTS_GPIO_FUNC +#define ES_UART5_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_CTS_GPIO_PORT +#define ES_UART5_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_CTS_GPIO_PIN +#define ES_UART5_CTS_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_UART5_CTS_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_UART5_CTS_PIN ES_PIN_GPIO_D_3 +#endif +#endif + + +/* UART_CK */ + + +#ifndef ES_UART4_CK_GPIO_FUNC +#define ES_UART4_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_CK_GPIO_PORT +#define ES_UART4_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CK_GPIO_PIN +#define ES_UART4_CK_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_UART4_CK_PIN +#ifdef ES_PIN_GPIO_E_6 +#define ES_UART4_CK_PIN ES_PIN_GPIO_E_6 +#endif +#endif + +#ifndef ES_UART4_CK_GPIO_FUNC +#define ES_UART4_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_CK_GPIO_PORT +#define ES_UART4_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CK_GPIO_PIN +#define ES_UART4_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_UART4_CK_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_UART4_CK_PIN ES_PIN_GPIO_E_7 +#endif +#endif + +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_UART5_CK_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_UART5_CK_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_UART5_CK_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_UART5_CK_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_UART5_CK_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_UART5_CK_PIN ES_PIN_GPIO_E_0 +#endif +#endif + + +/* USART_TX */ + + + +/* USART_RX */ + + + +/* USART_RTS */ + + + +/* USART_CTS */ + + + +/* USART_CK */ + + + +/* I2C_SCL */ + + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_I2C0_SCL_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_I2C1_SCL_PIN +#ifdef ES_PIN_GPIO_H_0 +#define ES_I2C1_SCL_PIN ES_PIN_GPIO_H_0 +#endif +#endif + + +/* I2C_SDA */ + + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_I2C0_SDA_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_I2C1_SDA_PIN +#ifdef ES_PIN_GPIO_H_1 +#define ES_I2C1_SDA_PIN ES_PIN_GPIO_H_1 +#endif +#endif + + +/* SPI_MISO */ + + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_MISO_PIN +#ifdef ES_PIN_GPIO_D_4 +#define ES_SPI0_MISO_PIN ES_PIN_GPIO_D_4 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_C_2 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_C_2 +#endif +#endif + +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_SPI1_MISO_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_SPI1_MISO_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_SPI2_MISO_GPIO_FUNC +#define ES_SPI2_MISO_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_MISO_GPIO_PORT +#define ES_SPI2_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MISO_GPIO_PIN +#define ES_SPI2_MISO_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI2_MISO_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_SPI2_MISO_PIN ES_PIN_GPIO_B_4 +#endif +#endif + +#ifndef ES_SPI2_MISO_GPIO_FUNC +#define ES_SPI2_MISO_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_MISO_GPIO_PORT +#define ES_SPI2_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MISO_GPIO_PIN +#define ES_SPI2_MISO_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_SPI2_MISO_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_SPI2_MISO_PIN ES_PIN_GPIO_B_0 +#endif +#endif + + +/* SPI_MOSI */ + + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_SPI0_MOSI_PIN +#ifdef ES_PIN_GPIO_D_7 +#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_D_7 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_C_3 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_C_3 +#endif +#endif + +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI1_MOSI_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_SPI2_MOSI_GPIO_FUNC +#define ES_SPI2_MOSI_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_MOSI_GPIO_PORT +#define ES_SPI2_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MOSI_GPIO_PIN +#define ES_SPI2_MOSI_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI2_MOSI_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_SPI2_MOSI_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_SPI2_MOSI_GPIO_FUNC +#define ES_SPI2_MOSI_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_MOSI_GPIO_PORT +#define ES_SPI2_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MOSI_GPIO_PIN +#define ES_SPI2_MOSI_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_SPI2_MOSI_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_SPI2_MOSI_PIN ES_PIN_GPIO_B_1 +#endif +#endif + + +/* SPI_SCK */ + + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_A_5 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_A_5 +#endif +#endif + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI0_SCK_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_SPI0_SCK_PIN ES_PIN_GPIO_D_3 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_C_1 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_C_1 +#endif +#endif + +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_SPI1_SCK_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_SPI1_SCK_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_SPI2_SCK_GPIO_FUNC +#define ES_SPI2_SCK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_SCK_GPIO_PORT +#define ES_SPI2_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI2_SCK_GPIO_PIN +#define ES_SPI2_SCK_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_SPI2_SCK_PIN +#ifdef ES_PIN_GPIO_C_5 +#define ES_SPI2_SCK_PIN ES_PIN_GPIO_C_5 +#endif +#endif + +#ifndef ES_SPI2_SCK_GPIO_FUNC +#define ES_SPI2_SCK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_SCK_GPIO_PORT +#define ES_SPI2_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_SCK_GPIO_PIN +#define ES_SPI2_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_SPI2_SCK_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_SPI2_SCK_PIN ES_PIN_GPIO_B_3 +#endif +#endif + + +/* SPI_NSS */ + + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI0_NSS_PIN +#ifdef ES_PIN_GPIO_A_4 +#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_4 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_C_0 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_C_0 +#endif +#endif + +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_SPI1_NSS_PIN +#ifdef ES_PIN_GPIO_B_12 +#define ES_SPI1_NSS_PIN ES_PIN_GPIO_B_12 +#endif +#endif + +#ifndef ES_SPI2_NSS_GPIO_FUNC +#define ES_SPI2_NSS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_NSS_GPIO_PORT +#define ES_SPI2_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI2_NSS_GPIO_PIN +#define ES_SPI2_NSS_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_SPI2_NSS_PIN +#ifdef ES_PIN_GPIO_C_4 +#define ES_SPI2_NSS_PIN ES_PIN_GPIO_C_4 +#endif +#endif + +#ifndef ES_SPI2_NSS_GPIO_FUNC +#define ES_SPI2_NSS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_NSS_GPIO_PORT +#define ES_SPI2_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI2_NSS_GPIO_PIN +#define ES_SPI2_NSS_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_SPI2_NSS_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_SPI2_NSS_PIN ES_PIN_GPIO_A_15 +#endif +#endif + + +/* CAN_TX */ + + +#ifndef ES_CAN0_TX_GPIO_FUNC +#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_TX_GPIO_PORT +#define ES_CAN0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_TX_GPIO_PIN +#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_CAN0_TX_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_CAN0_TX_PIN ES_PIN_GPIO_B_9 +#endif +#endif + + +/* CAN_RX */ + + +#ifndef ES_CAN0_RX_GPIO_FUNC +#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_RX_GPIO_PORT +#define ES_CAN0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_RX_GPIO_PIN +#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_CAN0_RX_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_CAN0_RX_PIN ES_PIN_GPIO_B_8 +#endif +#endif + + +/* AD16C4T_CH1 */ + + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_AD16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_E_9 +#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_E_9 +#endif +#endif + +#ifndef ES_AD16C4T1_CH1_GPIO_FUNC +#define ES_AD16C4T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH1_GPIO_PORT +#define ES_AD16C4T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH1_GPIO_PIN +#define ES_AD16C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_AD16C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_AD16C4T1_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif + + +/* AD16C4T_CH2 */ + + +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_AD16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_E_11 +#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_E_11 +#endif +#endif + +#ifndef ES_AD16C4T1_CH2_GPIO_FUNC +#define ES_AD16C4T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH2_GPIO_PORT +#define ES_AD16C4T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH2_GPIO_PIN +#define ES_AD16C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_AD16C4T1_CH2_PIN ES_PIN_GPIO_C_7 +#endif +#endif + + +/* AD16C4T_CH3 */ + + +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_E_13 +#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_E_13 +#endif +#endif + +#ifndef ES_AD16C4T1_CH3_GPIO_FUNC +#define ES_AD16C4T1_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH3_GPIO_PORT +#define ES_AD16C4T1_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH3_GPIO_PIN +#define ES_AD16C4T1_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_C_8 +#define ES_AD16C4T1_CH3_PIN ES_PIN_GPIO_C_8 +#endif +#endif + + +/* AD16C4T_CH4 */ + + +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_E_14 +#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_E_14 +#endif +#endif + + +/* AD16C4T_CH1N */ + + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_B_13 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_B_13 +#endif +#endif + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_AD16C4T0_CH1N_PIN +#ifdef ES_PIN_GPIO_E_8 +#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_E_8 +#endif +#endif + +#ifndef ES_AD16C4T1_CH1N_GPIO_FUNC +#define ES_AD16C4T1_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH1N_GPIO_PORT +#define ES_AD16C4T1_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T1_CH1N_GPIO_PIN +#define ES_AD16C4T1_CH1N_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T1_CH1N_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_AD16C4T1_CH1N_PIN ES_PIN_GPIO_A_7 +#endif +#endif + + +/* AD16C4T_CH2N */ + + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_B_14 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_14 +#endif +#endif + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_AD16C4T0_CH2N_PIN +#ifdef ES_PIN_GPIO_E_10 +#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_E_10 +#endif +#endif + +#ifndef ES_AD16C4T1_CH2N_GPIO_FUNC +#define ES_AD16C4T1_CH2N_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T1_CH2N_GPIO_PORT +#define ES_AD16C4T1_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T1_CH2N_GPIO_PIN +#define ES_AD16C4T1_CH2N_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T1_CH2N_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_AD16C4T1_CH2N_PIN ES_PIN_GPIO_B_0 +#endif +#endif + + +/* AD16C4T_CH3N */ + + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_B_15 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_15 +#endif +#endif + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_AD16C4T0_CH3N_PIN +#ifdef ES_PIN_GPIO_E_12 +#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_E_12 +#endif +#endif + +#ifndef ES_AD16C4T1_CH3N_GPIO_FUNC +#define ES_AD16C4T1_CH3N_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T1_CH3N_GPIO_PORT +#define ES_AD16C4T1_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T1_CH3N_GPIO_PIN +#define ES_AD16C4T1_CH3N_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_AD16C4T1_CH3N_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_AD16C4T1_CH3N_PIN ES_PIN_GPIO_B_1 +#endif +#endif + + +/* AD16C4T_CH4N */ + + + +/* AD16C4T_ET */ + + +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_AD16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_7 +#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_E_7 +#endif +#endif + +#ifndef ES_AD16C4T1_ET_GPIO_FUNC +#define ES_AD16C4T1_ET_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T1_ET_GPIO_PORT +#define ES_AD16C4T1_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T1_ET_GPIO_PIN +#define ES_AD16C4T1_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_AD16C4T1_ET_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_AD16C4T1_ET_PIN ES_PIN_GPIO_A_0 +#endif +#endif + + +/* GP32C4T_CH1 */ + + +#ifndef ES_GP32C4T0_CH1_GPIO_FUNC +#define ES_GP32C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PORT +#define ES_GP32C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PIN +#define ES_GP32C4T0_CH1_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP32C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP32C4T0_CH1_PIN ES_PIN_GPIO_A_0 +#endif +#endif + +#ifndef ES_GP32C4T0_CH1_GPIO_FUNC +#define ES_GP32C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PORT +#define ES_GP32C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PIN +#define ES_GP32C4T0_CH1_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP32C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP32C4T0_CH1_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP32C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_A_6 +#define ES_GP32C4T1_CH1_PIN ES_PIN_GPIO_A_6 +#endif +#endif + +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP32C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_C_6 +#define ES_GP32C4T1_CH1_PIN ES_PIN_GPIO_C_6 +#endif +#endif + +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_4 +#endif + +#ifndef ES_GP32C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_B_4 +#define ES_GP32C4T1_CH1_PIN ES_PIN_GPIO_B_4 +#endif +#endif + + +/* GP32C4T_CH2 */ + + +#ifndef ES_GP32C4T0_CH2_GPIO_FUNC +#define ES_GP32C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PORT +#define ES_GP32C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PIN +#define ES_GP32C4T0_CH2_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP32C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_GP32C4T0_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif + +#ifndef ES_GP32C4T0_CH2_GPIO_FUNC +#define ES_GP32C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PORT +#define ES_GP32C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PIN +#define ES_GP32C4T0_CH2_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP32C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_3 +#define ES_GP32C4T0_CH2_PIN ES_PIN_GPIO_B_3 +#endif +#endif + +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_5 +#endif + +#ifndef ES_GP32C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_B_5 +#define ES_GP32C4T1_CH2_PIN ES_PIN_GPIO_B_5 +#endif +#endif + +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP32C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_A_7 +#define ES_GP32C4T1_CH2_PIN ES_PIN_GPIO_A_7 +#endif +#endif + +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP32C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_C_7 +#define ES_GP32C4T1_CH2_PIN ES_PIN_GPIO_C_7 +#endif +#endif + + +/* GP32C4T_CH3 */ + + +#ifndef ES_GP32C4T0_CH3_GPIO_FUNC +#define ES_GP32C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PORT +#define ES_GP32C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PIN +#define ES_GP32C4T0_CH3_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP32C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_GP32C4T0_CH3_PIN ES_PIN_GPIO_A_2 +#endif +#endif + +#ifndef ES_GP32C4T0_CH3_GPIO_FUNC +#define ES_GP32C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PORT +#define ES_GP32C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PIN +#define ES_GP32C4T0_CH3_GPIO_PIN GPIO_PIN_10 +#endif + +#ifndef ES_GP32C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_10 +#define ES_GP32C4T0_CH3_PIN ES_PIN_GPIO_B_10 +#endif +#endif + +#ifndef ES_GP32C4T1_CH3_GPIO_FUNC +#define ES_GP32C4T1_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PORT +#define ES_GP32C4T1_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PIN +#define ES_GP32C4T1_CH3_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP32C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_B_0 +#define ES_GP32C4T1_CH3_PIN ES_PIN_GPIO_B_0 +#endif +#endif + +#ifndef ES_GP32C4T1_CH3_GPIO_FUNC +#define ES_GP32C4T1_CH3_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PORT +#define ES_GP32C4T1_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PIN +#define ES_GP32C4T1_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP32C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_C_8 +#define ES_GP32C4T1_CH3_PIN ES_PIN_GPIO_C_8 +#endif +#endif + + +/* GP32C4T_CH4 */ + + +#ifndef ES_GP32C4T0_CH4_GPIO_FUNC +#define ES_GP32C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PORT +#define ES_GP32C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PIN +#define ES_GP32C4T0_CH4_GPIO_PIN GPIO_PIN_11 +#endif + +#ifndef ES_GP32C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_B_11 +#define ES_GP32C4T0_CH4_PIN ES_PIN_GPIO_B_11 +#endif +#endif + +#ifndef ES_GP32C4T0_CH4_GPIO_FUNC +#define ES_GP32C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PORT +#define ES_GP32C4T0_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PIN +#define ES_GP32C4T0_CH4_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP32C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_GP32C4T0_CH4_PIN ES_PIN_GPIO_A_3 +#endif +#endif + +#ifndef ES_GP32C4T1_CH4_GPIO_FUNC +#define ES_GP32C4T1_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH4_GPIO_PORT +#define ES_GP32C4T1_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH4_GPIO_PIN +#define ES_GP32C4T1_CH4_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP32C4T1_CH4_PIN +#ifdef ES_PIN_GPIO_B_1 +#define ES_GP32C4T1_CH4_PIN ES_PIN_GPIO_B_1 +#endif +#endif + + +/* GP32C4T_ET */ + + +#ifndef ES_GP32C4T0_ET_GPIO_FUNC +#define ES_GP32C4T0_ET_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PORT +#define ES_GP32C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PIN +#define ES_GP32C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP32C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP32C4T0_ET_PIN ES_PIN_GPIO_A_0 +#endif +#endif + +#ifndef ES_GP32C4T0_ET_GPIO_FUNC +#define ES_GP32C4T0_ET_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PORT +#define ES_GP32C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PIN +#define ES_GP32C4T0_ET_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP32C4T0_ET_PIN +#ifdef ES_PIN_GPIO_A_15 +#define ES_GP32C4T0_ET_PIN ES_PIN_GPIO_A_15 +#endif +#endif + +#ifndef ES_GP32C4T1_ET_GPIO_FUNC +#define ES_GP32C4T1_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_ET_GPIO_PORT +#define ES_GP32C4T1_ET_GPIO_PORT GPIOD +#endif +#ifndef ES_GP32C4T1_ET_GPIO_PIN +#define ES_GP32C4T1_ET_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP32C4T1_ET_PIN +#ifdef ES_PIN_GPIO_D_2 +#define ES_GP32C4T1_ET_PIN ES_PIN_GPIO_D_2 +#endif +#endif + + +/* GP16C4T_CH1 */ + + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_B_6 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_B_6 +#endif +#endif + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_12 +#endif + +#ifndef ES_GP16C4T0_CH1_PIN +#ifdef ES_PIN_GPIO_D_12 +#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_D_12 +#endif +#endif + +#ifndef ES_GP16C4T1_CH1_GPIO_FUNC +#define ES_GP16C4T1_CH1_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PORT +#define ES_GP16C4T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PIN +#define ES_GP16C4T1_CH1_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T1_CH1_PIN +#ifdef ES_PIN_GPIO_A_0 +#define ES_GP16C4T1_CH1_PIN ES_PIN_GPIO_A_0 +#endif +#endif + + +/* GP16C4T_CH2 */ + + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_B_7 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_B_7 +#endif +#endif + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_13 +#endif + +#ifndef ES_GP16C4T0_CH2_PIN +#ifdef ES_PIN_GPIO_D_13 +#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_D_13 +#endif +#endif + +#ifndef ES_GP16C4T1_CH2_GPIO_FUNC +#define ES_GP16C4T1_CH2_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PORT +#define ES_GP16C4T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PIN +#define ES_GP16C4T1_CH2_GPIO_PIN GPIO_PIN_1 +#endif + +#ifndef ES_GP16C4T1_CH2_PIN +#ifdef ES_PIN_GPIO_A_1 +#define ES_GP16C4T1_CH2_PIN ES_PIN_GPIO_A_1 +#endif +#endif + + +/* GP16C4T_CH3 */ + + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_B_8 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_B_8 +#endif +#endif + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_14 +#endif + +#ifndef ES_GP16C4T0_CH3_PIN +#ifdef ES_PIN_GPIO_D_14 +#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_D_14 +#endif +#endif + +#ifndef ES_GP16C4T1_CH3_GPIO_FUNC +#define ES_GP16C4T1_CH3_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PORT +#define ES_GP16C4T1_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PIN +#define ES_GP16C4T1_CH3_GPIO_PIN GPIO_PIN_2 +#endif + +#ifndef ES_GP16C4T1_CH3_PIN +#ifdef ES_PIN_GPIO_A_2 +#define ES_GP16C4T1_CH3_PIN ES_PIN_GPIO_A_2 +#endif +#endif + + +/* GP16C4T_CH4 */ + + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_9 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_B_9 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_B_9 +#endif +#endif + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_15 +#endif + +#ifndef ES_GP16C4T0_CH4_PIN +#ifdef ES_PIN_GPIO_D_15 +#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_D_15 +#endif +#endif + +#ifndef ES_GP16C4T1_CH4_GPIO_FUNC +#define ES_GP16C4T1_CH4_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PORT +#define ES_GP16C4T1_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PIN +#define ES_GP16C4T1_CH4_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP16C4T1_CH4_PIN +#ifdef ES_PIN_GPIO_A_3 +#define ES_GP16C4T1_CH4_PIN ES_PIN_GPIO_A_3 +#endif +#endif + + +/* GP16C4T_ET */ + + +#ifndef ES_GP16C4T0_ET_GPIO_FUNC +#define ES_GP16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PORT +#define ES_GP16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PIN +#define ES_GP16C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif + +#ifndef ES_GP16C4T0_ET_PIN +#ifdef ES_PIN_GPIO_E_0 +#define ES_GP16C4T0_ET_PIN ES_PIN_GPIO_E_0 +#endif +#endif + +#ifndef ES_GP16C4T1_ET_GPIO_FUNC +#define ES_GP16C4T1_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PORT +#define ES_GP16C4T1_ET_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PIN +#define ES_GP16C4T1_ET_GPIO_PIN GPIO_PIN_3 +#endif + +#ifndef ES_GP16C4T1_ET_PIN +#ifdef ES_PIN_GPIO_D_3 +#define ES_GP16C4T1_ET_PIN ES_PIN_GPIO_D_3 +#endif +#endif + + +/* GP16C2T_CH1 */ + + + +/* GP16C2T_CH2 */ + + + +/* GP16C2T_CH1N */ + + + +/* GP16C2T_CH2N */ + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h new file mode 100644 index 0000000000..580268312c --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PM_H__ +#define __ES_CONF_INFO_PM_H__ + +#include +#include + +#define ES_PMU_SAVE_LOAD_UART + +/* PM 配置 */ + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h new file mode 100644 index 0000000000..86010a80ce --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h @@ -0,0 +1,78 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PWM_H__ +#define __ES_CONF_INFO_PWM_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + + +#define ES_C_PWM_OC_POL_HIGH TIMER_OC_POLARITY_HIGH +#define ES_C_PWM_OC_POL_LOW TIMER_OC_POLARITY_LOW + +#define ES_C_PWM_OC_MODE_PWM1 TIMER_OC_MODE_PWM1 +#define ES_C_PWM_OC_MODE_PWM2 TIMER_OC_MODE_PWM2 + + + +/* PWM 配置 */ + + +/* codes_main */ + + + +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 + +#ifndef ES_PWM_OC_POLARITY +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#endif +#ifndef ES_PWM_OC_MODE +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 +#endif + +#ifndef ES_DEVICE_NAME_AD16C4T0_PWM +#define ES_DEVICE_NAME_AD16C4T0_PWM "pwm0" +#endif +#ifndef ES_DEVICE_NAME_AD16C4T1_PWM +#define ES_DEVICE_NAME_AD16C4T1_PWM "pwm1" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T0_PWM +#define ES_DEVICE_NAME_GP32C4T0_PWM "pwm2" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T1_PWM +#define ES_DEVICE_NAME_GP32C4T1_PWM "pwm3" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_PWM +#define ES_DEVICE_NAME_GP16C4T0_PWM "pwm4" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T1_PWM +#define ES_DEVICE_NAME_GP16C4T1_PWM "pwm5" +#endif + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h new file mode 100644 index 0000000000..2aa8faf9d7 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_RTC_H__ +#define __ES_CONF_INFO_RTC_H__ + +#include +#include + +/* RTC 配置 */ + +#define ES_C_RTC_SOURCE_LRC RTC_SOURCE_LRC +#define ES_C_RTC_SOURCE_LOSC RTC_SOURCE_LOSC + +#define ES_RTC_CLK_SOURCE ES_C_RTC_SOURCE_LOSC + + + + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_RTC +#define ES_DEVICE_NAME_RTC "rtc" +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h new file mode 100644 index 0000000000..06a28d6fd0 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h @@ -0,0 +1,43 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SELECT_H__ +#define __ES_CONF_INFO_SELECT_H__ + + +#define ES_C_ENABLE 1 +#define ES_C_DISABLE 0 + + +/* codes_main */ + +#ifndef ES_USE_ASSERT +#define ES_USE_ASSERT ES_C_DISABLE +#endif + + +#if ES_USE_ASSERT + #define USE_ASSERT +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h new file mode 100644 index 0000000000..c9cf895aeb --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h @@ -0,0 +1,159 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SPI_H__ +#define __ES_CONF_INFO_SPI_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +/* SPI 配置 */ + +#define SPI_BUS_CONFIG(_CONF_,_I_) do{_CONF_.mode = 0U; \ + _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE | \ + ES_SPI##_I_##_WIRE_3_4 | \ + ES_SPI##_I_##_CPHA_1_2 | \ + ES_SPI##_I_##_CPOL_H_L | \ + ES_SPI##_I_##_CS | \ + ES_SPI##_I_##_M_L_SB ); \ + _CONF_.data_width = ES_SPI##_I_##_DATA_W; \ + _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ; \ + }while(0) + + +// spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ +// spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ +// spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ +// spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ +// spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ +// spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ +// spi_config.data_width = 8; /* 数据长度：8 */ +// spi_config.max_hz = 2000000; /* 最快时钟频率 */ + +#define ES_C_SPI_CLK_POL_HIGH RT_SPI_CPOL +#define ES_C_SPI_CLK_POL_LOW !RT_SPI_CPOL + +#define ES_C_SPI_CLK_PHA_FIRST !RT_SPI_CPHA +#define ES_C_SPI_CLK_PHA_SECOND RT_SPI_CPHA + +#define ES_C_SPI_MSB RT_SPI_MSB +#define ES_C_SPI_LSB RT_SPI_LSB + +#define ES_C_SPI_CS_LOW_LEVEL 0 +#define ES_C_SPI_CS_HIGH_LEVEL 1 + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_SPI0_BUS +#define ES_DEVICE_NAME_SPI0_BUS "spi0" +#endif +#ifndef ES_DEVICE_NAME_SPI0_DEV0 +#define ES_DEVICE_NAME_SPI0_DEV0 "spi00" +#endif + +#ifndef ES_DEVICE_NAME_SPI1_BUS +#define ES_DEVICE_NAME_SPI1_BUS "spi1" +#endif +#ifndef ES_DEVICE_NAME_SPI1_DEV0 +#define ES_DEVICE_NAME_SPI1_DEV0 "spi10" +#endif + +#ifndef ES_DEVICE_NAME_SPI2_BUS +#define ES_DEVICE_NAME_SPI2_BUS "spi2" +#endif +#ifndef ES_DEVICE_NAME_SPI2_DEV0 +#define ES_DEVICE_NAME_SPI2_DEV0 "spi20" +#endif + + +#define ES_SPI_CS_LEVEL ES_C_SPI_CS_LOW_LEVEL + +#ifndef ES_SPI0_CPHA_1_2 +#define ES_SPI0_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI0_CPOL_H_L +#define ES_SPI0_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI0_M_L_SB +#define ES_SPI0_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI0_MAX_HZ +#define ES_SPI0_MAX_HZ 2000000 +#endif +#ifndef ES_SPI0_NSS_PIN +#define ES_SPI0_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI1_CPHA_1_2 +#define ES_SPI1_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI1_CPOL_H_L +#define ES_SPI1_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI1_M_L_SB +#define ES_SPI1_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI1_MAX_HZ +#define ES_SPI1_MAX_HZ 2000000 +#endif +#ifndef ES_SPI1_NSS_PIN +#define ES_SPI1_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI2_CPHA_1_2 +#define ES_SPI2_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI2_CPOL_H_L +#define ES_SPI2_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI2_M_L_SB +#define ES_SPI2_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI2_MAX_HZ +#define ES_SPI2_MAX_HZ 2000000 +#endif +#ifndef ES_SPI2_NSS_PIN +#define ES_SPI2_NSS_PIN 0xFFFFFFFF +#endif + + +#define ES_SPI0_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI0_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI0_CS RT_SPI_NO_CS +#define ES_SPI0_DATA_W 8 + +#define ES_SPI1_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI1_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI1_CS RT_SPI_NO_CS +#define ES_SPI1_DATA_W 8 + +#define ES_SPI2_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI2_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI2_CS RT_SPI_NO_CS +#define ES_SPI2_DATA_W 8 + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h new file mode 100644 index 0000000000..430cb9f599 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h @@ -0,0 +1,205 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_UART_H__ +#define __ES_CONF_INFO_UART_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + + + +#define ES_C_UART_PARITY_NONE PARITY_NONE +#define ES_C_UART_PARITY_ODD PARITY_ODD +#define ES_C_UART_PARITY_EVEN PARITY_EVEN + +#define ES_C_UART_STOP_1 STOP_BITS_1 +#define ES_C_UART_STOP_2 STOP_BITS_2 + + +/* UART 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_UART0 +#define ES_DEVICE_NAME_UART0 "uart0" +#endif +#ifndef ES_DEVICE_NAME_UART1 +#define ES_DEVICE_NAME_UART1 "uart1" +#endif +#ifndef ES_DEVICE_NAME_UART2 +#define ES_DEVICE_NAME_UART2 "uart2" +#endif +#ifndef ES_DEVICE_NAME_UART3 +#define ES_DEVICE_NAME_UART3 "uart3" +#endif +#ifndef ES_DEVICE_NAME_UART4 +#define ES_DEVICE_NAME_UART4 "uart4" +#endif +#ifndef ES_DEVICE_NAME_UART5 +#define ES_DEVICE_NAME_UART5 "uart5" +#endif + +#ifndef ES_CONF_UART0_BAUD_RATE +#define ES_CONF_UART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART0_PARITY +#define ES_CONF_UART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART0_STOP_BITS +#define ES_CONF_UART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART1_BAUD_RATE +#define ES_CONF_UART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART1_PARITY +#define ES_CONF_UART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART1_STOP_BITS +#define ES_CONF_UART1_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART2_BAUD_RATE +#define ES_CONF_UART2_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART2_PARITY +#define ES_CONF_UART2_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART2_STOP_BITS +#define ES_CONF_UART2_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART3_BAUD_RATE +#define ES_CONF_UART3_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART3_PARITY +#define ES_CONF_UART3_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART3_STOP_BITS +#define ES_CONF_UART3_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART4_BAUD_RATE +#define ES_CONF_UART4_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART4_PARITY +#define ES_CONF_UART4_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART4_STOP_BITS +#define ES_CONF_UART4_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART5_BAUD_RATE +#define ES_CONF_UART5_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART5_PARITY +#define ES_CONF_UART5_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART5_STOP_BITS +#define ES_CONF_UART5_STOP_BITS ES_C_UART_STOP_1 +#endif + + +#define ES_UART0_CONFIG \ +{ \ + ES_CONF_UART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART0_STOP_BITS, \ + ES_CONF_UART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART1_CONFIG \ +{ \ + ES_CONF_UART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART1_STOP_BITS, \ + ES_CONF_UART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART2_CONFIG \ +{ \ + ES_CONF_UART2_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART2_STOP_BITS, \ + ES_CONF_UART2_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART3_CONFIG \ +{ \ + ES_CONF_UART3_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART3_STOP_BITS, \ + ES_CONF_UART3_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART4_CONFIG \ +{ \ + ES_CONF_UART4_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART4_STOP_BITS, \ + ES_CONF_UART4_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART5_CONFIG \ +{ \ + ES_CONF_UART5_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART5_STOP_BITS, \ + ES_CONF_UART5_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + +#endif diff --git a/bsp/essemi/es32f369x/drivers/Kconfig b/bsp/essemi/es32f369x/drivers/Kconfig index 4b42e7e074..75cb7bd164 100644 --- a/bsp/essemi/es32f369x/drivers/Kconfig +++ b/bsp/essemi/es32f369x/drivers/Kconfig @@ -1,139 +1,37 @@ menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN default y - menu "UART Drivers" - config BSP_USING_UART0 - bool "Enable UART0 PB10/PB11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART1 - bool "Enable UART1 PC10/PC11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART2 - bool "Enable UART2 PC12/PD02(T/R)" - select RT_USING_SERIAL - default y - - config BSP_USING_UART3 - bool "Enable UART3 PC04/PC05(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_SPI2 - - config BSP_USING_UART4 - bool "Enable UART4 PB06/PB07(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_I2C0 - depends on !BSP_USING_PWM0 - - config BSP_USING_UART5 - bool "Enable UART5 PB09/PB08(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_PWM0 - endmenu - - menu "SPI Drivers" - config BSP_USING_SPI0 - bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI1 - bool "Enable SPI1 BUS PC01/PC02/PC03(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI2 - bool "Enable SPI2 BUS PC05/PB00/PB01(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - depends on !BSP_USING_UART3 - endmenu - - menu "I2C Drivers" - config BSP_USING_I2C0 - bool "Enable I2C0 BUS PB06/PB07(SCL/SDA)" - select RT_USING_I2C - default n - depends on !BSP_USING_PWM0 - - config BSP_USING_I2C1 - bool "Enable I2C1 BUS PA05/PA06(SCL/SDA)" - select RT_USING_I2C - default n - endmenu - - menu "CAN Drivers" - config BSP_USING_CAN - bool "Enable CAN BUS PB08/PB09(RX/TX)" - select RT_USING_CAN - default n - endmenu - - menu "ADC Drivers" - config BSP_USING_ADC - bool "Using ADC" - select RT_USING_ADC - default n - endmenu - - menu "RTC Drivers" - config BSP_USING_RTC - bool "Using RTC" - select RT_USING_RTC - default n - endmenu - - menu "HWtimer Drivers" - config BSP_USING_HWTIMER0 - bool "Using timer0" - select RT_USING_HWTIMER - default n - - config BSP_USING_HWTIMER1 - bool "Using timer1" - select RT_USING_HWTIMER - default n - endmenu - - menu "PWM Drivers" - config BSP_USING_PWM0 - bool "Using PWM0 PB06/PB07/PB08/PB09" - select RT_USING_PWM - default n - depends on !BSP_USING_CAN - depends on !BSP_USING_I2C0 - - config BSP_USING_PWM1 - bool "Using PWM1 PA00/PA01/PA02/PA03" - select RT_USING_PWM - default n - endmenu - - menu "PM Drivers" - config BSP_USING_PM - bool "Using PM" - select RT_USING_PM - default n - endmenu + source "drivers/ES/Kconfig" endmenu menu "Onboard Peripheral Drivers" + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (W25Q64 spi0)" + select BSP_USING_SPI + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + +if BSP_USING_SPI_FLASH + + config ES_DEVICE_NAME_SPI_DEV + string "The name of spi device (registered)" + default "spi00" + + config ES_DEVICE_NAME_SPI_FALSH_DEV + string "The name of spi flash device" + default "W25Q64" +endif + endmenu menu "Offboard Peripheral Drivers" @@ -155,13 +53,17 @@ menu "Hardware Drivers Config" bool "BSP_USING_EXAMPLE_I2C" default n + config BSP_USING_EXAMPLE_I2C_E2PROM + bool "BSP_USING_EXAMPLE_I2C_E2PROM" + default n + config BSP_USING_EXAMPLE_LED_BLINK bool "BSP_USING_EXAMPLE_LED_BLINK" - default y + default n config BSP_USING_EXAMPLE_PIN_BEEP bool "BSP_USING_EXAMPLE_PIN_BEEP" - default y + default n config BSP_USING_EXAMPLE_PWM_LED bool "BSP_USING_EXAMPLE_PWM_LED" @@ -177,7 +79,7 @@ menu "Hardware Drivers Config" config BSP_USING_EXAMPLE_UART bool "BSP_USING_EXAMPLE_UART" - default y + default n config BSP_USING_EXAMPLE_CAN bool "BSP_USING_EXAMPLE_CAN" diff --git a/bsp/essemi/es32f369x/drivers/SConscript b/bsp/essemi/es32f369x/drivers/SConscript index 735ebb37be..b39d545e35 100644 --- a/bsp/essemi/es32f369x/drivers/SConscript +++ b/bsp/essemi/es32f369x/drivers/SConscript @@ -15,7 +15,9 @@ if GetDepend('RT_USING_PIN'): # add serial driver code if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \ - GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5'): + GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5') or \ + GetDepend('BSP_USING_USART0') or GetDepend('BSP_USING_USART1') or GetDepend('BSP_USING_USART2') or GetDepend('BSP_USING_USART3') or \ + GetDepend('BSP_USING_USART4') or GetDepend('BSP_USING_USART5'): src += ['drv_uart.c'] # add spi driver code @@ -27,23 +29,32 @@ if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): src += ['drv_i2c.c'] # add can driver code -if GetDepend('BSP_USING_CAN'): +if GetDepend('BSP_USING_CAN') or GetDepend('BSP_USING_CAN0') or GetDepend('RT_USING_CAN'): src += ['drv_can.c'] # add adc driver code -if GetDepend(['BSP_USING_ADC']): +if GetDepend(['BSP_USING_ADC0']) or GetDepend('BSP_USING_ADC1'): src += ['drv_adc.c'] # add rtc driver code if GetDepend(['BSP_USING_RTC']): src += ['drv_rtc.c'] +# add spi flash driver code +if GetDepend('BSP_USING_SPI_FLASH'): + src += ['drv_spiflash.c'] + # add hwtimer driver code -if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1'): +if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMER'): src += ['drv_hwtimer.c'] # add pwm driver code -if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1'): +if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ + GetDepend('BSP_USING_GP32C4T0_PWM') or GetDepend('BSP_USING_GP32C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM'): src += ['drv_pwm.c'] # add pm driver code @@ -56,7 +67,7 @@ objs = objs + group src = [] cwd = GetCurrentDir() -include_path = [cwd] +include_path = [cwd + '/ES'] if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): src += ['bsp_driver_example/adc_vol_sample.c'] @@ -67,6 +78,9 @@ if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): if GetDepend('BSP_USING_EXAMPLE_I2C'): src += ['bsp_driver_example/i2c_sample.c'] +if GetDepend('BSP_USING_EXAMPLE_I2C_E2PROM'): + src += ['bsp_driver_example/i2c_e2_sample.c'] + if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'): src += ['bsp_driver_example/led_blink_sample.c'] diff --git a/bsp/essemi/es32f369x/drivers/board.c b/bsp/essemi/es32f369x/drivers/board.c index 1c2b834177..ea42df63dc 100644 --- a/bsp/essemi/es32f369x/drivers/board.c +++ b/bsp/essemi/es32f369x/drivers/board.c @@ -1,11 +1,24 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include @@ -13,7 +26,6 @@ #include "board.h" #include "drv_uart.h" #include "drv_gpio.h" -#include #include /** @@ -42,11 +54,68 @@ void NVIC_Configuration(void) *******************************************************************************/ void SystemClock_Config(void) { - /* hosc 12MHz, from hosc/3 pll to 96MHz */ - ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_96M); - /* SYSCLK 96MHz */ - ald_cmu_clock_config(CMU_CLOCK_PLL1, 96000000); + + SYSCFG_UNLOCK(); +#if ES_CMU_LRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#endif /*ES_CMU_LRC_EN*/ + +#if ES_CMU_LOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#endif /*ES_CMU_LOSC_EN*/ + +#if ES_CMU_HRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#endif /*ES_CMU_HRC_EN*/ + +#if ES_CMU_HOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#endif /*ES_CMU_HOSC_EN*/ + + SYSCFG_LOCK(); + +#if ES_CMU_PLL1_EN + /*PLL的源必须是4M*/ + ald_cmu_pll1_config(ES_PLL1_REFER_CLK, ES_PLL1_OUT_CLK); + + #if ES_CMU_PLL1_SAFE_EN + ald_cmu_pll_safe_config(ENABLE); + #else + ald_cmu_pll_safe_config(DISABLE); + #endif + +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); +#endif /*ES_CMU_PLL1_EN*/ + + ald_cmu_clock_config(ES_SYS_CLK_SOURSE, ES_SYS_CLK); + + ald_cmu_div_config(CMU_SYS,ES_CMU_SYS_DIV); + ald_cmu_div_config(CMU_HCLK_1,ES_CMU_HCLK_1_DIV); + ald_cmu_div_config(CMU_HCLK_2,ES_CMU_HCLK_2_DIV); + ald_cmu_div_config(CMU_PCLK_1,ES_CMU_PCLK_1_DIV); + ald_cmu_div_config(CMU_PCLK_2,ES_CMU_PCLK_2_DIV); + ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE); + +/*低功耗时钟使能*/ +#ifdef RT_USING_PM + SYSCFG_UNLOCK(); + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); + SYSCFG_LOCK(); +#endif + } /******************************************************************************* @@ -70,11 +139,21 @@ void SysTick_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); + ald_inc_tick(); rt_tick_increase(); /* leave interrupt */ rt_interrupt_leave(); } +/** + * This is the cmu interrupt service. + * + */ +void CMU_Handler(void) +{ + ald_cmu_irq_handler(); +} + /*@}*/ /** * This function will initial ES32F3 board. diff --git a/bsp/essemi/es32f369x/drivers/board.h b/bsp/essemi/es32f369x/drivers/board.h index 628c2f87fd..640cf44864 100644 --- a/bsp/essemi/es32f369x/drivers/board.h +++ b/bsp/essemi/es32f369x/drivers/board.h @@ -1,11 +1,24 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ // <<< Use Configuration Wizard in Context Menu >>> @@ -13,6 +26,7 @@ #define __BOARD_H__ #include +#include "es_conf_info_cmu.h" #define ES32F3_SRAM_SIZE 0x18000 #define ES32F3_SRAM_END (0x20000000 + ES32F3_SRAM_SIZE) diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c index f9444982d4..9576736bcd 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c @@ -18,11 +18,15 @@ #include #include + +#ifdef RT_USING_ADC + #define ADC_DEV_NAME "adc0" /* ADC 设备名称 */ #define ADC_DEV_CHANNEL 5 /* ADC 通道 5 PA1*/ #define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ #define CONVERT_BITS (1 << 12) /* 转换位数为12位 */ + static int adc_vol_sample(int argc, char *argv[]) { rt_adc_device_t adc_dev; @@ -55,3 +59,5 @@ static int adc_vol_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c index bfbd50095e..1133ad8d2b 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c @@ -18,7 +18,9 @@ #include #include "rtdevice.h" -#define CAN_DEV_NAME "can" /* CAN 设备名称 */ +#ifdef RT_USING_CAN + +#define CAN_DEV_NAME "can0" /* CAN 设备名称 */ static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */ static rt_device_t can_dev; /* CAN 设备句柄 */ @@ -142,3 +144,5 @@ int can_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(can_sample, can device sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c index e2e39664f3..025b4f26c0 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c @@ -17,6 +17,8 @@ #include #include +#ifdef RT_USING_HWTIMER + #define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ /* 定时器超时回调函数 */ @@ -83,3 +85,5 @@ static int hwtimer_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_e2_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_e2_sample.c new file mode 100644 index 0000000000..3bfd005e67 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_e2_sample.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 I2C 设备使用例程 + * 例程导出了 i2c_e2_sample 命令到控制终端 + * 命令调用格式：i2c_e2_sample + * 命令解释：使用默认的I2C总线设备i2c0 + * 程序功能：通过 I2C 设备写读e2prom，ST24C04WP。 +*/ + +/*ST24C04WP 有2个Block ：Block0 的从机地址为：0x50,Block1 的从机地址为：0x51 + 一个Block有 256字节，一页16字节,写只可在一页内(超过一页的范围后,会回到页的开始),读无页限制*/ +#include +#include + +#ifdef RT_USING_I2C + +#define I2C_BUS_NAME "i2c0" /*I2C总线设备名称 */ +#define SLAVE_ADDR 0x50 /*从机地址*/ +#define MEM_ADDR 0x00 /*从机的起始储存地址,范围：0x00到0xEF(例程写读范围：2页)*/ +#define ADDR_LEN 1 /*定义从机储存地址的长度，默认8位,1字节*/ +#define STR_LEN 16 /*接收发送的页数据长度 ,最大16*/ + +static rt_uint8_t mem_addr,rx_buffer[33] = { 0U }; /*读两页,需要32字节，字符串结束'\0'*/ +/*第一个字节' '用来放 E2PROM 的内存地址,最后一个字节'\0'作为子串的结束，不存入e2prom*/ +static rt_uint8_t tx_buffer1[STR_LEN + ADDR_LEN + 1] = " e2prom example !\0"; +static rt_uint8_t tx_buffer2[STR_LEN + ADDR_LEN + 1] = " ABCDEFGH12345678\0"; + +static void i2c_e2_sample(int argc, char *argv[]) +{ + struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */ + struct rt_i2c_msg i2c_msg[2]; /* I2C消息 */ + rt_size_t s_stat; + + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */ + + if( i2c_bus == RT_NULL) + { + rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME); + return; + } + + /*写T24C04WP + 如果 (MEM_ADDR & 0x0F) + STR_LEN <= 16, 写的范围为：(MEM_ADDR , MEM_ADDR + STR_LEN ) + (0x10 + MEM_ADDR , 0x10 + MEM_ADDR + STR_LEN ) + 如果 (MEM_ADDR & 0x0F) + STR_LEN > 16, 超出范围的部分会在页内循环写。*/ + tx_buffer1[0] = MEM_ADDR; + + /*初始化消息*/ + i2c_msg[0].addr = SLAVE_ADDR; /* 从机地址 */ + i2c_msg[0].len = ADDR_LEN + STR_LEN ; /* 写入的长度，地址+数据 */ + i2c_msg[0].buf = tx_buffer1; /* 待写入第一段数据 */ + i2c_msg[0].flags = RT_I2C_WR; /* I2C写 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1); /* 写入第一段数据 */ + + if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer1[1]); + else rt_kprintf("device %s write fail \n",I2C_BUS_NAME); + + tx_buffer2[0] = MEM_ADDR + 0x10; /*加一页*/ + i2c_msg[0].buf = tx_buffer2; /* 待写入第二段数据 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1); /* 写入第二段数据 */ + + if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer2[1]); + else rt_kprintf("device %s write fail \n",I2C_BUS_NAME); + + /*读T24C04WP 读2页的数据。读数据需要2条消息：第一条消息：发送读取的地址。 + 第二条消息：读取具体的数据。*/ + + mem_addr = MEM_ADDR & 0xF0; /*从页的开始读*/ + + i2c_msg[0].len = ADDR_LEN; + i2c_msg[0].buf = &mem_addr; + + i2c_msg[1].addr = SLAVE_ADDR; /* 从机地址 */ + i2c_msg[1].len = 32; /* 读取的数据长度：2*16 */ + i2c_msg[1].buf = rx_buffer; /* 数据存放地址 */ + i2c_msg[1].flags = RT_I2C_RD; /* I2C读 */ + s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,2); /* 读已写的2页 */ + + if( s_stat == 2 )rt_kprintf(" read successful \n messege : %s \n",rx_buffer); + else + rt_kprintf("read fail \n"); + + return; + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(i2c_e2_sample, i2c e2prom sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c index 4fd42baf41..c8a666609d 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -18,6 +30,8 @@ #include #include +#ifdef RT_USING_I2C + #define I2C_BUS_NAME "i2c0" /* I2C总线设备名称 */ #define SLAVE_ADDR 0x2D /* 从机地址 */ #define STR_LEN 16 /* 接收发送的数据长度 */ @@ -95,3 +109,5 @@ static void i2c_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(i2c_io_sample, i2c io sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c index b886876108..731dca4115 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -11,18 +23,26 @@ * 程序清单：这是一个 pm睡眠唤醒的使用例程 * 例程导出了 pm_sample 命令到控制终端 * 命令调用格式：pm_sample - * 命令解释：进入不同的睡眠模式，然后用按键唤醒 + * 命令解释：进入不同的睡眠模式，然后用按键唤醒。 * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。 + * 注意：进入睡眠前，如果有中断挂起（SYSTICK、UART、EXTI等），睡眠将被瞬间唤醒。 */ #include #include -#include "drv_pm.h" +#include "drv_pm.h" +#include "ald_gpio.h" + + +#ifdef RT_USING_PM #define PM_NAME "pm" /* 设备名称 */ #define WAKE_UP_PIN 51 /* 唤醒源 */ #define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ +/*部分芯片进入深度睡眠后，部分外设的部分寄存器可能会丢失*/ +#define SAVE_REG UART0 +#define SAVE_REG_TYPE UART_TypeDef struct pm_callback_t { @@ -64,14 +84,15 @@ void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data) /*进入睡眠前*/ case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1; rt_kprintf("\n\r##%d : ENTER ",g_pm_data.in_fun_times); - save_register(UART0,sizeof(UART_TypeDef),save_load_mem); /*备份寄存器的值*/ + /*进入深度睡眠后，部分外设的部分寄存器可能会丢失*/ + save_register(SAVE_REG,sizeof(SAVE_REG_TYPE),save_load_mem); /*备份寄存器的值*/ g_pm_data.in_fun_times++; /*进入睡眠次数+1*/ break; /*睡眠唤醒后*/ case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/ - load_register(UART0,sizeof(UART_TypeDef),save_load_mem); /*还原寄存器的值*/ + load_register(SAVE_REG,sizeof(SAVE_REG_TYPE),save_load_mem); /*还原寄存器的值*/ rt_kprintf("\n\rEXIT\n\r"); - rt_pm_release(mode); /*释放休眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); /*进无休眠模式*/ return; default: break; @@ -118,7 +139,7 @@ static void pm_test(void *parameter) /*设置回调函数和私有数据*/ rt_pm_notify_set(sleep_in_out_callback,RT_NULL); - + while(i < SLEEP_TIMES) { @@ -130,9 +151,12 @@ static void pm_test(void *parameter) g_pm_data.flag = 2; } + + /*彻底释放无休眠模式*/ + rt_pm_release_all(PM_SLEEP_MODE_NONE); /*请求选择的休眠模式*/ - rt_pm_request(in_mode[i%6]); + rt_pm_request(in_mode[i%6]); rt_thread_mdelay(500); @@ -142,14 +166,19 @@ static void pm_test(void *parameter) rt_thread_mdelay(500); } - /*释放选择的休眠模式*/ - rt_pm_release(in_mode[i%6]); + /*释放选择的休眠模式 ，彻底释放*/ + rt_pm_release_all(in_mode[i%6]); i++; } - /*清除回调函数和私有数据*/ + + /*切换为无睡眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); + + /*清除回调函数和私有数据*/ rt_pm_notify_set(RT_NULL,RT_NULL); + rt_kprintf("thread pm_test close\n\r"); } @@ -187,3 +216,5 @@ static int pm_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pm_sample, pm sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c index df82c1b41c..8d12b74e15 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c @@ -17,9 +17,12 @@ #include #include -#define LED_PIN_NUM 19 /* PF1 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ + +#ifdef RT_USING_PWM + +#define LED_PIN_NUM 37 /* PF1 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ #define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ -#define PWM_DEV_CHANNEL 2 /* PA1 PWM通道 */ +#define PWM_DEV_CHANNEL 1 /* PWM通道 */ struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ @@ -70,3 +73,5 @@ static int pwm_led_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pwm_led_sample, pwm sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c index 711a3a0ebb..d66b9db9df 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c @@ -17,6 +17,8 @@ #include #include +#ifdef RT_USING_RTC + static int rtc_sample(int argc, char *argv[]) { rt_err_t ret = RT_EOK; @@ -39,7 +41,7 @@ static int rtc_sample(int argc, char *argv[]) } /* 延时3秒 */ - rt_thread_mdelay(3000); + rt_thread_mdelay(3000); /* 获取时间 */ now = time(RT_NULL); @@ -49,3 +51,5 @@ static int rtc_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(rtc_sample, rtc sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c index 994888cdb0..6f6e730288 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -17,13 +29,14 @@ #include #include +#ifdef RT_USING_SPI + #define SPI_DEVICE_NAME "spi00" #define BUF_LEN 16 static void spi_io_sample(int argc, char *argv[]) { struct rt_spi_device * spi_dev; /* spi设备的句柄 */ - struct rt_spi_configuration spi_config; rt_uint8_t i,buffer[BUF_LEN] = { 0U }; rt_err_t s_stat; rt_err_t result; @@ -37,23 +50,8 @@ static void spi_io_sample(int argc, char *argv[]) return; } - - /* 清空配置结构体 */ - rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration)); - - spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ - spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ - spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ - spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ - spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ - spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ - - spi_config.data_width = 8; /* 数据长度：8 */ - - spi_config.max_hz = 2000000; /* 最快时钟频率 */ - /* 配置SPI设备 */ - s_stat = rt_spi_configure(spi_dev,&spi_config); + s_stat = rt_spi_configure(spi_dev,&(spi_dev->config)); if(s_stat != RT_EOK) { @@ -150,3 +148,5 @@ static void spi_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(spi_io_sample, spi sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_adc.c b/bsp/essemi/es32f369x/drivers/drv_adc.c index 79afc06123..716fddcfa4 100644 --- a/bsp/essemi/es32f369x/drivers/drv_adc.c +++ b/bsp/essemi/es32f369x/drivers/drv_adc.c @@ -1,26 +1,44 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-04-03 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include "board.h" -#include "drv_adc.h" -#include -#include +#include "drv_adc.h" #ifdef RT_USING_ADC /* define adc instance */ + +#ifdef BSP_USING_ADC0 static struct rt_adc_device _device_adc0; +#endif /*BSP_USING_ADC0*/ + +#ifdef BSP_USING_ADC1 +static struct rt_adc_device _device_adc1; +#endif /*BSP_USING_ADC1*/ /* enable or disable adc */ static rt_err_t es32f3_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) @@ -48,7 +66,8 @@ static adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel) /* Initialize ADC pin */ gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.odos = GPIO_OPEN_DRAIN; gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1; gpio_initstruct.flt = GPIO_FILTER_DISABLE; @@ -60,77 +79,69 @@ static adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel) { case 0: es32f3_channel = ADC_CHANNEL_0; - ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH0_GPIO, ES_GPIO_ADC_CH0_PIN, &gpio_initstruct); break; case 1: es32f3_channel = ADC_CHANNEL_1; - ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH1_GPIO, ES_GPIO_ADC_CH1_PIN, &gpio_initstruct); break; case 2: es32f3_channel = ADC_CHANNEL_2; - ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH2_GPIO, ES_GPIO_ADC_CH2_PIN, &gpio_initstruct); break; case 3: es32f3_channel = ADC_CHANNEL_3; - ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH3_GPIO, ES_GPIO_ADC_CH3_PIN, &gpio_initstruct); break; case 4: es32f3_channel = ADC_CHANNEL_4; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH4_GPIO, ES_GPIO_ADC_CH4_PIN, &gpio_initstruct); break; case 5: es32f3_channel = ADC_CHANNEL_5; - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH5_GPIO, ES_GPIO_ADC_CH5_PIN, &gpio_initstruct); break; case 6: es32f3_channel = ADC_CHANNEL_6; - ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH6_GPIO, ES_GPIO_ADC_CH6_PIN, &gpio_initstruct); break; case 7: es32f3_channel = ADC_CHANNEL_7; - ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH7_GPIO, ES_GPIO_ADC_CH7_PIN, &gpio_initstruct); break; case 8: es32f3_channel = ADC_CHANNEL_8; - ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH8_GPIO, ES_GPIO_ADC_CH8_PIN, &gpio_initstruct); break; case 9: es32f3_channel = ADC_CHANNEL_9; - ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH9_GPIO, ES_GPIO_ADC_CH9_PIN, &gpio_initstruct); break; case 10: es32f3_channel = ADC_CHANNEL_10; - ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH10_GPIO, ES_GPIO_ADC_CH10_PIN, &gpio_initstruct); break; case 11: es32f3_channel = ADC_CHANNEL_11; - ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH11_GPIO, ES_GPIO_ADC_CH11_PIN, &gpio_initstruct); break; case 12: es32f3_channel = ADC_CHANNEL_12; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH12_GPIO, ES_GPIO_ADC_CH12_PIN, &gpio_initstruct); break; case 13: es32f3_channel = ADC_CHANNEL_13; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH13_GPIO, ES_GPIO_ADC_CH13_PIN, &gpio_initstruct); break; case 14: es32f3_channel = ADC_CHANNEL_14; - ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH14_GPIO, ES_GPIO_ADC_CH14_PIN, &gpio_initstruct); break; case 15: es32f3_channel = ADC_CHANNEL_15; - ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); - break; - case 16: - es32f3_channel = ADC_CHANNEL_16; - break; - case 17: - es32f3_channel = ADC_CHANNEL_17; - break; - case 18: - es32f3_channel = ADC_CHANNEL_18; + ald_gpio_init(ES_GPIO_ADC_CH15_GPIO, ES_GPIO_ADC_CH15_PIN, &gpio_initstruct); break; + default: break; } @@ -149,7 +160,7 @@ static rt_err_t es32f3_get_adc_value(struct rt_adc_device *device, rt_uint32_t c /* config adc channel */ nm_config.ch = es32f3_adc_get_channel(channel); nm_config.idx = ADC_NCH_IDX_1; - nm_config.samp = ADC_SAMPLETIME_4; + nm_config.samp = ES_ADC0_NCH_SAMPLETIME; ald_adc_normal_channel_config(_hadc, &nm_config); ald_adc_normal_start(_hadc); @@ -169,23 +180,51 @@ static const struct rt_adc_ops es32f3_adc_ops = int rt_hw_adc_init(void) { int result = RT_EOK; - static adc_handle_t _h_adc0; + adc_handle_t _h_adc; /* adc function initialization */ - _h_adc0.perh = ADC0; - _h_adc0.init.align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan = DISABLE; - _h_adc0.init.cont = DISABLE; - _h_adc0.init.disc = ADC_ALL_DISABLE; - _h_adc0.init.disc_nr = ADC_DISC_NR_1; - _h_adc0.init.data_bit = ADC_CONV_BIT_12; - _h_adc0.init.div = ADC_CKDIV_128; - _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; - _h_adc0.init.n_ref = ADC_NEG_REF_VSS; - _h_adc0.init.p_ref = ADC_POS_REF_VDD; - ald_adc_init(&_h_adc0); + _h_adc.init.scan = DISABLE; + _h_adc.init.cont = DISABLE; + _h_adc.init.disc = ADC_ALL_DISABLE; + _h_adc.init.disc_nr = ADC_DISC_NR_1; + _h_adc.init.nch_nr = ADC_NCH_NR_16; + _h_adc.init.nche_sel = ADC_NCHESEL_MODE_ALL; + _h_adc.init.cont = DISABLE; + _h_adc.init.n_ref = ADC_NEG_REF_VSS; + _h_adc.init.p_ref = ADC_POS_REF_VDD; - rt_hw_adc_register(&_device_adc0, "adc0", &es32f3_adc_ops, &_h_adc0); +#ifdef BSP_USING_ADC0 + + static adc_handle_t _h_adc0; + + _h_adc0.init = _h_adc.init; + + _h_adc0.perh = ADC0; + _h_adc0.init.align = ES_ADC0_ALIGN; + _h_adc0.init.data_bit = ES_ADC0_DATA_BIT; + _h_adc0.init.div = ES_ADC0_CLK_DIV; + ald_adc_init(&_h_adc0); + + rt_hw_adc_register(&_device_adc0, ES_DEVICE_NAME_ADC0, &es32f3_adc_ops, &_h_adc0); + +#endif /*BSP_USING_ADC0*/ + +#ifdef BSP_USING_ADC1 + + static adc_handle_t _h_adc1; + + _h_adc1.init = _h_adc.init; + + _h_adc1.perh = ADC1; + _h_adc1.init.align = ES_ADC1_ALIGN; + _h_adc1.init.data_bit = ES_ADC1_DATA_BIT; + _h_adc1.init.div = ES_ADC1_CLK_DIV; + ald_adc_init(&_h_adc1); + + rt_hw_adc_register(&_device_adc1, ES_DEVICE_NAME_ADC1, &es32f3_adc_ops, &_h_adc1); + +#endif /*BSP_USING_ADC1*/ + return result; } diff --git a/bsp/essemi/es32f369x/drivers/drv_adc.h b/bsp/essemi/es32f369x/drivers/drv_adc.h index eaddd67407..6585b44cf0 100644 --- a/bsp/essemi/es32f369x/drivers/drv_adc.h +++ b/bsp/essemi/es32f369x/drivers/drv_adc.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-04-03 wangyq the first version + * 2019-04-03 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_ADC_H__ #define DRV_ADC_H__ +#include "es_conf_info_adc.h" + int rt_hw_adc_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_can.c b/bsp/essemi/es32f369x/drivers/drv_can.c index 04f4f161d7..6e7456b9b6 100644 --- a/bsp/essemi/es32f369x/drivers/drv_can.c +++ b/bsp/essemi/es32f369x/drivers/drv_can.c @@ -1,51 +1,93 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include "drv_can.h" -#ifdef BSP_USING_CAN +#ifdef RT_USING_CAN static struct es32f3_can can; -/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc) 48 / ((1 + 3 + 2) * 8) = 1MHz */ -static const struct es32f3_baud_rate_tab can_baud_rate_tab[] = -{ - {CAN1MBaud, 8}, - {CAN800kBaud, 10}, - {CAN500kBaud, 16}, - {CAN250kBaud, 32}, - {CAN125kBaud, 64}, - {CAN100kBaud, 80}, - {CAN50kBaud, 160}, - {CAN20kBaud, 400}, - {CAN10kBaud, 800} -}; -static rt_uint32_t get_can_baud_index(rt_uint32_t baud) -{ - rt_uint32_t len, index; - - len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); - for (index = 0; index < len; index++) +static rt_uint32_t get_can_baud_index(rt_uint32_t baud,can_init_t * init) +{ +/* attention !!! baud calculation example: Pclk / ((1 + seg1 + seg2) * psc) Pclk=48 / ((1 + seg1=3 + seg2=2) * 8) = 1MHz */ + double target,temp,min; + uint32_t i,j,j_max,near = 0; + target = (double)(ald_cmu_get_pclk1_clock()); + target/= baud; /*计算误差1*/ + + min = 0xFFFFFFFF; + + for(i = 1 + 16 + 8 ;i > 2;i--) /*SYNC_SEG + SEG1 + SEG2*/ { - if (can_baud_rate_tab[index].baud_rate == baud) - return index; + j_max = target/i/(0.98) + 1; /*缩小范围*/ + j_max = (j_max > 1024) ? (1024) : (j_max); + + for(j = target/i/1.02 ;j < j_max;j++) + { + temp = target/i/j; /*计算误差2*/ + temp = (temp > 1) ? (temp - 1) : (1 - temp); + temp+= ((1.0 * i * j) / 0xFFFFFFFF) ; + + if(temp < min) + { + if(temp > 0.000001) + { + near = (i<<16) + j; + min = temp; + } + else + { + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + } + } } - return 0; /* default baud is CAN1MBaud */ + if(min < 0.01) + { + i = near>>16; + j = near % (1<<16); + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + else + { + return 1; + } } + static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg) { struct es32f3_can *drv_can; - rt_uint32_t baud_index; RT_ASSERT(can_device); RT_ASSERT(cfg); @@ -56,7 +98,7 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.ttcm = DISABLE; drv_can->CanHandle.init.abom = ENABLE; drv_can->CanHandle.init.awk = DISABLE; - drv_can->CanHandle.init.artx = DISABLE; + drv_can->CanHandle.init.artx = (type_func_t)ES_CAN0_AUTO_BAN_RE_T; drv_can->CanHandle.init.rfom = DISABLE; drv_can->CanHandle.init.txmp = ENABLE; @@ -75,12 +117,13 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK; break; } - - baud_index = get_can_baud_index(cfg->baud_rate); - drv_can->CanHandle.init.sjw = CAN_SJW_1; - drv_can->CanHandle.init.seg1 = CAN_SEG1_3; - drv_can->CanHandle.init.seg2 = CAN_SEG2_2; - drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; + /*配置参数*/ + if(get_can_baud_index(cfg->baud_rate,&(drv_can->CanHandle.init))) + { + return -RT_ERROR; + } + drv_can->CanHandle.init.sjw = (can_sjw_t)(cfg->reserved); + /* init can */ if (ald_can_init(&drv_can->CanHandle) != OK) { @@ -95,8 +138,12 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *arg) { rt_uint32_t argval; + struct es32f3_can *drv_can; + +#ifdef RT_CAN_USING_HDR struct rt_can_filter_config *filter_cfg; +#endif RT_ASSERT(can_device != RT_NULL); drv_can = (struct es32f3_can *)can_device->parent.user_data; @@ -108,17 +155,24 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar argval = (rt_uint32_t) arg; if (argval == RT_DEVICE_FLAG_INT_RX) { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | - CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, DISABLE); } else if (argval == RT_DEVICE_FLAG_INT_TX) { ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, DISABLE); } else if (argval == RT_DEVICE_CAN_INT_ERR) - { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), DISABLE); + { + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, DISABLE); } break; case RT_DEVICE_CTRL_SET_INT: @@ -127,29 +181,36 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar { NVIC_SetPriority(CAN0_RX0_IRQn, 1); NVIC_EnableIRQ(CAN0_RX0_IRQn); - - NVIC_SetPriority(CAN0_RX0_IRQn, 1); - NVIC_EnableIRQ(CAN0_RX0_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | - CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, ENABLE); + } else if (argval == RT_DEVICE_FLAG_INT_TX) { NVIC_SetPriority(CAN0_TX_IRQn, 1); NVIC_EnableIRQ(CAN0_TX_IRQn); - + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, ENABLE); } else if (argval == RT_DEVICE_CAN_INT_ERR) { NVIC_SetPriority(CAN0_EXCEPTION_IRQn, 1); NVIC_EnableIRQ(CAN0_EXCEPTION_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, ENABLE); + } break; +#ifdef RT_CAN_USING_HDR case RT_CAN_CMD_SET_FILTER: if (RT_NULL == arg) { @@ -161,20 +222,70 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar filter_cfg = (struct rt_can_filter_config *)arg; /* get default filter */ for (int i = 0; i < filter_cfg->count; i++) - { - drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + { + + /*默认过滤表判断*/ + if(filter_cfg->items[i].hdr < drv_can->device.config.maxhdr) + drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + else + drv_can->FilterConfig.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; + + if(filter_cfg->items[i].mode) + { + /*标识符列表模式： 类型匹配 ，id匹配为：接收的id = 配置的id + 或者 = 配置的mask ，通过*/ + /*扩展帧*/ + if(filter_cfg->items[i].ide) + { +// filter_cfg->items[i].id = filter_cfg->items[i].id ; /*id 29 位*/ + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 3) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + else /*标准帧*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id << 18); + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 21) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + } + else + { + /*标识符掩码模式*/ + /*扩展帧*/ + if(filter_cfg->items[i].ide) + { + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<3; + } + else /*标准帧*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id)<<18; + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<21; + } + +#if ES_C_CAN_FILTER_FRAME_TYPE + /*匹配类型*/ + filter_cfg->items[i].mask |= 0x6; +#endif + + } + drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF; drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) | (filter_cfg->items[i].ide << 2) | (filter_cfg->items[i].rtr << 1)) & 0xFFFF; drv_can->FilterConfig.mask_id_high = (filter_cfg->items[i].mask >> 16) & 0xFFFF; drv_can->FilterConfig.mask_id_low = filter_cfg->items[i].mask & 0xFFFF; + drv_can->FilterConfig.mode = (can_filter_mode_t)filter_cfg->items[i].mode; /* Filter conf */ ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); } } break; + +#endif case RT_CAN_CMD_SET_MODE: argval = (rt_uint32_t) arg; if (argval != RT_CAN_MODE_NORMAL && @@ -192,18 +303,7 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar break; case RT_CAN_CMD_SET_BAUD: argval = (rt_uint32_t) arg; - if (argval != CAN1MBaud && - argval != CAN800kBaud && - argval != CAN500kBaud && - argval != CAN250kBaud && - argval != CAN125kBaud && - argval != CAN100kBaud && - argval != CAN50kBaud && - argval != CAN20kBaud && - argval != CAN10kBaud) - { - return -RT_ERROR; - } + if (argval != drv_can->device.config.baud_rate) { drv_can->device.config.baud_rate = argval; @@ -312,6 +412,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t } /* clear TIR */ h_can->perh->TxMailBox[box_num].TXID &= CAN_TXID0_TXMREQ_MSK; + /* Set up the Id */ if (RT_CAN_STDID == pmsg->ide) { @@ -336,7 +437,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t ((uint32_t)pmsg->data[0] << CAN_TXDL0_BYTE0_POSS)); /* Request transmission */ SET_BIT(h_can->perh->TxMailBox[box_num].TXID, CAN_TXID0_TXMREQ_MSK); - + return RT_EOK; } else @@ -346,6 +447,8 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t return -RT_ERROR; } + + } static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) @@ -427,8 +530,12 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO0) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } + /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK); } @@ -444,8 +551,12 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO1) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } + /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK); } @@ -575,30 +686,30 @@ void CAN0_EXCEPTION_Handler(void) int rt_hw_can_init(void) { gpio_init_t h_gpio; - struct can_configure config = CANDEFAULTCONFIG; - - config.privmode = RT_CAN_MODE_NOPRIV; - config.ticks = 50; -#ifdef RT_CAN_USING_HDR - config.maxhdr = 14; -#endif /* Initialize can common pin */ h_gpio.odos = GPIO_PUSH_PULL; h_gpio.pupd = GPIO_PUSH_UP; - h_gpio.podrv = GPIO_OUT_DRIVE_1; - h_gpio.nodrv = GPIO_OUT_DRIVE_0_1; + h_gpio.podrv = GPIO_OUT_DRIVE_6; + h_gpio.nodrv = GPIO_OUT_DRIVE_6; h_gpio.flt = GPIO_FILTER_DISABLE; h_gpio.type = GPIO_TYPE_TTL; - h_gpio.func = GPIO_FUNC_3; +#if defined(ES_CAN0_RX_GPIO_FUNC)&&defined(ES_CAN0_RX_GPIO_PORT)&&defined(ES_CAN0_RX_GPIO_PIN) /* Initialize can rx pin */ - h_gpio.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_8, &h_gpio); - + h_gpio.mode = GPIO_MODE_INPUT; + h_gpio.func = ES_CAN0_RX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_RX_GPIO_PORT, ES_CAN0_RX_GPIO_PIN, &h_gpio); +#endif + + +#if defined(ES_CAN0_TX_GPIO_FUNC)&&defined(ES_CAN0_TX_GPIO_PORT)&&defined(ES_CAN0_TX_GPIO_PIN) /* Initialize can tx pin */ - h_gpio.mode = GPIO_MODE_OUTPUT; - ald_gpio_init(GPIOB, GPIO_PIN_9, &h_gpio); + h_gpio.mode = GPIO_MODE_OUTPUT; + h_gpio.func = ES_CAN0_TX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_TX_GPIO_PORT, ES_CAN0_TX_GPIO_PIN, &h_gpio); +#endif + /* config default filter */ can_filter_t filter = {0}; @@ -607,15 +718,21 @@ int rt_hw_can_init(void) filter.mask_id_high = 0x0000; filter.mask_id_low = 0x0000; filter.fifo = CAN_FILTER_FIFO0; - filter.number = 0; + filter.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; filter.mode = CAN_FILTER_MODE_MASK; filter.scale = CAN_FILTER_SCALE_32; filter.active = ENABLE; can.FilterConfig = filter; - can.device.config = config; + can.device.config = (struct can_configure)ES_CAN0_CONFIG; +#ifdef RT_CAN_USING_HDR + can.device.config.maxhdr = 14; +#endif + can.device.config.privmode = RT_CAN_MODE_NOPRIV; + can.device.config.ticks = 50; + can.device.config.reserved = ES_CAN0_SJW; /* register CAN1 device */ - rt_hw_can_register(&can.device, "can", &_can_ops, &can); + rt_hw_can_register(&can.device, ES_DEVICE_NAME_CAN0, &_can_ops, &can); return 0; } diff --git a/bsp/essemi/es32f369x/drivers/drv_can.h b/bsp/essemi/es32f369x/drivers/drv_can.h index cffe4b81b0..d7eeb859aa 100644 --- a/bsp/essemi/es32f369x/drivers/drv_can.h +++ b/bsp/essemi/es32f369x/drivers/drv_can.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_CAN_H__ @@ -14,16 +27,9 @@ #include #include #include +#include "es_conf_info_can.h" -#include -#include - -struct es32f3_baud_rate_tab -{ - rt_uint32_t baud_rate; - rt_uint32_t config_data; -}; - +#ifdef RT_USING_CAN /* es32f3 can device */ struct es32f3_can { @@ -34,4 +40,5 @@ struct es32f3_can int rt_hw_can_init(void); +#endif #endif /*DRV_CAN_H__ */ diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.c b/bsp/essemi/es32f369x/drivers/drv_gpio.c index fa39a31ea5..8ce6ab7aa8 100644 --- a/bsp/essemi/es32f369x/drivers/drv_gpio.c +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.c @@ -1,107 +1,40 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ -#include -#include #include "board.h" #include "drv_gpio.h" -#include -#include + +/*管脚映射在 es_conf_info_map.h 的 pins[] 中*/ #ifdef RT_USING_PIN -#define __ES32F3_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} -#define __ES32F3_PIN_DEFAULT {-1, 0, 0} - -/* ES32F3 GPIO driver */ -struct pin_index -{ - int index; - GPIO_TypeDef *gpio; - uint32_t pin; -}; - -static const struct pin_index pins[] = -{ - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(2, C, 13), - __ES32F3_PIN(3, C, 14), - __ES32F3_PIN(4, C, 15), - __ES32F3_PIN(5, H, 0), - __ES32F3_PIN(6, H, 1), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(8, C, 0), - __ES32F3_PIN(9, C, 1), - __ES32F3_PIN(10, C, 2), - __ES32F3_PIN(11, C, 3), - __ES32F3_PIN(12, H, 3), - __ES32F3_PIN(13, H, 4), - __ES32F3_PIN(14, A, 0), - __ES32F3_PIN(15, A, 1), - __ES32F3_PIN(16, A, 2), - __ES32F3_PIN(17, A, 3), - __ES32F3_PIN(18, F, 0), - __ES32F3_PIN(19, F, 1), - __ES32F3_PIN(20, A, 4), - __ES32F3_PIN(21, A, 5), - __ES32F3_PIN(22, A, 6), - __ES32F3_PIN(23, A, 7), - __ES32F3_PIN(24, C, 4), - __ES32F3_PIN(25, C, 5), - __ES32F3_PIN(26, B, 0), - __ES32F3_PIN(27, B, 1), - __ES32F3_PIN(28, B, 2), - __ES32F3_PIN(29, B, 10), - __ES32F3_PIN(30, B, 11), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(33, B, 12), - __ES32F3_PIN(34, B, 13), - __ES32F3_PIN(35, B, 14), - __ES32F3_PIN(36, B, 15), - __ES32F3_PIN(37, C, 6), - __ES32F3_PIN(38, C, 7), - __ES32F3_PIN(39, C, 8), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(46, A, 13), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(49, A, 14), - __ES32F3_PIN(50, A, 15), - __ES32F3_PIN(51, C, 10), - __ES32F3_PIN(52, C, 11), - __ES32F3_PIN(53, C, 12), - __ES32F3_PIN(54, D, 2), - __ES32F3_PIN(55, B, 3), - __ES32F3_PIN(56, B, 4), - __ES32F3_PIN(57, B, 5), - __ES32F3_PIN(58, B, 6), - __ES32F3_PIN(59, B, 7), - __ES32F3_PIN(60, H, 2), - __ES32F3_PIN(61, B, 8), - __ES32F3_PIN(62, B, 9), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, -}; struct pin_irq_map { rt_uint16_t pinbit; IRQn_Type irqno; }; + static const struct pin_irq_map pin_irq_map[] = { {GPIO_PIN_0, EXTI0_IRQn}, @@ -140,7 +73,151 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { -1, 0, RT_NULL, RT_NULL}, { -1, 0, RT_NULL, RT_NULL}, { -1, 0, RT_NULL, RT_NULL}, -}; +}; + +#ifdef ES_CONF_EXTI_IRQ_0 + +RT_WEAK void irq_pin0_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 0\r\n"); +} +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 + +RT_WEAK void irq_pin1_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 1\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 + + RT_WEAK void irq_pin2_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 2\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 + +RT_WEAK void irq_pin3_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 3\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 + +RT_WEAK void irq_pin4_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 4\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 + +RT_WEAK void irq_pin5_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 5\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 + +RT_WEAK void irq_pin6_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 6\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 + +RT_WEAK void irq_pin7_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 7\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 + +RT_WEAK void irq_pin8_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 8\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 + +RT_WEAK void irq_pin9_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 9\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 + +RT_WEAK void irq_pin10_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 10\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 + +RT_WEAK void irq_pin11_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 11\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 + +RT_WEAK void irq_pin12_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 12\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 + +RT_WEAK void irq_pin13_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 13\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 + +RT_WEAK void irq_pin14_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 14\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 + +RT_WEAK void irq_pin15_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 15\r\n"); +} + +#endif + #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) const struct pin_index *get_pin(uint8_t pin) @@ -200,8 +277,8 @@ void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; gpio_initstruct.nodrv = GPIO_OUT_DRIVE_0_1; gpio_initstruct.type = GPIO_TYPE_CMOS; - gpio_initstruct.pupd = GPIO_FLOATING; - gpio_initstruct.odos = GPIO_PUSH_PULL; + gpio_initstruct.odos = GPIO_PUSH_PULL; + gpio_initstruct.flt = GPIO_FILTER_DISABLE; if (mode == PIN_MODE_OUTPUT) { @@ -364,7 +441,11 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin, ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct); /* Configure GPIO_InitStructure */ gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.func = GPIO_FUNC_1; + gpio_initstruct.odos = GPIO_PUSH_PULL; + gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; + gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_initstruct.func = GPIO_FUNC_1; + gpio_initstruct.flt = GPIO_FILTER_DISABLE; switch (pin_irq_hdr_tab[irqindex].mode) { case PIN_IRQ_MODE_RISING: @@ -408,18 +489,9 @@ const static struct rt_pin_ops _es32f3_pin_ops = es32f3_pin_attach_irq, es32f3_pin_detach_irq, es32f3_pin_irq_enable, - RT_NULL, + /*RT_NULL,*/ }; -int rt_hw_pin_init(void) -{ - int result; - ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); - result = rt_device_pin_register("pin", &_es32f3_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) { uint16_t irqno; @@ -560,4 +632,44 @@ void EXTI15_Handler(void) rt_interrupt_leave(); } +int rt_hw_pin_init(void) +{ + int result; + + +#ifdef ES_INIT_GPIOS + + rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t); + +#endif + + ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); + + result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f3_pin_ops, RT_NULL); + + if(result != RT_EOK)return result; + +#ifdef ES_INIT_GPIOS + + for(i = 0;i < gpio_conf_num;i++) + { + rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode); + + if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD)) + rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level); + + if(!gpio_conf_all[i].irq_en)continue; + + rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL); + rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en); + } + +#endif + + + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.h b/bsp/essemi/es32f369x/drivers/drv_gpio.h index fef8fb8487..8489e625d5 100644 --- a/bsp/essemi/es32f369x/drivers/drv_gpio.h +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_GPIO_H__ #define DRV_GPIO_H__ +#include "es_conf_info_gpio.h" + int rt_hw_pin_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_hwtimer.c b/bsp/essemi/es32f369x/drivers/drv_hwtimer.c index f693137ae7..e0fd46a36b 100644 --- a/bsp/essemi/es32f369x/drivers/drv_hwtimer.c +++ b/bsp/essemi/es32f369x/drivers/drv_hwtimer.c @@ -1,21 +1,33 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-3-19 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include + #ifdef RT_USING_HWTIMER @@ -26,53 +38,167 @@ struct es32f3_hwtimer_dev IRQn_Type IRQn; }; -#ifdef BSP_USING_HWTIMER0 -static struct es32f3_hwtimer_dev hwtimer0; +#ifdef BSP_USING_AD16C4T0_HWTIMER +static struct es32f3_hwtimer_dev ad16c4t0_hwtimer; + +static struct rt_hwtimer_info ad16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T0_HWTIMER_MODE +}; + +void AD16C4T0_UP_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent); +} + +#endif + +#ifdef BSP_USING_AD16C4T1_HWTIMER + +static struct es32f3_hwtimer_dev ad16c4t1_hwtimer; + +static struct rt_hwtimer_info ad16c4t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T1_HWTIMER_MODE +}; + +void AD16C4T1_UP_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&ad16c4t1_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP32C4T0_HWTIMER + +static struct es32f3_hwtimer_dev gp32c4t0_hwtimer; + +static struct rt_hwtimer_info gp32c4t0_info = +{ + + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV , /* maximum count frequency */ + ( ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ + 0xFFFFFFFF, /* counter maximum value */ + ES_GP32C4T0_HWTIMER_MODE +}; + +void GP32C4T0_Handler(void) +{ + ald_timer_clear_flag_status(gp32c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp32c4t0_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP32C4T1_HWTIMER + +static struct es32f3_hwtimer_dev gp32c4t1_hwtimer; + +static struct rt_hwtimer_info gp32c4t1_info = +{ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV ), /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ + 0xFFFFFFFF, /* counter maximum value */ + ES_GP32C4T1_HWTIMER_MODE +}; + +void GP32C4T1_Handler(void) +{ + ald_timer_clear_flag_status(gp32c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp32c4t1_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP16C4T0_HWTIMER + +static struct es32f3_hwtimer_dev gp16c4t0_hwtimer; + +static struct rt_hwtimer_info gp16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T0_HWTIMER_MODE +}; + +void GP16C4T0_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP16C4T1_HWTIMER + +static struct es32f3_hwtimer_dev gp16c4t1_hwtimer; + +static struct rt_hwtimer_info gp16c4t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T1_HWTIMER_MODE +}; + +void GP16C4T1_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_BS16T0_HWTIMER + +static struct es32f3_hwtimer_dev bs16t0_hwtimer; + +static struct rt_hwtimer_info bs16t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T0_HWTIMER_MODE +}; void BS16T0_Handler(void) { - ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer0.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) - { - ald_timer_base_stop(hwtimer0.hwtimer_periph); - } + ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t0_hwtimer.parent); } -#endif -#ifdef BSP_USING_HWTIMER1 -static struct es32f3_hwtimer_dev hwtimer1; -/* can not use when UART2 Handler is enabled */ +#endif +#ifdef BSP_USING_BS16T1_HWTIMER + +static struct es32f3_hwtimer_dev bs16t1_hwtimer; + +static struct rt_hwtimer_info bs16t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T1_HWTIMER_MODE +}; + void BS16T1_Handler(void) { - /* if BS16T1 it */ - if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer1.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) - { - ald_timer_base_stop(hwtimer1.hwtimer_periph); - } - } + ald_timer_clear_flag_status(bs16t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t1_hwtimer.parent); } -#endif -static struct rt_hwtimer_info es32f3_hwtimer_info = -{ - 96000000, /* maximum count frequency */ - 1, /* minimum count frequency */ - 65535, /* counter maximum value */ - HWTIMER_CNTMODE_UP -}; +#endif static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) { struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info; + + RT_ASSERT(hwtimer != RT_NULL); if (1 == state) @@ -81,19 +207,21 @@ static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); NVIC_EnableIRQ(hwtimer->IRQn); } - hwtimer->parent.freq = ald_cmu_get_pclk1_clock(); - es32f3_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock(); - es32f3_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock(); + + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + hwtimer_info->maxfreq = hwtimer->parent.freq; + hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF; + } static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) { - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; RT_ASSERT(hwtimer != RT_NULL); - + WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); ald_timer_base_start(hwtimer->hwtimer_periph); @@ -135,10 +263,37 @@ static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer, { case HWTIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; - if (freq != ald_cmu_get_pclk1_clock()) - { - ret = -RT_ERROR; + + ret = -RT_ERROR; + + if(freq) + { + double temp,target; + temp = (double)ald_cmu_get_pclk1_clock(); + target = temp/freq; + + if(target < 0x10001) /*最大分频 = max(PRES)+1*/ + { + temp = target - (int)(target); + + if((temp > 0.998)&&(target < 0x10000)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target; + ret = RT_EOK; + } + if((temp < 0.002)&&(target >= 0x1)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1; + ret = RT_EOK; + } + + } + + if(ret == RT_EOK) /*更新信息*/ + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + } + break; case HWTIMER_CTRL_STOP: @@ -166,24 +321,124 @@ int rt_hw_hwtimer_init(void) { rt_err_t ret = RT_EOK; -#ifdef BSP_USING_HWTIMER0 - static timer_handle_t _hwtimer_periph0; - _hwtimer_periph0.perh = BS16T0; - hwtimer0.IRQn = BS16T0_IRQn; - hwtimer0.hwtimer_periph = &_hwtimer_periph0; - hwtimer0.parent.info = &es32f3_hwtimer_info; - hwtimer0.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); +#ifdef BSP_USING_AD16C4T0_HWTIMER + static timer_handle_t ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer_periph.perh = AD16C4T0; + ad16c4t0_hwtimer.IRQn = AD16C4T0_UP_IRQn; + + ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1; + ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer.parent.info = &ad16c4t0_info; + ad16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer); #endif -#ifdef BSP_USING_HWTIMER1 - static timer_handle_t _hwtimer_periph1; - _hwtimer_periph1.perh = BS16T1; - hwtimer1.IRQn = BS16T1_IRQn; - hwtimer1.hwtimer_periph = &_hwtimer_periph1; - hwtimer1.parent.info = &es32f3_hwtimer_info; - hwtimer1.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); +#ifdef BSP_USING_AD16C4T1_HWTIMER + static timer_handle_t ad16c4t1_hwtimer_periph; + + ad16c4t1_hwtimer_periph.perh = AD16C4T1; + ad16c4t1_hwtimer.IRQn = AD16C4T1_UP_IRQn; + + ad16c4t1_hwtimer_periph.init.prescaler = ES_AD16C4T1_HWTIMER_PRES - 1; + ad16c4t1_hwtimer_periph.init.mode = ( ES_AD16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t1_hwtimer.hwtimer_periph = &ad16c4t1_hwtimer_periph; + + ad16c4t1_hwtimer.parent.info = &ad16c4t1_info; + ad16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&ad16c4t1_hwtimer.parent, ES_DEVICE_NAME_AD16C4T1_HWTIMER, &ad16c4t1_hwtimer); +#endif + +#ifdef BSP_USING_GP32C4T0_HWTIMER + static timer_handle_t gp32c4t0_hwtimer_periph; + + gp32c4t0_hwtimer_periph.perh = GP32C4T0; + gp32c4t0_hwtimer.IRQn = GP32C4T0_IRQn; + + gp32c4t0_hwtimer_periph.init.prescaler = ES_GP32C4T0_HWTIMER_PRES - 1; + gp32c4t0_hwtimer_periph.init.mode = ( ES_GP32C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp32c4t0_hwtimer.hwtimer_periph = &gp32c4t0_hwtimer_periph; + + gp32c4t0_hwtimer.parent.info = &gp32c4t0_info; + gp32c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp32c4t0_hwtimer.parent, ES_DEVICE_NAME_GP32C4T0_HWTIMER, &gp32c4t0_hwtimer); +#endif + +#ifdef BSP_USING_GP32C4T1_HWTIMER + static timer_handle_t gp32c4t1_hwtimer_periph; + + gp32c4t1_hwtimer_periph.perh = GP32C4T1; + gp32c4t1_hwtimer.IRQn = GP32C4T1_IRQn; + + gp32c4t1_hwtimer_periph.init.prescaler = ES_GP32C4T1_HWTIMER_PRES - 1; + gp32c4t1_hwtimer_periph.init.mode = ( ES_GP32C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp32c4t1_hwtimer.hwtimer_periph = &gp32c4t1_hwtimer_periph; + + gp32c4t1_hwtimer.parent.info = &gp32c4t1_info; + gp32c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp32c4t1_hwtimer.parent, ES_DEVICE_NAME_GP32C4T1_HWTIMER, &gp32c4t1_hwtimer); +#endif + +#ifdef BSP_USING_GP16C4T0_HWTIMER + static timer_handle_t gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer_periph.perh = GP16C4T0; + gp16c4t0_hwtimer.IRQn = GP16C4T0_IRQn; + + gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1; + gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer.parent.info = &gp16c4t0_info; + gp16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer); +#endif + +#ifdef BSP_USING_GP16C4T1_HWTIMER + static timer_handle_t gp16c4t1_hwtimer_periph; + + gp16c4t1_hwtimer_periph.perh = GP16C4T1; + gp16c4t1_hwtimer.IRQn = GP16C4T1_IRQn; + + gp16c4t1_hwtimer_periph.init.prescaler = ES_GP16C4T1_HWTIMER_PRES - 1; + gp16c4t1_hwtimer_periph.init.mode = ( ES_GP16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t1_hwtimer.hwtimer_periph = &gp16c4t1_hwtimer_periph; + + gp16c4t1_hwtimer.parent.info = &gp16c4t1_info; + gp16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t1_hwtimer.parent, ES_DEVICE_NAME_GP16C4T1_HWTIMER, &gp16c4t1_hwtimer); +#endif + +#ifdef BSP_USING_BS16T0_HWTIMER + static timer_handle_t bs16t0_hwtimer_periph; + + bs16t0_hwtimer_periph.perh = BS16T0; + bs16t0_hwtimer.IRQn = BS16T0_IRQn; + + bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1; + bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph; + + bs16t0_hwtimer.parent.info = &bs16t0_info; + bs16t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer); +#endif + +#ifdef BSP_USING_BS16T1_HWTIMER + static timer_handle_t bs16t1_hwtimer_periph; + + bs16t1_hwtimer_periph.perh = BS16T1; + bs16t1_hwtimer.IRQn = BS16T1_IRQn; + + bs16t1_hwtimer_periph.init.prescaler = ES_BS16T1_HWTIMER_PRES - 1; + bs16t1_hwtimer_periph.init.mode = ( ES_BS16T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t1_hwtimer.hwtimer_periph = &bs16t1_hwtimer_periph; + + bs16t1_hwtimer.parent.info = &bs16t1_info; + bs16t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t1_hwtimer.parent, ES_DEVICE_NAME_BS16T1_HWTIMER, &bs16t1_hwtimer); #endif return ret; diff --git a/bsp/essemi/es32f369x/drivers/drv_hwtimer.h b/bsp/essemi/es32f369x/drivers/drv_hwtimer.h index e18d580fbd..46e307a5c3 100644 --- a/bsp/essemi/es32f369x/drivers/drv_hwtimer.h +++ b/bsp/essemi/es32f369x/drivers/drv_hwtimer.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-3-19 wangyq the first version + * 2019-3-19 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_HWTIMER_H__ #define DRV_HWTIMER_H__ +#include "es_conf_info_hwtimer.h" int rt_hw_hwtimer_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.c b/bsp/essemi/es32f369x/drivers/drv_i2c.c index 207890a6d4..c398d5ab45 100644 --- a/bsp/essemi/es32f369x/drivers/drv_i2c.c +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.c @@ -1,12 +1,24 @@ /* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: - * Date Author Notes - * 2020-01-14 wangyq the first version - * 2019-11-01 wangyq update libraries + * Date Author Notes + * 2019-11-01 wangyq update libraries + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include @@ -14,9 +26,7 @@ #include #include "board.h" #include "drv_i2c.h" -#include -#include -#include + #ifdef RT_USING_I2C @@ -43,36 +53,58 @@ static void _i2c_init(void) gpio_instruct.nodrv = GPIO_OUT_DRIVE_0_1; gpio_instruct.flt = GPIO_FILTER_DISABLE; gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.func = GPIO_FUNC_5; + + +#ifdef BSP_USING_I2C0 + +#if defined(ES_I2C0_SCL_GPIO_FUNC)&&defined(ES_I2C0_SCL_GPIO_PORT)&&defined(ES_I2C0_SCL_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SCL_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SCL_GPIO_PORT, ES_I2C0_SCL_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C0_SDA_GPIO_FUNC)&&defined(ES_I2C0_SDA_GPIO_PORT)&&defined(ES_I2C0_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SDA_GPIO_PORT, ES_I2C0_SDA_GPIO_PIN, &gpio_instruct); +#endif -#ifdef BSP_USING_I2C0 /* Initialize I2C Function */ - _h_i2c0.perh = I2C0; - _h_i2c0.init.clk_speed = 100000; - _h_i2c0.init.own_addr1 = 0x0A; - _h_i2c0.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE; + _h_i2c0.perh = I2C0; + _h_i2c0.init.module = I2C_MODULE_MASTER; + _h_i2c0.init.clk_speed = ES_I2C0_CLK_SPEED; + _h_i2c0.init.own_addr1 = ES_I2C0_OWN_ADDR1; + _h_i2c0.init.addr_mode = ES_I2C0_ADDR_MODE; + _h_i2c0.init.general_call = ES_I2C0_GENERAL_CALL; + _h_i2c0.init.no_stretch = ES_I2C0_STRETCH; ald_i2c_reset(&_h_i2c0); ald_i2c_init(&_h_i2c0); - /* PB06->I2C0_SCL, PB07->I2C0_SDA */ - ald_gpio_init(GPIOB, GPIO_PIN_6 | GPIO_PIN_7, &gpio_instruct); + #endif -#ifdef BSP_USING_I2C1 +#ifdef BSP_USING_I2C1 + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + /* Initialize i2c function */ - _h_i2c1.perh = I2C1; - _h_i2c1.init.clk_speed = 100000; - _h_i2c1.init.own_addr1 = 0xA0; - _h_i2c1.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE; + _h_i2c1.perh = I2C1; + _h_i2c1.init.module = I2C_MODULE_MASTER; + _h_i2c1.init.clk_speed = ES_I2C1_CLK_SPEED; + _h_i2c1.init.own_addr1 = ES_I2C1_OWN_ADDR1; + _h_i2c1.init.addr_mode = ES_I2C1_ADDR_MODE; + _h_i2c1.init.general_call = ES_I2C1_GENERAL_CALL; + _h_i2c1.init.no_stretch = ES_I2C1_STRETCH; ald_i2c_reset(&_h_i2c1); ald_i2c_init(&_h_i2c1); - /* PA05->I2C1_SCL, PA06->I2C1_SDA */ - ald_gpio_init(GPIOA, GPIO_PIN_5 | GPIO_PIN_6, &gpio_instruct); + #endif } @@ -133,7 +165,7 @@ int rt_hw_i2c_init(void) _i2c_device0.ops = &es32f3_i2c_ops; _i2c_device0.priv = &_h_i2c0; - result = rt_i2c_bus_device_register(&_i2c_device0, "i2c0"); + result = rt_i2c_bus_device_register(&_i2c_device0, ES_DEVICE_NAME_I2C0); if (result != RT_EOK) { return result; @@ -147,7 +179,7 @@ int rt_hw_i2c_init(void) _i2c_device1.ops = &es32f3_i2c_ops; _i2c_device1.priv = &_h_i2c1; - rt_i2c_bus_device_register(&_i2c_device1, "i2c1"); + rt_i2c_bus_device_register(&_i2c_device1, ES_DEVICE_NAME_I2C1); if (result != RT_EOK) { return result; diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.h b/bsp/essemi/es32f369x/drivers/drv_i2c.h index d7c2410682..16bfa324d3 100644 --- a/bsp/essemi/es32f369x/drivers/drv_i2c.h +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.h @@ -1,16 +1,31 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_I2C_H__ #define DRV_I2C_H__ +#include "es_conf_info_i2c.h" + int rt_hw_i2c_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_pm.c b/bsp/essemi/es32f369x/drivers/drv_pm.c index ffe46ff6f3..5ec1c8c701 100644 --- a/bsp/essemi/es32f369x/drivers/drv_pm.c +++ b/bsp/essemi/es32f369x/drivers/drv_pm.c @@ -3,16 +3,27 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2020-12-15 liuhy the first version */ -#include "drv_pm.h" +#include "drv_pm.h" #ifdef RT_USING_PM -//uint32_t save_mem[1024] __attribute__ ((aligned(4))); void save_register(void *p_head,uint32_t size,void *p_save) { @@ -21,15 +32,17 @@ void save_register(void *p_head,uint32_t size,void *p_save) void load_register(void *p_head,uint32_t size,void *p_load) { - uint32_t tmp; memcpy(p_head,p_load,size); - + +#ifdef ES_PMU_SAVE_LOAD_UART + if((p_head == UART0) || (p_head == UART1) || (p_head == UART2) || (p_head == UART3) || (p_head == UART4) || (p_head == UART5) ) { - tmp = ((UART_TypeDef*)p_load)->IVS; - ((UART_TypeDef*)p_head)->IER = tmp; + ((UART_TypeDef*)p_head)->IER = ((UART_TypeDef*)p_load)->IVS; } +#endif + } static void uart_console_reconfig(void) @@ -39,36 +52,14 @@ static void uart_console_reconfig(void) rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); } -static void delay(void) -{ - long i; - rt_base_t level; - - level = rt_hw_interrupt_disable(); - i = 0; - do{ - i++; - } - while (i < 4000000); - - rt_hw_interrupt_enable(level); -} - /** * This function will put ES32F369x into sleep mode. * * @param pm pointer to power manage structure */ -struct pm_callback_t -{ - volatile int in_fun_times; /*进入函数的次数*/ - volatile char flag; /*标志*/ - volatile int mode; /*需要打印的模式*/ -}; - -extern volatile struct pm_callback_t g_pm_data; +/* 注意：进入睡眠前，如果有中断挂起（SYSTICK、PENDSV、UART、EXTI等），睡眠将被瞬间唤醒。*/ static void sleep(struct rt_pm *pm, uint8_t mode) { @@ -83,26 +74,21 @@ static void sleep(struct rt_pm *pm, uint8_t mode) case PM_SLEEP_MODE_LIGHT: /* Enter SLEEP Mode, Main regulator is ON */ ald_pmu_stop1_enter(); - delay(); - break; case PM_SLEEP_MODE_DEEP: - /* Enter STOP 2 mode */ + /* Enter STOP 2 mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_STANDBY: - /* Enter STANDBY mode */ + /* Enter STANDBY mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_SHUTDOWN: - /* Enter SHUTDOWNN mode */ + /* Enter SHUTDOWNN mode */ ald_pmu_stop2_enter(); - delay(); break; default: diff --git a/bsp/essemi/es32f369x/drivers/drv_pm.h b/bsp/essemi/es32f369x/drivers/drv_pm.h index 56de29eef5..874f86ed08 100644 --- a/bsp/essemi/es32f369x/drivers/drv_pm.h +++ b/bsp/essemi/es32f369x/drivers/drv_pm.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-04-01 wangyq the first version + * 2019-04-01 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_PM_H__ @@ -14,9 +27,8 @@ #include #include #include -#include -#include -#include "shell.h" +#include "es_conf_info_pm.h" +#include int rt_hw_pm_init(void); diff --git a/bsp/essemi/es32f369x/drivers/drv_pwm.c b/bsp/essemi/es32f369x/drivers/drv_pwm.c index e033e47cec..b61e363633 100644 --- a/bsp/essemi/es32f369x/drivers/drv_pwm.c +++ b/bsp/essemi/es32f369x/drivers/drv_pwm.c @@ -3,28 +3,33 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-11 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include "es_conf_info_pwm.h" -static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) -{ - uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / - (timer_initstruct->init.prescaler + 1); - WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); - timer_initstruct->init.period = (uint32_t)_arr; -} +#ifdef RT_USING_PWM static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns) { @@ -44,37 +49,40 @@ static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, u static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { rt_err_t ret = RT_EOK; - uint32_t _ccep; + uint64_t _arr,bus_speed,tmp; + uint32_t _maxcnt,_ccep_ch_en = 0U; timer_channel_t pwm_channel; timer_oc_init_t tim_ocinit; timer_handle_t *timer_initstruct = (timer_handle_t *)device->parent.user_data; struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; RT_ASSERT(timer_initstruct != RT_NULL); - - tim_ocinit.oc_mode = TIMER_OC_MODE_PWM1; - tim_ocinit.oc_polarity = TIMER_OC_POLARITY_HIGH; - tim_ocinit.oc_fast_en = DISABLE; - tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; - tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; - tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; - + + /* select pwm output channel */ if (1 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_1; - - else if (2 == cfg->channel) + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC1EN_MSK; + } + else if (2 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_2; - - else if (3 == cfg->channel) + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC2EN_MSK; + } + else if (3 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_3; - - else if (4 == cfg->channel) + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC3EN_MSK; + } + else if (4 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_4; - + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK; + } else return RT_EINVAL; - + switch (cmd) { case PWM_CMD_ENABLE: @@ -86,19 +94,53 @@ static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void * break; case PWM_CMD_SET: - _ccep = timer_initstruct->perh->CCEP; - /* count registers max 0xFFFF, auto adjust prescaler */ + + /*当通道没开的时候：关通道，设置输出模式和极性，初始化通道*/ + if(!_ccep_ch_en) + { + tim_ocinit.oc_mode = ES_PWM_OC_MODE; + tim_ocinit.oc_polarity = ES_PWM_OC_POLARITY; + tim_ocinit.oc_fast_en = DISABLE; + tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; + tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; + + ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + } + + bus_speed = (uint64_t)ald_cmu_get_pclk1_clock(); + + /*判断外设的计数器最大值*/ +#ifdef ES32F36xx + if((timer_initstruct->perh == GP32C4T0)||(timer_initstruct->perh == GP32C4T1)) + { + _maxcnt = 0xFFFFFFFF; + } + else _maxcnt = 0xFFFF; +#else + _maxcnt = 0xFFFF; +#endif + + /*当最大分频 <= _maxcnt时：估计大概的分频，加快速度 */ + tmp = bus_speed * (cfg->period)/1000000000/_maxcnt; + timer_initstruct->init.prescaler = (tmp > 2U) ? (tmp - 2U) : 0U ; /*bus_speed < 500000000*/ + + /* count registers max , auto adjust prescaler */ do { - pwm_set_freq(timer_initstruct, cfg->period); - timer_initstruct->init.prescaler ++; + _arr = bus_speed * (cfg->period) / 1000000000 /(++timer_initstruct->init.prescaler); + } - while (timer_initstruct->init.period > 0xFFFF); + while (_arr > _maxcnt); + + WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); + timer_initstruct->init.period = (uint32_t)_arr; + /* update prescaler */ WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler); - ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse); - timer_initstruct->perh->CCEP = _ccep; + break; case PWM_CMD_GET: @@ -130,42 +172,210 @@ int rt_hw_pwm_init(void) gpio_initstructure.flt = GPIO_FILTER_DISABLE; gpio_initstructure.type = GPIO_TYPE_TTL; -#ifdef BSP_USING_PWM0 /* 4 channels */ - static struct rt_device_pwm pwm_dev0; - static timer_handle_t timer_initstruct0; +#ifdef BSP_USING_AD16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t0_pwm_dev; + static timer_handle_t ad16c4t0_timer_initstruct; - timer_initstruct0.perh = GP16C4T0; - ald_timer_pwm_init(&timer_initstruct0); + ad16c4t0_timer_initstruct.perh = AD16C4T0; + ald_timer_pwm_init(&ad16c4t0_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); - ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f3_pwm_ops, - &timer_initstruct0); +#if defined(ES_AD16C4T0_CH1_GPIO_FUNC)&&defined(ES_AD16C4T0_CH1_GPIO_PORT)&&defined(ES_AD16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH1_GPIO_PORT, ES_AD16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH2_GPIO_FUNC)&&defined(ES_AD16C4T0_CH2_GPIO_PORT)&&defined(ES_AD16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH2_GPIO_PORT, ES_AD16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH3_GPIO_FUNC)&&defined(ES_AD16C4T0_CH3_GPIO_PORT)&&defined(ES_AD16C4T0_CH3_GPIO_FUNC) + gpio_initstructure.func = ES_AD16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH3_GPIO_PORT, ES_AD16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH4_GPIO_FUNC)&&defined(ES_AD16C4T0_CH4_GPIO_PORT)&&defined(ES_AD16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH4_GPIO_PORT, ES_AD16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T0_PWM, &es32f3_pwm_ops, + &ad16c4t0_timer_initstruct); #endif -#ifdef BSP_USING_PWM1 /* 4 channels */ - static struct rt_device_pwm pwm_dev1; - static timer_handle_t timer_initstruct1; +#ifdef BSP_USING_AD16C4T1_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t1_pwm_dev; + static timer_handle_t ad16c4t1_timer_initstruct; - timer_initstruct1.perh = GP16C4T1; - ald_timer_pwm_init(&timer_initstruct1); + ad16c4t1_timer_initstruct.perh = AD16C4T1; + ald_timer_pwm_init(&ad16c4t1_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_5; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstructure); + +#if defined(ES_AD16C4T1_CH1_GPIO_FUNC)&&defined(ES_AD16C4T1_CH1_GPIO_PORT)&&defined(ES_AD16C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH1_GPIO_PORT, ES_AD16C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH2_GPIO_FUNC)&&defined(ES_AD16C4T1_CH2_GPIO_PORT)&&defined(ES_AD16C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH2_GPIO_PORT, ES_AD16C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif - ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f3_pwm_ops, - &timer_initstruct1); +#if defined(ES_AD16C4T1_CH3_GPIO_FUNC)&&defined(ES_AD16C4T1_CH3_GPIO_PORT)&&defined(ES_AD16C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH3_GPIO_PORT, ES_AD16C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH4_GPIO_FUNC)&&defined(ES_AD16C4T1_CH4_GPIO_PORT)&&defined(ES_AD16C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH4_GPIO_PORT, ES_AD16C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t1_pwm_dev, ES_DEVICE_NAME_AD16C4T1_PWM, &es32f3_pwm_ops, + &ad16c4t1_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP32C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp32c4t0_pwm_dev; + static timer_handle_t gp32c4t0_timer_initstruct; + + gp32c4t0_timer_initstruct.perh = GP32C4T0; + ald_timer_pwm_init(&gp32c4t0_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP32C4T0_CH1_GPIO_FUNC)&&defined(ES_GP32C4T0_CH1_GPIO_PORT)&&defined(ES_GP32C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH1_GPIO_PORT, ES_GP32C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH2_GPIO_FUNC)&&defined(ES_GP32C4T0_CH2_GPIO_PORT)&&defined(ES_GP32C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH2_GPIO_PORT, ES_GP32C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH3_GPIO_FUNC)&&defined(ES_GP32C4T0_CH3_GPIO_PORT)&&defined(ES_GP32C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH3_GPIO_PORT, ES_GP32C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH4_GPIO_FUNC)&&defined(ES_GP32C4T0_CH4_GPIO_PORT)&&defined(ES_GP32C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH4_GPIO_PORT, ES_GP32C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp32c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T1_PWM, &es32f3_pwm_ops, + &gp32c4t0_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP32C4T1_PWM /* 4 channels */ + static struct rt_device_pwm gp32c4t1_pwm_dev; + static timer_handle_t gp32c4t1_timer_initstruct; + + gp32c4t1_timer_initstruct.perh = GP32C4T1; + ald_timer_pwm_init(&gp32c4t1_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP32C4T1_CH1_GPIO_FUNC)&&defined(ES_GP32C4T1_CH1_GPIO_PORT)&&defined(ES_GP32C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH1_GPIO_PORT, ES_GP32C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH2_GPIO_FUNC)&&defined(ES_GP32C4T1_CH2_GPIO_PORT)&&defined(ES_GP32C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH2_GPIO_PORT, ES_GP32C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH3_GPIO_FUNC)&&defined(ES_GP32C4T1_CH3_GPIO_PORT)&&defined(ES_GP32C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH3_GPIO_PORT, ES_GP32C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH4_GPIO_FUNC)&&defined(ES_GP32C4T1_CH4_GPIO_PORT)&&defined(ES_GP32C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH4_GPIO_PORT, ES_GP32C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp32c4t1_pwm_dev, ES_DEVICE_NAME_GP32C4T1_PWM, &es32f3_pwm_ops, + &gp32c4t1_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t0_pwm_dev; + static timer_handle_t gp16c4t0_timer_initstruct; + + gp16c4t0_timer_initstruct.perh = GP16C4T0; + ald_timer_pwm_init(&gp16c4t0_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP16C4T0_CH1_GPIO_FUNC)&&defined(ES_GP16C4T0_CH1_GPIO_PORT)&&defined(ES_GP16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH1_GPIO_PORT, ES_GP16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH2_GPIO_FUNC)&&defined(ES_GP16C4T0_CH2_GPIO_PORT)&&defined(ES_GP16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH2_GPIO_PORT, ES_GP16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH3_GPIO_FUNC)&&defined(ES_GP16C4T0_CH3_GPIO_PORT)&&defined(ES_GP16C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH3_GPIO_PORT, ES_GP16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH4_GPIO_FUNC)&&defined(ES_GP16C4T0_CH4_GPIO_PORT)&&defined(ES_GP16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH4_GPIO_PORT, ES_GP16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t0_pwm_dev, ES_DEVICE_NAME_GP16C4T0_PWM, &es32f3_pwm_ops, + &gp16c4t0_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP16C4T1_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t1_pwm_dev; + static timer_handle_t gp16c4t1_timer_initstruct; + + gp16c4t1_timer_initstruct.perh = GP16C4T1; + ald_timer_pwm_init(&gp16c4t1_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP16C4T1_CH1_GPIO_FUNC)&&defined(ES_GP16C4T1_CH1_GPIO_PORT)&&defined(ES_GP16C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH1_GPIO_PORT, ES_GP16C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH2_GPIO_FUNC)&&defined(ES_GP16C4T1_CH2_GPIO_PORT)&&defined(ES_GP16C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH2_GPIO_PORT, ES_GP16C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH3_GPIO_FUNC)&&defined(ES_GP16C4T1_CH3_GPIO_PORT)&&defined(ES_GP16C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH3_GPIO_PORT, ES_GP16C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH4_GPIO_FUNC)&&defined(ES_GP16C4T1_CH4_GPIO_PORT)&&defined(ES_GP16C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH4_GPIO_PORT, ES_GP16C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t1_pwm_dev, ES_DEVICE_NAME_GP16C4T1_PWM, &es32f3_pwm_ops, + &gp16c4t1_timer_initstruct); #endif return ret; } INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_rtc.c b/bsp/essemi/es32f369x/drivers/drv_rtc.c index cab5b8b61b..13b0fc9a24 100644 --- a/bsp/essemi/es32f369x/drivers/drv_rtc.c +++ b/bsp/essemi/es32f369x/drivers/drv_rtc.c @@ -3,21 +3,32 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-22 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include -#include +#include #include #include #include "board.h" -#include "drv_rtc.h" -#include -#include +#include "drv_rtc.h" #ifdef RT_USING_RTC @@ -117,20 +128,28 @@ int rt_hw_rtc_init(void) rt_err_t ret = RT_EOK; static struct rt_device rtc_dev; rtc_init_t rtc_initstruct; + + /* enable clk */ + ald_rtc_source_select(ES_RTC_CLK_SOURCE); - /* enable external 32.768kHz */ - CMU_LOSC_ENABLE(); - ald_cmu_losc_safe_config(ENABLE); + if(ES_RTC_CLK_SOURCE == ES_C_RTC_SOURCE_LOSC) + { + CMU_LOSC_ENABLE(); + ald_cmu_losc_safe_config(ENABLE); + } + /* set default time */ RTC_UNLOCK(); WRITE_REG(RTC->TIME, 0x134251); WRITE_REG(RTC->DATE, 0x1190401); RTC_LOCK(); + /* RTC function initialization */ rtc_initstruct.hour_format = RTC_HOUR_FORMAT_24; rtc_initstruct.asynch_pre_div = 0; rtc_initstruct.synch_pre_div = 32767; - rtc_initstruct.output = RTC_OUTPUT_DISABLE; + rtc_initstruct.output = RTC_OUTPUT_DISABLE; + rtc_initstruct.output_polarity = RTC_OUTPUT_POLARITY_HIGH; __rtc_init(&rtc_initstruct); rtc_dev.type = RT_Device_Class_RTC; @@ -150,7 +169,7 @@ int rt_hw_rtc_init(void) rtc_dev.user_data = RTC; - ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); + ret = rt_device_register(&rtc_dev, ES_DEVICE_NAME_RTC, RT_DEVICE_FLAG_RDWR); return ret; } diff --git a/bsp/essemi/es32f369x/drivers/drv_rtc.h b/bsp/essemi/es32f369x/drivers/drv_rtc.h index fe0264fb51..76e5b24d85 100644 --- a/bsp/essemi/es32f369x/drivers/drv_rtc.h +++ b/bsp/essemi/es32f369x/drivers/drv_rtc.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-03-22 wangyq the first version + * 2019-03-22 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_RTC_H__ #define DRV_RTC_H__ +#include "es_conf_info_rtc.h" int rt_hw_rtc_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.c b/bsp/essemi/es32f369x/drivers/drv_spi.c index 9bf7e4e4b5..aae178f78e 100644 --- a/bsp/essemi/es32f369x/drivers/drv_spi.c +++ b/bsp/essemi/es32f369x/drivers/drv_spi.c @@ -3,10 +3,23 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: - * Date Author Notes - * 2020-01-14 wangyq the first version - * 2019-11-01 wangyq update libraries + * Date Author Notes + * 2019-11-01 wangyq update libraries + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include @@ -15,9 +28,7 @@ #include #include "board.h" #include "drv_spi.h" -#include -#include -#include + #ifdef RT_USING_SPI @@ -31,6 +42,7 @@ rt_err_t spi_configure(struct rt_spi_device *device, hspi->init.ss_en = DISABLE; hspi->init.crc_calc = DISABLE; + hspi->init.frame = SPI_FRAME_MOTOROLA; /* config spi mode */ if (cfg->mode & RT_SPI_SLAVE) @@ -163,73 +175,54 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * hspi = (spi_handle_t *)device->bus->parent.user_data; cs = device->parent.user_data; + if (message->cs_take) + { + rt_pin_write(cs->pin, ES_SPI_CS_LEVEL); + } + if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) { /* send & receive */ if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } else { /* only send data */ if (message->recv_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } /* only receive data */ if (message->send_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } } - + + if (message->cs_release) + { + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); + } + + if (res != RT_EOK) + return RT_ERROR; + else + return message->length; + } else { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } - + if (message->cs_release) { - rt_pin_write(cs->pin, 1); + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); } return RT_EOK; } - return message->length; + } const struct rt_spi_ops es32f3_spi_ops = @@ -240,6 +233,7 @@ const struct rt_spi_ops es32f3_spi_ops = rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) { + int result; /* define spi Instance */ struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); @@ -248,7 +242,20 @@ rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const c cs_pin->pin = pin; rt_pin_mode(pin, PIN_MODE_OUTPUT); rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + +#ifdef BSP_USING_SPI0 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI0_BUS)))SPI_BUS_CONFIG(spi_device->config,0); +#endif +#ifdef BSP_USING_SPI1 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI1_BUS)))SPI_BUS_CONFIG(spi_device->config,1); +#endif +#ifdef BSP_USING_SPI2 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI2_BUS)))SPI_BUS_CONFIG(spi_device->config,2); +#endif + + return result; } #ifdef BSP_USING_SPI0 @@ -273,40 +280,47 @@ int rt_hw_spi_init(void) struct rt_spi_bus *spi_bus; spi_handle_t *spi; gpio_init_t gpio_instruct; - + + gpio_instruct.pupd = GPIO_PUSH_UP_DOWN; + gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.podrv = GPIO_OUT_DRIVE_1; + gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_instruct.type = GPIO_TYPE_TTL; + gpio_instruct.flt = GPIO_FILTER_DISABLE; + #ifdef BSP_USING_SPI0 _spi0.perh = SPI0; spi_bus = &_spi_bus0; spi = &_spi0; - rt_device_t spi_bus_dev0; /* SPI0 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_TTL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - /* PB3->SPI0_SCK, PB5->SPI0_MOSI */ - ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); +#if defined(ES_SPI0_SCK_GPIO_FUNC)&&defined(ES_SPI0_SCK_GPIO_PORT)&&defined(ES_SPI0_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI0_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI0_SCK_GPIO_PORT, ES_SPI0_SCK_GPIO_PIN, &gpio_instruct); +#endif - /* PB4->SPI0_MISO */ +#if defined(ES_SPI0_MOSI_GPIO_FUNC)&&defined(ES_SPI0_MOSI_GPIO_PORT)&&defined(ES_SPI0_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MOSI_GPIO_PORT, ES_SPI0_MOSI_GPIO_PIN, &gpio_instruct); +#endif + gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); + +#if defined(ES_SPI0_MISO_GPIO_FUNC)&&defined(ES_SPI0_MISO_GPIO_PORT)&&defined(ES_SPI0_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MISO_GPIO_PORT, ES_SPI0_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi0", &es32f3_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR); - - /* SPI0_NSS = PA15 = PIN 50 */ - result = es32f3_spi_device_attach(50, "spi0", "spi00"); + result = es32f3_spi_device_attach(ES_SPI0_NSS_PIN, ES_DEVICE_NAME_SPI0_BUS, ES_DEVICE_NAME_SPI0_DEV0); if (result != RT_EOK) { @@ -319,35 +333,35 @@ int rt_hw_spi_init(void) _spi1.perh = SPI1; spi_bus = &_spi_bus1; spi = &_spi1; - rt_device_t spi_bus_dev0; /* SPI1 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_TTL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PC01->SPI1_SCK, PC03->SPI1_MOSI */ - ald_gpio_init(GPIOC, GPIO_PIN_1 | GPIO_PIN_3, &gpio_instruct); - - /* PC02->SPI1_MISO */ + +#if defined(ES_SPI1_SCK_GPIO_FUNC)&&defined(ES_SPI1_SCK_GPIO_PORT)&&defined(ES_SPI1_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI1_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI1_SCK_GPIO_PORT, ES_SPI1_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI1_MOSI_GPIO_FUNC)&&defined(ES_SPI1_MOSI_GPIO_PORT)&&defined(ES_SPI1_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MOSI_GPIO_PORT, ES_SPI1_MOSI_GPIO_PIN, &gpio_instruct); +#endif + gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_instruct); + +#if defined(ES_SPI1_MISO_GPIO_FUNC)&&defined(ES_SPI1_MISO_GPIO_PORT)&&defined(ES_SPI1_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MISO_GPIO_PORT, ES_SPI1_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi1", &es32f3_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f3_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR); - - /* SPI1_NSS = PC00 = PIN 8 */ - result = es32f3_spi_device_attach(8, "spi1", "spi10"); + result = es32f3_spi_device_attach(ES_SPI1_NSS_PIN, ES_DEVICE_NAME_SPI1_BUS, ES_DEVICE_NAME_SPI1_DEV0); if (result != RT_EOK) { @@ -357,38 +371,38 @@ int rt_hw_spi_init(void) #endif #ifdef BSP_USING_SPI2 - _spi1.perh = SPI2; + _spi2.perh = SPI2; spi_bus = &_spi_bus2; spi = &_spi2; - rt_device_t spi_bus_dev0; /* SPI2 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; - gpio_instruct.func = GPIO_FUNC_5; - gpio_instruct.type = GPIO_TYPE_TTL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PC05->SPI1_SCK, PB01->SPI1_MOSI */ - ald_gpio_init(GPIOC, GPIO_PIN_5 | GPIO_PIN_1, &gpio_instruct); - - /* PB00->SPI1_MISO */ + +#if defined(ES_SPI2_SCK_GPIO_FUNC)&&defined(ES_SPI2_SCK_GPIO_PORT)&&defined(ES_SPI2_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI2_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI2_SCK_GPIO_PORT, ES_SPI2_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI2_MOSI_GPIO_FUNC)&&defined(ES_SPI2_MOSI_GPIO_PORT)&&defined(ES_SPI2_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI2_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI2_MOSI_GPIO_PORT, ES_SPI2_MOSI_GPIO_PIN, &gpio_instruct); +#endif + gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_instruct); + +#if defined(ES_SPI2_MISO_GPIO_FUNC)&&defined(ES_SPI2_MISO_GPIO_PORT)&&defined(ES_SPI2_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI2_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI2_MISO_GPIO_PORT, ES_SPI2_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi2", &es32f3_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI2_BUS, &es32f3_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi20", RT_DEVICE_FLAG_RDWR); - - /* SPI2_NSS = PC04 = PIN 24 */ - result = es32f3_spi_device_attach(39, "spi2", "spi20"); + result = es32f3_spi_device_attach(ES_SPI2_NSS_PIN, ES_DEVICE_NAME_SPI2_BUS, ES_DEVICE_NAME_SPI1_DEV0); if (result != RT_EOK) { diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.h b/bsp/essemi/es32f369x/drivers/drv_spi.h index 832d1a58b1..32eab04cc5 100644 --- a/bsp/essemi/es32f369x/drivers/drv_spi.h +++ b/bsp/essemi/es32f369x/drivers/drv_spi.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_SPI_H__ @@ -14,6 +27,8 @@ #include #include #include + +#include "es_conf_info_spi.h" struct es32f3_hw_spi_cs { diff --git a/bsp/essemi/es32f369x/drivers/drv_spiflash.c b/bsp/essemi/es32f369x/drivers/drv_spiflash.c new file mode 100644 index 0000000000..d8176257d1 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_spiflash.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-15 wangyq the first version + * 2019-11-01 wangyq update libraries + */ + +#include "board.h" +#include + +#if defined(BSP_USING_SPI_FLASH) + +#include "spi_flash.h" +#include "drv_spiflash.h" +#include "spi_flash_sfud.h" +#include "drv_spi.h" + +int rt_hw_spi_flash_init(void) +{ + + if (RT_NULL == rt_sfud_flash_probe(ES_DEVICE_NAME_SPI_FALSH_DEV, ES_DEVICE_NAME_SPI_DEV)) + { + return -RT_ERROR; + }; + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_spiflash.h b/bsp/essemi/es32f369x/drivers/drv_spiflash.h new file mode 100644 index 0000000000..6ef31852bb --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_spiflash.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-15 wangyq the first version + * 2021-04-20 liuhy the second version + */ + +#ifndef DRV_NOR_FLASH_H__ +#define DRV_NOR_FLASH_H__ + +#include "es_conf_info_spi.h" + +int rt_hw_spi_flash_init(void); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.c b/bsp/essemi/es32f369x/drivers/drv_uart.c index b6a8b7a453..5ca5085c54 100644 --- a/bsp/essemi/es32f369x/drivers/drv_uart.c +++ b/bsp/essemi/es32f369x/drivers/drv_uart.c @@ -3,19 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include #include #include #include "board.h" -#include "drv_uart.h" -#include -#include -#include +#include "es_conf_info_uart.h" #ifdef RT_USING_SERIAL @@ -26,183 +36,6 @@ struct es32_uart IRQn_Type irq; }; -static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - gpio_init_t gpio_initstructure; - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - /* Initialize tx pin */ - gpio_initstructure.mode = GPIO_MODE_OUTPUT; - gpio_initstructure.odos = GPIO_PUSH_PULL; - gpio_initstructure.pupd = GPIO_PUSH_UP; - gpio_initstructure.podrv = GPIO_OUT_DRIVE_1; - gpio_initstructure.nodrv = GPIO_OUT_DRIVE_1; - gpio_initstructure.flt = GPIO_FILTER_DISABLE; - gpio_initstructure.type = GPIO_TYPE_TTL; - -#ifdef BSP_USING_UART0 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE); -#endif /* uart0 gpio init */ - -#ifdef BSP_USING_UART1 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE); -#endif /* uart1 gpio init */ - -#ifdef BSP_USING_UART2 - gpio_initstructure.func = GPIO_FUNC_5; - ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE); -#endif /* uart2 gpio init */ - -#ifdef BSP_USING_UART3 - gpio_initstructure.func = GPIO_FUNC_4; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE); -#endif /* uart3 gpio init */ - -#ifdef BSP_USING_UART4 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART4, ENABLE); -#endif /* uart4 gpio init */ - -#ifdef BSP_USING_UART5 - gpio_initstructure.func = GPIO_FUNC_4; - ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE); -#endif /* uart5 gpio init */ - - ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY); - ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE); - - uart->huart.init.mode = UART_MODE_UART; - uart->huart.init.baud = cfg->baud_rate; - uart->huart.init.word_length = (uart_word_length_t)(8 - cfg->data_bits); - uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); - uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; - ald_uart_init(&uart->huart); - - if (cfg->bit_order == BIT_ORDER_MSB) - { - UART_MSB_FIRST_ENABLE(&uart->huart); - } - else - { - UART_MSB_FIRST_DISABLE(&uart->huart); - } - - if (cfg->invert == NRZ_INVERTED) - { - UART_DATA_INV_ENABLE(&uart->huart); - } - else - { - UART_DATA_INV_DISABLE(&uart->huart); - } - - return RT_EOK; -} - -static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct es32_uart *)serial->parent.user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); - /* disable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, DISABLE); - break; - - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, ENABLE); - break; - } - - return RT_EOK; -} - -static int es32f3x_putc(struct rt_serial_device *serial, char c) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - while (ald_uart_get_status(&uart->huart, UART_STATUS_TFEMPTY) == RESET) - ; - WRITE_REG(uart->huart.perh->TXBUF, c); - - return 1; -} - -static int es32f3x_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct es32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - if (ald_uart_get_status(&uart->huart, UART_STATUS_RFTH)) - { - ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF); - } - - return ch; -} - -static const struct rt_uart_ops es32f3x_uart_ops = -{ - es32f3x_configure, - es32f3x_control, - es32f3x_putc, - es32f3x_getc, -}; - #ifdef BSP_USING_UART0 /* UART0 device driver structure */ struct es32_uart uart0 = @@ -353,18 +186,243 @@ void UART5_Handler(void) } #endif /* BSP_USING_UART5 */ +static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + gpio_init_t gpio_initstructure; + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Initialize tx pin */ + gpio_initstructure.mode = GPIO_MODE_OUTPUT; + gpio_initstructure.odos = GPIO_PUSH_PULL; + gpio_initstructure.pupd = GPIO_PUSH_UP; + gpio_initstructure.podrv = GPIO_OUT_DRIVE_1; + gpio_initstructure.nodrv = GPIO_OUT_DRIVE_1; + gpio_initstructure.flt = GPIO_FILTER_DISABLE; + gpio_initstructure.type = GPIO_TYPE_TTL; + +#ifdef BSP_USING_UART0 + if(uart == (&uart0)) + { +#if defined(ES_UART0_TX_GPIO_FUNC)&&defined(ES_UART0_TX_GPIO_PORT)&&defined(ES_UART0_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART0_TX_GPIO_FUNC; + ald_gpio_init(ES_UART0_TX_GPIO_PORT, ES_UART0_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART0_RX_GPIO_FUNC)&&defined(ES_UART0_RX_GPIO_PORT)&&defined(ES_UART0_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART0_RX_GPIO_FUNC; + ald_gpio_init(ES_UART0_RX_GPIO_PORT, ES_UART0_RX_GPIO_PIN, &gpio_initstructure); +#endif + ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE); + } + +#endif /* uart0 gpio init */ + +#ifdef BSP_USING_UART1 + if(uart == (&uart1)) + { +#if defined(ES_UART1_TX_GPIO_FUNC)&&defined(ES_UART1_TX_GPIO_PORT)&&defined(ES_UART1_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART1_TX_GPIO_FUNC; + ald_gpio_init(ES_UART1_TX_GPIO_PORT, ES_UART1_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART1_RX_GPIO_FUNC)&&defined(ES_UART1_RX_GPIO_PORT)&&defined(ES_UART1_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART1_RX_GPIO_FUNC; + ald_gpio_init(ES_UART1_RX_GPIO_PORT, ES_UART1_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE); + } +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_UART2 + if(uart == (&uart2)) + { +#if defined(ES_UART2_TX_GPIO_FUNC)&&defined(ES_UART2_TX_GPIO_PORT)&&defined(ES_UART2_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART2_TX_GPIO_FUNC; + ald_gpio_init(ES_UART2_TX_GPIO_PORT, ES_UART2_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART2_RX_GPIO_FUNC)&&defined(ES_UART2_RX_GPIO_PORT)&&defined(ES_UART2_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART2_RX_GPIO_FUNC; + ald_gpio_init(ES_UART2_RX_GPIO_PORT, ES_UART2_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE); + } +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_UART3 + if(uart == (&uart3)) + { +#if defined(ES_UART3_TX_GPIO_FUNC)&&defined(ES_UART3_TX_GPIO_PORT)&&defined(ES_UART3_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART3_TX_GPIO_FUNC; + ald_gpio_init(ES_UART3_TX_GPIO_PORT, ES_UART3_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART3_RX_GPIO_FUNC)&&defined(ES_UART3_RX_GPIO_PORT)&&defined(ES_UART3_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART3_RX_GPIO_FUNC; + ald_gpio_init(ES_UART3_RX_GPIO_PORT, ES_UART3_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE); + } +#endif /* uart3 gpio init */ + +#ifdef BSP_USING_UART4 + if(uart == (&uart4)) + { +#if defined(ES_UART4_TX_GPIO_FUNC)&&defined(ES_UART4_TX_GPIO_PORT)&&defined(ES_UART4_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART4_TX_GPIO_FUNC; + ald_gpio_init(ES_UART4_TX_GPIO_PORT, ES_UART4_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART4_RX_GPIO_FUNC)&&defined(ES_UART4_RX_GPIO_PORT)&&defined(ES_UART4_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART4_RX_GPIO_FUNC; + ald_gpio_init(ES_UART4_RX_GPIO_PORT, ES_UART4_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART4, ENABLE); + } +#endif /* uart4 gpio init */ + +#ifdef BSP_USING_UART5 + if(uart == (&uart5)) + { +#if defined(ES_UART5_TX_GPIO_FUNC)&&defined(ES_UART5_TX_GPIO_PORT)&&defined(ES_UART5_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART5_TX_GPIO_FUNC; + ald_gpio_init(ES_UART5_TX_GPIO_PORT, ES_UART5_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART5_RX_GPIO_FUNC)&&defined(ES_UART5_RX_GPIO_PORT)&&defined(ES_UART5_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART5_RX_GPIO_FUNC; + ald_gpio_init(ES_UART5_RX_GPIO_PORT, ES_UART5_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE); + } +#endif /* uart5 gpio init */ + + ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY); + ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE); + + uart->huart.init.mode = UART_MODE_UART; + uart->huart.init.baud = cfg->baud_rate; + uart->huart.init.word_length = (uart_word_length_t)(8 - cfg->data_bits); + uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); + uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; + uart->huart.init.stop_bits = UART_STOP_BITS_1; + ald_uart_init(&uart->huart); + + if (cfg->bit_order == BIT_ORDER_MSB) + { + UART_MSB_FIRST_ENABLE(&uart->huart); + } + else + { + UART_MSB_FIRST_DISABLE(&uart->huart); + } + + if (cfg->invert == NRZ_INVERTED) + { + UART_DATA_INV_ENABLE(&uart->huart); + } + else + { + UART_DATA_INV_DISABLE(&uart->huart); + } + + return RT_EOK; +} + +static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, ENABLE); + break; + } + + return RT_EOK; +} + +static int es32f3x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + while (ald_uart_get_status(&uart->huart, UART_STATUS_TFEMPTY) == RESET) + ; + WRITE_REG(uart->huart.perh->TXBUF, c); + + return 1; +} + +static int es32f3x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if (ald_uart_get_status(&uart->huart, UART_STATUS_RFTH)) + { + ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF); + } + + return ch; +} + +static const struct rt_uart_ops es32f3x_uart_ops = +{ + es32f3x_configure, + es32f3x_control, + es32f3x_putc, + es32f3x_getc, +}; + int rt_hw_uart_init(void) { struct es32_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef BSP_USING_UART0 uart = &uart0; serial0.ops = &es32f3x_uart_ops; - serial0.config = config; + serial0.config = (struct serial_configure)ES_UART0_CONFIG; /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", + rt_hw_serial_register(&serial0, ES_DEVICE_NAME_UART0, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART0 */ @@ -372,10 +430,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART1 uart = &uart1; serial1.ops = &es32f3x_uart_ops; - serial1.config = config; + serial1.config = (struct serial_configure)ES_UART1_CONFIG; /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", + rt_hw_serial_register(&serial1, ES_DEVICE_NAME_UART1, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART1 */ @@ -383,10 +441,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART2 uart = &uart2; serial2.ops = &es32f3x_uart_ops; - serial2.config = config; + serial2.config = (struct serial_configure)ES_UART2_CONFIG; /* register UART2 device */ - rt_hw_serial_register(&serial2, "uart2", + rt_hw_serial_register(&serial2, ES_DEVICE_NAME_UART2, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART2 */ @@ -394,10 +452,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART3 uart = &uart3; serial3.ops = &es32f3x_uart_ops; - serial3.config = config; + serial3.config = (struct serial_configure)ES_UART3_CONFIG; /* register UART3 device */ - rt_hw_serial_register(&serial3, "uart3", + rt_hw_serial_register(&serial3, ES_DEVICE_NAME_UART3, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART3 */ @@ -405,10 +463,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART4 uart = &uart4; serial4.ops = &es32f3x_uart_ops; - serial4.config = config; + serial4.config = (struct serial_configure)ES_UART4_CONFIG; /* register UART4 device */ - rt_hw_serial_register(&serial4, "uart4", + rt_hw_serial_register(&serial4, ES_DEVICE_NAME_UART4, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART4 */ @@ -416,10 +474,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART5 uart = &uart5; serial5.ops = &es32f3x_uart_ops; - serial5.config = config; + serial5.config = (struct serial_configure)ES_UART5_CONFIG; /* register UART5 device */ - rt_hw_serial_register(&serial5, "uart5", + rt_hw_serial_register(&serial5, ES_DEVICE_NAME_UART5, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART5 */ diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.h b/bsp/essemi/es32f369x/drivers/drv_uart.h index fed3184080..6e9b7703e0 100644 --- a/bsp/essemi/es32f369x/drivers/drv_uart.h +++ b/bsp/essemi/es32f369x/drivers/drv_uart.h @@ -3,6 +3,18 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2020-01-14 wangyq the first version diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h index 2e29a0d583..71e4e83261 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S new file mode 100644 index 0000000000..4e34d42c1d --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S @@ -0,0 +1,438 @@ +/** + ****************************************************************************** + * @file startup_es32f36xx.s + * @author AE Team + * @brief ES32F36xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + */ + + .syntax unified + .arch armv7-m + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/*bl __libc_init_array + + bl main */ + bl entry + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack /* 0, load top of stack */ + .word Reset_Handler /* 1, reset handler */ + .word NMI_Handler /* 2, nmi handler */ + .word HardFault_Handler /* 3, hard fault handler */ + .word MemManage_Handler /* 4, MPU Fault Handler */ + .word BusFault_Handler /* 5, Bus Fault Handler */ + .word UsageFault_Handler /* 6, Usage Fault Handler */ + .word 0 /* 7, Reserved */ + .word 0 /* 8, Reserved */ + .word 0 /* 9, Reserved */ + .word 0 /* 10, Reserved */ + .word SVC_Handler /* 11, svcall handler */ + .word DebugMon_Handler /* 12, Debug Monitor Handler */ + .word 0 /* 13, Reserved */ + .word PendSV_Handler /* 14, pendsv handler */ + .word SysTick_Handler /* 15, systick handler */ + .word WWDG_Handler /* 16, irq0 WWDG handler */ + .word IWDG_Handler /* 17, irq1 IWDG handler */ + .word LVD_Handler /* 18, irq2 LVD handler */ + .word RTC_Handler /* 19, irq3 RTC handler */ + .word 0 /* 20, irq4 Reserved */ + .word 0 /* 21, irq5 Reserved */ + .word CMU_Handler /* 22, irq6 CMU handler */ + .word ADC0_Handler /* 23, irq7 ADC0 handler */ + .word CAN0_TX_Handler /* 24, irq8 CAN0_TX handler */ + .word CAN0_RX0_Handler /* 25, irq9 CAN0_RX0 handler */ + .word CAN0_RX1_Handler /* 26, irq10 CAN0_RX1 handler */ + .word CAN0_EXCEPTION_Handler /* 27, irq11 CAN0_EXCEPTION handler */ + .word AD16C4T0_BRK_Handler /* 28, irq12 AD16C4T0_BRK handler */ + .word AD16C4T0_UP_Handler /* 29, irq13 AD16C4T0_UP handler */ + .word AD16C4T0_TRIG_COM_Handler /* 30, irq14 AD16C4T0_TRIG_COM handler */ + .word AD16C4T0_CC_Handler /* 31, irq15 AD16C4T0_CC handler */ + .word AD16C4T1_BRK_Handler /* 32, irq16 AD16C4T1_BRK handler */ + .word AD16C4T1_UP_Handler /* 33, irq17 AD16C4T1_UP handler */ + .word AD16C4T1_TRIG_COM_Handler /* 34, irq18 AD16C4T1_TRIG_COM handler */ + .word AD16C4T1_CC_Handler /* 35, irq19 AD16C4T1_CC handler */ + .word GP32C4T0_Handler /* 36, irq20 GP32C4T0 handler */ + .word GP32C4T1_Handler /* 37, irq21 GP32C4T1 handler */ + .word BS16T0_Handler /* 38, irq22 BS16T0 handler */ + .word BS16T1_Handler /* 39, irq23 BS16T1 handler */ + .word GP16C4T0_Handler /* 40, irq24 GP16C4T0 handler */ + .word GP16C4T1_Handler /* 41, irq25 GP16C4T1 handler */ + .word 0 /* 42, irq26 Reserved */ + .word DAC0_CH0_Handler /* 43, irq27 DAC0_CH0 handler */ + .word I2C0_EV_Handler /* 44, irq28 I2C0_EV handler */ + .word I2C0_ERR_Handler /* 45, irq29 I2C0_ERR handler */ + .word I2C1_EV_Handler /* 46 irq30 I2C1_EV handler */ + .word I2C1_ERR_Handler /* 47, irq31 I2C1_ERR handler */ + .word SPI0_I2S0_Handler /* 48, irq32 SPI0_I2S0 handler */ + .word SPI1_I2S1_Handler /* 49, irq33 SPI1_I2S1 handler */ + .word UART0_Handler /* 50, irq34 UART0 handler */ + .word UART1_Handler /* 51, irq35 UART1 handler */ + .word UART2_Handler /* 52, irq36 UART2 handler */ + .word UART3_Handler /* 53, irq37 UART3 handler */ + .word UART4_Handler /* 54, irq38 UART4 handler */ + .word UART5_Handler /* 55, irq39 UART5 handler */ + .word 0 /* 56, irq40 Reserved */ + .word 0 /* 57, irq41 Reserved */ + .word CRYPT_Handler /* 58, irq42 CRYPT handler */ + .word ACMP0_Handler /* 59, irq43 ACMP0 handler */ + .word ACMP1_Handler /* 60, irq44 ACMP1 handler */ + .word SPI2_I2S2_Handler /* 61, irq45 SPI2_I2S2 handler */ + .word 0 /* 62, irq46 Reserved */ + .word EBI_Handler /* 63, irq47 EBI handler */ + .word TRNG_Handler /* 64, irq48 TRNG handler */ + .word TSENSE_Handler /* 65, irq49 TSENSE handler */ + .word EXTI0_Handler /* 66, irq50 EXTI0 handler */ + .word EXTI1_Handler /* 67, irq51 EXTI1 handler */ + .word EXTI2_Handler /* 68, irq52 EXTI2 handler */ + .word EXTI3_Handler /* 69, irq53 EXTI3 handler */ + .word EXTI4_Handler /* 70, irq54 EXTI4 handler */ + .word EXTI5_Handler /* 71, irq55 EXTI5 handler */ + .word EXTI6_Handler /* 72, irq56 EXTI6 handler */ + .word EXTI7_Handler /* 73, irq57 EXTI7 handler */ + .word EXTI8_Handler /* 74, irq58 EXTI8 handler */ + .word EXTI9_Handler /* 75, irq59 EXTI9 handler */ + .word EXTI10_Handler /* 76, irq60 EXTI10 handler */ + .word EXTI11_Handler /* 77, irq61 EXTI11 handler */ + .word EXTI12_Handler /* 78, irq62 EXTI12 handler */ + .word EXTI13_Handler /* 79, irq63 EXTI13 handler */ + .word EXTI14_Handler /* 80, irq64 EXTI14 handler */ + .word EXTI15_Handler /* 81, irq65 EXTI15 handler */ + .word DMA_Handler /* 82, irq66 DMA handler */ + .word ADC1_Handler /* 83, irq67 ADC1 handler */ + .word DAC0_CH1_Handler /* 84, irq68 DAC0_CH1 handler */ + .word QSPI_Handler /* 85, irq69 QSPI handler */ + .word USB_INT_Handler /* 86, irq70 USB_INT handler */ + .word USB_DMA_Handler /* 87, irq71 USB_DMA handler */ + .word ACMP2_Handler /* 88, irq72 ACMP2 handler */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_Handler + .thumb_set WWDG_Handler,Default_Handler + + .weak IWDG_Handler + .thumb_set IWDG_Handler,Default_Handler + + .weak LVD_Handler + .thumb_set LVD_Handler,Default_Handler + + .weak RTC_Handler + .thumb_set RTC_Handler,Default_Handler + + .weak CMU_Handler + .thumb_set CMU_Handler,Default_Handler + + .weak ADC0_Handler + .thumb_set ADC0_Handler,Default_Handler + + .weak CAN0_TX_Handler + .thumb_set CAN0_TX_Handler,Default_Handler + + .weak CAN0_RX0_Handler + .thumb_set CAN0_RX0_Handler,Default_Handler + + .weak CAN0_RX1_Handler + .thumb_set CAN0_RX1_Handler,Default_Handler + + .weak CAN0_EXCEPTION_Handler + .thumb_set CAN0_EXCEPTION_Handler,Default_Handler + + .weak AD16C4T0_BRK_Handler + .thumb_set AD16C4T0_BRK_Handler,Default_Handler + + .weak AD16C4T0_UP_Handler + .thumb_set AD16C4T0_UP_Handler,Default_Handler + + .weak AD16C4T0_TRIG_COM_Handler + .thumb_set AD16C4T0_TRIG_COM_Handler,Default_Handler + + .weak AD16C4T0_CC_Handler + .thumb_set AD16C4T0_CC_Handler,Default_Handler + + .weak AD16C4T1_BRK_Handler + .thumb_set AD16C4T1_BRK_Handler,Default_Handler + + .weak AD16C4T1_UP_Handler + .thumb_set AD16C4T1_UP_Handler,Default_Handler + + .weak AD16C4T1_TRIG_COM_Handler + .thumb_set AD16C4T1_TRIG_COM_Handler,Default_Handler + + .weak AD16C4T1_CC_Handler + .thumb_set AD16C4T1_CC_Handler,Default_Handler + + .weak GP32C4T0_Handler + .thumb_set GP32C4T0_Handler,Default_Handler + + .weak GP32C4T1_Handler + .thumb_set GP32C4T1_Handler,Default_Handler + + .weak BS16T0_Handler + .thumb_set BS16T0_Handler,Default_Handler + + .weak BS16T1_Handler + .thumb_set BS16T1_Handler,Default_Handler + + .weak GP16C4T0_Handler + .thumb_set GP16C4T0_Handler,Default_Handler + + .weak GP16C4T1_Handler + .thumb_set GP16C4T1_Handler,Default_Handler + + .weak DAC0_CH0_Handler + .thumb_set DAC0_CH0_Handler,Default_Handler + + .weak I2C0_EV_Handler + .thumb_set I2C0_EV_Handler,Default_Handler + + .weak I2C0_ERR_Handler + .thumb_set I2C0_ERR_Handler,Default_Handler + + .weak I2C1_EV_Handler + .thumb_set I2C1_EV_Handler,Default_Handler + + .weak I2C1_ERR_Handler + .thumb_set I2C1_ERR_Handler,Default_Handler + + .weak SPI0_I2S0_Handler + .thumb_set SPI0_I2S0_Handler,Default_Handler + + .weak SPI1_I2S1_Handler + .thumb_set SPI1_I2S1_Handler,Default_Handler + + .weak UART0_Handler + .thumb_set UART0_Handler,Default_Handler + + .weak UART1_Handler + .thumb_set UART1_Handler,Default_Handler + + .weak UART2_Handler + .thumb_set UART2_Handler,Default_Handler + + .weak UART3_Handler + .thumb_set UART3_Handler,Default_Handler + + .weak UART4_Handler + .thumb_set UART4_Handler,Default_Handler + + .weak UART5_Handler + .thumb_set UART5_Handler,Default_Handler + + .weak CRYPT_Handler + .thumb_set CRYPT_Handler,Default_Handler + + .weak ACMP0_Handler + .thumb_set ACMP0_Handler,Default_Handler + + .weak ACMP1_Handler + .thumb_set ACMP1_Handler,Default_Handler + + .weak SPI2_I2S2_Handler + .thumb_set SPI2_I2S2_Handler,Default_Handler + + .weak EBI_Handler + .thumb_set EBI_Handler,Default_Handler + + .weak TRNG_Handler + .thumb_set TRNG_Handler,Default_Handler + + .weak TSENSE_Handler + .thumb_set TSENSE_Handler,Default_Handler + + .weak EXTI0_Handler + .thumb_set EXTI0_Handler,Default_Handler + + .weak EXTI1_Handler + .thumb_set EXTI1_Handler,Default_Handler + + .weak EXTI2_Handler + .thumb_set EXTI2_Handler,Default_Handler + + .weak EXTI3_Handler + .thumb_set EXTI3_Handler,Default_Handler + + .weak EXTI4_Handler + .thumb_set EXTI4_Handler,Default_Handler + + .weak EXTI5_Handler + .thumb_set EXTI5_Handler,Default_Handler + + .weak EXTI6_Handler + .thumb_set EXTI6_Handler,Default_Handler + + .weak EXTI7_Handler + .thumb_set EXTI7_Handler,Default_Handler + + .weak EXTI8_Handler + .thumb_set EXTI8_Handler,Default_Handler + + .weak EXTI9_Handler + .thumb_set EXTI9_Handler,Default_Handler + + .weak EXTI10_Handler + .thumb_set EXTI10_Handler,Default_Handler + + .weak EXTI11_Handler + .thumb_set EXTI11_Handler,Default_Handler + + .weak EXTI12_Handler + .thumb_set EXTI12_Handler,Default_Handler + + .weak EXTI13_Handler + .thumb_set EXTI13_Handler,Default_Handler + + .weak EXTI14_Handler + .thumb_set EXTI14_Handler,Default_Handler + + .weak EXTI15_Handler + .thumb_set EXTI15_Handler,Default_Handler + + .weak DMA_Handler + .thumb_set DMA_Handler,Default_Handler + + .weak ADC1_Handler + .thumb_set ADC1_Handler,Default_Handler + + .weak DAC0_CH1_Handler + .thumb_set DAC0_CH1_Handler,Default_Handler + + .weak QSPI_Handler + .thumb_set QSPI_Handler,Default_Handler + + .weak USB_INT_Handler + .thumb_set USB_INT_Handler,Default_Handler + + .weak USB_DMA_Handler + .thumb_set USB_DMA_Handler,Default_Handler + + .weak ACMP2_Handler + .thumb_set ACMP2_Handler,Default_Handler + diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s index 362c8483fe..c8aaf3ed69 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s @@ -4,6 +4,20 @@ ; author : AE Team ; data : 23 Jan 2019 ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. ;******************************************************************************* ;Stack Configuration------------------------------------------------------------ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h index 7fbb68e655..60877098d6 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h index 2638e139fd..e88c16d10b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -9,6 +9,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h index ce23ba73e9..246f6397d3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h index bd861b2d04..e14ff7851e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h index 196094eaaa..04a5d5ef5e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h index 400551ae45..55d713ed38 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h index 1ee5597055..4953ab4f14 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h index dcd6761acb..4e0f3cc152 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h index f72cb06fc7..36a4d41387 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h index d086905826..0e71f3e7e0 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h @@ -9,6 +9,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h index 4d72f6cb2b..c6471b2c2c 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -10,6 +10,21 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h index efd366889c..6f29a0cc7b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h index a4c0f372d6..d3ed85d97a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h index 3a1dfac113..8899ca4326 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h index 4731c34a67..517330ce32 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h index 7219542d60..c520c3d41a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h index 46d0c36c8e..e6a811aae3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h index 900cc43086..cb1e0bf023 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h index bf08b7de80..89d8d5875b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h index 83a200b34e..9815aa6ebc 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h index 992b3790f0..39f481a5be 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h index d58c34db24..f400be8a9f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h index a8e80b09d8..f4e2642dcd 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h @@ -7,6 +7,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h index 07319306b0..bb3ec3df89 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h index 4c31312e84..3234aa7d6e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h index 55cbbfec47..6faecf5145 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h index 63a4a01f56..ebda1db3a7 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h index 2743b83535..aff23692a3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h index c541c714ed..35063a28a1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h index 1805c3f95a..dcbc884368 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h index ff86dbbcbf..267a7db0da 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h index 6aff4435b1..cceb2587ec 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h index a525f59783..56c1b5b94d 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h index 38c991a757..d319f7a575 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h index 5629fafaa3..805be32d50 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h index ea5bd88970..a8db397a97 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ @@ -22,7 +36,7 @@ extern "C" { #endif #include - +#include "es_conf_info_select.h" #if defined (__CC_ARM) #define __INLINE__ __inline diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h index 1c6b1b942f..b5589ce07a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c index 75c53bda13..2e2dbe74d5 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c index c239d074b2..6870742cc0 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -24,6 +24,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c index c0a5e86f8a..568f7cec0e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c index 7a00c641fb..a49d150e32 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c index 24cabd8cef..ec9ec28260 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c @@ -14,6 +14,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c index 76c6e516be..8beb08de5b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* * @verbatim diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c index ad0199a486..ea64ad1245 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c index 4d17afca3b..04a0fa19de 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c index ba07048b07..7f98ce0b88 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c index a314e72b29..eae14f80c3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c index 5fc69ba3f9..d58acdfc9b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c index 48c7fe0228..33b114fa55 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * ********************************************************************************* diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 0c8f94b3a2..07d7dc5f60 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * ********************************************************************************* diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c index 686bb601d2..255c569463 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -16,6 +16,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== @@ -185,7 +199,7 @@ void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) for (i = 0; i < 16; ++i) { if (((pin >> i) & 0x1) == 0) continue; - + /* Get position and 2-bits mask */ pos = i << 1; mask = 0x3 << pos; diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c index 419bb25481..37ec31d67d 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c index 9570ddf8f7..c018037845 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c index e350c0a3ac..a2265bc1dc 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c index 1595d520e6..cc178feb7f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c index 4d52faee86..ca28cbf091 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c index e26037fcfc..3546c0b3be 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c index bb588747db..0d411b0bbd 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c index d0c0ecb3ac..b8bd90ffc1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ #include "ald_qspi.h" diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c index c5bd06b325..55869f621b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c index c0fd24b64f..baf3e5d205 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -18,6 +18,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c index c423f657cb..684e1eb5e8 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c index ce78e605a7..470167d65e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c index 31f7491679..384175d117 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ #include "ald_sram.h" diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c index 49e8ccee2c..7860499237 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c index 200f8db8bc..54496cec18 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c index b5bbc8534b..90c341c864 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c index f747967e32..84c96348c6 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c index 26605cd791..3524853e37 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c index 1e69e95d8f..2077cdabed 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ #include "ald_conf.h" diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c index bd247fc055..d2c5bfecb6 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/project.uvoptx b/bsp/essemi/es32f369x/project.uvoptx index 9820d88eaa..2ee2601b40 100644 --- a/bsp/essemi/es32f369x/project.uvoptx +++ b/bsp/essemi/es32f369x/project.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -176,7 +176,7 @@ Applications - 1 + 0 0 0 0 @@ -195,7 +195,7 @@ - cpu + CPU 0 0 0 @@ -275,66 +275,6 @@ 0 0 0 - ..\..\..\components\drivers\can\can.c - can.c - 0 - 0 - - - 3 - 8 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c - 0 - 0 - - - 3 - 9 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c_core.c - i2c_core.c - 0 - 0 - - - 3 - 10 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c_dev.c - i2c_dev.c - 0 - 0 - - - 3 - 11 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - i2c-bit-ops.c - 0 - 0 - - - 3 - 12 - 1 - 0 - 0 - 0 ..\..\..\components\drivers\misc\pin.c pin.c 0 @@ -342,55 +282,7 @@ 3 - 13 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\misc\adc.c - adc.c - 0 - 0 - - - 3 - 14 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - rt_drv_pwm.c - 0 - 0 - - - 3 - 15 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\pm\pm.c - pm.c - 0 - 0 - - - 3 - 16 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\rtc\rtc.c - rtc.c - 0 - 0 - - - 3 - 17 + 8 1 0 0 @@ -402,43 +294,7 @@ 3 - 18 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\spi\spi_core.c - spi_core.c - 0 - 0 - - - 3 - 19 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\spi\spi_dev.c - spi_dev.c - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\completion.c - completion.c - 0 - 0 - - - 3 - 21 + 9 1 0 0 @@ -450,7 +306,7 @@ 3 - 22 + 10 1 0 0 @@ -462,7 +318,31 @@ 3 - 23 + 11 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 3 + 13 1 0 0 @@ -474,7 +354,7 @@ 3 - 24 + 14 1 0 0 @@ -486,7 +366,7 @@ 3 - 25 + 15 1 0 0 @@ -496,18 +376,6 @@ 0 0 - - 3 - 26 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c - 0 - 0 - @@ -518,19 +386,7 @@ 0 4 - 27 - 1 - 0 - 0 - 0 - drivers\board.c - board.c - 0 - 0 - - - 4 - 28 + 16 1 0 0 @@ -542,7 +398,7 @@ 4 - 29 + 17 1 0 0 @@ -552,6 +408,18 @@ 0 0 + + 4 + 18 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + @@ -562,7 +430,7 @@ 0 5 - 30 + 19 1 0 0 @@ -574,19 +442,7 @@ 5 - 31 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\cmd.c - cmd.c - 0 - 0 - - - 5 - 32 + 20 1 0 0 @@ -596,6 +452,18 @@ 0 0 + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + @@ -604,6 +472,138 @@ 0 0 0 + + 6 + 22 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 23 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 24 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + 6 + 25 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 26 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 27 + 1 + 0 + 0 + 0 + ..\..\..\src\signal.c + signal.c + 0 + 0 + + + 6 + 28 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + 6 33 @@ -611,8 +611,8 @@ 0 0 0 - ..\..\..\src\clock.c - clock.c + ..\..\..\src\device.c + device.c 0 0 @@ -635,140 +635,28 @@ 0 0 0 - ..\..\..\src\device.c - device.c + ..\..\..\src\clock.c + clock.c 0 0 + + + + libc + 0 + 0 + 0 + 0 - 6 + 7 36 1 0 0 0 - ..\..\..\src\idle.c - idle.c - 0 - 0 - - - 6 - 37 - 1 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - 0 - 0 - - - 6 - 38 - 1 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - 0 - 0 - - - 6 - 39 - 1 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - 0 - 0 - - - 6 - 40 - 1 - 0 - 0 - 0 - ..\..\..\src\mem.c - mem.c - 0 - 0 - - - 6 - 41 - 1 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - 0 - 0 - - - 6 - 42 - 1 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - 0 - 0 - - - 6 - 43 - 1 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 6 - 44 - 1 - 0 - 0 - 0 - ..\..\..\src\signal.c - signal.c - 0 - 0 - - - 6 - 45 - 1 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 6 - 46 - 1 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c + ..\..\..\components\libc\compilers\common\time.c + time.c 0 0 @@ -781,176 +669,8 @@ 0 0 - 7 - 47 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - ald_acmp.c - 0 - 0 - - - 7 - 48 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - ald_adc.c - 0 - 0 - - - 7 - 49 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c - ald_bkpc.c - 0 - 0 - - - 7 - 50 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - ald_calc.c - 0 - 0 - - - 7 - 51 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - ald_can.c - 0 - 0 - - - 7 - 52 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - ald_cmu.c - 0 - 0 - - - 7 - 53 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - ald_crc.c - 0 - 0 - - - 7 - 54 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - ald_crypt.c - 0 - 0 - - - 7 - 55 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - ald_dac.c - 0 - 0 - - - 7 - 56 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c - ald_dma.c - 0 - 0 - - - 7 - 57 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - ald_ebi.c - 0 - 0 - - - 7 - 58 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c - ald_flash.c - 0 - 0 - - - 7 - 59 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - ald_flash_ext.c - 0 - 0 - - - 7 - 60 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - ald_gpio.c - 0 - 0 - - - 7 - 61 + 8 + 37 1 0 0 @@ -961,44 +681,44 @@ 0 - 7 - 62 + 8 + 38 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - ald_i2s.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c + ald_ebi.c 0 0 - 7 - 63 + 8 + 39 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - ald_iap.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + ald_rtc.c 0 0 - 7 - 64 + 8 + 40 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c - ald_nand.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c + ald_can.c 0 0 - 7 - 65 + 8 + 41 1 0 0 @@ -1009,8 +729,20 @@ 0 - 7 - 66 + 8 + 42 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + ald_cmu.c + 0 + 0 + + + 8 + 43 1 0 0 @@ -1021,7 +753,283 @@ 0 - 7 + 8 + 44 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + ald_timer.c + 0 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c + ald_sram.c + 0 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + ald_iap.c + 0 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + ald_wdt.c + 0 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + ald_rtchw.c + 0 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + ald_dac.c + 0 + 0 + + + 8 + 50 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + ald_acmp.c + 0 + 0 + + + 8 + 51 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + ald_gpio.c + 0 + 0 + + + 8 + 52 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + ald_tsense.c + 0 + 0 + + + 8 + 53 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + ald_dma.c + 0 + 0 + + + 8 + 54 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + ald_rmu.c + 0 + 0 + + + 8 + 55 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + ald_trng.c + 0 + 0 + + + 8 + 56 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + ald_spi.c + 0 + 0 + + + 8 + 57 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + ald_crc.c + 0 + 0 + + + 8 + 58 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + ald_usb.c + 0 + 0 + + + 8 + 59 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c + ald_calc.c + 0 + 0 + + + 8 + 60 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + utils.c + 0 + 0 + + + 8 + 61 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + ald_qspi.c + 0 + 0 + + + 8 + 62 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + ald_flash.c + 0 + 0 + + + 8 + 63 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + ald_nand.c + 0 + 0 + + + 8 + 64 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + ald_adc.c + 0 + 0 + + + 8 + 65 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + ald_crypt.c + 0 + 0 + + + 8 + 66 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + ald_uart.c + 0 + 0 + + + 8 67 1 0 @@ -1033,164 +1041,32 @@ 0 - 7 + 8 68 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - ald_qspi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + ald_bkpc.c 0 0 - 7 + 8 69 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - ald_rmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + ald_flash_ext.c 0 0 - 7 + 8 70 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - ald_rtc.c - 0 - 0 - - - 7 - 71 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - ald_rtchw.c - 0 - 0 - - - 7 - 72 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - ald_spi.c - 0 - 0 - - - 7 - 73 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_sram.c - 0 - 0 - - - 7 - 74 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_timer.c - 0 - 0 - - - 7 - 75 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c - ald_trng.c - 0 - 0 - - - 7 - 76 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - ald_tsense.c - 0 - 0 - - - 7 - 77 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - ald_uart.c - 0 - 0 - - - 7 - 78 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c - ald_usb.c - 0 - 0 - - - 7 - 79 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c - ald_wdt.c - 0 - 0 - - - 7 - 80 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c - utils.c - 0 - 0 - - - 7 - 81 2 0 0 @@ -1200,6 +1076,18 @@ 0 0 + + 8 + 71 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + ald_i2s.c + 0 + 0 + diff --git a/bsp/essemi/es32f369x/project.uvprojx b/bsp/essemi/es32f369x/project.uvprojx index bca6765ef1..5fc8ec68b0 100644 --- a/bsp/essemi/es32f369x/project.uvprojx +++ b/bsp/essemi/es32f369x/project.uvprojx @@ -336,9 +336,9 @@ 0 - ES32F36xx + ES32F36xx, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include + applications;.;drivers\ES;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include @@ -390,7 +390,7 @@ - cpu + CPU backtrace.c @@ -421,146 +421,17 @@ DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - can.c - 1 - ..\..\..\components\drivers\can\can.c - - - hwtimer.c - 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c - - - i2c_core.c - 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - i2c-bit-ops.c - 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - adc.c - 1 - ..\..\..\components\drivers\misc\adc.c - - - rt_drv_pwm.c - 1 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - - - pm.c - 1 - ..\..\..\components\drivers\pm\pm.c - - - rtc.c - 1 - ..\..\..\components\drivers\rtc\rtc.c - serial.c 1 ..\..\..\components\drivers\serial\serial.c - - spi_core.c - 1 - ..\..\..\components\drivers\spi\spi_core.c - - - spi_dev.c - 1 - ..\..\..\components\drivers\spi\spi_dev.c - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - dataqueue.c 1 @@ -571,6 +442,16 @@ 1 ..\..\..\components\drivers\src\pipe.c + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + ringblk_buf.c 1 @@ -586,21 +467,11 @@ 1 ..\..\..\components\drivers\src\waitqueue.c - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - Drivers - - board.c - 1 - drivers\board.c - drv_gpio.c 1 @@ -611,6 +482,11 @@ 1 drivers\drv_uart.c + + board.c + 1 + drivers\board.c + @@ -621,45 +497,25 @@ 1 ..\..\..\components\finsh\shell.c - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - msh.c 1 ..\..\..\components\finsh\msh.c + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + Kernel - clock.c + mem.c 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c - 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c + ..\..\..\src\mem.c irq.c @@ -667,19 +523,9 @@ ..\..\..\src\irq.c - kservice.c + timer.c 1 - ..\..\..\src\kservice.c - - - mem.c - 1 - ..\..\..\src\mem.c - - - mempool.c - 1 - ..\..\..\src\mempool.c + ..\..\..\src\timer.c object.c @@ -687,24 +533,64 @@ ..\..\..\src\object.c - scheduler.c + kservice.c 1 - ..\..\..\src\scheduler.c + ..\..\..\src\kservice.c signal.c 1 ..\..\..\src\signal.c + + mempool.c + 1 + ..\..\..\src\mempool.c + thread.c 1 ..\..\..\src\thread.c - timer.c + ipc.c 1 - ..\..\..\src\timer.c + ..\..\..\src\ipc.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + device.c + 1 + ..\..\..\src\device.c + + + components.c + 1 + ..\..\..\src\components.c + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c @@ -712,54 +598,9 @@ Libraries - ald_acmp.c + ald_i2c.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - - - ald_adc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - - - ald_bkpc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c - - - ald_calc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - - - ald_can.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - - - ald_cmu.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - - - ald_crc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - - - ald_crypt.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - - - ald_dac.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - - - ald_dma.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c ald_ebi.c @@ -767,125 +608,170 @@ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - ald_flash.c + ald_rtc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - ald_flash_ext.c + ald_can.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - - - ald_gpio.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - - - ald_i2c.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c - - - ald_i2s.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - - - ald_iap.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - - - ald_nand.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c ald_nor_lcd.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + + ald_cmu.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + ald_pis.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c - - ald_pmu.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c - - - ald_qspi.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - - - ald_rmu.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - - - ald_rtc.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - - - ald_rtchw.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - - - ald_spi.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - - - ald_sram.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_timer.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_trng.c + ald_sram.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_tsense.c + ald_iap.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - - - ald_uart.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - - - ald_usb.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c ald_wdt.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + + ald_rtchw.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + + + ald_dac.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + + + ald_acmp.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + + + ald_gpio.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + + + ald_tsense.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + + + ald_dma.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + + + ald_rmu.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + + + ald_trng.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + + + ald_spi.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + + + ald_crc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + + + ald_usb.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + + + ald_calc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c + utils.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + + ald_qspi.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + + + ald_flash.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + + + ald_nand.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + + + ald_adc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + + + ald_crypt.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + + + ald_uart.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + + + ald_pmu.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + + + ald_bkpc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + + + ald_flash_ext.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + startup_es32f36xx.s 2 libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + + ald_i2s.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + diff --git a/bsp/essemi/es32f369x/rtconfig.h b/bsp/essemi/es32f369x/rtconfig.h index 54bd07901b..819056462c 100644 --- a/bsp/essemi/es32f369x/rtconfig.h +++ b/bsp/essemi/es32f369x/rtconfig.h @@ -15,7 +15,7 @@ #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 #define RT_DEBUG #define RT_DEBUG_COLOR @@ -26,6 +26,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS /* Memory Management */ @@ -76,22 +77,14 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_CAN -#define RT_USING_HWTIMER -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS #define RT_USING_PIN -#define RT_USING_ADC -#define RT_USING_PWM -#define RT_USING_PM -#define RT_USING_RTC -#define RT_USING_SPI /* Using USB */ /* POSIX layer and C standard library */ +#define RT_LIBC_USING_TIME /* Network */ @@ -144,6 +137,9 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ @@ -152,6 +148,9 @@ /* samples: kernel and components samples */ + +/* games: games run on RT-Thread console */ + #define SOC_ES32F3696LT /* Hardware Drivers Config */ @@ -179,7 +178,7 @@ /* RTC Drivers */ -/* HWtimer Drivers */ +/* HWTIMER Drivers */ /* PWM Drivers */ diff --git a/bsp/essemi/es32f369x/template.uvoptx b/bsp/essemi/es32f369x/template.uvoptx index 8d3f54f7f5..8e6583c22c 100644 --- a/bsp/essemi/es32f369x/template.uvoptx +++ b/bsp/essemi/es32f369x/template.uvoptx @@ -101,7 +101,9 @@ 0 0 1 - 2 + 0 + 0 + 3 @@ -165,6 +167,10 @@ + + + + diff --git a/bsp/essemi/es32f369x/template.uvprojx b/bsp/essemi/es32f369x/template.uvprojx index ad28753eb3..df9bb4e30c 100644 --- a/bsp/essemi/es32f369x/template.uvprojx +++ b/bsp/essemi/es32f369x/template.uvprojx @@ -10,11 +10,13 @@ rt-thread 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 ES32F3696LT Eastsoft - Eastsoft.ES32_DFP.1.0.5 + Eastsoft.ES32_DFP.7.2350 http://www.essemi.com IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -182,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -322,6 +325,7 @@ 0 0 1 + 0 0 1 1 From c444c5d3d49595ae9f5323e083355f6b9f0420ee Mon Sep 17 00:00:00 2001 From: THEWON Date: Wed, 16 Jun 2021 16:37:53 +0800 Subject: [PATCH 5/5] =?UTF-8?q?update=20bsp/stm32/libraries/HAL=5FDrivers/?= =?UTF-8?q?drv=5Fusbh.c.=20=E4=BF=AE=E6=94=B9=E4=BA=86=20hcd=20=E5=88=9D?= =?UTF-8?q?=E5=A7=8B=E5=8C=96=E5=87=BD=E6=95=B0=E3=80=82=E5=88=A0=E6=8E=89?= =?UTF-8?q?=20RT=5FASSERT=20=E5=AE=8F=E8=B0=83=E7=94=A8=E5=87=BD=E6=95=B0?= =?UTF-8?q?=E7=9A=84=E6=93=8D=E4=BD=9C=E6=96=B9=E6=B3=95=E3=80=82=E9=98=B2?= =?UTF-8?q?=E6=AD=A2=E5=9B=A0=E7=A6=81=E7=94=A8=E8=B0=83=E8=AF=95=20RT=5FA?= =?UTF-8?q?SSERT=20=E5=AE=9A=E4=B9=89=E4=B8=BA=E7=A9=BA=EF=BC=8C=E5=AF=BC?= =?UTF-8?q?=E8=87=B4=20HAL=5FHCD=5FInit=20=E4=B8=8D=E8=A2=AB=E7=BC=96?= =?UTF-8?q?=E8=AF=91=E7=9A=84=E6=83=85=E5=86=B5=E5=87=BA=E7=8E=B0=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32/libraries/HAL_Drivers/drv_usbh.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c index ad65accd07..9486e1a56d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c @@ -197,6 +197,8 @@ static struct uhcd_ops _uhcd_ops = static rt_err_t stm32_hcd_init(rt_device_t device) { + HAL_StatusTypeDef state; + HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef *)device->user_data; hhcd->Instance = USB_OTG_FS; hhcd->Init.Host_channels = 8; @@ -204,7 +206,11 @@ static rt_err_t stm32_hcd_init(rt_device_t device) hhcd->Init.dma_enable = DISABLE; hhcd->Init.phy_itface = HCD_PHY_EMBEDDED; hhcd->Init.Sof_enable = DISABLE; - RT_ASSERT(HAL_HCD_Init(hhcd) == HAL_OK); + state = HAL_HCD_Init(hhcd); + if (state != HAL_OK) + { + return -RT_ERROR; + } HAL_HCD_Start(hhcd); #ifdef USBH_USING_CONTROLLABLE_POWER rt_pin_mode(USBH_POWER_PIN, PIN_MODE_OUTPUT);