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fix some embedded assemble issues. 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@212 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong 2009-12-18 08:25:55 +00:00
parent dbade245bf
commit 80be36d818
2 changed files with 7 additions and 7 deletions
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2
libcpu/arm/s3c24x0/cpu.c
View File

@ -23,7 +23,7 @@
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNU_C__
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;

12
libcpu/arm/s3c24x0/mmu.c
View File

@ -41,7 +41,7 @@
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
#ifdef __GNU_C__
#ifdef __GNUC__
void mmu_setttbase(register rt_uint32_t i)
{
asm ("mcr p15, 0, %0, c2, c2, 0": :"r" (i));
@ -200,35 +200,35 @@ __asm void mmu_disable()
__asm void mmu_enable_icache()
{
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x100
orr r0, r0, #0x1000
mcr p15, 0, r0, c1, c0, 0
}
__asm void mmu_enable_dcache()
{
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x02
orr r0, r0, #0x04
mcr p15, 0, r0, c1, c0, 0
}
__asm void mmu_disable_icache()
{
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x100
bic r0, r0, #0x1000
mcr p15, 0, r0, c1, c0, 0
}
__asm void mmu_disable_dcache()
{
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x100
bic r0, r0, #0x04
mcr p15, 0, r0, c1, c0, 0
}
__asm void mmu_enable_alignfault()
{
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x01
orr r0, r0, #0x02
mcr p15, 0, r0, c1, c0, 0
}