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[bsp][stm32] fix bugs of i2c hardware drivers 

在STM32F429IGTx设备上使用硬件i2c驱动程序师遇到以下几个问题：

语法错误：drv_hard_i2c.c 行67、68中i2c_handle未正常替换过来，估计是上个版本对变量重命名后因为宏定义忽略了此处修改；
语法错误：drv_hard_i2c.c 行326中缺少一个"}"导致编译出错；
初始化i2c设备过程中对双地址选项进行设置时（i2c_handle->Init.OwnAddress2Masks = I2C_OA2_NOMASK），STM32F4系列SOC没有这个配置定义，于是我直接将双地址模式关闭了（i2c_handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE）；
初始化i2c设备（DMA方式）过程中发现i2c_hard_config.h文件中未定义DMA通道配置；

主要补丁如下：
修复硬件i2c驱动代码中语法错误（drv_hard_i2c.c行67、68、326）；
关闭默认i2c双地址模式（drv_hard_i2c.c行75：I2C_DUALADDRESS_DISABLE）；
添加硬件i2c驱动配置文件DMA相关配置项，增加对SOC_SERIES_STM32F2、SOC_SERIES_STM32F4、SOC_SERIES_STM32F7系列芯片配置DMA_CHANNEL的适配
This commit is contained in:
SCZeiDan 2024-04-24 13:42:03 +08:00 committed by GitHub
parent 98a234d430
commit 7ca2ebc51a
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GPG Key ID: B5690EEEBB952194
2 changed files with 75 additions and 13 deletions
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61
bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h
View File

@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2024-02-06 Dyyt587 first version
* 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG
*/
#ifndef __I2C_HARD_CONFIG_H__
#define __I2C_HARD_CONFIG_H__
@ -32,6 +33,15 @@ extern "C" {
#ifdef BSP_I2C1_TX_USING_DMA
#ifndef I2C1_TX_DMA_CONFIG
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#define I2C1_TX_DMA_CONFIG \
{ \
.dma_rcc = I2C1_TX_DMA_RCC, \
.Instance = I2C1_TX_DMA_INSTANCE, \
.dma_irq = I2C1_TX_DMA_IRQ, \
.channel = I2C1_TX_DMA_CHANNEL \
}
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
#define I2C1_TX_DMA_CONFIG \
{ \
.dma_rcc = I2C1_TX_DMA_RCC, \
@ -39,11 +49,21 @@ extern "C" {
.dma_irq = I2C1_TX_DMA_IRQ, \
.request = DMA_REQUEST_I2C1_TX \
}
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
#endif /* I2C1_TX_DMA_CONFIG */
#endif /* BSP_I2C1_TX_USING_DMA */
#ifdef BSP_I2C1_RX_USING_DMA
#ifndef I2C1_RX_DMA_CONFIG
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#define I2C1_RX_DMA_CONFIG \
{ \
.dma_rcc = I2C1_RX_DMA_RCC, \
.Instance = I2C1_RX_DMA_INSTANCE, \
.dma_irq = I2C1_RX_DMA_IRQ, \
.channel = I2C1_RX_DMA_CHANNEL, \
}
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
#define I2C1_RX_DMA_CONFIG \
{ \
.dma_rcc = I2C1_RX_DMA_RCC, \
@ -51,6 +71,7 @@ extern "C" {
.dma_irq = I2C1_RX_DMA_IRQ, \
.request = DMA_REQUEST_I2C1_RX \
}
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
#endif /* I2C1_RX_DMA_CONFIG */
#endif /* BSP_I2C1_RX_USING_DMA */
@ -70,6 +91,15 @@ extern "C" {
#ifdef BSP_I2C2_TX_USING_DMA
#ifndef I2C2_TX_DMA_CONFIG
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#define I2C2_TX_DMA_CONFIG \
{ \
.dma_rcc = I2C2_TX_DMA_RCC, \
.Instance = I2C2_TX_DMA_INSTANCE, \
.dma_irq = I2C2_TX_DMA_IRQ, \
.channel = I2C2_TX_DMA_CHANNEL, \
}
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
#define I2C2_TX_DMA_CONFIG \
{ \
.dma_rcc = I2C2_TX_DMA_RCC, \
@ -77,11 +107,21 @@ extern "C" {
.dma_irq = I2C2_TX_DMA_IRQ, \
.request = DMA_REQUEST_I2C2_TX \
}
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
#endif /* I2C2_TX_DMA_CONFIG */
#endif /* BSP_I2C2_TX_USING_DMA */
#ifdef BSP_I2C2_RX_USING_DMA
#ifndef I2C2_RX_DMA_CONFIG
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#define I2C2_RX_DMA_CONFIG \
{ \
.dma_rcc = I2C2_RX_DMA_RCC, \
.Instance = I2C2_RX_DMA_INSTANCE, \
.dma_irq = I2C2_RX_DMA_IRQ, \
.channel = I2C2_RX_DMA_CHANNEL, \
}
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
#define I2C2_RX_DMA_CONFIG \
{ \
.dma_rcc = I2C2_RX_DMA_RCC, \
@ -89,6 +129,7 @@ extern "C" {
.dma_irq = I2C2_RX_DMA_IRQ, \
.request = DMA_REQUEST_I2C2_RX \
}
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
#endif /* I2C2_RX_DMA_CONFIG */
#endif /* BSP_I2C2_RX_USING_DMA */
@ -108,6 +149,15 @@ extern "C" {
#ifdef BSP_I2C3_TX_USING_DMA
#ifndef I2C3_TX_DMA_CONFIG
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#define I2C3_TX_DMA_CONFIG \
{ \
.dma_rcc = I2C3_TX_DMA_RCC, \
.Instance = I2C3_TX_DMA_INSTANCE, \
.dma_irq = I2C3_TX_DMA_IRQ, \
.channel = I2C3_TX_DMA_CHANNEL, \
}
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
#define I2C3_TX_DMA_CONFIG \
{ \
.dma_rcc = I2C3_TX_DMA_RCC, \
@ -115,11 +165,21 @@ extern "C" {
.dma_irq = I2C3_TX_DMA_IRQ, \
.request = DMA_REQUEST_I2C3_TX \
}
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
#endif /* I2C3_TX_DMA_CONFIG */
#endif /* BSP_I2C3_TX_USING_DMA */
#ifdef BSP_I2C3_RX_USING_DMA
#ifndef I2C3_RX_DMA_CONFIG
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#define I2C3_RX_DMA_CONFIG \
{ \
.dma_rcc = I2C3_RX_DMA_RCC, \
.Instance = I2C3_RX_DMA_INSTANCE, \
.dma_irq = I2C3_RX_DMA_IRQ, \
.channel = I2C3_RX_DMA_CHANNEL, \
}
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
#define I2C3_RX_DMA_CONFIG \
{ \
.dma_rcc = I2C3_RX_DMA_RCC, \
@ -127,6 +187,7 @@ extern "C" {
.dma_irq = I2C3_RX_DMA_IRQ, \
.request = DMA_REQUEST_I2C3_RX \
}
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
#endif /* I2C3_RX_DMA_CONFIG */
#endif /* BSP_I2C3_RX_USING_DMA */

27
bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c
View File

@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2024-02-17 Dyyt587 first version
* 2024-04-23 Zeidan fix bugs, test on STM32F429IGTx
*/
#include <rtthread.h>
@ -63,16 +64,15 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv)
i2c_handle->Init.Timing = cfg->timing;
#endif /* defined(SOC_SERIES_STM32H7) */
#if defined(SOC_SERIES_STM32F4)
hi2c1.Init.ClockSpeed = 100000;
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
i2c_handle->Init.ClockSpeed = 100000;
i2c_handle->Init.DutyCycle = I2C_DUTYCYCLE_2;
#endif /* defined(SOC_SERIES_STM32F4) */
i2c_handle->Init.OwnAddress1 = 0;
i2c_handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
#if defined(SOC_SERIES_STM32H7)
i2c_handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
#endif /* defined(SOC_SERIES_STM32H7) */
i2c_handle->Init.OwnAddress2 = 0;
i2c_handle->Init.OwnAddress2Masks = I2C_OA2_NOMASK;
i2c_handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
i2c_handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
i2c_handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_DeInit(i2c_handle) != HAL_OK)
@ -203,11 +203,11 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus,
: "nuknown mode");
if ((i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN))
{
ret = HAL_I2C_Master_Seq_Receive_DMA(handle, (msg->addr<<1) , msg->buf, msg->len, mode);
ret = HAL_I2C_Master_Seq_Receive_DMA(handle, (msg->addr<<1), msg->buf, msg->len, mode);
}
else
{
ret = HAL_I2C_Master_Seq_Receive_IT(handle, (msg->addr<<1) , msg->buf, msg->len, mode);
ret = HAL_I2C_Master_Seq_Receive_IT(handle, (msg->addr<<1), msg->buf, msg->len, mode);
}
if (ret != RT_EOK)
{
@ -228,11 +228,11 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus,
: "nuknown mode");
if ((i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN))
{
ret = HAL_I2C_Master_Seq_Transmit_DMA(handle, (msg->addr<<1) , msg->buf, msg->len, mode);
ret = HAL_I2C_Master_Seq_Transmit_DMA(handle, (msg->addr<<1), msg->buf, msg->len, mode);
}
else
{
ret = HAL_I2C_Master_Seq_Transmit_IT(handle, (msg->addr<<1) , msg->buf, msg->len, mode);
ret = HAL_I2C_Master_Seq_Transmit_IT(handle, (msg->addr<<1), msg->buf, msg->len, mode);
}
if (ret != RT_EOK)
{
@ -263,11 +263,11 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus,
: "nuknown mode");
if ((i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN))
{
ret = HAL_I2C_Master_Seq_Receive_DMA(handle, (msg->addr<<1) , msg->buf, msg->len, mode);
ret = HAL_I2C_Master_Seq_Receive_DMA(handle, (msg->addr<<1), msg->buf, msg->len, mode);
}
else
{
ret = HAL_I2C_Master_Seq_Receive_IT(handle,(msg->addr<<1) , msg->buf, msg->len, mode);
ret = HAL_I2C_Master_Seq_Receive_IT(handle,(msg->addr<<1), msg->buf, msg->len, mode);
}
if (ret != RT_EOK)
{
@ -287,11 +287,11 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus,
: "nuknown mode");
if ((i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN))
{
ret = HAL_I2C_Master_Seq_Transmit_DMA(handle, (msg->addr<<1) , msg->buf, msg->len, mode);
ret = HAL_I2C_Master_Seq_Transmit_DMA(handle, (msg->addr<<1), msg->buf, msg->len, mode);
}
else
{
ret = HAL_I2C_Master_Seq_Transmit_IT(handle, (msg->addr<<1) , msg->buf, msg->len, mode);
ret = HAL_I2C_Master_Seq_Transmit_IT(handle, (msg->addr<<1), msg->buf, msg->len, mode);
}
if (ret != RT_EOK)
{
@ -321,8 +321,9 @@ out:
if (handle->ErrorCode == HAL_I2C_ERROR_BERR)
{
LOG_D("I2C BUS Error now stoped");
handle->Instance->CR1 |= I2C_IT_STOPI;
handle->Instance->CR1 |= I2C_CR1_STOP;
ret=i-1;
}
return ret;
}