diff --git a/.gitignore b/.gitignore
index f08897fb2d..ce663a867d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -48,3 +48,4 @@ tags
 .history
 CMakeLists.txt
 cmake-build-debug
+*.mk
diff --git a/bsp/tms320f28379d/drivers/config/pwm_config.h b/bsp/c28x/libraries/HAL_Drivers/config/pwm_config.h
similarity index 81%
rename from bsp/tms320f28379d/drivers/config/pwm_config.h
rename to bsp/c28x/libraries/HAL_Drivers/config/pwm_config.h
index 90b0b0bc63..d490cb4d71 100644
--- a/bsp/tms320f28379d/drivers/config/pwm_config.h
+++ b/bsp/c28x/libraries/HAL_Drivers/config/pwm_config.h
@@ -15,10 +15,6 @@
 #include "rtthread.h"
 #include "drv_config.h"
 
-#define BSP_USING_PWM1
-#define BSP_USING_PWM2
-#define BSP_USING_PWM3
-#define BSP_USING_PWM4
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -58,18 +54,6 @@ extern "C" {
     }
     #endif
 #endif
-#define EPWM1_MAX_DB   0x03FF
-#define EPWM2_MAX_DB   0x03FF
-#define EPWM3_MAX_DB   0x03FF
-#define EPWM1_MIN_DB   0
-#define EPWM2_MIN_DB   0
-#define EPWM3_MIN_DB   0
-#define DB_UP          1
-#define DB_DOWN        0
-
-#define RT_HSPCLKDIV TB_DIV4
-#define RT_CLKDIV TB_DIV4
-#define RT_CTRMODE TB_COUNT_UPDOWN
 
 #define TZ_OFF  2
 #define TZ_ON   1
diff --git a/bsp/tms320f28379d/drivers/drv_config.h b/bsp/c28x/libraries/HAL_Drivers/drv_config.h
similarity index 100%
rename from bsp/tms320f28379d/drivers/drv_config.h
rename to bsp/c28x/libraries/HAL_Drivers/drv_config.h
diff --git a/bsp/c28x/libraries/HAL_Drivers/drv_gpio.c b/bsp/c28x/libraries/HAL_Drivers/drv_gpio.c
new file mode 100644
index 0000000000..89d5931799
--- /dev/null
+++ b/bsp/c28x/libraries/HAL_Drivers/drv_gpio.c
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-08-28     qiyu     first version
+ */
+#include <rthw.h>
+#include "drv_gpio.h"
+#include "F2837xD_device.h"
+#include "F28x_Project.h"     // Device Headerfile and Examples Include File
+#ifdef RT_USING_PIN
+
+// the gpio pin number for each port is 32, while it is 16 for ARM
+#define PIN_NUM(port, no) (((((port) & 0xFu) << 5) | ((no) & 0x1F)))
+#define PIN_PORT(pin) ((rt_uint16_t)(((pin) >> 5) & 0xFu))
+#define PIN_NO(pin) ((rt_uint16_t)((pin) & 0x1Fu))
+
+#define PIN_c28x_PORT(pin) (volatile Uint32 *)&GpioDataRegs + (PIN_PORT(pin))*GPY_DATA_OFFSET
+#define PIN_c28x_PIN(pin) ((rt_uint32_t)(1u << PIN_NO(pin)))
+
+#define PIN_c28x_PORT_MAX 6 /* gpioA to GPIOF in total*/
+#define PIN_IRQ_MAX 5   /* XINT1 to XINT5 in total */
+
+static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                     rt_uint32_t mode, void (*hdr)(void *args), void *args);
+static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin);
+static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                     rt_uint32_t enabled);
+
+static rt_base_t c28x_pin_get(const char *name)
+{
+    int hw_pin_num = 0;
+    int i, name_len;
+
+    name_len = rt_strlen(name);
+
+    if ((name_len < 3) || (name_len >= 7))
+    {
+        return -RT_EINVAL;
+    }
+    /*
+     * PX.y
+     */
+    if ((name[0] != 'P') || (name[2] != '.'))
+    {
+        return -RT_EINVAL;
+    }
+
+    for (i = 3; i < name_len; i++)
+    {
+        hw_pin_num *= 10;
+        hw_pin_num += name[i] - '0';
+    }
+    return hw_pin_num;
+}
+
+static void c28x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    volatile Uint32 *gpioDataReg;
+    Uint32 pinMask;
+    if (PIN_PORT(pin) < PIN_c28x_PORT_MAX)
+    {
+        gpioDataReg = PIN_c28x_PORT(pin);
+        pinMask = 1UL << (PIN_NO(pin));
+        if (value == 0)
+        {
+            gpioDataReg[GPYCLEAR] = pinMask;
+        }
+        else
+        {
+            gpioDataReg[GPYSET] = pinMask;
+        }
+    }
+}
+
+static int c28x_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    volatile Uint32 *gpioDataReg;
+    int value = PIN_LOW;
+
+    if (PIN_PORT(pin) < PIN_c28x_PORT_MAX)
+    {
+        gpioDataReg = PIN_c28x_PORT(pin);
+        value = (gpioDataReg[GPYDAT] >> PIN_NO(pin)) & 0x1;
+    }
+
+    return value;
+}
+
+static void c28x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    volatile Uint32 *gpioBaseAddr;
+    volatile Uint32 *dir, *pud, *odr;
+    if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
+    {
+        return;
+    }
+    rt_uint32_t pinMask;
+    pinMask = 1UL << PIN_NO(pin);
+    gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (PIN_PORT(pin))*GPY_CTRL_OFFSET;
+
+    dir = gpioBaseAddr + GPYDIR;
+    pud = gpioBaseAddr + GPYPUD;
+    odr = gpioBaseAddr + GPYODR;
+
+    EALLOW;
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        *dir |= pinMask;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        *dir &= ~pinMask;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        *dir &= ~pinMask;
+        *pud &= ~pinMask;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        *dir &= ~pinMask;
+        *pud |= pinMask;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        *dir |= pinMask;
+        *odr |= pinMask;
+    }
+    EDIS;
+}
+
+const static struct rt_pin_ops _c28x_pin_ops =
+{
+    c28x_pin_mode,
+    c28x_pin_write,
+    c28x_pin_read,
+    c28x_pin_attach_irq,
+    c28x_pin_dettach_irq,
+    c28x_pin_irq_enable,
+    c28x_pin_get,
+};
+
+int rt_hw_pin_init(void)
+{
+    return rt_device_pin_register("pin", &_c28x_pin_ops, RT_NULL);
+}
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+
+static rt_int16_t pin_irq_xint_tab[] =
+{
+    BSP_XINT1_PIN,
+    BSP_XINT2_PIN,
+    BSP_XINT3_PIN,
+    BSP_XINT4_PIN,
+    BSP_XINT5_PIN
+};
+rt_inline rt_int32_t get_irq_index(rt_uint32_t pin)
+{
+    int i;
+    for(i = 0 ; i < PIN_IRQ_MAX ; i++)
+    {
+        if(pin_irq_xint_tab[i] == pin)
+        {
+            return i;
+        }
+    }
+    return -1;
+}
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+
+static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+    irqindex = get_irq_index(pin);
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+        pin_irq_hdr_tab[irqindex].hdr == hdr &&
+        pin_irq_hdr_tab[irqindex].mode == mode &&
+        pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return -RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    rt_uint16_t i;
+    if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+
+    for(i = 0 ; i < PIN_IRQ_MAX ; i++)
+    {
+        if(pin_irq_hdr_tab[i].pin == pin)
+        {
+            irqindex = i;
+            break;
+        }
+    }
+    if (irqindex == -1)
+    {
+        return -RT_ENOSYS;
+    }
+    level = rt_hw_interrupt_disable();
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                     rt_uint32_t enabled)
+{
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    rt_uint16_t channel;
+    rt_uint16_t edge_mode,pin_mode;
+
+    if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+
+    irqindex = get_irq_index(pin);
+
+    /* irqindex+1 = channel*/
+    if (irqindex < 0 || irqindex >= PIN_IRQ_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return -RT_ENOSYS;
+        }
+
+        /*
+         * 1. set the edge mode of interrupt triggering
+         * 2. set the GPIO mode
+         * 3. enable XINT channel and set the input source
+        */
+        channel = irqindex+1;
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            edge_mode = 1;
+            pin_mode = PIN_MODE_INPUT_PULLDOWN;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            edge_mode = 0;
+            pin_mode = PIN_MODE_INPUT_PULLUP;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            edge_mode = 3;
+            pin_mode = PIN_MODE_INPUT;
+            break;
+        }
+        if(channel == 1)
+        {
+            XintRegs.XINT1CR.bit.ENABLE = 1;        // Enable XINT1
+            EALLOW;
+            InputXbarRegs.INPUT4SELECT = pin;       //Set XINT1 source to GPIO-pin
+            EDIS;
+            XintRegs.XINT1CR.bit.POLARITY = edge_mode;      // Falling edge interrupt
+        }
+        else if(channel == 2)
+        {
+            XintRegs.XINT2CR.bit.ENABLE = 1;        // Enable XINT2
+            EALLOW;
+            InputXbarRegs.INPUT5SELECT = pin;       //Set XINT1 source to GPIO-pin
+            EDIS;
+            XintRegs.XINT2CR.bit.POLARITY = edge_mode;      // Falling edge interrupt
+        }
+        else if(channel == 3)
+        {
+            XintRegs.XINT3CR.bit.ENABLE = 1;        // Enable XINT2
+            EALLOW;
+            InputXbarRegs.INPUT6SELECT = pin;       //Set XINT1 source to GPIO-pin
+            EDIS;
+            XintRegs.XINT3CR.bit.POLARITY = edge_mode;      // Falling edge interrupt
+        }
+        else if(channel == 4)
+        {
+            XintRegs.XINT4CR.bit.ENABLE = 1;        // Enable XINT2
+            EALLOW;
+            InputXbarRegs.INPUT13SELECT = pin;       //Set XINT1 source to GPIO-pin
+            EDIS;
+            XintRegs.XINT4CR.bit.POLARITY = edge_mode;      // Falling edge interrupt
+        }
+        else if(channel == 5)
+        {
+            XintRegs.XINT5CR.bit.ENABLE = 1;        // Enable XINT2
+            EALLOW;
+            InputXbarRegs.INPUT14SELECT = pin;       //Set XINT1 source to GPIO-pin
+            EDIS;
+            XintRegs.XINT5CR.bit.POLARITY = edge_mode;      // Falling edge interrupt
+        }
+
+        c28x_pin_mode(device, pin, pin_mode);
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        level = rt_hw_interrupt_disable();
+        channel = irqindex+1;
+        /*
+         * TODO modify this simpler
+         */
+        if(channel == 1)
+        {
+            XintRegs.XINT1CR.bit.ENABLE = 0;        // Disable XINT1
+        }
+        else if(channel == 2)
+        {
+            XintRegs.XINT2CR.bit.ENABLE = 0;        // Disable XINT2
+        }
+        else if(channel == 3)
+        {
+            XintRegs.XINT3CR.bit.ENABLE = 0;        // Disable XINT2
+        }
+        else if(channel == 4)
+        {
+            XintRegs.XINT4CR.bit.ENABLE = 0;        // Disable XINT2
+        }
+        else if(channel == 5)
+        {
+            XintRegs.XINT5CR.bit.ENABLE = 0;        // Disable XINT2
+        }
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+
+void GPIO_XINT_Callback(rt_int16_t XINT_number);
+
+interrupt void XINT1_Handler(void)
+{
+    rt_interrupt_enter();
+    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+    GPIO_XINT_Callback(1);
+    rt_interrupt_leave();
+}
+
+interrupt void XINT2_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_XINT_Callback(2);
+    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+    rt_interrupt_leave();
+}
+
+interrupt void XINT3_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_XINT_Callback(3);
+    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+    rt_interrupt_leave();
+}
+
+interrupt void XINT4_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_XINT_Callback(4);
+    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+    rt_interrupt_leave();
+}
+
+interrupt void XINT5_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_XINT_Callback(5);
+    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+    rt_interrupt_leave();
+}
+
+void GPIO_XINT_Callback(rt_int16_t XINT_number)
+{
+    rt_int32_t irqindex = XINT_number - 1;
+    if(pin_irq_hdr_tab[irqindex].hdr)
+    {
+        pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
+    }
+}
+
+#endif /* RT_USING_PIN */
+
+
+
diff --git a/bsp/c28x/libraries/HAL_Drivers/drv_gpio.h b/bsp/c28x/libraries/HAL_Drivers/drv_gpio.h
new file mode 100644
index 0000000000..ceb1cc1cfa
--- /dev/null
+++ b/bsp/c28x/libraries/HAL_Drivers/drv_gpio.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-08-28     qiyu     first version
+ */
+
+#ifndef DRIVERS_DRV_GPIO_H_
+#define DRIVERS_DRV_GPIO_H_
+
+#include <board.h>
+#include "rtdevice.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int rt_hw_pin_init(void);
+
+#ifndef BSP_XINT1_PIN
+#define BSP_XINT1_PIN -1
+#endif
+#ifndef BSP_XINT2_PIN
+#define BSP_XINT2_PIN -1
+#endif
+#ifndef BSP_XINT3_PIN
+#define BSP_XINT3_PIN -1
+#endif
+#ifndef BSP_XINT4_PIN
+#define BSP_XINT4_PIN -1
+#endif
+#ifndef BSP_XINT5_PIN
+#define BSP_XINT5_PIN -1
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* DRIVERS_DRV_GPIO_H_ */
diff --git a/bsp/tms320f28379d/drivers/drv_pwm.c b/bsp/c28x/libraries/HAL_Drivers/drv_pwm.c
similarity index 63%
rename from bsp/tms320f28379d/drivers/drv_pwm.c
rename to bsp/c28x/libraries/HAL_Drivers/drv_pwm.c
index 4db7f6b079..336e7f6e57 100644
--- a/bsp/tms320f28379d/drivers/drv_pwm.c
+++ b/bsp/c28x/libraries/HAL_Drivers/drv_pwm.c
@@ -17,7 +17,7 @@
 /*
  * for now, cpu rate is a fixed value, waiting to be modified to an auto-ajustable variable.
 */
-
+#ifdef BSP_USING_PWM
 rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data);
 
 #define CPU_FREQUENCY 200e6
@@ -120,8 +120,6 @@ static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_config
     {
         return -RT_ERROR;
     }
-
-
     /*
      * TODO Unknown problem
      * the clock division configuration of PWM module is 1
@@ -136,13 +134,8 @@ static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_config
 
     epwm->TBPRD = prd;                       /* Set timer period*/
     epwm->TBCTR = 0x0000;                     /* Clear counter*/
-    epwm->TBCTL.bit.CTRMODE = RT_CTRMODE; /* Count up*/
-    epwm->TBCTL.bit.HSPCLKDIV = TB_DIV1;       /* Clock ratio to SYSCLKOUT*/
-    epwm->TBCTL.bit.CLKDIV = TB_DIV1;
     epwm->CMPCTL.bit.SHDWAMODE = RT_SHADOW_MODE;    /* Load registers every ZERO*/
     epwm->CMPCTL.bit.SHDWBMODE = RT_SHADOW_MODE;
-    epwm->CMPCTL.bit.LOADAMODE = RT_LOAD_TIME;
-    epwm->CMPCTL.bit.LOADBMODE = RT_LOAD_TIME;
     /* Setup compare */
     if(configuration->channel == CHANNEL_A)
     {
@@ -180,9 +173,7 @@ static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_config
     epwm->DBCTL.bit.IN_MODE = DBA_ALL;
     /* if disable dead time, set dead_time to 0 */
 
-    epwm->ETSEL.bit.INTSEL = ET_CTR_ZERO;    /* Select INT on Zero event */
-    epwm->ETPS.bit.INTPRD = ET_1ST;          /* Generate INT on 1st event */
-
+#ifdef BSP_PWM1_CTR_MODE_UPDOWN
     if(phase<180)
     {
         epwm->TBPHS.bit.TBPHS = prd * phase/180;
@@ -192,6 +183,7 @@ static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_config
         epwm->TBPHS.bit.TBPHS = prd-prd * (phase-180)/180;
         epwm->TBCTL.bit.PHSDIR = 1; /* count up*/
     }
+#endif
     if(epwm == &EPwm1Regs)
     {
         epwm->TBCTL.bit.PHSEN = TB_DISABLE;        /* Disable phase loading */
@@ -374,52 +366,168 @@ static void pwm_isr(struct rt_device_pwm *rt_pwm)
     rt_interrupt_leave();   \
 }
 
-#ifdef BSP_USING_PWM1
+#ifdef BSP_PWM1_IT_ENABLE
 EPWM_ISR_DEFINE(1)
+void EPWM1_Isr();
+#endif
+#ifdef BSP_PWM2_IT_ENABLE
+EPWM_ISR_DEFINE(2)
+void EPWM2_Isr();
+#endif
+#ifdef BSP_PWM3_IT_ENABLE
+EPWM_ISR_DEFINE(3)
+void EPWM3_Isr();
+#endif
+#ifdef BSP_PWM4_IT_ENABLE
+EPWM_ISR_DEFINE(4)
+void EPWM4_Isr();
 #endif
 
-void EPWM1_Isr();
 
 static int c28x_hw_pwm_init(struct c28x_pwm *device)
 {
-    EALLOW;
-    /* Assigning ISR to PIE */
-    PieVectTable.EPWM1_INT = &EPWM1_Isr;
-    /* ENABLE Interrupt */
-    EDIS;
     IER |= M_INT3;
     rt_err_t result = 0;
-
     EALLOW;
 #ifdef BSP_USING_PWM1
-    GpioCtrlRegs.GPAPUD.all |= 5<<(1-1)*4;      /* Disable pull-up on GPIO0 (EPWM1A) */
-    GpioCtrlRegs.GPAMUX1.all|= 5<<(1-1)*4;      /* Configure GPIO0 as EPWM1A */
+    GpioCtrlRegs.GPAPUD.all |= 5<<(1-1)*4;      /* Disable pull-up(EPWM1A) */
+    GpioCtrlRegs.GPAMUX1.all|= 5<<(1-1)*4;      /* Configure as EPWM1A */
     EPwm1Regs.TZCTL.bit.TZA = TZ_OFF;           /* diable A when trip zone */
     EPwm1Regs.TZCTL.bit.TZB = TZ_OFF;           /* diable B when trip zone */
+    EPwm1Regs.TBCTL.bit.CTRMODE = BSP_PWM1_CTRMODE;
+    EPwm1Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM1_HSPCLKDIV;       /* Clock ratio to SYSCLKOUT*/
+    EPwm1Regs.TBCTL.bit.CLKDIV = BSP_PWM1_CLKDIV;
+    EPwm1Regs.CMPCTL.bit.LOADAMODE = BSP_PWM1_LOADAMODE;
+    EPwm1Regs.CMPCTL.bit.LOADBMODE = BSP_PWM1_LOADAMODE;
+    #ifdef BSP_PWM1_IT_ENABLE
+        EPwm1Regs.ETSEL.bit.INTEN = 1;               /* Enable INT */
+        EPwm1Regs.ETSEL.bit.INTSEL = BSP_PWM1_INTSEL;
+        EPwm1Regs.ETPS.bit.INTPRD = BSP_PWM1_INTPRD;
+        /* Assigning ISR to PIE */
+        PieVectTable.EPWM1_INT = &EPWM1_Isr;
+        /* ENABLE Interrupt */
+    #else
+        EPwm1Regs.ETSEL.bit.INTEN = 0;               /* Disable INT */
+    #endif
+    #ifdef BSP_PWM1_ADC_TRIGGER
+        EPwm1Regs.ETSEL.bit.SOCAEN    = 1;        // Enable SOC on A group
+        EPwm1Regs.ETSEL.bit.SOCASEL  = BSP_PWM1_SOCASEL;        // Select SOC from zero
+        EPwm1Regs.ETPS.bit.SOCAPRD   = BSP_PWM1_SOCAPRD;        // Generate pulse on 1st event
+    #else
+        EPwm1Regs.ETSEL.bit.SOCAEN    = 0;        // Disable SOC on A group
+    #endif
+    #ifdef BSP_PWM1_MASTER
+        EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        /* Disable phase loading */
+        EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
+    #else
+        EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;        /* Disable phase loading */
+        EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
+    #endif
 #endif
 #ifdef BSP_USING_PWM2
-    GpioCtrlRegs.GPAPUD.all |= 5<<(2-1)*4;      /* Disable pull-up on GPIO0 (EPWM1A) */
-    GpioCtrlRegs.GPAMUX1.all|= 5<<(2-1)*4;      /* Configure GPIO0 as EPWM1A */
+    GpioCtrlRegs.GPAPUD.all |= 5<<(2-1)*4;      /* Disable pull-up on  (EPWM2A) */
+    GpioCtrlRegs.GPAMUX1.all|= 5<<(2-1)*4;      /* Configure as EPWM2A */
     EPwm2Regs.TZCTL.bit.TZA = TZ_OFF;           /* diable A when trip zone */
     EPwm2Regs.TZCTL.bit.TZB = TZ_OFF;           /* diable B when trip zone */
+    EPwm2Regs.TBCTL.bit.CTRMODE = BSP_PWM2_CTRMODE;
+    EPwm2Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM2_HSPCLKDIV;       /* Clock ratio to SYSCLKOUT*/
+    EPwm2Regs.TBCTL.bit.CLKDIV = BSP_PWM2_CLKDIV;
+    EPwm2Regs.CMPCTL.bit.LOADAMODE = BSP_PWM2_LOADAMODE;
+    EPwm2Regs.CMPCTL.bit.LOADBMODE = BSP_PWM2_LOADAMODE;
+    #ifdef BSP_PWM2_IT_ENABLE
+        EPwm2Regs.ETSEL.bit.INTEN = 1;               /* Enable INT */
+        EPwm2Regs.ETSEL.bit.INTSEL = BSP_PWM2_INTSEL;
+        EPwm2Regs.ETPS.bit.INTPRD = BSP_PWM2_INTPRD;
+        /* Assigning ISR to PIE */
+        PieVectTable.EPWM2_INT = &EPWM2_Isr;
+        /* ENABLE Interrupt */
+    #else
+        EPwm2Regs.ETSEL.bit.INTEN = 0;               /* Disable INT */
+    #endif
+    #ifdef BSP_PWM2_ADC_TRIGGER
+        EPwm2Regs.ETSEL.bit.SOCAEN    = 1;        // Enable SOC on A group
+        EPwm2Regs.ETSEL.bit.SOCASEL  = BSP_PWM2_SOCASEL;        // Select SOC from zero
+        EPwm2Regs.ETPS.bit.SOCAPRD   = BSP_PWM2_SOCAPRD;        // Generate pulse on 1st event
+    #else
+        EPwm2Regs.ETSEL.bit.SOCAEN    = 0;        // Disable SOC on A group
+    #endif
+    #ifdef BSP_PWM2_MASTER
+        EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;        /* Disable phase loading */
+        EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
+    #else
+        EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;        /* Disable phase loading */
+        EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
+    #endif
 #endif
 #ifdef BSP_USING_PWM3
-    GpioCtrlRegs.GPAPUD.all |= 5<<(3-1)*4;      /* Disable pull-up on GPIO0 (EPWM1A) */
-    GpioCtrlRegs.GPAMUX1.all|= 5<<(3-1)*4;      /* Configure GPIO0 as EPWM1A */
+    GpioCtrlRegs.GPAPUD.all |= 5<<(3-1)*4;      /* Disable pull-up on (EPWM3A) */
+    GpioCtrlRegs.GPAMUX1.all|= 5<<(3-1)*4;      /* Configure as EPWM3A */
     EPwm3Regs.TZCTL.bit.TZA = TZ_OFF;           /* diable A when trip zone */
     EPwm3Regs.TZCTL.bit.TZB = TZ_OFF;           /* diable B when trip zone */
+    EPwm3Regs.TBCTL.bit.CTRMODE = BSP_PWM3_CTRMODE;
+    EPwm3Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM3_HSPCLKDIV;       /* Clock ratio to SYSCLKOUT*/
+    EPwm3Regs.TBCTL.bit.CLKDIV = BSP_PWM3_CLKDIV;
+    EPwm3Regs.CMPCTL.bit.LOADAMODE = BSP_PWM3_LOADAMODE;
+    EPwm3Regs.CMPCTL.bit.LOADBMODE = BSP_PWM3_LOADAMODE;
+    #ifdef BSP_PWM3_IT_ENABLE
+        EPwm3Regs.ETSEL.bit.INTEN = 1;               /* Enable INT */
+        EPwm3Regs.ETSEL.bit.INTSEL = BSP_PWM3_INTSEL;
+        EPwm3Regs.ETPS.bit.INTPRD = BSP_PWM3_INTPRD;
+        /* Assigning ISR to PIE */
+        PieVectTable.EPWM3_INT = &EPWM3_Isr;
+        /* ENABLE Interrupt */
+    #else
+        EPwm3Regs.ETSEL.bit.INTEN = 0;               /* Disable INT */
+    #endif
+    #ifdef BSP_PWM3_ADC_TRIGGER
+        EPwm3Regs.ETSEL.bit.SOCAEN    = 1;        // Enable SOC on A group
+        EPwm3Regs.ETSEL.bit.SOCASEL  = BSP_PWM3_SOCASEL;        // Select SOC from zero
+        EPwm3Regs.ETPS.bit.SOCAPRD   = BSP_PWM3_SOCAPRD;        // Generate pulse on 1st event
+    #else
+        EPwm3Regs.ETSEL.bit.SOCAEN    = 0;        // Disable SOC on A group
+    #endif
+    #ifdef BSP_PWM3_MASTER
+        EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;        /* Disable phase loading */
+        EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
+    #else
+        EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;        /* Disable phase loading */
+        EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
+    #endif
 #endif
 #ifdef BSP_USING_PWM4
-    GpioCtrlRegs.GPAPUD.all |= 5<<(4-1)*4;      /* Disable pull-up on GPIO0 (EPWM1A) */
-    GpioCtrlRegs.GPAMUX1.all|= 5<<(4-1)*4;      /* Configure GPIO0 as EPWM1A */
+    GpioCtrlRegs.GPAPUD.all |= 5<<(4-1)*4;      /* Disable pull-up on (EPWM4A) */
+    GpioCtrlRegs.GPAMUX1.all|= 5<<(4-1)*4;      /* Configure as EPWM4A */
     EPwm4Regs.TZCTL.bit.TZA = TZ_OFF;           /* diable A when trip zone */
     EPwm4Regs.TZCTL.bit.TZB = TZ_OFF;           /* diable B when trip zone */
-#endif
-#ifdef BSP_USING_PWM5
-    GpioCtrlRegs.GPAPUD.all |= 5<<(5-1)*4;      /* Disable pull-up on GPIO0 (EPWM1A) */
-    GpioCtrlRegs.GPAMUX1.all|= 5<<(5-1)*4;      /* Configure GPIO0 as EPWM1A */
-    EPwm5Regs.TZCTL.bit.TZA = TZ_OFF;           /* diable A when trip zone */
-    EPwm5Regs.TZCTL.bit.TZB = TZ_OFF;           /* diable B when trip zone */
+    EPwm4Regs.TBCTL.bit.CTRMODE = BSP_PWM4_CTRMODE;
+    EPwm4Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM4_HSPCLKDIV;       /* Clock ratio to SYSCLKOUT*/
+    EPwm4Regs.TBCTL.bit.CLKDIV = BSP_PWM4_CLKDIV;
+    EPwm4Regs.CMPCTL.bit.LOADAMODE = BSP_PWM4_LOADAMODE;
+    EPwm4Regs.CMPCTL.bit.LOADBMODE = BSP_PWM4_LOADAMODE;
+    #ifdef BSP_PWM4_IT_ENABLE
+        EPwm4Regs.ETSEL.bit.INTEN = 1;               /* Enable INT */
+        EPwm4Regs.ETSEL.bit.INTSEL = BSP_PWM4_INTSEL;
+        EPwm4Regs.ETPS.bit.INTPRD = BSP_PWM4_INTPRD;
+        /* Assigning ISR to PIE */
+        PieVectTable.EPWM4_INT = &EPWM4_Isr;
+        /* ENABLE Interrupt */
+    #else
+        EPwm4Regs.ETSEL.bit.INTEN = 0;               /* Disable INT */
+    #endif
+    #ifdef BSP_PWM4_ADC_TRIGGER
+        EPwm4Regs.ETSEL.bit.SOCAEN    = 1;        // Enable SOC on A group
+        EPwm4Regs.ETSEL.bit.SOCASEL  = BSP_PWM4_SOCASEL;        // Select SOC from zero
+        EPwm4Regs.ETPS.bit.SOCAPRD   = BSP_PWM4_SOCAPRD;        // Generate pulse on 1st event
+    #else
+        EPwm4Regs.ETSEL.bit.SOCAEN    = 0;        // Disable SOC on A group
+    #endif
+    #ifdef BSP_PWM4_MASTER
+        EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;        /* Disable phase loading */
+        EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
+    #else
+        EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;        /* Disable phase loading */
+        EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
+    #endif
 #endif
     EDIS;
 
@@ -459,20 +567,21 @@ int c28x_pwm_init(void)
     struct rt_pwm_configuration config_tmp1 =
     {
        .channel = CHANNEL_A,
-       .period = 10000,
-       .pulse = 5000,
-       .dead_time = 100,
+       .period = BSP_PWM1_INIT_PERIOD,
+       .pulse = BSP_PWM1_INIT_PULSE,
+       .dead_time = BSP_PWM1_DB,
        .phase = 0,
        .complementary = RT_TRUE
     };
     drv_pwm_set(c28x_pwm_obj[0].pwm_regs,&config_tmp1);
-    config_tmp1.phase = 180;
-    drv_pwm_set(c28x_pwm_obj[1].pwm_regs,&config_tmp1);
-    config_tmp1.phase = 90;
-    drv_pwm_set(c28x_pwm_obj[2].pwm_regs,&config_tmp1);
-    config_tmp1.phase = 270;
-    drv_pwm_set(c28x_pwm_obj[3].pwm_regs,&config_tmp1);
+//    config_tmp1.phase = BSP_PWM2_PHASE;
+//    drv_pwm_set(c28x_pwm_obj[1].pwm_regs,&config_tmp1);
+//    config_tmp1.phase = BSP_PWM3_PHASE;
+//    drv_pwm_set(c28x_pwm_obj[2].pwm_regs,&config_tmp1);
+//    config_tmp1.phase = BSP_PWM4_PHASE;
+//    drv_pwm_set(c28x_pwm_obj[3].pwm_regs,&config_tmp1);
     return result;
 
 }
 INIT_DEVICE_EXPORT(c28x_pwm_init);
+#endif /* BSP_USING_PWM */
diff --git a/bsp/tms320f28379d/drivers/drv_pwm.h b/bsp/c28x/libraries/HAL_Drivers/drv_pwm.h
similarity index 90%
rename from bsp/tms320f28379d/drivers/drv_pwm.h
rename to bsp/c28x/libraries/HAL_Drivers/drv_pwm.h
index a91ee7a7d9..d3ef2ccddd 100644
--- a/bsp/tms320f28379d/drivers/drv_pwm.h
+++ b/bsp/c28x/libraries/HAL_Drivers/drv_pwm.h
@@ -13,6 +13,7 @@
 #include <board.h>
 #include "rtdevice.h"
 
+#ifdef BSP_USING_PWM
 struct c28x_pwm
 {
     struct rt_device_pwm pwm_device;
@@ -21,5 +22,5 @@ struct c28x_pwm
 };
 
 int c28x_pwm_init(void);
-
+#endif /* BSP_USING_PWM */
 #endif /* DRIVERS_DRV_PWM_H_ */
diff --git a/bsp/tms320f28379d/drivers/drv_sci.c b/bsp/c28x/libraries/HAL_Drivers/drv_sci.c
similarity index 99%
rename from bsp/tms320f28379d/drivers/drv_sci.c
rename to bsp/c28x/libraries/HAL_Drivers/drv_sci.c
index f3240953c7..f1ba3f26d3 100644
--- a/bsp/tms320f28379d/drivers/drv_sci.c
+++ b/bsp/c28x/libraries/HAL_Drivers/drv_sci.c
@@ -14,7 +14,7 @@
 #include "F2837xD_device.h"
 #include "F2837xD_sci.h"
 
-typedef long off_t;
+//typedef long off_t;
 #include "F2837xD_sci_io.h"
 
 #ifdef RT_USING_SERIAL
diff --git a/bsp/tms320f28379d/drivers/drv_sci.h b/bsp/c28x/libraries/HAL_Drivers/drv_sci.h
similarity index 100%
rename from bsp/tms320f28379d/drivers/drv_sci.h
rename to bsp/c28x/libraries/HAL_Drivers/drv_sci.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Adc_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Adc_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Can_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Can_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_typedefs.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_typedefs.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Dma_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Dma_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_EPwm_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_EPwm_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Emif_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Emif_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Examples.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Examples.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_GlobalPrototypes.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_GlobalPrototypes.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Gpio_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Gpio_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_I2c_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_I2c_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_drivers.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_drivers.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Pie_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Pie_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_SWPrioritizedIsrLevels.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_SWPrioritizedIsrLevels.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_SysCtrl_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_SysCtrl_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Systick_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Systick_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Upp_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_Upp_defines.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_cputimervars.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_cputimervars.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_defaultisr.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_defaultisr.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_sci_io.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_sci_io.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_sdfm_drivers.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_sdfm_drivers.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_struct.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F2837xD_struct.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h
diff --git a/bsp/tms320f28379d/libraries/common/include/F28x_Project.h b/bsp/c28x/libraries/tms320f28379d/common/include/F28x_Project.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/F28x_Project.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/F28x_Project.h
diff --git a/bsp/tms320f28379d/libraries/common/include/device.h b/bsp/c28x/libraries/tms320f28379d/common/include/device.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/device.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/device.h
diff --git a/bsp/tms320f28379d/libraries/common/include/driverlib.h b/bsp/c28x/libraries/tms320f28379d/common/include/driverlib.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/driverlib.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/driverlib.h
diff --git a/bsp/tms320f28379d/libraries/common/include/stdint.h b/bsp/c28x/libraries/tms320f28379d/common/include/stdint.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/stdint.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/stdint.h
diff --git a/bsp/tms320f28379d/libraries/common/include/usb.h b/bsp/c28x/libraries/tms320f28379d/common/include/usb.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/usb.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/usb.h
diff --git a/bsp/tms320f28379d/libraries/common/include/usb_hal.h b/bsp/c28x/libraries/tms320f28379d/common/include/usb_hal.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/include/usb_hal.h
rename to bsp/c28x/libraries/tms320f28379d/common/include/usb_hal.h
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Adc.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Adc.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_CodeStartBranch.asm b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_CodeStartBranch.asm
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_CpuTimers.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_CpuTimers.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_DBGIER.asm b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_DBGIER.asm
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_DefaultISR.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_DefaultISR.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Dma.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Dma.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_ECap.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_ECap.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_EPwm.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_EPwm.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_EQep.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_EQep.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Emif.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Emif.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Gpio.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Gpio.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_I2C.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_I2C.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Lite.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Lite.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Util.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Util.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Mcbsp.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Mcbsp.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_PieCtrl.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_PieCtrl.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_PieVect.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_PieVect.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_SWPrioritizedPieVect.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_SWPrioritizedPieVect.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Sci.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Sci.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Spi.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Spi.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_SysCtrl.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_SysCtrl.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_TempSensorConv.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_TempSensorConv.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Upp.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_Upp.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_can.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_can.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_sci_io.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_sci_io.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_sdfm_drivers.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_sdfm_drivers.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_struct.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_struct.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c
diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_usDelay.asm b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/F2837xD_usDelay.asm
rename to bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm
diff --git a/bsp/tms320f28379d/libraries/common/source/device.c b/bsp/c28x/libraries/tms320f28379d/common/source/device.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/device.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/device.c
diff --git a/bsp/tms320f28379d/libraries/common/source/usb.c b/bsp/c28x/libraries/tms320f28379d/common/source/usb.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/usb.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/usb.c
diff --git a/bsp/tms320f28379d/libraries/common/source/usb_hal.c b/bsp/c28x/libraries/tms320f28379d/common/source/usb_hal.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/common/source/usb_hal.c
rename to bsp/c28x/libraries/tms320f28379d/common/source/usb_hal.c
diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd b/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd
rename to bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd
diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd b/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd
rename to bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd
diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd b/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd
rename to bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd
diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd b/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd
rename to bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_adc.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_adc.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_analogsubsys.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_analogsubsys.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_can.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_can.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_cla.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_cla.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_cmpss.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_cmpss.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_cputimer.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_cputimer.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_dac.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_dac.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_dcsm.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_dcsm.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_device.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_device.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_dma.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_dma.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_ecap.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_ecap.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_emif.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_emif.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm_xbar.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm_xbar.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_eqep.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_eqep.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_flash.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_flash.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_gpio.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_gpio.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_i2c.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_i2c.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_input_xbar.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_input_xbar.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_ipc.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_ipc.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_mcbsp.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_mcbsp.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_memconfig.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_memconfig.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_nmiintrupt.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_nmiintrupt.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_output_xbar.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_output_xbar.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_piectrl.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_piectrl.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_pievect.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_pievect.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_sci.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_sci.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_sdfm.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_sdfm.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_spi.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_spi.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_sysctrl.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_sysctrl.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_upp.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_upp.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_xbar.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_xbar.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h
diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_xint.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/include/F2837xD_xint.h
rename to bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h
diff --git a/bsp/tms320f28379d/libraries/headers/source/F2837xD_GlobalVariableDefs.c b/bsp/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c
similarity index 100%
rename from bsp/tms320f28379d/libraries/headers/source/F2837xD_GlobalVariableDefs.c
rename to bsp/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c
diff --git a/bsp/tms320f28379d/.ccsproject b/bsp/c28x/tms320f28379d/.ccsproject
similarity index 95%
rename from bsp/tms320f28379d/.ccsproject
rename to bsp/c28x/tms320f28379d/.ccsproject
index e3dbeec008..028ef9f5ea 100644
--- a/bsp/tms320f28379d/.ccsproject
+++ b/bsp/c28x/tms320f28379d/.ccsproject
@@ -13,5 +13,5 @@
 	<createSlaveProjects value=""/>
 	<templateProperties value="id=com.ti.common.project.core.emptyProjectWithMainTemplate"/>
 	<filesToOpen value="main.c"/>
-	<isTargetManual value="false"/>
+	<isTargetManual value="true"/>
 </projectOptions>
diff --git a/bsp/tms320f28379d/.config b/bsp/c28x/tms320f28379d/.config
similarity index 97%
rename from bsp/tms320f28379d/.config
rename to bsp/c28x/tms320f28379d/.config
index adeabca77e..15627f816e 100644
--- a/bsp/tms320f28379d/.config
+++ b/bsp/c28x/tms320f28379d/.config
@@ -79,7 +79,7 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="scia"
-CONFIG_RT_VER_NUM=0x40101
+CONFIG_RT_VER_NUM=0x50000
 # CONFIG_RT_USING_CPU_FFS is not set
 CONFIG_ARCH_TIDSP=y
 CONFIG_ARCH_TIDSP_C28X=y
@@ -129,7 +129,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-# CONFIG_RT_USING_PWM is not set
+CONFIG_RT_USING_PWM=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
@@ -655,3 +655,30 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_MFBD is not set
 # CONFIG_PKG_USING_SLCAN2RTT is not set
 # CONFIG_PKG_USING_SOEM is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+# CONFIG_BSP_USING_XINT is not set
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_USBD is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/c28x/tms320f28379d/.cproject b/bsp/c28x/tms320f28379d/.cproject
new file mode 100644
index 0000000000..36f16276d4
--- /dev/null
+++ b/bsp/c28x/tms320f28379d/.cproject
@@ -0,0 +1,224 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1821767246.778586462">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1821767246.778586462" moduleId="org.eclipse.cdt.core.settings" name="FLASH">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1821767246.778586462" name="FLASH" parent="com.ti.ccstudio.buildDefinitions.C2000.Debug">
+					<folderInfo id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1821767246.778586462." name="/" resourcePath="">
+						<toolChain id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.DebugToolchain.1828213264" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.linkerDebug.1060489674">
+							<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1747799616" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+								<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=TMS320C28XX.TMS320F28379D"/>
+								<listOptionValue builtIn="false" value="DEVICE_CORE_ID="/>
+								<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+								<listOptionValue builtIn="false" value="OUTPUT_FORMAT=COFF"/>
+								<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE=2837x_RAM_lnk_cpu1.cmd"/>
+								<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+								<listOptionValue builtIn="false" value="CCS_MBS_VERSION=6.1.3"/>
+								<listOptionValue builtIn="false" value="PRODUCTS="/>
+								<listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={}"/>
+								<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
+							</option>
+							<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1244962932" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="20.2.5.LTS" valueType="string"/>
+							<targetPlatform id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.targetPlatformDebug.1821011613" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.targetPlatformDebug"/>
+							<builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.builderDebug.1609190757" keepEnvironmentInBuildfile="false" name="GNU Make" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.builderDebug"/>
+							<tool id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.compilerDebug.412070056" name="C2000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.compilerDebug">
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.LARGE_MEMORY_MODEL.999128620" name="Option deprecated, set by default (--large_memory_model, -ml)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.LARGE_MEMORY_MODEL" value="true" valueType="boolean"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.UNIFIED_MEMORY.1331338857" name="Unified memory (--unified_memory, -mt)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.UNIFIED_MEMORY" value="true" valueType="boolean"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.SILICON_VERSION.225185951" name="Processor version (--silicon_version, -v)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.SILICON_VERSION.28" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.FLOAT_SUPPORT.1493589098" name="Specify floating point support (--float_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.FLOAT_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.FLOAT_SUPPORT.softlib" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.CLA_SUPPORT.1026250140" name="Specify CLA support (--cla_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.CLA_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.CLA_SUPPORT.cla1" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.VCU_SUPPORT.683442163" name="Specify VCU support (--vcu_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.VCU_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.VCU_SUPPORT.vcu2" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.TMU_SUPPORT.1763042063" name="Specify TMU support (--tmu_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.TMU_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.TMU_SUPPORT.tmu0" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.INCLUDE_PATH.156684069" name="Add dir to #include search path (--include_path, -I)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.INCLUDE_PATH" valueType="includePath">
+									<listOptionValue builtIn="false" value="${PROJECT_ROOT}"/>
+									<listOptionValue builtIn="false" value="${PROJECT_LOC}/../../../components/finsh"/>
+									<listOptionValue builtIn="false" value="${PROJECT_LOC}/../../../components/drivers/include"/>
+									<listOptionValue builtIn="false" value="${PROJECT_LOC}/../libraries/tms320f28379d/headers/include"/>
+									<listOptionValue builtIn="false" value="${PROJECT_LOC}/../libraries/tms320f28379d/common/include"/>
+									<listOptionValue builtIn="false" value="${PROJECT_LOC}/../../../include"/>
+									<listOptionValue builtIn="false" value="${PROJECT_LOC}/../libraries/HAL_Drivers"/>
+									<listOptionValue builtIn="false" value="${PROJECT_LOC}/../../../src"/>
+									<listOptionValue builtIn="false" value="${PROJECT_LOC}/board"/>
+									<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ADVICE__PERFORMANCE.859143042" name="Provide advice on optimization techniques (--advice:performance)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ADVICE__PERFORMANCE" value="--advice:performance=all" valueType="string"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEFINE.843921936" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEFINE" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="CPU1"/>
+									<listOptionValue builtIn="false" value="_FLASH"/>
+									<listOptionValue builtIn="false" value="_LAUNCHXL_F28379D"/>
+									<listOptionValue builtIn="false" value="RT_USING_LIBC"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEBUGGING_MODEL.2015418143" name="Debugging model" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEBUGGING_MODEL" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEBUGGING_MODEL.SYMDEBUG__DWARF" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DIAG_WARNING.79420422" name="Treat diagnostic &lt;id&gt; as warning (--diag_warning, -pdsw)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DIAG_WARNING" valueType="stringList">
+									<listOptionValue builtIn="false" value="225"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DIAG_WRAP.228020105" name="Wrap diagnostic messages (--diag_wrap)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DIAG_WRAP" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DIAG_WRAP.off" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DISPLAY_ERROR_NUMBER.1214520629" name="Emit diagnostic identifier numbers (--display_error_number, -pden)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ABI.1089628126" name="Application binary interface [See 'General' page to edit] (--abi)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ABI" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ABI.coffabi" valueType="enumerated"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__C_SRCS.1318794569" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__C_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__CPP_SRCS.909041686" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__CPP_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__ASM_SRCS.260944938" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__ASM_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__ASM2_SRCS.157539313" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__ASM2_SRCS"/>
+							</tool>
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diff --git a/bsp/c28x/tms320f28379d/.gitignore b/bsp/c28x/tms320f28379d/.gitignore
new file mode 100644
index 0000000000..025af2b856
--- /dev/null
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diff --git a/bsp/c28x/tms320f28379d/.project b/bsp/c28x/tms320f28379d/.project
new file mode 100644
index 0000000000..fe05f8c849
--- /dev/null
+++ b/bsp/c28x/tms320f28379d/.project
@@ -0,0 +1,869 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>rt-thread</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+			</arguments>
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+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
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+	</buildSpec>
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+		<nature>org.eclipse.cdt.core.ccnature</nature>
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+		</link>
+		<link>
+			<name>libraries/tms320f28379d/headers/include/F2837xD_upp.h</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_upp.h</locationURI>
+		</link>
+		<link>
+			<name>libraries/tms320f28379d/headers/include/F2837xD_xbar.h</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_xbar.h</locationURI>
+		</link>
+		<link>
+			<name>libraries/tms320f28379d/headers/include/F2837xD_xint.h</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_xint.h</locationURI>
+		</link>
+		<link>
+			<name>libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/bsp/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs b/bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs
similarity index 100%
rename from bsp/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs
rename to bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs
diff --git a/bsp/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs b/bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs
similarity index 100%
rename from bsp/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs
rename to bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs
diff --git a/bsp/tms320f28379d/.settings/org.eclipse.core.resources.prefs b/bsp/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs
similarity index 55%
rename from bsp/tms320f28379d/.settings/org.eclipse.core.resources.prefs
rename to bsp/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs
index 9436acf25a..814522b6df 100644
--- a/bsp/tms320f28379d/.settings/org.eclipse.core.resources.prefs
+++ b/bsp/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs
@@ -1,29 +1,12 @@
 eclipse.preferences.version=1
-encoding//Debug/DeviceDrivers/ipc/subdir_rules.mk=UTF-8
-encoding//Debug/DeviceDrivers/ipc/subdir_vars.mk=UTF-8
-encoding//Debug/DeviceDrivers/subdir_rules.mk=UTF-8
-encoding//Debug/DeviceDrivers/subdir_vars.mk=UTF-8
-encoding//Debug/Kernel/subdir_rules.mk=UTF-8
-encoding//Debug/Kernel/subdir_vars.mk=UTF-8
-encoding//Debug/applications/subdir_rules.mk=UTF-8
-encoding//Debug/applications/subdir_vars.mk=UTF-8
-encoding//Debug/c28x/subdir_rules.mk=UTF-8
-encoding//Debug/c28x/subdir_vars.mk=UTF-8
 encoding//Debug/drivers/subdir_rules.mk=UTF-8
 encoding//Debug/drivers/subdir_vars.mk=UTF-8
-encoding//Debug/finsh/subdir_rules.mk=UTF-8
-encoding//Debug/finsh/subdir_vars.mk=UTF-8
 encoding//Debug/libraries/common/source/subdir_rules.mk=UTF-8
 encoding//Debug/libraries/common/source/subdir_vars.mk=UTF-8
 encoding//Debug/libraries/headers/cmd/subdir_rules.mk=UTF-8
 encoding//Debug/libraries/headers/cmd/subdir_vars.mk=UTF-8
 encoding//Debug/libraries/headers/source/subdir_rules.mk=UTF-8
 encoding//Debug/libraries/headers/source/subdir_vars.mk=UTF-8
-encoding//Debug/makefile=UTF-8
-encoding//Debug/objects.mk=UTF-8
-encoding//Debug/sources.mk=UTF-8
-encoding//Debug/subdir_rules.mk=UTF-8
-encoding//Debug/subdir_vars.mk=UTF-8
 encoding//FLASH/DeviceDrivers/ipc/subdir_rules.mk=UTF-8
 encoding//FLASH/DeviceDrivers/ipc/subdir_vars.mk=UTF-8
 encoding//FLASH/DeviceDrivers/subdir_rules.mk=UTF-8
@@ -32,18 +15,34 @@ encoding//FLASH/Kernel/subdir_rules.mk=UTF-8
 encoding//FLASH/Kernel/subdir_vars.mk=UTF-8
 encoding//FLASH/applications/subdir_rules.mk=UTF-8
 encoding//FLASH/applications/subdir_vars.mk=UTF-8
+encoding//FLASH/board/subdir_rules.mk=UTF-8
+encoding//FLASH/board/subdir_vars.mk=UTF-8
 encoding//FLASH/c28x/subdir_rules.mk=UTF-8
 encoding//FLASH/c28x/subdir_vars.mk=UTF-8
 encoding//FLASH/drivers/subdir_rules.mk=UTF-8
 encoding//FLASH/drivers/subdir_vars.mk=UTF-8
 encoding//FLASH/finsh/subdir_rules.mk=UTF-8
 encoding//FLASH/finsh/subdir_vars.mk=UTF-8
+encoding//FLASH/libraries/HAL_Drivers/subdir_rules.mk=UTF-8
+encoding//FLASH/libraries/HAL_Drivers/subdir_vars.mk=UTF-8
 encoding//FLASH/libraries/common/source/subdir_rules.mk=UTF-8
 encoding//FLASH/libraries/common/source/subdir_vars.mk=UTF-8
 encoding//FLASH/libraries/headers/cmd/subdir_rules.mk=UTF-8
 encoding//FLASH/libraries/headers/cmd/subdir_vars.mk=UTF-8
 encoding//FLASH/libraries/headers/source/subdir_rules.mk=UTF-8
 encoding//FLASH/libraries/headers/source/subdir_vars.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/common/cmd/subdir_rules.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/common/cmd/subdir_vars.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/common/deprecated/driverlib/subdir_rules.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/common/deprecated/driverlib/subdir_vars.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/common/deprecated/utils/subdir_rules.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/common/deprecated/utils/subdir_vars.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/common/source/subdir_rules.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/common/source/subdir_vars.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/headers/cmd/subdir_rules.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/headers/cmd/subdir_vars.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/headers/source/subdir_rules.mk=UTF-8
+encoding//FLASH/libraries/tms320f28379d/headers/source/subdir_vars.mk=UTF-8
 encoding//FLASH/makefile=UTF-8
 encoding//FLASH/objects.mk=UTF-8
 encoding//FLASH/sources.mk=UTF-8
@@ -57,18 +56,34 @@ encoding//RAM/Kernel/subdir_rules.mk=UTF-8
 encoding//RAM/Kernel/subdir_vars.mk=UTF-8
 encoding//RAM/applications/subdir_rules.mk=UTF-8
 encoding//RAM/applications/subdir_vars.mk=UTF-8
+encoding//RAM/board/subdir_rules.mk=UTF-8
+encoding//RAM/board/subdir_vars.mk=UTF-8
 encoding//RAM/c28x/subdir_rules.mk=UTF-8
 encoding//RAM/c28x/subdir_vars.mk=UTF-8
 encoding//RAM/drivers/subdir_rules.mk=UTF-8
 encoding//RAM/drivers/subdir_vars.mk=UTF-8
 encoding//RAM/finsh/subdir_rules.mk=UTF-8
 encoding//RAM/finsh/subdir_vars.mk=UTF-8
+encoding//RAM/libraries/HAL_Drivers/subdir_rules.mk=UTF-8
+encoding//RAM/libraries/HAL_Drivers/subdir_vars.mk=UTF-8
 encoding//RAM/libraries/common/source/subdir_rules.mk=UTF-8
 encoding//RAM/libraries/common/source/subdir_vars.mk=UTF-8
 encoding//RAM/libraries/headers/cmd/subdir_rules.mk=UTF-8
 encoding//RAM/libraries/headers/cmd/subdir_vars.mk=UTF-8
 encoding//RAM/libraries/headers/source/subdir_rules.mk=UTF-8
 encoding//RAM/libraries/headers/source/subdir_vars.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/common/cmd/subdir_rules.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/common/cmd/subdir_vars.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/common/deprecated/driverlib/subdir_rules.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/common/deprecated/driverlib/subdir_vars.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/common/deprecated/utils/subdir_rules.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/common/deprecated/utils/subdir_vars.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/common/source/subdir_rules.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/common/source/subdir_vars.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/headers/cmd/subdir_rules.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/headers/cmd/subdir_vars.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/headers/source/subdir_rules.mk=UTF-8
+encoding//RAM/libraries/tms320f28379d/headers/source/subdir_vars.mk=UTF-8
 encoding//RAM/makefile=UTF-8
 encoding//RAM/objects.mk=UTF-8
 encoding//RAM/sources.mk=UTF-8
diff --git a/bsp/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd b/bsp/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd
similarity index 100%
rename from bsp/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd
rename to bsp/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd
diff --git a/bsp/tms320f28379d/2837x_RAM_lnk_cpu1.cmd b/bsp/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd
similarity index 100%
rename from bsp/tms320f28379d/2837x_RAM_lnk_cpu1.cmd
rename to bsp/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd
diff --git a/bsp/tms320f28379d/Kconfig b/bsp/c28x/tms320f28379d/Kconfig
similarity index 92%
rename from bsp/tms320f28379d/Kconfig
rename to bsp/c28x/tms320f28379d/Kconfig
index 6e4c810c5f..e832d7eb6d 100644
--- a/bsp/tms320f28379d/Kconfig
+++ b/bsp/c28x/tms320f28379d/Kconfig
@@ -8,7 +8,7 @@ config BSP_DIR
 config RTT_DIR
     string
     option env="RTT_ROOT"
-    default "../.."
+    default "../../.."
     
 # you can change the RTT_ROOT default "../.." to your rtthread_root,
 # example : default "F:/git_repositories/rt-thread"
@@ -27,3 +27,4 @@ config SOC_TMS320F28X
 
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/tms320f28379d/README.md b/bsp/c28x/tms320f28379d/README.md
similarity index 100%
rename from bsp/tms320f28379d/README.md
rename to bsp/c28x/tms320f28379d/README.md
diff --git a/bsp/tms320f28379d/applications/startup.c b/bsp/c28x/tms320f28379d/applications/startup.c
similarity index 100%
rename from bsp/tms320f28379d/applications/startup.c
rename to bsp/c28x/tms320f28379d/applications/startup.c
diff --git a/bsp/c28x/tms320f28379d/board/Kconfig b/bsp/c28x/tms320f28379d/board/Kconfig
new file mode 100644
index 0000000000..740e3073ea
--- /dev/null
+++ b/bsp/c28x/tms320f28379d/board/Kconfig
@@ -0,0 +1,1045 @@
+menu "Hardware Drivers Config"
+
+menu "Onboard Peripheral Drivers"
+endmenu
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+    menuconfig BSP_USING_XINT
+        bool "Enable external interrupt"
+        default n
+        if BSP_USING_XINT
+            menuconfig BSP_USING_XINT1
+                bool "Enable XINT1"
+                if BSP_USING_XINT1
+                    config BSP_XINT1_PIN
+                        int "Interrupt pin"
+                        range 0 168
+                        default 0
+                endif
+                if !BSP_USING_XINT1
+                    config BSP_XINT1_PIN
+                        int
+                        default -1
+                endif
+            menuconfig BSP_USING_XINT2
+                bool "Enable XINT2"
+                if BSP_USING_XINT2
+                    config BSP_XINT2_PIN
+                        int "Interrupt pin"
+                        range 0 168
+                        default 0
+                endif
+                if !BSP_USING_XINT2
+                    config BSP_XINT2_PIN
+                        int
+                        default -1
+                endif
+            menuconfig BSP_USING_XINT3
+                bool "Enable XINT3"
+                if BSP_USING_XINT3
+                    config BSP_XINT3_PIN
+                        int "Interrupt pin"
+                        range 0 168
+                        default 0
+                endif
+                if !BSP_USING_XINT3
+                    config BSP_XINT3_PIN
+                        int
+                        default -1
+                endif
+            menuconfig BSP_USING_XINT4
+                bool "Enable XINT4"
+                if BSP_USING_XINT4
+                    config BSP_XINT4_PIN
+                        int "Interrupt pin"
+                        range 0 168
+                        default 0
+                endif
+                if !BSP_USING_XINT4
+                    config BSP_XINT4_PIN
+                        int
+                        default -1
+                endif
+                if !BSP_USING_XINT5
+                    config BSP_XINT5_PIN
+                        int
+                        default -1
+                endif
+            menuconfig BSP_USING_XINT5
+                bool "Enable XINT5"
+                if BSP_USING_XINT5
+                    config BSP_XINT5_PIN
+                        int "Interrupt pin"
+                        range 0 168
+                        default 0
+                endif
+        endif
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default y
+        endif
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        default n
+        select RT_USING_PWM
+
+        if BSP_USING_PWM
+            menuconfig BSP_USING_PWM1
+                bool "Enable ePWM1"
+                default n
+                if BSP_USING_PWM1
+                    menu "Basic settings for PWM1"
+                        config BSP_PWM1_INIT_PERIOD
+                            int "Initial period for PWM1(ns)"
+                            default 10000
+                        config BSP_PWM1_INIT_PULSE
+                            int "Initial pulse for PWM1(ns)"
+                            default 1000
+                    endmenu
+                    menu "Advanced Settings for PWM1"
+                        menuconfig BSP_PWM1_PHASE_ENABLE
+                            bool "Enable phase"
+                            default n
+                            if BSP_PWM1_PHASE_ENABLE
+                                choice
+                                    prompt "Select master or slave"
+                                    default BSP_PWM1_MASTER
+                                    config BSP_PWM1_MASTER
+                                        bool "Master"
+                                    config BSP_PWM1_SLAVE
+                                        bool "Slave"
+                                endchoice
+                                if BSP_PWM1_MASTER
+                                    config BSP_PWM1_PHASE
+                                        int
+                                        default 0
+                                endif
+                                if BSP_PWM1_SLAVE
+                                    config BSP_PWM1_PHASE
+                                        int "Phase, 0~360"
+                                        range 0 360
+                                        default 0
+                                        help
+                                            the phase for PWM1 module
+                                endif
+                            endif
+                        
+                        menuconfig BSP_PWM1_IT_ENABLE
+                            bool "Enable interrupt service"
+                            default n
+                            if BSP_PWM1_IT_ENABLE
+                                choice
+                                    prompt "Select interrupt time"
+                                    default BSP_PWM1_INTSEL_ET_CTR_ZERO
+                                    config BSP_PWM1_INTSEL_ET_DCAEVT1SOC
+                                        bool "DCAEVT1SOC"
+                                    config BSP_PWM1_INTSEL_ET_CTR_ZERO
+                                        bool "ctr == zero"
+                                    config BSP_PWM1_INTSEL_ET_CTR_PRD
+                                        bool "ctr == prd"
+                                    config BSP_PWM1_INTSEL_ET_CTR_PRDZERO
+                                        bool "ctr == prd or ctr == zero"
+                                    config BSP_PWM1_INTSEL_ET_CTRU_CMPA
+                                        bool "ctr == compa when counting up"
+                                    config BSP_PWM1_INTSEL_ET_CTRD_CMPA
+                                        bool "ctr == compa when counting down"
+                                    config BSP_PWM1_INTSEL_ET_CTRU_CMPB
+                                        bool "ctr == compb when counting up"
+                                    config BSP_PWM1_INTSEL_ET_CTRD_CMPB
+                                        bool "ctr == compb when counting down"
+                                endchoice
+
+                                config BSP_PWM1_INTSEL
+                                    int
+                                    default 0 if BSP_PWM1_INTSEL_ET_DCAEVT1SOC
+                                    default 1 if BSP_PWM1_INTSEL_ET_CTR_ZERO
+                                    default 2 if BSP_PWM1_INTSEL_ET_CTR_PRD
+                                    default 3 if BSP_PWM1_INTSEL_ET_CTR_PRDZERO
+                                    default 4 if BSP_PWM1_INTSEL_ET_CTRU_CMPA
+                                    default 5 if BSP_PWM1_INTSEL_ET_CTRD_CMPA
+                                    default 6 if BSP_PWM1_INTSEL_ET_CTRU_CMPB
+                                    default 7 if BSP_PWM1_INTSEL_ET_CTRD_CMPB
+                                choice
+                                    prompt "Interrupt generation time"
+                                    default BSP_PWM1_INT_ET_1ST
+                                    config BSP_PWM1_INT_ET_DISABLE
+                                        bool "disable PWM interrupt"
+                                    config BSP_PWM1_INT_ET_1ST
+                                        bool "generate interrupt at the first time"
+                                    config BSP_PWM1_INT_ET_2ND
+                                        bool "generate interrupt at the second time"
+                                    config BSP_PWM1_INT_ET_3RD
+                                        bool "generate interrupt at the third time"
+                                endchoice
+                                config BSP_PWM1_INTPRD
+                                    int 
+                                    default 0 if BSP_PWM1_INT_ET_DISABLE
+                                    default 1 if BSP_PWM1_INT_ET_1ST
+                                    default 2 if BSP_PWM1_INT_ET_2ND
+                                    default 3 if BSP_PWM1_INT_ET_3RD
+                            endif
+                        choice 
+                            prompt "HSP Clock division"
+                            default BSP_PWM1_HSPCLKDIV1
+                            config BSP_PWM1_HSPCLKDIV1
+                                bool "Clock Divided by 1"
+                            config BSP_PWM1_HSPCLKDIV2
+                                bool "Clock Divided by 2"
+                            config BSP_PWM1_HSPCLKDIV4
+                                bool "Clock Divided by 4"
+                        endchoice
+                        config BSP_PWM1_HSPCLKDIV
+                            int 
+                            default 0 if BSP_PWM1_HSPCLKDIV1
+                            default 1 if BSP_PWM1_HSPCLKDIV2
+                            default 2 if BSP_PWM1_HSPCLKDIV4
+                        choice 
+                            prompt "Clock division"
+                            default BSP_PWM1_CLKDIV1
+                            config BSP_PWM1_CLKDIV1
+                                bool "Clock Divided by 1"
+                            config BSP_PWM1_CLKDIV2
+                                bool "Clock Divided by 2"
+                            config BSP_PWM1_CLKDIV4
+                                bool "Clock Divided by 4"
+                        endchoice
+                        config BSP_PWM1_CLKDIV
+                            int 
+                            default 0 if BSP_PWM1_CLKDIV1
+                            default 1 if BSP_PWM1_CLKDIV2
+                            default 2 if BSP_PWM1_CLKDIV4
+                        choice 
+                            default BSP_PWM1_CTR_MODE_UPDOWN
+                            prompt "Select counter mode"
+                            config BSP_PWM1_CTR_MODE_UPDOWN
+                                bool "Up-down mode"
+                            config BSP_PWM1_CTR_MODE_UP
+                                bool "Up mode"
+                            config BSP_PWM1_CTR_MODE_DOWN
+                                bool "Down mode"
+                            config BSP_PWM1_CTR_FREEZE
+                                bool "Freezing Counter"
+                        endchoice
+                        config BSP_PWM1_CTRMODE
+                            int
+                            default 0 if BSP_PWM1_CTR_MODE_UP
+                            default 1 if BSP_PWM1_CTR_MODE_DOWN
+                            default 2 if BSP_PWM1_CTR_MODE_UPDOWN
+                            default 3 if BSP_PWM1_CTR_FREEZE
+                        choice
+                            prompt "Register load mode"
+                            config BSP_PWM1_CC_CTR_ZERO
+                                bool "Load when counter == 0"
+                            config BSP_PWM1_CC_CTR_PRD
+                                bool "Load when counter == prd"
+                            config BSP_PWM1_CC_CTR_ZERO_PRD
+                                bool "load when counter ==0 or counter == prd"
+                            config BSP_PWM1_CC_LD_DISABLE
+                                bool "disable load"
+                        endchoice
+
+                        config BSP_PWM1_LOADAMODE
+                            int 
+                            default 0 if BSP_PWM1_CC_CTR_ZERO
+                            default 1 if BSP_PWM1_CC_CTR_PRD
+                            default 2 if BSP_PWM1_CC_CTR_ZERO_PRD
+                            default 3 if BSP_PWM1_CC_LD_DISABLE
+
+                        config BSP_PWM1_DB
+                            int "Dead time(ns)"
+                            default 100
+                            range 0 100000
+                        menuconfig BSP_PWM1_ADC_TRIGGER
+                            bool "Enable ADC trigger from PWM1"
+                            if BSP_PWM1_ADC_TRIGGER
+                                choice
+                                    prompt "Select soc triggering time"
+                                    default BSP_PWM1_SOCASEL_ET_CTR_ZERO
+                                    config BSP_PWM1_SOCASEL_ET_DCAEVT1SOC
+                                        bool "DCAEVT1SOC"
+                                    config BSP_PWM1_SOCASEL_ET_CTR_ZERO
+                                        bool "ctr == zero"
+                                    config BSP_PWM1_SOCASEL_ET_CTR_PRD
+                                        bool "ctr == prd"
+                                    config BSP_PWM1_SOCASEL_ET_CTR_PRDZERO
+                                        bool "ctr == prd or ctr == zero"
+                                    config BSP_PWM1_SOCASEL_ET_CTRU_CMPA
+                                        bool "ctr == compa when counting up"
+                                    config BSP_PWM1_SOCASEL_ET_CTRD_CMPA
+                                        bool "ctr == compa when counting down"
+                                    config BSP_PWM1_SOCASEL_ET_CTRU_CMPB
+                                        bool "ctr == compb when counting up"
+                                    config BSP_PWM1_SOCASEL_ET_CTRD_CMPB
+                                        bool "ctr == compb when counting down"
+                                endchoice
+
+                                config BSP_PWM1_SOCASEL
+                                    int
+                                    default 0 if BSP_PWM1_SOCASEL_ET_DCAEVT1SOC
+                                    default 1 if BSP_PWM1_SOCASEL_ET_CTR_ZERO
+                                    default 2 if BSP_PWM1_SOCASEL_ET_CTR_PRD
+                                    default 3 if BSP_PWM1_SOCASEL_ET_CTR_PRDZERO
+                                    default 4 if BSP_PWM1_SOCASEL_ET_CTRU_CMPA
+                                    default 5 if BSP_PWM1_SOCASEL_ET_CTRD_CMPA
+                                    default 6 if BSP_PWM1_SOCASEL_ET_CTRU_CMPB
+                                    default 7 if BSP_PWM1_SOCASEL_ET_CTRD_CMPB
+                                choice
+                                    prompt "SOCA generation time"
+                                    default BSP_PWM1_SOCA_ET_1ST
+                                    config BSP_PWM1_SOCA_ET_DISABLE
+                                        bool "disable soc generation"
+                                    config BSP_PWM1_SOCA_ET_1ST
+                                        bool "generate soc at the first time"
+                                    config BSP_PWM1_SOCA_ET_2ND
+                                        bool "generate soc at the second time"
+                                    config BSP_PWM1_SOCA_ET_3RD
+                                        bool "generate soc at the third time"
+                                endchoice
+                                config BSP_PWM1_SOCAPRD
+                                    int 
+                                    default 0 if BSP_PWM1_SOCA_ET_DISABLE
+                                    default 1 if BSP_PWM1_SOCA_ET_1ST
+                                    default 2 if BSP_PWM1_SOCA_ET_2ND
+                                    default 3 if BSP_PWM1_SOCA_ET_3RD
+                            endif
+                    endmenu
+                endif
+            menuconfig BSP_USING_PWM2
+                bool "Enable ePWM2"
+                default n
+                if BSP_USING_PWM2
+                    menu "Basic settings for PWM2"
+                        config BSP_PWM2_INIT_PERIOD
+                            int "Initial period for PWM2(ns)"
+                            default 10000
+                        config BSP_PWM2_INIT_PULSE
+                            int "Initial pulse for PWM2(ns)"
+                            default 1000
+                    endmenu
+                    menu "Advanced Settings for PWM2"
+                        menuconfig BSP_PWM2_PHASE_ENABLE
+                            bool "Enable phase"
+                            default n
+                            if BSP_PWM2_PHASE_ENABLE
+                                choice
+                                    prompt "Select master or slave"
+                                    default BSP_PWM2_SLAVE
+                                    config BSP_PWM2_MASTER
+                                        bool "Master"
+                                    config BSP_PWM2_SLAVE
+                                        bool "Slave"
+                                endchoice
+                                if BSP_PWM2_MASTER
+                                    config BSP_PWM2_PHASE
+                                        int
+                                        default 0
+                                endif
+                                if BSP_PWM2_SLAVE
+                                    config BSP_PWM2_PHASE
+                                        int "Phase, 0~360"
+                                        range 0 360
+                                        default 0
+                                        help
+                                            the phase for PWM2 module
+                                endif
+                            endif
+                        
+                        menuconfig BSP_PWM2_IT_ENABLE
+                            bool "Enable interrupt service"
+                            default n
+                            if BSP_PWM2_IT_ENABLE
+                                choice
+                                    prompt "Select interrupt time"
+                                    default BSP_PWM2_INTSEL_ET_CTR_ZERO
+                                    config BSP_PWM2_INTSEL_ET_DCAEVT1SOC
+                                        bool "DCAEVT1SOC"
+                                    config BSP_PWM2_INTSEL_ET_CTR_ZERO
+                                        bool "ctr == zero"
+                                    config BSP_PWM2_INTSEL_ET_CTR_PRD
+                                        bool "ctr == prd"
+                                    config BSP_PWM2_INTSEL_ET_CTR_PRDZERO
+                                        bool "ctr == prd or ctr == zero"
+                                    config BSP_PWM2_INTSEL_ET_CTRU_CMPA
+                                        bool "ctr == compa when counting up"
+                                    config BSP_PWM2_INTSEL_ET_CTRD_CMPA
+                                        bool "ctr == compa when counting down"
+                                    config BSP_PWM2_INTSEL_ET_CTRU_CMPB
+                                        bool "ctr == compb when counting up"
+                                    config BSP_PWM2_INTSEL_ET_CTRD_CMPB
+                                        bool "ctr == compb when counting down"
+                                endchoice
+
+                                config BSP_PWM2_INTSEL
+                                    int
+                                    default 0 if BSP_PWM2_INTSEL_ET_DCAEVT1SOC
+                                    default 1 if BSP_PWM2_INTSEL_ET_CTR_ZERO
+                                    default 2 if BSP_PWM2_INTSEL_ET_CTR_PRD
+                                    default 3 if BSP_PWM2_INTSEL_ET_CTR_PRDZERO
+                                    default 4 if BSP_PWM2_INTSEL_ET_CTRU_CMPA
+                                    default 5 if BSP_PWM2_INTSEL_ET_CTRD_CMPA
+                                    default 6 if BSP_PWM2_INTSEL_ET_CTRU_CMPB
+                                    default 7 if BSP_PWM2_INTSEL_ET_CTRD_CMPB
+                                choice
+                                    prompt "Interrupt generation time"
+                                    default BSP_PWM2_INT_ET_1ST
+                                    config BSP_PWM2_INT_ET_DISABLE
+                                        bool "disable PWM interrupt"
+                                    config BSP_PWM2_INT_ET_1ST
+                                        bool "generate interrupt at the first time"
+                                    config BSP_PWM2_INT_ET_2ND
+                                        bool "generate interrupt at the second time"
+                                    config BSP_PWM2_INT_ET_3RD
+                                        bool "generate interrupt at the third time"
+                                endchoice
+                                config BSP_PWM2_INTPRD
+                                    int 
+                                    default 0 if BSP_PWM2_INT_ET_DISABLE
+                                    default 1 if BSP_PWM2_INT_ET_1ST
+                                    default 2 if BSP_PWM2_INT_ET_2ND
+                                    default 3 if BSP_PWM2_INT_ET_3RD
+                            endif
+                        choice 
+                            prompt "HSP Clock division"
+                            default BSP_PWM2_HSPCLKDIV1
+                            config BSP_PWM2_HSPCLKDIV1
+                                bool "Clock Divided by 1"
+                            config BSP_PWM2_HSPCLKDIV2
+                                bool "Clock Divided by 2"
+                            config BSP_PWM2_HSPCLKDIV4
+                                bool "Clock Divided by 4"
+                        endchoice
+                        config BSP_PWM2_HSPCLKDIV
+                            int 
+                            default 0 if BSP_PWM2_HSPCLKDIV1
+                            default 1 if BSP_PWM2_HSPCLKDIV2
+                            default 2 if BSP_PWM2_HSPCLKDIV4
+                        choice 
+                            prompt "Clock division"
+                            default BSP_PWM2_CLKDIV1
+                            config BSP_PWM2_CLKDIV1
+                                bool "Clock Divided by 1"
+                            config BSP_PWM2_CLKDIV2
+                                bool "Clock Divided by 2"
+                            config BSP_PWM2_CLKDIV4
+                                bool "Clock Divided by 4"
+                        endchoice
+                        config BSP_PWM2_CLKDIV
+                            int 
+                            default 0 if BSP_PWM2_CLKDIV1
+                            default 1 if BSP_PWM2_CLKDIV2
+                            default 2 if BSP_PWM2_CLKDIV4
+                        choice 
+                            default BSP_PWM2_CTR_MODE_UPDOWN
+                            prompt "Select counter mode"
+                            config BSP_PWM2_CTR_MODE_UPDOWN
+                                bool "Up-down mode"
+                            config BSP_PWM2_CTR_MODE_UP
+                                bool "Up mode"
+                            config BSP_PWM2_CTR_MODE_DOWN
+                                bool "Down mode"
+                            config BSP_PWM2_CTR_FREEZE
+                                bool "Freezing Counter"
+                        endchoice
+                        config BSP_PWM2_CTRMODE
+                            int
+                            default 0 if BSP_PWM2_CTR_MODE_UP
+                            default 1 if BSP_PWM2_CTR_MODE_DOWN
+                            default 2 if BSP_PWM2_CTR_MODE_UPDOWN
+                            default 3 if BSP_PWM2_CTR_FREEZE
+                        choice
+                            prompt "Register load mode"
+                            config BSP_PWM2_CC_CTR_ZERO
+                                bool "Load when counter == 0"
+                            config BSP_PWM2_CC_CTR_PRD
+                                bool "Load when counter == prd"
+                            config BSP_PWM2_CC_CTR_ZERO_PRD
+                                bool "load when counter ==0 or counter == prd"
+                            config BSP_PWM2_CC_LD_DISABLE
+                                bool "disable load"
+                        endchoice
+
+                        config BSP_PWM2_LOADAMODE
+                            int 
+                            default 0 if BSP_PWM2_CC_CTR_ZERO
+                            default 1 if BSP_PWM2_CC_CTR_PRD
+                            default 2 if BSP_PWM2_CC_CTR_ZERO_PRD
+                            default 3 if BSP_PWM2_CC_LD_DISABLE
+
+                        config BSP_PWM2_DB
+                            int "Dead time(ns)"
+                            default 100
+                            range 0 100000
+                        menuconfig BSP_PWM2_ADC_TRIGGER
+                            bool "Enable ADC trigger from PWM2"
+                            if BSP_PWM2_ADC_TRIGGER
+                                choice
+                                    prompt "Select soc triggering time"
+                                    default BSP_PWM2_SOCASEL_ET_CTR_ZERO
+                                    config BSP_PWM2_SOCASEL_ET_DCAEVT1SOC
+                                        bool "DCAEVT1SOC"
+                                    config BSP_PWM2_SOCASEL_ET_CTR_ZERO
+                                        bool "ctr == zero"
+                                    config BSP_PWM2_SOCASEL_ET_CTR_PRD
+                                        bool "ctr == prd"
+                                    config BSP_PWM2_SOCASEL_ET_CTR_PRDZERO
+                                        bool "ctr == prd or ctr == zero"
+                                    config BSP_PWM2_SOCASEL_ET_CTRU_CMPA
+                                        bool "ctr == compa when counting up"
+                                    config BSP_PWM2_SOCASEL_ET_CTRD_CMPA
+                                        bool "ctr == compa when counting down"
+                                    config BSP_PWM2_SOCASEL_ET_CTRU_CMPB
+                                        bool "ctr == compb when counting up"
+                                    config BSP_PWM2_SOCASEL_ET_CTRD_CMPB
+                                        bool "ctr == compb when counting down"
+                                endchoice
+
+                                config BSP_PWM2_SOCASEL
+                                    int
+                                    default 0 if BSP_PWM2_SOCASEL_ET_DCAEVT1SOC
+                                    default 1 if BSP_PWM2_SOCASEL_ET_CTR_ZERO
+                                    default 2 if BSP_PWM2_SOCASEL_ET_CTR_PRD
+                                    default 3 if BSP_PWM2_SOCASEL_ET_CTR_PRDZERO
+                                    default 4 if BSP_PWM2_SOCASEL_ET_CTRU_CMPA
+                                    default 5 if BSP_PWM2_SOCASEL_ET_CTRD_CMPA
+                                    default 6 if BSP_PWM2_SOCASEL_ET_CTRU_CMPB
+                                    default 7 if BSP_PWM2_SOCASEL_ET_CTRD_CMPB
+                                choice
+                                    prompt "SOCA generation time"
+                                    default BSP_PWM2_SOCA_ET_1ST
+                                    config BSP_PWM2_SOCA_ET_DISABLE
+                                        bool "disable soc generation"
+                                    config BSP_PWM2_SOCA_ET_1ST
+                                        bool "generate soc at the first time"
+                                    config BSP_PWM2_SOCA_ET_2ND
+                                        bool "generate soc at the second time"
+                                    config BSP_PWM2_SOCA_ET_3RD
+                                        bool "generate soc at the third time"
+                                endchoice
+                                config BSP_PWM2_SOCAPRD
+                                    int 
+                                    default 0 if BSP_PWM2_SOCA_ET_DISABLE
+                                    default 1 if BSP_PWM2_SOCA_ET_1ST
+                                    default 2 if BSP_PWM2_SOCA_ET_2ND
+                                    default 3 if BSP_PWM2_SOCA_ET_3RD
+                            endif
+                    endmenu
+                endif
+            menuconfig BSP_USING_PWM3
+                bool "Enable ePWM3"
+                default n
+                if BSP_USING_PWM3
+                    menu "Basic settings for PWM3"
+                        config BSP_PWM3_INIT_PERIOD
+                            int "Initial period for PWM3(ns)"
+                            default 10000
+                        config BSP_PWM3_INIT_PULSE
+                            int "Initial pulse for PWM3(ns)"
+                            default 1000
+                    endmenu
+                    menu "Advanced Settings for PWM3"
+                        menuconfig BSP_PWM3_PHASE_ENABLE
+                            bool "Enable phase"
+                            default n
+                            if BSP_PWM3_PHASE_ENABLE
+                                choice
+                                    prompt "Select master or slave"
+                                    default BSP_PWM3_SLAVE
+                                    config BSP_PWM3_MASTER
+                                        bool "Master"
+                                    config BSP_PWM3_SLAVE
+                                        bool "Slave"
+                                endchoice
+                                if BSP_PWM3_MASTER
+                                    config BSP_PWM3_PHASE
+                                        int
+                                        default 0
+                                endif
+                                if BSP_PWM3_SLAVE
+                                    config BSP_PWM3_PHASE
+                                        int "Phase, 0~360"
+                                        range 0 360
+                                        default 0
+                                        help
+                                            the phase for PWM3 module
+                                endif
+                            endif
+                        
+                        menuconfig BSP_PWM3_IT_ENABLE
+                            bool "Enable interrupt service"
+                            default n
+                            if BSP_PWM3_IT_ENABLE
+                                choice
+                                    prompt "Select interrupt time"
+                                    default BSP_PWM3_INTSEL_ET_CTR_ZERO
+                                    config BSP_PWM3_INTSEL_ET_DCAEVT1SOC
+                                        bool "DCAEVT1SOC"
+                                    config BSP_PWM3_INTSEL_ET_CTR_ZERO
+                                        bool "ctr == zero"
+                                    config BSP_PWM3_INTSEL_ET_CTR_PRD
+                                        bool "ctr == prd"
+                                    config BSP_PWM3_INTSEL_ET_CTR_PRDZERO
+                                        bool "ctr == prd or ctr == zero"
+                                    config BSP_PWM3_INTSEL_ET_CTRU_CMPA
+                                        bool "ctr == compa when counting up"
+                                    config BSP_PWM3_INTSEL_ET_CTRD_CMPA
+                                        bool "ctr == compa when counting down"
+                                    config BSP_PWM3_INTSEL_ET_CTRU_CMPB
+                                        bool "ctr == compb when counting up"
+                                    config BSP_PWM3_INTSEL_ET_CTRD_CMPB
+                                        bool "ctr == compb when counting down"
+                                endchoice
+
+                                config BSP_PWM3_INTSEL
+                                    int
+                                    default 0 if BSP_PWM3_INTSEL_ET_DCAEVT1SOC
+                                    default 1 if BSP_PWM3_INTSEL_ET_CTR_ZERO
+                                    default 2 if BSP_PWM3_INTSEL_ET_CTR_PRD
+                                    default 3 if BSP_PWM3_INTSEL_ET_CTR_PRDZERO
+                                    default 4 if BSP_PWM3_INTSEL_ET_CTRU_CMPA
+                                    default 5 if BSP_PWM3_INTSEL_ET_CTRD_CMPA
+                                    default 6 if BSP_PWM3_INTSEL_ET_CTRU_CMPB
+                                    default 7 if BSP_PWM3_INTSEL_ET_CTRD_CMPB
+                                choice
+                                    prompt "Interrupt generation time"
+                                    default BSP_PWM3_INT_ET_1ST
+                                    config BSP_PWM3_INT_ET_DISABLE
+                                        bool "disable PWM interrupt"
+                                    config BSP_PWM3_INT_ET_1ST
+                                        bool "generate interrupt at the first time"
+                                    config BSP_PWM3_INT_ET_2ND
+                                        bool "generate interrupt at the second time"
+                                    config BSP_PWM3_INT_ET_3RD
+                                        bool "generate interrupt at the third time"
+                                endchoice
+                                config BSP_PWM3_INTPRD
+                                    int 
+                                    default 0 if BSP_PWM3_INT_ET_DISABLE
+                                    default 1 if BSP_PWM3_INT_ET_1ST
+                                    default 2 if BSP_PWM3_INT_ET_2ND
+                                    default 3 if BSP_PWM3_INT_ET_3RD
+                            endif
+                        choice 
+                            prompt "HSP Clock division"
+                            default BSP_PWM3_HSPCLKDIV1
+                            config BSP_PWM3_HSPCLKDIV1
+                                bool "Clock Divided by 1"
+                            config BSP_PWM3_HSPCLKDIV2
+                                bool "Clock Divided by 2"
+                            config BSP_PWM3_HSPCLKDIV4
+                                bool "Clock Divided by 4"
+                        endchoice
+                        config BSP_PWM3_HSPCLKDIV
+                            int 
+                            default 0 if BSP_PWM3_HSPCLKDIV1
+                            default 1 if BSP_PWM3_HSPCLKDIV2
+                            default 2 if BSP_PWM3_HSPCLKDIV4
+                        choice 
+                            prompt "Clock division"
+                            default BSP_PWM3_CLKDIV1
+                            config BSP_PWM3_CLKDIV1
+                                bool "Clock Divided by 1"
+                            config BSP_PWM3_CLKDIV2
+                                bool "Clock Divided by 2"
+                            config BSP_PWM3_CLKDIV4
+                                bool "Clock Divided by 4"
+                        endchoice
+                        config BSP_PWM3_CLKDIV
+                            int 
+                            default 0 if BSP_PWM3_CLKDIV1
+                            default 1 if BSP_PWM3_CLKDIV2
+                            default 2 if BSP_PWM3_CLKDIV4
+                        choice 
+                            default BSP_PWM3_CTR_MODE_UPDOWN
+                            prompt "Select counter mode"
+                            config BSP_PWM3_CTR_MODE_UPDOWN
+                                bool "Up-down mode"
+                            config BSP_PWM3_CTR_MODE_UP
+                                bool "Up mode"
+                            config BSP_PWM3_CTR_MODE_DOWN
+                                bool "Down mode"
+                            config BSP_PWM3_CTR_FREEZE
+                                bool "Freezing Counter"
+                        endchoice
+                        config BSP_PWM3_CTRMODE
+                            int
+                            default 0 if BSP_PWM3_CTR_MODE_UP
+                            default 1 if BSP_PWM3_CTR_MODE_DOWN
+                            default 2 if BSP_PWM3_CTR_MODE_UPDOWN
+                            default 3 if BSP_PWM3_CTR_FREEZE
+                        choice
+                            prompt "Register load mode"
+                            config BSP_PWM3_CC_CTR_ZERO
+                                bool "Load when counter == 0"
+                            config BSP_PWM3_CC_CTR_PRD
+                                bool "Load when counter == prd"
+                            config BSP_PWM3_CC_CTR_ZERO_PRD
+                                bool "load when counter ==0 or counter == prd"
+                            config BSP_PWM3_CC_LD_DISABLE
+                                bool "disable load"
+                        endchoice
+
+                        config BSP_PWM3_LOADAMODE
+                            int 
+                            default 0 if BSP_PWM3_CC_CTR_ZERO
+                            default 1 if BSP_PWM3_CC_CTR_PRD
+                            default 2 if BSP_PWM3_CC_CTR_ZERO_PRD
+                            default 3 if BSP_PWM3_CC_LD_DISABLE
+
+                        config BSP_PWM3_DB
+                            int "Dead time(ns)"
+                            default 100
+                            range 0 100000
+                        menuconfig BSP_PWM3_ADC_TRIGGER
+                            bool "Enable ADC trigger from PWM3"
+                            if BSP_PWM3_ADC_TRIGGER
+                                choice
+                                    prompt "Select soc triggering time"
+                                    default BSP_PWM3_SOCASEL_ET_CTR_ZERO
+                                    config BSP_PWM3_SOCASEL_ET_DCAEVT1SOC
+                                        bool "DCAEVT1SOC"
+                                    config BSP_PWM3_SOCASEL_ET_CTR_ZERO
+                                        bool "ctr == zero"
+                                    config BSP_PWM3_SOCASEL_ET_CTR_PRD
+                                        bool "ctr == prd"
+                                    config BSP_PWM3_SOCASEL_ET_CTR_PRDZERO
+                                        bool "ctr == prd or ctr == zero"
+                                    config BSP_PWM3_SOCASEL_ET_CTRU_CMPA
+                                        bool "ctr == compa when counting up"
+                                    config BSP_PWM3_SOCASEL_ET_CTRD_CMPA
+                                        bool "ctr == compa when counting down"
+                                    config BSP_PWM3_SOCASEL_ET_CTRU_CMPB
+                                        bool "ctr == compb when counting up"
+                                    config BSP_PWM3_SOCASEL_ET_CTRD_CMPB
+                                        bool "ctr == compb when counting down"
+                                endchoice
+
+                                config BSP_PWM3_SOCASEL
+                                    int
+                                    default 0 if BSP_PWM3_SOCASEL_ET_DCAEVT1SOC
+                                    default 1 if BSP_PWM3_SOCASEL_ET_CTR_ZERO
+                                    default 2 if BSP_PWM3_SOCASEL_ET_CTR_PRD
+                                    default 3 if BSP_PWM3_SOCASEL_ET_CTR_PRDZERO
+                                    default 4 if BSP_PWM3_SOCASEL_ET_CTRU_CMPA
+                                    default 5 if BSP_PWM3_SOCASEL_ET_CTRD_CMPA
+                                    default 6 if BSP_PWM3_SOCASEL_ET_CTRU_CMPB
+                                    default 7 if BSP_PWM3_SOCASEL_ET_CTRD_CMPB
+                                choice
+                                    prompt "SOCA generation time"
+                                    default BSP_PWM3_SOCA_ET_1ST
+                                    config BSP_PWM3_SOCA_ET_DISABLE
+                                        bool "disable soc generation"
+                                    config BSP_PWM3_SOCA_ET_1ST
+                                        bool "generate soc at the first time"
+                                    config BSP_PWM3_SOCA_ET_2ND
+                                        bool "generate soc at the second time"
+                                    config BSP_PWM3_SOCA_ET_3RD
+                                        bool "generate soc at the third time"
+                                endchoice
+                                config BSP_PWM3_SOCAPRD
+                                    int 
+                                    default 0 if BSP_PWM3_SOCA_ET_DISABLE
+                                    default 1 if BSP_PWM3_SOCA_ET_1ST
+                                    default 2 if BSP_PWM3_SOCA_ET_2ND
+                                    default 3 if BSP_PWM3_SOCA_ET_3RD
+                            endif
+                    endmenu
+                endif
+            menuconfig BSP_USING_PWM4
+                bool "Enable ePWM4"
+                default n
+                if BSP_USING_PWM4
+                    menu "Basic settings for PWM4"
+                        config BSP_PWM4_INIT_PERIOD
+                            int "Initial period for PWM4(ns)"
+                            default 10000
+                        config BSP_PWM4_INIT_PULSE
+                            int "Initial pulse for PWM4(ns)"
+                            default 1000
+                    endmenu
+                    menu "Advanced Settings for PWM4"
+                        menuconfig BSP_PWM4_PHASE_ENABLE
+                            bool "Enable phase"
+                            default n
+                            if BSP_PWM4_PHASE_ENABLE
+                                choice
+                                    prompt "Select master or slave"
+                                    default BSP_PWM4_SLAVE
+                                    config BSP_PWM4_MASTER
+                                        bool "Master"
+                                    config BSP_PWM4_SLAVE
+                                        bool "Slave"
+                                endchoice
+                                if BSP_PWM4_MASTER
+                                    config BSP_PWM4_PHASE
+                                        int
+                                        default 0
+                                endif
+                                if BSP_PWM4_SLAVE
+                                    config BSP_PWM4_PHASE
+                                        int "Phase, 0~360"
+                                        range 0 360
+                                        default 0
+                                        help
+                                            the phase for PWM4 module
+                                endif
+                            endif
+                        
+                        menuconfig BSP_PWM4_IT_ENABLE
+                            bool "Enable interrupt service"
+                            default n
+                            if BSP_PWM4_IT_ENABLE
+                                choice
+                                    prompt "Select interrupt time"
+                                    default BSP_PWM4_INTSEL_ET_CTR_ZERO
+                                    config BSP_PWM4_INTSEL_ET_DCAEVT1SOC
+                                        bool "DCAEVT1SOC"
+                                    config BSP_PWM4_INTSEL_ET_CTR_ZERO
+                                        bool "ctr == zero"
+                                    config BSP_PWM4_INTSEL_ET_CTR_PRD
+                                        bool "ctr == prd"
+                                    config BSP_PWM4_INTSEL_ET_CTR_PRDZERO
+                                        bool "ctr == prd or ctr == zero"
+                                    config BSP_PWM4_INTSEL_ET_CTRU_CMPA
+                                        bool "ctr == compa when counting up"
+                                    config BSP_PWM4_INTSEL_ET_CTRD_CMPA
+                                        bool "ctr == compa when counting down"
+                                    config BSP_PWM4_INTSEL_ET_CTRU_CMPB
+                                        bool "ctr == compb when counting up"
+                                    config BSP_PWM4_INTSEL_ET_CTRD_CMPB
+                                        bool "ctr == compb when counting down"
+                                endchoice
+
+                                config BSP_PWM4_INTSEL
+                                    int
+                                    default 0 if BSP_PWM4_INTSEL_ET_DCAEVT1SOC
+                                    default 1 if BSP_PWM4_INTSEL_ET_CTR_ZERO
+                                    default 2 if BSP_PWM4_INTSEL_ET_CTR_PRD
+                                    default 3 if BSP_PWM4_INTSEL_ET_CTR_PRDZERO
+                                    default 4 if BSP_PWM4_INTSEL_ET_CTRU_CMPA
+                                    default 5 if BSP_PWM4_INTSEL_ET_CTRD_CMPA
+                                    default 6 if BSP_PWM4_INTSEL_ET_CTRU_CMPB
+                                    default 7 if BSP_PWM4_INTSEL_ET_CTRD_CMPB
+                                choice
+                                    prompt "Interrupt generation time"
+                                    default BSP_PWM4_INT_ET_1ST
+                                    config BSP_PWM4_INT_ET_DISABLE
+                                        bool "disable PWM interrupt"
+                                    config BSP_PWM4_INT_ET_1ST
+                                        bool "generate interrupt at the first time"
+                                    config BSP_PWM4_INT_ET_2ND
+                                        bool "generate interrupt at the second time"
+                                    config BSP_PWM4_INT_ET_3RD
+                                        bool "generate interrupt at the third time"
+                                endchoice
+                                config BSP_PWM4_INTPRD
+                                    int 
+                                    default 0 if BSP_PWM4_INT_ET_DISABLE
+                                    default 1 if BSP_PWM4_INT_ET_1ST
+                                    default 2 if BSP_PWM4_INT_ET_2ND
+                                    default 3 if BSP_PWM4_INT_ET_3RD
+                            endif
+                        choice 
+                            prompt "HSP Clock division"
+                            default BSP_PWM4_HSPCLKDIV1
+                            config BSP_PWM4_HSPCLKDIV1
+                                bool "Clock Divided by 1"
+                            config BSP_PWM4_HSPCLKDIV2
+                                bool "Clock Divided by 2"
+                            config BSP_PWM4_HSPCLKDIV4
+                                bool "Clock Divided by 4"
+                        endchoice
+                        config BSP_PWM4_HSPCLKDIV
+                            int 
+                            default 0 if BSP_PWM4_HSPCLKDIV1
+                            default 1 if BSP_PWM4_HSPCLKDIV2
+                            default 2 if BSP_PWM4_HSPCLKDIV4
+                        choice 
+                            prompt "Clock division"
+                            default BSP_PWM4_CLKDIV1
+                            config BSP_PWM4_CLKDIV1
+                                bool "Clock Divided by 1"
+                            config BSP_PWM4_CLKDIV2
+                                bool "Clock Divided by 2"
+                            config BSP_PWM4_CLKDIV4
+                                bool "Clock Divided by 4"
+                        endchoice
+                        config BSP_PWM4_CLKDIV
+                            int 
+                            default 0 if BSP_PWM4_CLKDIV1
+                            default 1 if BSP_PWM4_CLKDIV2
+                            default 2 if BSP_PWM4_CLKDIV4
+                        choice 
+                            default BSP_PWM4_CTR_MODE_UPDOWN
+                            prompt "Select counter mode"
+                            config BSP_PWM4_CTR_MODE_UPDOWN
+                                bool "Up-down mode"
+                            config BSP_PWM4_CTR_MODE_UP
+                                bool "Up mode"
+                            config BSP_PWM4_CTR_MODE_DOWN
+                                bool "Down mode"
+                            config BSP_PWM4_CTR_FREEZE
+                                bool "Freezing Counter"
+                        endchoice
+                        config BSP_PWM4_CTRMODE
+                            int
+                            default 0 if BSP_PWM4_CTR_MODE_UP
+                            default 1 if BSP_PWM4_CTR_MODE_DOWN
+                            default 2 if BSP_PWM4_CTR_MODE_UPDOWN
+                            default 3 if BSP_PWM4_CTR_FREEZE
+                        choice
+                            prompt "Register load mode"
+                            config BSP_PWM4_CC_CTR_ZERO
+                                bool "Load when counter == 0"
+                            config BSP_PWM4_CC_CTR_PRD
+                                bool "Load when counter == prd"
+                            config BSP_PWM4_CC_CTR_ZERO_PRD
+                                bool "load when counter ==0 or counter == prd"
+                            config BSP_PWM4_CC_LD_DISABLE
+                                bool "disable load"
+                        endchoice
+
+                        config BSP_PWM4_LOADAMODE
+                            int 
+                            default 0 if BSP_PWM4_CC_CTR_ZERO
+                            default 1 if BSP_PWM4_CC_CTR_PRD
+                            default 2 if BSP_PWM4_CC_CTR_ZERO_PRD
+                            default 3 if BSP_PWM4_CC_LD_DISABLE
+
+                        config BSP_PWM4_DB
+                            int "Dead time(ns)"
+                            default 100
+                            range 0 100000
+                        menuconfig BSP_PWM4_ADC_TRIGGER
+                            bool "Enable ADC trigger from PWM4"
+                            if BSP_PWM4_ADC_TRIGGER
+                                choice
+                                    prompt "Select soc triggering time"
+                                    default BSP_PWM4_SOCASEL_ET_CTR_ZERO
+                                    config BSP_PWM4_SOCASEL_ET_DCAEVT1SOC
+                                        bool "DCAEVT1SOC"
+                                    config BSP_PWM4_SOCASEL_ET_CTR_ZERO
+                                        bool "ctr == zero"
+                                    config BSP_PWM4_SOCASEL_ET_CTR_PRD
+                                        bool "ctr == prd"
+                                    config BSP_PWM4_SOCASEL_ET_CTR_PRDZERO
+                                        bool "ctr == prd or ctr == zero"
+                                    config BSP_PWM4_SOCASEL_ET_CTRU_CMPA
+                                        bool "ctr == compa when counting up"
+                                    config BSP_PWM4_SOCASEL_ET_CTRD_CMPA
+                                        bool "ctr == compa when counting down"
+                                    config BSP_PWM4_SOCASEL_ET_CTRU_CMPB
+                                        bool "ctr == compb when counting up"
+                                    config BSP_PWM4_SOCASEL_ET_CTRD_CMPB
+                                        bool "ctr == compb when counting down"
+                                endchoice
+
+                                config BSP_PWM4_SOCASEL
+                                    int
+                                    default 0 if BSP_PWM4_SOCASEL_ET_DCAEVT1SOC
+                                    default 1 if BSP_PWM4_SOCASEL_ET_CTR_ZERO
+                                    default 2 if BSP_PWM4_SOCASEL_ET_CTR_PRD
+                                    default 3 if BSP_PWM4_SOCASEL_ET_CTR_PRDZERO
+                                    default 4 if BSP_PWM4_SOCASEL_ET_CTRU_CMPA
+                                    default 5 if BSP_PWM4_SOCASEL_ET_CTRD_CMPA
+                                    default 6 if BSP_PWM4_SOCASEL_ET_CTRU_CMPB
+                                    default 7 if BSP_PWM4_SOCASEL_ET_CTRD_CMPB
+                                choice
+                                    prompt "SOCA generation time"
+                                    default BSP_PWM4_SOCA_ET_1ST
+                                    config BSP_PWM4_SOCA_ET_DISABLE
+                                        bool "disable soc generation"
+                                    config BSP_PWM4_SOCA_ET_1ST
+                                        bool "generate soc at the first time"
+                                    config BSP_PWM4_SOCA_ET_2ND
+                                        bool "generate soc at the second time"
+                                    config BSP_PWM4_SOCA_ET_3RD
+                                        bool "generate soc at the third time"
+                                endchoice
+                                config BSP_PWM4_SOCAPRD
+                                    int 
+                                    default 0 if BSP_PWM4_SOCA_ET_DISABLE
+                                    default 1 if BSP_PWM4_SOCA_ET_1ST
+                                    default 2 if BSP_PWM4_SOCA_ET_2ND
+                                    default 3 if BSP_PWM4_SOCA_ET_3RD
+                            endif
+                    endmenu
+                endif
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+        endif
+
+    menuconfig BSP_USING_ONCHIP_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+        if BSP_USING_ONCHIP_RTC
+            choice
+                prompt "Select clock source"
+                default BSP_RTC_USING_LSE
+
+                config BSP_RTC_USING_LSE
+                    bool "RTC USING LSE"
+
+                config BSP_RTC_USING_LSI
+                    bool "RTC USING LSI"
+            endchoice
+        endif
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
+    config BSP_USING_SDIO
+        bool "Enable SDIO"
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        default n
+
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        default n
+        select RT_USING_CAN
+        if BSP_USING_CAN
+            config BSP_USING_CAN1
+                bool "using CAN1"
+                default n
+        endif
+
+    config BSP_USING_USBD
+        bool "Enable USB device"
+        select RT_USING_USB_DEVICE
+        default n
+        if BSP_USING_USBD
+            config BSP_USB_CONNECT_PIN
+                int "USB connect pin"
+                default 67
+
+            config BSP_USB_PULL_UP_STATUS
+                int "USB PULL UP STATUS"
+                default 0
+        endif
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/tms320f28379d/drivers/board.c b/bsp/c28x/tms320f28379d/board/board.c
similarity index 84%
rename from bsp/tms320f28379d/drivers/board.c
rename to bsp/c28x/tms320f28379d/board/board.c
index 2c9c38eb05..c391a2589e 100644
--- a/bsp/tms320f28379d/drivers/board.c
+++ b/bsp/c28x/tms320f28379d/board/board.c
@@ -13,6 +13,7 @@
 #include <rtthread.h>
 #include "board.h"
 #include "drv_sci.h"
+#include "drv_gpio.h"
 #include "F28x_Project.h"
 
 #ifndef RT_USING_SMP
@@ -59,6 +60,8 @@ interrupt void cpu_timer2_isr(void)
     rt_interrupt_leave();
 }
 
+extern interrupt void XINT1_Handler(void);
+extern interrupt void XINT2_Handler(void);
 /**
  * This function will initial TMS320F28379D board.
  */
@@ -82,12 +85,29 @@ void rt_hw_board_init()
     EALLOW;  // This is needed to write to EALLOW protected registers
     PieVectTable.TIMER2_INT = &cpu_timer2_isr;
     PieVectTable.RTOS_INT = &RTOSINT_Handler;
+
+#ifdef BSP_USING_XINT1
+    PieVectTable.XINT1_INT = &XINT1_Handler;
+#endif
+#ifdef BSP_USING_XINT2
+    PieVectTable.XINT2_INT = &XINT2_Handler;
+#endif
+#ifdef BSP_USING_XINT3
+    PieVectTable.XINT3_INT = &XINT3_Handler;
+#endif
+#ifdef BSP_USING_XINT4
+    PieVectTable.XINT4_INT = &XINT4_Handler;
+#endif
+#ifdef BSP_USING_XINT5
+    PieVectTable.XINT5_INT = &XINT5_Handler;
+#endif
     EDIS;
 
     InitCpuTimers();
     ConfigCpuTimer(&CpuTimer2, 200, 1000000 / RT_TICK_PER_SECOND);
     CpuTimer2Regs.TCR.all = 0x4000;
     IER |= M_INT14;
+    IER |= M_INT1;
 
 #ifdef RT_USING_HEAP
     rt_system_heap_init(&__ebss_end, &(__heap_end));
@@ -97,6 +117,10 @@ void rt_hw_board_init()
     rt_hw_sci_init();
 #endif
 
+#ifdef RT_USING_PIN
+    rt_hw_pin_init();
+#endif
+
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
diff --git a/bsp/tms320f28379d/drivers/board.h b/bsp/c28x/tms320f28379d/board/board.h
similarity index 100%
rename from bsp/tms320f28379d/drivers/board.h
rename to bsp/c28x/tms320f28379d/board/board.h
diff --git a/bsp/tms320f28379d/figures/build.png b/bsp/c28x/tms320f28379d/figures/build.png
similarity index 100%
rename from bsp/tms320f28379d/figures/build.png
rename to bsp/c28x/tms320f28379d/figures/build.png
diff --git a/bsp/tms320f28379d/figures/debug_as.png b/bsp/c28x/tms320f28379d/figures/debug_as.png
similarity index 100%
rename from bsp/tms320f28379d/figures/debug_as.png
rename to bsp/c28x/tms320f28379d/figures/debug_as.png
diff --git a/bsp/tms320f28379d/figures/import.png b/bsp/c28x/tms320f28379d/figures/import.png
similarity index 100%
rename from bsp/tms320f28379d/figures/import.png
rename to bsp/c28x/tms320f28379d/figures/import.png
diff --git a/bsp/tms320f28379d/figures/import_dia.png b/bsp/c28x/tms320f28379d/figures/import_dia.png
similarity index 100%
rename from bsp/tms320f28379d/figures/import_dia.png
rename to bsp/c28x/tms320f28379d/figures/import_dia.png
diff --git a/bsp/tms320f28379d/figures/launch-28379d.png b/bsp/c28x/tms320f28379d/figures/launch-28379d.png
similarity index 100%
rename from bsp/tms320f28379d/figures/launch-28379d.png
rename to bsp/c28x/tms320f28379d/figures/launch-28379d.png
diff --git a/bsp/tms320f28379d/figures/launching.png b/bsp/c28x/tms320f28379d/figures/launching.png
similarity index 100%
rename from bsp/tms320f28379d/figures/launching.png
rename to bsp/c28x/tms320f28379d/figures/launching.png
diff --git a/bsp/tms320f28379d/rtconfig.h b/bsp/c28x/tms320f28379d/rtconfig.h
similarity index 93%
rename from bsp/tms320f28379d/rtconfig.h
rename to bsp/c28x/tms320f28379d/rtconfig.h
index 5c94c07763..fc87483220 100644
--- a/bsp/tms320f28379d/rtconfig.h
+++ b/bsp/c28x/tms320f28379d/rtconfig.h
@@ -45,7 +45,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "scia"
-#define RT_VER_NUM 0x40101
+#define RT_VER_NUM 0x50000
 #define ARCH_TIDSP
 #define ARCH_TIDSP_C28X
 #define ARCH_CPU_STACK_GROWS_UPWARD
@@ -177,6 +177,19 @@
 
 /* entertainment: terminal games and other interesting software packages */
 
+
+/* Hardware Drivers Config */
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART1
+
+/* Board extended module Drivers */
+
 #include "rtconfig_project.h"
 
 #endif
diff --git a/bsp/tms320f28379d/rtconfig_project.h b/bsp/c28x/tms320f28379d/rtconfig_project.h
similarity index 100%
rename from bsp/tms320f28379d/rtconfig_project.h
rename to bsp/c28x/tms320f28379d/rtconfig_project.h
diff --git a/bsp/tms320f28379d/targetConfigs/TMS320F28379D.ccxml b/bsp/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml
similarity index 100%
rename from bsp/tms320f28379d/targetConfigs/TMS320F28379D.ccxml
rename to bsp/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml
diff --git a/bsp/tms320f28379d/targetConfigs/readme.txt b/bsp/c28x/tms320f28379d/targetConfigs/readme.txt
similarity index 100%
rename from bsp/tms320f28379d/targetConfigs/readme.txt
rename to bsp/c28x/tms320f28379d/targetConfigs/readme.txt
diff --git a/bsp/stm32/stm32f103-atk-nano/.config b/bsp/stm32/stm32f103-atk-nano/.config
index d03f8c6844..2ca2f6d4e7 100644
--- a/bsp/stm32/stm32f103-atk-nano/.config
+++ b/bsp/stm32/stm32f103-atk-nano/.config
@@ -80,7 +80,7 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40101
+CONFIG_RT_VER_NUM=0x50000
 CONFIG_ARCH_ARM=y
 CONFIG_RT_USING_CPU_FFS=y
 CONFIG_ARCH_ARM_CORTEX_M=y
@@ -505,7 +505,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_ADT74XX is not set
 # CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_RTT_ESP_IDF is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
@@ -583,7 +583,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_CW2015 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
-# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 
 #
 # AI packages
@@ -659,64 +658,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_MFBD is not set
 # CONFIG_PKG_USING_SLCAN2RTT is not set
 # CONFIG_PKG_USING_SOEM is not set
-# CONFIG_PKG_USING_QPARAM is not set
-
-#
-# Privated Packages of RealThread
-#
-# CONFIG_PKG_USING_CODEC is not set
-# CONFIG_PKG_USING_PLAYER is not set
-# CONFIG_PKG_USING_MPLAYER is not set
-# CONFIG_PKG_USING_PERSIMMON_SRC is not set
-# CONFIG_PKG_USING_JS_PERSIMMON is not set
-# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
-
-#
-# Network Utilities
-#
-# CONFIG_PKG_USING_WICED is not set
-# CONFIG_PKG_USING_CLOUDSDK is not set
-# CONFIG_PKG_USING_POWER_MANAGER is not set
-# CONFIG_PKG_USING_RT_OTA is not set
-# CONFIG_PKG_USING_RTINSIGHT is not set
-# CONFIG_PKG_USING_SMARTCONFIG is not set
-# CONFIG_PKG_USING_RTX is not set
-# CONFIG_RT_USING_TESTCASE is not set
-# CONFIG_PKG_USING_NGHTTP2 is not set
-# CONFIG_PKG_USING_AVS is not set
-# CONFIG_PKG_USING_ALI_LINKKIT is not set
-# CONFIG_PKG_USING_STS is not set
-# CONFIG_PKG_USING_DLMS is not set
-# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
-# CONFIG_PKG_USING_ZBAR is not set
-# CONFIG_PKG_USING_MCF is not set
-# CONFIG_PKG_USING_URPC is not set
-# CONFIG_PKG_USING_DCM is not set
-# CONFIG_PKG_USING_EMQ is not set
-# CONFIG_PKG_USING_CFGM is not set
-# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
-# CONFIG_PKG_USING_SMODULE is not set
-# CONFIG_PKG_USING_SNFD is not set
-# CONFIG_PKG_USING_UDBD is not set
-# CONFIG_PKG_USING_BENCHMARK is not set
-# CONFIG_PKG_USING_UBJSON is not set
-# CONFIG_PKG_USING_DATATYPE is not set
-# CONFIG_PKG_USING_FASTFS is not set
-# CONFIG_PKG_USING_RIL is not set
-# CONFIG_PKG_USING_WATCH_DCM_SVC is not set
-# CONFIG_PKG_USING_WATCH_APP_FWK is not set
-# CONFIG_PKG_USING_GUI_TEST is not set
-# CONFIG_PKG_USING_PMEM is not set
-# CONFIG_PKG_USING_LWRDP is not set
-# CONFIG_PKG_USING_MASAN is not set
-# CONFIG_PKG_USING_BSDIFF_LIB is not set
-# CONFIG_PKG_USING_PRC_DIFF is not set
-
-#
-# RT-Thread Smart
-#
-# CONFIG_PKG_USING_UKERNEL is not set
-# CONFIG_PKG_USING_TRACE_AGENT is not set
 CONFIG_SOC_FAMILY_STM32=y
 CONFIG_SOC_SERIES_STM32F1=y
 
diff --git a/bsp/stm32/stm32f103-atk-nano/rtconfig.h b/bsp/stm32/stm32f103-atk-nano/rtconfig.h
index ab30f3810e..976345330d 100644
--- a/bsp/stm32/stm32f103-atk-nano/rtconfig.h
+++ b/bsp/stm32/stm32f103-atk-nano/rtconfig.h
@@ -46,7 +46,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x40101
+#define RT_VER_NUM 0x50000
 #define ARCH_ARM
 #define RT_USING_CPU_FFS
 #define ARCH_ARM_CORTEX_M
@@ -179,15 +179,6 @@
 
 /* entertainment: terminal games and other interesting software packages */
 
-
-/* Privated Packages of RealThread */
-
-
-/* Network Utilities */
-
-
-/* RT-Thread Smart */
-
 #define SOC_FAMILY_STM32
 #define SOC_SERIES_STM32F1
 
diff --git a/bsp/tms320f28379d/.cproject b/bsp/tms320f28379d/.cproject
deleted file mode 100644
index 4dcd4d64f1..0000000000
--- a/bsp/tms320f28379d/.cproject
+++ /dev/null
@@ -1,401 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1821767246">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1821767246" moduleId="org.eclipse.cdt.core.settings" name="Debug">
-				<externalSettings/>
-				<extensions>
-					<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1821767246" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C2000.Debug">
-					<folderInfo id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1821767246." name="/" resourcePath="">
-						<toolChain id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.DebugToolchain.292610809" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.linkerDebug.2098344227">
-							<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.848606551" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
-								<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=TMS320C28XX.TMS320F28379D"/>
-								<listOptionValue builtIn="false" value="DEVICE_CORE_ID="/>
-								<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
-								<listOptionValue builtIn="false" value="OUTPUT_FORMAT=COFF"/>
-								<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE=2837x_RAM_lnk_cpu1.cmd"/>
-								<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
-								<listOptionValue builtIn="false" value="CCS_MBS_VERSION=6.1.3"/>
-								<listOptionValue builtIn="false" value="PRODUCTS="/>
-								<listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={}"/>
-								<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
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-									<listOptionValue builtIn="false" value="libc.a"/>
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-									<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/lib"/>
-									<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
-								</option>
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-									<listOptionValue builtIn="false" value=""/>
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-								<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__CMD2_SRCS.659513631" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__CMD2_SRCS"/>
-								<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__GEN_CMDS.338092707" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__GEN_CMDS"/>
-							</tool>
-							<tool id="com.ti.ccstudio.buildDefinitions.C2000_20.2.hex.1460260981" name="C2000 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.hex"/>
-						</toolChain>
-					</folderInfo>
-					<sourceEntries>
-						<entry excluding="2837x_FLASH_lnk_cpu1.cmd|DeviceDrivers/ipc/pipe.c|finsh/msh_cmd.c|libraries/common/source/F2837xD_SWPrioritizedPieVect.c|libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd|libraries/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd|libraries/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd|libraries/common/source/device.c|libraries/common/source/usb.c|libraries/common/source/usb_hal.c|libraries/common/targetConfigs|libraries/common/deprecated|libraries/common/cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
-					</sourceEntries>
-				</configuration>
-			</storageModule>
-			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
-		</cconfiguration>
-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
-		<project-mappings>
-			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/>
-			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
-			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
-			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
-			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
-		</project-mappings>
-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
-	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-		<project id="rt-thread.com.ti.ccstudio.buildDefinitions.C2000.ProjectType.1837437567" name="C2000" projectType="com.ti.ccstudio.buildDefinitions.C2000.ProjectType"/>
-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="scannerConfiguration"/>
-</cproject>
diff --git a/bsp/tms320f28379d/.gitignore b/bsp/tms320f28379d/.gitignore
deleted file mode 100644
index e335ff02f9..0000000000
--- a/bsp/tms320f28379d/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-.launches/
-/FLASH/
-/RAM/
diff --git a/bsp/tms320f28379d/.project b/bsp/tms320f28379d/.project
deleted file mode 100644
index d8178fe759..0000000000
--- a/bsp/tms320f28379d/.project
+++ /dev/null
@@ -1,64 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>rt-thread</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<triggers>full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>com.ti.ccstudio.core.ccsNature</nature>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.core.ccnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-	</natures>
-	<linkedResources>
-		<link>
-			<name>DeviceDrivers</name>
-			<type>2</type>
-			<locationURI>virtual:/virtual</locationURI>
-		</link>
-		<link>
-			<name>Kernel</name>
-			<type>2</type>
-			<locationURI>PARENT-2-PROJECT_LOC/src</locationURI>
-		</link>
-		<link>
-			<name>c28x</name>
-			<type>2</type>
-			<locationURI>PARENT-2-PROJECT_LOC/libcpu/ti-dsp/c28x</locationURI>
-		</link>
-		<link>
-			<name>finsh</name>
-			<type>2</type>
-			<locationURI>PARENT-2-PROJECT_LOC/components/finsh</locationURI>
-		</link>
-		<link>
-			<name>DeviceDrivers/ipc</name>
-			<type>2</type>
-			<locationURI>PARENT-2-PROJECT_LOC/components/drivers/ipc</locationURI>
-		</link>
-		<link>
-			<name>DeviceDrivers/rt_drv_pwm.c</name>
-			<type>1</type>
-			<locationURI>PARENT-2-PROJECT_LOC/components/drivers/misc/rt_drv_pwm.c</locationURI>
-		</link>
-		<link>
-			<name>DeviceDrivers/serial.c</name>
-			<type>1</type>
-			<locationURI>PARENT-2-PROJECT_LOC/components/drivers/serial/serial.c</locationURI>
-		</link>
-	</linkedResources>
-</projectDescription>
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_CLA_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_CLA_lnk_cpu1.cmd
deleted file mode 100644
index 9bc86fabf8..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_CLA_lnk_cpu1.cmd
+++ /dev/null
@@ -1,178 +0,0 @@
-// The user must define CLA_C in the project linker settings if using the
-// CLA C compiler
-// Project Properties -> C2000 Linker -> Advanced Options -> Command File
-// Preprocessing -> --define
-#ifdef CLA_C
-// Define a size for the CLA scratchpad area that will be used
-// by the CLA compiler for local symbols and temps
-// Also force references to the special symbols that mark the
-// scratchpad are.
-CLA_SCRATCHPAD_SIZE = 0x100;
---undef_sym=__cla_scratchpad_end
---undef_sym=__cla_scratchpad_start
-#endif //CLA_C
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x080000,   length = 0x000002
-   RAMM0           	: origin = 0x000122,   length = 0x0002DE
-   RAMD0           	: origin = 0x00B000,   length = 0x000800
-   RAMLS0          	: origin = 0x008000,   length = 0x000800
-   RAMLS1          	: origin = 0x008800,   length = 0x000800   
-   /* RAMLS4      	   : origin = 0x00A000, length = 0x000800 */
-   /* RAMLS5           : origin = 0x00A800, length = 0x000800 */
-   RAMLS4_5         : origin = 0x00A000,   length = 0x001000
-   
-   RAMGS14          : origin = 0x01A000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RESET           	: origin = 0x3FFFC0,   length = 0x000002
-
-   /* Flash sectors */
-   FLASHA           : origin = 0x080002,   length = 0x001FFE	/* on-chip Flash */
-   FLASHB           : origin = 0x082000,   length = 0x002000	/* on-chip Flash */
-   FLASHC           : origin = 0x084000,   length = 0x002000	/* on-chip Flash */
-   FLASHD           : origin = 0x086000,   length = 0x002000	/* on-chip Flash */
-   FLASHE           : origin = 0x088000,   length = 0x008000	/* on-chip Flash */
-   FLASHF           : origin = 0x090000,   length = 0x008000	/* on-chip Flash */
-   FLASHG           : origin = 0x098000,   length = 0x008000	/* on-chip Flash */
-   FLASHH           : origin = 0x0A0000,   length = 0x008000	/* on-chip Flash */
-   FLASHI           : origin = 0x0A8000,   length = 0x008000	/* on-chip Flash */
-   FLASHJ           : origin = 0x0B0000,   length = 0x008000	/* on-chip Flash */
-   FLASHK           : origin = 0x0B8000,   length = 0x002000	/* on-chip Flash */
-   FLASHL           : origin = 0x0BA000,   length = 0x002000	/* on-chip Flash */
-   FLASHM           : origin = 0x0BC000,   length = 0x002000	/* on-chip Flash */
-   FLASHN           : origin = 0x0BE000,   length = 0x002000	/* on-chip Flash */
-
-PAGE 1 :
-
-   BOOT_RSVD        : origin = 0x000002,   length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1            : origin = 0x000400,   length = 0x000400     /* on-chip RAM block M1 */
-
-   RAMLS2      		: origin = 0x009000,   length = 0x000800
-   RAMLS3      		: origin = 0x009800,   length = 0x000800
-
-   RAMGS0           : origin = 0x00C000,   length = 0x001000
-   RAMGS1           : origin = 0x00D000,   length = 0x001000
-   RAMGS2           : origin = 0x00E000,   length = 0x001000
-   RAMGS3           : origin = 0x00F000,   length = 0x001000
-   RAMGS4           : origin = 0x010000,   length = 0x001000
-   RAMGS5           : origin = 0x011000,   length = 0x001000
-   RAMGS6           : origin = 0x012000,   length = 0x001000
-   RAMGS7           : origin = 0x013000,   length = 0x001000
-   RAMGS8           : origin = 0x014000,   length = 0x001000
-   RAMGS9           : origin = 0x015000,   length = 0x001000
-   RAMGS10          : origin = 0x016000,   length = 0x001000
-   RAMGS11          : origin = 0x017000,   length = 0x001000
-   RAMGS12          : origin = 0x018000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13          : origin = 0x019000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   EMIF1_CS0n       : origin = 0x80000000, length = 0x10000000
-   EMIF1_CS2n       : origin = 0x00100000, length = 0x00200000
-   EMIF1_CS3n       : origin = 0x00300000, length = 0x00080000
-   EMIF1_CS4n       : origin = 0x00380000, length = 0x00060000
-   EMIF2_CS0n       : origin = 0x90000000, length = 0x10000000
-   EMIF2_CS2n       : origin = 0x00002000, length = 0x00001000
-
-   CLA1_MSGRAMLOW   : origin = 0x001480,   length = 0x000080
-   CLA1_MSGRAMHIGH  : origin = 0x001500,   length = 0x000080
-}
-
-
-SECTIONS
-{
-   /* Allocate program areas: */
-   .cinit           : > FLASHB      PAGE = 0, ALIGN(4)
-   .pinit           : > FLASHB,     PAGE = 0, ALIGN(4)
-   .text            : > FLASHB      PAGE = 0, ALIGN(4)
-   codestart        : > BEGIN       PAGE = 0, ALIGN(4)
-
-   /* Allocate uninitalized data sections: */
-   .stack           : > RAMM1        PAGE = 1
-   .ebss            : > RAMLS2       PAGE = 1
-   .esysmem         : > RAMLS2       PAGE = 1
-
-   /* Initalized sections go in Flash */
-   .econst          : > FLASHB      PAGE = 0, ALIGN(4)
-   .switch          : > FLASHB      PAGE = 0, ALIGN(4)
-
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
-   
-   .em2_cs0         : > EMIF2_CS0n, PAGE = 1
-   .em2_cs2         : > EMIF2_CS2n, PAGE = 1
-
-    /* CLA specific sections */
-   Cla1Prog         : LOAD = FLASHD,
-                      RUN = RAMLS4_5,
-                      LOAD_START(_Cla1funcsLoadStart),
-                      LOAD_END(_Cla1funcsLoadEnd),
-                      RUN_START(_Cla1funcsRunStart),
-                      LOAD_SIZE(_Cla1funcsLoadSize),
-                      PAGE = 0, ALIGN(4)
-
-   CLADataLS0		: > RAMLS0, PAGE=0
-   CLADataLS1		: > RAMLS1, PAGE=0
-
-   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
-   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} LOAD = FLASHD,
-						 RUN = RAMD0,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-						 PAGE = 0, ALIGN(4)
-   #else
-   ramfuncs         : LOAD = FLASHD,
-                      RUN = RAMD0,
-                      LOAD_START(_RamfuncsLoadStart),
-                      LOAD_SIZE(_RamfuncsLoadSize),
-                      LOAD_END(_RamfuncsLoadEnd),
-                      RUN_START(_RamfuncsRunStart),
-                      RUN_SIZE(_RamfuncsRunSize),
-                      RUN_END(_RamfuncsRunEnd),
-                      PAGE = 0, ALIGN(4)
-   #endif
-#endif
-
-   /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-
-#ifdef CLA_C
-   /* CLA C compiler sections */
-   //
-   // Must be allocated to memory the CLA has write access to
-   //
-   CLAscratch       :
-                     { *.obj(CLAscratch)
-                     . += CLA_SCRATCHPAD_SIZE;
-                     *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 0
-
-   .scratchpad      : > RAMLS1,       PAGE = 0
-   .bss_cla		    : > RAMLS1,       PAGE = 0
-   .const_cla	    :  LOAD = FLASHB,
-                       RUN = RAMLS1,
-                       RUN_START(_Cla1ConstRunStart),
-                       LOAD_START(_Cla1ConstLoadStart),
-                       LOAD_SIZE(_Cla1ConstLoadSize),
-                       PAGE = 0
-#endif //CLA_C
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_IQMATH_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_IQMATH_lnk_cpu1.cmd
deleted file mode 100644
index afd9da2351..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_IQMATH_lnk_cpu1.cmd
+++ /dev/null
@@ -1,134 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :  /* Program Memory */
-          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
-          /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x080000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-   /* Flash sectors */
-   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
-   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
-   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
-   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
-   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
-   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
-   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
-   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
-   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
-   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
-   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
-   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
-   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
-   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
-
-PAGE 1 : /* Data Memory */
-         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-
-SECTIONS
-{
-   /* Allocate program areas: */
-   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
-   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
-   .text               : > FLASHB      PAGE = 0, ALIGN(4)
-   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
-
-   /* Allocate uninitalized data sections: */
-   .stack              : > RAMM1        PAGE = 1
-   .ebss               : > RAMLS5       PAGE = 1
-   .esysmem            : > RAMLS5       PAGE = 1
-
-   /* Initalized sections go in Flash */
-   .econst             : > FLASHB      PAGE = 0, ALIGN(4)
-   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
-
-   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)
-   #else
-   ramfuncs            : LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-   /* Allocate IQ math areas: */
-   IQmath			: > FLASHB, PAGE = 0, ALIGN(4)            /* Math Code */
-   IQmathTables		: > FLASHC, PAGE = 0, ALIGN(4)
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_SGEN_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_SGEN_lnk_cpu1.cmd
deleted file mode 100644
index ffcab867e8..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_SGEN_lnk_cpu1.cmd
+++ /dev/null
@@ -1,147 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :  /* Program Memory */
-          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
-          /* BEGIN is used for the "boot to Flash" bootloader mode   */
-
-   BEGIN           	: origin = 0x080000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-   /* Flash sectors */
-   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
-   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
-   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
-   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
-   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
-   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
-   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
-   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
-   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
-   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
-   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
-   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
-   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
-
-PAGE 1 : /* Data Memory */
-         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   FLASHN      : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-
-SECTIONS
-{
-   /* Allocate program areas: */
-   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
-   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
-   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
-   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)
-   #else
-   ramfuncs            : LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)   
-   #endif
-#endif
-
-   /* Allocate uninitalized data sections: */
-   .stack              : > RAMM1        PAGE = 1
-   .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
-   .esysmem            : > RAMLS5       PAGE = 1
-
-   /* Initalized sections go in Flash */
-   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
-   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
-
-   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
-
-   ramgs0           : > RAMGS0,     PAGE = 1
-   ramgs1           : > RAMGS1,     PAGE = 1
-   .cio				: > RAMGS2,	   	PAGE = 1
-
-   /* Sine Table */
-   SINTBL			: > FLASHN,	   PAGE = 1
-
-   /* Data Log */
-   DLOG				: > RAMGS3,    PAGE = 1
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-   /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_TMU_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_TMU_lnk_cpu1.cmd
deleted file mode 100644
index e2d9e19e0f..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_TMU_lnk_cpu1.cmd
+++ /dev/null
@@ -1,136 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :  /* Program Memory */
-          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
-          /* BEGIN is used for the "boot to Flash" bootloader mode   */
-
-   BEGIN           	: origin = 0x080000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-   /* Flash sectors */
-   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
-   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
-   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
-   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
-   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
-   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
-   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
-   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
-   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
-   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
-   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
-   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
-   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
-   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
-
-PAGE 1 : /* Data Memory */
-         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
-
-   BOOT_RSVD        : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1            : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1            : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1           : origin = 0x00D000, length = 0x001000
-   RAMGS2_GS4       : origin = 0x00E000, length = 0x003000
-   /*
-   RAMGS2           : origin = 0x00E000, length = 0x001000
-   RAMGS3           : origin = 0x00F000, length = 0x001000
-   RAMGS4           : origin = 0x010000, length = 0x001000
-   */
-   RAMGS5           : origin = 0x011000, length = 0x001000
-   RAMGS6           : origin = 0x012000, length = 0x001000
-   RAMGS7           : origin = 0x013000, length = 0x001000
-   RAMGS8           : origin = 0x014000, length = 0x001000
-   RAMGS9           : origin = 0x015000, length = 0x001000
-   RAMGS10          : origin = 0x016000, length = 0x001000
-   RAMGS11          : origin = 0x017000, length = 0x001000
-   RAMGS12          : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13          : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CPU2TOCPU1RAM    : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM    : origin = 0x03FC00, length = 0x000400
-}
-
-
-SECTIONS
-{
-   /* Allocate program areas: */
-   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
-   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
-   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
-   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
-
-   /* Allocate uninitalized data sections: */
-   .stack              : > RAMGS1        PAGE = 1
-   .ebss               : > RAMGS2_GS4       PAGE = 1
-   .esysmem            : > RAMLS5       PAGE = 1
-
-   /* Initalized sections go in Flash */
-   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
-   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
-
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
-
-   .sysmem          : > RAMGS1,    PAGE = 1
-   .cio             : > RAMGS1,    PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),                         
-                         PAGE = 0, ALIGN(4)
-   #else
-   ramfuncs            : LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_afe031_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_afe031_lnk_cpu1.cmd
deleted file mode 100644
index 323926d783..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_afe031_lnk_cpu1.cmd
+++ /dev/null
@@ -1,170 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :  /* Program Memory */
-          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
-          /* BEGIN is used for the "boot to Flash" bootloader mode   */
-
-   BEGIN           	: origin = 0x080000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x001800
-  // RAMLS3      		: origin = 0x009800, length = 0x000800
- //  RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-   /* Flash sectors */
-   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
-   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
-   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
-   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
-   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
-   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
-   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
-   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
-   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
-   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
-   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
-   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
-   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
-   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
-
-PAGE 1 : /* Data Memory */
-         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-   /* Allocate program areas: */
-   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
-   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
-   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
-   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
-
-   /* Allocate uninitalized data sections: */
-   .stack              : > RAMM1        PAGE = 1
-   .ebss               : >> RAMGS0 | RAMGS1       PAGE = 1
-   .esysmem            : > RAMLS5       PAGE = 1
-   .cio                : > RAMLS5     PAGE = 1
-   
-   /* Initalized sections go in Flash */
-   .econst             : >> FLASHG | FLASHH      PAGE = 0, ALIGN(4)
-   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
-
-   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
-
-   SHARERAMGS0		: > RAMGS0,		PAGE = 1
-   SHARERAMGS1		: > RAMGS1,		PAGE = 1
-   ramgs0           : > RAMGS0,     PAGE = 1
-   ramgs1           : > RAMGS1,     PAGE = 1
-   ramls2           : > RAMLS2,     PAGE = 0
-//   SINETABLE        : > FLASHF      PAGE = 0, ALIGN(4)
-
-fsk_corr_lib_data : > RAMGS5		PAGE = 1	/* Flash block for lib data */
-
-#ifdef __TI_COMPILER_VERSION__
-	#if __TI_COMPILER_VERSION__ >= 15009000
-	.TI.ramfunc : {} LOAD = FLASHD,
-						 RUN = RAMLS0 | RAMLS1 | RAMLS2 ,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-						 PAGE = 0, ALIGN(4)
-	#else
-   ramfuncs            : LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)    
-    #endif
-#endif
-    #ifdef __TI_COMPILER_VERSION__
-	#if __TI_COMPILER_VERSION__ >= 15009000
-SINETABLE : {} LOAD = FLASHF,
-						 RUN = RAMLS2 ,
-                         LOAD_START(_SineTableLoadStart),
-                         LOAD_SIZE(_SineTableLoadSize),
-                         LOAD_END(_SineTableLoadEnd),
-                         RUN_START(_SineTableRunStart),
-                         RUN_SIZE(_SineTableRunSize),
-                         RUN_END(_SineTableRunEnd),
-						 PAGE = 0, ALIGN(4)
-
-	#else
-SINETABLE           :    LOAD = FLASHF,
-						 RUN = RAMLS2 ,
-                         LOAD_START(_SineTableLoadStart),
-                         LOAD_SIZE(_SineTableLoadSize),
-                         LOAD_END(_SineTableLoadEnd),
-                         RUN_START(_SineTableRunStart),
-                         RUN_SIZE(_SineTableRunSize),
-                         RUN_END(_SineTableRunEnd),
-						 PAGE = 0, ALIGN(4)
-
-    #endif
-#endif
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-   /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1.cmd
deleted file mode 100644
index b1dadb8351..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1.cmd
+++ /dev/null
@@ -1,142 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :  /* Program Memory */
-          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
-          /* BEGIN is used for the "boot to Flash" bootloader mode   */
-
-   BEGIN           	: origin = 0x080000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-   /* Flash sectors */
-   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
-   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
-   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
-   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
-   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
-   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
-   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
-   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
-   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
-   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
-   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
-   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
-   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
-   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
-
-PAGE 1 : /* Data Memory */
-         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-   /* Allocate program areas: */
-   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
-   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
-   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
-   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
-
-   /* Allocate uninitalized data sections: */
-   .stack              : > RAMM1        PAGE = 1
-   .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
-   .esysmem            : > RAMLS5       PAGE = 1
-   .cio                : > RAMLS5     PAGE = 1
-   
-   /* Initalized sections go in Flash */
-   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
-   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
-
-   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
-
-   SHARERAMGS0		: > RAMGS0,		PAGE = 1
-   SHARERAMGS1		: > RAMGS1,		PAGE = 1
-   ramgs0           : > RAMGS0,     PAGE = 1
-   ramgs1           : > RAMGS1,     PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-	#if __TI_COMPILER_VERSION__ >= 15009000
-	.TI.ramfunc : {} LOAD = FLASHD,
-						 RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-						 PAGE = 0, ALIGN(4)
-	#else
-   ramfuncs            : LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)    
-    #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-   /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1_far.cmd
deleted file mode 100644
index f8744f3935..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1_far.cmd
+++ /dev/null
@@ -1,156 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :  /* Program Memory */
-          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
-          /* BEGIN is used for the "boot to Flash" bootloader mode   */
-
-   BEGIN           	: origin = 0x080000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-   /* Flash sectors */
-   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
-   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
-   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
-   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
-   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
-   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
-   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
-   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
-   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
-   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
-   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
-   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
-   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
-   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
-
-PAGE 1 : /* Data Memory */
-         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5          : origin = 0x00A800, length = 0x000800
-
-   RAMGS0          : origin = 0x00C000, length = 0x001000
-   RAMGS1          : origin = 0x00D000, length = 0x001000
-   RAMGS2          : origin = 0x00E000, length = 0x001000
-   RAMGS3          : origin = 0x00F000, length = 0x001000
-   RAMGS4          : origin = 0x010000, length = 0x001000
-   RAMGS5          : origin = 0x011000, length = 0x001000
-   RAMGS6          : origin = 0x012000, length = 0x001000
-   RAMGS7          : origin = 0x013000, length = 0x001000
-   RAMGS8          : origin = 0x014000, length = 0x001000
-   RAMGS9          : origin = 0x015000, length = 0x001000
-   RAMGS10         : origin = 0x016000, length = 0x001000
-   RAMGS11         : origin = 0x017000, length = 0x001000
-   RAMGS12         : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13         : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   EMIF1_CS0n      : origin = 0x80000000, length = 0x10000000
-   EMIF1_CS2n      : origin = 0x00100000, length = 0x00200000
-   EMIF1_CS3n      : origin = 0x00300000, length = 0x00080000
-   EMIF1_CS4n      : origin = 0x00380000, length = 0x00060000
-   EMIF2_CS0n      : origin = 0x90000000, length = 0x10000000
-   EMIF2_CS2n      : origin = 0x00002000, length = 0x00001000
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-   /* Allocate program areas: */
-   .cinit           : > FLASHB      PAGE = 0, ALIGN(4)
-   .pinit           : > FLASHB,     PAGE = 0, ALIGN(4)
-   .text            : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
-   codestart        : > BEGIN       PAGE = 0, ALIGN(4)
-
-   /* Allocate uninitalized data sections: */
-   .stack           : > RAMM1        PAGE = 1
-   .ebss            : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
-   .esysmem         : > RAMLS5       PAGE = 1
-   .farbss          : > EMIF1_CS0n,  PAGE = 1
-
-   .em1_cs0         : > EMIF1_CS0n,      PAGE = 1
-   .em1_cs2         : > EMIF1_CS2n,      PAGE = 1
-   .em1_cs3         : > EMIF1_CS3n,      PAGE = 1
-   .em1_cs4         : > EMIF1_CS4n,      PAGE = 1
-   .em2_cs0         : > EMIF2_CS0n,      PAGE = 1
-   .em2_cs2         : > EMIF2_CS2n,      PAGE = 1
-
-   /* Initalized sections go in Flash */
-   .econst          : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
-   .switch          : > FLASHB      PAGE = 0, ALIGN(4)
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-   .farconst        : > EMIF1_CS0n, PAGE = 1
-
-   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
-
-   SHARERAMGS0		: > RAMGS0,		PAGE = 1
-   SHARERAMGS1		: > RAMGS1,		PAGE = 1
-   ramgs0           : > RAMGS0,     PAGE = 1
-   ramgs1           : > RAMGS1,     PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)
-   #else
-   ramfuncs            : LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-   /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2.cmd
deleted file mode 100644
index 038dfdbed8..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2.cmd
+++ /dev/null
@@ -1,114 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x080000, length = 0x000002
-   RAMM0           	: origin = 0x000080, length = 0x000380
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RESET       		: origin = 0x3FFFC0, length = 0x000002
-
-   /* Flash sectors */
-   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
-   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
-   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
-   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
-   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
-   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
-   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
-   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
-   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
-   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
-   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
-   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
-   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
-   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5          : origin = 0x00A800, length = 0x000800
-
-   RAMGS0          : origin = 0x00C000, length = 0x001000
-   RAMGS1          : origin = 0x00D000, length = 0x001000
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-   /* Allocate program areas: */
-   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
-   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
-   .text               : > FLASHB      PAGE = 0, ALIGN(4)
-   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
-
-   /* Allocate uninitalized data sections: */
-   .stack              : > RAMM1        PAGE = 1
-   .ebss               : > RAMLS5       PAGE = 1
-   .esysmem            : > RAMLS5       PAGE = 1
-
-   /* Initalized sections go in Flash */
-   .econst             : > FLASHB      PAGE = 0, ALIGN(4)
-   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   SHARERAMGS0		: > RAMGS0,		PAGE = 1
-   SHARERAMGS1		: > RAMGS1,		PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)
-   #else
-   ramfuncs            : LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2_far.cmd
deleted file mode 100644
index bd7aff0faf..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2_far.cmd
+++ /dev/null
@@ -1,120 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x080000, length = 0x000002
-   RAMM0           	: origin = 0x000080, length = 0x000380
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RESET       		: origin = 0x3FFFC0, length = 0x000002
-
-   /* Flash sectors */
-   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
-   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
-   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
-   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
-   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
-   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
-   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
-   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
-   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
-   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
-   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
-   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
-   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
-   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5          : origin = 0x00A800, length = 0x000800
-
-   RAMGS0          : origin = 0x00C000, length = 0x001000
-   RAMGS1          : origin = 0x00D000, length = 0x001000
-
-   EMIF1_CS0n      : origin = 0x80000000, length = 0x10000000
-   EMIF1_CS2n      : origin = 0x00100000, length = 0x00200000
-   EMIF1_CS3n      : origin = 0x00300000, length = 0x00080000
-   EMIF1_CS4n      : origin = 0x00380000, length = 0x00060000
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-   /* Allocate program areas: */
-   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
-   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
-   .text               : > FLASHB      PAGE = 0, ALIGN(4)
-   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
-
-   /* Allocate uninitalized data sections: */
-   .stack              : > RAMM1        PAGE = 1
-   .ebss               : > RAMLS5       PAGE = 1
-   .esysmem            : > RAMLS5       PAGE = 1
-   .farbss             : > EMIF1_CS0n,  PAGE = 1
-   /* Initalized sections go in Flash */
-   .econst             : > FLASHB       PAGE = 0, ALIGN(4)
-   .switch             : > FLASHB       PAGE = 0, ALIGN(4)
-   .reset              : > RESET,       PAGE = 0, TYPE = DSECT /* not used, */
-   .farconst           : > EMIF1_CS0n,  PAGE = 1
-   SHARERAMGS0		   : > RAMGS0,		PAGE = 1
-   SHARERAMGS1		   : > RAMGS1,		PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)
-   #else
-   ramfuncs            : LOAD = FLASHD,
-                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
-                         LOAD_START(_RamfuncsLoadStart),
-                         LOAD_SIZE(_RamfuncsLoadSize),
-                         LOAD_END(_RamfuncsLoadEnd),
-                         RUN_START(_RamfuncsRunStart),
-                         RUN_SIZE(_RamfuncsRunSize),
-                         RUN_END(_RamfuncsRunEnd),
-                         PAGE = 0, ALIGN(4)   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_CLA_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_CLA_lnk_cpu1.cmd
deleted file mode 100644
index 55100fcccb..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_CLA_lnk_cpu1.cmd
+++ /dev/null
@@ -1,135 +0,0 @@
-// The user must define CLA_C in the project linker settings if using the
-// CLA C compiler
-// Project Properties -> C2000 Linker -> Advanced Options -> Command File
-// Preprocessing -> --define
-#ifdef CLA_C
-// Define a size for the CLA scratchpad area that will be used
-// by the CLA compiler for local symbols and temps
-// Also force references to the special symbols that mark the
-// scratchpad are.
-CLA_SCRATCHPAD_SIZE = 0x100;
---undef_sym=__cla_scratchpad_end
---undef_sym=__cla_scratchpad_start
-#endif //CLA_C
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000,   length = 0x000002
-   RAMM0           	: origin = 0x000122,   length = 0x0002DE
-   RAMD0           	: origin = 0x00B000,   length = 0x000800
-   RAMD1            : origin = 0x00B800,   length = 0x000800
-   /* RAMLS4      	    : origin = 0x00A000, length = 0x000800 */
-   /* RAMLS5           : origin = 0x00A800, length = 0x000800 */
-   RAMLS4_5         : origin = 0x00A000,   length = 0x001000 
-   RESET           	: origin = 0x3FFFC0,   length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD        : origin = 0x000002,   length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1            : origin = 0x000400,   length = 0x000400     /* on-chip RAM block M1 */
-
-   RAMLS0          	: origin = 0x008000,   length = 0x000800
-   RAMLS1          	: origin = 0x008800,   length = 0x000800
-   RAMLS2      		: origin = 0x009000,   length = 0x000800
-   RAMLS3      		: origin = 0x009800,   length = 0x000800
-
-   RAMGS0           : origin = 0x00C000,   length = 0x001000
-   RAMGS1           : origin = 0x00D000,   length = 0x001000
-   RAMGS2           : origin = 0x00E000,   length = 0x001000
-   RAMGS3           : origin = 0x00F000,   length = 0x001000
-   RAMGS4           : origin = 0x010000,   length = 0x001000
-   RAMGS5           : origin = 0x011000,   length = 0x001000
-   RAMGS6           : origin = 0x012000,   length = 0x001000
-   RAMGS7           : origin = 0x013000,   length = 0x001000
-   RAMGS8           : origin = 0x014000,   length = 0x001000
-   RAMGS9           : origin = 0x015000,   length = 0x001000
-   RAMGS10          : origin = 0x016000,   length = 0x001000
-   RAMGS11          : origin = 0x017000,   length = 0x001000
-   RAMGS12          : origin = 0x018000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13          : origin = 0x019000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14          : origin = 0x01A000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   EMIF1_CS0n       : origin = 0x80000000, length = 0x10000000
-   EMIF1_CS2n       : origin = 0x00100000, length = 0x00200000
-   EMIF1_CS3n       : origin = 0x00300000, length = 0x00080000
-   EMIF1_CS4n       : origin = 0x00380000, length = 0x00060000
-   EMIF2_CS0n       : origin = 0x90000000, length = 0x10000000
-   EMIF2_CS2n       : origin = 0x00002000, length = 0x00001000
-
-   CANA_MSG_RAM     : origin = 0x049000,   length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000,   length = 0x000800
-
-   CLA1_MSGRAMLOW   : origin = 0x001480,   length = 0x000080
-   CLA1_MSGRAMHIGH  : origin = 0x001500,   length = 0x000080
-}
-
-SECTIONS
-{
-   codestart        : > BEGIN,      PAGE = 0
-   .text            : >> RAMM0 | RAMD0 | RAMD1,    PAGE = 0
-   .cinit           : > RAMM0,      PAGE = 0
-   .pinit           : > RAMM0,      PAGE = 0
-   .switch          : > RAMM0,      PAGE = 0
-   .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,      PAGE = 1
-   .ebss            : > RAMLS2,     PAGE = 1
-   .econst          : > RAMLS3,     PAGE = 1
-   .esysmem         : > RAMLS3,     PAGE = 1
-   Filter_RegsFile  : > RAMGS0,	    PAGE = 1
-
-   .em1_cs0         : > EMIF1_CS0n, PAGE = 1
-   .em1_cs2         : > EMIF1_CS2n, PAGE = 1
-   .em1_cs3         : > EMIF1_CS3n, PAGE = 1
-   .em1_cs4         : > EMIF1_CS4n, PAGE = 1
-   .em2_cs0         : > EMIF2_CS0n, PAGE = 1
-   .em2_cs2         : > EMIF2_CS2n, PAGE = 1
-
-    /* CLA specific sections */
-   Cla1Prog         : > RAMLS4_5, PAGE=0
-
-   CLADataLS0		: > RAMLS0, PAGE=1
-   CLADataLS1		: > RAMLS1, PAGE=1
-
-   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
-   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
-
-   /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-    ramfuncs    : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-#ifdef CLA_C
-   /* CLA C compiler sections */
-   //
-   // Must be allocated to memory the CLA has write access to
-   //
-   CLAscratch       :
-                     { *.obj(CLAscratch)
-                     . += CLA_SCRATCHPAD_SIZE;
-                     *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 1
-
-   .scratchpad      : > RAMLS1,       PAGE = 1
-   .bss_cla		    : > RAMLS1,       PAGE = 1
-   .const_cla	    : > RAMLS1,       PAGE = 1
-#endif //CLA_C
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu1.cmd
deleted file mode 100644
index 690c322d80..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu1.cmd
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker map for Soprano Shared Memory. */
-
-MEMORY
-{
-PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */
-
-
-PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */
-
-    CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-    CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-
-    /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-}
-
-/*
-* ===========================================================================
-* End of file.
-* ===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu2.cmd
deleted file mode 100644
index ca157058ee..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu2.cmd
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Linker map for Soprano Shared Memory. */
-
-MEMORY
-{
-PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */
-
-PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */
-
-	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-    CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-
-    /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-}
-
-/*
-* ===========================================================================
-* End of file.
-* ===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IQMATH_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IQMATH_lnk_cpu1.cmd
deleted file mode 100644
index 405efe5900..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IQMATH_lnk_cpu1.cmd
+++ /dev/null
@@ -1,103 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1_LS2       : origin = 0x008800, length = 0x001000
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            : >>RAMM0 | RAMD0 |  RAMLS0 | RAMLS1_LS2 | RAMLS3 | RAMLS4,   PAGE = 0
-   .cinit           : > RAMM0,     PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,     PAGE = 1
-   .ebss            : > RAMLS5,    PAGE = 1
-   .econst          : > RAMLS5,    PAGE = 1
-   .esysmem         : > RAMLS5,    PAGE = 1
-   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-    ramfuncs    : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-    /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
-
-   /* Allocate IQ math areas: */
-   IQmath			: > RAMLS0,     PAGE = 0            /* Math Code */
-   IQmathTables		: > RAMLS1_LS2, PAGE = 0
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SGEN_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SGEN_lnk_cpu1.cmd
deleted file mode 100644
index 0f42056151..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SGEN_lnk_cpu1.cmd
+++ /dev/null
@@ -1,106 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            : >>RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
-   .cinit           : > RAMM0,     PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,     PAGE = 1
-   .ebss            : > RAMLS5,    PAGE = 1
-   .econst          : > RAMLS5,    PAGE = 1
-   .esysmem         : > RAMLS5,    PAGE = 1
-   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
-
-   ramgs0           : > RAMGS0,    PAGE = 1
-   ramgs1           : > RAMGS1,    PAGE = 1
-   .cio				: > RAMGS2,	   PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-   ramfuncs         : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-   /* Sine Table */
-   SINTBL			: > RAMGS2,	   PAGE = 1
-
-   /* Data Log */
-   DLOG				: > RAMGS3,    PAGE = 1
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-    /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SWPrioritizedISR_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SWPrioritizedISR_lnk_cpu1.cmd
deleted file mode 100644
index b5c4b58c78..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SWPrioritizedISR_lnk_cpu1.cmd
+++ /dev/null
@@ -1,89 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-   RAMGS0_2         : origin = 0x00C000, length = 0x003000
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5          : origin = 0x00A800, length = 0x000800
-
-   RAMGS3          : origin = 0x00F000, length = 0x001000
-   RAMGS4          : origin = 0x010000, length = 0x001000
-   RAMGS5          : origin = 0x011000, length = 0x001000
-   RAMGS6          : origin = 0x012000, length = 0x001000
-   RAMGS7          : origin = 0x013000, length = 0x001000
-   RAMGS8          : origin = 0x014000, length = 0x001000
-   RAMGS9          : origin = 0x015000, length = 0x001000
-   RAMGS10         : origin = 0x016000, length = 0x001000
-   RAMGS11         : origin = 0x017000, length = 0x001000
-   RAMGS12         : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13         : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14         : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15         : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            : >>RAMGS0_2,   PAGE = 0
-   .cinit           : > RAMM0,     PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,     PAGE = 1
-   .ebss            : > RAMLS5,    PAGE = 1
-   .econst          : > RAMLS5,    PAGE = 1
-   .esysmem         : > RAMLS5,    PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-   ramfuncs         : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_TMU_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_TMU_lnk_cpu1.cmd
deleted file mode 100644
index 22e06c6e58..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_TMU_lnk_cpu1.cmd
+++ /dev/null
@@ -1,97 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RAMLS5           : origin = 0x00A800, length = 0x000800
-   RAMGS0           : origin = 0x00C000, length = 0x001000
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD        : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1            : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1            : origin = 0x00B800, length = 0x000800
-
-   RAMGS1           : origin = 0x00D000, length = 0x001000
-   RAMGS2_GS4       : origin = 0x00E000, length = 0x003000
-   /*
-   RAMGS2           : origin = 0x00E000, length = 0x001000
-   RAMGS3           : origin = 0x00F000, length = 0x001000
-   RAMGS4           : origin = 0x010000, length = 0x001000
-   */
-   RAMGS5           : origin = 0x011000, length = 0x001000
-   RAMGS6           : origin = 0x012000, length = 0x001000
-   RAMGS7           : origin = 0x013000, length = 0x001000
-   RAMGS8           : origin = 0x014000, length = 0x001000
-   RAMGS9           : origin = 0x015000, length = 0x001000
-   RAMGS10          : origin = 0x016000, length = 0x001000
-   RAMGS11          : origin = 0x017000, length = 0x001000
-   RAMGS12          : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13          : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-
-   CPU2TOCPU1RAM    : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM    : origin = 0x03FC00, length = 0x000400
-}
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            :>> RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS0,   PAGE = 0
-   .cinit           : > RAMM0,     PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMGS1,    PAGE = 1
-   .ebss            : > RAMGS2_GS4,PAGE = 1
-   .econst          : > RAMGS1,    PAGE = 1
-   .esysmem         : > RAMGS1,    PAGE = 1
-   Filter_RegsFile  : > RAMGS1,	   PAGE = 1
-
-   .sysmem          : > RAMGS1,    PAGE = 1
-   .cio             : > RAMGS1,    PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-   ramfuncs         : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_afe031_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_afe031_lnk_cpu1.cmd
deleted file mode 100644
index 5da6b7958c..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_afe031_lnk_cpu1.cmd
+++ /dev/null
@@ -1,99 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS234      		: origin = 0x009000, length = 0x001800
- //  RAMLS3      		: origin = 0x009800, length = 0x000800
- //  RAMLS4      		: origin = 0x00A000, length = 0x000800
-    RAMLS5      : origin = 0x00A800, length = 0x000800
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-}
-
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            : >> RAMD0 | RAMLS0 | RAMLS1,   PAGE = 0
-   .cinit           : >RAMM0 , PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,     PAGE = 1
-   .ebss            : >> RAMGS0,    PAGE = 1
-   .econst          : >> RAMLS234,    PAGE = 0
-   .esysmem         : > RAMLS5,    PAGE = 0
-   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
-
-   ramgs0           : > RAMGS0,    PAGE = 1
-   ramgs1           : > RAMGS3,    PAGE = 1
-
-   SINETABLE        : > RAMLS234    PAGE = 0	/* Ram block for SINETABLE data */
-   fsk_corr_lib_data : > RAMGS5,	PAGE = 1	/* Ram block for lib data */
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-    ramfuncs    : > RAMM0      PAGE = 0
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1.cmd
deleted file mode 100644
index 1561ba58b7..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1.cmd
+++ /dev/null
@@ -1,103 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-}
-
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            : >>RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
-   .cinit           : > RAMM0,     PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,     PAGE = 1
-   .ebss            : > RAMLS5,    PAGE = 1
-   .econst          : > RAMLS5,    PAGE = 1
-   .esysmem         : > RAMLS5,    PAGE = 1
-   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
-
-   ramgs0           : > RAMGS0,    PAGE = 1
-   ramgs1           : > RAMGS1,    PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-    ramfuncs    : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-    /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_USB.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_USB.cmd
deleted file mode 100644
index 0b470f5951..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_USB.cmd
+++ /dev/null
@@ -1,97 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x002000
-
-
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS01         : origin = 0x008000, length = 0x001000
-/*   RAMLS1          	: origin = 0x008800, length = 0x000800  */
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3_RAMLS4_RAMLS5      		: origin = 0x009800, length = 0x001800
-/*   RAMLS3      : origin = 0x009800, length = 0x000800  */
-/*   RAMLS4      : origin = 0x00A000, length = 0x000800  */
-/*   RAMLS5      : origin = 0x00A800, length = 0x000800  */
-   
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            : >> RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3 | RAMGS4 | RAMGS5,   PAGE = 0
-   .cio             : > RAMLS3_RAMLS4_RAMLS5, PAGE = 1
-   .sysmem          : > RAMD1, PAGE = 1
-   .cinit           : > RAMM0,     PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,     PAGE = 1
-   .ebss            : >> RAMLS01 | RAMLS2 | RAMLS3_RAMLS4_RAMLS5,     PAGE = 1
-   .econst          : > RAMLS3_RAMLS4_RAMLS5,     PAGE = 1
-   .esysmem         : > RAMLS3_RAMLS4_RAMLS5,     PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-   ramfuncs         : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_far.cmd
deleted file mode 100644
index 709c066557..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_far.cmd
+++ /dev/null
@@ -1,121 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5          : origin = 0x00A800, length = 0x000800
-
-   RAMGS0          : origin = 0x00C000, length = 0x001000
-   RAMGS1          : origin = 0x00D000, length = 0x001000
-   RAMGS2          : origin = 0x00E000, length = 0x001000
-   RAMGS3          : origin = 0x00F000, length = 0x001000
-   RAMGS4          : origin = 0x010000, length = 0x001000
-   RAMGS5          : origin = 0x011000, length = 0x001000
-   RAMGS6          : origin = 0x012000, length = 0x001000
-   RAMGS7          : origin = 0x013000, length = 0x001000
-   RAMGS8          : origin = 0x014000, length = 0x001000
-   RAMGS9          : origin = 0x015000, length = 0x001000
-   RAMGS10         : origin = 0x016000, length = 0x001000
-   RAMGS11         : origin = 0x017000, length = 0x001000
-   RAMGS12         : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13         : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS14         : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ 
-   RAMGS15         : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   EMIF1_CS0n      : origin = 0x80000000, length = 0x10000000
-   EMIF1_CS2n      : origin = 0x00100000, length = 0x00200000
-   EMIF1_CS3n      : origin = 0x00300000, length = 0x00080000
-   EMIF1_CS4n      : origin = 0x00380000, length = 0x00060000
-   EMIF2_CS0n      : origin = 0x90000000, length = 0x10000000
-   EMIF2_CS2n      : origin = 0x00002000, length = 0x00001000
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-
-SECTIONS
-{
-   codestart        : > BEGIN,           PAGE = 0
-   .text            : >>RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
-   .cinit           : > RAMM0,           PAGE = 0
-   .pinit           : > RAMM0,           PAGE = 0
-   .switch          : > RAMM0,           PAGE = 0
-   .reset           : > RESET,           PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,           PAGE = 1
-   .ebss            : > RAMLS5,          PAGE = 1
-   .econst          : > RAMLS5,          PAGE = 1
-   .esysmem         : > RAMLS5,          PAGE = 1
-
-   .farbss          : > EMIF1_CS0n,      PAGE = 1
-   .farconst        : > EMIF1_CS0n,      PAGE = 1
-
-   .em1_cs0         : > EMIF1_CS0n,      PAGE = 1
-   .em1_cs2         : > EMIF1_CS2n,      PAGE = 1
-   .em1_cs3         : > EMIF1_CS3n,      PAGE = 1
-   .em1_cs4         : > EMIF1_CS4n,      PAGE = 1
-   .em2_cs0         : > EMIF2_CS0n,      PAGE = 1
-   .em2_cs2         : > EMIF2_CS2n,      PAGE = 1
-
-   Filter_RegsFile  : > RAMGS0,	         PAGE = 1
-
-   ramgs0           : > RAMGS0,          PAGE = 1
-   ramgs1           : > RAMGS1,          PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,            PAGE = 0
-   #else
-   ramfuncs         : > RAMM0            PAGE = 0   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-
-    /* The following section definition are for SDFM examples */
-   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
-   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
-   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
-   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
-   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2.cmd
deleted file mode 100644
index 764ae4bea2..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2.cmd
+++ /dev/null
@@ -1,75 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000080, length = 0x000380
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          : origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RESET           : origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            : >>RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
-   .cinit           : > RAMM0,     PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,     PAGE = 1
-   .ebss            : > RAMLS5,     PAGE = 1
-   .econst          : > RAMLS5,     PAGE = 1
-   .esysmem         : > RAMLS5,     PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-   ramfuncs         : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2_far.cmd
deleted file mode 100644
index 976309764d..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2_far.cmd
+++ /dev/null
@@ -1,83 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000080, length = 0x000380
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0           : origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RESET            : origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   EMIF1_CS0n      : origin = 0x80000000, length = 0x10000000
-   EMIF1_CS2n      : origin = 0x00100000, length = 0x00200000
-   EMIF1_CS3n      : origin = 0x00300000, length = 0x00080000
-   EMIF1_CS4n      : origin = 0x00380000, length = 0x00060000
-
-   RAMLS5          : origin = 0x00A800, length = 0x000800
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-
-   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
-   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
-}
-
-
-SECTIONS
-{
-   codestart        : > BEGIN,      PAGE = 0
-   .text            : >>RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
-   .cinit           : > RAMM0,      PAGE = 0
-   .pinit           : > RAMM0,      PAGE = 0
-   .switch          : > RAMM0,      PAGE = 0
-   .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,      PAGE = 1
-   .ebss            : > RAMLS5,     PAGE = 1
-   .econst          : > RAMLS5,     PAGE = 1
-   .esysmem         : > RAMLS5,     PAGE = 1
-
-   .farbss          : > EMIF1_CS0n, PAGE = 1
-   .farconst        : > EMIF1_CS0n, PAGE = 1
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-   ramfuncs         : > RAMM0       PAGE = 0   
-   #endif
-#endif
-
-   /* The following section definitions are required when using the IPC API Drivers */
-    GROUP : > CPU2TOCPU1RAM, PAGE = 1
-    {
-        PUTBUFFER
-        PUTWRITEIDX
-        GETREADIDX
-    }
-
-    GROUP : > CPU1TOCPU2RAM, PAGE = 1
-    {
-        GETBUFFER :    TYPE = DSECT
-        GETWRITEIDX :  TYPE = DSECT
-        PUTREADIDX :   TYPE = DSECT
-    }
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu1.cmd
deleted file mode 100644
index d7f5abe0a1..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu1.cmd
+++ /dev/null
@@ -1,92 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000122, length = 0x0002DE
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0          	: origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RESET           	: origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-}
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            : >>RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
-   .cinit           : > RAMM0,     PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,     PAGE = 1
-   .ebss            : > RAMLS5,     PAGE = 1
-   .econst          : > RAMLS5,     PAGE = 1
-   .esysmem         : > RAMLS5,     PAGE = 1
-   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
-
-   SHARERAMGS0		: > RAMGS0,		PAGE = 1
-   SHARERAMGS1		: > RAMGS1,		PAGE = 1
-   SHARERAMGS2		: > RAMGS2,		PAGE = 1
-   SHARERAMGS3		: > RAMGS3,		PAGE = 1
-   SHARERAMGS4		: > RAMGS4,		PAGE = 1
-   SHARERAMGS5		: > RAMGS5,		PAGE = 1
-   SHARERAMGS6		: > RAMGS6,		PAGE = 1
-   SHARERAMGS7		: > RAMGS7,		PAGE = 1
-   SHARERAMGS8		: > RAMGS8,		PAGE = 1
-   SHARERAMGS9		: > RAMGS9,		PAGE = 1
-   SHARERAMGS10		: > RAMGS10,	PAGE = 1
-   SHARERAMGS11		: > RAMGS11,	PAGE = 1
-   SHARERAMGS12		: > RAMGS12,	PAGE = 1     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   SHARERAMGS13		: > RAMGS13,	PAGE = 1     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   SHARERAMGS14		: > RAMGS14,	PAGE = 0     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   SHARERAMGS15		: > RAMGS15,	PAGE = 0     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-   ramfuncs         : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu2.cmd
deleted file mode 100644
index da95201cf9..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu2.cmd
+++ /dev/null
@@ -1,92 +0,0 @@
-
-MEMORY
-{
-PAGE 0 :
-   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
-
-   BEGIN           	: origin = 0x000000, length = 0x000002
-   RAMM0           	: origin = 0x000080, length = 0x000380
-   RAMD0           	: origin = 0x00B000, length = 0x000800
-   RAMLS0           : origin = 0x008000, length = 0x000800
-   RAMLS1          	: origin = 0x008800, length = 0x000800
-   RAMLS2      		: origin = 0x009000, length = 0x000800
-   RAMLS3      		: origin = 0x009800, length = 0x000800
-   RAMLS4      		: origin = 0x00A000, length = 0x000800
-   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RESET            : origin = 0x3FFFC0, length = 0x000002
-
-PAGE 1 :
-
-   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
-   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
-   RAMD1           : origin = 0x00B800, length = 0x000800
-
-   RAMLS5      : origin = 0x00A800, length = 0x000800
-
-   RAMGS0      : origin = 0x00C000, length = 0x001000
-   RAMGS1      : origin = 0x00D000, length = 0x001000
-   RAMGS2      : origin = 0x00E000, length = 0x001000
-   RAMGS3      : origin = 0x00F000, length = 0x001000
-   RAMGS4      : origin = 0x010000, length = 0x001000
-   RAMGS5      : origin = 0x011000, length = 0x001000
-   RAMGS6      : origin = 0x012000, length = 0x001000
-   RAMGS7      : origin = 0x013000, length = 0x001000
-   RAMGS8      : origin = 0x014000, length = 0x001000
-   RAMGS9      : origin = 0x015000, length = 0x001000
-   RAMGS10     : origin = 0x016000, length = 0x001000
-   RAMGS11     : origin = 0x017000, length = 0x001000
-   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
-   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
-}
-
-
-SECTIONS
-{
-   codestart        : > BEGIN,     PAGE = 0
-   .text            : >>RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
-   .cinit           : > RAMM0,     PAGE = 0
-   .pinit           : > RAMM0,     PAGE = 0
-   .switch          : > RAMM0,     PAGE = 0
-   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
-
-   .stack           : > RAMM1,     PAGE = 1
-   .ebss            : > RAMLS5,     PAGE = 1
-   .econst          : > RAMLS5,     PAGE = 1
-   .esysmem         : > RAMLS5,     PAGE = 1
-
-   SHARERAMGS0		: > RAMGS0,		PAGE = 1
-   SHARERAMGS1		: > RAMGS1,		PAGE = 1
-   SHARERAMGS2		: > RAMGS2,		PAGE = 1
-   SHARERAMGS3		: > RAMGS3,		PAGE = 1
-   SHARERAMGS4		: > RAMGS4,		PAGE = 1
-   SHARERAMGS5		: > RAMGS5,		PAGE = 1
-   SHARERAMGS6		: > RAMGS6,		PAGE = 1
-   SHARERAMGS7		: > RAMGS7,		PAGE = 1
-   SHARERAMGS8		: > RAMGS8,		PAGE = 1
-   SHARERAMGS9		: > RAMGS9,		PAGE = 1
-   SHARERAMGS10		: > RAMGS10,	PAGE = 1
-   SHARERAMGS11		: > RAMGS11,	PAGE = 1
-   SHARERAMGS12		: > RAMGS12,	PAGE = 1     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   SHARERAMGS13		: > RAMGS13,	PAGE = 1     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   SHARERAMGS14		: > RAMGS14,	PAGE = 0     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-   SHARERAMGS15		: > RAMGS15,	PAGE = 0     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
-
-#ifdef __TI_COMPILER_VERSION__
-   #if __TI_COMPILER_VERSION__ >= 15009000
-    .TI.ramfunc : {} > RAMM0,      PAGE = 0
-   #else
-   ramfuncs         : > RAMM0      PAGE = 0   
-   #endif
-#endif
-
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu1.cmd
deleted file mode 100644
index ff0d4cb751..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu1.cmd
+++ /dev/null
@@ -1,68 +0,0 @@
-
-/* this linker command file is to be included if user wants to use the DCSM feature on the device
- * DCSM  means Dual Zone Code Security Module.
- * This linker command file works as an addendum ot the already existing Flash/RAM linker command file
- * that the project has.
- * The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file
- * NOTE - please note fill=0xFFFF, this helps if users include this file in the project by mistake and
- * doesn't provide the needed proper *_ZoneSelectBlock.asm sources .
- * Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this.
- *
- * Once users are confident that they want to program the passwords in OTP, the DSECT section type can be removed.
- *
-*/
-
-MEMORY
-{
-PAGE 0 :  /* Program Memory */
-
-   /* Z1 OTP.  LinkPointers */
-   DCSM_OTP_Z1_LINKPOINTER   : origin = 0x78000, length = 0x00000C
-   /* Z1 OTP.  PSWDLOCK/RESERVED */
-   DCSM_OTP_Z1_PSWDLOCK	    : origin = 0x78010, length = 0x000004
-   /* Z1 OTP.  CRCLOCK/RESERVED */
-   DCSM_OTP_Z1_CRCLOCK	    : origin = 0x78014, length = 0x000004
-   /* Z1 OTP.  RESERVED/BOOTCTRL */
-   DCSM_OTP_Z1_BOOTCTRL	    : origin = 0x7801C, length = 0x000004
-
-   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
-   /* Z1 OTP.  Z1 password locations / Flash and RAM partitioning */
-   DCSM_ZSEL_Z1_P0	        : origin = 0x78020, length = 0x000010
-
-   /* Z2 OTP.  LinkPointers */
-   DCSM_OTP_Z2_LINKPOINTER	: origin = 0x78200, length = 0x00000C
-   /* Z2 OTP.  GPREG1/GPREG2 */
-   DCSM_OTP_Z2_GPREG	        : origin = 0x7820C, length = 0x000004
-   /* Z2 OTP.  PSWDLOCK/RESERVED */
-   DCSM_OTP_Z2_PSWDLOCK	    : origin = 0x78210, length = 0x000004
-   /* Z2 OTP.  CRCLOCK/RESERVED */
-   DCSM_OTP_Z2_CRCLOCK	    : origin = 0x78214, length = 0x000004
-   /* Z2 OTP.  GPREG3/BOOTCTRL */
-   DCSM_OTP_Z2_BOOTCTRL	    : origin = 0x7821C, length = 0x000004
-
-   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
-   /* Z2 OTP.  Z2 password locations / Flash and RAM partitioning  */
-   DCSM_ZSEL_Z2_P0	        : origin = 0x78220, length = 0x000010
-
-}
-
-SECTIONS
-{
-   dcsm_otp_z1_linkpointer 	: > DCSM_OTP_Z1_LINKPOINTER		PAGE = 0, type = DSECT
-   dcsm_otp_z1_pswdlock		: > DCSM_OTP_Z1_PSWDLOCK		PAGE = 0, type = DSECT
-   dcsm_otp_z1_crclock		: > DCSM_OTP_Z1_CRCLOCK			PAGE = 0, type = DSECT
-   dcsm_otp_z1_bootctrl		: > DCSM_OTP_Z1_BOOTCTRL		PAGE = 0, type = DSECT
-   dcsm_zsel_z1				: > DCSM_ZSEL_Z1_P0				PAGE = 0, type = DSECT
-
-   dcsm_otp_z2_linkpointer	: > DCSM_OTP_Z2_LINKPOINTER		PAGE = 0, type = DSECT
-   dcsm_otp_z2_pswdlock		: > DCSM_OTP_Z2_PSWDLOCK		PAGE = 0, type = DSECT
-   dcsm_otp_z2_crclock		: > DCSM_OTP_Z2_CRCLOCK			PAGE = 0, type = DSECT
-   dcsm_otp_z2_bootctrl		: > DCSM_OTP_Z2_BOOTCTRL		PAGE = 0, type = DSECT
-   dcsm_zsel_z2				: > DCSM_ZSEL_Z2_P0				PAGE = 0, type = DSECT
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu2.cmd
deleted file mode 100644
index 38111c8a18..0000000000
--- a/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu2.cmd
+++ /dev/null
@@ -1,44 +0,0 @@
-
-/* this linker command file is to be included if user wants to use the DCSM feature on the device
- * DCSM  means Dual Zone Code Security Module.
- * This linker command file works as an addendum ot the already existing Flash/RAM linker command file
- * that the project has.
- * The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file
- * NOTEG - please note fill=0xFFFF, this helps if users include this file in the project by mistake and
- * doesn't provide the needed *_ZoneSelectBlock.asm sources.
- * Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this.
-*/
-
-MEMORY
-{
-PAGE 0 :  /* Program Memory */
-
-   /* Part of Z1 OTP.  LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */
-   DCSM_OTP_Z1_P0	: origin = 0x78000, length = 0x000020
-   /* Part of Z2 OTP.  LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */
-   DCSM_OTP_Z2_P0	: origin = 0x78200, length = 0x000020
-
-   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
-   /* Part of Z1 OTP.  Z1 password locations / Flash and RAM partitioning */
-   DCSM_ZSEL_Z1_P0	: origin = 0x78020, length = 0x000010
-
-   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
-   /* Part of Z2 OTP.  Z2 password locations / Flash and RAM partitioning  */
-   DCSM_ZSEL_Z2_P0	: origin = 0x78220, length = 0x000010
-}
-
-
-SECTIONS
-{
-   dcsm_otp_z1		: > DCSM_OTP_Z1_P0,		PAGE = 0, type = DSECT
-   dcsm_otp_z2		: > DCSM_OTP_Z2_P0,		PAGE = 0, type = DSECT
-
-   dcsm_zsel_z1		: > DCSM_ZSEL_Z1_P0,	PAGE = 0, type = DSECT
-   dcsm_zsel_z2		: > DCSM_ZSEL_Z2_P0,	PAGE = 0, type = DSECT
-}
-
-/*
-//===========================================================================
-// End of file.
-//===========================================================================
-*/
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/Deprecated_F2837xD_DRL_UG.pdf b/bsp/tms320f28379d/libraries/common/deprecated/Deprecated_F2837xD_DRL_UG.pdf
deleted file mode 100644
index 759a3d87ff..0000000000
Binary files a/bsp/tms320f28379d/libraries/common/deprecated/Deprecated_F2837xD_DRL_UG.pdf and /dev/null differ
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.c
deleted file mode 100644
index 72343c5094..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.c
+++ /dev/null
@@ -1,1919 +0,0 @@
-//###########################################################################
-//
-// FILE:   can.c
-//
-// TITLE:  F2837xD CAN Initialization & Support Functions.
-//
-// NOTE: The CAN bus bridge uses a different addressing scheme in order to
-//       allow byte accesses. Because of this, 32-bit reads/writes can execute
-//       abnormally at higher optimization levels. The CAN driver functions
-//       have been adjusted to explicitly use two 16-bit read/writes to access
-//       the full 32-bit register where HWREGH(base + offset) represents the
-//       lower 16-bits and HWREGH(base + offset + 2) represents the upper
-//       16-bits.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-//*****************************************************************************
-//! \addtogroup can_api
-//! @{
-//*****************************************************************************
-
-#include "F28x_Project.h"
-#include <stdint.h>
-#include <stdbool.h>
-#include "inc/hw_can.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_types.h"
-#include "driverlib/can.h"
-#include "driverlib/debug.h"
-#include "driverlib/interrupt.h"
-
-//*****************************************************************************
-// This is the maximum number that can be stored as an 11bit Message
-// identifier.
-//*****************************************************************************
-#define CAN_MAX_11BIT_MSG_ID    (0x7ff)
-
-//*****************************************************************************
-// This is used as the loop delay for accessing the CAN controller registers.
-//*****************************************************************************
-
-// The maximum CAN bit timing divisor is 13.
-#define CAN_MAX_BIT_DIVISOR     (13)
-
-// The minimum CAN bit timing divisor is 5.
-#define CAN_MIN_BIT_DIVISOR     (5)
-
-// The maximum CAN pre-divisor is 1024.
-#define CAN_MAX_PRE_DIVISOR     (1024)
-
-// The minimum CAN pre-divisor is 1.
-#define CAN_MIN_PRE_DIVISOR     (1)
-
-//*****************************************************************************
-// This table is used by the CANBitRateSet() API as the register defaults for
-// the bit timing values.
-//*****************************************************************************
-
-static const uint16_t g_ui16CANBitValues[] =
-{
-    0x1100, // TSEG2 2, TSEG1 2, SJW 1, Divide 5
-    0x1200, // TSEG2 2, TSEG1 3, SJW 1, Divide 6
-    0x2240, // TSEG2 3, TSEG1 3, SJW 2, Divide 7
-    0x2340, // TSEG2 3, TSEG1 4, SJW 2, Divide 8
-    0x3340, // TSEG2 4, TSEG1 4, SJW 2, Divide 9
-    0x3440, // TSEG2 4, TSEG1 5, SJW 2, Divide 10
-    0x3540, // TSEG2 4, TSEG1 6, SJW 2, Divide 11
-    0x3640, // TSEG2 4, TSEG1 7, SJW 2, Divide 12
-    0x3740  // TSEG2 4, TSEG1 8, SJW 2, Divide 13
-};
-
-//*****************************************************************************
-//! \internal
-//! Checks a CAN base address.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//!
-//! This function determines if a CAN controller base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static bool
-CANBaseValid(uint32_t ui32Base)
-{
-    return((ui32Base == CANA_BASE) || (ui32Base == CANB_BASE));
-}
-
-#endif
-
-//*****************************************************************************
-//! \internal
-//!
-//! Returns the CAN controller interrupt number.
-//!
-//! \param ui32Base is the base address of the selected CAN controller
-//! \param ucNumber is the interrupt line number requested, valid values are 0
-//! or 1
-//!
-//! Given a CAN controller base address and interrupt line number, returns the
-//! corresponding interrupt number.
-//!
-//! \return Returns a CAN interrupt number, or -1 if \e ui32Port is invalid.
-//
-//*****************************************************************************
-static int32_t
-CANIntNumberGet(uint32_t ui32Base, unsigned char ucNumber)
-{
-    int32_t lIntNumber;
-
-    // Return the interrupt number for the given CAN controller.
-    switch(ui32Base)
-    {
-        // Return the interrupt number for CAN 0
-        case CANA_BASE:
-        {
-            switch(ucNumber)
-            {
-            case 0:
-            {
-                lIntNumber = INT_CANA_0;
-                break;
-            }
-            case 1:
-            {
-                lIntNumber = INT_CANA_1;
-                break;
-
-            }
-            default:
-            {
-                lIntNumber = -1;
-                break;
-            }
-            }
-            break;
-        }
-
-        // Return the interrupt number for CAN 1
-        case CANB_BASE:
-        {
-            switch(ucNumber)
-            {
-            case 0:
-            {
-                lIntNumber = INT_CANB_0;
-                break;
-            }
-            case 1:
-            {
-                lIntNumber = INT_CANB_1;
-                break;
-
-            }
-            default:
-            {
-                lIntNumber = -1;
-                break;
-            }
-            }
-            break;
-        }
-
-        // Return -1 to indicate a bad address was passed in.
-        default:
-        {
-            lIntNumber = -1;
-        }
-    }
-    return(lIntNumber);
-}
-
-//*****************************************************************************
-//! \internal
-//!
-//! Copies data from a buffer to the CAN Data registers.
-//!
-//! \param pucData is a pointer to the data to be written out to the CAN
-//! controller's data registers.
-//! \param pui32Register is an uint32_t pointer to the first register of the
-//! CAN controller's data registers.  For example, in order to use the IF1
-//! register set on CAN controller A, the value would be: \b CANA_BASE \b +
-//! \b CAN_O_IF1DATA.
-//! \param iSize is the number of bytes to copy into the CAN controller.
-//!
-//! This function takes the steps necessary to copy data from a contiguous
-//! buffer in memory into the non-contiguous data registers used by the CAN
-//! controller.  This function is rarely used outside of the CANMessageSet()
-//! function.
-//!
-//! This function replaces the original CANWriteDataReg() API and performs the
-//! same actions.  A macro is provided in <tt>can.h</tt> to map the original
-//! API to this API.
-//!
-//! \return None.
-//
-//*****************************************************************************
-static void
-CANDataRegWrite(unsigned char *pucData, uint32_t *pui32Register, int16_t iSize)
-{
-    int16_t iIdx;
-    unsigned char * pucRegister = (unsigned char *) pui32Register;
-
-    // Loop always copies 1 or 2 bytes per iteration.
-    for(iIdx = 0; iIdx < iSize; iIdx++ )
-    {
-        // Write out the data 8 bits at a time.
-        HWREGB(pucRegister++) = pucData[iIdx];
-    }
-}
-
-//*****************************************************************************
-//! \internal
-//!
-//! Copies data from a buffer to the CAN Data registers.
-//!
-//! \param pucData is a pointer to the location to store the data read from the
-//! CAN controller's data registers.
-//! \param pui32Register is an uint32_t pointer to the first register of the
-//! CAN controller's data registers.  For example, in order to use the IF1
-//! register set on CAN controller A, the value would be: \b CANA_BASE \b +
-//! \b CAN_O_IF1DATA.
-//! \param iSize is the number of bytes to copy from the CAN controller.
-//!
-//! This function takes the steps necessary to copy data to a contiguous buffer
-//! in memory from the non-contiguous data registers used by the CAN
-//! controller.  This function is rarely used outside of the CANMessageGet()
-//! function.
-//!
-//! This function replaces the original CANReadDataReg() API and performs the
-//! same actions.  A macro is provided in <tt>can.h</tt> to map the original
-//! API to this API.
-//!
-//! \return None.
-//
-//*****************************************************************************
-static void
-CANDataRegRead(unsigned char *pucData, uint32_t *pui32Register, int16_t iSize)
-{
-    int16_t iIdx;
-    unsigned char * pucRegister = (unsigned char *) pui32Register;
-
-    // Loop always copies 1 or 2 bytes per iteration.
-    for(iIdx = 0; iIdx < iSize; iIdx++ )
-    {
-        // Read out the data
-        pucData[iIdx] = HWREGB(pucRegister++);
-    }
-}
-
-//*****************************************************************************
-//
-//! Initializes the CAN controller after reset.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//!
-//! After reset, the CAN controller is left in the disabled state.  However,
-//! the memory used for message objects contains undefined values and must be
-//! cleared prior to enabling the CAN controller the first time.  This prevents
-//! unwanted transmission or reception of data before the message objects are
-//! configured.  This function must be called before enabling the controller
-//! the first time.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANInit(uint32_t ui32Base)
-{
-    int16_t iMsg;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    // Place CAN controller in init state, regardless of previous state.  This
-    // will put controller in idle, and allow the message object RAM to be
-    // programmed.
-
-    HWREGH(ui32Base + CAN_O_CTL) = CAN_CTL_INIT;
-    HWREGH(ui32Base + CAN_O_CTL) = CAN_CTL_SWR;
-
-    // Wait for busy bit to clear
-    while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY)
-    {
-    }
-
-    // Clear the message value bit in the arbitration register.  This indicates
-    // the message is not valid and is a "safe" condition to leave the message
-    // object.  The same arb reg is used to program all the message objects.
-    HWREGH(ui32Base + CAN_O_IF1CMD + 2) = (CAN_IF1CMD_DIR | CAN_IF1CMD_ARB |
-                                           CAN_IF1CMD_CONTROL) >> 16;
-    HWREGH(ui32Base + CAN_O_IF1ARB) = 0;
-    HWREGH(ui32Base + CAN_O_IF1ARB + 2) = 0;
-
-    HWREGH(ui32Base + CAN_O_IF1MCTL) = 0;
-    HWREGH(ui32Base + CAN_O_IF1MCTL + 2) = 0;
-
-    HWREGH(ui32Base + CAN_O_IF2CMD + 2) = (CAN_IF2CMD_DIR | CAN_IF2CMD_ARB |
-                                           CAN_IF2CMD_CONTROL) >> 16;
-    HWREGH(ui32Base + CAN_O_IF2ARB) = 0;
-    HWREGH(ui32Base + CAN_O_IF2ARB + 2) = 0;
-
-    HWREGH(ui32Base + CAN_O_IF2MCTL) = 0;
-    HWREGH(ui32Base + CAN_O_IF2MCTL + 2) = 0;
-
-    // Loop through to program all 32 message objects
-    for(iMsg = 1; iMsg <= 32; iMsg+=2)
-    {
-        // Wait for busy bit to clear
-        while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY)
-        {
-        }
-
-        // Initiate programming the message object
-        HWREGH(ui32Base + CAN_O_IF1CMD) = iMsg;
-
-        // Wait for busy bit to clear
-        while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY)
-        {
-        }
-
-        // Initiate programming the message object
-        HWREGH(ui32Base + CAN_O_IF2CMD) = iMsg + 1;
-    }
-
-    // Make sure that the interrupt and new data flags are updated for the
-    // message objects.
-    HWREGH(ui32Base + CAN_O_IF1CMD + 2) = (CAN_IF1CMD_TXRQST |
-                                           CAN_IF1CMD_CLRINTPND) >> 16;
-    HWREGH(ui32Base + CAN_O_IF2CMD + 2) = (CAN_IF2CMD_TXRQST |
-                                           CAN_IF2CMD_CLRINTPND) >> 16;
-
-    // Loop through to program all 32 message objects
-    for(iMsg = 1; iMsg <= 32; iMsg+=2)
-    {
-        // Wait for busy bit to clear.
-        while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY)
-        {
-        }
-
-        // Initiate programming the message object
-        HWREGH(ui32Base + CAN_O_IF1CMD) = iMsg;
-
-        // Wait for busy bit to clear.
-        while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY)
-        {
-        }
-
-        // Initiate programming the message object
-        HWREGH(ui32Base + CAN_O_IF2CMD) = iMsg + 1;
-    }
-
-    // Acknowledge any pending status interrupts.
-    HWREG(ui32Base + CAN_O_ES);
-}
-
-//*****************************************************************************
-//
-//! Enables the CAN controller.
-//!
-//! \param ui32Base is the base address of the CAN controller to enable.
-//!
-//! Enables the CAN controller for message processing.  Once enabled, the
-//! controller will automatically transmit any pending frames, and process any
-//! received frames.  The controller can be stopped by calling CANDisable().
-//! Prior to calling CANEnable(), CANInit() should have been called to
-//! initialize the controller and the CAN bus clock should be configured by
-//! calling CANBitTimingSet().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANEnable(uint32_t ui32Base)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    // Clear the init bit in the control register.
-    HWREGH(ui32Base + CAN_O_CTL) = HWREGH(ui32Base + CAN_O_CTL) &
-                                   ~CAN_CTL_INIT;
-}
-
-//*****************************************************************************
-//
-//! Disables the CAN controller.
-//!
-//! \param ui32Base is the base address of the CAN controller to disable.
-//!
-//! Disables the CAN controller for message processing.  When disabled, the
-//! controller will no longer automatically process data on the CAN bus.  The
-//! controller can be restarted by calling CANEnable().  The state of the CAN
-//! controller and the message objects in the controller are left as they were
-//! before this call was made.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANDisable(uint32_t ui32Base)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    // Set the init bit in the control register.
-    HWREGH(ui32Base + CAN_O_CTL) = HWREGH(ui32Base + CAN_O_CTL) |
-                                   CAN_CTL_INIT;
-}
-
-//*****************************************************************************
-//
-//! Select CAN peripheral clock source
-//!
-//! \param ui32Base is the base address of the CAN controller to disable.
-//! \param ui16Source is the clock source to select for the given CAN
-//!        peripheral: \n
-//!        0 - Selected CPU SYSCLKOUT (CPU1.Sysclk or CPU2.Sysclk)
-//!           (default at reset) \n
-//!        1 - External Oscillator (OSC) clock (direct from X1/X2) \n
-//!        2 - AUXCLKIN = GPIOn(GPIO19)
-//!
-//! Selects the desired clock source for use with a given CAN peripheral.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void CANClkSourceSelect(uint32_t ui32Base, uint16_t ui16Source)
-{
-    EALLOW;
-    switch(ui32Base)
-    {
-        case CANA_BASE:
-        {
-            ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = ui16Source;
-        }
-
-        case CANB_BASE:
-        {
-            ClkCfgRegs.CLKSRCCTL2.bit.CANBBCLKSEL = ui16Source;
-        }
-
-        default:
-            break;
-    }
-    EDIS;
-}
-
-//*****************************************************************************
-//
-//! Reads the current settings for the CAN controller bit timing.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param pClkParms is a pointer to a structure to hold the timing parameters.
-//!
-//! This function reads the current configuration of the CAN controller bit
-//! clock timing, and stores the resulting information in the structure
-//! supplied by the caller.  Refer to CANBitTimingSet() for the meaning of the
-//! values that are returned in the structure pointed to by \e pClkParms.
-//!
-//! This function replaces the original CANGetBitTiming() API and performs the
-//! same actions.  A macro is provided in <tt>can.h</tt> to map the original
-//! API to this API.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *pClkParms)
-{
-    uint32_t uBitReg;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT(pClkParms != 0);
-
-    uBitReg = HWREG(ui32Base + CAN_O_BTR);
-
-    // Set the phase 2 segment.
-    pClkParms->uPhase2Seg = ((uBitReg & CAN_BTR_TSEG2_M) >> 12) + 1;
-
-    // Set the phase 1 segment.
-    pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BTR_TSEG1_M) >> 8) + 1;
-
-    // Set the synchronous jump width.
-    pClkParms->uSJW = ((uBitReg & CAN_BTR_SJW_M) >> 6) + 1;
-
-    // Set the pre-divider for the CAN bus bit clock.
-    pClkParms->uQuantumPrescaler = ((uBitReg & CAN_BTR_BRP_M) |
-                                    ((uBitReg & CAN_BTR_BRPE_M) >> 10)) + 1;
-}
-
-//*****************************************************************************
-//
-//! This function is used to set the CAN bit timing values to a nominal setting
-//! based on a desired bit rate.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32SourceClock is the clock frequency for the CAN peripheral in Hz.
-//! \param ui32BitRate is the desired bit rate.
-//!
-//! This function will set the CAN bit timing for the bit rate passed in the
-//! \e ui32BitRate parameter based on the \e ui32SourceClock parameter. The CAN
-//! bit clock is calculated to be an average timing value that should work for
-//! most systems.  If tighter timing requirements are needed, then the
-//! CANBitTimingSet() function is available for full customization of all of
-//! the CAN bit timing values.  Since not all bit rates can be matched
-//! exactly, the bit rate is set to the value closest to the desired bit rate
-//! without being higher than the \e ui32BitRate value.
-//!
-//! \return This function returns the bit rate that the CAN controller was
-//! configured to use or it returns 0 to indicate that the bit rate was not
-//! changed because the requested bit rate was not valid.
-//
-//*****************************************************************************
-uint32_t
-CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, uint32_t ui32BitRate)
-{
-    uint32_t ui32DesiredRatio;
-    uint32_t ui32CANBits;
-    uint32_t ui32PreDivide;
-    uint32_t ui32RegValue;
-    uint16_t ui16CANCTL;
-
-    ASSERT(ui32BitRate != 0);
-
-    // Calculate the desired clock rate.
-    ui32DesiredRatio = ui32SourceClock / ui32BitRate;
-
-    // If the ratio of CAN bit rate to processor clock is too small or too
-    // large then return 0 indicating that no bit rate was set.
-    ASSERT(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR));
-    ASSERT(ui32DesiredRatio >= (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR));
-
-    // Make sure that the Desired Ratio is not too large.  This enforces the
-    // requirement that the bit rate is larger than requested.
-    if((ui32SourceClock / ui32DesiredRatio) > ui32BitRate)
-    {
-        ui32DesiredRatio += 1;
-    }
-
-    // Check all possible values to find a matching value.
-    while(ui32DesiredRatio <= CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)
-    {
-        // Loop through all possible CAN bit divisors.
-        for(ui32CANBits = CAN_MAX_BIT_DIVISOR;
-            ui32CANBits >= CAN_MIN_BIT_DIVISOR;
-            ui32CANBits--)
-        {
-            // For a given CAN bit divisor save the pre divisor.
-            ui32PreDivide = ui32DesiredRatio / ui32CANBits;
-
-            // If the calculated divisors match the desired clock ratio then
-            // return these bit rate and set the CAN bit timing.
-            if((ui32PreDivide * ui32CANBits) == ui32DesiredRatio)
-            {
-                // Start building the bit timing value by adding the bit timing
-                // in time quanta.
-                ui32RegValue =
-                    g_ui16CANBitValues[ui32CANBits - CAN_MIN_BIT_DIVISOR];
-
-                // To set the bit timing register, the controller must be
-                // placed
-                // in init mode (if not already), and also configuration change
-                // bit enabled.  The state of the register should be saved
-                // so it can be restored.
-
-                ui16CANCTL = HWREGH(ui32Base + CAN_O_CTL);
-                HWREGH(ui32Base + CAN_O_CTL) = ui16CANCTL | CAN_CTL_INIT |
-                                               CAN_CTL_CCE;
-
-                // Now add in the pre-scalar on the bit rate.
-                ui32RegValue |= ((ui32PreDivide - 1) & CAN_BTR_BRP_M) |
-                				(((ui32PreDivide - 1) << 10) & CAN_BTR_BRPE_M);
-
-                // Set the clock bits in the and the bits of the
-                // pre-scalar.
-                HWREGH(ui32Base + CAN_O_BTR) = (ui32RegValue &
-                                                CAN_REG_WORD_MASK);
-                HWREGH(ui32Base + CAN_O_BTR + 2) = (ui32RegValue >> 16);
-
-                // Restore the saved CAN Control register.
-                HWREGH(ui32Base + CAN_O_CTL) = ui16CANCTL;
-
-                // Return the computed bit rate.
-                return(ui32SourceClock / ( ui32PreDivide * ui32CANBits));
-            }
-        }
-
-        // Move the divisor up one and look again.  Only in rare cases are
-        // more than 2 loops required to find the value.
-        ui32DesiredRatio++;
-    }
-    return(0);
-}
-
-//*****************************************************************************
-//
-//! Configures the CAN controller bit timing.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param pClkParms points to the structure with the clock parameters.
-//!
-//! Configures the various timing parameters for the CAN bus bit timing:
-//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and
-//! the Synchronization Jump Width.  The values for Propagation and Phase
-//! Buffer 1 segments are derived from the combination
-//! \e pClkParms->uSyncPropPhase1Seg parameter.  Phase Buffer 2 is determined
-//! from the \e pClkParms->uPhase2Seg parameter.  These two parameters, along
-//! with \e pClkParms->uSJW are based in units of bit time quanta.  The actual
-//! quantum time is determined by the \e pClkParms->uQuantumPrescaler value,
-//! which specifies the divisor for the CAN module clock.
-//!
-//! The total bit time, in quanta, will be the sum of the two Seg parameters,
-//! as follows:
-//!
-//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1
-//!
-//! Note that the Sync_Seg is always one quantum in duration, and will be added
-//! to derive the correct duration of Prop_Seg and Phase1_Seg.
-//!
-//! The equation to determine the actual bit rate is as follows:
-//!
-//! CAN Clock /
-//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1) * (\e uQuantumPrescaler))
-//!
-//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1,
-//! \e uQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be
-//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *pClkParms)
-{
-    uint32_t uBitReg;
-    uint16_t uSavedInit;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT(pClkParms != 0);
-
-    // The phase 1 segment must be in the range from 2 to 16.
-    ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) &&
-           (pClkParms->uSyncPropPhase1Seg <= 16));
-
-    // The phase 2 segment must be in the range from 1 to 8.
-    ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8));
-
-    // The synchronous jump windows must be in the range from 1 to 4.
-    ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4));
-
-    // The CAN clock pre-divider must be in the range from 1 to 1024.
-    ASSERT((pClkParms->uQuantumPrescaler <= 1024) &&
-           (pClkParms->uQuantumPrescaler >= 1));
-
-    // To set the bit timing register, the controller must be placed in init
-    // mode (if not already), and also configuration change bit enabled.  State
-    // of the init bit should be saved so it can be restored at the end.
-    uSavedInit = HWREGH(ui32Base + CAN_O_CTL);
-    HWREGH(ui32Base + CAN_O_CTL) = uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE;
-
-    // Set the bit fields of the bit timing register according to the parms.
-    uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BTR_TSEG2_M;
-    uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BTR_TSEG1_M;
-    uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BTR_SJW_M;
-    uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BTR_BRP_M;
-    uBitReg |= ((pClkParms->uQuantumPrescaler - 1) << 10)& CAN_BTR_BRPE_M;
-    HWREGH(ui32Base + CAN_O_BTR) = uBitReg & CAN_REG_WORD_MASK;
-    HWREGH(ui32Base + CAN_O_BTR + 2) = uBitReg >> 16;
-
-    // Clear the config change bit, and restore the init bit.
-    uSavedInit &= ~CAN_CTL_CCE;
-
-    // If Init was not set before, then clear it.
-    if(uSavedInit & CAN_CTL_INIT)
-    {
-        uSavedInit &= ~CAN_CTL_INIT;
-    }
-    HWREGH(ui32Base + CAN_O_CTL) = uSavedInit;
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the CAN controller.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ucIntNumber is the interrupt line to register (0 or 1).
-//! \param pfnHandler is a pointer to the function to be called when the
-//! enabled CAN interrupts occur.
-//!
-//! This function registers the interrupt handler in the interrupt vector
-//! table, and enables CAN interrupts on the interrupt controller; specific CAN
-//! interrupt sources must be enabled using CANIntEnable().  The interrupt
-//! handler being registered must clear the source of the interrupt using
-//! CANIntClear().
-//!
-//! If the application is using a static interrupt vector table stored in
-//! flash, then it is not necessary to register the interrupt handler this way.
-//! Instead, IntEnable() should be used to enable CAN interrupts on the
-//! interrupt controller.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANIntRegister(uint32_t ui32Base, unsigned char ucIntNumber,
-               void (*pfnHandler)(void))
-{
-    uint32_t ui32IntNumber;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    // Get the actual interrupt number for this CAN controller.
-    ui32IntNumber = CANIntNumberGet(ui32Base, ucIntNumber);
-
-    // Register the interrupt handler.
-    IntRegister(ui32IntNumber, pfnHandler);
-
-    // Enable the CAN interrupt.
-    IntEnable(ui32IntNumber);
-}
-
-//*****************************************************************************
-//! Unregisters an interrupt handler for the CAN controller.
-//!
-//! \param ui32Base is the base address of the controller.
-//! \param ucIntNumber is the interrupt line to un-register (0 or 1).
-//!
-//! This function unregisters the previously registered interrupt handler and
-//! disables the interrupt on the interrupt controller.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANIntUnregister(uint32_t ui32Base, unsigned char ucIntNumber)
-{
-    uint32_t ui32IntNumber;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    // Get the actual interrupt number for this CAN controller.
-    ui32IntNumber = CANIntNumberGet(ui32Base, ucIntNumber);
-
-    // Register the interrupt handler.
-    IntUnregister(ui32IntNumber);
-
-    // Disable the CAN interrupt.
-    IntDisable(ui32IntNumber);
-}
-
-//*****************************************************************************
-//
-//! Enables individual CAN controller interrupt sources.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! Enables specific interrupt sources of the CAN controller.  Only enabled
-//! sources will cause a processor interrupt.
-//!
-//! The \e ui32IntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b CAN_INT_ERROR - a controller error condition has occurred
-//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has
-//! been detected
-//! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt
-//! line 0
-//! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt
-//! line 1
-//!
-//! In order to generate status or error interrupts, \b CAN_INT_IE0 must be
-//! enabled.
-//! Further, for any particular transaction from a message object to generate
-//! an interrupt, that message object must have interrupts enabled (see
-//! CANMessageSet()).  \b CAN_INT_ERROR will generate an interrupt if the
-//! controller enters the ``bus off'' condition, or if the error counters reach
-//! a limit.  \b CAN_INT_STATUS will generate an interrupt under quite a few
-//! status conditions and may provide more interrupts than the application
-//! needs to handle.  When an interrupt occurs, use CANIntStatus() to determine
-//! the cause.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32IntFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 |
-                             CAN_INT_IE1)) == 0);
-
-    // Enable the specified interrupts.
-    HWREGH(ui32Base + CAN_O_CTL) = (HWREGH(ui32Base + CAN_O_CTL) |
-                                    (ui32IntFlags & CAN_REG_WORD_MASK));
-
-    HWREGH(ui32Base + CAN_O_CTL + 2) = (HWREGH(ui32Base + CAN_O_CTL + 2) |
-                                        (ui32IntFlags >> 16));
-}
-
-//*****************************************************************************
-//
-//! Disables individual CAN controller interrupt sources.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
-//!
-//! Disables the specified CAN controller interrupt sources.  Only enabled
-//! interrupt sources can cause a processor interrupt.
-//!
-//! The \e ui32IntFlags parameter has the same definition as in the
-//! CANIntEnable() function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32IntFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 |
-                             CAN_INT_IE1)) == 0);
-
-    // Disable the specified interrupts.
-    HWREGH(ui32Base + CAN_O_CTL) = HWREGH(ui32Base + CAN_O_CTL) &
-                                  ~(ui32IntFlags & CAN_REG_WORD_MASK);
-
-    HWREGH(ui32Base + CAN_O_CTL + 2) = HWREGH(ui32Base + CAN_O_CTL + 2) &
-                                       ~(ui32IntFlags >> 16);
-}
-
-//*****************************************************************************
-//
-//! Returns the current CAN controller interrupt status.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param eIntStsReg indicates which interrupt status register to read
-//!
-//! Returns the value of one of two interrupt status registers.  The interrupt
-//! status register read is determined by the \e eIntStsReg parameter, which
-//! can have one of the following values:
-//!
-//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt
-//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message
-//! objects
-//!
-//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register
-//! and indicates the cause of the interrupt.  It will be a value of
-//! \b CAN_INT_INT0ID_STATUS if the cause is a status interrupt.  In this case,
-//! the status register should be read with the CANStatusGet() function.
-//! Calling this function to read the status will also clear the status
-//! interrupt.  If the value of the interrupt register is in the range 1-32,
-//! then this indicates the number of the highest priority message object that
-//! has an interrupt pending.  The message object interrupt can be cleared by
-//! using the CANIntClear() function, or by reading the message using
-//! CANMessageGet() in the case of a received message.  The interrupt handler
-//! can read the interrupt status again to make sure all pending interrupts are
-//! cleared before returning from the interrupt.
-//!
-//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects
-//! have pending interrupts.  This can be used to discover all of the pending
-//! interrupts at once, as opposed to repeatedly reading the interrupt register
-//! by using \b CAN_INT_STS_CAUSE.
-//!
-//! \return Returns the value of one of the interrupt status registers.
-//
-//*****************************************************************************
-uint32_t
-CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg)
-{
-    uint32_t ui32Status;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    // See which status the caller is looking for.
-    switch(eIntStsReg)
-    {
-        // The caller wants the global interrupt status for the CAN controller
-        // specified by ui32Base.
-        case CAN_INT_STS_CAUSE:
-        {
-            ui32Status = HWREG(ui32Base + CAN_O_INT);
-            break;
-        }
-
-        // The caller wants the current message status interrupt for all
-        // messages.
-        case CAN_INT_STS_OBJECT:
-        {
-            // Read message object interrupt status
-            ui32Status = HWREG(ui32Base + CAN_O_IPEN_21);
-            break;
-        }
-
-        // Request was for unknown status so just return 0.
-        default:
-        {
-            ui32Status = 0;
-            break;
-        }
-    }
-    // Return the interrupt status value
-    return(ui32Status);
-}
-
-//*****************************************************************************
-//
-//! Clears a CAN interrupt source.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32IntClr is a value indicating which interrupt source to clear.
-//!
-//! This function can be used to clear a specific interrupt source.  The
-//! \e ui32IntClr parameter should be one of the following values:
-//!
-//! - \b CAN_INT_INTID_STATUS - Clears a status interrupt.
-//! - 1-32 - Clears the specified message object interrupt
-//!
-//! It is not necessary to use this function to clear an interrupt.  This
-//! should only be used if the application wants to clear an interrupt source
-//! without taking the normal interrupt action.
-//!
-//! Normally, the status interrupt is cleared by reading the controller status
-//! using CANStatusGet().  A specific message object interrupt is normally
-//! cleared by reading the message object using CANMessageGet().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32IntClr == CAN_INT_INT0ID_STATUS) ||
-           ((ui32IntClr>=1) && (ui32IntClr <=32)));
-
-    if(ui32IntClr == CAN_INT_INT0ID_STATUS)
-    {
-        // Simply read and discard the status to clear the interrupt.
-        HWREG(ui32Base + CAN_O_ES);
-    }
-    else
-    {
-        // Wait to be sure that this interface is not busy.
-        while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY)
-        {
-        }
-
-        // Only change the interrupt pending state by setting only the
-        // CAN_IF1CMD_CLRINTPND bit.
-        HWREGH(ui32Base + CAN_O_IF1CMD + 2) = CAN_IF1CMD_CLRINTPND >> 16;
-
-        // Send the clear pending interrupt command to the CAN controller.
-        HWREGH(ui32Base + CAN_O_IF1CMD) = ui32IntClr & CAN_IF1CMD_MSG_NUM_M;
-
-        // Wait to be sure that this interface is not busy.
-        while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY)
-        {
-        }
-    }
-}
-
-//*****************************************************************************
-//
-//! Sets the CAN controller automatic retransmission behavior.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param bAutoRetry enables automatic retransmission.
-//!
-//! Enables or disables automatic retransmission of messages with detected
-//! errors.  If \e bAutoRetry is \b true, then automatic retransmission is
-//! enabled, otherwise it is disabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANRetrySet(uint32_t ui32Base, bool bAutoRetry)
-{
-    uint16_t ui16CtlReg;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    ui16CtlReg = HWREGH(ui32Base + CAN_O_CTL);
-
-    // Conditionally set the DAR bit to enable/disable auto-retry.
-    if(bAutoRetry)
-    {
-        // Clearing the DAR bit tells the controller to not disable the
-        // auto-retry of messages which were not transmitted or received
-        // correctly.
-        ui16CtlReg &= ~CAN_CTL_DAR;
-    }
-    else
-    {
-        // Setting the DAR bit tells the controller to disable the auto-retry
-        // of messages which were not transmitted or received correctly.
-        ui16CtlReg |= CAN_CTL_DAR;
-    }
-
-    HWREGH(ui32Base + CAN_O_CTL) = ui16CtlReg;
-}
-
-//*****************************************************************************
-//
-//! Returns the current setting for automatic retransmission.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//!
-//! Reads the current setting for the automatic retransmission in the CAN
-//! controller and returns it to the caller.
-//!
-//! \return Returns \b true if automatic retransmission is enabled, \b false
-//! otherwise.
-//
-//*****************************************************************************
-bool
-CANRetryGet(uint32_t ui32Base)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    // Read the disable automatic retry setting from the CAN controller.
-    if(HWREGH(ui32Base + CAN_O_CTL) & CAN_CTL_DAR)
-    {
-        // Automatic data retransmission is not enabled.
-        return(false);
-    }
-
-    // Automatic data retransmission is enabled.
-    return(true);
-}
-
-//*****************************************************************************
-//
-//! Reads one of the controller status registers.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param eStatusReg is the status register to read.
-//!
-//! Reads a status register of the CAN controller and returns it to the caller.
-//! The different status registers are:
-//!
-//! - \b CAN_STS_CONTROL - the main controller status
-//! - \b CAN_STS_TXREQUEST - bit mask of objects pending transmission
-//! - \b CAN_STS_NEWDAT - bit mask of objects with new data
-//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration
-//!
-//! When reading the main controller status register, a pending status
-//! interrupt will be cleared.  This should be used in the interrupt handler
-//! for the CAN controller if the cause is a status interrupt.  The controller
-//! status register fields are as follows:
-//!
-//! - \b CAN_STATUS_PDA - controller in local power down mode
-//! - \b CAN_STATUS_WAKE_UP - controller initiated system wake up
-//! - \b CAN_STATUS_PERR - parity error detected
-//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition
-//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96
-//! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state
-//! - \b CAN_STATUS_RXOK - a message was received successfully (independent of
-//! any message filtering).
-//! - \b CAN_STATUS_TXOK - a message was successfully transmitted
-//! - \b CAN_STATUS_LEC_NONE - no error
-//! - \b CAN_STATUS_LEC_STUFF - stuffing error detected
-//! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part
-//! of a message
-//! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged
-//! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in
-//! recessive mode
-//! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in
-//! dominant mode
-//! - \b CAN_STATUS_LEC_CRC - CRC error in received message
-//!
-//! The remaining status registers are 32-bit bit maps to the message objects.
-//! They can be used to quickly obtain information about the status of all the
-//! message objects without needing to query each one.  They contain the
-//! following information:
-//!
-//! - \b CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that
-//! means that a transmission is pending on that object.  The application can
-//! use this to determine which objects are still waiting to send a message.
-//! - \b CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means
-//! that a new message has been received in that object, and has not yet been
-//! picked up by the host application
-//! - \b CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means
-//! it has a valid configuration programmed.  The host application can use this
-//! to determine which message objects are empty/unused.
-//!
-//! \return Returns the value of the status register.
-//
-//*****************************************************************************
-uint32_t
-CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg)
-{
-    uint32_t ui32Status;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    switch(eStatusReg)
-    {
-        // Just return the global CAN status register since that is what was
-        // requested.
-        case CAN_STS_CONTROL:
-        {
-            ui32Status = HWREG(ui32Base + CAN_O_ES);
-            break;
-        }
-
-        // Return objects with valid transmit requests
-        case CAN_STS_TXREQUEST:
-        {
-            ui32Status = HWREG(ui32Base + CAN_O_TXRQ_21);
-            break;
-        }
-
-        // Return messages objects with new data
-        case CAN_STS_NEWDAT:
-        {
-            ui32Status = HWREG(ui32Base + CAN_O_NDAT_21);
-            break;
-        }
-
-        // Return valid message objects
-        case CAN_STS_MSGVAL:
-        {
-            ui32Status = HWREG(ui32Base + CAN_O_MVAL_21);
-            break;
-        }
-
-        // Unknown CAN status requested so return 0.
-        default:
-        {
-            ui32Status = 0;
-            break;
-        }
-    }
-    return(ui32Status);
-}
-
-//*****************************************************************************
-//
-//! Reads the CAN controller error counter register.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param pui32RxCount is a pointer to storage for the receive error counter.
-//! \param pui32TxCount is a pointer to storage for the transmit error counter.
-//!
-//! Reads the error counter register and returns the transmit and receive error
-//! counts to the caller along with a flag indicating if the controller receive
-//! counter has reached the error passive limit.  The values of the receive and
-//! transmit error counters are returned through the pointers provided as
-//! parameters.
-//!
-//! After this call, \e *pui32RxCount will hold the current receive error count
-//! and \e *pui32TxCount will hold the current transmit error count.
-//!
-//! \return Returns \b true if the receive error count has reached the error
-//! passive limit, and \b false if the error count is below the error passive
-//! limit.
-//
-//*****************************************************************************
-bool
-CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
-              uint32_t *pui32TxCount)
-{
-    uint16_t ui16CANError;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-
-    // Read the current count of transmit/receive errors.
-    ui16CANError = HWREGH(ui32Base + CAN_O_ERRC);
-
-    // Extract the error numbers from the register value.
-    *pui32RxCount = (ui16CANError & CAN_ERRC_REC_M) >> CAN_ERRC_REC_S;
-    *pui32TxCount = (ui16CANError & CAN_ERRC_TEC_M) >> CAN_ERRC_TEC_S;
-
-    if(ui16CANError & CAN_ERRC_RP)
-    {
-        return(true);
-    }
-
-    return(false);
-}
-
-//*****************************************************************************
-//
-//! Configures a message object in the CAN controller.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32ObjID is the object number to configure (1-32).
-//! \param pMsgObject is a pointer to a structure containing message object
-//! settings.
-//! \param eMsgType indicates the type of message for this object.
-//!
-//! This function is used to configure any one of the 32 message objects in the
-//! CAN controller.  A message object can be configured as any type of CAN
-//! message object as well as several options for automatic transmission and
-//! reception.  This call also allows the message object to be configured to
-//! generate interrupts on completion of message receipt or transmission.  The
-//! message object can also be configured with a filter/mask so that actions
-//! are only taken when a message that meets certain parameters is seen on the
-//! CAN bus.
-//!
-//! The \e eMsgType parameter must be one of the following values:
-//!
-//! - \b MSG_OBJ_TYPE_TX - CAN transmit message object.
-//! - \b MSG_OBJ_TYPE_TX_REMOTE - CAN transmit remote request message object.
-//! - \b MSG_OBJ_TYPE_RX - CAN receive message object.
-//! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object.
-//! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then
-//! transmit message object.
-//!
-//! The message object pointed to by \e pMsgObject must be populated by the
-//! caller, as follows:
-//!
-//! - \e ui32MsgID - contains the message ID, either 11 or 29 bits.
-//! - \e ui32MsgIDMask - mask of bits from \e ui32MsgID that must match if
-//! identifier filtering is enabled.
-//! - \e ui32Flags
-//!   - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission.
-//!   - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt.
-//!   - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the
-//!   identifier mask specified by \e ui32MsgIDMask.
-//! - \e ui32MsgLen - the number of bytes in the message data.  This should be
-//! non-zero even for a remote frame; it should match the expected bytes of the
-//! data responding data frame.
-//! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a
-//! data frame.
-//!
-//! \b Example: To send a data frame or remote frame(in response to a remote
-//! request), take the following steps:
-//!
-//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX.
-//! -# Set \e pMsgObject->ui32MsgID to the message ID.
-//! -# Set \e pMsgObject->ui32Flags. Make sure to set \b MSG_OBJ_TX_INT_ENABLE to
-//! allow an interrupt to be generated when the message is sent.
-//! -# Set \e pMsgObject->ui32MsgLen to the number of bytes in the data frame.
-//! -# Set \e pMsgObject->pucMsgData to point to an array containing the bytes
-//! to send in the message.
-//! -# Call this function with \e ui32ObjID set to one of the 32 object buffers.
-//!
-//! \b Example: To receive a specific data frame, take the following steps:
-//!
-//! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX.
-//! -# Set \e pMsgObject->ui32MsgID to the full message ID, or a partial mask to
-//! use partial ID matching.
-//! -# Set \e pMsgObject->ui32MsgIDMask bits that should be used for masking
-//! during comparison.
-//! -# Set \e pMsgObject->ui32Flags as follows:
-//!   - Set \b MSG_OBJ_TX_INT_ENABLE flag to be interrupted when the data frame
-//!   is received.
-//!   - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering.
-//! -# Set \e pMsgObject->ui32MsgLen to the number of bytes in the expected data
-//! frame.
-//! -# The buffer pointed to by \e pMsgObject->pucMsgData  and
-//! \e pMsgObject->ui32MsgLen are not used by this call as no data is present at
-//! the time of the call.
-//! -# Call this function with \e ui32ObjID set to one of the 32 object buffers.
-//!
-//! If you specify a message object buffer that already contains a message
-//! definition, it will be overwritten.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, tCANMsgObject *pMsgObject,
-              tMsgObjType eMsgType)
-{
-    uint32_t ui32CmdMaskReg;
-    uint32_t ui32MaskReg;
-    uint32_t ui32ArbReg;
-    uint32_t ui32MsgCtrl;
-    bool bTransferData;
-    bool bUseExtendedID;
-
-    bTransferData = 0;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0));
-    ASSERT((eMsgType == MSG_OBJ_TYPE_TX) ||
-           (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) ||
-           (eMsgType == MSG_OBJ_TYPE_RX) ||
-           (eMsgType == MSG_OBJ_TYPE_RX_REMOTE) ||
-           (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) ||
-           (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE));
-
-    // Wait for busy bit to clear
-    while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY)
-    {
-    }
-
-    // See if we need to use an extended identifier or not.
-    if((pMsgObject->ui32MsgID > CAN_MAX_11BIT_MSG_ID) ||
-       (pMsgObject->ui32Flags & MSG_OBJ_EXTENDED_ID))
-    {
-        bUseExtendedID = 1;
-    }
-    else
-    {
-        bUseExtendedID = 0;
-    }
-
-    // This is always a write to the Message object as this call is setting a
-    // message object.  This call will also always set all size bits so it sets
-    // both data bits.  The call will use the CONTROL register to set control
-    // bits so this bit needs to be set as well.
-    ui32CmdMaskReg = (CAN_IF1CMD_DIR | CAN_IF1CMD_DATA_A | CAN_IF1CMD_DATA_B |
-                      CAN_IF1CMD_CONTROL);
-
-    // Initialize the values to a known state before filling them in based on
-    // the type of message object that is being configured.
-    ui32ArbReg = 0;
-    ui32MsgCtrl = 0;
-    ui32MaskReg = 0;
-
-    switch(eMsgType)
-    {
-    // Transmit message object.
-    case MSG_OBJ_TYPE_TX:
-    {
-        // Set the TXRQST bit and the reset the rest of the register.
-        ui32MsgCtrl |= CAN_IF1MCTL_TXRQST;
-        ui32ArbReg = CAN_IF1ARB_DIR;
-        bTransferData = 1;
-        break;
-    }
-
-    // Transmit remote request message object
-    case MSG_OBJ_TYPE_TX_REMOTE:
-    {
-        // Set the TXRQST bit and the reset the rest of the register.
-        ui32MsgCtrl |= CAN_IF1MCTL_TXRQST;
-        ui32ArbReg = 0;
-        break;
-    }
-
-    // Receive message object.
-    case MSG_OBJ_TYPE_RX:
-    {
-        // This clears the DIR bit along with everything else.  The TXRQST
-        // bit was cleared by defaulting ui32MsgCtrl to 0.
-        ui32ArbReg = 0;
-        break;
-    }
-
-    // Receive remote request message object.
-    case MSG_OBJ_TYPE_RX_REMOTE:
-    {
-        // The DIR bit is set to one for remote receivers.  The TXRQST bit
-        // was cleared by defaulting ui32MsgCtrl to 0.
-        ui32ArbReg = CAN_IF1ARB_DIR;
-
-        // Set this object so that it only indicates that a remote frame
-        // was received and allow for software to handle it by sending back
-        // a data frame.
-        ui32MsgCtrl = CAN_IF1MCTL_UMASK;
-
-        // Use the full Identifier by default.
-        ui32MaskReg = CAN_IF1MSK_MSK_M;
-
-        // Make sure to send the mask to the message object.
-        ui32CmdMaskReg |= CAN_IF1CMD_MASK;
-        break;
-    }
-
-    // Remote frame receive remote, with auto-transmit message object.
-    case MSG_OBJ_TYPE_RXTX_REMOTE:
-    {
-        // Oddly the DIR bit is set to one for remote receivers.
-        ui32ArbReg = CAN_IF1ARB_DIR;
-
-        // Set this object to auto answer if a matching identifier is seen.
-        ui32MsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK;
-
-        // The data to be returned needs to be filled in.
-        bTransferData = 1;
-        break;
-    }
-
-    // This case should never happen due to the ASSERT statement at the
-    // beginning of this function.
-    default:
-    {
-        return;
-    }
-    }
-
-    // Configure the Mask Registers.
-    if(pMsgObject->ui32Flags & MSG_OBJ_USE_ID_FILTER)
-    {
-        if(bUseExtendedID)
-        {
-            // Set the 29 bits of Identifier mask that were requested.
-            ui32MaskReg = pMsgObject->ui32MsgIDMask & CAN_IF1MSK_MSK_M;
-        }
-        else
-        {
-
-            // Put the 11 bit Mask Identifier into the upper bits of the field
-            // in the register.
-            ui32MaskReg = ((pMsgObject->ui32MsgIDMask << CAN_IF1ARB_STD_ID_S) &
-                           CAN_IF1ARB_STD_ID_M);
-        }
-    }
-
-    // If the caller wants to filter on the extended ID bit then set it.
-    if((pMsgObject->ui32Flags & MSG_OBJ_USE_EXT_FILTER) ==
-       MSG_OBJ_USE_EXT_FILTER)
-    {
-        ui32MaskReg |= CAN_IF1MSK_MXTD;
-    }
-
-    // The caller wants to filter on the message direction field.
-    if((pMsgObject->ui32Flags & MSG_OBJ_USE_DIR_FILTER) ==
-       MSG_OBJ_USE_DIR_FILTER)
-    {
-        ui32MaskReg |= CAN_IF1MSK_MDIR;
-    }
-
-    if(pMsgObject->ui32Flags & (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER |
-                              MSG_OBJ_USE_EXT_FILTER))
-    {
-        // Set the UMASK bit to enable using the mask register.
-        ui32MsgCtrl |= CAN_IF1MCTL_UMASK;
-
-        // Set the MASK bit so that this gets transferred to the Message
-        // Object.
-        ui32CmdMaskReg |= CAN_IF1CMD_MASK;
-    }
-
-    // Set the Arb bit so that this gets transferred to the Message object.
-    ui32CmdMaskReg |= CAN_IF1CMD_ARB;
-
-    // Configure the Arbitration registers.
-    if(bUseExtendedID)
-    {
-        // Set the 29 bit version of the Identifier for this message object.
-        // Mark the message as valid and set the extended ID bit.
-        ui32ArbReg |= (pMsgObject->ui32MsgID & CAN_IF1ARB_ID_M) |
-                      CAN_IF1ARB_MSGVAL | CAN_IF1ARB_XTD;
-    }
-    else
-    {
-        // Set the 11 bit version of the Identifier for this message object.
-        // The lower 18 bits are set to zero.
-        // Mark the message as valid.
-        ui32ArbReg |= ((pMsgObject->ui32MsgID << CAN_IF1ARB_STD_ID_S) &
-                       CAN_IF1ARB_STD_ID_M) | CAN_IF1ARB_MSGVAL;
-    }
-
-    // Set the data length since this is set for all transfers.  This is also a
-    // single transfer and not a FIFO transfer so set EOB bit.
-    ui32MsgCtrl |= (pMsgObject->ui32MsgLen & CAN_IF1MCTL_DLC_M);
-
-    // Mark this as the last entry if this is not the last entry in a FIFO.
-    if((pMsgObject->ui32Flags & MSG_OBJ_FIFO) == 0)
-    {
-        ui32MsgCtrl |= CAN_IF1MCTL_EOB;
-    }
-
-    // Enable transmit interrupts if they should be enabled.
-    if(pMsgObject->ui32Flags & MSG_OBJ_TX_INT_ENABLE)
-    {
-        ui32MsgCtrl |= CAN_IF1MCTL_TXIE;
-    }
-
-    // Enable receive interrupts if they should be enabled.
-    if(pMsgObject->ui32Flags & MSG_OBJ_RX_INT_ENABLE)
-    {
-        ui32MsgCtrl |= CAN_IF1MCTL_RXIE;
-    }
-
-    // Write the data out to the CAN Data registers if needed.
-    if(bTransferData)
-    {
-        CANDataRegWrite(pMsgObject->pucMsgData,
-                        (uint32_t *)(ui32Base + CAN_O_IF1DATA),
-                        pMsgObject->ui32MsgLen);
-    }
-
-    // Write out the registers to program the message object.
-    HWREGH(ui32Base + CAN_O_IF1CMD + 2) = ui32CmdMaskReg >> 16;
-
-    HWREGH(ui32Base + CAN_O_IF1MSK) = ui32MaskReg & CAN_REG_WORD_MASK;
-    HWREGH(ui32Base + CAN_O_IF1MSK + 2) = ui32MaskReg >> 16;
-
-    HWREGH(ui32Base + CAN_O_IF1ARB) = ui32ArbReg & CAN_REG_WORD_MASK;
-    HWREGH(ui32Base + CAN_O_IF1ARB + 2) = ui32ArbReg >> 16;
-
-    HWREGH(ui32Base + CAN_O_IF1MCTL) = ui32MsgCtrl & CAN_REG_WORD_MASK;
-
-    // Transfer the message object to the message object specific by ui32ObjID.
-    HWREGH(ui32Base + CAN_O_IF1CMD) = ui32ObjID & CAN_IF1CMD_MSG_NUM_M;
-
-    return;
-}
-
-//*****************************************************************************
-//
-//! Reads a CAN message from one of the message object buffers.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32ObjID is the object number to read (1-32).
-//! \param pMsgObject points to a structure containing message object fields.
-//! \param bClrPendingInt indicates whether an associated interrupt should be
-//! cleared.
-//!
-//! This function is used to read the contents of one of the 32 message objects
-//! in the CAN controller, and return it to the caller.  The data returned is
-//! stored in the fields of the caller-supplied structure pointed to by
-//! \e pMsgObject.  The data consists of all of the parts of a CAN message,
-//! plus some control and status information.
-//!
-//! Normally this is used to read a message object that has received and stored
-//! a CAN message with a certain identifier.  However, this could also be used
-//! to read the contents of a message object in order to load the fields of the
-//! structure in case only part of the structure needs to be changed from a
-//! previous setting.
-//!
-//! When using CANMessageGet, all of the same fields of the structure are
-//! populated in the same way as when the CANMessageSet() function is used,
-//! with the following exceptions:
-//!
-//! \e pMsgObject->ui32Flags:
-//!
-//! - \b MSG_OBJ_NEW_DATA indicates if this is new data since the last time it
-//! was read
-//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on
-//! this message object, and not read by the host before being overwritten.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, tCANMsgObject *pMsgObject,
-              bool bClrPendingInt)
-{
-    uint32_t ui32CmdMaskReg;
-    uint32_t ui32MaskReg;
-    uint32_t ui32ArbReg;
-    uint32_t ui32MsgCtrl;
-
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0));
-
-    // This is always a read to the Message object as this call is setting a
-    // message object.
-    ui32CmdMaskReg = (CAN_IF2CMD_DATA_A | CAN_IF2CMD_DATA_B |
-                      CAN_IF2CMD_CONTROL | CAN_IF2CMD_MASK | CAN_IF2CMD_ARB);
-
-    // Clear a pending interrupt and new data in a message object.
-    if(bClrPendingInt)
-    {
-        ui32CmdMaskReg |= CAN_IF2CMD_CLRINTPND | CAN_IF2CMD_TXRQST;
-    }
-
-    // Set up the request for data from the message object.
-    HWREGH(ui32Base + CAN_O_IF2CMD + 2) =  ui32CmdMaskReg >> 16;
-
-    // Transfer the message object to the message object specified by ui32ObjID.
-    HWREGH(ui32Base + CAN_O_IF2CMD) = ui32ObjID & CAN_IF2CMD_MSG_NUM_M;
-
-    // Wait for busy bit to clear
-    while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY)
-    {
-    }
-
-    // Read out the IF Registers.
-    ui32MaskReg = HWREG(ui32Base + CAN_O_IF2MSK);
-    ui32ArbReg = HWREG(ui32Base + CAN_O_IF2ARB);
-    ui32MsgCtrl = HWREG(ui32Base + CAN_O_IF2MCTL);
-    pMsgObject->ui32Flags = MSG_OBJ_NO_FLAGS;
-
-    // Determine if this is a remote frame by checking the TXRQST and DIR bits.
-    if((!(ui32MsgCtrl & CAN_IF2MCTL_TXRQST) && (ui32ArbReg & CAN_IF2ARB_DIR)) ||
-       ((ui32MsgCtrl & CAN_IF2MCTL_TXRQST) && (!(ui32ArbReg & CAN_IF2ARB_DIR))))
-    {
-        pMsgObject->ui32Flags |= MSG_OBJ_REMOTE_FRAME;
-    }
-
-    // Get the identifier out of the register, the format depends on size of
-    // the mask.
-    if(ui32ArbReg & CAN_IF2ARB_XTD)
-    {
-        // Set the 29 bit version of the Identifier for this message object.
-        pMsgObject->ui32MsgID = ui32ArbReg & CAN_IF2ARB_ID_M;
-
-        pMsgObject->ui32Flags |= MSG_OBJ_EXTENDED_ID;
-    }
-    else
-    {
-        // The Identifier is an 11 bit value.
-        pMsgObject->ui32MsgID = (ui32ArbReg &
-                                 CAN_IF2ARB_STD_ID_M) >> CAN_IF2ARB_STD_ID_S;
-    }
-
-    // Indicate that we lost some data.
-    if(ui32MsgCtrl & CAN_IF2MCTL_MSGLST)
-    {
-        pMsgObject->ui32Flags |= MSG_OBJ_DATA_LOST;
-    }
-
-    // Set the flag to indicate if ID masking was used.
-    if(ui32MsgCtrl & CAN_IF2MCTL_UMASK)
-    {
-        if(ui32ArbReg & CAN_IF2ARB_XTD)
-        {
-            // The Identifier Mask is assumed to also be a 29 bit value.
-            pMsgObject->ui32MsgIDMask = (ui32MaskReg & CAN_IF2MSK_MSK_M);
-
-            // If this is a fully specified Mask and a remote frame then don't
-            // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
-            // filtered.
-            if((pMsgObject->ui32MsgIDMask != 0x1fffffff) ||
-               ((pMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0))
-            {
-                pMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER;
-            }
-        }
-        else
-        {
-            // The Identifier Mask is assumed to also be an 11 bit value.
-            pMsgObject->ui32MsgIDMask = ((ui32MaskReg & CAN_IF2MSK_MSK_M) >>
-                                         18);
-
-            // If this is a fully specified Mask and a remote frame then don't
-            // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
-            // filtered.
-            if((pMsgObject->ui32MsgIDMask != 0x7ff) ||
-               ((pMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0))
-            {
-                pMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER;
-            }
-        }
-
-        // Indicate if the extended bit was used in filtering.
-        if(ui32MaskReg & CAN_IF2MSK_MXTD)
-        {
-            pMsgObject->ui32Flags |= MSG_OBJ_USE_EXT_FILTER;
-        }
-
-        // Indicate if direction filtering was enabled.
-        if(ui32MaskReg & CAN_IF2MSK_MDIR)
-        {
-            pMsgObject->ui32Flags |= MSG_OBJ_USE_DIR_FILTER;
-        }
-    }
-
-    // Set the interrupt flags.
-    if(ui32MsgCtrl & CAN_IF2MCTL_TXIE)
-    {
-        pMsgObject->ui32Flags |= MSG_OBJ_TX_INT_ENABLE;
-    }
-    if(ui32MsgCtrl & CAN_IF2MCTL_RXIE)
-    {
-        pMsgObject->ui32Flags |= MSG_OBJ_RX_INT_ENABLE;
-    }
-
-    // See if there is new data available.
-    if(ui32MsgCtrl & CAN_IF2MCTL_NEWDAT)
-    {
-        // Get the amount of data needed to be read.
-        pMsgObject->ui32MsgLen = (ui32MsgCtrl & CAN_IF2MCTL_DLC_M);
-
-        // Don't read any data for a remote frame, there is nothing valid in
-        // that buffer anyway.
-        if((pMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)
-        {
-            // Read out the data from the CAN registers.
-            CANDataRegRead(pMsgObject->pucMsgData,
-                           (uint32_t *)(ui32Base + CAN_O_IF2DATA),
-                           pMsgObject->ui32MsgLen);
-        }
-
-        // Now clear out the new data flag.
-        HWREGH(ui32Base + CAN_O_IF2CMD + 2) = CAN_IF2CMD_TXRQST >> 16;
-
-        // Transfer the message object to the message object specified by
-        // ui32ObjID.
-        HWREGH(ui32Base + CAN_O_IF2CMD) = ui32ObjID & CAN_IF2CMD_MSG_NUM_M;
-
-        // Wait for busy bit to clear
-        while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY)
-        {
-        }
-
-        // Indicate that there is new data in this message.
-        pMsgObject->ui32Flags |= MSG_OBJ_NEW_DATA;
-    }
-    else
-    {
-        // Along with the MSG_OBJ_NEW_DATA not being set the amount of data
-        // needs to be set to zero if none was available.
-        pMsgObject->ui32MsgLen = 0;
-    }
-}
-
-//*****************************************************************************
-//
-//! Clears a message object so that it is no longer used.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32ObjID is the message object number to disable (1-32).
-//!
-//! This function frees the specified message object from use.  Once a message
-//! object has been ``cleared,'' it will no longer automatically send or
-//! receive messages, or generate interrupts.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32ObjID >= 1) && (ui32ObjID <= 32));
-
-    // Wait for busy bit to clear
-    while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY)
-    {
-    }
-
-    // Clear the message value bit in the arbitration register. This indicates
-    // the message is not valid.
-    HWREGH(ui32Base + CAN_O_IF1CMD + 2) = (CAN_IF1CMD_DIR |
-                                           CAN_IF1CMD_ARB) >> 16;
-    HWREGH(ui32Base + CAN_O_IF1ARB) = 0;
-    HWREGH(ui32Base + CAN_O_IF1ARB + 2) = 0;
-
-    // Initiate programming the message object
-    HWREGH(ui32Base + CAN_O_IF1CMD) = ui32ObjID & CAN_IF1CMD_MSG_NUM_M;
-}
-
-//*****************************************************************************
-//
-//! CAN Global interrupt Enable function.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! Enables specific CAN interrupt in the global interrupt enable register
-//!
-//! The \e ui32IntFlags parameter is the logical OR of any of the following:
-//!
-//! CAN_GLB_INT_CANINT0   -Global Interrupt Enable bit for CAN INT0
-//! CAN_GLB_INT_CANINT1   -Global Interrupt Enable bit for CAN INT1
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANGlobalIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 |
-                             CAN_GLB_INT_CANINT1)) == 0);
-
-    //enable the requested interrupts
-    HWREGH(ui32Base + CAN_O_GLB_INT_EN) |= ui32IntFlags;
-}
-
-//*****************************************************************************
-//
-//! CAN Global interrupt Disable function.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! Disables the specific CAN interrupt in the global interrupt enable register
-//!
-//! The \e ui32IntFlags parameter is the logical OR of any of the following:
-//!
-//! CAN_GLB_INT_CANINT0   -Global Interrupt bit for CAN INT0
-//! CAN_GLB_INT_CANINT1   -Global Interrupt bit for CAN INT1
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANGlobalIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 |
-                             CAN_GLB_INT_CANINT1)) == 0);
-
-    //disable the requested interrupts
-    HWREGH(ui32Base + CAN_O_GLB_INT_EN) &= ~ui32IntFlags;
-}
-
-//*****************************************************************************
-//
-//! CAN Global interrupt Clear function.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! Clear the specific CAN interrupt bit in the global interrupt flag register.
-//!
-//! The \e ui32IntFlags parameter is the logical OR of any of the following:
-//!
-//! CAN_GLB_INT_CANINT0   -Global Interrupt bit for CAN INT0
-//! CAN_GLB_INT_CANINT1   -Global Interrupt bit for CAN INT1
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CANGlobalIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 |
-                             CAN_GLB_INT_CANINT1)) == 0);
-
-    //clear the requested interrupts
-    HWREGH(ui32Base + CAN_O_GLB_INT_CLR) = ui32IntFlags;
-}
-
-//*****************************************************************************
-//
-//! CAN Global interrupt Status function.
-//!
-//! \param ui32Base is the base address of the CAN controller.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be checked.
-//!
-//! Get the status of the specific CAN interrupt bits in the global interrupt
-//! flag register.
-//!
-//! The \e ui32IntFlags parameter is the logical OR of any of the following:
-//!
-//! CAN_GLB_INT_CANINT0   -Global Interrupt bit for CAN INT0
-//! CAN_GLB_INT_CANINT1   -Global Interrupt bit for CAN INT1
-//!
-//! \return True if any of the requested interrupt bit(s) is (are) set.
-//
-//*****************************************************************************
-bool
-CANGlobalIntstatusGet(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    // Check the arguments.
-    ASSERT(CANBaseValid(ui32Base));
-    ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 |
-                             CAN_GLB_INT_CANINT1)) == 0);
-
-    //enable the requested interrupts
-    if(HWREGH(ui32Base + CAN_O_GLB_INT_FLG) & ui32IntFlags)
-    {
-        return true;
-    }
-    else
-    {
-        return false;
-    }
-}
-
-//*****************************************************************************
-// Close the Doxygen group.
-//! @}
-//*****************************************************************************
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.h
deleted file mode 100644
index 471d1fcc6d..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.h
+++ /dev/null
@@ -1,415 +0,0 @@
-//###########################################################################
-//
-// FILE:   can.h
-//
-// TITLE:  Defines and Macros for the CAN controller.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __CAN_H__
-#define __CAN_H__
-
-//*****************************************************************************
-//! \addtogroup can_api
-//! @{
-//*****************************************************************************
-
-//*****************************************************************************
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-#define CAN_INDEX_TO_BASE(idx)             ((idx == 0) ? CAN_A_BASE : CAN_B_BASE)
-
-#define CAN_INDEX_TO_MSG_RAM_BASE(idx)     ((idx == 0) ? CAN_A_MSG_RAM : CAN_B_MSG_RAM)
-
-#define CAN_REG_WORD_MASK                  (0xFFFFU)
-
-//****************************************************************************
-//   These are the Defines to select CAN pin muxing when calling the functions
-//  ConfigCanPinMuxing(), ConfigGpioCanA() & ConfigGpioCanB() in F2837x_Can.c
-//****************************************************************************
-#define CAN_A_GPIO4_GPIO5       1   //switch case 1
-#define CAN_A_GPIO19_GPIO18     2   //switch case 2
-#define CAN_A_GPIO31_GPIO30     3   //switch case 3
-#define CAN_A_GPIO37_GPIO36     4   //switch case 4
-#define CAN_A_GPIO63_GPIO62     5   //switch case 5
-#define CAN_A_GPIO71_GPIO70     6   //switch case 6
-
-#define CAN_B_GPIO6_GPIO7       1   //switch case 1
-#define CAN_B_GPIO8_GPIO10      2   //switch case 2
-#define CAN_B_GPIO12_GPIO13     3   //switch case 3
-#define CAN_B_GPIO16_GPIO17     4   //switch case 4
-#define CAN_B_GPIO20_GPIO21     5   //switch case 5
-#define CAN_B_GPIO38_GPIO39     6   //switch case 6
-#define CAN_B_GPIO72_GPIO73     7   //switch case 7
-
-//*****************************************************************************
-// Miscellaneous defines for Message ID Types
-//*****************************************************************************
-
-//*****************************************************************************
-// These are the flags used by the tCANMsgObject.ui32Flags value when calling the
-// CANMessageSet() and CANMessageGet() functions.
-//*****************************************************************************
-
-//! This definition is used with the tCANMsgObject ui32Flags value and indicates
-//! that transmit interrupts should be enabled, or are enabled.
-#define MSG_OBJ_TX_INT_ENABLE           0x00000001
-
-//! This indicates that receive interrupts should be enabled, or are
-//! enabled.
-#define MSG_OBJ_RX_INT_ENABLE           0x00000002
-
-//! This indicates that a message object will use or is using an extended
-//! identifier.
-#define MSG_OBJ_EXTENDED_ID             0x00000004
-
-//! This indicates that a message object will use or is using filtering
-//! based on the object's message identifier.
-#define MSG_OBJ_USE_ID_FILTER           0x00000008
-
-//! This indicates that new data was available in the message object.
-#define MSG_OBJ_NEW_DATA                0x00000080
-
-//! This indicates that data was lost since this message object was last
-//! read.
-#define MSG_OBJ_DATA_LOST               0x00000100
-
-//! This indicates that a message object will use or is using filtering
-//! based on the direction of the transfer.  If the direction filtering is
-//! used, then ID filtering must also be enabled.
-#define MSG_OBJ_USE_DIR_FILTER          (0x00000010 | MSG_OBJ_USE_ID_FILTER)
-
-//! This indicates that a message object will use or is using message
-//! identifier filtering based on the extended identifier.  If the extended
-//! identifier filtering is used, then ID filtering must also be enabled.
-#define MSG_OBJ_USE_EXT_FILTER          (0x00000020 | MSG_OBJ_USE_ID_FILTER)
-
-//! This indicates that a message object is a remote frame.
-#define MSG_OBJ_REMOTE_FRAME            0x00000040
-
-//! This indicates that this message object is part of a FIFO structure and
-//! not the final message object in a FIFO.
-#define MSG_OBJ_FIFO                    0x00000200
-
-//! This indicates that a message object has no flags set.
-#define MSG_OBJ_NO_FLAGS                0x00000000
-
-//*****************************************************************************
-//! This define is used with the flag values to allow checking only status
-//! flags and not configuration flags.
-//*****************************************************************************
-#define MSG_OBJ_STATUS_MASK             (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
-
-//*****************************************************************************
-//! The structure used for encapsulating all the items associated with a CAN
-//! message object in the CAN controller.
-//*****************************************************************************
-typedef struct
-{
-        //! The CAN message identifier used for 11 or 29 bit identifiers.
-        uint32_t ui32MsgID;
-
-        //! The message identifier mask used when identifier filtering is enabled.
-        uint32_t ui32MsgIDMask;
-
-        //! This value holds various status flags and settings specified by
-        //! tCANObjFlags.
-        uint32_t ui32Flags;
-
-        //! This value is the number of bytes of data in the message object.
-        uint32_t ui32MsgLen;
-
-        //! This is a pointer to the message object's data.
-        unsigned char *pucMsgData;
-}
-tCANMsgObject;
-
-//*****************************************************************************
-//! This structure is used for encapsulating the values associated with setting
-//! up the bit timing for a CAN controller.  The structure is used when calling
-//! the CANGetBitTiming and CANSetBitTiming functions.
-//*****************************************************************************
-typedef struct
-{
-        //! This value holds the sum of the Synchronization, Propagation, and Phase
-        //! Buffer 1 segments, measured in time quanta.  The valid values for this
-        //! setting range from 2 to 16.
-        uint16_t  uSyncPropPhase1Seg;
-
-        //! This value holds the Phase Buffer 2 segment in time quanta.  The valid
-        //! values for this setting range from 1 to 8.
-        uint16_t  uPhase2Seg;
-
-        //! This value holds the Resynchronization Jump Width in time quanta.  The
-        //! valid values for this setting range from 1 to 4.
-        uint16_t  uSJW;
-
-        //! This value holds the CAN_CLK divider used to determine time quanta.
-        //! The valid values for this setting range from 1 to 1023.
-        uint16_t  uQuantumPrescaler;
-}
-tCANBitClkParms;
-
-//*****************************************************************************
-//! This data type is used to identify the interrupt status register.  This is
-//! used when calling the CANIntStatus() function.
-//*****************************************************************************
-typedef enum
-{
-        //! Read the CAN interrupt status information.
-        CAN_INT_STS_CAUSE,
-
-        //! Read a message object's interrupt status.
-        CAN_INT_STS_OBJECT
-}
-tCANIntStsReg;
-
-//*****************************************************************************
-//! This data type is used to identify which of several status registers to
-//! read when calling the CANStatusGet() function.
-//*****************************************************************************
-typedef enum
-{
-        //! Read the full CAN controller status.
-        CAN_STS_CONTROL,
-
-        //! Read the full 32-bit mask of message objects with a transmit request
-        //! set.
-        CAN_STS_TXREQUEST,
-
-        //! Read the full 32-bit mask of message objects with new data available.
-        CAN_STS_NEWDAT,
-
-        //! Read the full 32-bit mask of message objects that are enabled.
-        CAN_STS_MSGVAL
-}
-tCANStsReg;
-
-//*****************************************************************************
-// These definitions are used to specify interrupt sources to CANIntEnable()
-// and CANIntDisable().
-//*****************************************************************************
-//! This flag is used to allow a CAN controller to generate error
-//! interrupts.
-#define CAN_INT_ERROR           0x00000008
-
-//! This flag is used to allow a CAN controller to generate status
-//! interrupts.
-#define CAN_INT_STATUS          0x00000004
-
-//! This flag is used to allow a CAN controller to generate interrupts
-//! on interrupt line 0
-#define CAN_INT_IE0             0x00000002
-
-//! This flag is used to allow a CAN controller to generate interrupts
-//! on interrupt line 1
-#define CAN_INT_IE1             0x00020000
-
-// Defined to maintain compatibility with Stellaris Examples
-#define CAN_INT_MASTER          CAN_INT_IE0
-
-//*****************************************************************************
-// These definitions are used to specify the clock source to
-// CANClkSourceSelect()
-//*****************************************************************************
-//! This flag is used to clock the CAN controller Selected CPU SYSCLKOUT
-//! (CPU1.Sysclk or CPU2.Sysclk).
-#define CAN_CLK_CPU_SYSCLKOUT       0 // PERx.SYSCLK (default on reset)
-
-//! This flag is used to clock the CAN controller with the X1/X2 oscillator
-//! clock.
-#define CAN_CLK_EXT_OSC             1 // External Oscillator (XTAL)
-
-//! This flag is used to clock the CAN controller with the clock from
-//! AUXCLKIN (from GPIO)
-#define CAN_CLK_AUXCLKIN            2 // AUXCLKIN (from GPIO)
-
-
-//*****************************************************************************
-//! This definition is used to determine the type of message object that will
-//! be set up via a call to the CANMessageSet() API.
-//*****************************************************************************
-typedef enum
-{
-        //! Transmit message object.
-        MSG_OBJ_TYPE_TX,
-
-        //! Transmit remote request message object
-        MSG_OBJ_TYPE_TX_REMOTE,
-
-        //! Receive message object.
-        MSG_OBJ_TYPE_RX,
-
-        //! Receive remote request message object.
-        MSG_OBJ_TYPE_RX_REMOTE,
-
-        //! Remote frame receive remote, with auto-transmit message object.
-        MSG_OBJ_TYPE_RXTX_REMOTE
-}
-tMsgObjType;
-
-//*****************************************************************************
-// The following enumeration contains all error or status indicators that can
-// be returned when calling the CANStatusGet() function.
-//*****************************************************************************
-//! CAN controller is in local power down mode.
-#define CAN_STATUS_PDA                0x00000400
-
-//! CAN controller has initiated a system wakeup.
-#define CAN_STATUS_WAKE_UP            0x00000200
-
-//! CAN controller has detected a parity error.
-#define CAN_STATUS_PERR               0x00000100
-
-//! CAN controller has entered a Bus Off state.
-#define CAN_STATUS_BUS_OFF            0x00000080
-
-//! CAN controller error level has reached warning level.
-#define CAN_STATUS_EWARN              0x00000040
-
-//! CAN controller error level has reached error passive level.
-#define CAN_STATUS_EPASS              0x00000020
-
-//! A message was received successfully since the last read of this status.
-#define CAN_STATUS_RXOK               0x00000010
-
-//! A message was transmitted successfully since the last read of this
-//! status.
-#define CAN_STATUS_TXOK               0x00000008
-
-//! This is the mask for the last error code field.
-#define CAN_STATUS_LEC_MSK            0x00000007
-
-//! There was no error.
-#define CAN_STATUS_LEC_NONE           0x00000000
-
-//! A bit stuffing error has occurred.
-#define CAN_STATUS_LEC_STUFF          0x00000001
-
-//! A formatting error has occurred.
-#define CAN_STATUS_LEC_FORM           0x00000002
-
-//! An acknowledge error has occurred.
-#define CAN_STATUS_LEC_ACK            0x00000003
-
-//! The bus remained a bit level of 1 for longer than is allowed.
-#define CAN_STATUS_LEC_BIT1           0x00000004
-
-//! The bus remained a bit level of 0 for longer than is allowed.
-#define CAN_STATUS_LEC_BIT0           0x00000005
-
-//! A CRC error has occurred.
-#define CAN_STATUS_LEC_CRC            0x00000006
-
-//*****************************************************************************
-// The following macros are added for the new Global Interrupt EN/FLG/CLR
-// register
-//*****************************************************************************
-//CANINT0 global interrupt bit
-#define CAN_GLOBAL_INT_CANINT0       0x00000001
-
-//CANINT1 global interrupt bit
-#define CAN_GLOBAL_INT_CANINT1       0x00000002
-
-//*****************************************************************************
-// The following macros are missing in hw_can.h because of scripting
-// but driverlib can.c needs them
-//*****************************************************************************
-
-#define CAN_INT_INT0ID_STATUS       0x8000
-
-#define CAN_IF1ARB_STD_ID_S         18
-#define CAN_IF1ARB_STD_ID_M         0x1FFC0000 // Standard Message Identifier
-
-#define CAN_IF2ARB_STD_ID_S         18
-#define CAN_IF2ARB_STD_ID_M         0x1FFC0000 // Standard Message Identifier
-
-//*****************************************************************************
-// API Function prototypes
-//*****************************************************************************
-extern void CANClkSourceSelect(uint32_t ui32Base, uint16_t  ucSource);
-extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *pClkParms);
-extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *pClkParms);
-extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock,
-                              uint32_t ui32BitRate);
-extern void CANDisable(uint32_t ui32Base);
-extern void CANEnable(uint32_t ui32Base);
-extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
-                          uint32_t *pui32TxCount);
-extern void CANInit(uint32_t ui32Base);
-extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr);
-extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void CANIntRegister(uint32_t ui32Base, unsigned char ucIntNumber,
-                           void (*pfnHandler)(void));
-extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg);
-extern void CANIntUnregister(uint32_t ui32Base, unsigned char ucIntNumber);
-extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID);
-extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID,
-                          tCANMsgObject *pMsgObject, bool bClrPendingInt);
-extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID,
-                          tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
-extern bool CANRetryGet(uint32_t ui32Base);
-extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry);
-extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg);
-extern void CANGlobalIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void CANGlobalIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void CANGlobalIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern bool CANGlobalIntstatusGet(uint32_t ui32Base, uint32_t ui32IntFlags);
-
-//*****************************************************************************
-// Mark the end of the C bindings section for C++ compilers.
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-//*****************************************************************************
-// Close the Doxygen group.
-//! @}
-//*****************************************************************************
-
-#endif //  __CAN_H__
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/debug.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/debug.h
deleted file mode 100644
index 8d018c0c7c..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/debug.h
+++ /dev/null
@@ -1,75 +0,0 @@
-//###########################################################################
-//
-// FILE:   debug.h
-//
-// TITLE:  Stellaris style debug header. Included for compatability.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __DEBUG_H__
-#define __DEBUG_H__
-
-//*****************************************************************************
-//
-// Prototype for the function that is called when an invalid argument is passed
-// to an API.  This is only used when doing a DEBUG build.
-//
-//*****************************************************************************
-extern void __error__(char *pcFilename, unsigned long ulLine);
-
-//*****************************************************************************
-//
-// The ASSERT macro, which does the actual assertion checking.  Typically, this
-// will be for procedure arguments.
-//
-//*****************************************************************************
-
-
-#ifdef DEBUG
-#define ASSERT(expr) {                                      \
-                         if(!(expr))                        \
-                         {                                  \
-                             __error__(__FILE__, __LINE__); \
-                         }                                  \
-                     }
-#else
-#define ASSERT(expr)
-#endif
-
-#endif // __DEBUG_H__
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.c
deleted file mode 100644
index 5bff0345ab..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.c
+++ /dev/null
@@ -1,411 +0,0 @@
-//###########################################################################
-//
-// FILE:   interrupt.c
-//
-// TITLE:  Stellaris style wrapper driver for C28x PIE Interrupt Controller.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-//*****************************************************************************
-//
-//! \addtogroup interrupt_api
-//! @{
-//
-//*****************************************************************************
-
-#include "F28x_Project.h"
-
-#include "inc/hw_types.h"
-#include "driverlib/interrupt.h"
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-
-
-//*****************************************************************************
-//
-//! \internal
-//! The default interrupt handler.
-//!
-//! This is the default interrupt handler.  Whenever an interrupt is
-//! unregisterd this handler takes it place.
-//!
-//! \return None.
-//
-//*****************************************************************************
-__interrupt void IntDefaultHandler(void)
-{
-    asm(" ESTOP0");
-    return;
-}
-
-//*****************************************************************************
-//
-//! Enables the processor interrupt.
-//!
-//! Allows the processor to respond to interrupts.  This does not affect the
-//! set of interrupts enabled in the interrupt controller; it just gates the
-//! single interrupt from the controller to the processor.
-//!
-//! \note Previously, this function had no return value.  As such, it was
-//! possible to include <tt>interrupt.h</tt> and call this function without
-//! having included <tt>hw_types.h</tt>.  Now that the return is a
-//! <tt>bool</tt>, a compiler error will occur in this case.  The solution
-//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
-//!
-//! \return Returns \b true if interrupts were disabled when the function was
-//! called or \b false if they were initially enabled.
-//
-//*****************************************************************************
-bool
-IntMasterEnable(void)
-{
-    //
-    // Enable processor interrupts.
-    //
-    return __enable_interrupts() & 0x1;
-}
-
-//*****************************************************************************
-//
-//! Disables the processor interrupt.
-//!
-//! Prevents the processor from receiving interrupts.  This does not affect the
-//! set of interrupts enabled in the interrupt controller; it just gates the
-//! single interrupt from the controller to the processor.
-//!
-//! \note Previously, this function had no return value.  As such, it was
-//! possible to include <tt>interrupt.h</tt> and call this function without
-//! having included <tt>hw_types.h</tt>.  Now that the return is a
-//! <tt>bool</tt>, a compiler error will occur in this case.  The solution
-//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
-//!
-//! \return Returns \b true if interrupts were already disabled when the
-//! function was called or \b false if they were initially enabled.
-//
-//*****************************************************************************
-bool
-IntMasterDisable(void)
-{
-    //
-    // Disable processor interrupts.
-    //
-    return __disable_interrupts() & 0x1;
-}
-
-//*****************************************************************************
-//
-//! Registers a function to be called when an interrupt occurs.
-//
-//! Assumes PIE is enabled
-//!
-//! \param ui32Interrupt specifies the interrupt in question.
-//! \param pfnHandler is a pointer to the function to be called.
-//!
-//! This function is used to specify the handler function to be called when the
-//! given interrupt is asserted to the processor.  When the interrupt occurs,
-//! if it is enabled (via IntEnable()), the handler function will be called in
-//! interrupt context.  Since the handler function can pre-empt other code, care
-//! must be taken to protect memory or peripherals that are accessed by the
-//! handler and other non-handler code.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void))
-{
-    EALLOW;
-    //Copy ISR address into PIE table
-    memcpy((uint16_t *) &PieVectTable + ((ui32Interrupt & 0xFFFF0000) >> 16)*2, (uint16_t *) &pfnHandler, sizeof(pfnHandler));
-    EDIS;
-}
-
-//*****************************************************************************
-//
-//! Unregisters the function to be called when an interrupt occurs.
-//!
-//! \param ui32Interrupt specifies the interrupt in question.
-//!
-//! This function is used to indicate that no handler should be called when the
-//! given interrupt is asserted to the processor.  The interrupt source will be
-//! automatically disabled (via IntDisable()) if necessary.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntUnregister(uint32_t ui32Interrupt)
-{
-    uint32_t temp;
-
-    temp = (uint32_t) IntDefaultHandler;
-
-    EALLOW;
-    //Copy default ISR address into PIE table
-    memcpy((uint16_t *) &PieVectTable + ((ui32Interrupt & 0xFFFF0000) >> 16)*2, (uint16_t *) &temp, sizeof(temp));
-    EDIS;
-}
-
-//*****************************************************************************
-//
-//! Enables an interrupt.
-//!
-//! \param ui32Interrupt specifies the interrupt to be enabled.
-//!
-//! The specified interrupt is enabled in the interrupt controller.  Other
-//! enables for the interrupt (such as at the peripheral level) are unaffected
-//! by this function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntEnable(uint32_t ui32Interrupt)
-{
-    uint16_t ui16IntsEnabled;
-
-    ui32Interrupt = ui32Interrupt >> 16;
-    EALLOW;
-    //Ensure that PIE is enabled
-    PieCtrlRegs.PIECTRL.bit.ENPIE=1;
-
-    ui16IntsEnabled = IntMasterDisable();
-
-    if (ui32Interrupt >= 0x20 && ui32Interrupt <= 0x7F) //Lower PIE table
-    {
-        //Enable Individual PIE interrupt
-        *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x20)/8))*2) |= 1 << ((ui32Interrupt-0x20)%8);
-
-        // Wait for any pending interrupts to get to the CPU
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-
-        //Clear the CPU flag
-        IntIFRClear(1 << ((ui32Interrupt - 0x20)/8));
-
-        //Acknowlege any interrupts
-        PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x20)/8);
-
-        //Enable PIE Group Interrupt
-        IER |= 1 << ((ui32Interrupt - 0x20)/8);
-    }
-    else if (ui32Interrupt >= 0x80) //Upper PIE table
-    {
-        //Enable Individual PIE interrupt
-        *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x80)/8))*2) |= 1 << (((ui32Interrupt-0x80)%8)+8);
-
-        // Wait for any pending interrupts to get to the CPU
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-
-        //Clear the CPU flag
-        IntIFRClear(1 << ((ui32Interrupt - 0x80)/8));
-
-        //Acknowlege any interrupts
-        PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x80)/8);
-
-        //Enable PIE Group Interrupt
-        IER |= 1 << ((ui32Interrupt - 0x80)/8);
-    }
-    else if (ui32Interrupt >= 0x0D && ui32Interrupt <= 0x10) //INT13, INT14, DLOGINT, & RTOSINT
-    {
-        //Enable PIE Group Interrupt
-        IER |= 1 << (ui32Interrupt - 1);
-    }
-    else
-    {
-        //Other interrupts
-    }
-
-    EDIS;
-
-    //Re-enable interrupts if they were enabled
-    if(!ui16IntsEnabled){
-        IntMasterEnable();
-    }
-}
-
-//*****************************************************************************
-//
-//! Disables an interrupt.
-//!
-//! \param ui32Interrupt specifies the interrupt to be disabled.
-//!
-//! The specified interrupt is disabled in the interrupt controller.  Other
-//! enables for the interrupt (such as at the peripheral level) are unaffected
-//! by this function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntDisable(uint32_t ui32Interrupt)
-{
-    uint16_t ui16IntsEnabled;
-
-    ui32Interrupt = ui32Interrupt >> 16;
-    EALLOW;
-
-    ui16IntsEnabled = IntMasterDisable();
-
-    if (ui32Interrupt >= 0x20 && ui32Interrupt <= 0x7F) //Lower PIE table
-    {
-        //Disable Individual PIE interrupt
-        *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x20)/8))*2) &= ~(1 << ((ui32Interrupt-0x20)%8));
-
-        // Wait for any pending interrupts to get to the CPU
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-
-        //Clear the CPU flag
-        IntIFRClear(1 << ((ui32Interrupt - 0x20)/8));
-
-        //Acknowlege any interrupts
-        PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x20)/8);
-    }
-    else if (ui32Interrupt >= 0x80) //Upper PIE table
-    {
-        //Disable Individual PIE interrupt
-        *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x80)/8))*2) &= ~(1 << (((ui32Interrupt-0x80)%8)+8));
-
-        // Wait for any pending interrupts to get to the CPU
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-        asm(" nop");
-
-        //Clear the CPU flag
-        IntIFRClear(1 << ((ui32Interrupt - 0x80)/8));
-
-        //Acknowlege any interrupts
-        PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x80)/8);
-    }
-    else if (ui32Interrupt >= 0x0D && ui32Interrupt <= 0x10) //INT13, INT14, DLOGINT, & RTOSINT //Work-around Case
-    {
-        //Disable PIE Group Interrupt
-        IER &= ~(1 << (ui32Interrupt - 1));
-    }
-    else
-    {
-        //Other Interrupts
-    }
-    EDIS;
-
-    //Re-enable interrupts if they were enabled
-    if(!ui16IntsEnabled){
-        IntMasterEnable();
-    }
-}
-
-void IntIFRClear(uint16_t ui16Interrupts)
-{
-    switch(ui16Interrupts){
-    case 0x0001:
-        IFR &= ~0x0001;
-        break;
-    case 0x0002:
-        IFR &= ~0x0002;
-        break;
-    case 0x0004:
-        IFR &= ~0x0004;
-        break;
-    case 0x0008:
-        IFR &= ~0x0008;
-        break;
-    case 0x0010:
-        IFR &= ~0x0010;
-        break;
-    case 0x0020:
-        IFR &= ~0x0020;
-        break;
-    case 0x0040:
-        IFR &= ~0x0040;
-        break;
-    case 0x0080:
-        IFR &= ~0x0080;
-        break;
-    case 0x0100:
-        IFR &= ~0x0100;
-        break;
-    case 0x0200:
-        IFR &= ~0x0200;
-        break;
-    case 0x0400:
-        IFR &= ~0x0400;
-        break;
-    case 0x0800:
-        IFR &= ~0x0800;
-        break;
-    case 0x1000:
-        IFR &= ~0x1000;
-        break;
-    case 0x2000:
-        IFR &= ~0x2000;
-        break;
-    case 0x4000:
-        IFR &= ~0x4000;
-        break;
-    case 0x8000:
-        IFR &= ~0x8000;
-        break;
-    default:
-        break;
-    }
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.h
deleted file mode 100644
index d6104fba3f..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.h
+++ /dev/null
@@ -1,81 +0,0 @@
-//###########################################################################
-//
-// FILE:   interrupt.h
-//
-// TITLE:  Stellaris style wrapper driver for C28x PIE Interrupt Controller.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-    extern bool IntMasterEnable(void);
-    extern bool IntMasterDisable(void);
-    extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void));
-    extern void IntUnregister(uint32_t ui32Interrupt);
-    extern void IntEnable(uint32_t ui32Interrupt);
-    extern void IntDisable(uint32_t ui32Interrupt);
-    extern void IntIFRClear(uint16_t ui16Interrupts);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __INTERRUPT_H__
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom.h
deleted file mode 100644
index c085a00c61..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom.h
+++ /dev/null
@@ -1,44 +0,0 @@
-//*****************************************************************************
-//
-// rom.h - Macros to facilitate calling functions in the ROM.
-//
-// Copyright (c) 2007-2012 Texas Instruments Incorporated.  All rights reserved.
-// Software License Agreement
-// 
-//   Redistribution and use in source and binary forms, with or without
-//   modification, are permitted provided that the following conditions
-//   are met:
-// 
-//   Redistributions of source code must retain the above copyright
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the
-//   documentation and/or other materials provided with the  
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// 
-// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __ROM_H__
-#define __ROM_H__
-
-
-#endif //__ROM_H__
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom_map.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom_map.h
deleted file mode 100644
index 7794c1a9d0..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom_map.h
+++ /dev/null
@@ -1,5082 +0,0 @@
-//*****************************************************************************
-//
-// rom_map.h - Macros to facilitate calling functions in the ROM when they are
-//             available and in flash otherwise.
-//
-// Copyright (c) 2008-2012 Texas Instruments Incorporated.  All rights reserved.
-// Software License Agreement
-// 
-//   Redistribution and use in source and binary forms, with or without
-//   modification, are permitted provided that the following conditions
-//   are met:
-// 
-//   Redistributions of source code must retain the above copyright
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the
-//   documentation and/or other materials provided with the  
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// 
-// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __ROM_MAP_H__
-#define __ROM_MAP_H__
-
-//*****************************************************************************
-//
-// Macros for the ADC API.
-//
-//*****************************************************************************
-#ifdef ROM_ADCSequenceDataGet
-#define MAP_ADCSequenceDataGet \
-        ROM_ADCSequenceDataGet
-#else
-#define MAP_ADCSequenceDataGet \
-        ADCSequenceDataGet
-#endif
-#ifdef ROM_ADCIntDisable
-#define MAP_ADCIntDisable \
-        ROM_ADCIntDisable
-#else
-#define MAP_ADCIntDisable \
-        ADCIntDisable
-#endif
-#ifdef ROM_ADCIntEnable
-#define MAP_ADCIntEnable \
-        ROM_ADCIntEnable
-#else
-#define MAP_ADCIntEnable \
-        ADCIntEnable
-#endif
-#ifdef ROM_ADCIntStatus
-#define MAP_ADCIntStatus \
-        ROM_ADCIntStatus
-#else
-#define MAP_ADCIntStatus \
-        ADCIntStatus
-#endif
-#ifdef ROM_ADCIntClear
-#define MAP_ADCIntClear \
-        ROM_ADCIntClear
-#else
-#define MAP_ADCIntClear \
-        ADCIntClear
-#endif
-#ifdef ROM_ADCSequenceEnable
-#define MAP_ADCSequenceEnable \
-        ROM_ADCSequenceEnable
-#else
-#define MAP_ADCSequenceEnable \
-        ADCSequenceEnable
-#endif
-#ifdef ROM_ADCSequenceDisable
-#define MAP_ADCSequenceDisable \
-        ROM_ADCSequenceDisable
-#else
-#define MAP_ADCSequenceDisable \
-        ADCSequenceDisable
-#endif
-#ifdef ROM_ADCSequenceConfigure
-#define MAP_ADCSequenceConfigure \
-        ROM_ADCSequenceConfigure
-#else
-#define MAP_ADCSequenceConfigure \
-        ADCSequenceConfigure
-#endif
-#ifdef ROM_ADCSequenceStepConfigure
-#define MAP_ADCSequenceStepConfigure \
-        ROM_ADCSequenceStepConfigure
-#else
-#define MAP_ADCSequenceStepConfigure \
-        ADCSequenceStepConfigure
-#endif
-#ifdef ROM_ADCSequenceOverflow
-#define MAP_ADCSequenceOverflow \
-        ROM_ADCSequenceOverflow
-#else
-#define MAP_ADCSequenceOverflow \
-        ADCSequenceOverflow
-#endif
-#ifdef ROM_ADCSequenceOverflowClear
-#define MAP_ADCSequenceOverflowClear \
-        ROM_ADCSequenceOverflowClear
-#else
-#define MAP_ADCSequenceOverflowClear \
-        ADCSequenceOverflowClear
-#endif
-#ifdef ROM_ADCSequenceUnderflow
-#define MAP_ADCSequenceUnderflow \
-        ROM_ADCSequenceUnderflow
-#else
-#define MAP_ADCSequenceUnderflow \
-        ADCSequenceUnderflow
-#endif
-#ifdef ROM_ADCSequenceUnderflowClear
-#define MAP_ADCSequenceUnderflowClear \
-        ROM_ADCSequenceUnderflowClear
-#else
-#define MAP_ADCSequenceUnderflowClear \
-        ADCSequenceUnderflowClear
-#endif
-#ifdef ROM_ADCProcessorTrigger
-#define MAP_ADCProcessorTrigger \
-        ROM_ADCProcessorTrigger
-#else
-#define MAP_ADCProcessorTrigger \
-        ADCProcessorTrigger
-#endif
-#ifdef ROM_ADCHardwareOversampleConfigure
-#define MAP_ADCHardwareOversampleConfigure \
-        ROM_ADCHardwareOversampleConfigure
-#else
-#define MAP_ADCHardwareOversampleConfigure \
-        ADCHardwareOversampleConfigure
-#endif
-#ifdef ROM_ADCComparatorConfigure
-#define MAP_ADCComparatorConfigure \
-        ROM_ADCComparatorConfigure
-#else
-#define MAP_ADCComparatorConfigure \
-        ADCComparatorConfigure
-#endif
-#ifdef ROM_ADCComparatorRegionSet
-#define MAP_ADCComparatorRegionSet \
-        ROM_ADCComparatorRegionSet
-#else
-#define MAP_ADCComparatorRegionSet \
-        ADCComparatorRegionSet
-#endif
-#ifdef ROM_ADCComparatorReset
-#define MAP_ADCComparatorReset \
-        ROM_ADCComparatorReset
-#else
-#define MAP_ADCComparatorReset \
-        ADCComparatorReset
-#endif
-#ifdef ROM_ADCComparatorIntDisable
-#define MAP_ADCComparatorIntDisable \
-        ROM_ADCComparatorIntDisable
-#else
-#define MAP_ADCComparatorIntDisable \
-        ADCComparatorIntDisable
-#endif
-#ifdef ROM_ADCComparatorIntEnable
-#define MAP_ADCComparatorIntEnable \
-        ROM_ADCComparatorIntEnable
-#else
-#define MAP_ADCComparatorIntEnable \
-        ADCComparatorIntEnable
-#endif
-#ifdef ROM_ADCComparatorIntStatus
-#define MAP_ADCComparatorIntStatus \
-        ROM_ADCComparatorIntStatus
-#else
-#define MAP_ADCComparatorIntStatus \
-        ADCComparatorIntStatus
-#endif
-#ifdef ROM_ADCComparatorIntClear
-#define MAP_ADCComparatorIntClear \
-        ROM_ADCComparatorIntClear
-#else
-#define MAP_ADCComparatorIntClear \
-        ADCComparatorIntClear
-#endif
-#ifdef ROM_ADCReferenceSet
-#define MAP_ADCReferenceSet \
-        ROM_ADCReferenceSet
-#else
-#define MAP_ADCReferenceSet \
-        ADCReferenceSet
-#endif
-#ifdef ROM_ADCReferenceGet
-#define MAP_ADCReferenceGet \
-        ROM_ADCReferenceGet
-#else
-#define MAP_ADCReferenceGet \
-        ADCReferenceGet
-#endif
-#ifdef ROM_ADCPhaseDelaySet
-#define MAP_ADCPhaseDelaySet \
-        ROM_ADCPhaseDelaySet
-#else
-#define MAP_ADCPhaseDelaySet \
-        ADCPhaseDelaySet
-#endif
-#ifdef ROM_ADCPhaseDelayGet
-#define MAP_ADCPhaseDelayGet \
-        ROM_ADCPhaseDelayGet
-#else
-#define MAP_ADCPhaseDelayGet \
-        ADCPhaseDelayGet
-#endif
-#ifdef ROM_ADCResolutionSet
-#define MAP_ADCResolutionSet \
-        ROM_ADCResolutionSet
-#else
-#define MAP_ADCResolutionSet \
-        ADCResolutionSet
-#endif
-#ifdef ROM_ADCResolutionGet
-#define MAP_ADCResolutionGet \
-        ROM_ADCResolutionGet
-#else
-#define MAP_ADCResolutionGet \
-        ADCResolutionGet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the CAN API.
-//
-//*****************************************************************************
-#ifdef ROM_CANIntClear
-#define MAP_CANIntClear \
-        ROM_CANIntClear
-#else
-#define MAP_CANIntClear \
-        CANIntClear
-#endif
-#ifdef ROM_CANInit
-#define MAP_CANInit \
-        ROM_CANInit
-#else
-#define MAP_CANInit \
-        CANInit
-#endif
-#ifdef ROM_CANEnable
-#define MAP_CANEnable \
-        ROM_CANEnable
-#else
-#define MAP_CANEnable \
-        CANEnable
-#endif
-#ifdef ROM_CANDisable
-#define MAP_CANDisable \
-        ROM_CANDisable
-#else
-#define MAP_CANDisable \
-        CANDisable
-#endif
-#ifdef ROM_CANBitTimingSet
-#define MAP_CANBitTimingSet \
-        ROM_CANBitTimingSet
-#else
-#define MAP_CANBitTimingSet \
-        CANBitTimingSet
-#endif
-#ifdef ROM_CANBitTimingGet
-#define MAP_CANBitTimingGet \
-        ROM_CANBitTimingGet
-#else
-#define MAP_CANBitTimingGet \
-        CANBitTimingGet
-#endif
-#ifdef ROM_CANMessageSet
-#define MAP_CANMessageSet \
-        ROM_CANMessageSet
-#else
-#define MAP_CANMessageSet \
-        CANMessageSet
-#endif
-#ifdef ROM_CANMessageGet
-#define MAP_CANMessageGet \
-        ROM_CANMessageGet
-#else
-#define MAP_CANMessageGet \
-        CANMessageGet
-#endif
-#ifdef ROM_CANStatusGet
-#define MAP_CANStatusGet \
-        ROM_CANStatusGet
-#else
-#define MAP_CANStatusGet \
-        CANStatusGet
-#endif
-#ifdef ROM_CANMessageClear
-#define MAP_CANMessageClear \
-        ROM_CANMessageClear
-#else
-#define MAP_CANMessageClear \
-        CANMessageClear
-#endif
-#ifdef ROM_CANIntEnable
-#define MAP_CANIntEnable \
-        ROM_CANIntEnable
-#else
-#define MAP_CANIntEnable \
-        CANIntEnable
-#endif
-#ifdef ROM_CANIntDisable
-#define MAP_CANIntDisable \
-        ROM_CANIntDisable
-#else
-#define MAP_CANIntDisable \
-        CANIntDisable
-#endif
-#ifdef ROM_CANIntStatus
-#define MAP_CANIntStatus \
-        ROM_CANIntStatus
-#else
-#define MAP_CANIntStatus \
-        CANIntStatus
-#endif
-#ifdef ROM_CANRetryGet
-#define MAP_CANRetryGet \
-        ROM_CANRetryGet
-#else
-#define MAP_CANRetryGet \
-        CANRetryGet
-#endif
-#ifdef ROM_CANRetrySet
-#define MAP_CANRetrySet \
-        ROM_CANRetrySet
-#else
-#define MAP_CANRetrySet \
-        CANRetrySet
-#endif
-#ifdef ROM_CANErrCntrGet
-#define MAP_CANErrCntrGet \
-        ROM_CANErrCntrGet
-#else
-#define MAP_CANErrCntrGet \
-        CANErrCntrGet
-#endif
-#ifdef ROM_CANBitRateSet
-#define MAP_CANBitRateSet \
-        ROM_CANBitRateSet
-#else
-#define MAP_CANBitRateSet \
-        CANBitRateSet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Comparator API.
-//
-//*****************************************************************************
-#ifdef ROM_ComparatorIntClear
-#define MAP_ComparatorIntClear \
-        ROM_ComparatorIntClear
-#else
-#define MAP_ComparatorIntClear \
-        ComparatorIntClear
-#endif
-#ifdef ROM_ComparatorConfigure
-#define MAP_ComparatorConfigure \
-        ROM_ComparatorConfigure
-#else
-#define MAP_ComparatorConfigure \
-        ComparatorConfigure
-#endif
-#ifdef ROM_ComparatorRefSet
-#define MAP_ComparatorRefSet \
-        ROM_ComparatorRefSet
-#else
-#define MAP_ComparatorRefSet \
-        ComparatorRefSet
-#endif
-#ifdef ROM_ComparatorValueGet
-#define MAP_ComparatorValueGet \
-        ROM_ComparatorValueGet
-#else
-#define MAP_ComparatorValueGet \
-        ComparatorValueGet
-#endif
-#ifdef ROM_ComparatorIntEnable
-#define MAP_ComparatorIntEnable \
-        ROM_ComparatorIntEnable
-#else
-#define MAP_ComparatorIntEnable \
-        ComparatorIntEnable
-#endif
-#ifdef ROM_ComparatorIntDisable
-#define MAP_ComparatorIntDisable \
-        ROM_ComparatorIntDisable
-#else
-#define MAP_ComparatorIntDisable \
-        ComparatorIntDisable
-#endif
-#ifdef ROM_ComparatorIntStatus
-#define MAP_ComparatorIntStatus \
-        ROM_ComparatorIntStatus
-#else
-#define MAP_ComparatorIntStatus \
-        ComparatorIntStatus
-#endif
-
-//*****************************************************************************
-//
-// Macros for the EEPROM API.
-//
-//*****************************************************************************
-#ifdef ROM_EEPROMRead
-#define MAP_EEPROMRead \
-        ROM_EEPROMRead
-#else
-#define MAP_EEPROMRead \
-        EEPROMRead
-#endif
-#ifdef ROM_EEPROMBlockCountGet
-#define MAP_EEPROMBlockCountGet \
-        ROM_EEPROMBlockCountGet
-#else
-#define MAP_EEPROMBlockCountGet \
-        EEPROMBlockCountGet
-#endif
-#ifdef ROM_EEPROMBlockHide
-#define MAP_EEPROMBlockHide \
-        ROM_EEPROMBlockHide
-#else
-#define MAP_EEPROMBlockHide \
-        EEPROMBlockHide
-#endif
-#ifdef ROM_EEPROMBlockLock
-#define MAP_EEPROMBlockLock \
-        ROM_EEPROMBlockLock
-#else
-#define MAP_EEPROMBlockLock \
-        EEPROMBlockLock
-#endif
-#ifdef ROM_EEPROMBlockPasswordSet
-#define MAP_EEPROMBlockPasswordSet \
-        ROM_EEPROMBlockPasswordSet
-#else
-#define MAP_EEPROMBlockPasswordSet \
-        EEPROMBlockPasswordSet
-#endif
-#ifdef ROM_EEPROMBlockProtectGet
-#define MAP_EEPROMBlockProtectGet \
-        ROM_EEPROMBlockProtectGet
-#else
-#define MAP_EEPROMBlockProtectGet \
-        EEPROMBlockProtectGet
-#endif
-#ifdef ROM_EEPROMBlockProtectSet
-#define MAP_EEPROMBlockProtectSet \
-        ROM_EEPROMBlockProtectSet
-#else
-#define MAP_EEPROMBlockProtectSet \
-        EEPROMBlockProtectSet
-#endif
-#ifdef ROM_EEPROMBlockUnlock
-#define MAP_EEPROMBlockUnlock \
-        ROM_EEPROMBlockUnlock
-#else
-#define MAP_EEPROMBlockUnlock \
-        EEPROMBlockUnlock
-#endif
-#ifdef ROM_EEPROMIntClear
-#define MAP_EEPROMIntClear \
-        ROM_EEPROMIntClear
-#else
-#define MAP_EEPROMIntClear \
-        EEPROMIntClear
-#endif
-#ifdef ROM_EEPROMIntDisable
-#define MAP_EEPROMIntDisable \
-        ROM_EEPROMIntDisable
-#else
-#define MAP_EEPROMIntDisable \
-        EEPROMIntDisable
-#endif
-#ifdef ROM_EEPROMIntEnable
-#define MAP_EEPROMIntEnable \
-        ROM_EEPROMIntEnable
-#else
-#define MAP_EEPROMIntEnable \
-        EEPROMIntEnable
-#endif
-#ifdef ROM_EEPROMIntStatus
-#define MAP_EEPROMIntStatus \
-        ROM_EEPROMIntStatus
-#else
-#define MAP_EEPROMIntStatus \
-        EEPROMIntStatus
-#endif
-#ifdef ROM_EEPROMMassErase
-#define MAP_EEPROMMassErase \
-        ROM_EEPROMMassErase
-#else
-#define MAP_EEPROMMassErase \
-        EEPROMMassErase
-#endif
-#ifdef ROM_EEPROMProgram
-#define MAP_EEPROMProgram \
-        ROM_EEPROMProgram
-#else
-#define MAP_EEPROMProgram \
-        EEPROMProgram
-#endif
-#ifdef ROM_EEPROMProgramNonBlocking
-#define MAP_EEPROMProgramNonBlocking \
-        ROM_EEPROMProgramNonBlocking
-#else
-#define MAP_EEPROMProgramNonBlocking \
-        EEPROMProgramNonBlocking
-#endif
-#ifdef ROM_EEPROMSizeGet
-#define MAP_EEPROMSizeGet \
-        ROM_EEPROMSizeGet
-#else
-#define MAP_EEPROMSizeGet \
-        EEPROMSizeGet
-#endif
-#ifdef ROM_EEPROMStatusGet
-#define MAP_EEPROMStatusGet \
-        ROM_EEPROMStatusGet
-#else
-#define MAP_EEPROMStatusGet \
-        EEPROMStatusGet
-#endif
-#ifdef ROM_EEPROMInit
-#define MAP_EEPROMInit \
-        ROM_EEPROMInit
-#else
-#define MAP_EEPROMInit \
-        EEPROMInit
-#endif
-
-//*****************************************************************************
-//
-// Macros for the EPI API.
-//
-//*****************************************************************************
-#ifdef ROM_EPIIntStatus
-#define MAP_EPIIntStatus \
-        ROM_EPIIntStatus
-#else
-#define MAP_EPIIntStatus \
-        EPIIntStatus
-#endif
-#ifdef ROM_EPIModeSet
-#define MAP_EPIModeSet \
-        ROM_EPIModeSet
-#else
-#define MAP_EPIModeSet \
-        EPIModeSet
-#endif
-#ifdef ROM_EPIDividerSet
-#define MAP_EPIDividerSet \
-        ROM_EPIDividerSet
-#else
-#define MAP_EPIDividerSet \
-        EPIDividerSet
-#endif
-#ifdef ROM_EPIConfigSDRAMSet
-#define MAP_EPIConfigSDRAMSet \
-        ROM_EPIConfigSDRAMSet
-#else
-#define MAP_EPIConfigSDRAMSet \
-        EPIConfigSDRAMSet
-#endif
-#ifdef ROM_EPIConfigGPModeSet
-#define MAP_EPIConfigGPModeSet \
-        ROM_EPIConfigGPModeSet
-#else
-#define MAP_EPIConfigGPModeSet \
-        EPIConfigGPModeSet
-#endif
-#ifdef ROM_EPIConfigHB8Set
-#define MAP_EPIConfigHB8Set \
-        ROM_EPIConfigHB8Set
-#else
-#define MAP_EPIConfigHB8Set \
-        EPIConfigHB8Set
-#endif
-#ifdef ROM_EPIConfigHB16Set
-#define MAP_EPIConfigHB16Set \
-        ROM_EPIConfigHB16Set
-#else
-#define MAP_EPIConfigHB16Set \
-        EPIConfigHB16Set
-#endif
-#ifdef ROM_EPIAddressMapSet
-#define MAP_EPIAddressMapSet \
-        ROM_EPIAddressMapSet
-#else
-#define MAP_EPIAddressMapSet \
-        EPIAddressMapSet
-#endif
-#ifdef ROM_EPINonBlockingReadConfigure
-#define MAP_EPINonBlockingReadConfigure \
-        ROM_EPINonBlockingReadConfigure
-#else
-#define MAP_EPINonBlockingReadConfigure \
-        EPINonBlockingReadConfigure
-#endif
-#ifdef ROM_EPINonBlockingReadStart
-#define MAP_EPINonBlockingReadStart \
-        ROM_EPINonBlockingReadStart
-#else
-#define MAP_EPINonBlockingReadStart \
-        EPINonBlockingReadStart
-#endif
-#ifdef ROM_EPINonBlockingReadStop
-#define MAP_EPINonBlockingReadStop \
-        ROM_EPINonBlockingReadStop
-#else
-#define MAP_EPINonBlockingReadStop \
-        EPINonBlockingReadStop
-#endif
-#ifdef ROM_EPINonBlockingReadCount
-#define MAP_EPINonBlockingReadCount \
-        ROM_EPINonBlockingReadCount
-#else
-#define MAP_EPINonBlockingReadCount \
-        EPINonBlockingReadCount
-#endif
-#ifdef ROM_EPINonBlockingReadAvail
-#define MAP_EPINonBlockingReadAvail \
-        ROM_EPINonBlockingReadAvail
-#else
-#define MAP_EPINonBlockingReadAvail \
-        EPINonBlockingReadAvail
-#endif
-#ifdef ROM_EPINonBlockingReadGet32
-#define MAP_EPINonBlockingReadGet32 \
-        ROM_EPINonBlockingReadGet32
-#else
-#define MAP_EPINonBlockingReadGet32 \
-        EPINonBlockingReadGet32
-#endif
-#ifdef ROM_EPINonBlockingReadGet16
-#define MAP_EPINonBlockingReadGet16 \
-        ROM_EPINonBlockingReadGet16
-#else
-#define MAP_EPINonBlockingReadGet16 \
-        EPINonBlockingReadGet16
-#endif
-#ifdef ROM_EPINonBlockingReadGet8
-#define MAP_EPINonBlockingReadGet8 \
-        ROM_EPINonBlockingReadGet8
-#else
-#define MAP_EPINonBlockingReadGet8 \
-        EPINonBlockingReadGet8
-#endif
-#ifdef ROM_EPIFIFOConfig
-#define MAP_EPIFIFOConfig \
-        ROM_EPIFIFOConfig
-#else
-#define MAP_EPIFIFOConfig \
-        EPIFIFOConfig
-#endif
-#ifdef ROM_EPIWriteFIFOCountGet
-#define MAP_EPIWriteFIFOCountGet \
-        ROM_EPIWriteFIFOCountGet
-#else
-#define MAP_EPIWriteFIFOCountGet \
-        EPIWriteFIFOCountGet
-#endif
-#ifdef ROM_EPIIntEnable
-#define MAP_EPIIntEnable \
-        ROM_EPIIntEnable
-#else
-#define MAP_EPIIntEnable \
-        EPIIntEnable
-#endif
-#ifdef ROM_EPIIntDisable
-#define MAP_EPIIntDisable \
-        ROM_EPIIntDisable
-#else
-#define MAP_EPIIntDisable \
-        EPIIntDisable
-#endif
-#ifdef ROM_EPIIntErrorStatus
-#define MAP_EPIIntErrorStatus \
-        ROM_EPIIntErrorStatus
-#else
-#define MAP_EPIIntErrorStatus \
-        EPIIntErrorStatus
-#endif
-#ifdef ROM_EPIIntErrorClear
-#define MAP_EPIIntErrorClear \
-        ROM_EPIIntErrorClear
-#else
-#define MAP_EPIIntErrorClear \
-        EPIIntErrorClear
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Ethernet API.
-//
-//*****************************************************************************
-#ifdef ROM_EthernetIntClear
-#define MAP_EthernetIntClear \
-        ROM_EthernetIntClear
-#else
-#define MAP_EthernetIntClear \
-        EthernetIntClear
-#endif
-#ifdef ROM_EthernetInitExpClk
-#define MAP_EthernetInitExpClk \
-        ROM_EthernetInitExpClk
-#else
-#define MAP_EthernetInitExpClk \
-        EthernetInitExpClk
-#endif
-#ifdef ROM_EthernetConfigSet
-#define MAP_EthernetConfigSet \
-        ROM_EthernetConfigSet
-#else
-#define MAP_EthernetConfigSet \
-        EthernetConfigSet
-#endif
-#ifdef ROM_EthernetConfigGet
-#define MAP_EthernetConfigGet \
-        ROM_EthernetConfigGet
-#else
-#define MAP_EthernetConfigGet \
-        EthernetConfigGet
-#endif
-#ifdef ROM_EthernetMACAddrSet
-#define MAP_EthernetMACAddrSet \
-        ROM_EthernetMACAddrSet
-#else
-#define MAP_EthernetMACAddrSet \
-        EthernetMACAddrSet
-#endif
-#ifdef ROM_EthernetMACAddrGet
-#define MAP_EthernetMACAddrGet \
-        ROM_EthernetMACAddrGet
-#else
-#define MAP_EthernetMACAddrGet \
-        EthernetMACAddrGet
-#endif
-#ifdef ROM_EthernetEnable
-#define MAP_EthernetEnable \
-        ROM_EthernetEnable
-#else
-#define MAP_EthernetEnable \
-        EthernetEnable
-#endif
-#ifdef ROM_EthernetDisable
-#define MAP_EthernetDisable \
-        ROM_EthernetDisable
-#else
-#define MAP_EthernetDisable \
-        EthernetDisable
-#endif
-#ifdef ROM_EthernetPacketAvail
-#define MAP_EthernetPacketAvail \
-        ROM_EthernetPacketAvail
-#else
-#define MAP_EthernetPacketAvail \
-        EthernetPacketAvail
-#endif
-#ifdef ROM_EthernetSpaceAvail
-#define MAP_EthernetSpaceAvail \
-        ROM_EthernetSpaceAvail
-#else
-#define MAP_EthernetSpaceAvail \
-        EthernetSpaceAvail
-#endif
-#ifdef ROM_EthernetPacketGetNonBlocking
-#define MAP_EthernetPacketGetNonBlocking \
-        ROM_EthernetPacketGetNonBlocking
-#else
-#define MAP_EthernetPacketGetNonBlocking \
-        EthernetPacketGetNonBlocking
-#endif
-#ifdef ROM_EthernetPacketGet
-#define MAP_EthernetPacketGet \
-        ROM_EthernetPacketGet
-#else
-#define MAP_EthernetPacketGet \
-        EthernetPacketGet
-#endif
-#ifdef ROM_EthernetPacketPutNonBlocking
-#define MAP_EthernetPacketPutNonBlocking \
-        ROM_EthernetPacketPutNonBlocking
-#else
-#define MAP_EthernetPacketPutNonBlocking \
-        EthernetPacketPutNonBlocking
-#endif
-#ifdef ROM_EthernetPacketPut
-#define MAP_EthernetPacketPut \
-        ROM_EthernetPacketPut
-#else
-#define MAP_EthernetPacketPut \
-        EthernetPacketPut
-#endif
-#ifdef ROM_EthernetIntEnable
-#define MAP_EthernetIntEnable \
-        ROM_EthernetIntEnable
-#else
-#define MAP_EthernetIntEnable \
-        EthernetIntEnable
-#endif
-#ifdef ROM_EthernetIntDisable
-#define MAP_EthernetIntDisable \
-        ROM_EthernetIntDisable
-#else
-#define MAP_EthernetIntDisable \
-        EthernetIntDisable
-#endif
-#ifdef ROM_EthernetIntStatus
-#define MAP_EthernetIntStatus \
-        ROM_EthernetIntStatus
-#else
-#define MAP_EthernetIntStatus \
-        EthernetIntStatus
-#endif
-#ifdef ROM_EthernetPHYWrite
-#define MAP_EthernetPHYWrite \
-        ROM_EthernetPHYWrite
-#else
-#define MAP_EthernetPHYWrite \
-        EthernetPHYWrite
-#endif
-#ifdef ROM_EthernetPHYRead
-#define MAP_EthernetPHYRead \
-        ROM_EthernetPHYRead
-#else
-#define MAP_EthernetPHYRead \
-        EthernetPHYRead
-#endif
-#ifdef ROM_EthernetPHYAddrSet
-#define MAP_EthernetPHYAddrSet \
-        ROM_EthernetPHYAddrSet
-#else
-#define MAP_EthernetPHYAddrSet \
-        EthernetPHYAddrSet
-#endif
-#ifdef ROM_EthernetPHYPowerOff
-#define MAP_EthernetPHYPowerOff \
-        ROM_EthernetPHYPowerOff
-#else
-#define MAP_EthernetPHYPowerOff \
-        EthernetPHYPowerOff
-#endif
-#ifdef ROM_EthernetPHYPowerOn
-#define MAP_EthernetPHYPowerOn \
-        ROM_EthernetPHYPowerOn
-#else
-#define MAP_EthernetPHYPowerOn \
-        EthernetPHYPowerOn
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Fan API.
-//
-//*****************************************************************************
-#ifdef ROM_FanIntClear
-#define MAP_FanIntClear \
-        ROM_FanIntClear
-#else
-#define MAP_FanIntClear \
-        FanIntClear
-#endif
-#ifdef ROM_FanChannelConfigAuto
-#define MAP_FanChannelConfigAuto \
-        ROM_FanChannelConfigAuto
-#else
-#define MAP_FanChannelConfigAuto \
-        FanChannelConfigAuto
-#endif
-#ifdef ROM_FanChannelConfigManual
-#define MAP_FanChannelConfigManual \
-        ROM_FanChannelConfigManual
-#else
-#define MAP_FanChannelConfigManual \
-        FanChannelConfigManual
-#endif
-#ifdef ROM_FanChannelDisable
-#define MAP_FanChannelDisable \
-        ROM_FanChannelDisable
-#else
-#define MAP_FanChannelDisable \
-        FanChannelDisable
-#endif
-#ifdef ROM_FanChannelDutyGet
-#define MAP_FanChannelDutyGet \
-        ROM_FanChannelDutyGet
-#else
-#define MAP_FanChannelDutyGet \
-        FanChannelDutyGet
-#endif
-#ifdef ROM_FanChannelDutySet
-#define MAP_FanChannelDutySet \
-        ROM_FanChannelDutySet
-#else
-#define MAP_FanChannelDutySet \
-        FanChannelDutySet
-#endif
-#ifdef ROM_FanChannelEnable
-#define MAP_FanChannelEnable \
-        ROM_FanChannelEnable
-#else
-#define MAP_FanChannelEnable \
-        FanChannelEnable
-#endif
-#ifdef ROM_FanChannelRPMGet
-#define MAP_FanChannelRPMGet \
-        ROM_FanChannelRPMGet
-#else
-#define MAP_FanChannelRPMGet \
-        FanChannelRPMGet
-#endif
-#ifdef ROM_FanChannelRPMSet
-#define MAP_FanChannelRPMSet \
-        ROM_FanChannelRPMSet
-#else
-#define MAP_FanChannelRPMSet \
-        FanChannelRPMSet
-#endif
-#ifdef ROM_FanChannelStatus
-#define MAP_FanChannelStatus \
-        ROM_FanChannelStatus
-#else
-#define MAP_FanChannelStatus \
-        FanChannelStatus
-#endif
-#ifdef ROM_FanChannelsGet
-#define MAP_FanChannelsGet \
-        ROM_FanChannelsGet
-#else
-#define MAP_FanChannelsGet \
-        FanChannelsGet
-#endif
-#ifdef ROM_FanIntDisable
-#define MAP_FanIntDisable \
-        ROM_FanIntDisable
-#else
-#define MAP_FanIntDisable \
-        FanIntDisable
-#endif
-#ifdef ROM_FanIntEnable
-#define MAP_FanIntEnable \
-        ROM_FanIntEnable
-#else
-#define MAP_FanIntEnable \
-        FanIntEnable
-#endif
-#ifdef ROM_FanIntStatus
-#define MAP_FanIntStatus \
-        ROM_FanIntStatus
-#else
-#define MAP_FanIntStatus \
-        FanIntStatus
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Flash API.
-//
-//*****************************************************************************
-#ifdef ROM_FlashProgram
-#define MAP_FlashProgram \
-        ROM_FlashProgram
-#else
-#define MAP_FlashProgram \
-        FlashProgram
-#endif
-#ifdef ROM_FlashUsecGet
-#define MAP_FlashUsecGet \
-        ROM_FlashUsecGet
-#else
-#define MAP_FlashUsecGet \
-        FlashUsecGet
-#endif
-#ifdef ROM_FlashUsecSet
-#define MAP_FlashUsecSet \
-        ROM_FlashUsecSet
-#else
-#define MAP_FlashUsecSet \
-        FlashUsecSet
-#endif
-#ifdef ROM_FlashErase
-#define MAP_FlashErase \
-        ROM_FlashErase
-#else
-#define MAP_FlashErase \
-        FlashErase
-#endif
-#ifdef ROM_FlashProtectGet
-#define MAP_FlashProtectGet \
-        ROM_FlashProtectGet
-#else
-#define MAP_FlashProtectGet \
-        FlashProtectGet
-#endif
-#ifdef ROM_FlashProtectSet
-#define MAP_FlashProtectSet \
-        ROM_FlashProtectSet
-#else
-#define MAP_FlashProtectSet \
-        FlashProtectSet
-#endif
-#ifdef ROM_FlashProtectSave
-#define MAP_FlashProtectSave \
-        ROM_FlashProtectSave
-#else
-#define MAP_FlashProtectSave \
-        FlashProtectSave
-#endif
-#ifdef ROM_FlashUserGet
-#define MAP_FlashUserGet \
-        ROM_FlashUserGet
-#else
-#define MAP_FlashUserGet \
-        FlashUserGet
-#endif
-#ifdef ROM_FlashUserSet
-#define MAP_FlashUserSet \
-        ROM_FlashUserSet
-#else
-#define MAP_FlashUserSet \
-        FlashUserSet
-#endif
-#ifdef ROM_FlashUserSave
-#define MAP_FlashUserSave \
-        ROM_FlashUserSave
-#else
-#define MAP_FlashUserSave \
-        FlashUserSave
-#endif
-#ifdef ROM_FlashIntEnable
-#define MAP_FlashIntEnable \
-        ROM_FlashIntEnable
-#else
-#define MAP_FlashIntEnable \
-        FlashIntEnable
-#endif
-#ifdef ROM_FlashIntDisable
-#define MAP_FlashIntDisable \
-        ROM_FlashIntDisable
-#else
-#define MAP_FlashIntDisable \
-        FlashIntDisable
-#endif
-#ifdef ROM_FlashIntStatus
-#define MAP_FlashIntStatus \
-        ROM_FlashIntStatus
-#else
-#define MAP_FlashIntStatus \
-        FlashIntStatus
-#endif
-#ifdef ROM_FlashIntClear
-#define MAP_FlashIntClear \
-        ROM_FlashIntClear
-#else
-#define MAP_FlashIntClear \
-        FlashIntClear
-#endif
-
-//*****************************************************************************
-//
-// Macros for the FPU API.
-//
-//*****************************************************************************
-#ifdef ROM_FPUEnable
-#define MAP_FPUEnable \
-        ROM_FPUEnable
-#else
-#define MAP_FPUEnable \
-        FPUEnable
-#endif
-#ifdef ROM_FPUDisable
-#define MAP_FPUDisable \
-        ROM_FPUDisable
-#else
-#define MAP_FPUDisable \
-        FPUDisable
-#endif
-#ifdef ROM_FPUFlushToZeroModeSet
-#define MAP_FPUFlushToZeroModeSet \
-        ROM_FPUFlushToZeroModeSet
-#else
-#define MAP_FPUFlushToZeroModeSet \
-        FPUFlushToZeroModeSet
-#endif
-#ifdef ROM_FPUHalfPrecisionModeSet
-#define MAP_FPUHalfPrecisionModeSet \
-        ROM_FPUHalfPrecisionModeSet
-#else
-#define MAP_FPUHalfPrecisionModeSet \
-        FPUHalfPrecisionModeSet
-#endif
-#ifdef ROM_FPULazyStackingEnable
-#define MAP_FPULazyStackingEnable \
-        ROM_FPULazyStackingEnable
-#else
-#define MAP_FPULazyStackingEnable \
-        FPULazyStackingEnable
-#endif
-#ifdef ROM_FPUNaNModeSet
-#define MAP_FPUNaNModeSet \
-        ROM_FPUNaNModeSet
-#else
-#define MAP_FPUNaNModeSet \
-        FPUNaNModeSet
-#endif
-#ifdef ROM_FPURoundingModeSet
-#define MAP_FPURoundingModeSet \
-        ROM_FPURoundingModeSet
-#else
-#define MAP_FPURoundingModeSet \
-        FPURoundingModeSet
-#endif
-#ifdef ROM_FPUStackingDisable
-#define MAP_FPUStackingDisable \
-        ROM_FPUStackingDisable
-#else
-#define MAP_FPUStackingDisable \
-        FPUStackingDisable
-#endif
-#ifdef ROM_FPUStackingEnable
-#define MAP_FPUStackingEnable \
-        ROM_FPUStackingEnable
-#else
-#define MAP_FPUStackingEnable \
-        FPUStackingEnable
-#endif
-
-//*****************************************************************************
-//
-// Macros for the GPIO API.
-//
-//*****************************************************************************
-#ifdef ROM_GPIOPinWrite
-#define MAP_GPIOPinWrite \
-        ROM_GPIOPinWrite
-#else
-#define MAP_GPIOPinWrite \
-        GPIOPinWrite
-#endif
-#ifdef ROM_GPIODirModeSet
-#define MAP_GPIODirModeSet \
-        ROM_GPIODirModeSet
-#else
-#define MAP_GPIODirModeSet \
-        GPIODirModeSet
-#endif
-#ifdef ROM_GPIODirModeGet
-#define MAP_GPIODirModeGet \
-        ROM_GPIODirModeGet
-#else
-#define MAP_GPIODirModeGet \
-        GPIODirModeGet
-#endif
-#ifdef ROM_GPIOIntTypeSet
-#define MAP_GPIOIntTypeSet \
-        ROM_GPIOIntTypeSet
-#else
-#define MAP_GPIOIntTypeSet \
-        GPIOIntTypeSet
-#endif
-#ifdef ROM_GPIOIntTypeGet
-#define MAP_GPIOIntTypeGet \
-        ROM_GPIOIntTypeGet
-#else
-#define MAP_GPIOIntTypeGet \
-        GPIOIntTypeGet
-#endif
-#ifdef ROM_GPIOPadConfigSet
-#define MAP_GPIOPadConfigSet \
-        ROM_GPIOPadConfigSet
-#else
-#define MAP_GPIOPadConfigSet \
-        GPIOPadConfigSet
-#endif
-#ifdef ROM_GPIOPadConfigGet
-#define MAP_GPIOPadConfigGet \
-        ROM_GPIOPadConfigGet
-#else
-#define MAP_GPIOPadConfigGet \
-        GPIOPadConfigGet
-#endif
-#ifdef ROM_GPIOPinIntEnable
-#define MAP_GPIOPinIntEnable \
-        ROM_GPIOPinIntEnable
-#else
-#define MAP_GPIOPinIntEnable \
-        GPIOPinIntEnable
-#endif
-#ifdef ROM_GPIOPinIntDisable
-#define MAP_GPIOPinIntDisable \
-        ROM_GPIOPinIntDisable
-#else
-#define MAP_GPIOPinIntDisable \
-        GPIOPinIntDisable
-#endif
-#ifdef ROM_GPIOPinIntStatus
-#define MAP_GPIOPinIntStatus \
-        ROM_GPIOPinIntStatus
-#else
-#define MAP_GPIOPinIntStatus \
-        GPIOPinIntStatus
-#endif
-#ifdef ROM_GPIOPinIntClear
-#define MAP_GPIOPinIntClear \
-        ROM_GPIOPinIntClear
-#else
-#define MAP_GPIOPinIntClear \
-        GPIOPinIntClear
-#endif
-#ifdef ROM_GPIOPinRead
-#define MAP_GPIOPinRead \
-        ROM_GPIOPinRead
-#else
-#define MAP_GPIOPinRead \
-        GPIOPinRead
-#endif
-#ifdef ROM_GPIOPinTypeCAN
-#define MAP_GPIOPinTypeCAN \
-        ROM_GPIOPinTypeCAN
-#else
-#define MAP_GPIOPinTypeCAN \
-        GPIOPinTypeCAN
-#endif
-#ifdef ROM_GPIOPinTypeComparator
-#define MAP_GPIOPinTypeComparator \
-        ROM_GPIOPinTypeComparator
-#else
-#define MAP_GPIOPinTypeComparator \
-        GPIOPinTypeComparator
-#endif
-#ifdef ROM_GPIOPinTypeGPIOInput
-#define MAP_GPIOPinTypeGPIOInput \
-        ROM_GPIOPinTypeGPIOInput
-#else
-#define MAP_GPIOPinTypeGPIOInput \
-        GPIOPinTypeGPIOInput
-#endif
-#ifdef ROM_GPIOPinTypeGPIOOutput
-#define MAP_GPIOPinTypeGPIOOutput \
-        ROM_GPIOPinTypeGPIOOutput
-#else
-#define MAP_GPIOPinTypeGPIOOutput \
-        GPIOPinTypeGPIOOutput
-#endif
-#ifdef ROM_GPIOPinTypeI2C
-#define MAP_GPIOPinTypeI2C \
-        ROM_GPIOPinTypeI2C
-#else
-#define MAP_GPIOPinTypeI2C \
-        GPIOPinTypeI2C
-#endif
-#ifdef ROM_GPIOPinTypePWM
-#define MAP_GPIOPinTypePWM \
-        ROM_GPIOPinTypePWM
-#else
-#define MAP_GPIOPinTypePWM \
-        GPIOPinTypePWM
-#endif
-#ifdef ROM_GPIOPinTypeQEI
-#define MAP_GPIOPinTypeQEI \
-        ROM_GPIOPinTypeQEI
-#else
-#define MAP_GPIOPinTypeQEI \
-        GPIOPinTypeQEI
-#endif
-#ifdef ROM_GPIOPinTypeSSI
-#define MAP_GPIOPinTypeSSI \
-        ROM_GPIOPinTypeSSI
-#else
-#define MAP_GPIOPinTypeSSI \
-        GPIOPinTypeSSI
-#endif
-#ifdef ROM_GPIOPinTypeTimer
-#define MAP_GPIOPinTypeTimer \
-        ROM_GPIOPinTypeTimer
-#else
-#define MAP_GPIOPinTypeTimer \
-        GPIOPinTypeTimer
-#endif
-#ifdef ROM_GPIOPinTypeUART
-#define MAP_GPIOPinTypeUART \
-        ROM_GPIOPinTypeUART
-#else
-#define MAP_GPIOPinTypeUART \
-        GPIOPinTypeUART
-#endif
-#ifdef ROM_GPIOPinTypeGPIOOutputOD
-#define MAP_GPIOPinTypeGPIOOutputOD \
-        ROM_GPIOPinTypeGPIOOutputOD
-#else
-#define MAP_GPIOPinTypeGPIOOutputOD \
-        GPIOPinTypeGPIOOutputOD
-#endif
-#ifdef ROM_GPIOPinTypeADC
-#define MAP_GPIOPinTypeADC \
-        ROM_GPIOPinTypeADC
-#else
-#define MAP_GPIOPinTypeADC \
-        GPIOPinTypeADC
-#endif
-#ifdef ROM_GPIOPinTypeUSBDigital
-#define MAP_GPIOPinTypeUSBDigital \
-        ROM_GPIOPinTypeUSBDigital
-#else
-#define MAP_GPIOPinTypeUSBDigital \
-        GPIOPinTypeUSBDigital
-#endif
-#ifdef ROM_GPIOPinTypeI2S
-#define MAP_GPIOPinTypeI2S \
-        ROM_GPIOPinTypeI2S
-#else
-#define MAP_GPIOPinTypeI2S \
-        GPIOPinTypeI2S
-#endif
-#ifdef ROM_GPIOPinConfigure
-#define MAP_GPIOPinConfigure \
-        ROM_GPIOPinConfigure
-#else
-#define MAP_GPIOPinConfigure \
-        GPIOPinConfigure
-#endif
-#ifdef ROM_GPIOPinTypeEthernetLED
-#define MAP_GPIOPinTypeEthernetLED \
-        ROM_GPIOPinTypeEthernetLED
-#else
-#define MAP_GPIOPinTypeEthernetLED \
-        GPIOPinTypeEthernetLED
-#endif
-#ifdef ROM_GPIOPinTypeUSBAnalog
-#define MAP_GPIOPinTypeUSBAnalog \
-        ROM_GPIOPinTypeUSBAnalog
-#else
-#define MAP_GPIOPinTypeUSBAnalog \
-        GPIOPinTypeUSBAnalog
-#endif
-#ifdef ROM_GPIOPinTypeEPI
-#define MAP_GPIOPinTypeEPI \
-        ROM_GPIOPinTypeEPI
-#else
-#define MAP_GPIOPinTypeEPI \
-        GPIOPinTypeEPI
-#endif
-#ifdef ROM_GPIOPinTypeEthernetMII
-#define MAP_GPIOPinTypeEthernetMII \
-        ROM_GPIOPinTypeEthernetMII
-#else
-#define MAP_GPIOPinTypeEthernetMII \
-        GPIOPinTypeEthernetMII
-#endif
-#ifdef ROM_GPIODMATriggerEnable
-#define MAP_GPIODMATriggerEnable \
-        ROM_GPIODMATriggerEnable
-#else
-#define MAP_GPIODMATriggerEnable \
-        GPIODMATriggerEnable
-#endif
-#ifdef ROM_GPIODMATriggerDisable
-#define MAP_GPIODMATriggerDisable \
-        ROM_GPIODMATriggerDisable
-#else
-#define MAP_GPIODMATriggerDisable \
-        GPIODMATriggerDisable
-#endif
-#ifdef ROM_GPIOADCTriggerEnable
-#define MAP_GPIOADCTriggerEnable \
-        ROM_GPIOADCTriggerEnable
-#else
-#define MAP_GPIOADCTriggerEnable \
-        GPIOADCTriggerEnable
-#endif
-#ifdef ROM_GPIOADCTriggerDisable
-#define MAP_GPIOADCTriggerDisable \
-        ROM_GPIOADCTriggerDisable
-#else
-#define MAP_GPIOADCTriggerDisable \
-        GPIOADCTriggerDisable
-#endif
-#ifdef ROM_GPIOPinTypeFan
-#define MAP_GPIOPinTypeFan \
-        ROM_GPIOPinTypeFan
-#else
-#define MAP_GPIOPinTypeFan \
-        GPIOPinTypeFan
-#endif
-#ifdef ROM_GPIOPinTypeLPC
-#define MAP_GPIOPinTypeLPC \
-        ROM_GPIOPinTypeLPC
-#else
-#define MAP_GPIOPinTypeLPC \
-        GPIOPinTypeLPC
-#endif
-#ifdef ROM_GPIOPinTypePECIRx
-#define MAP_GPIOPinTypePECIRx \
-        ROM_GPIOPinTypePECIRx
-#else
-#define MAP_GPIOPinTypePECIRx \
-        GPIOPinTypePECIRx
-#endif
-#ifdef ROM_GPIOPinTypePECITx
-#define MAP_GPIOPinTypePECITx \
-        ROM_GPIOPinTypePECITx
-#else
-#define MAP_GPIOPinTypePECITx \
-        GPIOPinTypePECITx
-#endif
-#ifdef ROM_GPIOPinTypeI2CSCL
-#define MAP_GPIOPinTypeI2CSCL \
-        ROM_GPIOPinTypeI2CSCL
-#else
-#define MAP_GPIOPinTypeI2CSCL \
-        GPIOPinTypeI2CSCL
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Hibernate API.
-//
-//*****************************************************************************
-#ifdef ROM_HibernateIntClear
-#define MAP_HibernateIntClear \
-        ROM_HibernateIntClear
-#else
-#define MAP_HibernateIntClear \
-        HibernateIntClear
-#endif
-#ifdef ROM_HibernateEnableExpClk
-#define MAP_HibernateEnableExpClk \
-        ROM_HibernateEnableExpClk
-#else
-#define MAP_HibernateEnableExpClk \
-        HibernateEnableExpClk
-#endif
-#ifdef ROM_HibernateDisable
-#define MAP_HibernateDisable \
-        ROM_HibernateDisable
-#else
-#define MAP_HibernateDisable \
-        HibernateDisable
-#endif
-#ifdef ROM_HibernateClockSelect
-#define MAP_HibernateClockSelect \
-        ROM_HibernateClockSelect
-#else
-#define MAP_HibernateClockSelect \
-        HibernateClockSelect
-#endif
-#ifdef ROM_HibernateRTCEnable
-#define MAP_HibernateRTCEnable \
-        ROM_HibernateRTCEnable
-#else
-#define MAP_HibernateRTCEnable \
-        HibernateRTCEnable
-#endif
-#ifdef ROM_HibernateRTCDisable
-#define MAP_HibernateRTCDisable \
-        ROM_HibernateRTCDisable
-#else
-#define MAP_HibernateRTCDisable \
-        HibernateRTCDisable
-#endif
-#ifdef ROM_HibernateWakeSet
-#define MAP_HibernateWakeSet \
-        ROM_HibernateWakeSet
-#else
-#define MAP_HibernateWakeSet \
-        HibernateWakeSet
-#endif
-#ifdef ROM_HibernateWakeGet
-#define MAP_HibernateWakeGet \
-        ROM_HibernateWakeGet
-#else
-#define MAP_HibernateWakeGet \
-        HibernateWakeGet
-#endif
-#ifdef ROM_HibernateLowBatSet
-#define MAP_HibernateLowBatSet \
-        ROM_HibernateLowBatSet
-#else
-#define MAP_HibernateLowBatSet \
-        HibernateLowBatSet
-#endif
-#ifdef ROM_HibernateLowBatGet
-#define MAP_HibernateLowBatGet \
-        ROM_HibernateLowBatGet
-#else
-#define MAP_HibernateLowBatGet \
-        HibernateLowBatGet
-#endif
-#ifdef ROM_HibernateRTCSet
-#define MAP_HibernateRTCSet \
-        ROM_HibernateRTCSet
-#else
-#define MAP_HibernateRTCSet \
-        HibernateRTCSet
-#endif
-#ifdef ROM_HibernateRTCGet
-#define MAP_HibernateRTCGet \
-        ROM_HibernateRTCGet
-#else
-#define MAP_HibernateRTCGet \
-        HibernateRTCGet
-#endif
-#ifdef ROM_HibernateRTCMatch0Set
-#define MAP_HibernateRTCMatch0Set \
-        ROM_HibernateRTCMatch0Set
-#else
-#define MAP_HibernateRTCMatch0Set \
-        HibernateRTCMatch0Set
-#endif
-#ifdef ROM_HibernateRTCMatch0Get
-#define MAP_HibernateRTCMatch0Get \
-        ROM_HibernateRTCMatch0Get
-#else
-#define MAP_HibernateRTCMatch0Get \
-        HibernateRTCMatch0Get
-#endif
-#ifdef ROM_HibernateRTCMatch1Set
-#define MAP_HibernateRTCMatch1Set \
-        ROM_HibernateRTCMatch1Set
-#else
-#define MAP_HibernateRTCMatch1Set \
-        HibernateRTCMatch1Set
-#endif
-#ifdef ROM_HibernateRTCMatch1Get
-#define MAP_HibernateRTCMatch1Get \
-        ROM_HibernateRTCMatch1Get
-#else
-#define MAP_HibernateRTCMatch1Get \
-        HibernateRTCMatch1Get
-#endif
-#ifdef ROM_HibernateRTCTrimSet
-#define MAP_HibernateRTCTrimSet \
-        ROM_HibernateRTCTrimSet
-#else
-#define MAP_HibernateRTCTrimSet \
-        HibernateRTCTrimSet
-#endif
-#ifdef ROM_HibernateRTCTrimGet
-#define MAP_HibernateRTCTrimGet \
-        ROM_HibernateRTCTrimGet
-#else
-#define MAP_HibernateRTCTrimGet \
-        HibernateRTCTrimGet
-#endif
-#ifdef ROM_HibernateDataSet
-#define MAP_HibernateDataSet \
-        ROM_HibernateDataSet
-#else
-#define MAP_HibernateDataSet \
-        HibernateDataSet
-#endif
-#ifdef ROM_HibernateDataGet
-#define MAP_HibernateDataGet \
-        ROM_HibernateDataGet
-#else
-#define MAP_HibernateDataGet \
-        HibernateDataGet
-#endif
-#ifdef ROM_HibernateRequest
-#define MAP_HibernateRequest \
-        ROM_HibernateRequest
-#else
-#define MAP_HibernateRequest \
-        HibernateRequest
-#endif
-#ifdef ROM_HibernateIntEnable
-#define MAP_HibernateIntEnable \
-        ROM_HibernateIntEnable
-#else
-#define MAP_HibernateIntEnable \
-        HibernateIntEnable
-#endif
-#ifdef ROM_HibernateIntDisable
-#define MAP_HibernateIntDisable \
-        ROM_HibernateIntDisable
-#else
-#define MAP_HibernateIntDisable \
-        HibernateIntDisable
-#endif
-#ifdef ROM_HibernateIntStatus
-#define MAP_HibernateIntStatus \
-        ROM_HibernateIntStatus
-#else
-#define MAP_HibernateIntStatus \
-        HibernateIntStatus
-#endif
-#ifdef ROM_HibernateIsActive
-#define MAP_HibernateIsActive \
-        ROM_HibernateIsActive
-#else
-#define MAP_HibernateIsActive \
-        HibernateIsActive
-#endif
-#ifdef ROM_HibernateRTCSSMatch0Set
-#define MAP_HibernateRTCSSMatch0Set \
-        ROM_HibernateRTCSSMatch0Set
-#else
-#define MAP_HibernateRTCSSMatch0Set \
-        HibernateRTCSSMatch0Set
-#endif
-#ifdef ROM_HibernateRTCSSMatch0Get
-#define MAP_HibernateRTCSSMatch0Get \
-        ROM_HibernateRTCSSMatch0Get
-#else
-#define MAP_HibernateRTCSSMatch0Get \
-        HibernateRTCSSMatch0Get
-#endif
-#ifdef ROM_HibernateRTCSSGet
-#define MAP_HibernateRTCSSGet \
-        ROM_HibernateRTCSSGet
-#else
-#define MAP_HibernateRTCSSGet \
-        HibernateRTCSSGet
-#endif
-#ifdef ROM_HibernateClockConfig
-#define MAP_HibernateClockConfig \
-        ROM_HibernateClockConfig
-#else
-#define MAP_HibernateClockConfig \
-        HibernateClockConfig
-#endif
-#ifdef ROM_HibernateBatCheckStart
-#define MAP_HibernateBatCheckStart \
-        ROM_HibernateBatCheckStart
-#else
-#define MAP_HibernateBatCheckStart \
-        HibernateBatCheckStart
-#endif
-#ifdef ROM_HibernateBatCheckDone
-#define MAP_HibernateBatCheckDone \
-        ROM_HibernateBatCheckDone
-#else
-#define MAP_HibernateBatCheckDone \
-        HibernateBatCheckDone
-#endif
-
-//*****************************************************************************
-//
-// Macros for the I2C API.
-//
-//*****************************************************************************
-#ifdef ROM_I2CMasterDataPut
-#define MAP_I2CMasterDataPut \
-        ROM_I2CMasterDataPut
-#else
-#define MAP_I2CMasterDataPut \
-        I2CMasterDataPut
-#endif
-#ifdef ROM_I2CMasterInitExpClk
-#define MAP_I2CMasterInitExpClk \
-        ROM_I2CMasterInitExpClk
-#else
-#define MAP_I2CMasterInitExpClk \
-        I2CMasterInitExpClk
-#endif
-#ifdef ROM_I2CSlaveInit
-#define MAP_I2CSlaveInit \
-        ROM_I2CSlaveInit
-#else
-#define MAP_I2CSlaveInit \
-        I2CSlaveInit
-#endif
-#ifdef ROM_I2CMasterEnable
-#define MAP_I2CMasterEnable \
-        ROM_I2CMasterEnable
-#else
-#define MAP_I2CMasterEnable \
-        I2CMasterEnable
-#endif
-#ifdef ROM_I2CSlaveEnable
-#define MAP_I2CSlaveEnable \
-        ROM_I2CSlaveEnable
-#else
-#define MAP_I2CSlaveEnable \
-        I2CSlaveEnable
-#endif
-#ifdef ROM_I2CMasterDisable
-#define MAP_I2CMasterDisable \
-        ROM_I2CMasterDisable
-#else
-#define MAP_I2CMasterDisable \
-        I2CMasterDisable
-#endif
-#ifdef ROM_I2CSlaveDisable
-#define MAP_I2CSlaveDisable \
-        ROM_I2CSlaveDisable
-#else
-#define MAP_I2CSlaveDisable \
-        I2CSlaveDisable
-#endif
-#ifdef ROM_I2CMasterIntEnable
-#define MAP_I2CMasterIntEnable \
-        ROM_I2CMasterIntEnable
-#else
-#define MAP_I2CMasterIntEnable \
-        I2CMasterIntEnable
-#endif
-#ifdef ROM_I2CSlaveIntEnable
-#define MAP_I2CSlaveIntEnable \
-        ROM_I2CSlaveIntEnable
-#else
-#define MAP_I2CSlaveIntEnable \
-        I2CSlaveIntEnable
-#endif
-#ifdef ROM_I2CMasterIntDisable
-#define MAP_I2CMasterIntDisable \
-        ROM_I2CMasterIntDisable
-#else
-#define MAP_I2CMasterIntDisable \
-        I2CMasterIntDisable
-#endif
-#ifdef ROM_I2CSlaveIntDisable
-#define MAP_I2CSlaveIntDisable \
-        ROM_I2CSlaveIntDisable
-#else
-#define MAP_I2CSlaveIntDisable \
-        I2CSlaveIntDisable
-#endif
-#ifdef ROM_I2CMasterIntStatus
-#define MAP_I2CMasterIntStatus \
-        ROM_I2CMasterIntStatus
-#else
-#define MAP_I2CMasterIntStatus \
-        I2CMasterIntStatus
-#endif
-#ifdef ROM_I2CSlaveIntStatus
-#define MAP_I2CSlaveIntStatus \
-        ROM_I2CSlaveIntStatus
-#else
-#define MAP_I2CSlaveIntStatus \
-        I2CSlaveIntStatus
-#endif
-#ifdef ROM_I2CMasterIntClear
-#define MAP_I2CMasterIntClear \
-        ROM_I2CMasterIntClear
-#else
-#define MAP_I2CMasterIntClear \
-        I2CMasterIntClear
-#endif
-#ifdef ROM_I2CSlaveIntClear
-#define MAP_I2CSlaveIntClear \
-        ROM_I2CSlaveIntClear
-#else
-#define MAP_I2CSlaveIntClear \
-        I2CSlaveIntClear
-#endif
-#ifdef ROM_I2CMasterSlaveAddrSet
-#define MAP_I2CMasterSlaveAddrSet \
-        ROM_I2CMasterSlaveAddrSet
-#else
-#define MAP_I2CMasterSlaveAddrSet \
-        I2CMasterSlaveAddrSet
-#endif
-#ifdef ROM_I2CMasterBusy
-#define MAP_I2CMasterBusy \
-        ROM_I2CMasterBusy
-#else
-#define MAP_I2CMasterBusy \
-        I2CMasterBusy
-#endif
-#ifdef ROM_I2CMasterBusBusy
-#define MAP_I2CMasterBusBusy \
-        ROM_I2CMasterBusBusy
-#else
-#define MAP_I2CMasterBusBusy \
-        I2CMasterBusBusy
-#endif
-#ifdef ROM_I2CMasterControl
-#define MAP_I2CMasterControl \
-        ROM_I2CMasterControl
-#else
-#define MAP_I2CMasterControl \
-        I2CMasterControl
-#endif
-#ifdef ROM_I2CMasterErr
-#define MAP_I2CMasterErr \
-        ROM_I2CMasterErr
-#else
-#define MAP_I2CMasterErr \
-        I2CMasterErr
-#endif
-#ifdef ROM_I2CMasterDataGet
-#define MAP_I2CMasterDataGet \
-        ROM_I2CMasterDataGet
-#else
-#define MAP_I2CMasterDataGet \
-        I2CMasterDataGet
-#endif
-#ifdef ROM_I2CSlaveStatus
-#define MAP_I2CSlaveStatus \
-        ROM_I2CSlaveStatus
-#else
-#define MAP_I2CSlaveStatus \
-        I2CSlaveStatus
-#endif
-#ifdef ROM_I2CSlaveDataPut
-#define MAP_I2CSlaveDataPut \
-        ROM_I2CSlaveDataPut
-#else
-#define MAP_I2CSlaveDataPut \
-        I2CSlaveDataPut
-#endif
-#ifdef ROM_I2CSlaveDataGet
-#define MAP_I2CSlaveDataGet \
-        ROM_I2CSlaveDataGet
-#else
-#define MAP_I2CSlaveDataGet \
-        I2CSlaveDataGet
-#endif
-#ifdef ROM_I2CSlaveIntEnableEx
-#define MAP_I2CSlaveIntEnableEx \
-        ROM_I2CSlaveIntEnableEx
-#else
-#define MAP_I2CSlaveIntEnableEx \
-        I2CSlaveIntEnableEx
-#endif
-#ifdef ROM_I2CSlaveIntDisableEx
-#define MAP_I2CSlaveIntDisableEx \
-        ROM_I2CSlaveIntDisableEx
-#else
-#define MAP_I2CSlaveIntDisableEx \
-        I2CSlaveIntDisableEx
-#endif
-#ifdef ROM_I2CSlaveIntStatusEx
-#define MAP_I2CSlaveIntStatusEx \
-        ROM_I2CSlaveIntStatusEx
-#else
-#define MAP_I2CSlaveIntStatusEx \
-        I2CSlaveIntStatusEx
-#endif
-#ifdef ROM_I2CSlaveIntClearEx
-#define MAP_I2CSlaveIntClearEx \
-        ROM_I2CSlaveIntClearEx
-#else
-#define MAP_I2CSlaveIntClearEx \
-        I2CSlaveIntClearEx
-#endif
-#ifdef ROM_I2CMasterIntEnableEx
-#define MAP_I2CMasterIntEnableEx \
-        ROM_I2CMasterIntEnableEx
-#else
-#define MAP_I2CMasterIntEnableEx \
-        I2CMasterIntEnableEx
-#endif
-#ifdef ROM_I2CMasterIntDisableEx
-#define MAP_I2CMasterIntDisableEx \
-        ROM_I2CMasterIntDisableEx
-#else
-#define MAP_I2CMasterIntDisableEx \
-        I2CMasterIntDisableEx
-#endif
-#ifdef ROM_I2CMasterIntStatusEx
-#define MAP_I2CMasterIntStatusEx \
-        ROM_I2CMasterIntStatusEx
-#else
-#define MAP_I2CMasterIntStatusEx \
-        I2CMasterIntStatusEx
-#endif
-#ifdef ROM_I2CMasterIntClearEx
-#define MAP_I2CMasterIntClearEx \
-        ROM_I2CMasterIntClearEx
-#else
-#define MAP_I2CMasterIntClearEx \
-        I2CMasterIntClearEx
-#endif
-#ifdef ROM_I2CMasterTimeoutSet
-#define MAP_I2CMasterTimeoutSet \
-        ROM_I2CMasterTimeoutSet
-#else
-#define MAP_I2CMasterTimeoutSet \
-        I2CMasterTimeoutSet
-#endif
-#ifdef ROM_I2CSlaveACKOverride
-#define MAP_I2CSlaveACKOverride \
-        ROM_I2CSlaveACKOverride
-#else
-#define MAP_I2CSlaveACKOverride \
-        I2CSlaveACKOverride
-#endif
-#ifdef ROM_I2CSlaveACKValueSet
-#define MAP_I2CSlaveACKValueSet \
-        ROM_I2CSlaveACKValueSet
-#else
-#define MAP_I2CSlaveACKValueSet \
-        I2CSlaveACKValueSet
-#endif
-#ifdef ROM_I2CSlaveAddressSet
-#define MAP_I2CSlaveAddressSet \
-        ROM_I2CSlaveAddressSet
-#else
-#define MAP_I2CSlaveAddressSet \
-        I2CSlaveAddressSet
-#endif
-#ifdef ROM_I2CMasterLineStateGet
-#define MAP_I2CMasterLineStateGet \
-        ROM_I2CMasterLineStateGet
-#else
-#define MAP_I2CMasterLineStateGet \
-        I2CMasterLineStateGet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the I2S API.
-//
-//*****************************************************************************
-#ifdef ROM_I2SIntStatus
-#define MAP_I2SIntStatus \
-        ROM_I2SIntStatus
-#else
-#define MAP_I2SIntStatus \
-        I2SIntStatus
-#endif
-#ifdef ROM_I2STxEnable
-#define MAP_I2STxEnable \
-        ROM_I2STxEnable
-#else
-#define MAP_I2STxEnable \
-        I2STxEnable
-#endif
-#ifdef ROM_I2STxDisable
-#define MAP_I2STxDisable \
-        ROM_I2STxDisable
-#else
-#define MAP_I2STxDisable \
-        I2STxDisable
-#endif
-#ifdef ROM_I2STxDataPut
-#define MAP_I2STxDataPut \
-        ROM_I2STxDataPut
-#else
-#define MAP_I2STxDataPut \
-        I2STxDataPut
-#endif
-#ifdef ROM_I2STxDataPutNonBlocking
-#define MAP_I2STxDataPutNonBlocking \
-        ROM_I2STxDataPutNonBlocking
-#else
-#define MAP_I2STxDataPutNonBlocking \
-        I2STxDataPutNonBlocking
-#endif
-#ifdef ROM_I2STxConfigSet
-#define MAP_I2STxConfigSet \
-        ROM_I2STxConfigSet
-#else
-#define MAP_I2STxConfigSet \
-        I2STxConfigSet
-#endif
-#ifdef ROM_I2STxFIFOLimitSet
-#define MAP_I2STxFIFOLimitSet \
-        ROM_I2STxFIFOLimitSet
-#else
-#define MAP_I2STxFIFOLimitSet \
-        I2STxFIFOLimitSet
-#endif
-#ifdef ROM_I2STxFIFOLimitGet
-#define MAP_I2STxFIFOLimitGet \
-        ROM_I2STxFIFOLimitGet
-#else
-#define MAP_I2STxFIFOLimitGet \
-        I2STxFIFOLimitGet
-#endif
-#ifdef ROM_I2STxFIFOLevelGet
-#define MAP_I2STxFIFOLevelGet \
-        ROM_I2STxFIFOLevelGet
-#else
-#define MAP_I2STxFIFOLevelGet \
-        I2STxFIFOLevelGet
-#endif
-#ifdef ROM_I2SRxEnable
-#define MAP_I2SRxEnable \
-        ROM_I2SRxEnable
-#else
-#define MAP_I2SRxEnable \
-        I2SRxEnable
-#endif
-#ifdef ROM_I2SRxDisable
-#define MAP_I2SRxDisable \
-        ROM_I2SRxDisable
-#else
-#define MAP_I2SRxDisable \
-        I2SRxDisable
-#endif
-#ifdef ROM_I2SRxDataGet
-#define MAP_I2SRxDataGet \
-        ROM_I2SRxDataGet
-#else
-#define MAP_I2SRxDataGet \
-        I2SRxDataGet
-#endif
-#ifdef ROM_I2SRxDataGetNonBlocking
-#define MAP_I2SRxDataGetNonBlocking \
-        ROM_I2SRxDataGetNonBlocking
-#else
-#define MAP_I2SRxDataGetNonBlocking \
-        I2SRxDataGetNonBlocking
-#endif
-#ifdef ROM_I2SRxConfigSet
-#define MAP_I2SRxConfigSet \
-        ROM_I2SRxConfigSet
-#else
-#define MAP_I2SRxConfigSet \
-        I2SRxConfigSet
-#endif
-#ifdef ROM_I2SRxFIFOLimitSet
-#define MAP_I2SRxFIFOLimitSet \
-        ROM_I2SRxFIFOLimitSet
-#else
-#define MAP_I2SRxFIFOLimitSet \
-        I2SRxFIFOLimitSet
-#endif
-#ifdef ROM_I2SRxFIFOLimitGet
-#define MAP_I2SRxFIFOLimitGet \
-        ROM_I2SRxFIFOLimitGet
-#else
-#define MAP_I2SRxFIFOLimitGet \
-        I2SRxFIFOLimitGet
-#endif
-#ifdef ROM_I2SRxFIFOLevelGet
-#define MAP_I2SRxFIFOLevelGet \
-        ROM_I2SRxFIFOLevelGet
-#else
-#define MAP_I2SRxFIFOLevelGet \
-        I2SRxFIFOLevelGet
-#endif
-#ifdef ROM_I2STxRxEnable
-#define MAP_I2STxRxEnable \
-        ROM_I2STxRxEnable
-#else
-#define MAP_I2STxRxEnable \
-        I2STxRxEnable
-#endif
-#ifdef ROM_I2STxRxDisable
-#define MAP_I2STxRxDisable \
-        ROM_I2STxRxDisable
-#else
-#define MAP_I2STxRxDisable \
-        I2STxRxDisable
-#endif
-#ifdef ROM_I2STxRxConfigSet
-#define MAP_I2STxRxConfigSet \
-        ROM_I2STxRxConfigSet
-#else
-#define MAP_I2STxRxConfigSet \
-        I2STxRxConfigSet
-#endif
-#ifdef ROM_I2SMasterClockSelect
-#define MAP_I2SMasterClockSelect \
-        ROM_I2SMasterClockSelect
-#else
-#define MAP_I2SMasterClockSelect \
-        I2SMasterClockSelect
-#endif
-#ifdef ROM_I2SIntEnable
-#define MAP_I2SIntEnable \
-        ROM_I2SIntEnable
-#else
-#define MAP_I2SIntEnable \
-        I2SIntEnable
-#endif
-#ifdef ROM_I2SIntDisable
-#define MAP_I2SIntDisable \
-        ROM_I2SIntDisable
-#else
-#define MAP_I2SIntDisable \
-        I2SIntDisable
-#endif
-#ifdef ROM_I2SIntClear
-#define MAP_I2SIntClear \
-        ROM_I2SIntClear
-#else
-#define MAP_I2SIntClear \
-        I2SIntClear
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Interrupt API.
-//
-//*****************************************************************************
-#ifdef ROM_IntEnable
-#define MAP_IntEnable \
-        ROM_IntEnable
-#else
-#define MAP_IntEnable \
-        IntEnable
-#endif
-#ifdef ROM_IntMasterEnable
-#define MAP_IntMasterEnable \
-        ROM_IntMasterEnable
-#else
-#define MAP_IntMasterEnable \
-        IntMasterEnable
-#endif
-#ifdef ROM_IntMasterDisable
-#define MAP_IntMasterDisable \
-        ROM_IntMasterDisable
-#else
-#define MAP_IntMasterDisable \
-        IntMasterDisable
-#endif
-#ifdef ROM_IntDisable
-#define MAP_IntDisable \
-        ROM_IntDisable
-#else
-#define MAP_IntDisable \
-        IntDisable
-#endif
-#ifdef ROM_IntPriorityGroupingSet
-#define MAP_IntPriorityGroupingSet \
-        ROM_IntPriorityGroupingSet
-#else
-#define MAP_IntPriorityGroupingSet \
-        IntPriorityGroupingSet
-#endif
-#ifdef ROM_IntPriorityGroupingGet
-#define MAP_IntPriorityGroupingGet \
-        ROM_IntPriorityGroupingGet
-#else
-#define MAP_IntPriorityGroupingGet \
-        IntPriorityGroupingGet
-#endif
-#ifdef ROM_IntPrioritySet
-#define MAP_IntPrioritySet \
-        ROM_IntPrioritySet
-#else
-#define MAP_IntPrioritySet \
-        IntPrioritySet
-#endif
-#ifdef ROM_IntPriorityGet
-#define MAP_IntPriorityGet \
-        ROM_IntPriorityGet
-#else
-#define MAP_IntPriorityGet \
-        IntPriorityGet
-#endif
-#ifdef ROM_IntPendSet
-#define MAP_IntPendSet \
-        ROM_IntPendSet
-#else
-#define MAP_IntPendSet \
-        IntPendSet
-#endif
-#ifdef ROM_IntPendClear
-#define MAP_IntPendClear \
-        ROM_IntPendClear
-#else
-#define MAP_IntPendClear \
-        IntPendClear
-#endif
-#ifdef ROM_IntPriorityMaskSet
-#define MAP_IntPriorityMaskSet \
-        ROM_IntPriorityMaskSet
-#else
-#define MAP_IntPriorityMaskSet \
-        IntPriorityMaskSet
-#endif
-#ifdef ROM_IntPriorityMaskGet
-#define MAP_IntPriorityMaskGet \
-        ROM_IntPriorityMaskGet
-#else
-#define MAP_IntPriorityMaskGet \
-        IntPriorityMaskGet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the LPC API.
-//
-//*****************************************************************************
-#ifdef ROM_LPCIntClear
-#define MAP_LPCIntClear \
-        ROM_LPCIntClear
-#else
-#define MAP_LPCIntClear \
-        LPCIntClear
-#endif
-#ifdef ROM_LPCByteRead
-#define MAP_LPCByteRead \
-        ROM_LPCByteRead
-#else
-#define MAP_LPCByteRead \
-        LPCByteRead
-#endif
-#ifdef ROM_LPCByteWrite
-#define MAP_LPCByteWrite \
-        ROM_LPCByteWrite
-#else
-#define MAP_LPCByteWrite \
-        LPCByteWrite
-#endif
-#ifdef ROM_LPCChannelConfigCOMxSet
-#define MAP_LPCChannelConfigCOMxSet \
-        ROM_LPCChannelConfigCOMxSet
-#else
-#define MAP_LPCChannelConfigCOMxSet \
-        LPCChannelConfigCOMxSet
-#endif
-#ifdef ROM_LPCChannelConfigGet
-#define MAP_LPCChannelConfigGet \
-        ROM_LPCChannelConfigGet
-#else
-#define MAP_LPCChannelConfigGet \
-        LPCChannelConfigGet
-#endif
-#ifdef ROM_LPCChannelConfigEPSet
-#define MAP_LPCChannelConfigEPSet \
-        ROM_LPCChannelConfigEPSet
-#else
-#define MAP_LPCChannelConfigEPSet \
-        LPCChannelConfigEPSet
-#endif
-#ifdef ROM_LPCChannelConfigMBSet
-#define MAP_LPCChannelConfigMBSet \
-        ROM_LPCChannelConfigMBSet
-#else
-#define MAP_LPCChannelConfigMBSet \
-        LPCChannelConfigMBSet
-#endif
-#ifdef ROM_LPCChannelDMAConfigGet
-#define MAP_LPCChannelDMAConfigGet \
-        ROM_LPCChannelDMAConfigGet
-#else
-#define MAP_LPCChannelDMAConfigGet \
-        LPCChannelDMAConfigGet
-#endif
-#ifdef ROM_LPCChannelDMAConfigSet
-#define MAP_LPCChannelDMAConfigSet \
-        ROM_LPCChannelDMAConfigSet
-#else
-#define MAP_LPCChannelDMAConfigSet \
-        LPCChannelDMAConfigSet
-#endif
-#ifdef ROM_LPCChannelDisable
-#define MAP_LPCChannelDisable \
-        ROM_LPCChannelDisable
-#else
-#define MAP_LPCChannelDisable \
-        LPCChannelDisable
-#endif
-#ifdef ROM_LPCChannelEnable
-#define MAP_LPCChannelEnable \
-        ROM_LPCChannelEnable
-#else
-#define MAP_LPCChannelEnable \
-        LPCChannelEnable
-#endif
-#ifdef ROM_LPCChannelStatusClear
-#define MAP_LPCChannelStatusClear \
-        ROM_LPCChannelStatusClear
-#else
-#define MAP_LPCChannelStatusClear \
-        LPCChannelStatusClear
-#endif
-#ifdef ROM_LPCChannelStatusGet
-#define MAP_LPCChannelStatusGet \
-        ROM_LPCChannelStatusGet
-#else
-#define MAP_LPCChannelStatusGet \
-        LPCChannelStatusGet
-#endif
-#ifdef ROM_LPCChannelStatusSet
-#define MAP_LPCChannelStatusSet \
-        ROM_LPCChannelStatusSet
-#else
-#define MAP_LPCChannelStatusSet \
-        LPCChannelStatusSet
-#endif
-#ifdef ROM_LPCCOMxIntClear
-#define MAP_LPCCOMxIntClear \
-        ROM_LPCCOMxIntClear
-#else
-#define MAP_LPCCOMxIntClear \
-        LPCCOMxIntClear
-#endif
-#ifdef ROM_LPCCOMxIntDisable
-#define MAP_LPCCOMxIntDisable \
-        ROM_LPCCOMxIntDisable
-#else
-#define MAP_LPCCOMxIntDisable \
-        LPCCOMxIntDisable
-#endif
-#ifdef ROM_LPCCOMxIntEnable
-#define MAP_LPCCOMxIntEnable \
-        ROM_LPCCOMxIntEnable
-#else
-#define MAP_LPCCOMxIntEnable \
-        LPCCOMxIntEnable
-#endif
-#ifdef ROM_LPCCOMxIntStatus
-#define MAP_LPCCOMxIntStatus \
-        ROM_LPCCOMxIntStatus
-#else
-#define MAP_LPCCOMxIntStatus \
-        LPCCOMxIntStatus
-#endif
-#ifdef ROM_LPCConfigGet
-#define MAP_LPCConfigGet \
-        ROM_LPCConfigGet
-#else
-#define MAP_LPCConfigGet \
-        LPCConfigGet
-#endif
-#ifdef ROM_LPCConfigSet
-#define MAP_LPCConfigSet \
-        ROM_LPCConfigSet
-#else
-#define MAP_LPCConfigSet \
-        LPCConfigSet
-#endif
-#ifdef ROM_LPCHalfWordRead
-#define MAP_LPCHalfWordRead \
-        ROM_LPCHalfWordRead
-#else
-#define MAP_LPCHalfWordRead \
-        LPCHalfWordRead
-#endif
-#ifdef ROM_LPCHalfWordWrite
-#define MAP_LPCHalfWordWrite \
-        ROM_LPCHalfWordWrite
-#else
-#define MAP_LPCHalfWordWrite \
-        LPCHalfWordWrite
-#endif
-#ifdef ROM_LPCIRQClear
-#define MAP_LPCIRQClear \
-        ROM_LPCIRQClear
-#else
-#define MAP_LPCIRQClear \
-        LPCIRQClear
-#endif
-#ifdef ROM_LPCIRQConfig
-#define MAP_LPCIRQConfig \
-        ROM_LPCIRQConfig
-#else
-#define MAP_LPCIRQConfig \
-        LPCIRQConfig
-#endif
-#ifdef ROM_LPCIRQGet
-#define MAP_LPCIRQGet \
-        ROM_LPCIRQGet
-#else
-#define MAP_LPCIRQGet \
-        LPCIRQGet
-#endif
-#ifdef ROM_LPCIRQSend
-#define MAP_LPCIRQSend \
-        ROM_LPCIRQSend
-#else
-#define MAP_LPCIRQSend \
-        LPCIRQSend
-#endif
-#ifdef ROM_LPCIRQSet
-#define MAP_LPCIRQSet \
-        ROM_LPCIRQSet
-#else
-#define MAP_LPCIRQSet \
-        LPCIRQSet
-#endif
-#ifdef ROM_LPCIntDisable
-#define MAP_LPCIntDisable \
-        ROM_LPCIntDisable
-#else
-#define MAP_LPCIntDisable \
-        LPCIntDisable
-#endif
-#ifdef ROM_LPCIntEnable
-#define MAP_LPCIntEnable \
-        ROM_LPCIntEnable
-#else
-#define MAP_LPCIntEnable \
-        LPCIntEnable
-#endif
-#ifdef ROM_LPCIntStatus
-#define MAP_LPCIntStatus \
-        ROM_LPCIntStatus
-#else
-#define MAP_LPCIntStatus \
-        LPCIntStatus
-#endif
-#ifdef ROM_LPCSCIAssert
-#define MAP_LPCSCIAssert \
-        ROM_LPCSCIAssert
-#else
-#define MAP_LPCSCIAssert \
-        LPCSCIAssert
-#endif
-#ifdef ROM_LPCStatusGet
-#define MAP_LPCStatusGet \
-        ROM_LPCStatusGet
-#else
-#define MAP_LPCStatusGet \
-        LPCStatusGet
-#endif
-#ifdef ROM_LPCWordRead
-#define MAP_LPCWordRead \
-        ROM_LPCWordRead
-#else
-#define MAP_LPCWordRead \
-        LPCWordRead
-#endif
-#ifdef ROM_LPCWordWrite
-#define MAP_LPCWordWrite \
-        ROM_LPCWordWrite
-#else
-#define MAP_LPCWordWrite \
-        LPCWordWrite
-#endif
-#ifdef ROM_LPCChannelPoolAddressGet
-#define MAP_LPCChannelPoolAddressGet \
-        ROM_LPCChannelPoolAddressGet
-#else
-#define MAP_LPCChannelPoolAddressGet \
-        LPCChannelPoolAddressGet
-#endif
-#ifdef ROM_LPCStatusBlockAddressGet
-#define MAP_LPCStatusBlockAddressGet \
-        ROM_LPCStatusBlockAddressGet
-#else
-#define MAP_LPCStatusBlockAddressGet \
-        LPCStatusBlockAddressGet
-#endif
-#ifdef ROM_LPCStatusBlockAddressSet
-#define MAP_LPCStatusBlockAddressSet \
-        ROM_LPCStatusBlockAddressSet
-#else
-#define MAP_LPCStatusBlockAddressSet \
-        LPCStatusBlockAddressSet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the MPU API.
-//
-//*****************************************************************************
-#ifdef ROM_MPUEnable
-#define MAP_MPUEnable \
-        ROM_MPUEnable
-#else
-#define MAP_MPUEnable \
-        MPUEnable
-#endif
-#ifdef ROM_MPUDisable
-#define MAP_MPUDisable \
-        ROM_MPUDisable
-#else
-#define MAP_MPUDisable \
-        MPUDisable
-#endif
-#ifdef ROM_MPURegionCountGet
-#define MAP_MPURegionCountGet \
-        ROM_MPURegionCountGet
-#else
-#define MAP_MPURegionCountGet \
-        MPURegionCountGet
-#endif
-#ifdef ROM_MPURegionEnable
-#define MAP_MPURegionEnable \
-        ROM_MPURegionEnable
-#else
-#define MAP_MPURegionEnable \
-        MPURegionEnable
-#endif
-#ifdef ROM_MPURegionDisable
-#define MAP_MPURegionDisable \
-        ROM_MPURegionDisable
-#else
-#define MAP_MPURegionDisable \
-        MPURegionDisable
-#endif
-#ifdef ROM_MPURegionSet
-#define MAP_MPURegionSet \
-        ROM_MPURegionSet
-#else
-#define MAP_MPURegionSet \
-        MPURegionSet
-#endif
-#ifdef ROM_MPURegionGet
-#define MAP_MPURegionGet \
-        ROM_MPURegionGet
-#else
-#define MAP_MPURegionGet \
-        MPURegionGet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the PECI API.
-//
-//*****************************************************************************
-#ifdef ROM_PECIIntClear
-#define MAP_PECIIntClear \
-        ROM_PECIIntClear
-#else
-#define MAP_PECIIntClear \
-        PECIIntClear
-#endif
-#ifdef ROM_PECIAdvCmdSend
-#define MAP_PECIAdvCmdSend \
-        ROM_PECIAdvCmdSend
-#else
-#define MAP_PECIAdvCmdSend \
-        PECIAdvCmdSend
-#endif
-#ifdef ROM_PECIAdvCmdSendNonBlocking
-#define MAP_PECIAdvCmdSendNonBlocking \
-        ROM_PECIAdvCmdSendNonBlocking
-#else
-#define MAP_PECIAdvCmdSendNonBlocking \
-        PECIAdvCmdSendNonBlocking
-#endif
-#ifdef ROM_PECIAdvCmdStatusGet
-#define MAP_PECIAdvCmdStatusGet \
-        ROM_PECIAdvCmdStatusGet
-#else
-#define MAP_PECIAdvCmdStatusGet \
-        PECIAdvCmdStatusGet
-#endif
-#ifdef ROM_PECIConfigGet
-#define MAP_PECIConfigGet \
-        ROM_PECIConfigGet
-#else
-#define MAP_PECIConfigGet \
-        PECIConfigGet
-#endif
-#ifdef ROM_PECIConfigSet
-#define MAP_PECIConfigSet \
-        ROM_PECIConfigSet
-#else
-#define MAP_PECIConfigSet \
-        PECIConfigSet
-#endif
-#ifdef ROM_PECIDomainMaxReadClear
-#define MAP_PECIDomainMaxReadClear \
-        ROM_PECIDomainMaxReadClear
-#else
-#define MAP_PECIDomainMaxReadClear \
-        PECIDomainMaxReadClear
-#endif
-#ifdef ROM_PECIDomainValueClear
-#define MAP_PECIDomainValueClear \
-        ROM_PECIDomainValueClear
-#else
-#define MAP_PECIDomainValueClear \
-        PECIDomainValueClear
-#endif
-#ifdef ROM_PECIDomainConfigGet
-#define MAP_PECIDomainConfigGet \
-        ROM_PECIDomainConfigGet
-#else
-#define MAP_PECIDomainConfigGet \
-        PECIDomainConfigGet
-#endif
-#ifdef ROM_PECIDomainConfigSet
-#define MAP_PECIDomainConfigSet \
-        ROM_PECIDomainConfigSet
-#else
-#define MAP_PECIDomainConfigSet \
-        PECIDomainConfigSet
-#endif
-#ifdef ROM_PECIDomainDisable
-#define MAP_PECIDomainDisable \
-        ROM_PECIDomainDisable
-#else
-#define MAP_PECIDomainDisable \
-        PECIDomainDisable
-#endif
-#ifdef ROM_PECIDomainEnable
-#define MAP_PECIDomainEnable \
-        ROM_PECIDomainEnable
-#else
-#define MAP_PECIDomainEnable \
-        PECIDomainEnable
-#endif
-#ifdef ROM_PECIDomainMaxReadGet
-#define MAP_PECIDomainMaxReadGet \
-        ROM_PECIDomainMaxReadGet
-#else
-#define MAP_PECIDomainMaxReadGet \
-        PECIDomainMaxReadGet
-#endif
-#ifdef ROM_PECIDomainValueGet
-#define MAP_PECIDomainValueGet \
-        ROM_PECIDomainValueGet
-#else
-#define MAP_PECIDomainValueGet \
-        PECIDomainValueGet
-#endif
-#ifdef ROM_PECIIntDisable
-#define MAP_PECIIntDisable \
-        ROM_PECIIntDisable
-#else
-#define MAP_PECIIntDisable \
-        PECIIntDisable
-#endif
-#ifdef ROM_PECIIntEnable
-#define MAP_PECIIntEnable \
-        ROM_PECIIntEnable
-#else
-#define MAP_PECIIntEnable \
-        PECIIntEnable
-#endif
-#ifdef ROM_PECIIntStatus
-#define MAP_PECIIntStatus \
-        ROM_PECIIntStatus
-#else
-#define MAP_PECIIntStatus \
-        PECIIntStatus
-#endif
-#ifdef ROM_PECIBypassEnable
-#define MAP_PECIBypassEnable \
-        ROM_PECIBypassEnable
-#else
-#define MAP_PECIBypassEnable \
-        PECIBypassEnable
-#endif
-#ifdef ROM_PECIBypassDisable
-#define MAP_PECIBypassDisable \
-        ROM_PECIBypassDisable
-#else
-#define MAP_PECIBypassDisable \
-        PECIBypassDisable
-#endif
-
-//*****************************************************************************
-//
-// Macros for the PWM API.
-//
-//*****************************************************************************
-#ifdef ROM_PWMPulseWidthSet
-#define MAP_PWMPulseWidthSet \
-        ROM_PWMPulseWidthSet
-#else
-#define MAP_PWMPulseWidthSet \
-        PWMPulseWidthSet
-#endif
-#ifdef ROM_PWMGenConfigure
-#define MAP_PWMGenConfigure \
-        ROM_PWMGenConfigure
-#else
-#define MAP_PWMGenConfigure \
-        PWMGenConfigure
-#endif
-#ifdef ROM_PWMGenPeriodSet
-#define MAP_PWMGenPeriodSet \
-        ROM_PWMGenPeriodSet
-#else
-#define MAP_PWMGenPeriodSet \
-        PWMGenPeriodSet
-#endif
-#ifdef ROM_PWMGenPeriodGet
-#define MAP_PWMGenPeriodGet \
-        ROM_PWMGenPeriodGet
-#else
-#define MAP_PWMGenPeriodGet \
-        PWMGenPeriodGet
-#endif
-#ifdef ROM_PWMGenEnable
-#define MAP_PWMGenEnable \
-        ROM_PWMGenEnable
-#else
-#define MAP_PWMGenEnable \
-        PWMGenEnable
-#endif
-#ifdef ROM_PWMGenDisable
-#define MAP_PWMGenDisable \
-        ROM_PWMGenDisable
-#else
-#define MAP_PWMGenDisable \
-        PWMGenDisable
-#endif
-#ifdef ROM_PWMPulseWidthGet
-#define MAP_PWMPulseWidthGet \
-        ROM_PWMPulseWidthGet
-#else
-#define MAP_PWMPulseWidthGet \
-        PWMPulseWidthGet
-#endif
-#ifdef ROM_PWMDeadBandEnable
-#define MAP_PWMDeadBandEnable \
-        ROM_PWMDeadBandEnable
-#else
-#define MAP_PWMDeadBandEnable \
-        PWMDeadBandEnable
-#endif
-#ifdef ROM_PWMDeadBandDisable
-#define MAP_PWMDeadBandDisable \
-        ROM_PWMDeadBandDisable
-#else
-#define MAP_PWMDeadBandDisable \
-        PWMDeadBandDisable
-#endif
-#ifdef ROM_PWMSyncUpdate
-#define MAP_PWMSyncUpdate \
-        ROM_PWMSyncUpdate
-#else
-#define MAP_PWMSyncUpdate \
-        PWMSyncUpdate
-#endif
-#ifdef ROM_PWMSyncTimeBase
-#define MAP_PWMSyncTimeBase \
-        ROM_PWMSyncTimeBase
-#else
-#define MAP_PWMSyncTimeBase \
-        PWMSyncTimeBase
-#endif
-#ifdef ROM_PWMOutputState
-#define MAP_PWMOutputState \
-        ROM_PWMOutputState
-#else
-#define MAP_PWMOutputState \
-        PWMOutputState
-#endif
-#ifdef ROM_PWMOutputInvert
-#define MAP_PWMOutputInvert \
-        ROM_PWMOutputInvert
-#else
-#define MAP_PWMOutputInvert \
-        PWMOutputInvert
-#endif
-#ifdef ROM_PWMOutputFault
-#define MAP_PWMOutputFault \
-        ROM_PWMOutputFault
-#else
-#define MAP_PWMOutputFault \
-        PWMOutputFault
-#endif
-#ifdef ROM_PWMGenIntTrigEnable
-#define MAP_PWMGenIntTrigEnable \
-        ROM_PWMGenIntTrigEnable
-#else
-#define MAP_PWMGenIntTrigEnable \
-        PWMGenIntTrigEnable
-#endif
-#ifdef ROM_PWMGenIntTrigDisable
-#define MAP_PWMGenIntTrigDisable \
-        ROM_PWMGenIntTrigDisable
-#else
-#define MAP_PWMGenIntTrigDisable \
-        PWMGenIntTrigDisable
-#endif
-#ifdef ROM_PWMGenIntStatus
-#define MAP_PWMGenIntStatus \
-        ROM_PWMGenIntStatus
-#else
-#define MAP_PWMGenIntStatus \
-        PWMGenIntStatus
-#endif
-#ifdef ROM_PWMGenIntClear
-#define MAP_PWMGenIntClear \
-        ROM_PWMGenIntClear
-#else
-#define MAP_PWMGenIntClear \
-        PWMGenIntClear
-#endif
-#ifdef ROM_PWMIntEnable
-#define MAP_PWMIntEnable \
-        ROM_PWMIntEnable
-#else
-#define MAP_PWMIntEnable \
-        PWMIntEnable
-#endif
-#ifdef ROM_PWMIntDisable
-#define MAP_PWMIntDisable \
-        ROM_PWMIntDisable
-#else
-#define MAP_PWMIntDisable \
-        PWMIntDisable
-#endif
-#ifdef ROM_PWMFaultIntClear
-#define MAP_PWMFaultIntClear \
-        ROM_PWMFaultIntClear
-#else
-#define MAP_PWMFaultIntClear \
-        PWMFaultIntClear
-#endif
-#ifdef ROM_PWMIntStatus
-#define MAP_PWMIntStatus \
-        ROM_PWMIntStatus
-#else
-#define MAP_PWMIntStatus \
-        PWMIntStatus
-#endif
-#ifdef ROM_PWMOutputFaultLevel
-#define MAP_PWMOutputFaultLevel \
-        ROM_PWMOutputFaultLevel
-#else
-#define MAP_PWMOutputFaultLevel \
-        PWMOutputFaultLevel
-#endif
-#ifdef ROM_PWMFaultIntClearExt
-#define MAP_PWMFaultIntClearExt \
-        ROM_PWMFaultIntClearExt
-#else
-#define MAP_PWMFaultIntClearExt \
-        PWMFaultIntClearExt
-#endif
-#ifdef ROM_PWMGenFaultConfigure
-#define MAP_PWMGenFaultConfigure \
-        ROM_PWMGenFaultConfigure
-#else
-#define MAP_PWMGenFaultConfigure \
-        PWMGenFaultConfigure
-#endif
-#ifdef ROM_PWMGenFaultTriggerSet
-#define MAP_PWMGenFaultTriggerSet \
-        ROM_PWMGenFaultTriggerSet
-#else
-#define MAP_PWMGenFaultTriggerSet \
-        PWMGenFaultTriggerSet
-#endif
-#ifdef ROM_PWMGenFaultTriggerGet
-#define MAP_PWMGenFaultTriggerGet \
-        ROM_PWMGenFaultTriggerGet
-#else
-#define MAP_PWMGenFaultTriggerGet \
-        PWMGenFaultTriggerGet
-#endif
-#ifdef ROM_PWMGenFaultStatus
-#define MAP_PWMGenFaultStatus \
-        ROM_PWMGenFaultStatus
-#else
-#define MAP_PWMGenFaultStatus \
-        PWMGenFaultStatus
-#endif
-#ifdef ROM_PWMGenFaultClear
-#define MAP_PWMGenFaultClear \
-        ROM_PWMGenFaultClear
-#else
-#define MAP_PWMGenFaultClear \
-        PWMGenFaultClear
-#endif
-
-//*****************************************************************************
-//
-// Macros for the QEI API.
-//
-//*****************************************************************************
-#ifdef ROM_QEIPositionGet
-#define MAP_QEIPositionGet \
-        ROM_QEIPositionGet
-#else
-#define MAP_QEIPositionGet \
-        QEIPositionGet
-#endif
-#ifdef ROM_QEIEnable
-#define MAP_QEIEnable \
-        ROM_QEIEnable
-#else
-#define MAP_QEIEnable \
-        QEIEnable
-#endif
-#ifdef ROM_QEIDisable
-#define MAP_QEIDisable \
-        ROM_QEIDisable
-#else
-#define MAP_QEIDisable \
-        QEIDisable
-#endif
-#ifdef ROM_QEIConfigure
-#define MAP_QEIConfigure \
-        ROM_QEIConfigure
-#else
-#define MAP_QEIConfigure \
-        QEIConfigure
-#endif
-#ifdef ROM_QEIPositionSet
-#define MAP_QEIPositionSet \
-        ROM_QEIPositionSet
-#else
-#define MAP_QEIPositionSet \
-        QEIPositionSet
-#endif
-#ifdef ROM_QEIDirectionGet
-#define MAP_QEIDirectionGet \
-        ROM_QEIDirectionGet
-#else
-#define MAP_QEIDirectionGet \
-        QEIDirectionGet
-#endif
-#ifdef ROM_QEIErrorGet
-#define MAP_QEIErrorGet \
-        ROM_QEIErrorGet
-#else
-#define MAP_QEIErrorGet \
-        QEIErrorGet
-#endif
-#ifdef ROM_QEIVelocityEnable
-#define MAP_QEIVelocityEnable \
-        ROM_QEIVelocityEnable
-#else
-#define MAP_QEIVelocityEnable \
-        QEIVelocityEnable
-#endif
-#ifdef ROM_QEIVelocityDisable
-#define MAP_QEIVelocityDisable \
-        ROM_QEIVelocityDisable
-#else
-#define MAP_QEIVelocityDisable \
-        QEIVelocityDisable
-#endif
-#ifdef ROM_QEIVelocityConfigure
-#define MAP_QEIVelocityConfigure \
-        ROM_QEIVelocityConfigure
-#else
-#define MAP_QEIVelocityConfigure \
-        QEIVelocityConfigure
-#endif
-#ifdef ROM_QEIVelocityGet
-#define MAP_QEIVelocityGet \
-        ROM_QEIVelocityGet
-#else
-#define MAP_QEIVelocityGet \
-        QEIVelocityGet
-#endif
-#ifdef ROM_QEIIntEnable
-#define MAP_QEIIntEnable \
-        ROM_QEIIntEnable
-#else
-#define MAP_QEIIntEnable \
-        QEIIntEnable
-#endif
-#ifdef ROM_QEIIntDisable
-#define MAP_QEIIntDisable \
-        ROM_QEIIntDisable
-#else
-#define MAP_QEIIntDisable \
-        QEIIntDisable
-#endif
-#ifdef ROM_QEIIntStatus
-#define MAP_QEIIntStatus \
-        ROM_QEIIntStatus
-#else
-#define MAP_QEIIntStatus \
-        QEIIntStatus
-#endif
-#ifdef ROM_QEIIntClear
-#define MAP_QEIIntClear \
-        ROM_QEIIntClear
-#else
-#define MAP_QEIIntClear \
-        QEIIntClear
-#endif
-
-//*****************************************************************************
-//
-// Macros for the SMBus API.
-//
-//*****************************************************************************
-#ifdef ROM_SMBusMasterIntProcess
-#define MAP_SMBusMasterIntProcess \
-        ROM_SMBusMasterIntProcess
-#else
-#define MAP_SMBusMasterIntProcess \
-        SMBusMasterIntProcess
-#endif
-#ifdef ROM_SMBusARPDisable
-#define MAP_SMBusARPDisable \
-        ROM_SMBusARPDisable
-#else
-#define MAP_SMBusARPDisable \
-        SMBusARPDisable
-#endif
-#ifdef ROM_SMBusARPEnable
-#define MAP_SMBusARPEnable \
-        ROM_SMBusARPEnable
-#else
-#define MAP_SMBusARPEnable \
-        SMBusARPEnable
-#endif
-#ifdef ROM_SMBusARPUDIDPacketDecode
-#define MAP_SMBusARPUDIDPacketDecode \
-        ROM_SMBusARPUDIDPacketDecode
-#else
-#define MAP_SMBusARPUDIDPacketDecode \
-        SMBusARPUDIDPacketDecode
-#endif
-#ifdef ROM_SMBusARPUDIDPacketEncode
-#define MAP_SMBusARPUDIDPacketEncode \
-        ROM_SMBusARPUDIDPacketEncode
-#else
-#define MAP_SMBusARPUDIDPacketEncode \
-        SMBusARPUDIDPacketEncode
-#endif
-#ifdef ROM_SMBusMasterARPAssignAddress
-#define MAP_SMBusMasterARPAssignAddress \
-        ROM_SMBusMasterARPAssignAddress
-#else
-#define MAP_SMBusMasterARPAssignAddress \
-        SMBusMasterARPAssignAddress
-#endif
-#ifdef ROM_SMBusMasterARPGetUDIDDir
-#define MAP_SMBusMasterARPGetUDIDDir \
-        ROM_SMBusMasterARPGetUDIDDir
-#else
-#define MAP_SMBusMasterARPGetUDIDDir \
-        SMBusMasterARPGetUDIDDir
-#endif
-#ifdef ROM_SMBusMasterARPGetUDIDGen
-#define MAP_SMBusMasterARPGetUDIDGen \
-        ROM_SMBusMasterARPGetUDIDGen
-#else
-#define MAP_SMBusMasterARPGetUDIDGen \
-        SMBusMasterARPGetUDIDGen
-#endif
-#ifdef ROM_SMBusMasterARPNotifyMaster
-#define MAP_SMBusMasterARPNotifyMaster \
-        ROM_SMBusMasterARPNotifyMaster
-#else
-#define MAP_SMBusMasterARPNotifyMaster \
-        SMBusMasterARPNotifyMaster
-#endif
-#ifdef ROM_SMBusMasterARPPrepareToARP
-#define MAP_SMBusMasterARPPrepareToARP \
-        ROM_SMBusMasterARPPrepareToARP
-#else
-#define MAP_SMBusMasterARPPrepareToARP \
-        SMBusMasterARPPrepareToARP
-#endif
-#ifdef ROM_SMBusMasterARPResetDeviceDir
-#define MAP_SMBusMasterARPResetDeviceDir \
-        ROM_SMBusMasterARPResetDeviceDir
-#else
-#define MAP_SMBusMasterARPResetDeviceDir \
-        SMBusMasterARPResetDeviceDir
-#endif
-#ifdef ROM_SMBusMasterARPResetDeviceGen
-#define MAP_SMBusMasterARPResetDeviceGen \
-        ROM_SMBusMasterARPResetDeviceGen
-#else
-#define MAP_SMBusMasterARPResetDeviceGen \
-        SMBusMasterARPResetDeviceGen
-#endif
-#ifdef ROM_SMBusMasterBlockProcessCall
-#define MAP_SMBusMasterBlockProcessCall \
-        ROM_SMBusMasterBlockProcessCall
-#else
-#define MAP_SMBusMasterBlockProcessCall \
-        SMBusMasterBlockProcessCall
-#endif
-#ifdef ROM_SMBusMasterBlockRead
-#define MAP_SMBusMasterBlockRead \
-        ROM_SMBusMasterBlockRead
-#else
-#define MAP_SMBusMasterBlockRead \
-        SMBusMasterBlockRead
-#endif
-#ifdef ROM_SMBusMasterBlockWrite
-#define MAP_SMBusMasterBlockWrite \
-        ROM_SMBusMasterBlockWrite
-#else
-#define MAP_SMBusMasterBlockWrite \
-        SMBusMasterBlockWrite
-#endif
-#ifdef ROM_SMBusMasterByteReceive
-#define MAP_SMBusMasterByteReceive \
-        ROM_SMBusMasterByteReceive
-#else
-#define MAP_SMBusMasterByteReceive \
-        SMBusMasterByteReceive
-#endif
-#ifdef ROM_SMBusMasterByteSend
-#define MAP_SMBusMasterByteSend \
-        ROM_SMBusMasterByteSend
-#else
-#define MAP_SMBusMasterByteSend \
-        SMBusMasterByteSend
-#endif
-#ifdef ROM_SMBusMasterByteWordRead
-#define MAP_SMBusMasterByteWordRead \
-        ROM_SMBusMasterByteWordRead
-#else
-#define MAP_SMBusMasterByteWordRead \
-        SMBusMasterByteWordRead
-#endif
-#ifdef ROM_SMBusMasterByteWordWrite
-#define MAP_SMBusMasterByteWordWrite \
-        ROM_SMBusMasterByteWordWrite
-#else
-#define MAP_SMBusMasterByteWordWrite \
-        SMBusMasterByteWordWrite
-#endif
-#ifdef ROM_SMBusMasterHostNotify
-#define MAP_SMBusMasterHostNotify \
-        ROM_SMBusMasterHostNotify
-#else
-#define MAP_SMBusMasterHostNotify \
-        SMBusMasterHostNotify
-#endif
-#ifdef ROM_SMBusMasterI2CRead
-#define MAP_SMBusMasterI2CRead \
-        ROM_SMBusMasterI2CRead
-#else
-#define MAP_SMBusMasterI2CRead \
-        SMBusMasterI2CRead
-#endif
-#ifdef ROM_SMBusMasterI2CWrite
-#define MAP_SMBusMasterI2CWrite \
-        ROM_SMBusMasterI2CWrite
-#else
-#define MAP_SMBusMasterI2CWrite \
-        SMBusMasterI2CWrite
-#endif
-#ifdef ROM_SMBusMasterI2CWriteRead
-#define MAP_SMBusMasterI2CWriteRead \
-        ROM_SMBusMasterI2CWriteRead
-#else
-#define MAP_SMBusMasterI2CWriteRead \
-        SMBusMasterI2CWriteRead
-#endif
-#ifdef ROM_SMBusMasterInit
-#define MAP_SMBusMasterInit \
-        ROM_SMBusMasterInit
-#else
-#define MAP_SMBusMasterInit \
-        SMBusMasterInit
-#endif
-#ifdef ROM_SMBusMasterIntEnable
-#define MAP_SMBusMasterIntEnable \
-        ROM_SMBusMasterIntEnable
-#else
-#define MAP_SMBusMasterIntEnable \
-        SMBusMasterIntEnable
-#endif
-#ifdef ROM_SMBusMasterProcessCall
-#define MAP_SMBusMasterProcessCall \
-        ROM_SMBusMasterProcessCall
-#else
-#define MAP_SMBusMasterProcessCall \
-        SMBusMasterProcessCall
-#endif
-#ifdef ROM_SMBusMasterQuickCommand
-#define MAP_SMBusMasterQuickCommand \
-        ROM_SMBusMasterQuickCommand
-#else
-#define MAP_SMBusMasterQuickCommand \
-        SMBusMasterQuickCommand
-#endif
-#ifdef ROM_SMBusPECDisable
-#define MAP_SMBusPECDisable \
-        ROM_SMBusPECDisable
-#else
-#define MAP_SMBusPECDisable \
-        SMBusPECDisable
-#endif
-#ifdef ROM_SMBusPECEnable
-#define MAP_SMBusPECEnable \
-        ROM_SMBusPECEnable
-#else
-#define MAP_SMBusPECEnable \
-        SMBusPECEnable
-#endif
-#ifdef ROM_SMBusRxPacketSizeGet
-#define MAP_SMBusRxPacketSizeGet \
-        ROM_SMBusRxPacketSizeGet
-#else
-#define MAP_SMBusRxPacketSizeGet \
-        SMBusRxPacketSizeGet
-#endif
-#ifdef ROM_SMBusSlaveACKSend
-#define MAP_SMBusSlaveACKSend \
-        ROM_SMBusSlaveACKSend
-#else
-#define MAP_SMBusSlaveACKSend \
-        SMBusSlaveACKSend
-#endif
-#ifdef ROM_SMBusSlaveAddressSet
-#define MAP_SMBusSlaveAddressSet \
-        ROM_SMBusSlaveAddressSet
-#else
-#define MAP_SMBusSlaveAddressSet \
-        SMBusSlaveAddressSet
-#endif
-#ifdef ROM_SMBusSlaveARPFlagARGet
-#define MAP_SMBusSlaveARPFlagARGet \
-        ROM_SMBusSlaveARPFlagARGet
-#else
-#define MAP_SMBusSlaveARPFlagARGet \
-        SMBusSlaveARPFlagARGet
-#endif
-#ifdef ROM_SMBusSlaveARPFlagARSet
-#define MAP_SMBusSlaveARPFlagARSet \
-        ROM_SMBusSlaveARPFlagARSet
-#else
-#define MAP_SMBusSlaveARPFlagARSet \
-        SMBusSlaveARPFlagARSet
-#endif
-#ifdef ROM_SMBusSlaveARPFlagAVGet
-#define MAP_SMBusSlaveARPFlagAVGet \
-        ROM_SMBusSlaveARPFlagAVGet
-#else
-#define MAP_SMBusSlaveARPFlagAVGet \
-        SMBusSlaveARPFlagAVGet
-#endif
-#ifdef ROM_SMBusSlaveARPFlagAVSet
-#define MAP_SMBusSlaveARPFlagAVSet \
-        ROM_SMBusSlaveARPFlagAVSet
-#else
-#define MAP_SMBusSlaveARPFlagAVSet \
-        SMBusSlaveARPFlagAVSet
-#endif
-#ifdef ROM_SMBusSlaveBlockTransferDisable
-#define MAP_SMBusSlaveBlockTransferDisable \
-        ROM_SMBusSlaveBlockTransferDisable
-#else
-#define MAP_SMBusSlaveBlockTransferDisable \
-        SMBusSlaveBlockTransferDisable
-#endif
-#ifdef ROM_SMBusSlaveBlockTransferEnable
-#define MAP_SMBusSlaveBlockTransferEnable \
-        ROM_SMBusSlaveBlockTransferEnable
-#else
-#define MAP_SMBusSlaveBlockTransferEnable \
-        SMBusSlaveBlockTransferEnable
-#endif
-#ifdef ROM_SMBusSlaveCommandGet
-#define MAP_SMBusSlaveCommandGet \
-        ROM_SMBusSlaveCommandGet
-#else
-#define MAP_SMBusSlaveCommandGet \
-        SMBusSlaveCommandGet
-#endif
-#ifdef ROM_SMBusSlaveI2CDisable
-#define MAP_SMBusSlaveI2CDisable \
-        ROM_SMBusSlaveI2CDisable
-#else
-#define MAP_SMBusSlaveI2CDisable \
-        SMBusSlaveI2CDisable
-#endif
-#ifdef ROM_SMBusSlaveI2CEnable
-#define MAP_SMBusSlaveI2CEnable \
-        ROM_SMBusSlaveI2CEnable
-#else
-#define MAP_SMBusSlaveI2CEnable \
-        SMBusSlaveI2CEnable
-#endif
-#ifdef ROM_SMBusSlaveInit
-#define MAP_SMBusSlaveInit \
-        ROM_SMBusSlaveInit
-#else
-#define MAP_SMBusSlaveInit \
-        SMBusSlaveInit
-#endif
-#ifdef ROM_SMBusSlaveIntAddressGet
-#define MAP_SMBusSlaveIntAddressGet \
-        ROM_SMBusSlaveIntAddressGet
-#else
-#define MAP_SMBusSlaveIntAddressGet \
-        SMBusSlaveIntAddressGet
-#endif
-#ifdef ROM_SMBusSlaveIntEnable
-#define MAP_SMBusSlaveIntEnable \
-        ROM_SMBusSlaveIntEnable
-#else
-#define MAP_SMBusSlaveIntEnable \
-        SMBusSlaveIntEnable
-#endif
-#ifdef ROM_SMBusSlaveIntProcess
-#define MAP_SMBusSlaveIntProcess \
-        ROM_SMBusSlaveIntProcess
-#else
-#define MAP_SMBusSlaveIntProcess \
-        SMBusSlaveIntProcess
-#endif
-#ifdef ROM_SMBusSlaveManualACKDisable
-#define MAP_SMBusSlaveManualACKDisable \
-        ROM_SMBusSlaveManualACKDisable
-#else
-#define MAP_SMBusSlaveManualACKDisable \
-        SMBusSlaveManualACKDisable
-#endif
-#ifdef ROM_SMBusSlaveManualACKEnable
-#define MAP_SMBusSlaveManualACKEnable \
-        ROM_SMBusSlaveManualACKEnable
-#else
-#define MAP_SMBusSlaveManualACKEnable \
-        SMBusSlaveManualACKEnable
-#endif
-#ifdef ROM_SMBusSlaveManualACKStatusGet
-#define MAP_SMBusSlaveManualACKStatusGet \
-        ROM_SMBusSlaveManualACKStatusGet
-#else
-#define MAP_SMBusSlaveManualACKStatusGet \
-        SMBusSlaveManualACKStatusGet
-#endif
-#ifdef ROM_SMBusSlaveProcessCallDisable
-#define MAP_SMBusSlaveProcessCallDisable \
-        ROM_SMBusSlaveProcessCallDisable
-#else
-#define MAP_SMBusSlaveProcessCallDisable \
-        SMBusSlaveProcessCallDisable
-#endif
-#ifdef ROM_SMBusSlaveProcessCallEnable
-#define MAP_SMBusSlaveProcessCallEnable \
-        ROM_SMBusSlaveProcessCallEnable
-#else
-#define MAP_SMBusSlaveProcessCallEnable \
-        SMBusSlaveProcessCallEnable
-#endif
-#ifdef ROM_SMBusSlaveRxBufferSet
-#define MAP_SMBusSlaveRxBufferSet \
-        ROM_SMBusSlaveRxBufferSet
-#else
-#define MAP_SMBusSlaveRxBufferSet \
-        SMBusSlaveRxBufferSet
-#endif
-#ifdef ROM_SMBusSlaveTransferInit
-#define MAP_SMBusSlaveTransferInit \
-        ROM_SMBusSlaveTransferInit
-#else
-#define MAP_SMBusSlaveTransferInit \
-        SMBusSlaveTransferInit
-#endif
-#ifdef ROM_SMBusSlaveTxBufferSet
-#define MAP_SMBusSlaveTxBufferSet \
-        ROM_SMBusSlaveTxBufferSet
-#else
-#define MAP_SMBusSlaveTxBufferSet \
-        SMBusSlaveTxBufferSet
-#endif
-#ifdef ROM_SMBusSlaveUDIDSet
-#define MAP_SMBusSlaveUDIDSet \
-        ROM_SMBusSlaveUDIDSet
-#else
-#define MAP_SMBusSlaveUDIDSet \
-        SMBusSlaveUDIDSet
-#endif
-#ifdef ROM_SMBusStatusGet
-#define MAP_SMBusStatusGet \
-        ROM_SMBusStatusGet
-#else
-#define MAP_SMBusStatusGet \
-        SMBusStatusGet
-#endif
-#ifdef ROM_SMBusSlaveDataSend
-#define MAP_SMBusSlaveDataSend \
-        ROM_SMBusSlaveDataSend
-#else
-#define MAP_SMBusSlaveDataSend \
-        SMBusSlaveDataSend
-#endif
-
-//*****************************************************************************
-//
-// Macros for the SSI API.
-//
-//*****************************************************************************
-#ifdef ROM_SSIDataPut
-#define MAP_SSIDataPut \
-        ROM_SSIDataPut
-#else
-#define MAP_SSIDataPut \
-        SSIDataPut
-#endif
-#ifdef ROM_SSIConfigSetExpClk
-#define MAP_SSIConfigSetExpClk \
-        ROM_SSIConfigSetExpClk
-#else
-#define MAP_SSIConfigSetExpClk \
-        SSIConfigSetExpClk
-#endif
-#ifdef ROM_SSIEnable
-#define MAP_SSIEnable \
-        ROM_SSIEnable
-#else
-#define MAP_SSIEnable \
-        SSIEnable
-#endif
-#ifdef ROM_SSIDisable
-#define MAP_SSIDisable \
-        ROM_SSIDisable
-#else
-#define MAP_SSIDisable \
-        SSIDisable
-#endif
-#ifdef ROM_SSIIntEnable
-#define MAP_SSIIntEnable \
-        ROM_SSIIntEnable
-#else
-#define MAP_SSIIntEnable \
-        SSIIntEnable
-#endif
-#ifdef ROM_SSIIntDisable
-#define MAP_SSIIntDisable \
-        ROM_SSIIntDisable
-#else
-#define MAP_SSIIntDisable \
-        SSIIntDisable
-#endif
-#ifdef ROM_SSIIntStatus
-#define MAP_SSIIntStatus \
-        ROM_SSIIntStatus
-#else
-#define MAP_SSIIntStatus \
-        SSIIntStatus
-#endif
-#ifdef ROM_SSIIntClear
-#define MAP_SSIIntClear \
-        ROM_SSIIntClear
-#else
-#define MAP_SSIIntClear \
-        SSIIntClear
-#endif
-#ifdef ROM_SSIDataPutNonBlocking
-#define MAP_SSIDataPutNonBlocking \
-        ROM_SSIDataPutNonBlocking
-#else
-#define MAP_SSIDataPutNonBlocking \
-        SSIDataPutNonBlocking
-#endif
-#ifdef ROM_SSIDataGet
-#define MAP_SSIDataGet \
-        ROM_SSIDataGet
-#else
-#define MAP_SSIDataGet \
-        SSIDataGet
-#endif
-#ifdef ROM_SSIDataGetNonBlocking
-#define MAP_SSIDataGetNonBlocking \
-        ROM_SSIDataGetNonBlocking
-#else
-#define MAP_SSIDataGetNonBlocking \
-        SSIDataGetNonBlocking
-#endif
-#ifdef ROM_SSIDMAEnable
-#define MAP_SSIDMAEnable \
-        ROM_SSIDMAEnable
-#else
-#define MAP_SSIDMAEnable \
-        SSIDMAEnable
-#endif
-#ifdef ROM_SSIDMADisable
-#define MAP_SSIDMADisable \
-        ROM_SSIDMADisable
-#else
-#define MAP_SSIDMADisable \
-        SSIDMADisable
-#endif
-#ifdef ROM_SSIBusy
-#define MAP_SSIBusy \
-        ROM_SSIBusy
-#else
-#define MAP_SSIBusy \
-        SSIBusy
-#endif
-#ifdef ROM_SSIClockSourceGet
-#define MAP_SSIClockSourceGet \
-        ROM_SSIClockSourceGet
-#else
-#define MAP_SSIClockSourceGet \
-        SSIClockSourceGet
-#endif
-#ifdef ROM_SSIClockSourceSet
-#define MAP_SSIClockSourceSet \
-        ROM_SSIClockSourceSet
-#else
-#define MAP_SSIClockSourceSet \
-        SSIClockSourceSet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the SysCtl API.
-//
-//*****************************************************************************
-#ifdef ROM_SysCtlSleep
-#define MAP_SysCtlSleep \
-        ROM_SysCtlSleep
-#else
-#define MAP_SysCtlSleep \
-        SysCtlSleep
-#endif
-#ifdef ROM_SysCtlSRAMSizeGet
-#define MAP_SysCtlSRAMSizeGet \
-        ROM_SysCtlSRAMSizeGet
-#else
-#define MAP_SysCtlSRAMSizeGet \
-        SysCtlSRAMSizeGet
-#endif
-#ifdef ROM_SysCtlFlashSizeGet
-#define MAP_SysCtlFlashSizeGet \
-        ROM_SysCtlFlashSizeGet
-#else
-#define MAP_SysCtlFlashSizeGet \
-        SysCtlFlashSizeGet
-#endif
-#ifdef ROM_SysCtlPinPresent
-#define MAP_SysCtlPinPresent \
-        ROM_SysCtlPinPresent
-#else
-#define MAP_SysCtlPinPresent \
-        SysCtlPinPresent
-#endif
-#ifdef ROM_SysCtlPeripheralPresent
-#define MAP_SysCtlPeripheralPresent \
-        ROM_SysCtlPeripheralPresent
-#else
-#define MAP_SysCtlPeripheralPresent \
-        SysCtlPeripheralPresent
-#endif
-#ifdef ROM_SysCtlPeripheralReset
-#define MAP_SysCtlPeripheralReset \
-        ROM_SysCtlPeripheralReset
-#else
-#define MAP_SysCtlPeripheralReset \
-        SysCtlPeripheralReset
-#endif
-#ifdef ROM_SysCtlPeripheralEnable
-#define MAP_SysCtlPeripheralEnable \
-        ROM_SysCtlPeripheralEnable
-#else
-#define MAP_SysCtlPeripheralEnable \
-        SysCtlPeripheralEnable
-#endif
-#ifdef ROM_SysCtlPeripheralDisable
-#define MAP_SysCtlPeripheralDisable \
-        ROM_SysCtlPeripheralDisable
-#else
-#define MAP_SysCtlPeripheralDisable \
-        SysCtlPeripheralDisable
-#endif
-#ifdef ROM_SysCtlPeripheralSleepEnable
-#define MAP_SysCtlPeripheralSleepEnable \
-        ROM_SysCtlPeripheralSleepEnable
-#else
-#define MAP_SysCtlPeripheralSleepEnable \
-        SysCtlPeripheralSleepEnable
-#endif
-#ifdef ROM_SysCtlPeripheralSleepDisable
-#define MAP_SysCtlPeripheralSleepDisable \
-        ROM_SysCtlPeripheralSleepDisable
-#else
-#define MAP_SysCtlPeripheralSleepDisable \
-        SysCtlPeripheralSleepDisable
-#endif
-#ifdef ROM_SysCtlPeripheralDeepSleepEnable
-#define MAP_SysCtlPeripheralDeepSleepEnable \
-        ROM_SysCtlPeripheralDeepSleepEnable
-#else
-#define MAP_SysCtlPeripheralDeepSleepEnable \
-        SysCtlPeripheralDeepSleepEnable
-#endif
-#ifdef ROM_SysCtlPeripheralDeepSleepDisable
-#define MAP_SysCtlPeripheralDeepSleepDisable \
-        ROM_SysCtlPeripheralDeepSleepDisable
-#else
-#define MAP_SysCtlPeripheralDeepSleepDisable \
-        SysCtlPeripheralDeepSleepDisable
-#endif
-#ifdef ROM_SysCtlPeripheralClockGating
-#define MAP_SysCtlPeripheralClockGating \
-        ROM_SysCtlPeripheralClockGating
-#else
-#define MAP_SysCtlPeripheralClockGating \
-        SysCtlPeripheralClockGating
-#endif
-#ifdef ROM_SysCtlIntEnable
-#define MAP_SysCtlIntEnable \
-        ROM_SysCtlIntEnable
-#else
-#define MAP_SysCtlIntEnable \
-        SysCtlIntEnable
-#endif
-#ifdef ROM_SysCtlIntDisable
-#define MAP_SysCtlIntDisable \
-        ROM_SysCtlIntDisable
-#else
-#define MAP_SysCtlIntDisable \
-        SysCtlIntDisable
-#endif
-#ifdef ROM_SysCtlIntClear
-#define MAP_SysCtlIntClear \
-        ROM_SysCtlIntClear
-#else
-#define MAP_SysCtlIntClear \
-        SysCtlIntClear
-#endif
-#ifdef ROM_SysCtlIntStatus
-#define MAP_SysCtlIntStatus \
-        ROM_SysCtlIntStatus
-#else
-#define MAP_SysCtlIntStatus \
-        SysCtlIntStatus
-#endif
-#ifdef ROM_SysCtlLDOSet
-#define MAP_SysCtlLDOSet \
-        ROM_SysCtlLDOSet
-#else
-#define MAP_SysCtlLDOSet \
-        SysCtlLDOSet
-#endif
-#ifdef ROM_SysCtlLDOGet
-#define MAP_SysCtlLDOGet \
-        ROM_SysCtlLDOGet
-#else
-#define MAP_SysCtlLDOGet \
-        SysCtlLDOGet
-#endif
-#ifdef ROM_SysCtlReset
-#define MAP_SysCtlReset \
-        ROM_SysCtlReset
-#else
-#define MAP_SysCtlReset \
-        SysCtlReset
-#endif
-#ifdef ROM_SysCtlDeepSleep
-#define MAP_SysCtlDeepSleep \
-        ROM_SysCtlDeepSleep
-#else
-#define MAP_SysCtlDeepSleep \
-        SysCtlDeepSleep
-#endif
-#ifdef ROM_SysCtlResetCauseGet
-#define MAP_SysCtlResetCauseGet \
-        ROM_SysCtlResetCauseGet
-#else
-#define MAP_SysCtlResetCauseGet \
-        SysCtlResetCauseGet
-#endif
-#ifdef ROM_SysCtlResetCauseClear
-#define MAP_SysCtlResetCauseClear \
-        ROM_SysCtlResetCauseClear
-#else
-#define MAP_SysCtlResetCauseClear \
-        SysCtlResetCauseClear
-#endif
-#ifdef ROM_SysCtlClockSet
-#define MAP_SysCtlClockSet \
-        ROM_SysCtlClockSet
-#else
-#define MAP_SysCtlClockSet \
-        SysCtlClockSet
-#endif
-#ifdef ROM_SysCtlClockGet
-#define MAP_SysCtlClockGet \
-        ROM_SysCtlClockGet
-#else
-#define MAP_SysCtlClockGet \
-        SysCtlClockGet
-#endif
-#ifdef ROM_SysCtlPWMClockSet
-#define MAP_SysCtlPWMClockSet \
-        ROM_SysCtlPWMClockSet
-#else
-#define MAP_SysCtlPWMClockSet \
-        SysCtlPWMClockSet
-#endif
-#ifdef ROM_SysCtlPWMClockGet
-#define MAP_SysCtlPWMClockGet \
-        ROM_SysCtlPWMClockGet
-#else
-#define MAP_SysCtlPWMClockGet \
-        SysCtlPWMClockGet
-#endif
-#ifdef ROM_SysCtlADCSpeedSet
-#define MAP_SysCtlADCSpeedSet \
-        ROM_SysCtlADCSpeedSet
-#else
-#define MAP_SysCtlADCSpeedSet \
-        SysCtlADCSpeedSet
-#endif
-#ifdef ROM_SysCtlADCSpeedGet
-#define MAP_SysCtlADCSpeedGet \
-        ROM_SysCtlADCSpeedGet
-#else
-#define MAP_SysCtlADCSpeedGet \
-        SysCtlADCSpeedGet
-#endif
-#ifdef ROM_SysCtlGPIOAHBEnable
-#define MAP_SysCtlGPIOAHBEnable \
-        ROM_SysCtlGPIOAHBEnable
-#else
-#define MAP_SysCtlGPIOAHBEnable \
-        SysCtlGPIOAHBEnable
-#endif
-#ifdef ROM_SysCtlGPIOAHBDisable
-#define MAP_SysCtlGPIOAHBDisable \
-        ROM_SysCtlGPIOAHBDisable
-#else
-#define MAP_SysCtlGPIOAHBDisable \
-        SysCtlGPIOAHBDisable
-#endif
-#ifdef ROM_SysCtlUSBPLLEnable
-#define MAP_SysCtlUSBPLLEnable \
-        ROM_SysCtlUSBPLLEnable
-#else
-#define MAP_SysCtlUSBPLLEnable \
-        SysCtlUSBPLLEnable
-#endif
-#ifdef ROM_SysCtlUSBPLLDisable
-#define MAP_SysCtlUSBPLLDisable \
-        ROM_SysCtlUSBPLLDisable
-#else
-#define MAP_SysCtlUSBPLLDisable \
-        SysCtlUSBPLLDisable
-#endif
-#ifdef ROM_SysCtlI2SMClkSet
-#define MAP_SysCtlI2SMClkSet \
-        ROM_SysCtlI2SMClkSet
-#else
-#define MAP_SysCtlI2SMClkSet \
-        SysCtlI2SMClkSet
-#endif
-#ifdef ROM_SysCtlDelay
-#define MAP_SysCtlDelay \
-        ROM_SysCtlDelay
-#else
-#define MAP_SysCtlDelay \
-        SysCtlDelay
-#endif
-#ifdef ROM_SysCtlPeripheralReady
-#define MAP_SysCtlPeripheralReady \
-        ROM_SysCtlPeripheralReady
-#else
-#define MAP_SysCtlPeripheralReady \
-        SysCtlPeripheralReady
-#endif
-#ifdef ROM_SysCtlPeripheralPowerOn
-#define MAP_SysCtlPeripheralPowerOn \
-        ROM_SysCtlPeripheralPowerOn
-#else
-#define MAP_SysCtlPeripheralPowerOn \
-        SysCtlPeripheralPowerOn
-#endif
-#ifdef ROM_SysCtlPeripheralPowerOff
-#define MAP_SysCtlPeripheralPowerOff \
-        ROM_SysCtlPeripheralPowerOff
-#else
-#define MAP_SysCtlPeripheralPowerOff \
-        SysCtlPeripheralPowerOff
-#endif
-#ifdef ROM_SysCtlMOSCConfigSet
-#define MAP_SysCtlMOSCConfigSet \
-        ROM_SysCtlMOSCConfigSet
-#else
-#define MAP_SysCtlMOSCConfigSet \
-        SysCtlMOSCConfigSet
-#endif
-#ifdef ROM_SysCtlPIOSCCalibrate
-#define MAP_SysCtlPIOSCCalibrate \
-        ROM_SysCtlPIOSCCalibrate
-#else
-#define MAP_SysCtlPIOSCCalibrate \
-        SysCtlPIOSCCalibrate
-#endif
-#ifdef ROM_SysCtlDeepSleepClockSet
-#define MAP_SysCtlDeepSleepClockSet \
-        ROM_SysCtlDeepSleepClockSet
-#else
-#define MAP_SysCtlDeepSleepClockSet \
-        SysCtlDeepSleepClockSet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the SysExc API.
-//
-//*****************************************************************************
-#ifdef ROM_SysExcIntStatus
-#define MAP_SysExcIntStatus \
-        ROM_SysExcIntStatus
-#else
-#define MAP_SysExcIntStatus \
-        SysExcIntStatus
-#endif
-#ifdef ROM_SysExcIntClear
-#define MAP_SysExcIntClear \
-        ROM_SysExcIntClear
-#else
-#define MAP_SysExcIntClear \
-        SysExcIntClear
-#endif
-#ifdef ROM_SysExcIntDisable
-#define MAP_SysExcIntDisable \
-        ROM_SysExcIntDisable
-#else
-#define MAP_SysExcIntDisable \
-        SysExcIntDisable
-#endif
-#ifdef ROM_SysExcIntEnable
-#define MAP_SysExcIntEnable \
-        ROM_SysExcIntEnable
-#else
-#define MAP_SysExcIntEnable \
-        SysExcIntEnable
-#endif
-
-//*****************************************************************************
-//
-// Macros for the SysTick API.
-//
-//*****************************************************************************
-#ifdef ROM_SysTickValueGet
-#define MAP_SysTickValueGet \
-        ROM_SysTickValueGet
-#else
-#define MAP_SysTickValueGet \
-        SysTickValueGet
-#endif
-#ifdef ROM_SysTickEnable
-#define MAP_SysTickEnable \
-        ROM_SysTickEnable
-#else
-#define MAP_SysTickEnable \
-        SysTickEnable
-#endif
-#ifdef ROM_SysTickDisable
-#define MAP_SysTickDisable \
-        ROM_SysTickDisable
-#else
-#define MAP_SysTickDisable \
-        SysTickDisable
-#endif
-#ifdef ROM_SysTickIntEnable
-#define MAP_SysTickIntEnable \
-        ROM_SysTickIntEnable
-#else
-#define MAP_SysTickIntEnable \
-        SysTickIntEnable
-#endif
-#ifdef ROM_SysTickIntDisable
-#define MAP_SysTickIntDisable \
-        ROM_SysTickIntDisable
-#else
-#define MAP_SysTickIntDisable \
-        SysTickIntDisable
-#endif
-#ifdef ROM_SysTickPeriodSet
-#define MAP_SysTickPeriodSet \
-        ROM_SysTickPeriodSet
-#else
-#define MAP_SysTickPeriodSet \
-        SysTickPeriodSet
-#endif
-#ifdef ROM_SysTickPeriodGet
-#define MAP_SysTickPeriodGet \
-        ROM_SysTickPeriodGet
-#else
-#define MAP_SysTickPeriodGet \
-        SysTickPeriodGet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Timer API.
-//
-//*****************************************************************************
-#ifdef ROM_TimerIntClear
-#define MAP_TimerIntClear \
-        ROM_TimerIntClear
-#else
-#define MAP_TimerIntClear \
-        TimerIntClear
-#endif
-#ifdef ROM_TimerEnable
-#define MAP_TimerEnable \
-        ROM_TimerEnable
-#else
-#define MAP_TimerEnable \
-        TimerEnable
-#endif
-#ifdef ROM_TimerDisable
-#define MAP_TimerDisable \
-        ROM_TimerDisable
-#else
-#define MAP_TimerDisable \
-        TimerDisable
-#endif
-#ifdef ROM_TimerConfigure
-#define MAP_TimerConfigure \
-        ROM_TimerConfigure
-#else
-#define MAP_TimerConfigure \
-        TimerConfigure
-#endif
-#ifdef ROM_TimerControlLevel
-#define MAP_TimerControlLevel \
-        ROM_TimerControlLevel
-#else
-#define MAP_TimerControlLevel \
-        TimerControlLevel
-#endif
-#ifdef ROM_TimerControlTrigger
-#define MAP_TimerControlTrigger \
-        ROM_TimerControlTrigger
-#else
-#define MAP_TimerControlTrigger \
-        TimerControlTrigger
-#endif
-#ifdef ROM_TimerControlEvent
-#define MAP_TimerControlEvent \
-        ROM_TimerControlEvent
-#else
-#define MAP_TimerControlEvent \
-        TimerControlEvent
-#endif
-#ifdef ROM_TimerControlStall
-#define MAP_TimerControlStall \
-        ROM_TimerControlStall
-#else
-#define MAP_TimerControlStall \
-        TimerControlStall
-#endif
-#ifdef ROM_TimerRTCEnable
-#define MAP_TimerRTCEnable \
-        ROM_TimerRTCEnable
-#else
-#define MAP_TimerRTCEnable \
-        TimerRTCEnable
-#endif
-#ifdef ROM_TimerRTCDisable
-#define MAP_TimerRTCDisable \
-        ROM_TimerRTCDisable
-#else
-#define MAP_TimerRTCDisable \
-        TimerRTCDisable
-#endif
-#ifdef ROM_TimerPrescaleSet
-#define MAP_TimerPrescaleSet \
-        ROM_TimerPrescaleSet
-#else
-#define MAP_TimerPrescaleSet \
-        TimerPrescaleSet
-#endif
-#ifdef ROM_TimerPrescaleGet
-#define MAP_TimerPrescaleGet \
-        ROM_TimerPrescaleGet
-#else
-#define MAP_TimerPrescaleGet \
-        TimerPrescaleGet
-#endif
-#ifdef ROM_TimerPrescaleMatchSet
-#define MAP_TimerPrescaleMatchSet \
-        ROM_TimerPrescaleMatchSet
-#else
-#define MAP_TimerPrescaleMatchSet \
-        TimerPrescaleMatchSet
-#endif
-#ifdef ROM_TimerPrescaleMatchGet
-#define MAP_TimerPrescaleMatchGet \
-        ROM_TimerPrescaleMatchGet
-#else
-#define MAP_TimerPrescaleMatchGet \
-        TimerPrescaleMatchGet
-#endif
-#ifdef ROM_TimerLoadSet
-#define MAP_TimerLoadSet \
-        ROM_TimerLoadSet
-#else
-#define MAP_TimerLoadSet \
-        TimerLoadSet
-#endif
-#ifdef ROM_TimerLoadGet
-#define MAP_TimerLoadGet \
-        ROM_TimerLoadGet
-#else
-#define MAP_TimerLoadGet \
-        TimerLoadGet
-#endif
-#ifdef ROM_TimerValueGet
-#define MAP_TimerValueGet \
-        ROM_TimerValueGet
-#else
-#define MAP_TimerValueGet \
-        TimerValueGet
-#endif
-#ifdef ROM_TimerMatchSet
-#define MAP_TimerMatchSet \
-        ROM_TimerMatchSet
-#else
-#define MAP_TimerMatchSet \
-        TimerMatchSet
-#endif
-#ifdef ROM_TimerMatchGet
-#define MAP_TimerMatchGet \
-        ROM_TimerMatchGet
-#else
-#define MAP_TimerMatchGet \
-        TimerMatchGet
-#endif
-#ifdef ROM_TimerIntEnable
-#define MAP_TimerIntEnable \
-        ROM_TimerIntEnable
-#else
-#define MAP_TimerIntEnable \
-        TimerIntEnable
-#endif
-#ifdef ROM_TimerIntDisable
-#define MAP_TimerIntDisable \
-        ROM_TimerIntDisable
-#else
-#define MAP_TimerIntDisable \
-        TimerIntDisable
-#endif
-#ifdef ROM_TimerIntStatus
-#define MAP_TimerIntStatus \
-        ROM_TimerIntStatus
-#else
-#define MAP_TimerIntStatus \
-        TimerIntStatus
-#endif
-#ifdef ROM_TimerControlWaitOnTrigger
-#define MAP_TimerControlWaitOnTrigger \
-        ROM_TimerControlWaitOnTrigger
-#else
-#define MAP_TimerControlWaitOnTrigger \
-        TimerControlWaitOnTrigger
-#endif
-#ifdef ROM_TimerLoadSet64
-#define MAP_TimerLoadSet64 \
-        ROM_TimerLoadSet64
-#else
-#define MAP_TimerLoadSet64 \
-        TimerLoadSet64
-#endif
-#ifdef ROM_TimerLoadGet64
-#define MAP_TimerLoadGet64 \
-        ROM_TimerLoadGet64
-#else
-#define MAP_TimerLoadGet64 \
-        TimerLoadGet64
-#endif
-#ifdef ROM_TimerValueGet64
-#define MAP_TimerValueGet64 \
-        ROM_TimerValueGet64
-#else
-#define MAP_TimerValueGet64 \
-        TimerValueGet64
-#endif
-#ifdef ROM_TimerMatchSet64
-#define MAP_TimerMatchSet64 \
-        ROM_TimerMatchSet64
-#else
-#define MAP_TimerMatchSet64 \
-        TimerMatchSet64
-#endif
-#ifdef ROM_TimerMatchGet64
-#define MAP_TimerMatchGet64 \
-        ROM_TimerMatchGet64
-#else
-#define MAP_TimerMatchGet64 \
-        TimerMatchGet64
-#endif
-
-//*****************************************************************************
-//
-// Macros for the UART API.
-//
-//*****************************************************************************
-#ifdef ROM_UARTCharPut
-#define MAP_UARTCharPut \
-        ROM_UARTCharPut
-#else
-#define MAP_UARTCharPut \
-        UARTCharPut
-#endif
-#ifdef ROM_UARTParityModeSet
-#define MAP_UARTParityModeSet \
-        ROM_UARTParityModeSet
-#else
-#define MAP_UARTParityModeSet \
-        UARTParityModeSet
-#endif
-#ifdef ROM_UARTParityModeGet
-#define MAP_UARTParityModeGet \
-        ROM_UARTParityModeGet
-#else
-#define MAP_UARTParityModeGet \
-        UARTParityModeGet
-#endif
-#ifdef ROM_UARTFIFOLevelSet
-#define MAP_UARTFIFOLevelSet \
-        ROM_UARTFIFOLevelSet
-#else
-#define MAP_UARTFIFOLevelSet \
-        UARTFIFOLevelSet
-#endif
-#ifdef ROM_UARTFIFOLevelGet
-#define MAP_UARTFIFOLevelGet \
-        ROM_UARTFIFOLevelGet
-#else
-#define MAP_UARTFIFOLevelGet \
-        UARTFIFOLevelGet
-#endif
-#ifdef ROM_UARTConfigSetExpClk
-#define MAP_UARTConfigSetExpClk \
-        ROM_UARTConfigSetExpClk
-#else
-#define MAP_UARTConfigSetExpClk \
-        UARTConfigSetExpClk
-#endif
-#ifdef ROM_UARTConfigGetExpClk
-#define MAP_UARTConfigGetExpClk \
-        ROM_UARTConfigGetExpClk
-#else
-#define MAP_UARTConfigGetExpClk \
-        UARTConfigGetExpClk
-#endif
-#ifdef ROM_UARTEnable
-#define MAP_UARTEnable \
-        ROM_UARTEnable
-#else
-#define MAP_UARTEnable \
-        UARTEnable
-#endif
-#ifdef ROM_UARTDisable
-#define MAP_UARTDisable \
-        ROM_UARTDisable
-#else
-#define MAP_UARTDisable \
-        UARTDisable
-#endif
-#ifdef ROM_UARTEnableSIR
-#define MAP_UARTEnableSIR \
-        ROM_UARTEnableSIR
-#else
-#define MAP_UARTEnableSIR \
-        UARTEnableSIR
-#endif
-#ifdef ROM_UARTDisableSIR
-#define MAP_UARTDisableSIR \
-        ROM_UARTDisableSIR
-#else
-#define MAP_UARTDisableSIR \
-        UARTDisableSIR
-#endif
-#ifdef ROM_UARTCharsAvail
-#define MAP_UARTCharsAvail \
-        ROM_UARTCharsAvail
-#else
-#define MAP_UARTCharsAvail \
-        UARTCharsAvail
-#endif
-#ifdef ROM_UARTSpaceAvail
-#define MAP_UARTSpaceAvail \
-        ROM_UARTSpaceAvail
-#else
-#define MAP_UARTSpaceAvail \
-        UARTSpaceAvail
-#endif
-#ifdef ROM_UARTCharGetNonBlocking
-#define MAP_UARTCharGetNonBlocking \
-        ROM_UARTCharGetNonBlocking
-#else
-#define MAP_UARTCharGetNonBlocking \
-        UARTCharGetNonBlocking
-#endif
-#ifdef ROM_UARTCharGet
-#define MAP_UARTCharGet \
-        ROM_UARTCharGet
-#else
-#define MAP_UARTCharGet \
-        UARTCharGet
-#endif
-#ifdef ROM_UARTCharPutNonBlocking
-#define MAP_UARTCharPutNonBlocking \
-        ROM_UARTCharPutNonBlocking
-#else
-#define MAP_UARTCharPutNonBlocking \
-        UARTCharPutNonBlocking
-#endif
-#ifdef ROM_UARTBreakCtl
-#define MAP_UARTBreakCtl \
-        ROM_UARTBreakCtl
-#else
-#define MAP_UARTBreakCtl \
-        UARTBreakCtl
-#endif
-#ifdef ROM_UARTIntEnable
-#define MAP_UARTIntEnable \
-        ROM_UARTIntEnable
-#else
-#define MAP_UARTIntEnable \
-        UARTIntEnable
-#endif
-#ifdef ROM_UARTIntDisable
-#define MAP_UARTIntDisable \
-        ROM_UARTIntDisable
-#else
-#define MAP_UARTIntDisable \
-        UARTIntDisable
-#endif
-#ifdef ROM_UARTIntStatus
-#define MAP_UARTIntStatus \
-        ROM_UARTIntStatus
-#else
-#define MAP_UARTIntStatus \
-        UARTIntStatus
-#endif
-#ifdef ROM_UARTIntClear
-#define MAP_UARTIntClear \
-        ROM_UARTIntClear
-#else
-#define MAP_UARTIntClear \
-        UARTIntClear
-#endif
-#ifdef ROM_UARTDMAEnable
-#define MAP_UARTDMAEnable \
-        ROM_UARTDMAEnable
-#else
-#define MAP_UARTDMAEnable \
-        UARTDMAEnable
-#endif
-#ifdef ROM_UARTDMADisable
-#define MAP_UARTDMADisable \
-        ROM_UARTDMADisable
-#else
-#define MAP_UARTDMADisable \
-        UARTDMADisable
-#endif
-#ifdef ROM_UARTFIFOEnable
-#define MAP_UARTFIFOEnable \
-        ROM_UARTFIFOEnable
-#else
-#define MAP_UARTFIFOEnable \
-        UARTFIFOEnable
-#endif
-#ifdef ROM_UARTFIFODisable
-#define MAP_UARTFIFODisable \
-        ROM_UARTFIFODisable
-#else
-#define MAP_UARTFIFODisable \
-        UARTFIFODisable
-#endif
-#ifdef ROM_UARTBusy
-#define MAP_UARTBusy \
-        ROM_UARTBusy
-#else
-#define MAP_UARTBusy \
-        UARTBusy
-#endif
-#ifdef ROM_UARTTxIntModeSet
-#define MAP_UARTTxIntModeSet \
-        ROM_UARTTxIntModeSet
-#else
-#define MAP_UARTTxIntModeSet \
-        UARTTxIntModeSet
-#endif
-#ifdef ROM_UARTTxIntModeGet
-#define MAP_UARTTxIntModeGet \
-        ROM_UARTTxIntModeGet
-#else
-#define MAP_UARTTxIntModeGet \
-        UARTTxIntModeGet
-#endif
-#ifdef ROM_UARTRxErrorGet
-#define MAP_UARTRxErrorGet \
-        ROM_UARTRxErrorGet
-#else
-#define MAP_UARTRxErrorGet \
-        UARTRxErrorGet
-#endif
-#ifdef ROM_UARTRxErrorClear
-#define MAP_UARTRxErrorClear \
-        ROM_UARTRxErrorClear
-#else
-#define MAP_UARTRxErrorClear \
-        UARTRxErrorClear
-#endif
-#ifdef ROM_UARTClockSourceSet
-#define MAP_UARTClockSourceSet \
-        ROM_UARTClockSourceSet
-#else
-#define MAP_UARTClockSourceSet \
-        UARTClockSourceSet
-#endif
-#ifdef ROM_UARTClockSourceGet
-#define MAP_UARTClockSourceGet \
-        ROM_UARTClockSourceGet
-#else
-#define MAP_UARTClockSourceGet \
-        UARTClockSourceGet
-#endif
-#ifdef ROM_UART9BitEnable
-#define MAP_UART9BitEnable \
-        ROM_UART9BitEnable
-#else
-#define MAP_UART9BitEnable \
-        UART9BitEnable
-#endif
-#ifdef ROM_UART9BitDisable
-#define MAP_UART9BitDisable \
-        ROM_UART9BitDisable
-#else
-#define MAP_UART9BitDisable \
-        UART9BitDisable
-#endif
-#ifdef ROM_UART9BitAddrSet
-#define MAP_UART9BitAddrSet \
-        ROM_UART9BitAddrSet
-#else
-#define MAP_UART9BitAddrSet \
-        UART9BitAddrSet
-#endif
-#ifdef ROM_UART9BitAddrSend
-#define MAP_UART9BitAddrSend \
-        ROM_UART9BitAddrSend
-#else
-#define MAP_UART9BitAddrSend \
-        UART9BitAddrSend
-#endif
-
-//*****************************************************************************
-//
-// Macros for the uDMA API.
-//
-//*****************************************************************************
-#ifdef ROM_uDMAChannelTransferSet
-#define MAP_uDMAChannelTransferSet \
-        ROM_uDMAChannelTransferSet
-#else
-#define MAP_uDMAChannelTransferSet \
-        uDMAChannelTransferSet
-#endif
-#ifdef ROM_uDMAEnable
-#define MAP_uDMAEnable \
-        ROM_uDMAEnable
-#else
-#define MAP_uDMAEnable \
-        uDMAEnable
-#endif
-#ifdef ROM_uDMADisable
-#define MAP_uDMADisable \
-        ROM_uDMADisable
-#else
-#define MAP_uDMADisable \
-        uDMADisable
-#endif
-#ifdef ROM_uDMAErrorStatusGet
-#define MAP_uDMAErrorStatusGet \
-        ROM_uDMAErrorStatusGet
-#else
-#define MAP_uDMAErrorStatusGet \
-        uDMAErrorStatusGet
-#endif
-#ifdef ROM_uDMAErrorStatusClear
-#define MAP_uDMAErrorStatusClear \
-        ROM_uDMAErrorStatusClear
-#else
-#define MAP_uDMAErrorStatusClear \
-        uDMAErrorStatusClear
-#endif
-#ifdef ROM_uDMAChannelEnable
-#define MAP_uDMAChannelEnable \
-        ROM_uDMAChannelEnable
-#else
-#define MAP_uDMAChannelEnable \
-        uDMAChannelEnable
-#endif
-#ifdef ROM_uDMAChannelDisable
-#define MAP_uDMAChannelDisable \
-        ROM_uDMAChannelDisable
-#else
-#define MAP_uDMAChannelDisable \
-        uDMAChannelDisable
-#endif
-#ifdef ROM_uDMAChannelIsEnabled
-#define MAP_uDMAChannelIsEnabled \
-        ROM_uDMAChannelIsEnabled
-#else
-#define MAP_uDMAChannelIsEnabled \
-        uDMAChannelIsEnabled
-#endif
-#ifdef ROM_uDMAControlBaseSet
-#define MAP_uDMAControlBaseSet \
-        ROM_uDMAControlBaseSet
-#else
-#define MAP_uDMAControlBaseSet \
-        uDMAControlBaseSet
-#endif
-#ifdef ROM_uDMAControlBaseGet
-#define MAP_uDMAControlBaseGet \
-        ROM_uDMAControlBaseGet
-#else
-#define MAP_uDMAControlBaseGet \
-        uDMAControlBaseGet
-#endif
-#ifdef ROM_uDMAChannelRequest
-#define MAP_uDMAChannelRequest \
-        ROM_uDMAChannelRequest
-#else
-#define MAP_uDMAChannelRequest \
-        uDMAChannelRequest
-#endif
-#ifdef ROM_uDMAChannelAttributeEnable
-#define MAP_uDMAChannelAttributeEnable \
-        ROM_uDMAChannelAttributeEnable
-#else
-#define MAP_uDMAChannelAttributeEnable \
-        uDMAChannelAttributeEnable
-#endif
-#ifdef ROM_uDMAChannelAttributeDisable
-#define MAP_uDMAChannelAttributeDisable \
-        ROM_uDMAChannelAttributeDisable
-#else
-#define MAP_uDMAChannelAttributeDisable \
-        uDMAChannelAttributeDisable
-#endif
-#ifdef ROM_uDMAChannelAttributeGet
-#define MAP_uDMAChannelAttributeGet \
-        ROM_uDMAChannelAttributeGet
-#else
-#define MAP_uDMAChannelAttributeGet \
-        uDMAChannelAttributeGet
-#endif
-#ifdef ROM_uDMAChannelControlSet
-#define MAP_uDMAChannelControlSet \
-        ROM_uDMAChannelControlSet
-#else
-#define MAP_uDMAChannelControlSet \
-        uDMAChannelControlSet
-#endif
-#ifdef ROM_uDMAChannelSizeGet
-#define MAP_uDMAChannelSizeGet \
-        ROM_uDMAChannelSizeGet
-#else
-#define MAP_uDMAChannelSizeGet \
-        uDMAChannelSizeGet
-#endif
-#ifdef ROM_uDMAChannelModeGet
-#define MAP_uDMAChannelModeGet \
-        ROM_uDMAChannelModeGet
-#else
-#define MAP_uDMAChannelModeGet \
-        uDMAChannelModeGet
-#endif
-#ifdef ROM_uDMAChannelSelectSecondary
-#define MAP_uDMAChannelSelectSecondary \
-        ROM_uDMAChannelSelectSecondary
-#else
-#define MAP_uDMAChannelSelectSecondary \
-        uDMAChannelSelectSecondary
-#endif
-#ifdef ROM_uDMAChannelSelectDefault
-#define MAP_uDMAChannelSelectDefault \
-        ROM_uDMAChannelSelectDefault
-#else
-#define MAP_uDMAChannelSelectDefault \
-        uDMAChannelSelectDefault
-#endif
-#ifdef ROM_uDMAIntStatus
-#define MAP_uDMAIntStatus \
-        ROM_uDMAIntStatus
-#else
-#define MAP_uDMAIntStatus \
-        uDMAIntStatus
-#endif
-#ifdef ROM_uDMAIntClear
-#define MAP_uDMAIntClear \
-        ROM_uDMAIntClear
-#else
-#define MAP_uDMAIntClear \
-        uDMAIntClear
-#endif
-#ifdef ROM_uDMAControlAlternateBaseGet
-#define MAP_uDMAControlAlternateBaseGet \
-        ROM_uDMAControlAlternateBaseGet
-#else
-#define MAP_uDMAControlAlternateBaseGet \
-        uDMAControlAlternateBaseGet
-#endif
-#ifdef ROM_uDMAChannelScatterGatherSet
-#define MAP_uDMAChannelScatterGatherSet \
-        ROM_uDMAChannelScatterGatherSet
-#else
-#define MAP_uDMAChannelScatterGatherSet \
-        uDMAChannelScatterGatherSet
-#endif
-#ifdef ROM_uDMAChannelAssign
-#define MAP_uDMAChannelAssign \
-        ROM_uDMAChannelAssign
-#else
-#define MAP_uDMAChannelAssign \
-        uDMAChannelAssign
-#endif
-
-//*****************************************************************************
-//
-// Macros for the USB API.
-//
-//*****************************************************************************
-#ifdef ROM_USBIntStatus
-#define MAP_USBIntStatus \
-        ROM_USBIntStatus
-#else
-#define MAP_USBIntStatus \
-        USBIntStatus
-#endif
-#ifdef ROM_USBDevAddrGet
-#define MAP_USBDevAddrGet \
-        ROM_USBDevAddrGet
-#else
-#define MAP_USBDevAddrGet \
-        USBDevAddrGet
-#endif
-#ifdef ROM_USBDevAddrSet
-#define MAP_USBDevAddrSet \
-        ROM_USBDevAddrSet
-#else
-#define MAP_USBDevAddrSet \
-        USBDevAddrSet
-#endif
-#ifdef ROM_USBDevConnect
-#define MAP_USBDevConnect \
-        ROM_USBDevConnect
-#else
-#define MAP_USBDevConnect \
-        USBDevConnect
-#endif
-#ifdef ROM_USBDevDisconnect
-#define MAP_USBDevDisconnect \
-        ROM_USBDevDisconnect
-#else
-#define MAP_USBDevDisconnect \
-        USBDevDisconnect
-#endif
-#ifdef ROM_USBDevEndpointConfigSet
-#define MAP_USBDevEndpointConfigSet \
-        ROM_USBDevEndpointConfigSet
-#else
-#define MAP_USBDevEndpointConfigSet \
-        USBDevEndpointConfigSet
-#endif
-#ifdef ROM_USBDevEndpointDataAck
-#define MAP_USBDevEndpointDataAck \
-        ROM_USBDevEndpointDataAck
-#else
-#define MAP_USBDevEndpointDataAck \
-        USBDevEndpointDataAck
-#endif
-#ifdef ROM_USBDevEndpointStall
-#define MAP_USBDevEndpointStall \
-        ROM_USBDevEndpointStall
-#else
-#define MAP_USBDevEndpointStall \
-        USBDevEndpointStall
-#endif
-#ifdef ROM_USBDevEndpointStallClear
-#define MAP_USBDevEndpointStallClear \
-        ROM_USBDevEndpointStallClear
-#else
-#define MAP_USBDevEndpointStallClear \
-        USBDevEndpointStallClear
-#endif
-#ifdef ROM_USBDevEndpointStatusClear
-#define MAP_USBDevEndpointStatusClear \
-        ROM_USBDevEndpointStatusClear
-#else
-#define MAP_USBDevEndpointStatusClear \
-        USBDevEndpointStatusClear
-#endif
-#ifdef ROM_USBEndpointDataGet
-#define MAP_USBEndpointDataGet \
-        ROM_USBEndpointDataGet
-#else
-#define MAP_USBEndpointDataGet \
-        USBEndpointDataGet
-#endif
-#ifdef ROM_USBEndpointDataPut
-#define MAP_USBEndpointDataPut \
-        ROM_USBEndpointDataPut
-#else
-#define MAP_USBEndpointDataPut \
-        USBEndpointDataPut
-#endif
-#ifdef ROM_USBEndpointDataSend
-#define MAP_USBEndpointDataSend \
-        ROM_USBEndpointDataSend
-#else
-#define MAP_USBEndpointDataSend \
-        USBEndpointDataSend
-#endif
-#ifdef ROM_USBEndpointDataToggleClear
-#define MAP_USBEndpointDataToggleClear \
-        ROM_USBEndpointDataToggleClear
-#else
-#define MAP_USBEndpointDataToggleClear \
-        USBEndpointDataToggleClear
-#endif
-#ifdef ROM_USBEndpointStatus
-#define MAP_USBEndpointStatus \
-        ROM_USBEndpointStatus
-#else
-#define MAP_USBEndpointStatus \
-        USBEndpointStatus
-#endif
-#ifdef ROM_USBFIFOAddrGet
-#define MAP_USBFIFOAddrGet \
-        ROM_USBFIFOAddrGet
-#else
-#define MAP_USBFIFOAddrGet \
-        USBFIFOAddrGet
-#endif
-#ifdef ROM_USBFIFOConfigGet
-#define MAP_USBFIFOConfigGet \
-        ROM_USBFIFOConfigGet
-#else
-#define MAP_USBFIFOConfigGet \
-        USBFIFOConfigGet
-#endif
-#ifdef ROM_USBFIFOConfigSet
-#define MAP_USBFIFOConfigSet \
-        ROM_USBFIFOConfigSet
-#else
-#define MAP_USBFIFOConfigSet \
-        USBFIFOConfigSet
-#endif
-#ifdef ROM_USBFIFOFlush
-#define MAP_USBFIFOFlush \
-        ROM_USBFIFOFlush
-#else
-#define MAP_USBFIFOFlush \
-        USBFIFOFlush
-#endif
-#ifdef ROM_USBFrameNumberGet
-#define MAP_USBFrameNumberGet \
-        ROM_USBFrameNumberGet
-#else
-#define MAP_USBFrameNumberGet \
-        USBFrameNumberGet
-#endif
-#ifdef ROM_USBHostAddrGet
-#define MAP_USBHostAddrGet \
-        ROM_USBHostAddrGet
-#else
-#define MAP_USBHostAddrGet \
-        USBHostAddrGet
-#endif
-#ifdef ROM_USBHostAddrSet
-#define MAP_USBHostAddrSet \
-        ROM_USBHostAddrSet
-#else
-#define MAP_USBHostAddrSet \
-        USBHostAddrSet
-#endif
-#ifdef ROM_USBHostEndpointConfig
-#define MAP_USBHostEndpointConfig \
-        ROM_USBHostEndpointConfig
-#else
-#define MAP_USBHostEndpointConfig \
-        USBHostEndpointConfig
-#endif
-#ifdef ROM_USBHostEndpointDataAck
-#define MAP_USBHostEndpointDataAck \
-        ROM_USBHostEndpointDataAck
-#else
-#define MAP_USBHostEndpointDataAck \
-        USBHostEndpointDataAck
-#endif
-#ifdef ROM_USBHostEndpointDataToggle
-#define MAP_USBHostEndpointDataToggle \
-        ROM_USBHostEndpointDataToggle
-#else
-#define MAP_USBHostEndpointDataToggle \
-        USBHostEndpointDataToggle
-#endif
-#ifdef ROM_USBHostEndpointStatusClear
-#define MAP_USBHostEndpointStatusClear \
-        ROM_USBHostEndpointStatusClear
-#else
-#define MAP_USBHostEndpointStatusClear \
-        USBHostEndpointStatusClear
-#endif
-#ifdef ROM_USBHostHubAddrGet
-#define MAP_USBHostHubAddrGet \
-        ROM_USBHostHubAddrGet
-#else
-#define MAP_USBHostHubAddrGet \
-        USBHostHubAddrGet
-#endif
-#ifdef ROM_USBHostHubAddrSet
-#define MAP_USBHostHubAddrSet \
-        ROM_USBHostHubAddrSet
-#else
-#define MAP_USBHostHubAddrSet \
-        USBHostHubAddrSet
-#endif
-#ifdef ROM_USBHostPwrDisable
-#define MAP_USBHostPwrDisable \
-        ROM_USBHostPwrDisable
-#else
-#define MAP_USBHostPwrDisable \
-        USBHostPwrDisable
-#endif
-#ifdef ROM_USBHostPwrEnable
-#define MAP_USBHostPwrEnable \
-        ROM_USBHostPwrEnable
-#else
-#define MAP_USBHostPwrEnable \
-        USBHostPwrEnable
-#endif
-#ifdef ROM_USBHostPwrConfig
-#define MAP_USBHostPwrConfig \
-        ROM_USBHostPwrConfig
-#else
-#define MAP_USBHostPwrConfig \
-        USBHostPwrConfig
-#endif
-#ifdef ROM_USBHostPwrFaultDisable
-#define MAP_USBHostPwrFaultDisable \
-        ROM_USBHostPwrFaultDisable
-#else
-#define MAP_USBHostPwrFaultDisable \
-        USBHostPwrFaultDisable
-#endif
-#ifdef ROM_USBHostPwrFaultEnable
-#define MAP_USBHostPwrFaultEnable \
-        ROM_USBHostPwrFaultEnable
-#else
-#define MAP_USBHostPwrFaultEnable \
-        USBHostPwrFaultEnable
-#endif
-#ifdef ROM_USBHostRequestIN
-#define MAP_USBHostRequestIN \
-        ROM_USBHostRequestIN
-#else
-#define MAP_USBHostRequestIN \
-        USBHostRequestIN
-#endif
-#ifdef ROM_USBHostRequestStatus
-#define MAP_USBHostRequestStatus \
-        ROM_USBHostRequestStatus
-#else
-#define MAP_USBHostRequestStatus \
-        USBHostRequestStatus
-#endif
-#ifdef ROM_USBHostReset
-#define MAP_USBHostReset \
-        ROM_USBHostReset
-#else
-#define MAP_USBHostReset \
-        USBHostReset
-#endif
-#ifdef ROM_USBHostResume
-#define MAP_USBHostResume \
-        ROM_USBHostResume
-#else
-#define MAP_USBHostResume \
-        USBHostResume
-#endif
-#ifdef ROM_USBHostSpeedGet
-#define MAP_USBHostSpeedGet \
-        ROM_USBHostSpeedGet
-#else
-#define MAP_USBHostSpeedGet \
-        USBHostSpeedGet
-#endif
-#ifdef ROM_USBHostSuspend
-#define MAP_USBHostSuspend \
-        ROM_USBHostSuspend
-#else
-#define MAP_USBHostSuspend \
-        USBHostSuspend
-#endif
-#ifdef ROM_USBIntDisable
-#define MAP_USBIntDisable \
-        ROM_USBIntDisable
-#else
-#define MAP_USBIntDisable \
-        USBIntDisable
-#endif
-#ifdef ROM_USBIntEnable
-#define MAP_USBIntEnable \
-        ROM_USBIntEnable
-#else
-#define MAP_USBIntEnable \
-        USBIntEnable
-#endif
-#ifdef ROM_USBDevEndpointConfigGet
-#define MAP_USBDevEndpointConfigGet \
-        ROM_USBDevEndpointConfigGet
-#else
-#define MAP_USBDevEndpointConfigGet \
-        USBDevEndpointConfigGet
-#endif
-#ifdef ROM_USBEndpointDMAEnable
-#define MAP_USBEndpointDMAEnable \
-        ROM_USBEndpointDMAEnable
-#else
-#define MAP_USBEndpointDMAEnable \
-        USBEndpointDMAEnable
-#endif
-#ifdef ROM_USBEndpointDMADisable
-#define MAP_USBEndpointDMADisable \
-        ROM_USBEndpointDMADisable
-#else
-#define MAP_USBEndpointDMADisable \
-        USBEndpointDMADisable
-#endif
-#ifdef ROM_USBEndpointDataAvail
-#define MAP_USBEndpointDataAvail \
-        ROM_USBEndpointDataAvail
-#else
-#define MAP_USBEndpointDataAvail \
-        USBEndpointDataAvail
-#endif
-#ifdef ROM_USBOTGHostRequest
-#define MAP_USBOTGHostRequest \
-        ROM_USBOTGHostRequest
-#else
-#define MAP_USBOTGHostRequest \
-        USBOTGHostRequest
-#endif
-#ifdef ROM_USBModeGet
-#define MAP_USBModeGet \
-        ROM_USBModeGet
-#else
-#define MAP_USBModeGet \
-        USBModeGet
-#endif
-#ifdef ROM_USBEndpointDMAChannel
-#define MAP_USBEndpointDMAChannel \
-        ROM_USBEndpointDMAChannel
-#else
-#define MAP_USBEndpointDMAChannel \
-        USBEndpointDMAChannel
-#endif
-#ifdef ROM_USBIntDisableControl
-#define MAP_USBIntDisableControl \
-        ROM_USBIntDisableControl
-#else
-#define MAP_USBIntDisableControl \
-        USBIntDisableControl
-#endif
-#ifdef ROM_USBIntEnableControl
-#define MAP_USBIntEnableControl \
-        ROM_USBIntEnableControl
-#else
-#define MAP_USBIntEnableControl \
-        USBIntEnableControl
-#endif
-#ifdef ROM_USBIntStatusControl
-#define MAP_USBIntStatusControl \
-        ROM_USBIntStatusControl
-#else
-#define MAP_USBIntStatusControl \
-        USBIntStatusControl
-#endif
-#ifdef ROM_USBIntStatus
-#define MAP_USBIntStatus \
-        ROM_USBIntStatus
-#else
-#define MAP_USBIntStatus \
-        USBIntStatus
-#endif
-#ifdef ROM_USBIntDisableEndpoint
-#define MAP_USBIntDisableEndpoint \
-        ROM_USBIntDisableEndpoint
-#else
-#define MAP_USBIntDisableEndpoint \
-        USBIntDisableEndpoint
-#endif
-#ifdef ROM_USBIntEnableEndpoint
-#define MAP_USBIntEnableEndpoint \
-        ROM_USBIntEnableEndpoint
-#else
-#define MAP_USBIntEnableEndpoint \
-        USBIntEnableEndpoint
-#endif
-#ifdef ROM_USBIntStatusEndpoint
-#define MAP_USBIntStatusEndpoint \
-        ROM_USBIntStatusEndpoint
-#else
-#define MAP_USBIntStatusEndpoint \
-        USBIntStatusEndpoint
-#endif
-#ifdef ROM_USBHostMode
-#define MAP_USBHostMode \
-        ROM_USBHostMode
-#else
-#define MAP_USBHostMode \
-        USBHostMode
-#endif
-#ifdef ROM_USBDevMode
-#define MAP_USBDevMode \
-        ROM_USBDevMode
-#else
-#define MAP_USBDevMode \
-        USBDevMode
-#endif
-#ifdef ROM_USBPHYPowerOff
-#define MAP_USBPHYPowerOff \
-        ROM_USBPHYPowerOff
-#else
-#define MAP_USBPHYPowerOff \
-        USBPHYPowerOff
-#endif
-#ifdef ROM_USBPHYPowerOn
-#define MAP_USBPHYPowerOn \
-        ROM_USBPHYPowerOn
-#else
-#define MAP_USBPHYPowerOn \
-        USBPHYPowerOn
-#endif
-#ifdef ROM_USBOTGMode
-#define MAP_USBOTGMode \
-        ROM_USBOTGMode
-#else
-#define MAP_USBOTGMode \
-        USBOTGMode
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Watchdog API.
-//
-//*****************************************************************************
-#ifdef ROM_WatchdogIntClear
-#define MAP_WatchdogIntClear \
-        ROM_WatchdogIntClear
-#else
-#define MAP_WatchdogIntClear \
-        WatchdogIntClear
-#endif
-#ifdef ROM_WatchdogRunning
-#define MAP_WatchdogRunning \
-        ROM_WatchdogRunning
-#else
-#define MAP_WatchdogRunning \
-        WatchdogRunning
-#endif
-#ifdef ROM_WatchdogEnable
-#define MAP_WatchdogEnable \
-        ROM_WatchdogEnable
-#else
-#define MAP_WatchdogEnable \
-        WatchdogEnable
-#endif
-#ifdef ROM_WatchdogResetEnable
-#define MAP_WatchdogResetEnable \
-        ROM_WatchdogResetEnable
-#else
-#define MAP_WatchdogResetEnable \
-        WatchdogResetEnable
-#endif
-#ifdef ROM_WatchdogResetDisable
-#define MAP_WatchdogResetDisable \
-        ROM_WatchdogResetDisable
-#else
-#define MAP_WatchdogResetDisable \
-        WatchdogResetDisable
-#endif
-#ifdef ROM_WatchdogLock
-#define MAP_WatchdogLock \
-        ROM_WatchdogLock
-#else
-#define MAP_WatchdogLock \
-        WatchdogLock
-#endif
-#ifdef ROM_WatchdogUnlock
-#define MAP_WatchdogUnlock \
-        ROM_WatchdogUnlock
-#else
-#define MAP_WatchdogUnlock \
-        WatchdogUnlock
-#endif
-#ifdef ROM_WatchdogLockState
-#define MAP_WatchdogLockState \
-        ROM_WatchdogLockState
-#else
-#define MAP_WatchdogLockState \
-        WatchdogLockState
-#endif
-#ifdef ROM_WatchdogReloadSet
-#define MAP_WatchdogReloadSet \
-        ROM_WatchdogReloadSet
-#else
-#define MAP_WatchdogReloadSet \
-        WatchdogReloadSet
-#endif
-#ifdef ROM_WatchdogReloadGet
-#define MAP_WatchdogReloadGet \
-        ROM_WatchdogReloadGet
-#else
-#define MAP_WatchdogReloadGet \
-        WatchdogReloadGet
-#endif
-#ifdef ROM_WatchdogValueGet
-#define MAP_WatchdogValueGet \
-        ROM_WatchdogValueGet
-#else
-#define MAP_WatchdogValueGet \
-        WatchdogValueGet
-#endif
-#ifdef ROM_WatchdogIntEnable
-#define MAP_WatchdogIntEnable \
-        ROM_WatchdogIntEnable
-#else
-#define MAP_WatchdogIntEnable \
-        WatchdogIntEnable
-#endif
-#ifdef ROM_WatchdogIntStatus
-#define MAP_WatchdogIntStatus \
-        ROM_WatchdogIntStatus
-#else
-#define MAP_WatchdogIntStatus \
-        WatchdogIntStatus
-#endif
-#ifdef ROM_WatchdogStallEnable
-#define MAP_WatchdogStallEnable \
-        ROM_WatchdogStallEnable
-#else
-#define MAP_WatchdogStallEnable \
-        WatchdogStallEnable
-#endif
-#ifdef ROM_WatchdogStallDisable
-#define MAP_WatchdogStallDisable \
-        ROM_WatchdogStallDisable
-#else
-#define MAP_WatchdogStallDisable \
-        WatchdogStallDisable
-#endif
-#ifdef ROM_WatchdogIntTypeSet
-#define MAP_WatchdogIntTypeSet \
-        ROM_WatchdogIntTypeSet
-#else
-#define MAP_WatchdogIntTypeSet \
-        WatchdogIntTypeSet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Software API.
-//
-//*****************************************************************************
-#ifdef ROM_Crc16Array
-#define MAP_Crc16Array \
-        ROM_Crc16Array
-#else
-#define MAP_Crc16Array \
-        Crc16Array
-#endif
-#ifdef ROM_Crc16Array3
-#define MAP_Crc16Array3 \
-        ROM_Crc16Array3
-#else
-#define MAP_Crc16Array3 \
-        Crc16Array3
-#endif
-#ifdef ROM_Crc16
-#define MAP_Crc16 \
-        ROM_Crc16
-#else
-#define MAP_Crc16 \
-        Crc16
-#endif
-#ifdef ROM_Crc8CCITT
-#define MAP_Crc8CCITT \
-        ROM_Crc8CCITT
-#else
-#define MAP_Crc8CCITT \
-        Crc8CCITT
-#endif
-
-#endif // __ROM_MAP_H__
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rtos_bindings.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rtos_bindings.h
deleted file mode 100644
index 9c3df5da88..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rtos_bindings.h
+++ /dev/null
@@ -1,107 +0,0 @@
-//*****************************************************************************
-//
-// rtos_bindings.h - Macros ulIntIDended to aid porting of StellarisWare modules
-//                   for use with an RTOS.
-//
-// Copyright (c) 2012 Texas Instruments Incorporated.  All rights reserved.
-// Software License Agreement
-// 
-//   Redistribution and use in source and binary forms, with or without
-//   modification, are permitted provided that the following conditions
-//   are met:
-// 
-//   Redistributions of source code must retain the above copyright
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the
-//   documentation and/or other materials provided with the  
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// 
-// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-#ifndef RTOS_BINDINGS_H_
-#define RTOS_BINDINGS_H_
-
-#ifdef USE_RTOS
-//*****************************************************************************
-//
-// If an RTOS is in use, implement a header file called "stellaris_rtos.h"
-// which contains RTOS-specific versions of each of the macros defined below
-// and make sure it appears on the include path set when you build your
-// project.
-//
-// Note that there is no default implementation of this header file included
-// in StellarisWare - it is your responsibility to create it specifically for
-// your RTOS.
-//
-//*****************************************************************************
-#include "stellaris_rtos.h"
-
-#else
-//*****************************************************************************
-//
-// When no RTOS is in use, the follow macros compile to either nothing or a
-// minimal implementation that works in a bare-metal environment.
-//
-// Each of these macros must be redefined in stellaris_rtos.h if you are using
-// StellarisWare under an RTOS.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// A simple macro used to yield within polling loops.  In the default, non-RTOS
-// implementation, this compiles to nothing.
-//
-//*****************************************************************************
-#define OS_YIELD()
-
-//*****************************************************************************
-//
-// A simple macro around the SysCtlDelay function.  The parameter is the number
-// of 3 cycle loops to wait before returning (as for SysCtlDelay).  In an RTOS
-// implementation, this could be replaced with an OS delay call with
-// appropriate parameter scaling.
-//
-//*****************************************************************************
-#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles)
-
-//*****************************************************************************
-//
-// Wrappers around low level interrupt control functions.  For information
-// on each of these functions, please see the appropriate API documentation
-// for the DriverLib Interrupt driver.
-//
-// The macros defined here represent interrupt-control functions that may be
-// called from within StellarisWare code.  It is expected that application
-// code will use RTOS-specific functions to control interrupt priority, to
-// pend interrupts and to perform runtime vector manipulation.  As a result,
-// no macros are defined to wrap any of these functions from interrupt.c.
-//
-//*****************************************************************************
-#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable()
-#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable()
-#define OS_INT_DISABLE(ulIntID) MAP_IntDisable(ulIntID)
-#define OS_INT_ENABLE(ulIntID) MAP_IntEnable(ulIntID)
-
-#endif // USE_RTOS
-
-#endif // RTOS_BINDINGS_H_
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.c
deleted file mode 100644
index 00fbd65ad4..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.c
+++ /dev/null
@@ -1,841 +0,0 @@
-//###########################################################################
-//
-// FILE:   sysctl.c
-//
-// TITLE:  Stellaris style wrapper driver for F2837x system control.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-//*****************************************************************************
-//
-//! \addtogroup sysctl_api
-//! @{
-//
-//*****************************************************************************
-
-#include "F28x_Project.h"
-#include <stdint.h>
-#include <stdbool.h>
-#include "inc/hw_types.h"
-#include "driverlib/debug.h"
-#include "driverlib/sysctl.h"
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a peripheral identifier.
-//!
-//! \param ui32Peripheral is the peripheral identifier.
-//!
-//! This function determines if a peripheral identifier is valid.
-//!
-//! \return Returns \b true if the peripheral identifier is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static bool
-_SysCtlPeripheralValid(uint32_t ui32Peripheral)
-{
-    return((ui32Peripheral == SYSCTL_PERIPH_CLA1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_DMA) ||
-           (ui32Peripheral == SYSCTL_PERIPH_TIMER0) ||
-           (ui32Peripheral == SYSCTL_PERIPH_TIMER1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_TIMER2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_HRPWM) ||
-           (ui32Peripheral == SYSCTL_PERIPH_TBCLKSYNC) ||
-           (ui32Peripheral == SYSCTL_PERIPH_GTBCLKSYNC) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EMIF1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EMIF2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM3) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM4) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM5) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM6) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM7) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM8) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM9) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM10) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM11) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EPWM12) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ECAP1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ECAP2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ECAP3) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ECAP4) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ECAP5) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ECAP6) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EQEP1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EQEP2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_EQEP3) ||
-           (ui32Peripheral == SYSCTL_PERIPH_SD1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_SD2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_SCI1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_SCI2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_SCI3) ||
-           (ui32Peripheral == SYSCTL_PERIPH_SCI4) ||
-           (ui32Peripheral == SYSCTL_PERIPH_SPI1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_SPI2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_SPI3) ||
-           (ui32Peripheral == SYSCTL_PERIPH_I2C1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_I2C2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CAN1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CAN2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_MCBSP1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_MCBSP2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_UPP1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ADC1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ADC2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ADC3) ||
-           (ui32Peripheral == SYSCTL_PERIPH_ADC4) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CMPSS1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CMPSS2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CMPSS3) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CMPSS4) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CMPSS5) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CMPSS6) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CMPSS7) ||
-           (ui32Peripheral == SYSCTL_PERIPH_CMPSS8) ||
-           (ui32Peripheral == SYSCTL_PERIPH_BUFFDAC1) ||
-           (ui32Peripheral == SYSCTL_PERIPH_BUFFDAC2) ||
-           (ui32Peripheral == SYSCTL_PERIPH_BUFFDAC3));
-}
-#endif
-
-
-
-//*****************************************************************************
-//
-//! Determines if a peripheral is present.
-//!
-//! \param ui32Peripheral is the peripheral in question.
-//!
-//! This function determines if a particular peripheral is present in the
-//! device.  Each member of the family has a different peripheral
-//! set; this function determines which peripherals are present on this device.
-//!
-//! \return Returns \b true if the specified peripheral is present and \b false
-//! if it is not.
-//
-//*****************************************************************************
-bool
-SysCtlPeripheralPresent(uint32_t ui32Peripheral)
-{
-
-    uint16_t regIndex;
-    uint16_t bitIndex;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
-
-
-    regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M;
-    bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S;
-
-    if(HWREG(&(DevCfgRegs.DC0.all) + (2 * regIndex)) & (1 << bitIndex)){
-        return true;
-    }else{
-        return false;
-    }
-
-
-}
-
-//*****************************************************************************
-//
-//! Determines if a peripheral is ready.
-//!
-//! \param ui32Peripheral is the peripheral in question.
-//!
-//! This function determines if a particular peripheral is ready to be
-//! accessed.  The peripheral may be in a non-ready state if it is not enabled,
-//! is being held in reset, or is in the process of becoming ready after being
-//! enabled or taken out of reset.
-//!
-//! \note The ability to check for a peripheral being ready varies based on the
-//! part in use.  Please consult the data sheet for the part you are
-//! using to determine if this feature is available.
-//!
-//! \return Returns \b true if the specified peripheral is ready and \b false
-//! if it is not.
-//
-//*****************************************************************************
-bool
-SysCtlPeripheralReady(uint32_t ui32Peripheral)
-{
-
-    uint16_t regIndex;
-    uint16_t bitIndex;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
-
-
-    regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M;
-    bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S;
-
-    // Is the peripheral there?
-    if(HWREG((uint32_t)&(DevCfgRegs.DC0.all) + (2 * regIndex)) & ((uint32_t)1 << bitIndex)){
-        // Is the peripheral enabled?
-        if(HWREG((uint32_t)&(CpuSysRegs.PCLKCR0.all) + (2 * regIndex)) & ((uint32_t)1 << bitIndex)){
-            // Is the peripheral in reset?
-            if((HWREG((uint32_t)&(DevCfgRegs.SOFTPRES0.all) + (2 * regIndex)) & ((uint32_t)1 << bitIndex)) == 0){
-                // No?  Ok cool
-                return true;
-            }
-        }
-    }else{
-        return false;
-    }
-
-    return false;
-}
-//*****************************************************************************
-//
-//! Resets a peripheral
-//!
-//! \param ui32Peripheral is the peripheral to reset.
-//!
-//! The f2837x devices do not have a means of resetting peripherals via
-//! via software.  This is a dummy function that does nothing.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void SysCtlPeripheralReset(uint32_t ui32Peripheral)
-{
-    uint16_t regIndex;
-    uint16_t bitIndex;
-
-    regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M;
-    bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S;
-
-    EALLOW;
-
-    HWREG((uint32_t)&(DevCfgRegs.SOFTPRES0.all) + (2 * regIndex)) |= ((uint32_t)1 << bitIndex);
-    asm(" nop");
-    asm(" nop");
-    asm(" nop");
-    asm(" nop");
-    HWREG((uint32_t)&(DevCfgRegs.SOFTPRES0.all) + (2 * regIndex)) &= ~((uint32_t)1 << bitIndex);
-    EDIS;
-}
-
-//*****************************************************************************
-//
-//! Enables a peripheral.
-//!
-//! \param ui32Peripheral is the peripheral to enable.
-//!
-//! Peripherals are enabled with this function.  At power-up, all peripherals
-//! are disabled; they must be enabled in order to operate or respond to
-//! register reads/writes.
-//!
-//! The \e ui32Peripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_UART_A, \b SYSCTL_PERIPH_UART_B, \b SYSCTL_PERIPH_UART_C,
-//! \b SYSCTL_PERIPH_UART_D, \b SYSCTL_PERIPH_SPI_A, \b SYSCTL_PERIPH_SPI_B,
-//! \b SYSCTL_PERIPH_SPI_C, \b SYSCTL_PERIPH_MCBSP_A, \b SYSCTL_PERIPH_MCBSP_B,
-//! \b SYSCTL_PERIPH_DMA, \b SYSCTL_PERIPH_USB_A
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralEnable(uint32_t ui32Peripheral)
-{
-    uint16_t regIndex;
-    uint16_t bitIndex;
-    volatile uint32_t test1, test2, test3, test4;
-
-    regIndex = (ui32Peripheral & SYSCTL_PERIPH_REG_M);
-    bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S;
-
-    EALLOW;
-    HWREG((uint32_t)&(CpuSysRegs.PCLKCR0.all) + (2 * regIndex)) |= ((uint32_t)1 << bitIndex);
-
-    EDIS;
-}
-
-//*****************************************************************************
-//
-//! Disables a peripheral.
-//!
-//! \param ui32Peripheral is the peripheral to disable.
-//!
-//! Peripherals are disabled with this function.  Once disabled, they will not
-//! operate or respond to register reads/writes.
-//!
-//! The \e ui32Peripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_UART_A, \b SYSCTL_PERIPH_UART_B, \b SYSCTL_PERIPH_UART_C,
-//! \b SYSCTL_PERIPH_UART_D, \b SYSCTL_PERIPH_SPI_A, \b SYSCTL_PERIPH_SPI_B,
-//! \b SYSCTL_PERIPH_SPI_C, \b SYSCTL_PERIPH_MCBSP_A, \b SYSCTL_PERIPH_MCBSP_B,
-//! \b SYSCTL_PERIPH_DMA, \b SYSCTL_PERIPH_USB_A
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlPeripheralDisable(uint32_t ui32Peripheral)
-{
-    uint16_t regIndex;
-    uint16_t bitIndex;
-
-    regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M;
-    bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S;
-
-    EALLOW;
-
-    HWREG((uint32_t)&(CpuSysRegs.PCLKCR0.all) + (2 * regIndex)) &= ~((uint32_t)1 << bitIndex);
-
-    EDIS;
-}
-
-//*****************************************************************************
-//
-//! Resets the device.
-//!
-//! This function performs a software reset of the entire device.  The
-//! processor and all peripherals are reset and all device registers are
-//! returned to their default values (with the exception of the reset cause
-//! register, which maintains its current value but has the software reset
-//! bit set as well).
-//!
-//! \return This function does not return.
-//
-//*****************************************************************************
-void
-SysCtlReset(void)
-{
-    //
-    // Write an incorrect check value to the watchdog control register
-    // This will cause a device reset
-    //
-    EALLOW;
-    // Enable the watchdog
-    HWREG(&(WdRegs.WDCR.all)) = 0x0028;
-    // Write a bad check value
-    HWREG(&(WdRegs.WDCR.all)) = 0xFFFF;
-    EDIS;
-
-    //
-    // The device should have reset, so this should never be reached.  Just in
-    // case, loop forever.
-    //
-    while(1)
-    {
-    }
-}
-
-
-//*****************************************************************************
-//
-//! Provides a small delay.
-//!
-//! \param ulCount is the number of delay loop iterations to perform.
-//!
-//! This function provides a means of generating a constant length delay.  It
-//! is written in assembly to keep the delay consistent across tool chains,
-//! avoiding the need to tune the delay based on the tool chain in use.
-//!
-//! The loop takes 5 cycles/loop + 9.
-//!
-//! \return None.
-//
-//*****************************************************************************
-#ifdef __TI_COMPILER_VERSION__
-    #if __TI_COMPILER_VERSION__ >= 15009000
-    __asm(" .def _SysCtlDelay\n"
-          " .sect \".TI.ramfunc\"\n"
-          " .global  _SysCtlDelay\n"
-          "_SysCtlDelay:\n"
-          " SUB    ACC,#1\n"
-          " BF     _SysCtlDelay,GEQ\n"
-          " LRETR\n");    
-    #else
-    __asm(" .def _SysCtlDelay\n"
-          " .sect \"ramfuncs\"\n"
-          " .global  _SysCtlDelay\n"
-          "_SysCtlDelay:\n"
-          " SUB    ACC,#1\n"
-          " BF     _SysCtlDelay,GEQ\n"
-          " LRETR\n");        
-    #endif
-#endif
-
-//*****************************************************************************
-//
-//! Gets the processor clock rate.
-//!
-//! This function determines the clock rate of the processor clock.
-//!
-//! \note Because of the many different clocking options available, this
-//!  function cannot determine the clock speed of the processor.  This function
-//!  should be modified to return the actual clock speed of the processor in
-//!  your specific application.
-//!
-//! \return The processor clock rate.
-//
-//*****************************************************************************
-uint32_t
-SysCtlClockGet(uint32_t u32ClockIn)
-{
-
-    if((ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0) ||
-            (ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 2)){
-        //10MHz Internal Clock
-        u32ClockIn = 10000000;
-    }
-
-    //If the pll is enabled calculate its effect on the clock
-//    if((HWREG(SYSCTL_SYSPLLCTL) &
-//        (SYSCTL_SYSPLLCTL_SPLLEN | SYSCTL_SYSPLLCTL_SPLLCLKEN)) == 3)
-    if(ClkCfgRegs.SYSPLLCTL1.bit.PLLEN && ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN)
-    {
-        //Calculate integer multiplier and fixed divide by 2
-//        ulClockIn = ulClockIn *
-//                    (HWREG(SYSCTL_SYSPLLMULT) & SYSCTL_SYSPLLMULT_SPLLIMULT_M);
-        u32ClockIn = u32ClockIn * ClkCfgRegs.SYSPLLMULT.bit.IMULT;
-
-
-        //Calculate fractional multiplier
-//        switch((HWREG(SYSCTL_SYSPLLMULT) & SYSCTL_SYSPLLMULT_SPLLFMULT_M) >>
-//                SYSCTL_SYSPLLMULT_SPLLFMULT_S)
-        switch(ClkCfgRegs.SYSPLLMULT.bit.FMULT)
-        {
-        default:
-        case 0:
-            break;
-
-        case 1:
-            u32ClockIn += u32ClockIn / 4;
-            break;
-
-        case 2:
-            u32ClockIn += u32ClockIn / 2;
-            break;
-
-        case 3:
-            u32ClockIn += (u32ClockIn * 3) / 4;
-            break;
-        }
-    }
-
-    if(ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV != 0){
-        u32ClockIn /= (2 * ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV);
-    }
-
-    return u32ClockIn;
-
-}
-
-//*****************************************************************************
-//
-//! Gets the low speed peripheral clock rate.
-//!
-//! This function determines the clock rate of the low speed peripherals.
-//!
-//! \note Because of the many different clocking options available, this
-//!  function cannot determine the clock speed of the processor.  This function
-//!  should be modified to return the actual clock speed of the processor in
-//!  your specific application.
-//!
-//! \return The low speed peripheral clock rate.
-//
-//*****************************************************************************
-uint32_t
-SysCtlLowSpeedClockGet(uint32_t u32ClockIn)
-{
-
-    // Get the main system clock
-    u32ClockIn = SysCtlClockGet(u32ClockIn);
-
-    // Apply the divider to the main clock
-    if(ClkCfgRegs.LOSPCP.bit.LSPCLKDIV != 0){
-        u32ClockIn /= (2 * ClkCfgRegs.LOSPCP.bit.LSPCLKDIV);
-    }
-
-    return u32ClockIn;
-
-}
-
-//*****************************************************************************
-//
-//! Sets the clocking of the device.
-//!
-//! \param ui32Config is the required configuration of the device clocking.
-//!
-//! This function configures the clocking of the device.  The oscillator to be 
-//! used, SYSPLL fractional and integer multiplier, and the system clock
-//! divider are all configured with this function.
-//!
-//! The \e ui32Config parameter is the logical OR of four values:
-//! Clock divider, Integer multiplier, Fractional multiplier, and oscillator
-//! source. 
-//!
-//! The system clock divider is chosen with using the following macro:
-//! \b SYSCTL_SYSDIV(x) - "x" is an integer of value 1 or any even value
-//!                       up to 126
-//!
-//! The System PLL fractional multiplier is chosen with one of the following 
-//! values:
-//! \b SYSCTL_FMULT_0, \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2,
-//! \b SYSCTL_FMULT_3_4
-//!
-//! The System PLL integer multiplier is chosen with using the following macro:
-//! \b SYSCTL_IMULT(x) - "x" is an integer from 0 to 127
-//!
-//! The oscillator source is chosen with one of the following values:
-//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, \b SYSCTL_OSCSRC_OSC1
-//!
-//! \note The external oscillator must be enabled in order to use an external 
-//! clock source.  Note that attempts to disable the oscillator used to clock 
-//! the device is prevented by the hardware.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlClockSet(uint32_t ui32Config)
-{
-    uint32_t clock_source = (ui32Config & SYSCTL_OSCSRC_M) >> SYSCTL_OSCSRC_S;
-    uint32_t imult = (ui32Config & SYSCTL_IMULT_M);
-    uint32_t fmult = (ui32Config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S;
-    uint32_t divsel = (ui32Config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S;
-    
-    if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL)    &&
-      (imult         == ClkCfgRegs.SYSPLLMULT.bit.IMULT)           &&
-      (fmult         == ClkCfgRegs.SYSPLLMULT.bit.FMULT)           &&
-      (divsel        == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV))
-    {
-        //everything is set as required, so just return
-        return;
-    }    
- 
-    if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL)
-    {
-        //Configure Oscillator
-        EALLOW;
-        switch (clock_source)
-        {
-            case ((uint32_t)SYSCTL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S):
-                ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0;     // Turn on INTOSC2
-                ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2
-				ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1;        // Turn off XTALOSC
-                break;
-
-            case ((uint32_t)SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S):
-                ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0;        // Turn on XTALOSC
-                ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL
-                break;
-
-            case ((uint32_t)SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S):
-                ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1
-				ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1;        // Turn off XTALOSC
-                break;
-        }
-        EDIS; 
-    }
-    
-    EALLOW;
-    // first modify the PLL multipliers
-    if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || 
-       fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT)
-    {
-        // Bypass PLL and set dividers to /1
-        ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0;
-        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0;
-
-        // Program PLL multipliers
-        uint32_t temp_syspllmult = ClkCfgRegs.SYSPLLMULT.all;
-        ClkCfgRegs.SYSPLLMULT.all = ((temp_syspllmult & ~(0x37FU)) | 
-                                     ((fmult << 8U) | imult));
-               
-        ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1;            // Enable SYSPLL
-
-        // Wait for the SYSPLL lock
-        while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1)
-        {
-            // Uncomment to service the watchdog
-            //WdRegs.WDKEY.bit.WDKEY = 0x0055;
-            //WdRegs.WDKEY.bit.WDKEY = 0x00AA;
-        }
-
-        // Write a multiplier again to ensure proper PLL initialization
-        // This will force the PLL to lock a second time
-        ClkCfgRegs.SYSPLLMULT.bit.IMULT = imult;        // Setting integer multiplier
-
-        // Wait for the SYSPLL re-lock
-        while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1)
-        {
-            // Uncomment to service the watchdog
-            //WdRegs.WDKEY.bit.WDKEY = 0x0055;
-            //WdRegs.WDKEY.bit.WDKEY = 0x00AA;
-        }        
-    }
-    
-    // Set divider to produce slower output frequency to limit current increase
-    if(divsel != (126/2))
-    {
-        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1;
-    }
-    else
-    {
-        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;
-    } 
-
-    // Enable PLLSYSCLK is fed from system PLL clock
-    ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;
-
-    // Small 100 cycle delay
-    asm(" RPT #100 || NOP");
-
-    // Set the divider to user value
-    ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;    
-
-    EDIS;
-}
-
-//*****************************************************************************
-//
-//! Sets the clocking of the device.
-//!
-//! \param ui32Config is the required configuration of the device clocking.
-//!
-//! This function configures the clocking of the device.  The input crystal
-//! frequency, oscillator to be used, use of the PLL, and the system clock
-//! divider are all configured with this function.
-//!
-//! The \e ui32Config parameter is the logical OR of several different values,
-//! many of which are grouped into sets where only one can be chosen.
-//!
-//! The system clock divider is chosen with one of the following values:
-//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ...
-//! \b SYSCTL_SYSDIV_64.
-//!
-//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or
-//! \b SYSCTL_USE_OSC.
-//!
-//! The external crystal frequency is chosen with one of the following values:
-//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ,
-//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ,
-//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ,
-//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ,
-//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ,
-//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ,
-//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz.
-//! Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in
-//! operation.
-//!
-//! The oscillator source is chosen with one of the following values:
-//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4,
-//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32.  \b SYSCTL_OSC_EXT32 is only
-//! available on devices with the hibernate module, and then only when the
-//! hibernate module has been enabled.
-//!
-//! The internal and main oscillators are disabled with the
-//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.
-//! The external oscillator must be enabled in order to use an external clock
-//! source.  Note that attempts to disable the oscillator used to clock the
-//! device is prevented by the hardware.
-//!
-//! To clock the system from an external source (such as an external crystal
-//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN.  To clock the
-//! system from the main oscillator, use \b SYSCTL_USE_OSC \b |
-//! \b SYSCTL_OSC_MAIN.  To clock the system from the PLL, use
-//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate
-//! crystal with one of the \b SYSCTL_XTAL_xxx values.
-//!
-//! \note If selecting the PLL as the system clock source (that is, via
-//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to
-//! determine when the PLL has locked.  If an interrupt handler for the
-//! system control interrupt is in place, and it responds to and clears the
-//! PLL lock interrupt, this function delays until its timeout has occurred
-//! instead of completing as soon as PLL lock is achieved.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlAuxClockSet(uint32_t ui32Config)
-{
-    uint16_t ui16TempDivsel;
-
-    //Bypass PLL
-    //Ensure the PLL is out of our clock tree
-    EALLOW;
-    ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0;
-    EDIS;
-
-    __asm( " RPT #255 || NOP");
-
-    //Configure Oscillator
-    EALLOW;
-    switch (ui32Config & SYSCTL_OSCSRC_M)
-    {
-        default:
-        case SYSCTL_OSCSRC_OSC2:
-            ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0;     // Turn on INTOSC2
-            ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2
-			ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1;        // Turn off XTALOSC
-            break;
-
-        case SYSCTL_OSCSRC_XTAL:
-            ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0;        // Turn on XTALOSC
-            ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL
-            break;
-
-        case SYSCTL_OSCSRC_OSC1:
-            ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = INTOSC1
-			ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1;        // Turn off XTALOSC
-            break;
-
-    }
-    EDIS;
-
-    __asm( " RPT #255 || NOP");
-
-    //Configure PLL if enabled
-    if(ui32Config & SYSCTL_PLL_ENABLE)
-    {
-        EALLOW;
-        //modify dividers to maximum to reduce the inrush current
-        //set the integer fractional multipliers in one single write
-        ClkCfgRegs.AUXPLLMULT.all = ((ui32Config & SYSCTL_IMULT_M) >> SYSCTL_IMULT_S) |
-        		                    (((ui32Config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S) << 8);
-        EDIS;
-
-        __asm( " RPT #255 || NOP");
-
-        //Wait for the SYSPLL lock
-        while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1)
-        {
-            // Uncomment to service the watchdog
-            // ServiceDog();
-        }
-    }
-
-    //Configure Dividers
-    //increase the freq. of operation in steps to avoid any VDD fluctuations
-    ui16TempDivsel = 3;
-    while(ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV != ((ui32Config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S))
-    {
-        EALLOW;
-        ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = ui16TempDivsel;
-        EDIS;
-        ui16TempDivsel -= 1;
-        if(ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV != ((ui32Config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S))
-        {
-            SysCtlDelay(15);
-        }
-    }
-
-    //Enable PLLSYSCLK is fed from system PLL clock
-    EALLOW;
-    ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1;
-    EDIS;
-}
-
-//*****************************************************************************
-//
-//! Powers up the USB PLL.
-//!
-//! This function will enable the USB controller's PLL.
-//!
-//! \note Because every application is different, the user will likely have to
-//! modify this function to ensure the PLL multiplier is set correctly to
-//! achieve the 60 MHz required by the USB controller.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlUSBPLLEnable(void)
-{
-//    // Turn on INTOSC2
-//    ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0;
-//    //Select INTOSC2 as USB PLL Clk In
-//    ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0;
-//    // Set Aux PLL divider
-//    ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = 1;
-//    // Set Aux PLL multiplier
-//    ClkCfgRegs.AUXPLLMULT.bit.IMULT = 12;
-//    // Set Aux PLL fractional multiplier to 0.0
-//  ClkCfgRegs.AUXPLLMULT.bit.FMULT = 0;
-//    //Enable AUXPLL
-//  ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1;
-//
-//    //Wait for the AUXPLL lock
-//  while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1)
-//  {
-//      // Uncomment to service the watchdog
-//      // ServiceDog();
-//  }
-//    // AUXPLLCLK is fed from the AUXPLL
-//  ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1;
-
-}
-
-//*****************************************************************************
-//
-//! Powers down the USB PLL.
-//!
-//! This function will disable the USB controller's PLL.  The USB registers
-//! are still accessible, but the physical layer will no longer function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysCtlUSBPLLDisable(void)
-{
-    //Disable the PLL
-//    ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.h
deleted file mode 100644
index db3c9552de..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.h
+++ /dev/null
@@ -1,283 +0,0 @@
-//###########################################################################
-//
-// FILE:   sysctl.h
-//
-// TITLE:  Stellaris style wrapper driver for F2837x system control.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __SYSCTL_H__
-#define __SYSCTL_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-//*****************************************************************************
-//
-//! \addtogroup sysctl_api
-//! @{
-//
-//*****************************************************************************
-#include "inc/hw_types.h"
-//*****************************************************************************
-//
-//! Defined system clock oscillator source speed.  Adjust this to reflect your
-//! actual clock speed.
-//
-//*****************************************************************************
-#if defined(_LAUNCHXL_F28379D) || defined(_LAUNCHXL_F28377S)
-#define SYSTEM_CLOCK_SPEED      10000000
-#else
-#define SYSTEM_CLOCK_SPEED      20000000
-#endif
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the SysCtlClockSet() API as
-// the ui32Config parameter.
-//
-//*****************************************************************************
-#define SYSCTL_SYSDIV_M         0x00001F80
-#define SYSCTL_SYSDIV_S         0x00000007
-// Only 1 or even values up to 126 are allowed
-#define SYSCTL_SYSDIV(x)        ((((x == 1) ? 0 : (x / 2)) << SYSCTL_SYSDIV_S) & SYSCTL_SYSDIV_M)
-
-#define SYSCTL_IMULT_M          0x0000007F
-#define SYSCTL_IMULT_S          0x00000000
-#define SYSCTL_IMULT(x)         (((x) << SYSCTL_IMULT_S) & SYSCTL_IMULT_M)
-
-#define SYSCTL_FMULT_M          0x00006000
-#define SYSCTL_FMULT_S          0x0000000D
-#define SYSCTL_FMULT_0          0x00000000
-#define SYSCTL_FMULT_1_4        0x00002000
-#define SYSCTL_FMULT_1_2        0x00004000
-#define SYSCTL_FMULT_3_4        0x00006000
-
-#define SYSCTL_OSCSRC_M         0x00030000
-#define SYSCTL_OSCSRC_S         0x00000010
-#define SYSCTL_OSCSRC_OSC2      0x00000000
-#define SYSCTL_OSCSRC_XTAL      0x00010000
-#define SYSCTL_OSCSRC_OSC1      0x00020000
-
-#define SYSCTL_LSDIV_M          0x00700000
-#define SYSCTL_LSDIV_S          0x00000014
-// Only 1 or even values up to 14 are allowed
-#define SYSCTL_LSDIV(x)         (((x == 1) ? 0 : (x / 2)) << SYSCTL_LSDIV_S) & SYSCTL_LSDIV_M)
-
-#define SYSCTL_PLL_ENABLE       0x80000000
-#define SYSCTL_PLL_DISABLE      0x00000000
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the
-// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
-// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
-// ui32Peripheral parameter.  The peripherals in the fourth group (upper nibble
-// is 3) can only be used with the SysCtlPeripheralPresent() API.
-//
-//*****************************************************************************
-#define SYSCTL_PERIPH_REG_M             0x0000001F
-#define SYSCTL_PERIPH_REG_S             0x00000000
-
-#define SYSCTL_PERIPH_BIT_M             0x003F0000
-#define SYSCTL_PERIPH_BIT_S             0x00000010
-
-//PCLKCR0
-#define SYSCTL_PERIPH_CLA1              0x00000000
-#define SYSCTL_PERIPH_DMA               0x00020000
-#define SYSCTL_PERIPH_TIMER0            0x00030000
-#define SYSCTL_PERIPH_TIMER1            0x00040000
-#define SYSCTL_PERIPH_TIMER2            0x00050000
-#define SYSCTL_PERIPH_HRPWM             0x00100000
-#define SYSCTL_PERIPH_TBCLKSYNC         0x00120000
-#define SYSCTL_PERIPH_GTBCLKSYNC        0x00130000
-
-//PCLKCR1
-#define SYSCTL_PERIPH_EMIF1             0x00000001
-#define SYSCTL_PERIPH_EMIF2             0x00010001
-
-//PCLKCR2
-#define SYSCTL_PERIPH_EPWM1             0x00000002
-#define SYSCTL_PERIPH_EPWM2             0x00010002
-#define SYSCTL_PERIPH_EPWM3             0x00020002
-#define SYSCTL_PERIPH_EPWM4             0x00030002
-#define SYSCTL_PERIPH_EPWM5             0x00040002
-#define SYSCTL_PERIPH_EPWM6             0x00050002
-#define SYSCTL_PERIPH_EPWM7             0x00060002
-#define SYSCTL_PERIPH_EPWM8             0x00070002
-#define SYSCTL_PERIPH_EPWM9             0x00080002
-#define SYSCTL_PERIPH_EPWM10            0x00090002
-#define SYSCTL_PERIPH_EPWM11            0x000A0002
-#define SYSCTL_PERIPH_EPWM12            0x000B0002
-
-//PCLKCR3
-#define SYSCTL_PERIPH_ECAP1             0x00000003
-#define SYSCTL_PERIPH_ECAP2             0x00010003
-#define SYSCTL_PERIPH_ECAP3             0x00020003
-#define SYSCTL_PERIPH_ECAP4             0x00030003
-#define SYSCTL_PERIPH_ECAP5             0x00040003
-#define SYSCTL_PERIPH_ECAP6             0x00050003
-
-//PCLKCR4
-#define SYSCTL_PERIPH_EQEP1             0x00000004
-#define SYSCTL_PERIPH_EQEP2             0x00010004
-#define SYSCTL_PERIPH_EQEP3             0x00020004
-
-//PCLKCR5
-//Reserved
-
-//PCLKCR6
-#define SYSCTL_PERIPH_SD1               0x00000006
-#define SYSCTL_PERIPH_SD2               0x00010006
-
-//PCLKCR7
-#define SYSCTL_PERIPH_SCI1              0x00000007
-#define SYSCTL_PERIPH_SCI2              0x00010007
-#define SYSCTL_PERIPH_SCI3              0x00020007
-#define SYSCTL_PERIPH_SCI4              0x00030007
-
-//PCLKCR8
-#define SYSCTL_PERIPH_SPI1              0x00000008
-#define SYSCTL_PERIPH_SPI2              0x00010008
-#define SYSCTL_PERIPH_SPI3              0x00020008
-
-//PCLKCR9
-#define SYSCTL_PERIPH_I2C1              0x00000009
-#define SYSCTL_PERIPH_I2C2              0x00010009
-
-//PCLKCR10
-#define SYSCTL_PERIPH_CAN1              0x0000000A
-#define SYSCTL_PERIPH_CAN2              0x0001000A
-
-//PCLKCR11
-#define SYSCTL_PERIPH_MCBSP1            0x0000000B
-#define SYSCTL_PERIPH_MCBSP2            0x0001000B
-#define SYSCTL_PERIPH_USB0              0x0010000B
-
-//PCLKCR12
-#define SYSCTL_PERIPH_UPP1              0x0000000C
-
-//PCLKCR13
-#define SYSCTL_PERIPH_ADC1              0x0000000D
-#define SYSCTL_PERIPH_ADC2              0x0001000D
-#define SYSCTL_PERIPH_ADC3              0x0002000D
-#define SYSCTL_PERIPH_ADC4              0x0003000D
-
-//PCLKCR14
-#define SYSCTL_PERIPH_CMPSS1            0x0000000E
-#define SYSCTL_PERIPH_CMPSS2            0x0001000E
-#define SYSCTL_PERIPH_CMPSS3            0x0002000E
-#define SYSCTL_PERIPH_CMPSS4            0x0003000E
-#define SYSCTL_PERIPH_CMPSS5            0x0004000E
-#define SYSCTL_PERIPH_CMPSS6            0x0005000E
-#define SYSCTL_PERIPH_CMPSS7            0x0006000E
-#define SYSCTL_PERIPH_CMPSS8            0x0007000E
-
-//PCLKCR15
-//Reserved
-
-//PCLKCR16
-#define SYSCTL_PERIPH_BUFFDAC1          0x00000010
-#define SYSCTL_PERIPH_BUFFDAC2          0x00010010
-#define SYSCTL_PERIPH_BUFFDAC3          0x00020010
-
-
-//old
-//#define SYSCTL_PERIPH_UART_A     0x1  // SCI A
-//#define SYSCTL_PERIPH_UART_B     0x2  // SCI B
-//#define SYSCTL_PERIPH_UART_C     0x3  // SCI C
-//#define SYSCTL_PERIPH_UART_D     0x4  // SCI D
-//
-//#define SYSCTL_PERIPH_SPI_A      0x5  // SPI A
-//#define SYSCTL_PERIPH_SPI_B      0x6  // SPI B
-//#define SYSCTL_PERIPH_SPI_C      0x7  // SPI C
-//
-//#define SYSCTL_PERIPH_MCBSP_A    0x8  // McBSP A
-//#define SYSCTL_PERIPH_MCBSP_B    0x9  // McBSP B
-//
-//#define SYSCTL_PERIPH_DMA        0xA  // DMA
-//
-//#define SYSCTL_PERIPH_USB0       0xB  // USBA
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-
-extern uint32_t SysCtlSRAMSizeGet(void);
-extern uint32_t SysCtlFlashSizeGet(void);
-extern void SysCtlPeripheralReset(uint32_t ui32Peripheral);
-extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral);
-extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral);
-extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral);
-extern void SysCtlDelay(uint32_t ulCount);
-extern uint32_t SysCtlClockGet(uint32_t u32ClockIn);
-extern void SysCtlClockSet(uint32_t ui32Config);
-extern void SysCtlAuxClockSet(uint32_t ui32Config);
-extern uint32_t SysCtlLowSpeedClockGet(uint32_t u32ClockIn);
-extern void SysCtlUSBPLLEnable(void);
-extern void SysCtlUSBPLLDisable(void);
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//****************************************************************************
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __SYSCTL_H__
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.c
deleted file mode 100644
index 971715de78..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.c
+++ /dev/null
@@ -1,305 +0,0 @@
-//###########################################################################
-//
-// FILE:   systick.c
-//
-// TITLE:  Stellaris style wrapper driver for C28x CPU Timer 0.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-//*****************************************************************************
-//
-//! \addtogroup systick_api
-//! @{
-//
-//*****************************************************************************
-
-#include "F28x_Project.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_types.h"
-#include "driverlib/debug.h"
-#include "driverlib/interrupt.h"
-#include "driverlib/systick.h"
-
-
-//*****************************************************************************
-//
-//! Initializes the Timer0 Module to act as a system tick
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickInit(void)
-{
-    // CPU Timer 0
-    // Initialize timer period to maximum:
-    CpuTimer0Regs.PRD.all  = 0xFFFFFFFF;
-    // Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
-    CpuTimer0Regs.TPR.all  = 0;
-    CpuTimer0Regs.TPRH.all = 0;
-    // Make sure timer is stopped:
-    CpuTimer0Regs.TCR.bit.TSS = 1;
-    // Reload all counter register with period value:
-    CpuTimer0Regs.TCR.bit.TRB = 1;
-}
-
-//*****************************************************************************
-//
-//! Enables the SysTick counter.
-//!
-//! This will start the SysTick counter.  If an interrupt handler has been
-//! registered, it will be called when the SysTick counter rolls over.
-//!
-//! \note Calling this function will cause the SysTick counter to (re)commence
-//! counting from its current value.  The counter is not automatically reloaded
-//! with the period as specified in a previous call to SysTickPeriodSet().  If
-//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
-//! written to force this.  Any write to this register clears the SysTick
-//! counter to 0 and will cause a reload with the supplied period on the next
-//! clock.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickEnable(void)
-{
-    //
-    // Enable SysTick.
-    //
-    CpuTimer0Regs.TCR.bit.TRB = 1;
-    CpuTimer0Regs.TCR.bit.TSS = 0;
-}
-
-//*****************************************************************************
-//
-//! Disables the SysTick counter.
-//!
-//! This will stop the SysTick counter.  If an interrupt handler has been
-//! registered, it will no longer be called until SysTick is restarted.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickDisable(void)
-{
-    //
-    // Disable SysTick.
-    //
-    StopCpuTimer0();
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the SysTick interrupt.
-//!
-//! \param pfnHandler is a pointer to the function to be called when the
-//! SysTick interrupt occurs.
-//!
-//! This sets the handler to be called when a SysTick interrupt occurs.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntRegister(void (*pfnHandler)(void))
-{
-    //
-    // Register the interrupt handler, returning an error if an error occurs.
-    //
-    IntRegister(INT_TINT0, pfnHandler);
-
-    //
-    // Enable the SysTick interrupt.
-    //
-    IntEnable(INT_TINT0);
-}
-
-//*****************************************************************************
-//
-//! Unregisters the interrupt handler for the SysTick interrupt.
-//!
-//! This function will clear the handler to be called when a SysTick interrupt
-//! occurs.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntUnregister(void)
-{
-    //
-    // Disable the SysTick interrupt.
-    //
-    IntDisable(INT_TINT0);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(INT_TINT0);
-}
-
-//*****************************************************************************
-//
-//! Enables the SysTick interrupt.
-//!
-//! This function will enable the SysTick interrupt, allowing it to be
-//! reflected to the processor.
-//!
-//! \note The SysTick interrupt handler does not need to clear the SysTick
-//! interrupt source as this is done automatically by NVIC when the interrupt
-//! handler is called.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntEnable(void)
-{
-    //
-    // Enable the SysTick interrupt.
-    //
-    CpuTimer0Regs.TCR.bit.TIE = 1;
-    IntEnable(INT_TINT0);
-}
-
-//*****************************************************************************
-//
-//! Disables the SysTick interrupt.
-//!
-//! This function will disable the SysTick interrupt, preventing it from being
-//! reflected to the processor.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntDisable(void)
-{
-    //
-    // Disable the SysTick interrupt.
-    //
-    CpuTimer0Regs.TCR.bit.TIE = 0;
-    IntDisable(INT_TINT0);
-}
-
-//*****************************************************************************
-//
-//! Sets the period of the SysTick counter.
-//!
-//! \param ui32Period is the number of clock ticks in each period of the SysTick
-//! counter; must be between 1 and 16,777,216, inclusive.
-//!
-//! This function sets the rate at which the SysTick counter wraps; this
-//! equates to the number of processor clocks between interrupts.
-//!
-//! \note Calling this function does not cause the SysTick counter to reload
-//! immediately.  If an immediate reload is required, the \b NVIC_ST_CURRENT
-//! register must be written.  Any write to this register clears the SysTick
-//! counter to 0 and will cause a reload with the \e ui32Period supplied here on
-//! the next clock after the SysTick is enabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickPeriodSet(uint32_t ui32Period)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ui32Period > 0) && (ui32Period <= 16777216));
-
-    //
-    // Set the period of the SysTick counter.
-    //
-    CpuTimer0Regs.PRD.all = ui32Period;
-}
-
-//*****************************************************************************
-//
-//! Gets the period of the SysTick counter.
-//!
-//! This function returns the rate at which the SysTick counter wraps; this
-//! equates to the number of processor clocks between interrupts.
-//!
-//! \return Returns the period of the SysTick counter.
-//
-//*****************************************************************************
-uint32_t
-SysTickPeriodGet(void)
-{
-    //
-    // Return the period of the SysTick counter.
-    //
-    return(CpuTimer0Regs.PRD.all);
-}
-
-//*****************************************************************************
-//
-//! Gets the current value of the SysTick counter.
-//!
-//! This function returns the current value of the SysTick counter; this will
-//! be a value between the period - 1 and zero, inclusive.
-//!
-//! \return Returns the current value of the SysTick counter.
-//
-//*****************************************************************************
-uint32_t
-SysTickValueGet(void)
-{
-    //
-    // Return the current value of the SysTick counter.
-    //
-    return(CpuTimer0Regs.TIM.all);
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.h
deleted file mode 100644
index e4b6e7bf6f..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.h
+++ /dev/null
@@ -1,84 +0,0 @@
-//###########################################################################
-//
-// FILE:   systick.h
-//
-// TITLE:  Stellaris style wrapper driver for C28x CPU Timer 0.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __SYSTICK_H__
-#define __SYSTICK_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-    extern void SysTickInit(void);
-    extern void SysTickEnable(void);
-    extern void SysTickDisable(void);
-    extern void SysTickIntRegister(void (*pfnHandler)(void));
-    extern void SysTickIntUnregister(void);
-    extern void SysTickIntEnable(void);
-    extern void SysTickIntDisable(void);
-    extern void SysTickPeriodSet(uint32_t ui32Period);
-    extern uint32_t SysTickPeriodGet(void);
-    extern uint32_t SysTickValueGet(void);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __SYSTICK_H__
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.c
deleted file mode 100644
index 29b2454261..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.c
+++ /dev/null
@@ -1,1352 +0,0 @@
-//###########################################################################
-//
-// FILE:   uart.c
-//
-// TITLE:  Stellaris style wrapper driver for C28x SCI peripheral.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-//*****************************************************************************
-//
-//! \addtogroup uart_api
-//! @{
-//
-//*****************************************************************************
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_types.h"
-#include "inc/hw_uart.h"
-#include "driverlib/debug.h"
-#include "driverlib/interrupt.h"
-#include "driverlib/uart.h"
-
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a UART base address.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This function determines if a UART port base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static bool
-UARTBaseValid(uint32_t ui32Base)
-{
-    return((ui32Base == UARTA_BASE) || (ui32Base == UARTB_BASE) ||
-           (ui32Base == UARTC_BASE) || (ui32Base == UARTD_BASE));
-}
-#endif
-
-//*****************************************************************************
-//
-//! Sets the type of parity.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ui32Parity specifies the type of parity to use.
-//!
-//! Sets the type of parity to use for transmitting and expect when receiving.
-//! The \e ui32Parity parameter must be one of \b UART_CONFIG_PAR_NONE,
-//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
-//! or \b UART_CONFIG_PAR_ZERO.  The last two allow direct control of the
-//! parity bit; it is always either one or zero based on the mode.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-    ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) ||
-           (ui32Parity == UART_CONFIG_PAR_EVEN) ||
-           (ui32Parity == UART_CONFIG_PAR_ODD) ||
-           (ui32Parity == UART_CONFIG_PAR_ONE) ||
-           (ui32Parity == UART_CONFIG_PAR_ZERO));
-
-    //
-    // Set the parity mode.
-    //
-    HWREGB(ui32Base + UART_O_CCR) = ((HWREGB(ui32Base + UART_O_CCR) &
-                                   ~(UART_CONFIG_PAR_MASK)) | ui32Parity);
-}
-
-//*****************************************************************************
-//
-//! Gets the type of parity currently being used.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This function gets the type of parity used for transmitting data and
-//! expected when receiving data.
-//!
-//! \return Returns the current parity settings, specified as one of
-//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
-//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
-//
-//*****************************************************************************
-uint32_t
-UARTParityModeGet(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Return the current parity setting.
-    //
-    return(HWREGB(ui32Base + UART_O_CCR) &
-           (UART_CONFIG_PAR_MASK));
-}
-
-//*****************************************************************************
-//
-//! Sets the FIFO level at which interrupts are generated.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of
-//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
-//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
-//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of
-//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
-//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
-//!
-//! This function sets the FIFO level at which transmit and receive interrupts
-//! are generated.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFOIntLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel,
-                 uint32_t ui32RxLevel)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-    ASSERT((ui32TxLevel == UART_FIFO_TX1_8) ||
-           (ui32TxLevel == UART_FIFO_TX2_8) ||
-           (ui32TxLevel == UART_FIFO_TX4_8) ||
-           (ui32TxLevel == UART_FIFO_TX6_8));
-    ASSERT((ui32RxLevel == UART_FIFO_RX1_8) ||
-           (ui32RxLevel == UART_FIFO_RX2_8) ||
-           (ui32RxLevel == UART_FIFO_RX4_8) ||
-           (ui32RxLevel == UART_FIFO_RX6_8));
-
-    //
-    // Set the FIFO interrupt levels.
-    //
-    HWREGH(ui32Base + UART_O_FFTX) = (HWREGH(ui32Base + UART_O_FFTX)& (~UART_FFTX_TXFFIL_M)) | ui32TxLevel ;
-    HWREGH(ui32Base + UART_O_FFRX) = (HWREGH(ui32Base + UART_O_FFRX)& (~UART_FFRX_RXFFIL_M)) | ui32RxLevel ;
-}
-
-//*****************************************************************************
-//
-//! Gets the FIFO level at which interrupts are generated.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level,
-//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
-//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
-//! \param pui32RxLevel is a pointer to storage for the receive FIFO level,
-//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
-//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
-//!
-//! This function gets the FIFO level at which transmit and receive interrupts
-//! are generated.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFOIntLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
-                 uint32_t *pui32RxLevel)
-{
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Extract the transmit and receive FIFO levels.
-    //
-    *pui32TxLevel = HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_TXFFIL_M;
-    *pui32RxLevel = HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFIL_M;
-}
-
-//*****************************************************************************
-//
-//! Gets the FIFO level at which interrupts are generated.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level,
-//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
-//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
-//! \param pui32RxLevel is a pointer to storage for the receive FIFO level,
-//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
-//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
-//!
-//! This function gets the FIFO level at which transmit and receive interrupts
-//! are generated.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
-                 uint32_t *pui32RxLevel)
-{
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Extract the transmit and receive FIFO levels.
-    //
-    *pui32TxLevel = (HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_TXFFST_M) >> UART_FFTX_TXFFST_S;
-    *pui32RxLevel = (HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S;
-}
-
-//*****************************************************************************
-//
-//! Sets the configuration of a UART.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ui32UARTClk is the rate of the clock supplied to the UART module.
-//! \param ui32Baud is the desired baud rate.
-//! \param ui32Config is the data format for the port (number of data bits,
-//! number of stop bits, and parity).
-//!
-//! This function configures the UART for operation in the specified data
-//! format.  The baud rate is provided in the \e ui32Baud parameter and the data
-//! format in the \e ui32Config parameter.
-//!
-//! The \e ui32Config parameter is the logical OR of three values: the number of
-//! data bits, the number of stop bits, and the parity.  \b UART_CONFIG_WLEN_8,
-//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
-//! select from eight to five data bits per byte (respectively).
-//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
-//! bits (respectively).  \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
-//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
-//! select the parity mode (no parity bit, even parity bit, odd parity bit,
-//! parity bit always one, and parity bit always zero, respectively).
-//!
-//! The peripheral clock will be the same as the processor clock.  This will be
-//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
-//! if it is constant and known (to save the code/execution overhead of a call
-//! to SysCtlClockGet()).
-//!
-//! This function replaces the original UARTConfigSet() API and performs the
-//! same actions.  A macro is provided in <tt>uart.h</tt> to map the original
-//! API to this API.
-//!
-//! \return None.
-//
-//*****************************************************************************
-//Changed for C28x
-void
-UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
-                    uint32_t ui32Baud, uint32_t ui32Config)
-{
-    uint32_t ui32Div;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-    ASSERT(ui32Baud != 0);
-//    ASSERT(ui32UARTClk >= (ui32Baud * UART_CLK_DIVIDER));
-
-    //
-    // Stop the UART.
-    //
-    UARTDisable(ui32Base);
-
-    //
-    // Is the required baud rate greater than the maximum rate supported?
-    //
-    if((ui32Baud * 16) > ui32UARTClk)
-    {
-        //
-        // Baud Rate Not supported with current clock
-        //
-        return;
-    }
-
-    //
-    // Compute the baud rate divider.
-    //
-    ui32Div = ((ui32UARTClk  / (ui32Baud * 8)) - 1);
-
-    //
-    // Set the baud rate.
-    //
-    HWREGB(ui32Base + UART_O_HBAUD) = (ui32Div & 0xFF00) >> 8;
-    HWREGB(ui32Base + UART_O_LBAUD) = ui32Div & 0x00FF;
-
-    //
-    // Set parity, data length, and number of stop bits.
-    //
-    HWREGB(ui32Base + UART_O_CCR) = ((HWREGB(ui32Base + UART_O_CCR) &
-                                   ~(UART_CONFIG_PAR_MASK | UART_CONFIG_STOP_MASK | UART_CONFIG_WLEN_MASK))
-                                  | ui32Config);
-
-
-    //
-    // Start the UART.
-    //
-    UARTEnable(ui32Base);
-}
-
-//*****************************************************************************
-//
-//! Gets the current configuration of a UART.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ui32UARTClk is the rate of the clock supplied to the UART module.
-//! \param pui32Baud is a pointer to storage for the baud rate.
-//! \param pui32Config is a pointer to storage for the data format.
-//!
-//! The baud rate and data format for the UART is determined, given an
-//! explicitly provided peripheral clock (hence the ExpClk suffix).  The
-//! returned baud rate is the actual baud rate; it may not be the exact baud
-//! rate requested or an ``official'' baud rate.  The data format returned in
-//! \e pui32Config is enumerated the same as the \e ui32Config parameter of
-//! UARTConfigSetExpClk().
-//!
-//! The peripheral clock will be the same as the processor clock.  This will be
-//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
-//! if it is constant and known (to save the code/execution overhead of a call
-//! to SysCtlClockGet()).
-//!
-//! This function replaces the original UARTConfigGet() API and performs the
-//! same actions.  A macro is provided in <tt>uart.h</tt> to map the original
-//! API to this API.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
-                    uint32_t *pui32Baud, uint32_t *pui32Config)
-{
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Compute the baud rate.
-    //
-    *pui32Baud = ui32UARTClk / ((1 + (HWREGB(ui32Base + UART_O_HBAUD) << 8 ) | HWREGB(ui32Base + UART_O_LBAUD)) * 8);
-
-    //
-    // Get the parity, data length, and number of stop bits.
-    //
-    *pui32Config = HWREGB(ui32Base + UART_O_CCR) &
-                 (UART_CONFIG_PAR_MASK | UART_CONFIG_STOP_MASK | UART_CONFIG_WLEN_MASK);
-}
-
-//*****************************************************************************
-//
-//! Enables transmitting and receiving.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
-//! FIFOs.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTEnable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Enable RX, TX, and the UART.
-    //
-    HWREGB(ui32Base + UART_O_CTL1) |= (UART_CTL1_TXENA | UART_CTL1_RXENA | UART_CTL1_SWRESET);
-}
-
-//*****************************************************************************
-//
-//! Disables transmitting and receiving.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
-//! transmission of the current character, and flushes the transmit FIFO.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTDisable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Wait for end of TX.
-    //
-    while(!(HWREGH(ui32Base + UART_O_CTL2) & UART_CTL2_TXEMPTY))
-    {
-    }
-
-    //
-    // Disable the FIFO.
-    //
-    HWREGH(ui32Base + UART_O_FFTX) &= ~(UART_FFTX_SCIFFENA);
-
-    //
-    // Disable the UART.
-    //
-    HWREGB(ui32Base + UART_O_CTL1) &= ~(UART_CTL1_TXENA | UART_CTL1_RXENA);
-}
-
-//*****************************************************************************
-//
-//! Enables Loop Back Test Mode.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! Sets the SCICCR.LOOPBKENA to enable
-//!
-//! \return None.
-//
-//*****************************************************************************
-void UARTsetLoopBack(uint32_t ui32Base, bool enable)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    if(enable)
-    {
-		//
-		// Enable LoopBack.
-		//
-
-    	HWREGB(ui32Base + UART_O_CCR) |= UART_CCR_LOOPBKENA;
-    }
-    else
-    {
-		//
-		// Disable LoopBack.
-		//
-    	HWREGB(ui32Base + UART_O_CCR) &= ~UART_CCR_LOOPBKENA;
-    }
-}
-
-//*****************************************************************************
-//
-//! Enables the transmit and receive FIFOs.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This functions enables the transmit and receive FIFOs in the UART.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFOEnable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Enable the FIFO.
-    //
-    HWREGH(ui32Base + UART_O_FFTX) |= UART_FFTX_SCIFFENA;
-}
-
-//*****************************************************************************
-//
-//! Disables the transmit and receive FIFOs.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This functions disables the transmit and receive FIFOs in the UART.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFODisable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Disable the FIFO.
-    //
-    HWREGH(ui32Base + UART_O_FFTX) &= ~UART_FFTX_SCIFFENA;
-}
-
-//*****************************************************************************
-//
-//! Sets the operating mode for the UART transmit interrupt.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ui32Mode is the operating mode for the transmit interrupt.  It may be
-//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle
-//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO
-//! level.
-//!
-//! This function allows the mode of the UART transmit interrupt to be set.  By
-//! default, the transmit interrupt is asserted when the FIFO level falls past
-//! a threshold set via a call to UARTFIFOLevelSet().  Alternatively, if this
-//! function is called with \e ui32Mode set to \b UART_TXINT_MODE_EOT, the
-//! transmit interrupt will only be asserted once the transmitter is completely
-//! idle - the transmit FIFO is empty and all bits, including any stop bits,
-//! have cleared the transmitter.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-    ASSERT((ui32Mode == UART_TXINT_MODE_EOT) ||
-           (ui32Mode == UART_TXINT_MODE_FIFO_M));
-
-    //
-    // Set or clear the EOT bit of the UART control register as appropriate.
-    //
-    HWREGH(ui32Base + UART_O_FFTX) = ((HWREG(ui32Base + UART_O_FFTX) & ~(UART_TXINT_MODE_FIFO_M)) | ui32Mode);
-}
-
-//*****************************************************************************
-//
-//! Returns the current operating mode for the UART transmit interrupt.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This function returns the current operating mode for the UART transmit
-//! interrupt.  The return value will be \b UART_TXINT_MODE_EOT if the
-//! transmit interrupt is currently set to be asserted once the transmitter is
-//! completely idle - the transmit FIFO is empty and all bits, including any
-//! stop bits, have cleared the transmitter.  The return value will be \b
-//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the
-//! level of the transmit FIFO.
-//!
-//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
-//
-//*****************************************************************************
-uint32_t
-UARTTxIntModeGet(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Return the current transmit interrupt mode.
-    //
-    return(HWREGH(ui32Base + UART_O_FFTX) & UART_TXINT_MODE_FIFO_M);
-}
-
-//*****************************************************************************
-//
-//! Determines if there are any characters in the receive FIFO.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This function returns a flag indicating whether or not there is data
-//! available in the receive FIFO.
-//!
-//! \return Returns \b true if there is data in the receive FIFO or \b false
-//! if there is no data in the receive FIFO.
-//
-//*****************************************************************************
-bool
-UARTCharsAvail(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Return the availability of characters.
-    //
-    if(HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_SCIFFENA)
-    {
-		return(((HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S) ? true : false);
-
-    }
-    else
-    {
-    	return((HWREGB(ui32Base + UART_O_RXST) & UART_RXST_RXRDY) ? true : false);
-    }
-}
-
-//*****************************************************************************
-//
-//! Determines if there is any space in the transmit FIFO.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This function returns a flag indicating whether or not there is space
-//! available in the transmit FIFO.
-//!
-//! \return Returns \b true if there is space available in the transmit FIFO
-//! or \b false if there is no space available in the transmit FIFO.
-//
-//*****************************************************************************
-bool
-UARTSpaceAvail(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Return the availability of space.
-    //
-    return((HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY) ? true : false);
-
-}
-
-//*****************************************************************************
-//
-//! Receives a character from the specified port.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! Gets a character from the receive FIFO for the specified port.
-//!
-//! This function replaces the original UARTCharNonBlockingGet() API and
-//! performs the same actions.  A macro is provided in <tt>uart.h</tt> to map
-//! the original API to this API.
-//!
-//! \return Returns the character read from the specified port, cast as a
-//! \e long.  A \b -1 is returned if there are no characters present in the
-//! receive FIFO.  The UARTCharsAvail() function should be called before
-//! attempting to call this function.
-//
-//*****************************************************************************
-int32_t
-UARTCharGetNonBlocking(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // See if there are any characters in the receive FIFO.
-    //
-    if(HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_SCIFFENA)
-    {
-		if((HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S)
-		{
-			//
-			// Read and return the next character.
-			//
-			return(HWREGH(ui32Base + UART_O_RXBUF) & UART_RXBUF_SAR_M);
-		}
-		else
-		{
-			//
-			// There are no characters, so return a failure.
-			//
-			return(-1);
-		}
-    }
-    else
-    {
-    	if((HWREGB(ui32Base + UART_O_RXST) & UART_RXST_RXRDY))
-    	{
-            //
-            // Read and return the next character.
-            //
-            return(HWREGH(ui32Base + UART_O_RXBUF) & UART_RXBUF_SAR_M);
-    	}
-        else
-        {
-            //
-            // There are no characters, so return a failure.
-            //
-            return(-1);
-        }
-    }
-}
-
-//*****************************************************************************
-//
-//! Waits for a character from the specified port.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! Gets a character from the receive FIFO for the specified port.  If there
-//! are no characters available, this function waits until a character is
-//! received before returning.
-//!
-//! \return Returns the character read from the specified port, cast as a
-//! \e long.
-//
-//*****************************************************************************
-int32_t
-UARTCharGet(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Wait until a char is available.
-    //
-
-    if(HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_SCIFFENA)
-    {
-		while(!((HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S))
-		{
-		}
-    }
-    else
-    {
-    	while(!(HWREGH(ui32Base + UART_O_RXST) & UART_RXST_RXRDY))
-    	{
-
-    	}
-    }
-    //
-    // Now get the char.
-    //
-    return(HWREGH(ui32Base + UART_O_RXBUF) & UART_RXBUF_SAR_M);
-}
-
-//*****************************************************************************
-//
-//! Sends a character to the specified port.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ucData is the character to be transmitted.
-//!
-//! Writes the character \e ucData to the transmit FIFO for the specified port.
-//! This function does not block, so if there is no space available, then a
-//! \b false is returned, and the application must retry the function later.
-//!
-//! This function replaces the original UARTCharNonBlockingPut() API and
-//! performs the same actions.  A macro is provided in <tt>uart.h</tt> to map
-//! the original API to this API.
-//!
-//! \return Returns \b true if the character was successfully placed in the
-//! transmit FIFO or \b false if there was no space available in the transmit
-//! FIFO.
-//
-//*****************************************************************************
-bool
-UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // See if there is space in the transmit FIFO.
-    //
-    if(HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY)
-    {
-        //
-        // Write this character to the transmit FIFO.
-        //
-        HWREGB(ui32Base + UART_O_TXBUF) = ucData;
-
-        //
-        // Success.
-        //
-        return(true);
-    }
-    else
-    {
-        //
-        // There is no space in the transmit FIFO, so return a failure.
-        //
-        return(false);
-    }
-}
-
-//*****************************************************************************
-//
-//! Waits to send a character from the specified port.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ucData is the character to be transmitted.
-//!
-//! Sends the character \e ucData to the transmit FIFO for the specified port.
-//! If there is no space available in the transmit FIFO, this function waits
-//! until there is space available before returning.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTCharPut(uint32_t ui32Base, unsigned char ucData)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Wait until space is available.
-    //
-    while(!(HWREGH(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY))
-    {
-    }
-
-    //
-    // Send the char.
-    //
-    HWREGB(ui32Base + UART_O_TXBUF) = ucData;
-}
-
-//*****************************************************************************
-//
-//! Determines whether the UART transmitter is busy or not.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! Allows the caller to determine whether all transmitted bytes have cleared
-//! the transmitter hardware.  If \b false is returned, the transmit FIFO is
-//! empty and all bits of the last transmitted character, including all stop
-//! bits, have left the hardware shift register.
-//!
-//! \return Returns \b true if the UART is transmitting or \b false if all
-//! transmissions are complete.
-//
-//*****************************************************************************
-bool
-UARTBusy(uint32_t ui32Base)
-{
-    //
-    // Check the argument.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Determine if the UART is busy.
-    //
-    return((HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXEMPTY) ? false : true);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for a UART RX interrupt.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! UART interrupt occurs.
-//!
-//! This function does the actual registering of the interrupt handler.  This
-//! will enable the global interrupt in the interrupt controller; specific UART
-//! interrupts must be enabled via UARTIntEnable().  It is the interrupt
-//! handler's responsibility to clear the interrupt source.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTRXIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
-{
-    uint32_t ui32Int;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Determine the interrupt number based on the UART port.
-    //
-    ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCIRXINTA : INT_SCIRXINTB );
-
-    //
-    // Register the interrupt handler.
-    //
-    IntRegister(ui32Int, pfnHandler);
-
-    //
-    // Enable the UART interrupt.
-    //
-    IntEnable(ui32Int);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for a UART TX interrupt.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! UART interrupt occurs.
-//!
-//! This function does the actual registering of the interrupt handler.  This
-//! will enable the global interrupt in the interrupt controller; specific UART
-//! interrupts must be enabled via UARTIntEnable().  It is the interrupt
-//! handler's responsibility to clear the interrupt source.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTTXIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
-{
-    uint32_t ui32Int;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Determine the interrupt number based on the UART port.
-    //
-    ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCITXINTA : INT_SCITXINTB );
-
-    //
-    // Register the interrupt handler.
-    //
-    IntRegister(ui32Int, pfnHandler);
-
-    //
-    // Enable the UART interrupt.
-    //
-    IntEnable(ui32Int);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for a UART RX interrupt.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This function does the actual unregistering of the interrupt handler.  It
-//! will clear the handler to be called when a UART interrupt occurs.  This
-//! will also mask off the interrupt in the interrupt controller so that the
-//! interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTRXIntUnregister(uint32_t ui32Base)
-{
-    uint32_t ui32Int;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Determine the interrupt number based on the UART port.
-    //
-    ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCIRXINTA : INT_SCIRXINTB );
-
-    //
-    // Disable the interrupt.
-    //
-    IntDisable(ui32Int);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(ui32Int);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for a UART TX interrupt.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This function does the actual unregistering of the interrupt handler.  It
-//! will clear the handler to be called when a UART interrupt occurs.  This
-//! will also mask off the interrupt in the interrupt controller so that the
-//! interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTTXIntUnregister(uint32_t ui32Base)
-{
-    uint32_t ui32Int;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Determine the interrupt number based on the UART port.
-    //
-    ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCITXINTA : INT_SCITXINTB );
-
-    //
-    // Disable the interrupt.
-    //
-    IntDisable(ui32Int);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(ui32Int);
-}
-
-//*****************************************************************************
-//
-//! Enables individual UART interrupt sources.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! Enables the indicated UART interrupt sources.  Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
-//!
-//! The \e ui32IntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b UART_INT_OE - Overrun Error interrupt
-//! - \b UART_INT_BE - Break Error interrupt
-//! - \b UART_INT_PE - Parity Error interrupt
-//! - \b UART_INT_FE - Framing Error interrupt
-//! - \b UART_INT_RT - Receive Timeout interrupt
-//! - \b UART_INT_TX - Transmit interrupt
-//! - \b UART_INT_RX - Receive interrupt
-//! - \b UART_INT_DSR - DSR interrupt
-//! - \b UART_INT_DCD - DCD interrupt
-//! - \b UART_INT_CTS - CTS interrupt
-//! - \b UART_INT_RI - RI interrupt
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Enable the specified interrupts.
-    //
-    if(ui32IntFlags & UART_INT_RXERR)
-        HWREGB(ui32Base + UART_O_CTL1) |= UART_CTL1_RXERRINTENA;
-
-    if(ui32IntFlags & UART_INT_RXRDY_BRKDT)
-        HWREGB(ui32Base + UART_O_CTL2) |= UART_CTL2_RXBKINTENA;
-
-    if(ui32IntFlags & UART_INT_TXRDY)
-        HWREGB(ui32Base + UART_O_CTL2) |= UART_CTL2_TXINTENA;
-
-    if(ui32IntFlags & UART_INT_TXFF)
-        HWREGB(ui32Base + UART_O_FFTX) |= UART_FFTX_TXFFIENA;
-
-    if(ui32IntFlags & UART_INT_RXFF)
-        HWREGB(ui32Base + UART_O_FFRX) |= UART_FFRX_RXFFIENA;
-
-
-}
-
-//*****************************************************************************
-//
-//! Disables individual UART interrupt sources.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
-//!
-//! Disables the indicated UART interrupt sources.  Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
-//!
-//! The \e ui32IntFlags parameter has the same definition as the \e ui32IntFlags
-//! parameter to UARTIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Disable the specified interrupts.
-    //
-    if(ui32IntFlags & UART_INT_RXERR)
-        HWREGB(ui32Base + UART_O_CTL1) &= ~UART_CTL1_RXERRINTENA;
-
-    if(ui32IntFlags & UART_INT_RXRDY_BRKDT)
-        HWREGB(ui32Base + UART_O_CTL2) &= ~UART_CTL2_RXBKINTENA;
-
-    if(ui32IntFlags & UART_INT_TXRDY)
-        HWREGB(ui32Base + UART_O_CTL2) &= ~UART_CTL2_TXINTENA;
-
-    if(ui32IntFlags & UART_INT_TXFF)
-        HWREGB(ui32Base + UART_O_FFTX) &= ~UART_FFTX_TXFFIENA;
-
-    if(ui32IntFlags & UART_INT_RXFF)
-        HWREGB(ui32Base + UART_O_FFRX) &= ~UART_FFRX_RXFFIENA;
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param bMasked is \b false if the raw interrupt status is required and
-//! \b true if the masked interrupt status is required.
-//!
-//! This returns the interrupt status for the specified UART.  Either the raw
-//! interrupt status or the status of interrupts that are allowed to reflect to
-//! the processor can be returned.
-//!
-//! \return Returns the current interrupt status, enumerated as a bit field of
-//! values described in UARTIntEnable().
-//
-//*****************************************************************************
-uint32_t
-UARTIntStatus(uint32_t ui32Base, bool bMasked)
-{
-
-    uint32_t temp = 0;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Return either the interrupt status or the raw interrupt status as
-    // requested.
-    //
-
-
-    if(HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY)
-        temp |= UART_INT_TXRDY;
-
-    if(HWREGB(ui32Base + UART_O_RXST) & UART_RXST_RXERROR)
-        temp |= UART_INT_RXERR;
-
-    if(HWREGB(ui32Base + UART_O_RXST) & (UART_RXST_RXRDY | UART_RXST_BRKDT))
-        temp |= UART_INT_RXRDY_BRKDT;
-
-    if(HWREGB(ui32Base + UART_O_FFTX) & UART_FFTX_TXFFINT)
-        temp |= UART_INT_TXFF;
-
-    if(HWREGB(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFINT)
-        temp |= UART_INT_RXFF;
-
-    return temp;
-}
-
-//*****************************************************************************
-//
-//! Clears UART interrupt sources.
-//!
-//! \param ui32Base is the base address of the UART port.
-//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified UART interrupt sources are cleared, so that they no longer
-//! assert.  This function must be called in the interrupt handler to keep the
-//! interrupt from being recognized again immediately upon exit.
-//!
-//! The \e ui32IntFlags parameter has the same definition as the \e ui32IntFlags
-//! parameter to UARTIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Clear the requested interrupt sources.
-    //
-    if(ui32IntFlags & (UART_INT_RXERR | UART_INT_RXRDY_BRKDT))
-    {
-        HWREGB(ui32Base + UART_O_CTL1) &= ~UART_CTL1_SWRESET;
-       __asm(" nop");
-       __asm(" nop");
-       __asm(" nop");
-       __asm(" nop");
-        HWREGB(ui32Base + UART_O_CTL1) |= UART_CTL1_SWRESET;
-    }
-
-    if(ui32IntFlags & UART_INT_TXFF)
-        HWREGB(ui32Base + UART_O_FFTX) |= UART_FFTX_TXFFINTCLR;
-
-    if(ui32IntFlags & UART_INT_RXFF)
-        HWREGB(ui32Base + UART_O_FFRX) |= UART_FFRX_RXFFINTCLR;
-
-}
-
-//*****************************************************************************
-//
-//! Gets current receiver errors.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This function returns the current state of each of the 4 receiver error
-//! sources.  The returned errors are equivalent to the four error bits
-//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
-//! with the exception that the overrun error is set immediately the overrun
-//! occurs rather than when a character is next read.
-//!
-//! \return Returns a logical OR combination of the receiver error flags,
-//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
-//! and \b UART_RXERROR_OVERRUN.
-//
-//*****************************************************************************
-uint32_t
-UARTRxErrorGet(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // Return the current value of the receive status register.
-    //
-    return(HWREGH(ui32Base + UART_O_RXST));
-}
-
-//*****************************************************************************
-//
-//! Clears all reported receiver errors.
-//!
-//! \param ui32Base is the base address of the UART port.
-//!
-//! This function is used to clear all receiver error conditions reported via
-//! UARTRxErrorGet().  If using the overrun, framing error, parity error or
-//! break interrupts, this function must be called after clearing the interrupt
-//! to ensure that later errors of the same type trigger another interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTRxErrorClear(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ui32Base));
-
-    //
-    // To clear all errors a sw reset of the module is required
-    //
-    HWREGB(ui32Base + UART_O_CTL1) &= ~UART_CTL1_SWRESET;
-   __asm(" nop");
-   __asm(" nop");
-   __asm(" nop");
-   __asm(" nop");
-    HWREGB(ui32Base + UART_O_CTL1) |= UART_CTL1_SWRESET;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.h
deleted file mode 100644
index ed13d30ec2..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.h
+++ /dev/null
@@ -1,214 +0,0 @@
-//###########################################################################
-//
-// FILE:   uart.h
-//
-// TITLE:  Stellaris style wrapper driver for C28x SCI peripheral.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __UART_H__
-#define __UART_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
-// as the ui32IntFlags parameter, and returned from UARTIntStatus.
-//
-//*****************************************************************************
-#define UART_INT_RXERR          0x01
-#define UART_INT_RXRDY_BRKDT    0x02
-#define UART_INT_TXRDY          0x04
-#define UART_INT_TXFF           0x08
-#define UART_INT_RXFF           0x10
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter
-// and returned by UARTConfigGetExpClk in the pui32Config parameter.
-// Additionally, the UART_CONFIG_PAR_* subset can be passed to
-// UARTParityModeSet as the ui32Parity parameter, and are returned by
-// UARTParityModeGet.
-//
-//*****************************************************************************
-#define UART_CONFIG_WLEN_MASK   0x00000007  // Mask for extracting word length
-#define UART_CONFIG_WLEN_8      0x00000007  // 8 bit data
-#define UART_CONFIG_WLEN_7      0x00000006  // 7 bit data
-#define UART_CONFIG_WLEN_6      0x00000005  // 6 bit data
-#define UART_CONFIG_WLEN_5      0x00000004  // 5 bit data
-#define UART_CONFIG_STOP_MASK   0x00000080  // Mask for extracting stop bits
-#define UART_CONFIG_STOP_ONE    0x00000000  // One stop bit
-#define UART_CONFIG_STOP_TWO    0x00000080  // Two stop bits
-#define UART_CONFIG_PAR_MASK    0x00000060  // Parity Mask
-#define UART_CONFIG_PAR_NONE    0x00000000  // No parity
-#define UART_CONFIG_PAR_EVEN    0x00000060  // Even parity
-#define UART_CONFIG_PAR_ODD     0x00000020  // Odd parity
-#define UART_CONFIG_PAR_ONE     0x00000020  // Parity bit is one
-#define UART_CONFIG_PAR_ZERO    0x00000060  // Parity bit is zero
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter and
-// returned by UARTFIFOLevelGet in the pui32TxLevel.
-//
-//*****************************************************************************
-#define UART_FIFO_TX1_8         0x00000001  // Transmit interrupt at 1/4 Full
-#define UART_FIFO_TX2_8         0x00000002  // Transmit interrupt at 1/2 Full
-#define UART_FIFO_TX4_8         0x00000003  // Transmit interrupt at 3/4 Full
-#define UART_FIFO_TX6_8         0x00000004  // Transmit interrupt Full
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter and
-// returned by UARTFIFOLevelGet in the pui32RxLevel.
-//
-//*****************************************************************************
-#define UART_FIFO_RX1_8         0x00000001  // Receive interrupt at 1/4 Full
-#define UART_FIFO_RX2_8         0x00000002  // Receive interrupt at 1/2 Full
-#define UART_FIFO_RX4_8         0x00000003  // Receive interrupt at 3/4 Full
-#define UART_FIFO_RX6_8         0x00000004  // Receive interrupt at Full
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
-//
-//*****************************************************************************
-#define UART_DMA_ERR_RXSTOP     0x00000004  // Stop DMA receive if UART error
-#define UART_DMA_TX             0x00000002  // Enable DMA for transmit
-#define UART_DMA_RX             0x00000001  // Enable DMA for receive
-
-//*****************************************************************************
-//
-// Values returned from UARTRxErrorGet().
-//
-//*****************************************************************************
-#define UART_RXERROR_OVERRUN    0x00000008
-#define UART_RXERROR_BREAK      0x00000020
-#define UART_RXERROR_PARITY     0x00000004
-#define UART_RXERROR_FRAMING    0x00000010
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTHandshakeOutputsSet() or returned from
-// UARTHandshakeOutputGet().
-//
-//*****************************************************************************
-#define UART_OUTPUT_RTS         0x00000800
-#define UART_OUTPUT_DTR         0x00000400
-
-//*****************************************************************************
-//
-// Values that can be returned from UARTHandshakeInputsGet().
-//
-//*****************************************************************************
-#define UART_INPUT_RI           0x00000100
-#define UART_INPUT_DCD          0x00000004
-#define UART_INPUT_DSR          0x00000002
-#define UART_INPUT_CTS          0x00000001
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTTxIntModeSet() or returned from
-// UARTTxIntModeGet().
-//
-//*****************************************************************************
-#define UART_TXINT_MODE_FIFO_M  0x0000001F
-#define UART_TXINT_MODE_EOT     0x00000000
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity);
-extern uint32_t UARTParityModeGet(uint32_t ui32Base);
-extern void UARTFIFOIntLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel,
-                             uint32_t ui32RxLevel);
-extern void UARTFIFOIntLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
-                             uint32_t *pui32RxLevel);
-extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
-                             uint32_t *pui32RxLevel);
-extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
-                                uint32_t ui32Baud, uint32_t ui32Config);
-extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
-                                uint32_t *pui32Baud, uint32_t *pui32Config);
-extern void UARTEnable(uint32_t ui32Base);
-extern void UARTDisable(uint32_t ui32Base);
-extern void UARTsetLoopBack(uint32_t ui32Base, bool enable);
-extern void UARTFIFOEnable(uint32_t ui32Base);
-extern void UARTFIFODisable(uint32_t ui32Base);
-extern bool UARTCharsAvail(uint32_t ui32Base);
-extern bool UARTSpaceAvail(uint32_t ui32Base);
-extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base);
-extern int32_t UARTCharGet(uint32_t ui32Base);
-extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData);
-extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData);
-extern bool UARTBusy(uint32_t ui32Base);
-extern void UARTRXIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
-extern void UARTTXIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
-extern void UARTRXIntUnregister(uint32_t ui32Base);
-extern void UARTTXIntUnregister(uint32_t ui32Base);
-extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked);
-extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern uint32_t UARTRxErrorGet(uint32_t ui32Base);
-extern void UARTRxErrorClear(uint32_t ui32Base);
-extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode);
-extern uint32_t UARTTxIntModeGet(uint32_t ui32Base);
-
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif //  __UART_H__
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_adc.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_adc.h
deleted file mode 100644
index b3a09713c6..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_adc.h
+++ /dev/null
@@ -1,1227 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_adc.h
-//
-// TITLE:   Definitions for the C28x ADC registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_ADC_H__
-#define __HW_ADC_H__
-
-//*****************************************************************************
-//
-// The following are defines for the ADC register offsets
-//
-//*****************************************************************************
-#define ADC_O_CTL1                0x0         // ADC Control 1 Register
-#define ADC_O_CTL2                0x1         // ADC Control 2 Register
-#define ADC_O_BURSTCTL            0x2         // ADC Burst Control Register
-#define ADC_O_INTFLG              0x3         // ADC Interrupt Flag Register
-#define ADC_O_INTFLGCLR           0x4         // ADC Interrupt Flag Clear
-                                              // Register
-#define ADC_O_INTOVF              0x5         // ADC Interrupt Overflow Register
-#define ADC_O_INTOVFCLR           0x6         // ADC Interrupt Overflow Clear
-                                              // Register
-#define ADC_O_INTSEL1N2           0x7         // ADC Interrupt 1 and 2 Selection
-                                              // Register
-#define ADC_O_INTSEL3N4           0x8         // ADC Interrupt 3 and 4 Selection
-                                              // Register
-#define ADC_O_SOCPRICTL           0x9         // ADC SOC Priority Control
-                                              // Register
-#define ADC_O_INTSOCSEL1          0xA         // ADC Interrupt SOC Selection 1
-                                              // Register
-#define ADC_O_INTSOCSEL2          0xB         // ADC Interrupt SOC Selection 2
-                                              // Register
-#define ADC_O_SOCFLG1             0xC         // ADC SOC Flag 1 Register
-#define ADC_O_SOCFRC1             0xD         // ADC SOC Force 1 Register
-#define ADC_O_SOCOVF1             0xE         // ADC SOC Overflow 1 Register
-#define ADC_O_SOCOVFCLR1          0xF         // ADC SOC Overflow Clear 1
-                                              // Register
-#define ADC_O_SOC0CTL             0x10        // ADC SOC0 Control Register
-#define ADC_O_SOC1CTL             0x12        // ADC SOC1 Control Register
-#define ADC_O_SOC2CTL             0x14        // ADC SOC2 Control Register
-#define ADC_O_SOC3CTL             0x16        // ADC SOC3 Control Register
-#define ADC_O_SOC4CTL             0x18        // ADC SOC4 Control Register
-#define ADC_O_SOC5CTL             0x1A        // ADC SOC5 Control Register
-#define ADC_O_SOC6CTL             0x1C        // ADC SOC6 Control Register
-#define ADC_O_SOC7CTL             0x1E        // ADC SOC7 Control Register
-#define ADC_O_SOC8CTL             0x20        // ADC SOC8 Control Register
-#define ADC_O_SOC9CTL             0x22        // ADC SOC9 Control Register
-#define ADC_O_SOC10CTL            0x24        // ADC SOC10 Control Register
-#define ADC_O_SOC11CTL            0x26        // ADC SOC11 Control Register
-#define ADC_O_SOC12CTL            0x28        // ADC SOC12 Control Register
-#define ADC_O_SOC13CTL            0x2A        // ADC SOC13 Control Register
-#define ADC_O_SOC14CTL            0x2C        // ADC SOC14 Control Register
-#define ADC_O_SOC15CTL            0x2E        // ADC SOC15 Control Register
-#define ADC_O_EVTSTAT             0x30        // ADC Event Status Register
-#define ADC_O_EVTCLR              0x32        // ADC Event Clear Register
-#define ADC_O_EVTSEL              0x34        // ADC Event Selection Register
-#define ADC_O_EVTINTSEL           0x36        // ADC Event Interrupt Selection
-                                              // Register
-#define ADC_O_COUNTER             0x39        // ADC Counter Register
-#define ADC_O_REV                 0x3A        // ADC Revision Register
-#define ADC_O_OFFTRIM             0x3B        // ADC Offset Trim Register
-#define ADC_O_PPB1CONFIG          0x40        // ADC PPB1 Config Register
-#define ADC_O_PPB1STAMP           0x41        // ADC PPB1 Sample Delay Time
-                                              // Stamp Register
-#define ADC_O_PPB1OFFCAL          0x42        // ADC PPB1 Offset Calibration
-                                              // Register
-#define ADC_O_PPB1OFFREF          0x43        // ADC PPB1 Offset Reference
-                                              // Register
-#define ADC_O_PPB1TRIPHI          0x44        // ADC PPB1 Trip High Register
-#define ADC_O_PPB1TRIPLO          0x46        // ADC PPB1 Trip Low/Trigger Time
-                                              // Stamp Register
-#define ADC_O_PPB2CONFIG          0x48        // ADC PPB2 Config Register
-#define ADC_O_PPB2STAMP           0x49        // ADC PPB2 Sample Delay Time
-                                              // Stamp Register
-#define ADC_O_PPB2OFFCAL          0x4A        // ADC PPB2 Offset Calibration
-                                              // Register
-#define ADC_O_PPB2OFFREF          0x4B        // ADC PPB2 Offset Reference
-                                              // Register
-#define ADC_O_PPB2TRIPHI          0x4C        // ADC PPB2 Trip High Register
-#define ADC_O_PPB2TRIPLO          0x4E        // ADC PPB2 Trip Low/Trigger Time
-                                              // Stamp Register
-#define ADC_O_PPB3CONFIG          0x50        // ADC PPB3 Config Register
-#define ADC_O_PPB3STAMP           0x51        // ADC PPB3 Sample Delay Time
-                                              // Stamp Register
-#define ADC_O_PPB3OFFCAL          0x52        // ADC PPB3 Offset Calibration
-                                              // Register
-#define ADC_O_PPB3OFFREF          0x53        // ADC PPB3 Offset Reference
-                                              // Register
-#define ADC_O_PPB3TRIPHI          0x54        // ADC PPB3 Trip High Register
-#define ADC_O_PPB3TRIPLO          0x56        // ADC PPB3 Trip Low/Trigger Time
-                                              // Stamp Register
-#define ADC_O_PPB4CONFIG          0x58        // ADC PPB4 Config Register
-#define ADC_O_PPB4STAMP           0x59        // ADC PPB4 Sample Delay Time
-                                              // Stamp Register
-#define ADC_O_PPB4OFFCAL          0x5A        // ADC PPB4 Offset Calibration
-                                              // Register
-#define ADC_O_PPB4OFFREF          0x5B        // ADC PPB4 Offset Reference
-                                              // Register
-#define ADC_O_PPB4TRIPHI          0x5C        // ADC PPB4 Trip High Register
-#define ADC_O_PPB4TRIPLO          0x5E        // ADC PPB4 Trip Low/Trigger Time
-                                              // Stamp Register
-#define ADC_O_RESULT0             0x0         // ADC Result 0 Register
-#define ADC_O_RESULT1             0x1         // ADC Result 1 Register
-#define ADC_O_RESULT2             0x2         // ADC Result 2 Register
-#define ADC_O_RESULT3             0x3         // ADC Result 3 Register
-#define ADC_O_RESULT4             0x4         // ADC Result 4 Register
-#define ADC_O_RESULT5             0x5         // ADC Result 5 Register
-#define ADC_O_RESULT6             0x6         // ADC Result 6 Register
-#define ADC_O_RESULT7             0x7         // ADC Result 7 Register
-#define ADC_O_RESULT8             0x8         // ADC Result 8 Register
-#define ADC_O_RESULT9             0x9         // ADC Result 9 Register
-#define ADC_O_RESULT10            0xA         // ADC Result 10 Register
-#define ADC_O_RESULT11            0xB         // ADC Result 11 Register
-#define ADC_O_RESULT12            0xC         // ADC Result 12 Register
-#define ADC_O_RESULT13            0xD         // ADC Result 13 Register
-#define ADC_O_RESULT14            0xE         // ADC Result 14 Register
-#define ADC_O_RESULT15            0xF         // ADC Result 15 Register
-#define ADC_O_PPB1RESULT          0x10        // ADC Post Processing Block 1
-                                              // Result Register
-#define ADC_O_PPB2RESULT          0x12        // ADC Post Processing Block 2
-                                              // Result Register
-#define ADC_O_PPB3RESULT          0x14        // ADC Post Processing Block 3
-                                              // Result Register
-#define ADC_O_PPB4RESULT          0x16        // ADC Post Processing Block 4
-                                              // Result Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCCTL1 register
-//
-//*****************************************************************************
-#define ADC_CTL1_INTPULSEPOS      0x4         // ADC Interrupt Pulse Position
-#define ADC_CTL1_ADCPWDNZ         0x80        // ADC Power Down
-#define ADC_CTL1_ADCBSYCHN_S      8
-#define ADC_CTL1_ADCBSYCHN_M      0xF00       // ADC Busy Channel
-#define ADC_CTL1_ADCBSY           0x2000      // ADC Busy
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCCTL2 register
-//
-//*****************************************************************************
-#define ADC_CTL2_PRESCALE_S       0
-#define ADC_CTL2_PRESCALE_M       0xF         // ADC Clock Prescaler
-#define ADC_CTL2_RESOLUTION       0x40        // SOC Conversion Resolution
-#define ADC_CTL2_SIGNALMODE       0x80        // SOC Signaling Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCBURSTCTL register
-//
-//*****************************************************************************
-#define ADC_BURSTCTL_BURSTTRIGSEL_S  0
-#define ADC_BURSTCTL_BURSTTRIGSEL_M  0x3F        // SOC Burst Trigger Source Select
-#define ADC_BURSTCTL_BURSTSIZE_S  8
-#define ADC_BURSTCTL_BURSTSIZE_M  0xF00       // SOC Burst Size Select
-#define ADC_BURSTCTL_BURSTEN      0x8000      // SOC Burst Mode Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCINTFLG register
-//
-//*****************************************************************************
-#define ADC_INTFLG_ADCINT1        0x1         // ADC Interrupt 1 Flag
-#define ADC_INTFLG_ADCINT2        0x2         // ADC Interrupt 2 Flag
-#define ADC_INTFLG_ADCINT3        0x4         // ADC Interrupt 3 Flag
-#define ADC_INTFLG_ADCINT4        0x8         // ADC Interrupt 4 Flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCINTFLGCLR register
-//
-//*****************************************************************************
-#define ADC_INTFLGCLR_ADCINT1     0x1         // ADC Interrupt 1 Flag Clear
-#define ADC_INTFLGCLR_ADCINT2     0x2         // ADC Interrupt 2 Flag Clear
-#define ADC_INTFLGCLR_ADCINT3     0x4         // ADC Interrupt 3 Flag Clear
-#define ADC_INTFLGCLR_ADCINT4     0x8         // ADC Interrupt 4 Flag Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCINTOVF register
-//
-//*****************************************************************************
-#define ADC_INTOVF_ADCINT1        0x1         // ADC Interrupt 1 Overflow Flags
-#define ADC_INTOVF_ADCINT2        0x2         // ADC Interrupt 2 Overflow Flags
-#define ADC_INTOVF_ADCINT3        0x4         // ADC Interrupt 3 Overflow Flags
-#define ADC_INTOVF_ADCINT4        0x8         // ADC Interrupt 4 Overflow Flags
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCINTOVFCLR register
-//
-//*****************************************************************************
-#define ADC_INTOVFCLR_ADCINT1     0x1         // ADC Interrupt 1 Overflow Clear
-                                              // Bits
-#define ADC_INTOVFCLR_ADCINT2     0x2         // ADC Interrupt 2 Overflow Clear
-                                              // Bits
-#define ADC_INTOVFCLR_ADCINT3     0x4         // ADC Interrupt 3 Overflow Clear
-                                              // Bits
-#define ADC_INTOVFCLR_ADCINT4     0x8         // ADC Interrupt 4 Overflow Clear
-                                              // Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCINTSEL1N2 register
-//
-//*****************************************************************************
-#define ADC_INTSEL1N2_INT1SEL_S   0
-#define ADC_INTSEL1N2_INT1SEL_M   0xF         // ADCINT1 EOC Source Select
-#define ADC_INTSEL1N2_INT1E       0x20        // ADCINT1 Interrupt Enable
-#define ADC_INTSEL1N2_INT1CONT    0x40        // ADCINT1 Continuous Mode Enable
-#define ADC_INTSEL1N2_INT2SEL_S   8
-#define ADC_INTSEL1N2_INT2SEL_M   0xF00       // ADCINT2 EOC Source Select
-#define ADC_INTSEL1N2_INT2E       0x2000      // ADCINT2 Interrupt Enable
-#define ADC_INTSEL1N2_INT2CONT    0x4000      // ADCINT2 Continuous Mode Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCINTSEL3N4 register
-//
-//*****************************************************************************
-#define ADC_INTSEL3N4_INT3SEL_S   0
-#define ADC_INTSEL3N4_INT3SEL_M   0xF         // ADCINT3 EOC Source Select
-#define ADC_INTSEL3N4_INT3E       0x20        // ADCINT3 Interrupt Enable
-#define ADC_INTSEL3N4_INT3CONT    0x40        // ADCINT3 Continuous Mode Enable
-#define ADC_INTSEL3N4_INT4SEL_S   8
-#define ADC_INTSEL3N4_INT4SEL_M   0xF00       // ADCINT4 EOC Source Select
-#define ADC_INTSEL3N4_INT4E       0x2000      // ADCINT4 Interrupt Enable
-#define ADC_INTSEL3N4_INT4CONT    0x4000      // ADCINT4 Continuous Mode Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOCPRICTL register
-//
-//*****************************************************************************
-#define ADC_SOCPRICTL_SOCPRIORITY_S  0
-#define ADC_SOCPRICTL_SOCPRIORITY_M  0x1F        // SOC Priority
-#define ADC_SOCPRICTL_RRPOINTER_S  5
-#define ADC_SOCPRICTL_RRPOINTER_M  0x3E0       // Round Robin Pointer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCINTSOCSEL1 register
-//
-//*****************************************************************************
-#define ADC_INTSOCSEL1_SOC0_S     0
-#define ADC_INTSOCSEL1_SOC0_M     0x3         // SOC0 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL1_SOC1_S     2
-#define ADC_INTSOCSEL1_SOC1_M     0xC         // SOC1 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL1_SOC2_S     4
-#define ADC_INTSOCSEL1_SOC2_M     0x30        // SOC2 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL1_SOC3_S     6
-#define ADC_INTSOCSEL1_SOC3_M     0xC0        // SOC3 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL1_SOC4_S     8
-#define ADC_INTSOCSEL1_SOC4_M     0x300       // SOC4 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL1_SOC5_S     10
-#define ADC_INTSOCSEL1_SOC5_M     0xC00       // SOC5 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL1_SOC6_S     12
-#define ADC_INTSOCSEL1_SOC6_M     0x3000      // SOC6 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL1_SOC7_S     14
-#define ADC_INTSOCSEL1_SOC7_M     0xC000      // SOC7 ADC Interrupt Trigger
-                                              // Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCINTSOCSEL2 register
-//
-//*****************************************************************************
-#define ADC_INTSOCSEL2_SOC8_S     0
-#define ADC_INTSOCSEL2_SOC8_M     0x3         // SOC8 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL2_SOC9_S     2
-#define ADC_INTSOCSEL2_SOC9_M     0xC         // SOC9 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL2_SOC10_S    4
-#define ADC_INTSOCSEL2_SOC10_M    0x30        // SOC10 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL2_SOC11_S    6
-#define ADC_INTSOCSEL2_SOC11_M    0xC0        // SOC11 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL2_SOC12_S    8
-#define ADC_INTSOCSEL2_SOC12_M    0x300       // SOC12 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL2_SOC13_S    10
-#define ADC_INTSOCSEL2_SOC13_M    0xC00       // SOC13 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL2_SOC14_S    12
-#define ADC_INTSOCSEL2_SOC14_M    0x3000      // SOC14 ADC Interrupt Trigger
-                                              // Select
-#define ADC_INTSOCSEL2_SOC15_S    14
-#define ADC_INTSOCSEL2_SOC15_M    0xC000      // SOC15 ADC Interrupt Trigger
-                                              // Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOCFLG1 register
-//
-//*****************************************************************************
-#define ADC_SOCFLG1_SOC0          0x1         // SOC0 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC1          0x2         // SOC1 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC2          0x4         // SOC2 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC3          0x8         // SOC3 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC4          0x10        // SOC4 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC5          0x20        // SOC5 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC6          0x40        // SOC6 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC7          0x80        // SOC7 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC8          0x100       // SOC8 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC9          0x200       // SOC9 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC10         0x400       // SOC10 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC11         0x800       // SOC11 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC12         0x1000      // SOC12 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC13         0x2000      // SOC13 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC14         0x4000      // SOC14 Start of Conversion Flag
-#define ADC_SOCFLG1_SOC15         0x8000      // SOC15 Start of Conversion Flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOCFRC1 register
-//
-//*****************************************************************************
-#define ADC_SOCFRC1_SOC0          0x1         // SOC0 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC1          0x2         // SOC1 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC2          0x4         // SOC2 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC3          0x8         // SOC3 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC4          0x10        // SOC4 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC5          0x20        // SOC5 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC6          0x40        // SOC6 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC7          0x80        // SOC7 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC8          0x100       // SOC8 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC9          0x200       // SOC9 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC10         0x400       // SOC10 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC11         0x800       // SOC11 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC12         0x1000      // SOC12 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC13         0x2000      // SOC13 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC14         0x4000      // SOC14 Force Start of Conversion
-                                              // Bit
-#define ADC_SOCFRC1_SOC15         0x8000      // SOC15 Force Start of Conversion
-                                              // Bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOCOVF1 register
-//
-//*****************************************************************************
-#define ADC_SOCOVF1_SOC0          0x1         // SOC0 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC1          0x2         // SOC1 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC2          0x4         // SOC2 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC3          0x8         // SOC3 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC4          0x10        // SOC4 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC5          0x20        // SOC5 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC6          0x40        // SOC6 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC7          0x80        // SOC7 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC8          0x100       // SOC8 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC9          0x200       // SOC9 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC10         0x400       // SOC10 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC11         0x800       // SOC11 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC12         0x1000      // SOC12 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC13         0x2000      // SOC13 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC14         0x4000      // SOC14 Start of Conversion
-                                              // Overflow Flag
-#define ADC_SOCOVF1_SOC15         0x8000      // SOC15 Start of Conversion
-                                              // Overflow Flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOCOVFCLR1 register
-//
-//*****************************************************************************
-#define ADC_SOCOVFCLR1_SOC0       0x1         // SOC0 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC1       0x2         // SOC1 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC2       0x4         // SOC2 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC3       0x8         // SOC3 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC4       0x10        // SOC4 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC5       0x20        // SOC5 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC6       0x40        // SOC6 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC7       0x80        // SOC7 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC8       0x100       // SOC8 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC9       0x200       // SOC9 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC10      0x400       // SOC10 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC11      0x800       // SOC11 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC12      0x1000      // SOC12 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC13      0x2000      // SOC13 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC14      0x4000      // SOC14 Clear Start of Conversion
-                                              // Overflow Bit
-#define ADC_SOCOVFCLR1_SOC15      0x8000      // SOC15 Clear Start of Conversion
-                                              // Overflow Bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC0CTL register
-//
-//*****************************************************************************
-#define ADC_SOC0CTL_ACQPS_S       0
-#define ADC_SOC0CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC0CTL_CHSEL_S       15
-#define ADC_SOC0CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC0CTL_TRIGSEL_S     20
-#define ADC_SOC0CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC1CTL register
-//
-//*****************************************************************************
-#define ADC_SOC1CTL_ACQPS_S       0
-#define ADC_SOC1CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC1CTL_CHSEL_S       15
-#define ADC_SOC1CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC1CTL_TRIGSEL_S     20
-#define ADC_SOC1CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC2CTL register
-//
-//*****************************************************************************
-#define ADC_SOC2CTL_ACQPS_S       0
-#define ADC_SOC2CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC2CTL_CHSEL_S       15
-#define ADC_SOC2CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC2CTL_TRIGSEL_S     20
-#define ADC_SOC2CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC3CTL register
-//
-//*****************************************************************************
-#define ADC_SOC3CTL_ACQPS_S       0
-#define ADC_SOC3CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC3CTL_CHSEL_S       15
-#define ADC_SOC3CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC3CTL_TRIGSEL_S     20
-#define ADC_SOC3CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC4CTL register
-//
-//*****************************************************************************
-#define ADC_SOC4CTL_ACQPS_S       0
-#define ADC_SOC4CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC4CTL_CHSEL_S       15
-#define ADC_SOC4CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC4CTL_TRIGSEL_S     20
-#define ADC_SOC4CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC5CTL register
-//
-//*****************************************************************************
-#define ADC_SOC5CTL_ACQPS_S       0
-#define ADC_SOC5CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC5CTL_CHSEL_S       15
-#define ADC_SOC5CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC5CTL_TRIGSEL_S     20
-#define ADC_SOC5CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC6CTL register
-//
-//*****************************************************************************
-#define ADC_SOC6CTL_ACQPS_S       0
-#define ADC_SOC6CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC6CTL_CHSEL_S       15
-#define ADC_SOC6CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC6CTL_TRIGSEL_S     20
-#define ADC_SOC6CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC7CTL register
-//
-//*****************************************************************************
-#define ADC_SOC7CTL_ACQPS_S       0
-#define ADC_SOC7CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC7CTL_CHSEL_S       15
-#define ADC_SOC7CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC7CTL_TRIGSEL_S     20
-#define ADC_SOC7CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC8CTL register
-//
-//*****************************************************************************
-#define ADC_SOC8CTL_ACQPS_S       0
-#define ADC_SOC8CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC8CTL_CHSEL_S       15
-#define ADC_SOC8CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC8CTL_TRIGSEL_S     20
-#define ADC_SOC8CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC9CTL register
-//
-//*****************************************************************************
-#define ADC_SOC9CTL_ACQPS_S       0
-#define ADC_SOC9CTL_ACQPS_M       0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC9CTL_CHSEL_S       15
-#define ADC_SOC9CTL_CHSEL_M       0x78000     // SOC Channel Select
-#define ADC_SOC9CTL_TRIGSEL_S     20
-#define ADC_SOC9CTL_TRIGSEL_M     0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC10CTL register
-//
-//*****************************************************************************
-#define ADC_SOC10CTL_ACQPS_S      0
-#define ADC_SOC10CTL_ACQPS_M      0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC10CTL_CHSEL_S      15
-#define ADC_SOC10CTL_CHSEL_M      0x78000     // SOC Channel Select
-#define ADC_SOC10CTL_TRIGSEL_S    20
-#define ADC_SOC10CTL_TRIGSEL_M    0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC11CTL register
-//
-//*****************************************************************************
-#define ADC_SOC11CTL_ACQPS_S      0
-#define ADC_SOC11CTL_ACQPS_M      0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC11CTL_CHSEL_S      15
-#define ADC_SOC11CTL_CHSEL_M      0x78000     // SOC Channel Select
-#define ADC_SOC11CTL_TRIGSEL_S    20
-#define ADC_SOC11CTL_TRIGSEL_M    0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC12CTL register
-//
-//*****************************************************************************
-#define ADC_SOC12CTL_ACQPS_S      0
-#define ADC_SOC12CTL_ACQPS_M      0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC12CTL_CHSEL_S      15
-#define ADC_SOC12CTL_CHSEL_M      0x78000     // SOC Channel Select
-#define ADC_SOC12CTL_TRIGSEL_S    20
-#define ADC_SOC12CTL_TRIGSEL_M    0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC13CTL register
-//
-//*****************************************************************************
-#define ADC_SOC13CTL_ACQPS_S      0
-#define ADC_SOC13CTL_ACQPS_M      0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC13CTL_CHSEL_S      15
-#define ADC_SOC13CTL_CHSEL_M      0x78000     // SOC Channel Select
-#define ADC_SOC13CTL_TRIGSEL_S    20
-#define ADC_SOC13CTL_TRIGSEL_M    0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC14CTL register
-//
-//*****************************************************************************
-#define ADC_SOC14CTL_ACQPS_S      0
-#define ADC_SOC14CTL_ACQPS_M      0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC14CTL_CHSEL_S      15
-#define ADC_SOC14CTL_CHSEL_M      0x78000     // SOC Channel Select
-#define ADC_SOC14CTL_TRIGSEL_S    20
-#define ADC_SOC14CTL_TRIGSEL_M    0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCSOC15CTL register
-//
-//*****************************************************************************
-#define ADC_SOC15CTL_ACQPS_S      0
-#define ADC_SOC15CTL_ACQPS_M      0x1FF       // SOC Acquisition Prescale
-#define ADC_SOC15CTL_CHSEL_S      15
-#define ADC_SOC15CTL_CHSEL_M      0x78000     // SOC Channel Select
-#define ADC_SOC15CTL_TRIGSEL_S    20
-#define ADC_SOC15CTL_TRIGSEL_M    0x1F00000   // SOC Trigger Source Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCEVTSTAT register
-//
-//*****************************************************************************
-#define ADC_EVTSTAT_PPB1TRIPHI    0x1         // Post Processing Block 1 Trip
-                                              // High Flag
-#define ADC_EVTSTAT_PPB1TRIPLO    0x2         // Post Processing Block 1 Trip
-                                              // Low Flag
-#define ADC_EVTSTAT_PPB1ZERO      0x4         // Post Processing Block 1 Zero
-                                              // Crossing Flag
-#define ADC_EVTSTAT_PPB2TRIPHI    0x10        // Post Processing Block 2 Trip
-                                              // High Flag
-#define ADC_EVTSTAT_PPB2TRIPLO    0x20        // Post Processing Block 2 Trip
-                                              // Low Flag
-#define ADC_EVTSTAT_PPB2ZERO      0x40        // Post Processing Block 2 Zero
-                                              // Crossing Flag
-#define ADC_EVTSTAT_PPB3TRIPHI    0x100       // Post Processing Block 3 Trip
-                                              // High Flag
-#define ADC_EVTSTAT_PPB3TRIPLO    0x200       // Post Processing Block 3 Trip
-                                              // Low Flag
-#define ADC_EVTSTAT_PPB3ZERO      0x400       // Post Processing Block 3 Zero
-                                              // Crossing Flag
-#define ADC_EVTSTAT_PPB4TRIPHI    0x1000      // Post Processing Block 4 Trip
-                                              // High Flag
-#define ADC_EVTSTAT_PPB4TRIPLO    0x2000      // Post Processing Block 4 Trip
-                                              // Low Flag
-#define ADC_EVTSTAT_PPB4ZERO      0x4000      // Post Processing Block 4 Zero
-                                              // Crossing Flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCEVTCLR register
-//
-//*****************************************************************************
-#define ADC_EVTCLR_PPB1TRIPHI     0x1         // Post Processing Block 1 Trip
-                                              // High Clear
-#define ADC_EVTCLR_PPB1TRIPLO     0x2         // Post Processing Block 1 Trip
-                                              // Low Clear
-#define ADC_EVTCLR_PPB1ZERO       0x4         // Post Processing Block 1 Zero
-                                              // Crossing Clear
-#define ADC_EVTCLR_PPB2TRIPHI     0x10        // Post Processing Block 2 Trip
-                                              // High Clear
-#define ADC_EVTCLR_PPB2TRIPLO     0x20        // Post Processing Block 2 Trip
-                                              // Low Clear
-#define ADC_EVTCLR_PPB2ZERO       0x40        // Post Processing Block 2 Zero
-                                              // Crossing Clear
-#define ADC_EVTCLR_PPB3TRIPHI     0x100       // Post Processing Block 3 Trip
-                                              // High Clear
-#define ADC_EVTCLR_PPB3TRIPLO     0x200       // Post Processing Block 3 Trip
-                                              // Low Clear
-#define ADC_EVTCLR_PPB3ZERO       0x400       // Post Processing Block 3 Zero
-                                              // Crossing Clear
-#define ADC_EVTCLR_PPB4TRIPHI     0x1000      // Post Processing Block 4 Trip
-                                              // High Clear
-#define ADC_EVTCLR_PPB4TRIPLO     0x2000      // Post Processing Block 4 Trip
-                                              // Low Clear
-#define ADC_EVTCLR_PPB4ZERO       0x4000      // Post Processing Block 4 Zero
-                                              // Crossing Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCEVTSEL register
-//
-//*****************************************************************************
-#define ADC_EVTSEL_PPB1TRIPHI     0x1         // Post Processing Block 1 Trip
-                                              // High Event Enable
-#define ADC_EVTSEL_PPB1TRIPLO     0x2         // Post Processing Block 1 Trip
-                                              // Low Event Enable
-#define ADC_EVTSEL_PPB1ZERO       0x4         // Post Processing Block 1 Zero
-                                              // Crossing Event Enable
-#define ADC_EVTSEL_PPB2TRIPHI     0x10        // Post Processing Block 2 Trip
-                                              // High Event Enable
-#define ADC_EVTSEL_PPB2TRIPLO     0x20        // Post Processing Block 2 Trip
-                                              // Low Event Enable
-#define ADC_EVTSEL_PPB2ZERO       0x40        // Post Processing Block 2 Zero
-                                              // Crossing Event Enable
-#define ADC_EVTSEL_PPB3TRIPHI     0x100       // Post Processing Block 3 Trip
-                                              // High Event Enable
-#define ADC_EVTSEL_PPB3TRIPLO     0x200       // Post Processing Block 3 Trip
-                                              // Low Event Enable
-#define ADC_EVTSEL_PPB3ZERO       0x400       // Post Processing Block 3 Zero
-                                              // Crossing Event Enable
-#define ADC_EVTSEL_PPB4TRIPHI     0x1000      // Post Processing Block 4 Trip
-                                              // High Event Enable
-#define ADC_EVTSEL_PPB4TRIPLO     0x2000      // Post Processing Block 4 Trip
-                                              // Low Event Enable
-#define ADC_EVTSEL_PPB4ZERO       0x4000      // Post Processing Block 4 Zero
-                                              // Crossing Event Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCEVTINTSEL register
-//
-//*****************************************************************************
-#define ADC_EVTINTSEL_PPB1TRIPHI  0x1         // Post Processing Block 1 Trip
-                                              // High Interrupt Enable
-#define ADC_EVTINTSEL_PPB1TRIPLO  0x2         // Post Processing Block 1 Trip
-                                              // Low Interrupt Enable
-#define ADC_EVTINTSEL_PPB1ZERO    0x4         // Post Processing Block 1 Zero
-                                              // Crossing Interrupt Enable
-#define ADC_EVTINTSEL_PPB2TRIPHI  0x10        // Post Processing Block 2 Trip
-                                              // High Interrupt Enable
-#define ADC_EVTINTSEL_PPB2TRIPLO  0x20        // Post Processing Block 2 Trip
-                                              // Low Interrupt Enable
-#define ADC_EVTINTSEL_PPB2ZERO    0x40        // Post Processing Block 2 Zero
-                                              // Crossing Interrupt Enable
-#define ADC_EVTINTSEL_PPB3TRIPHI  0x100       // Post Processing Block 3 Trip
-                                              // High Interrupt Enable
-#define ADC_EVTINTSEL_PPB3TRIPLO  0x200       // Post Processing Block 3 Trip
-                                              // Low Interrupt Enable
-#define ADC_EVTINTSEL_PPB3ZERO    0x400       // Post Processing Block 3 Zero
-                                              // Crossing Interrupt Enable
-#define ADC_EVTINTSEL_PPB4TRIPHI  0x1000      // Post Processing Block 4 Trip
-                                              // High Interrupt Enable
-#define ADC_EVTINTSEL_PPB4TRIPLO  0x2000      // Post Processing Block 4 Trip
-                                              // Low Interrupt Enable
-#define ADC_EVTINTSEL_PPB4ZERO    0x4000      // Post Processing Block 4 Zero
-                                              // Crossing Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCCOUNTER register
-//
-//*****************************************************************************
-#define ADC_COUNTER_FREECOUNT_S   0
-#define ADC_COUNTER_FREECOUNT_M   0xFFF       // ADC Free Running Counter Value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCREV register
-//
-//*****************************************************************************
-#define ADC_REV_TYPE_S            0
-#define ADC_REV_TYPE_M            0xFF        // ADC Type
-#define ADC_REV_REV_S             8
-#define ADC_REV_REV_M             0xFF00      // ADC Revision
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCOFFTRIM register
-//
-//*****************************************************************************
-#define ADC_OFFTRIM_OFFTRIM_S     0
-#define ADC_OFFTRIM_OFFTRIM_M     0xFF        // ADC Offset Trim
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB1CONFIG register
-//
-//*****************************************************************************
-#define ADC_PPB1CONFIG_CONFIG_S   0
-#define ADC_PPB1CONFIG_CONFIG_M   0xF         // ADC Post Processing Block
-                                              // Configuration
-#define ADC_PPB1CONFIG_TWOSCOMPEN  0x10        // ADC Post Processing Block Two's
-                                              // Complement Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB1STAMP register
-//
-//*****************************************************************************
-#define ADC_PPB1STAMP_DLYSTAMP_S  0
-#define ADC_PPB1STAMP_DLYSTAMP_M  0xFFF       // ADC Post Processing Block Delay
-                                              // Time Stamp
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB1OFFCAL register
-//
-//*****************************************************************************
-#define ADC_PPB1OFFCAL_OFFCAL_S   0
-#define ADC_PPB1OFFCAL_OFFCAL_M   0x3FF       // ADC Post Processing Block
-                                              // Offset Correction
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB1OFFREF register
-//
-//*****************************************************************************
-#define ADC_PPB1OFFREF_OFFREF_S   0
-#define ADC_PPB1OFFREF_OFFREF_M   0xFFFF      // ADC Post Processing Block
-                                              // Offset Reference
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB1TRIPHI register
-//
-//*****************************************************************************
-#define ADC_PPB1TRIPHI_LIMITHI_S  0
-#define ADC_PPB1TRIPHI_LIMITHI_M  0xFFFF      // ADC Post Processing Block Trip
-                                              // High Limit
-#define ADC_PPB1TRIPHI_HSIGN      0x10000     // High Limit Sign Bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB1TRIPLO register
-//
-//*****************************************************************************
-#define ADC_PPB1TRIPLO_LIMITLO_S  0
-#define ADC_PPB1TRIPLO_LIMITLO_M  0xFFFF      // ADC Post Processing Block Trip
-                                              // Low Limit
-#define ADC_PPB1TRIPLO_LSIGN      0x10000     // Low Limit Sign Bit
-#define ADC_PPB1TRIPLO_REQSTAMP_S  20
-#define ADC_PPB1TRIPLO_REQSTAMP_M  0xFFF00000  // ADC Post Processing Block
-                                              // Request Time Stamp
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB2CONFIG register
-//
-//*****************************************************************************
-#define ADC_PPB2CONFIG_CONFIG_S   0
-#define ADC_PPB2CONFIG_CONFIG_M   0xF         // ADC Post Processing Block
-                                              // Configuration
-#define ADC_PPB2CONFIG_TWOSCOMPEN  0x10        // ADC Post Processing Block Two's
-                                              // Complement Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB2STAMP register
-//
-//*****************************************************************************
-#define ADC_PPB2STAMP_DLYSTAMP_S  0
-#define ADC_PPB2STAMP_DLYSTAMP_M  0xFFF       // ADC Post Processing Block Delay
-                                              // Time Stamp
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB2OFFCAL register
-//
-//*****************************************************************************
-#define ADC_PPB2OFFCAL_OFFCAL_S   0
-#define ADC_PPB2OFFCAL_OFFCAL_M   0x3FF       // ADC Post Processing Block
-                                              // Offset Correction
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB2OFFREF register
-//
-//*****************************************************************************
-#define ADC_PPB2OFFREF_OFFREF_S   0
-#define ADC_PPB2OFFREF_OFFREF_M   0xFFFF      // ADC Post Processing Block
-                                              // Offset Reference
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB2TRIPHI register
-//
-//*****************************************************************************
-#define ADC_PPB2TRIPHI_LIMITHI_S  0
-#define ADC_PPB2TRIPHI_LIMITHI_M  0xFFFF      // ADC Post Processing Block Trip
-                                              // High Limit
-#define ADC_PPB2TRIPHI_HSIGN      0x10000     // High Limit Sign Bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB2TRIPLO register
-//
-//*****************************************************************************
-#define ADC_PPB2TRIPLO_LIMITLO_S  0
-#define ADC_PPB2TRIPLO_LIMITLO_M  0xFFFF      // ADC Post Processing Block Trip
-                                              // Low Limit
-#define ADC_PPB2TRIPLO_LSIGN      0x10000     // Low Limit Sign Bit
-#define ADC_PPB2TRIPLO_REQSTAMP_S  20
-#define ADC_PPB2TRIPLO_REQSTAMP_M  0xFFF00000  // ADC Post Processing Block
-                                              // Request Time Stamp
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB3CONFIG register
-//
-//*****************************************************************************
-#define ADC_PPB3CONFIG_CONFIG_S   0
-#define ADC_PPB3CONFIG_CONFIG_M   0xF         // ADC Post Processing Block
-                                              // Configuration
-#define ADC_PPB3CONFIG_TWOSCOMPEN  0x10        // ADC Post Processing Block Two's
-                                              // Complement Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB3STAMP register
-//
-//*****************************************************************************
-#define ADC_PPB3STAMP_DLYSTAMP_S  0
-#define ADC_PPB3STAMP_DLYSTAMP_M  0xFFF       // ADC Post Processing Block Delay
-                                              // Time Stamp
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB3OFFCAL register
-//
-//*****************************************************************************
-#define ADC_PPB3OFFCAL_OFFCAL_S   0
-#define ADC_PPB3OFFCAL_OFFCAL_M   0x3FF       // ADC Post Processing Block
-                                              // Offset Correction
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB3OFFREF register
-//
-//*****************************************************************************
-#define ADC_PPB3OFFREF_OFFREF_S   0
-#define ADC_PPB3OFFREF_OFFREF_M   0xFFFF      // ADC Post Processing Block
-                                              // Offset Reference
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB3TRIPHI register
-//
-//*****************************************************************************
-#define ADC_PPB3TRIPHI_LIMITHI_S  0
-#define ADC_PPB3TRIPHI_LIMITHI_M  0xFFFF      // ADC Post Processing Block Trip
-                                              // High Limit
-#define ADC_PPB3TRIPHI_HSIGN      0x10000     // High Limit Sign Bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB3TRIPLO register
-//
-//*****************************************************************************
-#define ADC_PPB3TRIPLO_LIMITLO_S  0
-#define ADC_PPB3TRIPLO_LIMITLO_M  0xFFFF      // ADC Post Processing Block Trip
-                                              // Low Limit
-#define ADC_PPB3TRIPLO_LSIGN      0x10000     // Low Limit Sign Bit
-#define ADC_PPB3TRIPLO_REQSTAMP_S  20
-#define ADC_PPB3TRIPLO_REQSTAMP_M  0xFFF00000  // ADC Post Processing Block
-                                              // Request Time Stamp
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB4CONFIG register
-//
-//*****************************************************************************
-#define ADC_PPB4CONFIG_CONFIG_S   0
-#define ADC_PPB4CONFIG_CONFIG_M   0xF         // ADC Post Processing Block
-                                              // Configuration
-#define ADC_PPB4CONFIG_TWOSCOMPEN  0x10        // ADC Post Processing Block Two's
-                                              // Complement Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB4STAMP register
-//
-//*****************************************************************************
-#define ADC_PPB4STAMP_DLYSTAMP_S  0
-#define ADC_PPB4STAMP_DLYSTAMP_M  0xFFF       // ADC Post Processing Block Delay
-                                              // Time Stamp
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB4OFFCAL register
-//
-//*****************************************************************************
-#define ADC_PPB4OFFCAL_OFFCAL_S   0
-#define ADC_PPB4OFFCAL_OFFCAL_M   0x3FF       // ADC Post Processing Block
-                                              // Offset Correction
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB4OFFREF register
-//
-//*****************************************************************************
-#define ADC_PPB4OFFREF_OFFREF_S   0
-#define ADC_PPB4OFFREF_OFFREF_M   0xFFFF      // ADC Post Processing Block
-                                              // Offset Reference
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB4TRIPHI register
-//
-//*****************************************************************************
-#define ADC_PPB4TRIPHI_LIMITHI_S  0
-#define ADC_PPB4TRIPHI_LIMITHI_M  0xFFFF      // ADC Post Processing Block Trip
-                                              // High Limit
-#define ADC_PPB4TRIPHI_HSIGN      0x10000     // High Limit Sign Bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB4TRIPLO register
-//
-//*****************************************************************************
-#define ADC_PPB4TRIPLO_LIMITLO_S  0
-#define ADC_PPB4TRIPLO_LIMITLO_M  0xFFFF      // ADC Post Processing Block Trip
-                                              // Low Limit
-#define ADC_PPB4TRIPLO_LSIGN      0x10000     // Low Limit Sign Bit
-#define ADC_PPB4TRIPLO_REQSTAMP_S  20
-#define ADC_PPB4TRIPLO_REQSTAMP_M  0xFFF00000  // ADC Post Processing Block
-                                              // Request Time Stamp
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT0 register
-//
-//*****************************************************************************
-#define ADC_RESULT0_RESULT_S      0
-#define ADC_RESULT0_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT1 register
-//
-//*****************************************************************************
-#define ADC_RESULT1_RESULT_S      0
-#define ADC_RESULT1_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT2 register
-//
-//*****************************************************************************
-#define ADC_RESULT2_RESULT_S      0
-#define ADC_RESULT2_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT3 register
-//
-//*****************************************************************************
-#define ADC_RESULT3_RESULT_S      0
-#define ADC_RESULT3_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT4 register
-//
-//*****************************************************************************
-#define ADC_RESULT4_RESULT_S      0
-#define ADC_RESULT4_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT5 register
-//
-//*****************************************************************************
-#define ADC_RESULT5_RESULT_S      0
-#define ADC_RESULT5_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT6 register
-//
-//*****************************************************************************
-#define ADC_RESULT6_RESULT_S      0
-#define ADC_RESULT6_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT7 register
-//
-//*****************************************************************************
-#define ADC_RESULT7_RESULT_S      0
-#define ADC_RESULT7_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT8 register
-//
-//*****************************************************************************
-#define ADC_RESULT8_RESULT_S      0
-#define ADC_RESULT8_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT9 register
-//
-//*****************************************************************************
-#define ADC_RESULT9_RESULT_S      0
-#define ADC_RESULT9_RESULT_M      0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT10 register
-//
-//*****************************************************************************
-#define ADC_RESULT10_RESULT_S     0
-#define ADC_RESULT10_RESULT_M     0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT11 register
-//
-//*****************************************************************************
-#define ADC_RESULT11_RESULT_S     0
-#define ADC_RESULT11_RESULT_M     0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT12 register
-//
-//*****************************************************************************
-#define ADC_RESULT12_RESULT_S     0
-#define ADC_RESULT12_RESULT_M     0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT13 register
-//
-//*****************************************************************************
-#define ADC_RESULT13_RESULT_S     0
-#define ADC_RESULT13_RESULT_M     0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT14 register
-//
-//*****************************************************************************
-#define ADC_RESULT14_RESULT_S     0
-#define ADC_RESULT14_RESULT_M     0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCRESULT15 register
-//
-//*****************************************************************************
-#define ADC_RESULT15_RESULT_S     0
-#define ADC_RESULT15_RESULT_M     0xFFFF      // ADC Result
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB1RESULT register
-//
-//*****************************************************************************
-#define ADC_PPB1RESULT_PPBRESULT_S  0
-#define ADC_PPB1RESULT_PPBRESULT_M  0xFFFF      // ADC Post Processing Block
-                                              // Result
-#define ADC_PPB1RESULT_SIGN_S     16
-#define ADC_PPB1RESULT_SIGN_M     0xFFFF0000  // Sign Extended Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB2RESULT register
-//
-//*****************************************************************************
-#define ADC_PPB2RESULT_PPBRESULT_S  0
-#define ADC_PPB2RESULT_PPBRESULT_M  0xFFFF      // ADC Post Processing Block
-                                              // Result
-#define ADC_PPB2RESULT_SIGN_S     16
-#define ADC_PPB2RESULT_SIGN_M     0xFFFF0000  // Sign Extended Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB3RESULT register
-//
-//*****************************************************************************
-#define ADC_PPB3RESULT_PPBRESULT_S  0
-#define ADC_PPB3RESULT_PPBRESULT_M  0xFFFF      // ADC Post Processing Block
-                                              // Result
-#define ADC_PPB3RESULT_SIGN_S     16
-#define ADC_PPB3RESULT_SIGN_M     0xFFFF0000  // Sign Extended Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADCPPB4RESULT register
-//
-//*****************************************************************************
-#define ADC_PPB4RESULT_PPBRESULT_S  0
-#define ADC_PPB4RESULT_PPBRESULT_M  0xFFFF      // ADC Post Processing Block
-                                              // Result
-#define ADC_PPB4RESULT_SIGN_S     16
-#define ADC_PPB4RESULT_SIGN_M     0xFFFF0000  // Sign Extended Bits
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_can.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_can.h
deleted file mode 100644
index f421a0caf8..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_can.h
+++ /dev/null
@@ -1,612 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_can.h
-//
-// TITLE:   Definitions for the C28x CAN registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_CAN_H__
-#define __HW_CAN_H__
-
-//*****************************************************************************
-//
-// The following are defines for the CAN register offsets
-//
-//*****************************************************************************
-#define CAN_O_CTL                 0x0         // CAN Control Register
-#define CAN_O_ES                  0x4         // Error and Status Register
-#define CAN_O_ERRC                0x8         // Error Counter Register
-#define CAN_O_BTR                 0xC         // Bit Timing Register
-#define CAN_O_INT                 0x10        // Interrupt Register
-#define CAN_O_TEST                0x14        // Test Register
-#define CAN_O_PERR                0x1C        // CAN Parity Error Code Register
-#define CAN_O_REL                 0x20        // CAN Core Release Register
-#define CAN_O_RAM_INIT            0x40        // CAN RAM Initialization Register
-#define CAN_O_GLB_INT_EN          0x50        // CAN Global Interrupt Enable
-                                              // Register
-#define CAN_O_GLB_INT_FLG         0x54        // CAN Global Interrupt Flag
-                                              // Register
-#define CAN_O_GLB_INT_CLR         0x58        // CAN Global Interrupt Clear
-                                              // Register
-#define CAN_O_ABOTR               0x80        // Auto-Bus-On Time Register
-#define CAN_O_TXRQ_X              0x84        // CAN Transmission Request X
-                                              // Register
-#define CAN_O_TXRQ_21             0x88        // CAN Transmission Request 2_1
-                                              // Register
-#define CAN_O_NDAT_X              0x98        // CAN New Data X Register
-#define CAN_O_NDAT_21             0x9C        // CAN New Data 2_1 Register
-#define CAN_O_IPEN_X              0xAC        // CAN Interrupt Pending X
-                                              // Register
-#define CAN_O_IPEN_21             0xB0        // CAN Interrupt Pending 2_1
-                                              // Register
-#define CAN_O_MVAL_X              0xC0        // CAN Message Valid X Register
-#define CAN_O_MVAL_21             0xC4        // CAN Message Valid 2_1 Register
-#define CAN_O_IP_MUX21            0xD8        // CAN Interrupt Multiplexer 2_1
-                                              // Register
-#define CAN_O_IF1CMD              0x100       // IF1 Command Register
-#define CAN_O_IF1MSK              0x104       // IF1 Mask Register
-#define CAN_O_IF1ARB              0x108       // IF1 Arbitration Register
-#define CAN_O_IF1MCTL             0x10C       // IF1 Message Control Register
-#define CAN_O_IF1DATA             0x110       // IF1 Data A Register
-#define CAN_O_IF1DATB             0x114       // IF1 Data B Register
-#define CAN_O_IF2CMD              0x120       // IF2 Command Register
-#define CAN_O_IF2MSK              0x124       // IF2 Mask Register
-#define CAN_O_IF2ARB              0x128       // IF2 Arbitration Register
-#define CAN_O_IF2MCTL             0x12C       // IF2 Message Control Register
-#define CAN_O_IF2DATA             0x130       // IF2 Data A Register
-#define CAN_O_IF2DATB             0x134       // IF2 Data B Register
-#define CAN_O_IF3OBS              0x140       // IF3 Observation Register
-#define CAN_O_IF3MSK              0x144       // IF3 Mask Register
-#define CAN_O_IF3ARB              0x148       // IF3 Arbitration Register
-#define CAN_O_IF3MCTL             0x14C       // IF3 Message Control Register
-#define CAN_O_IF3DATA             0x150       // IF3 Data A Register
-#define CAN_O_IF3DATB             0x154       // IF3 Data B Register
-#define CAN_O_IF3UPD              0x160       // IF3 Update Enable Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_CTL register
-//
-//*****************************************************************************
-#define CAN_CTL_INIT              0x1         // Initialization
-#define CAN_CTL_IE0               0x2         // Interrupt line 0 Enable
-                                              // Disabled
-#define CAN_CTL_SIE               0x4         // Status Change Interrupt Enable
-                                              // Disabled
-#define CAN_CTL_EIE               0x8         // Error Interrupt Enable Disabled
-#define CAN_CTL_DAR               0x20        // Disable Automatic
-                                              // Retransmission
-#define CAN_CTL_CCE               0x40        // Configuration Change Enable
-#define CAN_CTL_TEST              0x80        // Test Mode Enable
-#define CAN_CTL_IDS               0x100       // Interruption Debug Support
-                                              // Enable
-#define CAN_CTL_ABO               0x200       // Auto-Bus-On Enable
-#define CAN_CTL_PMD_S             10
-#define CAN_CTL_PMD_M             0x3C00      // Parity on/off
-#define CAN_CTL_SWR               0x8000      // SW Reset Enable
-#define CAN_CTL_INITDBG           0x10000     // Debug Mode Status
-#define CAN_CTL_IE1               0x20000     // Interrupt line 1 Enable
-                                              // Disabled
-#define CAN_CTL_PDR               0x1000000   // Power Down Request Mode
-#define CAN_CTL_WUBA              0x2000000   // Wake Up on Bus Activity
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_ES register
-//
-//*****************************************************************************
-#define CAN_ES_LEC_S              0
-#define CAN_ES_LEC_M              0x7         // Last Error Code
-#define CAN_ES_TXOK               0x8         // Transmission status
-#define CAN_ES_RXOK               0x10        // Reception status
-#define CAN_ES_EPASS              0x20        // Error Passive State
-#define CAN_ES_EWARN              0x40        // Warning State
-#define CAN_ES_BOFF               0x80        // Bus-Off State
-#define CAN_ES_PER                0x100       // Parity Error Detected
-#define CAN_ES_WAKEUPPND          0x200       // Wake Up Pending
-#define CAN_ES_PDA                0x400       // Power down mode acknowledge
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_ERRC register
-//
-//*****************************************************************************
-#define CAN_ERRC_TEC_S            0
-#define CAN_ERRC_TEC_M            0xFF        // Transmit Error Counter
-#define CAN_ERRC_REC_S            8
-#define CAN_ERRC_REC_M            0x7F00      // Receive Error Counter
-#define CAN_ERRC_RP               0x8000      // Receive Error Passive
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_BTR register
-//
-//*****************************************************************************
-#define CAN_BTR_BRP_S             0
-#define CAN_BTR_BRP_M             0x3F       // Baud Rate Prescaler
-#define CAN_BTR_SJW_S             6
-#define CAN_BTR_SJW_M             0xC0        // Synchronization Jump Width
-#define CAN_BTR_TSEG1_S           8
-#define CAN_BTR_TSEG1_M           0xF00       // Time segment
-#define CAN_BTR_TSEG2_S           12
-#define CAN_BTR_TSEG2_M           0x7000      // Time segment
-#define CAN_BTR_BRPE_S            16
-#define CAN_BTR_BRPE_M            0xF0000     // Baud Rate Prescaler Extension
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_INT register
-//
-//*****************************************************************************
-#define CAN_INT_INT0ID_S          0
-#define CAN_INT_INT0ID_M          0xFFFF      // Interrupt Identifier
-#define CAN_INT_INT1ID_S          16
-#define CAN_INT_INT1ID_M          0xFF0000    // Interrupt 1 Identifier
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_TEST register
-//
-//*****************************************************************************
-#define CAN_TEST_SILENT           0x8         // Silent Mode
-#define CAN_TEST_LBACK            0x10        // Loopback Mode
-#define CAN_TEST_TX_S             5
-#define CAN_TEST_TX_M             0x60        // CANTX Pin Control
-#define CAN_TEST_RX               0x80        // CANRX Pin Status
-#define CAN_TEST_EXL              0x100       // External Loopback Mode
-#define CAN_TEST_RDA              0x200       // RAM Direct Access Enable:
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_PERR register
-//
-//*****************************************************************************
-#define CAN_PERR_MSG_NUM_S        0
-#define CAN_PERR_MSG_NUM_M        0xFF        // Message Number
-#define CAN_PERR_WORD_NUM_S       8
-#define CAN_PERR_WORD_NUM_M       0x700       // Word Number
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_REL register
-//
-//*****************************************************************************
-#define CAN_REL_DAY_S             0
-#define CAN_REL_DAY_M             0xFF        // Day
-#define CAN_REL_MON_S             8
-#define CAN_REL_MON_M             0xFF00      // Month
-#define CAN_REL_YEAR_S            16
-#define CAN_REL_YEAR_M            0xF0000     // Year
-#define CAN_REL_SUBSTEP_S         20
-#define CAN_REL_SUBSTEP_M         0xF00000    // Substep
-#define CAN_REL_STEP_S            24
-#define CAN_REL_STEP_M            0xF000000   // Step
-#define CAN_REL_REL_S             28
-#define CAN_REL_REL_M             0xF0000000  // Release
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_RAM_INIT register
-//
-//*****************************************************************************
-#define CAN_RAM_INIT_KEY0         0x1         // KEY0
-#define CAN_RAM_INIT_KEY1         0x2         // KEY1
-#define CAN_RAM_INIT_KEY2         0x4         // KEY2
-#define CAN_RAM_INIT_KEY3         0x8         // KEY3
-#define CAN_RAM_INIT_CAN_RAM_INIT  0x10        // Initialize CAN Mailbox RAM
-#define CAN_RAM_INIT_RAM_INIT_DONE  0x20        // CAN RAM initialization complete
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_GLB_INT_EN register
-//
-//*****************************************************************************
-#define CAN_GLB_INT_CANINT0  0x1         // Global Interrupt Enable for CAN INT0
-#define CAN_GLB_INT_CANINT1  0x2         // Global Interrupt Enable for CAN INT1
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_GLB_INT_FLG register
-//
-//*****************************************************************************
-#define CAN_GLB_INT_FLG_NAME      0x1         // Global Interrupt Flag for CAN
-                                              // INT0
-#define CAN_GLB_INT_FLG_INT1_FLG  0x2         // Global Interrupt Flag for CAN
-                                              // INT1
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_GLB_INT_CLR register
-//
-//*****************************************************************************
-#define CAN_GLB_INT_CLR_INT0_FLG_CLR  0x1         // Global Interrupt flag clear for
-                                              // CAN INT0
-#define CAN_GLB_INT_CLR_INT1_FLG_CLR  0x2         // Global Interrupt flag  clear
-                                              // for CAN INT1
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_ABOTR register
-//
-//*****************************************************************************
-#define CAN_ABOTR_ABO_TIME_S      0
-#define CAN_ABOTR_ABO_TIME_M      0xFFFFFFFF  // Auto-Bus-On Timer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_TXRQ_X register
-//
-//*****************************************************************************
-#define CAN_TXRQ_X_TXRQSTREG1_S   0
-#define CAN_TXRQ_X_TXRQSTREG1_M   0x3         // Transmit Request Register 1
-#define CAN_TXRQ_X_TXRQSTREG2_S   2
-#define CAN_TXRQ_X_TXRQSTREG2_M   0xC         // Transmit Request Register 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_TXRQ_21 register
-//
-//*****************************************************************************
-#define CAN_TXRQ_21_TXRQST_S      0
-#define CAN_TXRQ_21_TXRQST_M      0xFFFFFFFF  // Transmission Request Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_NDAT_X register
-//
-//*****************************************************************************
-#define CAN_NDAT_X_NEWDATREG1_S   0
-#define CAN_NDAT_X_NEWDATREG1_M   0x3         // New Data Register 1
-#define CAN_NDAT_X_NEWDATREG2_S   2
-#define CAN_NDAT_X_NEWDATREG2_M   0xC         // New Data Register 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_NDAT_21 register
-//
-//*****************************************************************************
-#define CAN_NDAT_21_NEWDAT_S      0
-#define CAN_NDAT_21_NEWDAT_M      0xFFFFFFFF  // New Data Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IPEN_X register
-//
-//*****************************************************************************
-#define CAN_IPEN_X_INTPNDREG1_S   0
-#define CAN_IPEN_X_INTPNDREG1_M   0x3         // Interrupt Pending Register 1
-#define CAN_IPEN_X_INTPNDREG2_S   2
-#define CAN_IPEN_X_INTPNDREG2_M   0xC         // Interrupt Pending Register 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IPEN_21 register
-//
-//*****************************************************************************
-#define CAN_IPEN_21_INTPND_S      0
-#define CAN_IPEN_21_INTPND_M      0xFFFFFFFF  // Interrupt Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_MVAL_X register
-//
-//*****************************************************************************
-#define CAN_MVAL_X_MSGVALREG1_S   0
-#define CAN_MVAL_X_MSGVALREG1_M   0x3         // Message Valid Register 1
-#define CAN_MVAL_X_MSGVALREG2_S   2
-#define CAN_MVAL_X_MSGVALREG2_M   0xC         // Message Valid Register 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_MVAL_21 register
-//
-//*****************************************************************************
-#define CAN_MVAL_21_MSGVALREG_S   0
-#define CAN_MVAL_21_MSGVALREG_M   0xFFFFFFFF  // Message Valid Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IP_MUX21 register
-//
-//*****************************************************************************
-#define CAN_IP_MUX21_INTMUX_S     0
-#define CAN_IP_MUX21_INTMUX_M     0xFFFFFFFF  // Interrupt Mux
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF1CMD register
-//
-//*****************************************************************************
-#define CAN_IF1CMD_MSG_NUM_S      0
-#define CAN_IF1CMD_MSG_NUM_M      0xFF        // Message Number
-#define CAN_IF1CMD_BUSY           0x8000      // Busy Flag
-#define CAN_IF1CMD_DATA_B         0x10000     // Access Data Bytes 4-7
-#define CAN_IF1CMD_DATA_A         0x20000     // Access Data Bytes 0-3
-#define CAN_IF1CMD_TXRQST         0x40000     // Access Transmission Request Bit
-#define CAN_IF1CMD_CLRINTPND      0x80000     // Clear Interrupt Pending Bit
-#define CAN_IF1CMD_CONTROL        0x100000    // Access Control Bits
-#define CAN_IF1CMD_ARB            0x200000    // Access Arbitration Bits
-#define CAN_IF1CMD_MASK           0x400000    // Access Mask Bits
-#define CAN_IF1CMD_DIR            0x800000    // Write/Read Direction
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF1MSK register
-//
-//*****************************************************************************
-#define CAN_IF1MSK_MSK_S          0
-#define CAN_IF1MSK_MSK_M          0x1FFFFFFF  // Identifier Mask
-#define CAN_IF1MSK_MDIR           0x40000000  // Mask Message Direction
-#define CAN_IF1MSK_MXTD           0x80000000  // Mask Extended Identifier
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF1ARB register
-//
-//*****************************************************************************
-#define CAN_IF1ARB_ID_S           0
-#define CAN_IF1ARB_ID_M           0x1FFFFFFF  // `
-#define CAN_IF1ARB_DIR            0x20000000  // Message Direction
-#define CAN_IF1ARB_XTD            0x40000000  // Extended Identifier
-#define CAN_IF1ARB_MSGVAL         0x80000000  // Message Valid
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF1MCTL register
-//
-//*****************************************************************************
-#define CAN_IF1MCTL_DLC_S         0
-#define CAN_IF1MCTL_DLC_M         0xF         // Data length code
-#define CAN_IF1MCTL_EOB           0x80        // End of Block
-#define CAN_IF1MCTL_TXRQST        0x100       // Transmit Request
-#define CAN_IF1MCTL_RMTEN         0x200       // Remote Enable
-#define CAN_IF1MCTL_RXIE          0x400       // Receive Interrupt Enable
-#define CAN_IF1MCTL_TXIE          0x800       // Transmit Interrupt Enable
-#define CAN_IF1MCTL_UMASK         0x1000      // Use Acceptance Mask
-#define CAN_IF1MCTL_INTPND        0x2000      // Interrupt Pending
-#define CAN_IF1MCTL_MSGLST        0x4000      // Message Lost
-#define CAN_IF1MCTL_NEWDAT        0x8000      // New Data
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF1DATA register
-//
-//*****************************************************************************
-#define CAN_IF1DATA_DATA_0_S      0
-#define CAN_IF1DATA_DATA_0_M      0xFF        // Data Byte 0
-#define CAN_IF1DATA_DATA_1_S      8
-#define CAN_IF1DATA_DATA_1_M      0xFF00      // Data Byte 1
-#define CAN_IF1DATA_DATA_2_S      16
-#define CAN_IF1DATA_DATA_2_M      0xFF0000    // Data Byte 2
-#define CAN_IF1DATA_DATA_3_S      24
-#define CAN_IF1DATA_DATA_3_M      0xFF000000  // Data Byte 3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF1DATB register
-//
-//*****************************************************************************
-#define CAN_IF1DATB_DATA_4_S      0
-#define CAN_IF1DATB_DATA_4_M      0xFF        // Data Byte 4
-#define CAN_IF1DATB_DATA_5_S      8
-#define CAN_IF1DATB_DATA_5_M      0xFF00      // Data Byte 5
-#define CAN_IF1DATB_DATA_6_S      16
-#define CAN_IF1DATB_DATA_6_M      0xFF0000    // Data Byte 6
-#define CAN_IF1DATB_DATA_7_S      24
-#define CAN_IF1DATB_DATA_7_M      0xFF000000  // Data Byte 7
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF2CMD register
-//
-//*****************************************************************************
-#define CAN_IF2CMD_MSG_NUM_S      0
-#define CAN_IF2CMD_MSG_NUM_M      0xFF        // Message Number
-#define CAN_IF2CMD_BUSY           0x8000      // Busy Flag
-#define CAN_IF2CMD_DATA_B         0x10000     // Access Data Bytes 4-7
-#define CAN_IF2CMD_DATA_A         0x20000     // Access Data Bytes 0-3
-#define CAN_IF2CMD_TXRQST         0x40000     // Access Transmission Request Bit
-#define CAN_IF2CMD_CLRINTPND      0x80000     // Clear Interrupt Pending Bit
-#define CAN_IF2CMD_CONTROL        0x100000    // Access Control Bits
-#define CAN_IF2CMD_ARB            0x200000    // Access Arbitration Bits
-#define CAN_IF2CMD_MASK           0x400000    // Access Mask Bits
-#define CAN_IF2CMD_DIR            0x800000    // Write/Read Direction
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF2MSK register
-//
-//*****************************************************************************
-#define CAN_IF2MSK_MSK_S          0
-#define CAN_IF2MSK_MSK_M          0x1FFFFFFF  // Identifier Mask
-#define CAN_IF2MSK_MDIR           0x40000000  // Mask Message Direction
-#define CAN_IF2MSK_MXTD           0x80000000  // Mask Extended Identifier
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF2ARB register
-//
-//*****************************************************************************
-#define CAN_IF2ARB_ID_S           0
-#define CAN_IF2ARB_ID_M           0x1FFFFFFF  // Message  Identifier
-#define CAN_IF2ARB_DIR            0x20000000  // Message Direction
-#define CAN_IF2ARB_XTD            0x40000000  // Extended Identifier
-#define CAN_IF2ARB_MSGVAL         0x80000000  // Message Valid
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF2MCTL register
-//
-//*****************************************************************************
-#define CAN_IF2MCTL_DLC_S         0
-#define CAN_IF2MCTL_DLC_M         0xF         // Data length code
-#define CAN_IF2MCTL_EOB           0x80        // End of Block
-#define CAN_IF2MCTL_TXRQST        0x100       // Transmit Request
-#define CAN_IF2MCTL_RMTEN         0x200       // Remote Enable
-#define CAN_IF2MCTL_RXIE          0x400       // Receive Interrupt Enable
-#define CAN_IF2MCTL_TXIE          0x800       // Transmit Interrupt Enable
-#define CAN_IF2MCTL_UMASK         0x1000      // Use Acceptance Mask
-#define CAN_IF2MCTL_INTPND        0x2000      // Interrupt Pending
-#define CAN_IF2MCTL_MSGLST        0x4000      // Message Lost
-#define CAN_IF2MCTL_NEWDAT        0x8000      // New Data
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF2DATA register
-//
-//*****************************************************************************
-#define CAN_IF2DATA_DATA_0_S      0
-#define CAN_IF2DATA_DATA_0_M      0xFF        // Data Byte 0
-#define CAN_IF2DATA_DATA_1_S      8
-#define CAN_IF2DATA_DATA_1_M      0xFF00      // Data Byte 1
-#define CAN_IF2DATA_DATA_2_S      16
-#define CAN_IF2DATA_DATA_2_M      0xFF0000    // Data Byte 2
-#define CAN_IF2DATA_DATA_3_S      24
-#define CAN_IF2DATA_DATA_3_M      0xFF000000  // Data Byte 3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF2DATB register
-//
-//*****************************************************************************
-#define CAN_IF2DATB_DATA_4_S      0
-#define CAN_IF2DATB_DATA_4_M      0xFF        // Data Byte 4
-#define CAN_IF2DATB_DATA_5_S      8
-#define CAN_IF2DATB_DATA_5_M      0xFF00      // Data Byte 5
-#define CAN_IF2DATB_DATA_6_S      16
-#define CAN_IF2DATB_DATA_6_M      0xFF0000    // Data Byte 6
-#define CAN_IF2DATB_DATA_7_S      24
-#define CAN_IF2DATB_DATA_7_M      0xFF000000  // Data Byte 7
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF3OBS register
-//
-//*****************************************************************************
-#define CAN_IF3OBS_MASK           0x1         // Mask data read observation
-#define CAN_IF3OBS_ARB            0x2         // Arbitration data read
-                                              // observation
-#define CAN_IF3OBS_CTRL           0x4         // Ctrl read observation
-#define CAN_IF3OBS_DATA_A         0x8         // Data A read observation
-#define CAN_IF3OBS_DATA_B         0x10        // Data B read observation
-#define CAN_IF3OBS_IF3SM          0x100       // IF3 Status of Mask data read
-                                              // access
-#define CAN_IF3OBS_IF3SA          0x200       // IF3 Status of Arbitration data
-                                              // read access
-#define CAN_IF3OBS_IF3SC          0x400       // IF3 Status of Control bits read
-                                              // access
-#define CAN_IF3OBS_IF3SDA         0x800       // IF3 Status of Data A read
-                                              // access
-#define CAN_IF3OBS_IF3SDB         0x1000      // IF3 Status of Data B read
-                                              // access
-#define CAN_IF3OBS_IF3UPD         0x8000      // IF3 Update Data
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF3MSK register
-//
-//*****************************************************************************
-#define CAN_IF3MSK_MSK_S          0
-#define CAN_IF3MSK_MSK_M          0x1FFFFFFF  // Mask
-#define CAN_IF3MSK_MDIR           0x40000000  // Mask Message Direction
-#define CAN_IF3MSK_MXTD           0x80000000  // Mask Extended Identifier
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF3ARB register
-//
-//*****************************************************************************
-#define CAN_IF3ARB_ID_S           0
-#define CAN_IF3ARB_ID_M           0x1FFFFFFF  // Message  Identifier
-#define CAN_IF3ARB_DIR            0x20000000  // Message Direction
-#define CAN_IF3ARB_XTD            0x40000000  // Extended Identifier
-#define CAN_IF3ARB_MSGVAL         0x80000000  // Message Valid
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF3MCTL register
-//
-//*****************************************************************************
-#define CAN_IF3MCTL_DLC_S         0
-#define CAN_IF3MCTL_DLC_M         0xF         // Data length code
-#define CAN_IF3MCTL_EOB           0x80        // End of Block
-#define CAN_IF3MCTL_TXRQST        0x100       // Transmit Request
-#define CAN_IF3MCTL_RMTEN         0x200       // Remote Enable
-#define CAN_IF3MCTL_RXIE          0x400       // Receive Interrupt Enable
-#define CAN_IF3MCTL_TXIE          0x800       // Transmit Interrupt Enable
-#define CAN_IF3MCTL_UMASK         0x1000      // Use Acceptance Mask
-#define CAN_IF3MCTL_INTPND        0x2000      // Interrupt Pending
-#define CAN_IF3MCTL_MSGLST        0x4000      // Message Lost
-#define CAN_IF3MCTL_NEWDAT        0x8000      // New Data
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF3DATA register
-//
-//*****************************************************************************
-#define CAN_IF3DATA_DATA_0_S      0
-#define CAN_IF3DATA_DATA_0_M      0xFF        // Data Byte 0
-#define CAN_IF3DATA_DATA_1_S      8
-#define CAN_IF3DATA_DATA_1_M      0xFF00      // Data Byte 1
-#define CAN_IF3DATA_DATA_2_S      16
-#define CAN_IF3DATA_DATA_2_M      0xFF0000    // Data Byte 2
-#define CAN_IF3DATA_DATA_3_S      24
-#define CAN_IF3DATA_DATA_3_M      0xFF000000  // Data Byte 3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF3DATB register
-//
-//*****************************************************************************
-#define CAN_IF3DATB_DATA_4_S      0
-#define CAN_IF3DATB_DATA_4_M      0xFF        // Data Byte 4
-#define CAN_IF3DATB_DATA_5_S      8
-#define CAN_IF3DATB_DATA_5_M      0xFF00      // Data Byte 5
-#define CAN_IF3DATB_DATA_6_S      16
-#define CAN_IF3DATB_DATA_6_M      0xFF0000    // Data Byte 6
-#define CAN_IF3DATB_DATA_7_S      24
-#define CAN_IF3DATB_DATA_7_M      0xFF000000  // Data Byte 7
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_IF3UPD register
-//
-//*****************************************************************************
-#define CAN_IF3UPD_IF3UPDEN_S     0
-#define CAN_IF3UPD_IF3UPDEN_M     0xFFFFFFFF  // IF3 Update Enabled
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cmpss.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cmpss.h
deleted file mode 100644
index c87a8840e8..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cmpss.h
+++ /dev/null
@@ -1,295 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_cmpss.h
-//
-// TITLE:   Definitions for the C28x CMPSS registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_CMPSS_H__
-#define __HW_CMPSS_H__
-
-//*****************************************************************************
-//
-// The following are defines for the CMPSS register offsets
-//
-//*****************************************************************************
-#define CMPSS_O_COMPCTL           0x0         // CMPSS Comparator Control
-                                              // Register
-#define CMPSS_O_COMPHYSCTL        0x1         // CMPSS Comparator Hysteresis
-                                              // Control Register
-#define CMPSS_O_COMPSTS           0x2         // CMPSS Comparator Status
-                                              // Register
-#define CMPSS_O_COMPSTSCLR        0x3         // CMPSS Comparator Status Clear
-                                              // Register
-#define CMPSS_O_COMPDACCTL        0x4         // CMPSS DAC Control Register
-#define CMPSS_O_DACHVALS          0x6         // CMPSS High DAC Value Shadow
-                                              // Register
-#define CMPSS_O_DACHVALA          0x7         // CMPSS High DAC Value Active
-                                              // Register
-#define CMPSS_O_RAMPMAXREFA       0x8         // CMPSS Ramp Max Reference Active
-                                              // Register
-#define CMPSS_O_RAMPMAXREFS       0xA         // CMPSS Ramp Max Reference Shadow
-                                              // Register
-#define CMPSS_O_RAMPDECVALA       0xC         // CMPSS Ramp Decrement Value
-                                              // Active Register
-#define CMPSS_O_RAMPDECVALS       0xE         // CMPSS Ramp Decrement Value
-                                              // Shadow Register
-#define CMPSS_O_RAMPSTS           0x10        // CMPSS Ramp Status Register
-#define CMPSS_O_DACLVALS          0x12        // CMPSS Low DAC Value Shadow
-                                              // Register
-#define CMPSS_O_DACLVALA          0x13        // CMPSS Low DAC Value Active
-                                              // Register
-#define CMPSS_O_RAMPDLYA          0x14        // CMPSS Ramp Delay Active
-                                              // Register
-#define CMPSS_O_RAMPDLYS          0x15        // CMPSS Ramp Delay Shadow
-                                              // Register
-#define CMPSS_O_CTRIPLFILCTL      0x16        // CTRIPL Filter Control Register
-#define CMPSS_O_CTRIPLFILCLKCTL   0x17        // CTRIPL Filter Clock Control
-                                              // Register
-#define CMPSS_O_CTRIPHFILCTL      0x18        // CTRIPH Filter Control Register
-#define CMPSS_O_CTRIPHFILCLKCTL   0x19        // CTRIPH Filter Clock Control
-                                              // Register
-#define CMPSS_O_COMPLOCK          0x1A        // CMPSS Lock Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMPCTL register
-//
-//*****************************************************************************
-#define CMPSS_COMPCTL_COMPHSOURCE  0x1         // High Comparator Source Select
-#define CMPSS_COMPCTL_COMPHINV    0x2         // High Comparator Invert Select
-#define CMPSS_COMPCTL_CTRIPHSEL_S  2
-#define CMPSS_COMPCTL_CTRIPHSEL_M  0xC         // High Comparator Trip Select
-#define CMPSS_COMPCTL_CTRIPOUTHSEL_S  4
-#define CMPSS_COMPCTL_CTRIPOUTHSEL_M  0x30        // High Comparator Trip Output
-                                              // Select
-#define CMPSS_COMPCTL_ASYNCHEN    0x40        // High Comparator Asynchronous
-                                              // Path Enable
-#define CMPSS_COMPCTL_COMPLSOURCE  0x100       // Low Comparator Source Select
-#define CMPSS_COMPCTL_COMPLINV    0x200       // Low Comparator Invert Select
-#define CMPSS_COMPCTL_CTRIPLSEL_S  10
-#define CMPSS_COMPCTL_CTRIPLSEL_M  0xC00       // Low Comparator Trip Select
-#define CMPSS_COMPCTL_CTRIPOUTLSEL_S  12
-#define CMPSS_COMPCTL_CTRIPOUTLSEL_M  0x3000      // Low Comparator Trip Output
-                                              // Select
-#define CMPSS_COMPCTL_ASYNCLEN    0x4000      // Low Comparator Asynchronous
-                                              // Path Enable
-#define CMPSS_COMPCTL_COMPDACE    0x8000      // Comparator/DAC Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMPHYSCTL register
-//
-//*****************************************************************************
-#define CMPSS_COMPHYSCTL_COMPHYS_S  0
-#define CMPSS_COMPHYSCTL_COMPHYS_M  0x7         // Comparator Hysteresis Trim
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMPSTS register
-//
-//*****************************************************************************
-#define CMPSS_COMPSTS_COMPHSTS    0x1         // High Comparator Status
-#define CMPSS_COMPSTS_COMPHLATCH  0x2         // High Comparator Latched Status
-#define CMPSS_COMPSTS_COMPLSTS    0x100       // Low Comparator Status
-#define CMPSS_COMPSTS_COMPLLATCH  0x200       // Low Comparator Latched Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMPSTSCLR register
-//
-//*****************************************************************************
-#define CMPSS_COMPSTSCLR_HLATCHCLR  0x2         // High Comparator Latched Status
-                                              // Clear
-#define CMPSS_COMPSTSCLR_HSYNCCLREN  0x4         // High Comparator PWMSYNC Clear
-                                              // Enable
-#define CMPSS_COMPSTSCLR_LLATCHCLR  0x200       // Low Comparator Latched Status
-                                              // Clear
-#define CMPSS_COMPSTSCLR_LSYNCCLREN  0x400       // Low Comparator PWMSYNC Clear
-                                              // Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMPDACCTL register
-//
-//*****************************************************************************
-#define CMPSS_COMPDACCTL_DACSOURCE  0x1         // DAC Source Control
-#define CMPSS_COMPDACCTL_RAMPSOURCE_S  1
-#define CMPSS_COMPDACCTL_RAMPSOURCE_M  0x1E        // Ramp Generator Source Control
-#define CMPSS_COMPDACCTL_SELREF   0x20        // DAC Reference Select
-#define CMPSS_COMPDACCTL_RAMPLOADSEL  0x40        // Ramp Load Select
-#define CMPSS_COMPDACCTL_SWLOADSEL  0x80        // Software Load Select
-#define CMPSS_COMPDACCTL_FREESOFT_S  14
-#define CMPSS_COMPDACCTL_FREESOFT_M  0xC000      // Free/Soft Emulation Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DACHVALS register
-//
-//*****************************************************************************
-#define CMPSS_DACHVALS_DACVAL_S   0
-#define CMPSS_DACHVALS_DACVAL_M   0xFFF       // DAC Value Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DACHVALA register
-//
-//*****************************************************************************
-#define CMPSS_DACHVALA_DACVAL_S   0
-#define CMPSS_DACHVALA_DACVAL_M   0xFFF       // DAC Value Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the RAMPMAXREFA register
-//
-//*****************************************************************************
-#define CMPSS_RAMPMAXREFA_RAMPMAXREF_S  0
-#define CMPSS_RAMPMAXREFA_RAMPMAXREF_M  0xFFFF      // Ramp Maximum Reference Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the RAMPMAXREFS register
-//
-//*****************************************************************************
-#define CMPSS_RAMPMAXREFS_RAMPMAXREF_S  0
-#define CMPSS_RAMPMAXREFS_RAMPMAXREF_M  0xFFFF      // Ramp Maximum Reference Shadow
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the RAMPDECVALA register
-//
-//*****************************************************************************
-#define CMPSS_RAMPDECVALA_RAMPDECVAL_S  0
-#define CMPSS_RAMPDECVALA_RAMPDECVAL_M  0xFFFF      // Ramp Decrement Value Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the RAMPDECVALS register
-//
-//*****************************************************************************
-#define CMPSS_RAMPDECVALS_RAMPDECVAL_S  0
-#define CMPSS_RAMPDECVALS_RAMPDECVAL_M  0xFFFF      // Ramp Decrement Value Shadow
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the RAMPSTS register
-//
-//*****************************************************************************
-#define CMPSS_RAMPSTS_RAMPVALUE_S  0
-#define CMPSS_RAMPSTS_RAMPVALUE_M  0xFFFF      // Ramp Value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DACLVALS register
-//
-//*****************************************************************************
-#define CMPSS_DACLVALS_DACVAL_S   0
-#define CMPSS_DACLVALS_DACVAL_M   0xFFF       // DAC Value Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DACLVALA register
-//
-//*****************************************************************************
-#define CMPSS_DACLVALA_DACVAL_S   0
-#define CMPSS_DACLVALA_DACVAL_M   0xFFF       // DAC Value Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the RAMPDLYA register
-//
-//*****************************************************************************
-#define CMPSS_RAMPDLYA_DELAY_S    0
-#define CMPSS_RAMPDLYA_DELAY_M    0x1FFF      // Ramp Delay Value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the RAMPDLYS register
-//
-//*****************************************************************************
-#define CMPSS_RAMPDLYS_DELAY_S    0
-#define CMPSS_RAMPDLYS_DELAY_M    0x1FFF      // Ramp Delay Value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CTRIPLFILCTL register
-//
-//*****************************************************************************
-#define CMPSS_CTRIPLFILCTL_SAMPWIN_S  4
-#define CMPSS_CTRIPLFILCTL_SAMPWIN_M  0x1F0       // Sample Window
-#define CMPSS_CTRIPLFILCTL_THRESH_S  9
-#define CMPSS_CTRIPLFILCTL_THRESH_M  0x3E00      // Majority Voting Threshold
-#define CMPSS_CTRIPLFILCTL_FILINIT  0x8000      // Filter Initialization Bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CTRIPLFILCLKCTL register
-//
-//*****************************************************************************
-#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S  0
-#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M  0x3FF       // Sample Clock Prescale
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CTRIPHFILCTL register
-//
-//*****************************************************************************
-#define CMPSS_CTRIPHFILCTL_SAMPWIN_S  4
-#define CMPSS_CTRIPHFILCTL_SAMPWIN_M  0x1F0       // Sample Window
-#define CMPSS_CTRIPHFILCTL_THRESH_S  9
-#define CMPSS_CTRIPHFILCTL_THRESH_M  0x3E00      // Majority Voting Threshold
-#define CMPSS_CTRIPHFILCTL_FILINIT  0x8000      // Filter Initialization Bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CTRIPHFILCLKCTL register
-//
-//*****************************************************************************
-#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S  0
-#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M  0x3FF       // Sample Clock Prescale
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMPLOCK register
-//
-//*****************************************************************************
-#define CMPSS_COMPLOCK_COMPCTL    0x1         // COMPCTL Lock
-#define CMPSS_COMPLOCK_COMPHYSCTL  0x2         // COMPHYSCTL Lock
-#define CMPSS_COMPLOCK_DACCTL     0x4         // DACCTL Lock
-#define CMPSS_COMPLOCK_CTRIP      0x8         // CTRIP Lock
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cputimer.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cputimer.h
deleted file mode 100644
index c29d0dbcb2..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cputimer.h
+++ /dev/null
@@ -1,125 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_cputimer.h
-//
-// TITLE:   Definitions for the C28x CPUTIMER registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_CPUTIMER_H__
-#define __HW_CPUTIMER_H__
-
-//*****************************************************************************
-//
-// The following are defines for the CPUTIMER register offsets
-//
-//*****************************************************************************
-#define CPUTIMER_O_TIM            0x0         // CPU-Timer, Counter Register
-#define CPUTIMER_O_TIMH           0x1         // CPU-Timer, Counter Register
-                                              // High
-#define CPUTIMER_O_PRD            0x2         // CPU-Timer, Period Register
-#define CPUTIMER_O_PRDH           0x3         // CPU-Timer, Period Register High
-#define CPUTIMER_O_TCR            0x4         // CPU-Timer, Control Register
-#define CPUTIMER_O_TPR            0x6         // CPU-Timer, Prescale Register
-#define CPUTIMER_O_TPRH           0x7         // CPU-Timer, Prescale Register
-                                              // High
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIM register
-//
-//*****************************************************************************
-#define CPUTIMER_TIM_TIM_S        0
-#define CPUTIMER_TIM_TIM_M        0xFFFF      // CPU-Timer Counter Registers
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMH register
-//
-//*****************************************************************************
-#define CPUTIMER_TIMH_TIMH_S      0
-#define CPUTIMER_TIMH_TIMH_M      0xFFFF      // CPU-Timer Counter Registers
-                                              // High
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PRD register
-//
-//*****************************************************************************
-#define CPUTIMER_PRD_PRD_S        0
-#define CPUTIMER_PRD_PRD_M        0xFFFF      // CPU-Timer Period Registers
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PRDH register
-//
-//*****************************************************************************
-#define CPUTIMER_PRDH_PRDH_S      0
-#define CPUTIMER_PRDH_PRDH_M      0xFFFF      // CPU-Timer Period Registers High
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TCR register
-//
-//*****************************************************************************
-#define CPUTIMER_TCR_TSS          0x10        // CPU-Timer stop status bit.
-#define CPUTIMER_TCR_TRB          0x20        // Timer reload
-#define CPUTIMER_TCR_FREE_SOFT_S  10
-#define CPUTIMER_TCR_FREE_SOFT_M  0xC00       // Emulation modes
-#define CPUTIMER_TCR_TIE          0x4000      // CPU-Timer Interrupt Enable.
-#define CPUTIMER_TCR_TIF          0x8000      // CPU-Timer Interrupt Flag.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TPR register
-//
-//*****************************************************************************
-#define CPUTIMER_TPR_TDDR_S       0
-#define CPUTIMER_TPR_TDDR_M       0xFF        // CPU-Timer Divide-Down.
-#define CPUTIMER_TPR_PSC_S        8
-#define CPUTIMER_TPR_PSC_M        0xFF00      // CPU-Timer Prescale Counter.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TPRH register
-//
-//*****************************************************************************
-#define CPUTIMER_TPRH_TDDRH_S     0
-#define CPUTIMER_TPRH_TDDRH_M     0xFF        // CPU-Timer Divide-Down.
-#define CPUTIMER_TPRH_PSCH_S      8
-#define CPUTIMER_TPRH_PSCH_M      0xFF00      // CPU-Timer Prescale Counter.
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ecap.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ecap.h
deleted file mode 100644
index ed45234ce1..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ecap.h
+++ /dev/null
@@ -1,220 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_ecap.h
-//
-// TITLE:   Definitions for the C28x ECAP registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_ECAP_H__
-#define __HW_ECAP_H__
-
-//*****************************************************************************
-//
-// The following are defines for the ECAP register offsets
-//
-//*****************************************************************************
-#define ECAP_O_TSCTR              0x0         // Time-Stamp Counter
-#define ECAP_O_CTRPHS             0x2         // Counter Phase Offset Value
-                                              // Register
-#define ECAP_O_CAP1               0x4         // Capture 1 Register
-#define ECAP_O_CAP2               0x6         // Capture 2 Register
-#define ECAP_O_CAP3               0x8         // Capture 3Register
-#define ECAP_O_CAP4               0xA         // Capture 4 Register
-#define ECAP_O_ECCTL1             0x14        // Capture Control Register 1
-#define ECAP_O_ECCTL2             0x15        // Capture Control Register 2
-#define ECAP_O_ECEINT             0x16        // Capture Interrupt Enable
-                                              // Register
-#define ECAP_O_ECFLG              0x17        // Capture Interrupt Flag Register
-#define ECAP_O_ECCLR              0x18        // Capture Interrupt Flag Register
-#define ECAP_O_ECFRC              0x19        // Capture Interrupt Force
-                                              // Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TSCTR register
-//
-//*****************************************************************************
-#define ECAP_TSCTR_TSCTR_S        0
-#define ECAP_TSCTR_TSCTR_M        0xFFFFFFFF  // Time Stamp Counter
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CTRPHS register
-//
-//*****************************************************************************
-#define ECAP_CTRPHS_CTRPHS_S      0
-#define ECAP_CTRPHS_CTRPHS_M      0xFFFFFFFF  // Counter phase
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAP1 register
-//
-//*****************************************************************************
-#define ECAP_CAP1_CAP1_S          0
-#define ECAP_CAP1_CAP1_M          0xFFFFFFFF  // Capture 1
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAP2 register
-//
-//*****************************************************************************
-#define ECAP_CAP2_CAP2_S          0
-#define ECAP_CAP2_CAP2_M          0xFFFFFFFF  // Capture 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAP3 register
-//
-//*****************************************************************************
-#define ECAP_CAP3_CAP3_S          0
-#define ECAP_CAP3_CAP3_M          0xFFFFFFFF  // Capture 3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAP4 register
-//
-//*****************************************************************************
-#define ECAP_CAP4_CAP4_S          0
-#define ECAP_CAP4_CAP4_M          0xFFFFFFFF  // Capture 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ECCTL1 register
-//
-//*****************************************************************************
-#define ECAP_ECCTL1_CAP1POL       0x1         // Capture Event 1 Polarity select
-#define ECAP_ECCTL1_CTRRST1       0x2         // Counter Reset on Capture Event
-                                              // 1
-#define ECAP_ECCTL1_CAP2POL       0x4         // Capture Event 2 Polarity select
-#define ECAP_ECCTL1_CTRRST2       0x8         // Counter Reset on Capture Event
-                                              // 2
-#define ECAP_ECCTL1_CAP3POL       0x10        // Capture Event 3 Polarity select
-#define ECAP_ECCTL1_CTRRST3       0x20        // Counter Reset on Capture Event
-                                              // 3
-#define ECAP_ECCTL1_CAP4POL       0x40        // Capture Event 4 Polarity select
-#define ECAP_ECCTL1_CTRRST4       0x80        // Counter Reset on Capture Event
-                                              // 4
-#define ECAP_ECCTL1_CAPLDEN       0x100       // Enable Loading CAP1-4 regs on a
-                                              // Cap Event
-#define ECAP_ECCTL1_PRESCALE_S    9
-#define ECAP_ECCTL1_PRESCALE_M    0x3E00      // Event Filter prescale select
-#define ECAP_ECCTL1_FREE_SOFT_S   14
-#define ECAP_ECCTL1_FREE_SOFT_M   0xC000      // Emulation mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ECCTL2 register
-//
-//*****************************************************************************
-#define ECAP_ECCTL2_CONT_ONESHT   0x1         // Continuous or one-shot
-#define ECAP_ECCTL2_STOP_WRAP_S   1
-#define ECAP_ECCTL2_STOP_WRAP_M   0x6         // Stop value for one-shot, Wrap
-                                              // for continuous
-#define ECAP_ECCTL2_RE_ARM        0x8         // One-shot re-arm
-#define ECAP_ECCTL2_TSCTRSTOP     0x10        // TSCNT counter stop
-#define ECAP_ECCTL2_SYNCI_EN      0x20        // Counter sync-in select
-#define ECAP_ECCTL2_SYNCO_SEL_S   6
-#define ECAP_ECCTL2_SYNCO_SEL_M   0xC0        // Sync-out mode
-#define ECAP_ECCTL2_SWSYNC        0x100       // SW forced counter sync
-#define ECAP_ECCTL2_CAP_APWM      0x200       // CAP/APWM operating mode select
-#define ECAP_ECCTL2_APWMPOL       0x400       // APWM output polarity select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ECEINT register
-//
-//*****************************************************************************
-#define ECAP_ECEINT_CEVT1         0x2         // Capture Event 1 Interrupt
-                                              // Enable
-#define ECAP_ECEINT_CEVT2         0x4         // Capture Event 2 Interrupt
-                                              // Enable
-#define ECAP_ECEINT_CEVT3         0x8         // Capture Event 3 Interrupt
-                                              // Enable
-#define ECAP_ECEINT_CEVT4         0x10        // Capture Event 4 Interrupt
-                                              // Enable
-#define ECAP_ECEINT_CTROVF        0x20        // Counter Overflow Interrupt
-                                              // Enable
-#define ECAP_ECEINT_CTR_PRD       0x40        // Period Equal Interrupt Enable
-#define ECAP_ECEINT_CTR_CMP       0x80        // Compare Equal Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ECFLG register
-//
-//*****************************************************************************
-#define ECAP_ECFLG_INT            0x1         // Global Flag
-#define ECAP_ECFLG_CEVT1          0x2         // Capture Event 1 Interrupt Flag
-#define ECAP_ECFLG_CEVT2          0x4         // Capture Event 2 Interrupt Flag
-#define ECAP_ECFLG_CEVT3          0x8         // Capture Event 3 Interrupt Flag
-#define ECAP_ECFLG_CEVT4          0x10        // Capture Event 4 Interrupt Flag
-#define ECAP_ECFLG_CTROVF         0x20        // Counter Overflow Interrupt Flag
-#define ECAP_ECFLG_CTR_PRD        0x40        // Period Equal Interrupt Flag
-#define ECAP_ECFLG_CTR_CMP        0x80        // Compare Equal Interrupt Flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ECCLR register
-//
-//*****************************************************************************
-#define ECAP_ECCLR_INT            0x1         // Global Flag
-#define ECAP_ECCLR_CEVT1          0x2         // Capture Event 1 Interrupt Flag
-#define ECAP_ECCLR_CEVT2          0x4         // Capture Event 2 Interrupt Flag
-#define ECAP_ECCLR_CEVT3          0x8         // Capture Event 3 Interrupt Flag
-#define ECAP_ECCLR_CEVT4          0x10        // Capture Event 4 Interrupt Flag
-#define ECAP_ECCLR_CTROVF         0x20        // Counter Overflow Interrupt Flag
-#define ECAP_ECCLR_CTR_PRD        0x40        // Period Equal Interrupt Flag
-#define ECAP_ECCLR_CTR_CMP        0x80        // Compare Equal Interrupt Flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ECFRC register
-//
-//*****************************************************************************
-#define ECAP_ECFRC_CEVT1          0x2         // Capture Event 1 Interrupt
-                                              // Enable
-#define ECAP_ECFRC_CEVT2          0x4         // Capture Event 2 Interrupt
-                                              // Enable
-#define ECAP_ECFRC_CEVT3          0x8         // Capture Event 3 Interrupt
-                                              // Enable
-#define ECAP_ECFRC_CEVT4          0x10        // Capture Event 4 Interrupt
-                                              // Enable
-#define ECAP_ECFRC_CTROVF         0x20        // Counter Overflow Interrupt
-                                              // Enable
-#define ECAP_ECFRC_CTR_PRD        0x40        // Period Equal Interrupt Enable
-#define ECAP_ECFRC_CTR_CMP        0x80        // Compare Equal Interrupt Enable
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_emif.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_emif.h
deleted file mode 100644
index f753222091..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_emif.h
+++ /dev/null
@@ -1,372 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_emif.h
-//
-// TITLE:   Definitions for the C28x EMIF registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_EMIF_H__
-#define __HW_EMIF_H__
-
-//*****************************************************************************
-//
-// The following are defines for the EMIF register offsets
-//
-//*****************************************************************************
-#define EMIF_O_RCSR               0x0         // Revision Code and Status
-                                              // Register
-#define EMIF_O_ASYNC_WCCR         0x2         // Async Wait Cycle Config
-                                              // Register
-#define EMIF_O_SDRAM_CR           0x4         // SDRAM
-                                              // (pad_cs_o_n[0]/pad_cs_o_n[1])
-                                              // Config Register
-#define EMIF_O_SDRAM_RCR          0x6         // SDRAM Refresh Control Register
-#define EMIF_O_ASYNC_CS2_CR       0x8         // Async 1 (pad_cs_o_n[2]) Config
-                                              // Register
-#define EMIF_O_ASYNC_CS3_CR       0xA         // Async 2 (pad_cs_o_n[3]) Config
-                                              // Register
-#define EMIF_O_ASYNC_CS4_CR       0xC         // Async 3 (pad_cs_o_n[4]) Config
-                                              // Register
-#define EMIF_O_ASYNC_CS5_CR       0xE         // Async 4 (pad_cs_o_n[5]) Config
-                                              // Register
-#define EMIF_O_SDRAM_TR           0x10        // SDRAM Timing Register
-#define EMIF_O_TOTAL_SDRAM_AR     0x18        // Total SDRAM Accesses Register
-#define EMIF_O_TOTAL_SDRAM_ACTR   0x1A        // Total SDRAM Activate Register
-#define EMIF_O_SDR_EXT_TMNG       0x1E        // SDRAM SR/PD Exit Timing
-                                              // Register
-#define EMIF_O_INT_RAW            0x20        // Interrupt Raw Register
-#define EMIF_O_INT_MSK            0x22        // Interrupt Masked Register
-#define EMIF_O_INT_MSK_SET        0x24        // Interrupt Mask Set Register
-#define EMIF_O_INT_MSK_CLR        0x26        // Interrupt Mask Clear Register
-#define EMIF_O_IO_CTRL            0x28        // IO Control Register
-#define EMIF_O_IO_STAT            0x2A        // IO Status Register
-#define EMIF_O_MODEL_REL_NUM      0x56        // Module Release Number Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the RCSR register
-//
-//*****************************************************************************
-#define EMIF_RCSR_MINOR_REVISION_S  0
-#define EMIF_RCSR_MINOR_REVISION_M  0xFF        // Minor Revision.
-#define EMIF_RCSR_MAJOR_REVISION_S  8
-#define EMIF_RCSR_MAJOR_REVISION_M  0xFF00      // Major Revision.
-#define EMIF_RCSR_MODULE_ID_S     16
-#define EMIF_RCSR_MODULE_ID_M     0x3FFF0000  // EMIF module ID.
-#define EMIF_RCSR_FR              0x40000000  // EMIF is running in full rate or
-                                              // half rate.
-#define EMIF_RCSR_BE              0x80000000  // EMIF endian mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ASYNC_WCCR register
-//
-//*****************************************************************************
-#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_S  0
-#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M  0xFF        // Maximum Extended Wait cycles.
-#define EMIF_ASYNC_WCCR_CS2_WAIT_S  16
-#define EMIF_ASYNC_WCCR_CS2_WAIT_M  0x30000     // Maps the wait signal for chip
-                                              // select 2.
-#define EMIF_ASYNC_WCCR_CS3_WAIT_S  18
-#define EMIF_ASYNC_WCCR_CS3_WAIT_M  0xC0000     // Maps the wait signal for chip
-                                              // select 3.
-#define EMIF_ASYNC_WCCR_CS4_WAIT_S  20
-#define EMIF_ASYNC_WCCR_CS4_WAIT_M  0x300000    // Maps the wait signal for chip
-                                              // select 4.
-#define EMIF_ASYNC_WCCR_CS5_WAIT_S  22
-#define EMIF_ASYNC_WCCR_CS5_WAIT_M  0xC00000    // Maps the wait signal for chip
-                                              // select 5.
-#define EMIF_ASYNC_WCCR_WP0       0x10000000  // Wait Polarity for
-                                              // pad_wait_i[0].
-#define EMIF_ASYNC_WCCR_WP1       0x20000000  // Wait Polarity for
-                                              // pad_wait_i[1].
-#define EMIF_ASYNC_WCCR_WP2       0x40000000  // Wait Polarity for
-                                              // pad_wait_i[2].
-#define EMIF_ASYNC_WCCR_WP3       0x80000000  // Wait Polarity for
-                                              // pad_wait_i[3].
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SDRAM_CR register
-//
-//*****************************************************************************
-#define EMIF_SDRAM_CR_PAGESIGE_S  0
-#define EMIF_SDRAM_CR_PAGESIGE_M  0x7         // Page Size.
-#define EMIF_SDRAM_CR_EBANK       0x8         // External chip select setup.
-#define EMIF_SDRAM_CR_IBANK_S     4
-#define EMIF_SDRAM_CR_IBANK_M     0x70        // Internal Bank setup of SDRAM
-                                              // devices.
-#define EMIF_SDRAM_CR_BIT_11_9_LOCK  0x100       // Bits 11 to 9 are writable only
-                                              // if this bit is set.
-#define EMIF_SDRAM_CR_CL_S        9
-#define EMIF_SDRAM_CR_CL_M        0xE00       // CAS Latency.
-#define EMIF_SDRAM_CR_BIT_13_LOCK  0x1000      // Bits 13 is writable only if
-                                              // this bit is set.
-#define EMIF_SDRAM_CR_NM          0x4000      // Narrow Mode.
-#define EMIF_SDRAM_CR_BIT_25_17_LOCK  0x10000     // Bits 25 to 17 are writable only
-                                              // if this bit is set
-#define EMIF_SDRAM_CR_IBANK_POS   0x80000     // Internal bank position.
-#define EMIF_SDRAM_CR_ROWSIZE_S   20
-#define EMIF_SDRAM_CR_ROWSIZE_M   0x700000    // Row Size.
-#define EMIF_SDRAM_CR_PASR_S      23
-#define EMIF_SDRAM_CR_PASR_M      0x3800000   // Partial Array Self Refresh.
-#define EMIF_SDRAM_CR_PDWR        0x20000000  // Perform refreshes during Power
-                                              // Down.
-#define EMIF_SDRAM_CR_PD          0x40000000  // Power Down.
-#define EMIF_SDRAM_CR_SR          0x80000000  // Self Refresh.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SDRAM_RCR register
-//
-//*****************************************************************************
-#define EMIF_SDRAM_RCR_REFRESH_RATE_S  0
-#define EMIF_SDRAM_RCR_REFRESH_RATE_M  0x1FFF      // Refresh Rate.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ASYNC_CS2_CR register
-//
-//*****************************************************************************
-#define EMIF_ASYNC_CS2_CR_ASIZE_S  0
-#define EMIF_ASYNC_CS2_CR_ASIZE_M  0x3         // Asynchronous Memory Size.
-#define EMIF_ASYNC_CS2_CR_TA_S    2
-#define EMIF_ASYNC_CS2_CR_TA_M    0xC         // Turn Around cycles.
-#define EMIF_ASYNC_CS2_CR_R_HOLD_S  4
-#define EMIF_ASYNC_CS2_CR_R_HOLD_M  0x70        // Read Strobe Hold cycles.
-#define EMIF_ASYNC_CS2_CR_R_STROBE_S  7
-#define EMIF_ASYNC_CS2_CR_R_STROBE_M  0x1F80      // Read Strobe Duration cycles.
-#define EMIF_ASYNC_CS2_CR_R_SETUP_S  13
-#define EMIF_ASYNC_CS2_CR_R_SETUP_M  0x1E000     // Read Strobe Setup cycles.
-#define EMIF_ASYNC_CS2_CR_W_HOLD_S  17
-#define EMIF_ASYNC_CS2_CR_W_HOLD_M  0xE0000     // Write Strobe Hold cycles.
-#define EMIF_ASYNC_CS2_CR_W_STROBE_S  20
-#define EMIF_ASYNC_CS2_CR_W_STROBE_M  0x3F00000   // Write Strobe Duration cycles.
-#define EMIF_ASYNC_CS2_CR_W_SETUP_S  26
-#define EMIF_ASYNC_CS2_CR_W_SETUP_M  0x3C000000  // Write Strobe Setup cycles.
-#define EMIF_ASYNC_CS2_CR_EW      0x40000000  // Extend Wait mode.
-#define EMIF_ASYNC_CS2_CR_SS      0x80000000  // Select Strobe mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ASYNC_CS3_CR register
-//
-//*****************************************************************************
-#define EMIF_ASYNC_CS3_CR_ASIZE_S  0
-#define EMIF_ASYNC_CS3_CR_ASIZE_M  0x3         // Asynchronous Memory Size.
-#define EMIF_ASYNC_CS3_CR_TA_S    2
-#define EMIF_ASYNC_CS3_CR_TA_M    0xC         // Turn Around cycles.
-#define EMIF_ASYNC_CS3_CR_R_HOLD_S  4
-#define EMIF_ASYNC_CS3_CR_R_HOLD_M  0x70        // Read Strobe Hold cycles.
-#define EMIF_ASYNC_CS3_CR_R_STROBE_S  7
-#define EMIF_ASYNC_CS3_CR_R_STROBE_M  0x1F80      // Read Strobe Duration cycles.
-#define EMIF_ASYNC_CS3_CR_R_SETUP_S  13
-#define EMIF_ASYNC_CS3_CR_R_SETUP_M  0x1E000     // Read Strobe Setup cycles.
-#define EMIF_ASYNC_CS3_CR_W_HOLD_S  17
-#define EMIF_ASYNC_CS3_CR_W_HOLD_M  0xE0000     // Write Strobe Hold cycles.
-#define EMIF_ASYNC_CS3_CR_W_STROBE_S  20
-#define EMIF_ASYNC_CS3_CR_W_STROBE_M  0x3F00000   // Write Strobe Duration cycles.
-#define EMIF_ASYNC_CS3_CR_W_SETUP_S  26
-#define EMIF_ASYNC_CS3_CR_W_SETUP_M  0x3C000000  // Write Strobe Setup cycles.
-#define EMIF_ASYNC_CS3_CR_EW      0x40000000  // Extend Wait mode.
-#define EMIF_ASYNC_CS3_CR_SS      0x80000000  // Select Strobe mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ASYNC_CS4_CR register
-//
-//*****************************************************************************
-#define EMIF_ASYNC_CS4_CR_ASIZE_S  0
-#define EMIF_ASYNC_CS4_CR_ASIZE_M  0x3         // Asynchronous Memory Size.
-#define EMIF_ASYNC_CS4_CR_TA_S    2
-#define EMIF_ASYNC_CS4_CR_TA_M    0xC         // Turn Around cycles.
-#define EMIF_ASYNC_CS4_CR_R_HOLD_S  4
-#define EMIF_ASYNC_CS4_CR_R_HOLD_M  0x70        // Read Strobe Hold cycles.
-#define EMIF_ASYNC_CS4_CR_R_STROBE_S  7
-#define EMIF_ASYNC_CS4_CR_R_STROBE_M  0x1F80      // Read Strobe Duration cycles.
-#define EMIF_ASYNC_CS4_CR_R_SETUP_S  13
-#define EMIF_ASYNC_CS4_CR_R_SETUP_M  0x1E000     // Read Strobe Setup cycles.
-#define EMIF_ASYNC_CS4_CR_W_HOLD_S  17
-#define EMIF_ASYNC_CS4_CR_W_HOLD_M  0xE0000     // Write Strobe Hold cycles.
-#define EMIF_ASYNC_CS4_CR_W_STROBE_S  20
-#define EMIF_ASYNC_CS4_CR_W_STROBE_M  0x3F00000   // Write Strobe Duration cycles.
-#define EMIF_ASYNC_CS4_CR_W_SETUP_S  26
-#define EMIF_ASYNC_CS4_CR_W_SETUP_M  0x3C000000  // Write Strobe Setup cycles.
-#define EMIF_ASYNC_CS4_CR_EW      0x40000000  // Extend Wait mode.
-#define EMIF_ASYNC_CS4_CR_SS      0x80000000  // Select Strobe mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ASYNC_CS5_CR register
-//
-//*****************************************************************************
-#define EMIF_ASYNC_CS5_CR_ASIZE_S  0
-#define EMIF_ASYNC_CS5_CR_ASIZE_M  0x3         // Asynchronous Memory Size.
-#define EMIF_ASYNC_CS5_CR_TA_S    2
-#define EMIF_ASYNC_CS5_CR_TA_M    0xC         // Turn Around cycles.
-#define EMIF_ASYNC_CS5_CR_R_HOLD_S  4
-#define EMIF_ASYNC_CS5_CR_R_HOLD_M  0x70        // Read Strobe Hold cycles.
-#define EMIF_ASYNC_CS5_CR_R_STROBE_S  7
-#define EMIF_ASYNC_CS5_CR_R_STROBE_M  0x1F80      // Read Strobe Duration cycles.
-#define EMIF_ASYNC_CS5_CR_R_SETUP_S  13
-#define EMIF_ASYNC_CS5_CR_R_SETUP_M  0x1E000     // Read Strobe Setup cycles.
-#define EMIF_ASYNC_CS5_CR_W_HOLD_S  17
-#define EMIF_ASYNC_CS5_CR_W_HOLD_M  0xE0000     // Write Strobe Hold cycles.
-#define EMIF_ASYNC_CS5_CR_W_STROBE_S  20
-#define EMIF_ASYNC_CS5_CR_W_STROBE_M  0x3F00000   // Write Strobe Duration cycles.
-#define EMIF_ASYNC_CS5_CR_W_SETUP_S  26
-#define EMIF_ASYNC_CS5_CR_W_SETUP_M  0x3C000000  // Write Strobe Setup cycles.
-#define EMIF_ASYNC_CS5_CR_EW      0x40000000  // Extend Wait mode.
-#define EMIF_ASYNC_CS5_CR_SS      0x80000000  // Select Strobe mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SDRAM_TR register
-//
-//*****************************************************************************
-#define EMIF_SDRAM_TR_T_RRD_S     4
-#define EMIF_SDRAM_TR_T_RRD_M     0x70        // Activate to Activate timing for
-                                              // different bank.
-#define EMIF_SDRAM_TR_T_RC_S      8
-#define EMIF_SDRAM_TR_T_RC_M      0xF00       // Activate to Activate timing .
-#define EMIF_SDRAM_TR_T_RAS_S     12
-#define EMIF_SDRAM_TR_T_RAS_M     0xF000      // Activate to Precharge timing.
-#define EMIF_SDRAM_TR_T_WR_S      16
-#define EMIF_SDRAM_TR_T_WR_M      0x70000     // Last Write to Precharge timing.
-#define EMIF_SDRAM_TR_T_RCD_S     20
-#define EMIF_SDRAM_TR_T_RCD_M     0x700000    // Activate to Read/Write timing.
-#define EMIF_SDRAM_TR_T_RP_S      24
-#define EMIF_SDRAM_TR_T_RP_M      0x7000000   // Precharge to Activate/Refresh
-                                              // timing.
-#define EMIF_SDRAM_TR_T_RFC_S     27
-#define EMIF_SDRAM_TR_T_RFC_M     0xF8000000  // Refresh/Load Mode to
-                                              // Refresh/Activate timing
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TOTAL_SDRAM_AR register
-//
-//*****************************************************************************
-#define EMIF_TOTAL_SDRAM_AR_TOTAL_SDRAM_AR_S  0
-#define EMIF_TOTAL_SDRAM_AR_TOTAL_SDRAM_AR_M  0xFFFFFFFF  // Total number of VBUSP accesses
-                                              // to SDRAM.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TOTAL_SDRAM_ACTR register
-//
-//*****************************************************************************
-#define EMIF_TOTAL_SDRAM_ACTR_TOTAL_SDRAM_ACTR_S  0
-#define EMIF_TOTAL_SDRAM_ACTR_TOTAL_SDRAM_ACTR_M  0xFFFFFFFF  // Number of SDRAM accesses which
-                                              // required an activate command.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SDR_EXT_TMNG register
-//
-//*****************************************************************************
-#define EMIF_SDR_EXT_TMNG_T_XS_S  0
-#define EMIF_SDR_EXT_TMNG_T_XS_M  0x1F        // Self Refresh exit to new
-                                              // command timing.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the INT_RAW register
-//
-//*****************************************************************************
-#define EMIF_INT_RAW_AT           0x1         // Asynchronous Timeout.
-#define EMIF_INT_RAW_LT           0x2         // Line Trap.
-#define EMIF_INT_RAW_WR_S         2
-#define EMIF_INT_RAW_WR_M         0x3C        // Wait Rise.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the INT_MSK register
-//
-//*****************************************************************************
-#define EMIF_INT_MSK_AT_MASKED    0x1         // Asynchronous Timeout.
-#define EMIF_INT_MSK_LT_MASKED    0x2         // Line Trap.
-#define EMIF_INT_MSK_WR_MASKED_S  2
-#define EMIF_INT_MSK_WR_MASKED_M  0x3C        // Wait Rise.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the INT_MSK_SET register
-//
-//*****************************************************************************
-#define EMIF_INT_MSK_SET_AT_MASK_SET  0x1         // Asynchronous Timeout.
-#define EMIF_INT_MSK_SET_LT_MASK_SET  0x2         // Line Trap.
-#define EMIF_INT_MSK_SET_WR_MASK_SET_S  2
-#define EMIF_INT_MSK_SET_WR_MASK_SET_M  0x3C        // Wait Rise.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the INT_MSK_CLR register
-//
-//*****************************************************************************
-#define EMIF_INT_MSK_CLR_AT_MASK_CLR  0x1         // Asynchronous Timeout.
-#define EMIF_INT_MSK_CLR_LT_MASK_CLR  0x2         // Line Trap.
-#define EMIF_INT_MSK_CLR_WR_MASK_CLR_S  2
-#define EMIF_INT_MSK_CLR_WR_MASK_CLR_M  0x3C        // Wait Rise.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IO_CTRL register
-//
-//*****************************************************************************
-#define EMIF_IO_CTRL_IO_CTRL_S    0
-#define EMIF_IO_CTRL_IO_CTRL_M    0xFFFF      // VTP calibration control for the
-                                              // IOs
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IO_STAT register
-//
-//*****************************************************************************
-#define EMIF_IO_STAT_IO_STAT_S    0
-#define EMIF_IO_STAT_IO_STAT_M    0xFFFF      // VTP calibration status of the
-                                              // IOs
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MODEL_REL_NUM register
-//
-//*****************************************************************************
-#define EMIF_MODEL_REL_NUM_RELEASE_NUM_S  0
-#define EMIF_MODEL_REL_NUM_RELEASE_NUM_M  0xFF        // Release Number.
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_epwm.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_epwm.h
deleted file mode 100644
index f72a5bc5f3..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_epwm.h
+++ /dev/null
@@ -1,1248 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_epwm.h
-//
-// TITLE:   Definitions for the C28x EPWM registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_EPWM_H__
-#define __HW_EPWM_H__
-
-//*****************************************************************************
-//
-// The following are defines for the EPWM register offsets
-//
-//*****************************************************************************
-#define EPWM_O_TBCTL              0x0         // Time Base Control Register
-#define EPWM_O_TBCTL2             0x1         // Time Base Control Register 2
-#define EPWM_O_TBCTR              0x4         // Time Base Counter Register
-#define EPWM_O_TBSTS              0x5         // Time Base Status Register
-#define EPWM_O_CMPCTL             0x8         // Counter Compare Control
-                                              // Register
-#define EPWM_O_CMPCTL2            0x9         // Counter Compare Control
-                                              // Register 2
-#define EPWM_O_DBCTL              0xC         // Dead-Band Generator Control
-                                              // Register
-#define EPWM_O_DBCTL2             0xD         // Dead-Band Generator Control
-                                              // Register 2
-#define EPWM_O_AQCTL              0x10        // Action Qualifier Control
-                                              // Register
-#define EPWM_O_AQTSRCSEL          0x11        // Action Qualifier Trigger Event
-                                              // Source Select Register
-#define EPWM_O_PCCTL              0x14        // PWM Chopper Control Register
-#define EPWM_O_HRCNFG             0x20        // HRPWM Configuration Register
-#define EPWM_O_HRPWR              0x21        // HRPWM Power Register
-#define EPWM_O_HRMSTEP            0x26        // HRPWM MEP Step Register
-#define EPWM_O_HRPCTL             0x2D        // High Resolution Period Control
-                                              // Register
-#define EPWM_O_GLDCTL             0x34        // Global PWM Load Control
-                                              // Register
-#define EPWM_O_GLDCFG             0x35        // Global PWM Load Config Register
-#define EPWM_O_XLINK              0x38        // EPWMx Link Register
-#define EPWM_O_AQCTLA             0x40        // Action Qualifier Control
-                                              // Register For Output A
-#define EPWM_O_AQCTLA2            0x41        // Additional Action Qualifier
-                                              // Control Register For Output A
-#define EPWM_O_AQCTLB             0x42        // Action Qualifier Control
-                                              // Register For Output B
-#define EPWM_O_AQCTLB2            0x43        // Additional Action Qualifier
-                                              // Control Register For Output B
-#define EPWM_O_AQSFRC             0x47        // Action Qualifier Software Force
-                                              // Register
-#define EPWM_O_AQCSFRC            0x49        // Action Qualifier Continuous S/W
-                                              // Force Register
-#define EPWM_O_DBREDHR            0x50        // Dead-Band Generator Rising Edge
-                                              // Delay High Resolution Mirror
-                                              // Register
-#define EPWM_O_DBRED              0x51        // Dead-Band Generator Rising Edge
-                                              // Delay High Resolution Mirror
-                                              // Register
-#define EPWM_O_DBFEDHR            0x52        // Dead-Band Generator Falling
-                                              // Edge Delay High Resolution
-                                              // Register
-#define EPWM_O_DBFED              0x53        // Dead-Band Generator Falling
-                                              // Edge Delay Count Register
-#define EPWM_O_TBPHS              0x60        // Time Base Phase High
-#define EPWM_O_TBPRDHR            0x62        // Time Base Period High
-                                              // Resolution Register
-#define EPWM_O_TBPRD              0x63        // Time Base Period Register
-#define EPWM_O_CMPA               0x6A        // Counter Compare A Register
-#define EPWM_O_CMPB               0x6C        // Compare B Register
-#define EPWM_O_CMPC               0x6F        // Counter Compare C Register
-#define EPWM_O_CMPD               0x71        // Counter Compare D Register
-#define EPWM_O_GLDCTL2            0x74        // Global PWM Load Control
-                                              // Register 2
-#define EPWM_O_TZSEL              0x80        // Trip Zone Select Register
-#define EPWM_O_TZDCSEL            0x82        // Trip Zone Digital Comparator
-                                              // Select Register
-#define EPWM_O_TZCTL              0x84        // Trip Zone Control Register
-#define EPWM_O_TZCTL2             0x85        // Additional Trip Zone Control
-                                              // Register
-#define EPWM_O_TZCTLDCA           0x86        // Trip Zone Control Register
-                                              // Digital Compare A
-#define EPWM_O_TZCTLDCB           0x87        // Trip Zone Control Register
-                                              // Digital Compare B
-#define EPWM_O_TZEINT             0x8D        // Trip Zone Enable Interrupt
-                                              // Register
-#define EPWM_O_TZFLG              0x93        // Trip Zone Flag Register
-#define EPWM_O_TZCBCFLG           0x94        // Trip Zone CBC Flag Register
-#define EPWM_O_TZOSTFLG           0x95        // Trip Zone OST Flag Register
-#define EPWM_O_TZCLR              0x97        // Trip Zone Clear Register
-#define EPWM_O_TZCBCCLR           0x98        // Trip Zone CBC Clear Register
-#define EPWM_O_TZOSTCLR           0x99        // Trip Zone OST Clear Register
-#define EPWM_O_TZFRC              0x9B        // Trip Zone Force Register
-#define EPWM_O_ETSEL              0xA4        // Event Trigger Selection
-                                              // Register
-#define EPWM_O_ETPS               0xA6        // Event Trigger Pre-Scale
-                                              // Register
-#define EPWM_O_ETFLG              0xA8        // Event Trigger Flag Register
-#define EPWM_O_ETCLR              0xAA        // Event Trigger Clear Register
-#define EPWM_O_ETFRC              0xAC        // Event Trigger Force Register
-#define EPWM_O_ETINTPS            0xAE        // Event-Trigger Interrupt
-                                              // Pre-Scale Register
-#define EPWM_O_ETSOCPS            0xB0        // Event-Trigger SOC Pre-Scale
-                                              // Register
-#define EPWM_O_ETCNTINITCTL       0xB2        // Event-Trigger Counter
-                                              // Initialization Control
-                                              // Register
-#define EPWM_O_ETCNTINIT          0xB4        // Event-Trigger Counter
-                                              // Initialization Register
-#define EPWM_O_DCTRIPSEL          0xC0        // Digital Compare Trip Select
-                                              // Register
-#define EPWM_O_DCACTL             0xC3        // Digital Compare A Control
-                                              // Register
-#define EPWM_O_DCBCTL             0xC4        // Digital Compare B Control
-                                              // Register
-#define EPWM_O_DCFCTL             0xC7        // Digital Compare Filter Control
-                                              // Register
-#define EPWM_O_DCCAPCTL           0xC8        // Digital Compare Capture Control
-                                              // Register
-#define EPWM_O_DCFOFFSET          0xC9        // Digital Compare Filter Offset
-                                              // Register
-#define EPWM_O_DCFOFFSETCNT       0xCA        // Digital Compare Filter Offset
-                                              // Counter Register
-#define EPWM_O_DCFWINDOW          0xCB        // Digital Compare Filter Window
-                                              // Register
-#define EPWM_O_DCFWINDOWCNT       0xCC        // Digital Compare Filter Window
-                                              // Counter Register
-#define EPWM_O_DCCAP              0xCF        // Digital Compare Counter Capture
-                                              // Register
-#define EPWM_O_DCAHTRIPSEL        0xD2        // Digital Compare AH Trip Select
-#define EPWM_O_DCALTRIPSEL        0xD3        // Digital Compare AL Trip Select
-#define EPWM_O_DCBHTRIPSEL        0xD4        // Digital Compare BH Trip Select
-#define EPWM_O_DCBLTRIPSEL        0xD5        // Digital Compare BL Trip Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TBCTL register
-//
-//*****************************************************************************
-#define EPWM_TBCTL_CTRMODE_S      0
-#define EPWM_TBCTL_CTRMODE_M      0x3         // Counter Mode
-#define EPWM_TBCTL_PHSEN          0x4         // Phase Load Enable
-#define EPWM_TBCTL_PRDLD          0x8         // Active Period Load
-#define EPWM_TBCTL_SYNCOSEL_S     4
-#define EPWM_TBCTL_SYNCOSEL_M     0x30        // Sync Output Select
-#define EPWM_TBCTL_SWFSYNC        0x40        // Software Force Sync Pulse
-#define EPWM_TBCTL_HSPCLKDIV_S    7
-#define EPWM_TBCTL_HSPCLKDIV_M    0x380       // High Speed TBCLK Pre-scaler
-#define EPWM_TBCTL_CLKDIV_S       10
-#define EPWM_TBCTL_CLKDIV_M       0x1C00      // Time Base Clock Pre-scaler
-#define EPWM_TBCTL_PHSDIR         0x2000      // Phase Direction Bit
-#define EPWM_TBCTL_FREE_SOFT_S    14
-#define EPWM_TBCTL_FREE_SOFT_M    0xC000      // Emulation Mode Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TBCTL2 register
-//
-//*****************************************************************************
-#define EPWM_TBCTL2_SELFCLRTRREM  0x20        // Self clear Translator reminder
-#define EPWM_TBCTL2_OSHTSYNCMODE  0x40        // One shot sync mode
-#define EPWM_TBCTL2_OSHTSYNC      0x80        // One shot sync
-#define EPWM_TBCTL2_SYNCOSELX_S   12
-#define EPWM_TBCTL2_SYNCOSELX_M   0x3000      // Syncout selection
-#define EPWM_TBCTL2_PRDLDSYNC_S   14
-#define EPWM_TBCTL2_PRDLDSYNC_M   0xC000      // PRD Shadow to Active Load on
-                                              // SYNC Event
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TBCTR register
-//
-//*****************************************************************************
-#define EPWM_TBCTR_TBCTR_S        0
-#define EPWM_TBCTR_TBCTR_M        0xFFFF      // Counter Value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TBSTS register
-//
-//*****************************************************************************
-#define EPWM_TBSTS_CTRDIR         0x1         // Counter Direction Status
-#define EPWM_TBSTS_SYNCI          0x2         // External Input Sync Status
-#define EPWM_TBSTS_CTRMAX         0x4         // Counter Max Latched Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CMPCTL register
-//
-//*****************************************************************************
-#define EPWM_CMPCTL_LOADAMODE_S   0
-#define EPWM_CMPCTL_LOADAMODE_M   0x3         // Active Compare A Load
-#define EPWM_CMPCTL_LOADBMODE_S   2
-#define EPWM_CMPCTL_LOADBMODE_M   0xC         // Active Compare B Load
-#define EPWM_CMPCTL_SHDWAMODE     0x10        // Compare A Register Block
-                                              // Operating Mode
-#define EPWM_CMPCTL_SHDWBMODE     0x40        // Compare B Register Block
-                                              // Operating Mode
-#define EPWM_CMPCTL_SHDWAFULL     0x100       // Compare A Shadow Register Full
-                                              // Status
-#define EPWM_CMPCTL_SHDWBFULL     0x200       // Compare B Shadow Register Full
-                                              // Status
-#define EPWM_CMPCTL_LOADASYNC_S   10
-#define EPWM_CMPCTL_LOADASYNC_M   0xC00       // Active Compare A Load on SYNC
-#define EPWM_CMPCTL_LOADBSYNC_S   12
-#define EPWM_CMPCTL_LOADBSYNC_M   0x3000      // Active Compare B Load on SYNC
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CMPCTL2 register
-//
-//*****************************************************************************
-#define EPWM_CMPCTL2_LOADCMODE_S  0
-#define EPWM_CMPCTL2_LOADCMODE_M  0x3         // Active Compare C Load
-#define EPWM_CMPCTL2_LOADDMODE_S  2
-#define EPWM_CMPCTL2_LOADDMODE_M  0xC         // Active Compare D load
-#define EPWM_CMPCTL2_SHDWCMODE    0x10        // Compare C Block Operating Mode
-#define EPWM_CMPCTL2_SHDWDMODE    0x40        // Compare D Block Operating Mode
-#define EPWM_CMPCTL2_LOADCSYNC_S  10
-#define EPWM_CMPCTL2_LOADCSYNC_M  0xC00       // Active Compare C Load on SYNC
-#define EPWM_CMPCTL2_LOADDSYNC_S  12
-#define EPWM_CMPCTL2_LOADDSYNC_M  0x3000      // Active Compare D Load on SYNC
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DBCTL register
-//
-//*****************************************************************************
-#define EPWM_DBCTL_OUT_MODE_S     0
-#define EPWM_DBCTL_OUT_MODE_M     0x3         // Dead Band Output Mode Control
-#define EPWM_DBCTL_POLSEL_S       2
-#define EPWM_DBCTL_POLSEL_M       0xC         // Polarity Select Control
-#define EPWM_DBCTL_IN_MODE_S      4
-#define EPWM_DBCTL_IN_MODE_M      0x30        // Dead Band Input Select Mode
-                                              // Control
-#define EPWM_DBCTL_LOADREDMODE_S  6
-#define EPWM_DBCTL_LOADREDMODE_M  0xC0        // Active DBRED Load Mode
-#define EPWM_DBCTL_LOADFEDMODE_S  8
-#define EPWM_DBCTL_LOADFEDMODE_M  0x300       // Active DBFED Load Mode
-#define EPWM_DBCTL_SHDWDBREDMODE  0x400       // DBRED Block Operating Mode
-#define EPWM_DBCTL_SHDWDBFEDMODE  0x800       // DBFED Block Operating Mode
-#define EPWM_DBCTL_OUTSWAP_S      12
-#define EPWM_DBCTL_OUTSWAP_M      0x3000      // Dead Band Output Swap Control
-#define EPWM_DBCTL_DEDB_MODE      0x4000      // Dead Band Dual-Edge B Mode
-                                              // Control
-#define EPWM_DBCTL_HALFCYCLE      0x8000      // Half Cycle Clocking Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DBCTL2 register
-//
-//*****************************************************************************
-#define EPWM_DBCTL2_LOADDBCTLMODE_S  0
-#define EPWM_DBCTL2_LOADDBCTLMODE_M  0x3         // DBCTL Load from Shadow Mode
-                                              // Select
-#define EPWM_DBCTL2_SHDWDBCTLMODE  0x4         // DBCTL Load mode Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AQCTL register
-//
-//*****************************************************************************
-#define EPWM_AQCTL_LDAQAMODE_S    0
-#define EPWM_AQCTL_LDAQAMODE_M    0x3         // Action Qualifier A Load Select
-#define EPWM_AQCTL_LDAQBMODE_S    2
-#define EPWM_AQCTL_LDAQBMODE_M    0xC         // Action Qualifier B Load Select
-#define EPWM_AQCTL_SHDWAQAMODE    0x10        // Action Qualifer A Operating
-                                              // Mode
-#define EPWM_AQCTL_SHDWAQBMODE    0x40        // Action Qualifier B Operating
-                                              // Mode
-#define EPWM_AQCTL_LDAQASYNC_S    8
-#define EPWM_AQCTL_LDAQASYNC_M    0x300       // AQCTLA Register Load on SYNC
-#define EPWM_AQCTL_LDAQBSYNC_S    10
-#define EPWM_AQCTL_LDAQBSYNC_M    0xC00       // AQCTLB Register Load on SYNC
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AQTSRCSEL register
-//
-//*****************************************************************************
-#define EPWM_AQTSRCSEL_T1SEL_S    0
-#define EPWM_AQTSRCSEL_T1SEL_M    0xF         // T1 Event Source Select Bits
-#define EPWM_AQTSRCSEL_T2SEL_S    4
-#define EPWM_AQTSRCSEL_T2SEL_M    0xF0        // T2 Event Source Select Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PCCTL register
-//
-//*****************************************************************************
-#define EPWM_PCCTL_CHPEN          0x1         // PWM chopping enable
-#define EPWM_PCCTL_OSHTWTH_S      1
-#define EPWM_PCCTL_OSHTWTH_M      0x1E        // One-shot pulse width
-#define EPWM_PCCTL_CHPFREQ_S      5
-#define EPWM_PCCTL_CHPFREQ_M      0xE0        // Chopping clock frequency
-#define EPWM_PCCTL_CHPDUTY_S      8
-#define EPWM_PCCTL_CHPDUTY_M      0x700       // Chopping clock Duty cycle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HRCNFG register
-//
-//*****************************************************************************
-#define EPWM_HRCNFG_EDGMODE_S     0
-#define EPWM_HRCNFG_EDGMODE_M     0x3         // ePWMxA Edge Mode Select Bits
-#define EPWM_HRCNFG_CTLMODE       0x4         // ePWMxA Control Mode Select Bits
-#define EPWM_HRCNFG_HRLOAD_S      3
-#define EPWM_HRCNFG_HRLOAD_M      0x18        // ePWMxA Shadow Mode Select Bits
-#define EPWM_HRCNFG_SELOUTB       0x20        // EPWMB Output Selection Bit
-#define EPWM_HRCNFG_AUTOCONV      0x40        // Autoconversion Bit
-#define EPWM_HRCNFG_SWAPAB        0x80        // Swap EPWMA and EPWMB Outputs
-                                              // Bit
-#define EPWM_HRCNFG_EDGMODEB_S    8
-#define EPWM_HRCNFG_EDGMODEB_M    0x300       // ePWMxB Edge Mode Select Bits
-#define EPWM_HRCNFG_CTLMODEB      0x400       // ePWMxB Control Mode Select Bits
-#define EPWM_HRCNFG_HRLOADB_S     11
-#define EPWM_HRCNFG_HRLOADB_M     0x1800      // ePWMxB Shadow Mode Select Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HRPWR register
-//
-//*****************************************************************************
-#define EPWM_HRPWR_CALPWRON       0x8000      // Calibration Power On
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HRMSTEP register
-//
-//*****************************************************************************
-#define EPWM_HRMSTEP_HRMSTEP_S    0
-#define EPWM_HRMSTEP_HRMSTEP_M    0xFF        // High Resolution Micro Step
-                                              // Value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HRPCTL register
-//
-//*****************************************************************************
-#define EPWM_HRPCTL_HRPE          0x1         // High Resolution Period Enable
-#define EPWM_HRPCTL_TBPHSHRLOADE  0x4         // TBPHSHR Load Enable
-#define EPWM_HRPCTL_PWMSYNCSELX_S  4
-#define EPWM_HRPCTL_PWMSYNCSELX_M  0x70        // PWMSYNCX Source Select Bit:
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GLDCTL register
-//
-//*****************************************************************************
-#define EPWM_GLDCTL_GLD           0x1         // Global Shadow to Active load
-                                              // event control
-#define EPWM_GLDCTL_GLDMODE_S     1
-#define EPWM_GLDCTL_GLDMODE_M     0x1E        // Shadow to Active Global Load
-                                              // Pulse Selection
-#define EPWM_GLDCTL_OSHTMODE      0x20        // One Shot Load mode control bit
-#define EPWM_GLDCTL_GLDPRD_S      7
-#define EPWM_GLDCTL_GLDPRD_M      0x380       // Global Reload Strobe Period
-                                              // Select Register
-#define EPWM_GLDCTL_GLDCNT_S      10
-#define EPWM_GLDCTL_GLDCNT_M      0x1C00      // Global Reload Strobe Counter
-                                              // Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GLDCFG register
-//
-//*****************************************************************************
-#define EPWM_GLDCFG_TBPRD_TBPRDHR  0x1         // Global load event configuration
-                                              // for TBPRD:TBPRDHR
-#define EPWM_GLDCFG_CMPA_CMPAHR   0x2         // Global load event configuration
-                                              // for CMPA:CMPAHR
-#define EPWM_GLDCFG_CMPB_CMPBHR   0x4         // Global load event configuration
-                                              // for CMPB:CMPBHR
-#define EPWM_GLDCFG_CMPC          0x8         // Global load event configuration
-                                              // for CMPC
-#define EPWM_GLDCFG_CMPD          0x10        // Global load event configuration
-                                              // for CMPD
-#define EPWM_GLDCFG_DBRED_DBREDHR  0x20        // Global load event configuration
-                                              // for DBRED:DBREDHR
-#define EPWM_GLDCFG_DBFED_DBFEDHR  0x40        // Global load event configuration
-                                              // for DBFED:DBFEDHR
-#define EPWM_GLDCFG_DBCTL         0x80        // Global load event configuration
-                                              // for DBCTL
-#define EPWM_GLDCFG_AQCTLA_AQCTLA2  0x100       // Global load event configuration
-                                              // for AQCTLA/A2
-#define EPWM_GLDCFG_AQCTLB_AQCTLB2  0x200       // Global load event configuration
-                                              // for AQCTLB/B2
-#define EPWM_GLDCFG_AQCSFRC       0x400       // Global load event configuration
-                                              // for AQCSFRC
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPWMXLINK register
-//
-//*****************************************************************************
-#define EPWM_XLINK_TBPRDLINK_S    0
-#define EPWM_XLINK_TBPRDLINK_M    0xF         // TBPRD:TBPRDHR  Link
-#define EPWM_XLINK_CMPALINK_S     4
-#define EPWM_XLINK_CMPALINK_M     0xF0        // CMPA:CMPAHR Link
-#define EPWM_XLINK_CMPBLINK_S     8
-#define EPWM_XLINK_CMPBLINK_M     0xF00       // CMPB:CMPBHR Link
-#define EPWM_XLINK_CMPCLINK_S     12
-#define EPWM_XLINK_CMPCLINK_M     0xF000      // CMPC Link
-#define EPWM_XLINK_CMPDLINK_S     16
-#define EPWM_XLINK_CMPDLINK_M     0xF0000     // CMPD Link
-#define EPWM_XLINK_GLDCTL2LINK_S  28
-#define EPWM_XLINK_GLDCTL2LINK_M  0xF0000000  // GLDCTL2 Link
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AQCTLA register
-//
-//*****************************************************************************
-#define EPWM_AQCTLA_ZRO_S         0
-#define EPWM_AQCTLA_ZRO_M         0x3         // Action Counter = Zero
-#define EPWM_AQCTLA_PRD_S         2
-#define EPWM_AQCTLA_PRD_M         0xC         // Action Counter = Period
-#define EPWM_AQCTLA_CAU_S         4
-#define EPWM_AQCTLA_CAU_M         0x30        // Action Counter = Compare A Up
-#define EPWM_AQCTLA_CAD_S         6
-#define EPWM_AQCTLA_CAD_M         0xC0        // Action Counter = Compare A Down
-#define EPWM_AQCTLA_CBU_S         8
-#define EPWM_AQCTLA_CBU_M         0x300       // Action Counter = Compare B Up
-#define EPWM_AQCTLA_CBD_S         10
-#define EPWM_AQCTLA_CBD_M         0xC00       // Action Counter = Compare B Down
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AQCTLA2 register
-//
-//*****************************************************************************
-#define EPWM_AQCTLA2_T1U_S        0
-#define EPWM_AQCTLA2_T1U_M        0x3         // Action when event occurs on T1
-                                              // in UP-Count
-#define EPWM_AQCTLA2_T1D_S        2
-#define EPWM_AQCTLA2_T1D_M        0xC         // Action when event occurs on T1
-                                              // in DOWN-Count
-#define EPWM_AQCTLA2_T2U_S        4
-#define EPWM_AQCTLA2_T2U_M        0x30        // Action when event occurs on T2
-                                              // in UP-Count
-#define EPWM_AQCTLA2_T2D_S        6
-#define EPWM_AQCTLA2_T2D_M        0xC0        // Action when event occurs on T2
-                                              // in DOWN-Count
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AQCTLB register
-//
-//*****************************************************************************
-#define EPWM_AQCTLB_ZRO_S         0
-#define EPWM_AQCTLB_ZRO_M         0x3         // Action Counter = Zero
-#define EPWM_AQCTLB_PRD_S         2
-#define EPWM_AQCTLB_PRD_M         0xC         // Action Counter = Period
-#define EPWM_AQCTLB_CAU_S         4
-#define EPWM_AQCTLB_CAU_M         0x30        // Action Counter = Compare A Up
-#define EPWM_AQCTLB_CAD_S         6
-#define EPWM_AQCTLB_CAD_M         0xC0        // Action Counter = Compare A Down
-#define EPWM_AQCTLB_CBU_S         8
-#define EPWM_AQCTLB_CBU_M         0x300       // Action Counter = Compare B Up
-#define EPWM_AQCTLB_CBD_S         10
-#define EPWM_AQCTLB_CBD_M         0xC00       // Action Counter = Compare B Down
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AQCTLB2 register
-//
-//*****************************************************************************
-#define EPWM_AQCTLB2_T1U_S        0
-#define EPWM_AQCTLB2_T1U_M        0x3         // Action when event occurs on T1
-                                              // in UP-Count
-#define EPWM_AQCTLB2_T1D_S        2
-#define EPWM_AQCTLB2_T1D_M        0xC         // Action when event occurs on T1
-                                              // in DOWN-Count
-#define EPWM_AQCTLB2_T2U_S        4
-#define EPWM_AQCTLB2_T2U_M        0x30        // Action when event occurs on T2
-                                              // in UP-Count
-#define EPWM_AQCTLB2_T2D_S        6
-#define EPWM_AQCTLB2_T2D_M        0xC0        // Action when event occurs on T2
-                                              // in DOWN-Count
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AQSFRC register
-//
-//*****************************************************************************
-#define EPWM_AQSFRC_ACTSFA_S      0
-#define EPWM_AQSFRC_ACTSFA_M      0x3         // Action when One-time SW Force A
-                                              // Invoked
-#define EPWM_AQSFRC_OTSFA         0x4         // One-time SW Force A Output
-#define EPWM_AQSFRC_ACTSFB_S      3
-#define EPWM_AQSFRC_ACTSFB_M      0x18        // Action when One-time SW Force B
-                                              // Invoked
-#define EPWM_AQSFRC_OTSFB         0x20        // One-time SW Force A Output
-#define EPWM_AQSFRC_RLDCSF_S      6
-#define EPWM_AQSFRC_RLDCSF_M      0xC0        // Reload from Shadow Options
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AQCSFRC register
-//
-//*****************************************************************************
-#define EPWM_AQCSFRC_CSFA_S       0
-#define EPWM_AQCSFRC_CSFA_M       0x3         // Continuous Software Force on
-                                              // output A
-#define EPWM_AQCSFRC_CSFB_S       2
-#define EPWM_AQCSFRC_CSFB_M       0xC         // Continuous Software Force on
-                                              // output B
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DBREDHR register
-//
-//*****************************************************************************
-#define EPWM_DBREDHR_DBREDHR_S    9
-#define EPWM_DBREDHR_DBREDHR_M    0xFE00      // DBREDHR High Resolution Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DBRED register
-//
-//*****************************************************************************
-#define EPWM_DBRED_DBRED_S        0
-#define EPWM_DBRED_DBRED_M        0xFFFF      // Rising edge delay value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DBFEDHR register
-//
-//*****************************************************************************
-#define EPWM_DBFEDHR_DBFEDHR_S    9
-#define EPWM_DBFEDHR_DBFEDHR_M    0xFE00      // DBFEDHR High Resolution Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DBFED register
-//
-//*****************************************************************************
-#define EPWM_DBFED_DBFED_S        0
-#define EPWM_DBFED_DBFED_M        0xFFFF      // Falling edge delay value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TBPHS register
-//
-//*****************************************************************************
-#define EPWM_TBPHS_TBPHSHR_S      0
-#define EPWM_TBPHS_TBPHSHR_M      0xFFFF      // Extension Register for HRPWM
-                                              // Phase (8-bits)
-#define EPWM_TBPHS_TBPHS_S        16
-#define EPWM_TBPHS_TBPHS_M        0xFFFF0000  // Phase Offset Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TBPRDHR register
-//
-//*****************************************************************************
-#define EPWM_TBPRDHR_TBPRDHR_S    0
-#define EPWM_TBPRDHR_TBPRDHR_M    0xFFFF      // High res Time base period
-                                              // register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TBPRD register
-//
-//*****************************************************************************
-#define EPWM_TBPRD_TBPRD_S        0
-#define EPWM_TBPRD_TBPRD_M        0xFFFF      // Time base period register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CMPA register
-//
-//*****************************************************************************
-#define EPWM_CMPA_CMPAHR_S        0
-#define EPWM_CMPA_CMPAHR_M        0xFFFF      // Compare A HRPWM Extension
-                                              // Register
-#define EPWM_CMPA_CMPA_S          16
-#define EPWM_CMPA_CMPA_M          0xFFFF0000  // Compare A Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CMPB register
-//
-//*****************************************************************************
-#define EPWM_CMPB_CMPB_S          16
-#define EPWM_CMPB_CMPB_M          0xFFFF0000  // Compare B Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CMPC register
-//
-//*****************************************************************************
-#define EPWM_CMPC_CMPC_S          0
-#define EPWM_CMPC_CMPC_M          0xFFFF      // Compare C Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CMPD register
-//
-//*****************************************************************************
-#define EPWM_CMPD_CMPD_S          0
-#define EPWM_CMPD_CMPD_M          0xFFFF      // Compare D Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GLDCTL2 register
-//
-//*****************************************************************************
-#define EPWM_GLDCTL2_OSHTLD       0x1         // Enable reload event in one shot
-                                              // mode
-#define EPWM_GLDCTL2_GFRCLD       0x2         // Force reload event in one shot
-                                              // mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZSEL register
-//
-//*****************************************************************************
-#define EPWM_TZSEL_CBC1           0x1         // TZ1 CBC select
-#define EPWM_TZSEL_CBC2           0x2         // TZ2 CBC select
-#define EPWM_TZSEL_CBC3           0x4         // TZ3 CBC select
-#define EPWM_TZSEL_CBC4           0x8         // TZ4 CBC select
-#define EPWM_TZSEL_CBC5           0x10        // TZ5 CBC select
-#define EPWM_TZSEL_CBC6           0x20        // TZ6 CBC select
-#define EPWM_TZSEL_DCAEVT2        0x40        // DCAEVT2 CBC select
-#define EPWM_TZSEL_DCBEVT2        0x80        // DCBEVT2 CBC select
-#define EPWM_TZSEL_OSHT1          0x100       // One-shot TZ1 select
-#define EPWM_TZSEL_OSHT2          0x200       // One-shot TZ2 select
-#define EPWM_TZSEL_OSHT3          0x400       // One-shot TZ3 select
-#define EPWM_TZSEL_OSHT4          0x800       // One-shot TZ4 select
-#define EPWM_TZSEL_OSHT5          0x1000      // One-shot TZ5 select
-#define EPWM_TZSEL_OSHT6          0x2000      // One-shot TZ6 select
-#define EPWM_TZSEL_DCAEVT1        0x4000      // One-shot DCAEVT1 select
-#define EPWM_TZSEL_DCBEVT1        0x8000      // One-shot DCBEVT1 select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZDCSEL register
-//
-//*****************************************************************************
-#define EPWM_TZDCSEL_DCAEVT1_S    0
-#define EPWM_TZDCSEL_DCAEVT1_M    0x7         // Digital Compare Output A Event
-                                              // 1
-#define EPWM_TZDCSEL_DCAEVT2_S    3
-#define EPWM_TZDCSEL_DCAEVT2_M    0x38        // Digital Compare Output A Event
-                                              // 2
-#define EPWM_TZDCSEL_DCBEVT1_S    6
-#define EPWM_TZDCSEL_DCBEVT1_M    0x1C0       // Digital Compare Output B Event
-                                              // 1
-#define EPWM_TZDCSEL_DCBEVT2_S    9
-#define EPWM_TZDCSEL_DCBEVT2_M    0xE00       // Digital Compare Output B Event
-                                              // 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZCTL register
-//
-//*****************************************************************************
-#define EPWM_TZCTL_TZA_S          0
-#define EPWM_TZCTL_TZA_M          0x3         // TZ1 to TZ6 Trip Action On
-                                              // EPWMxA
-#define EPWM_TZCTL_TZB_S          2
-#define EPWM_TZCTL_TZB_M          0xC         // TZ1 to TZ6 Trip Action On
-                                              // EPWMxB
-#define EPWM_TZCTL_DCAEVT1_S      4
-#define EPWM_TZCTL_DCAEVT1_M      0x30        // EPWMxA action on DCAEVT1
-#define EPWM_TZCTL_DCAEVT2_S      6
-#define EPWM_TZCTL_DCAEVT2_M      0xC0        // EPWMxA action on DCAEVT2
-#define EPWM_TZCTL_DCBEVT1_S      8
-#define EPWM_TZCTL_DCBEVT1_M      0x300       // EPWMxB action on DCBEVT1
-#define EPWM_TZCTL_DCBEVT2_S      10
-#define EPWM_TZCTL_DCBEVT2_M      0xC00       // EPWMxB action on DCBEVT2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZCTL2 register
-//
-//*****************************************************************************
-#define EPWM_TZCTL2_TZAU_S        0
-#define EPWM_TZCTL2_TZAU_M        0x7         // Trip Action On EPWMxA while
-                                              // Count direction is UP
-#define EPWM_TZCTL2_TZAD_S        3
-#define EPWM_TZCTL2_TZAD_M        0x38        // Trip Action On EPWMxA while
-                                              // Count direction is DOWN
-#define EPWM_TZCTL2_TZBU_S        6
-#define EPWM_TZCTL2_TZBU_M        0x1C0       // Trip Action On EPWMxB while
-                                              // Count direction is UP
-#define EPWM_TZCTL2_TZBD_S        9
-#define EPWM_TZCTL2_TZBD_M        0xE00       // Trip Action On EPWMxB while
-                                              // Count direction is DOWN
-#define EPWM_TZCTL2_ETZE          0x8000      // TZCTL2 Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZCTLDCA register
-//
-//*****************************************************************************
-#define EPWM_TZCTLDCA_DCAEVT1U_S  0
-#define EPWM_TZCTLDCA_DCAEVT1U_M  0x7         // DCAEVT1 Action On EPWMxA while
-                                              // Count direction is UP
-#define EPWM_TZCTLDCA_DCAEVT1D_S  3
-#define EPWM_TZCTLDCA_DCAEVT1D_M  0x38        // DCAEVT1 Action On EPWMxA while
-                                              // Count direction is DOWN
-#define EPWM_TZCTLDCA_DCAEVT2U_S  6
-#define EPWM_TZCTLDCA_DCAEVT2U_M  0x1C0       // DCAEVT2 Action On EPWMxA while
-                                              // Count direction is UP
-#define EPWM_TZCTLDCA_DCAEVT2D_S  9
-#define EPWM_TZCTLDCA_DCAEVT2D_M  0xE00       // DCAEVT2 Action On EPWMxA while
-                                              // Count direction is DOWN
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZCTLDCB register
-//
-//*****************************************************************************
-#define EPWM_TZCTLDCB_DCBEVT1U_S  0
-#define EPWM_TZCTLDCB_DCBEVT1U_M  0x7         // DCBEVT1 Action On EPWMxA while
-                                              // Count direction is UP
-#define EPWM_TZCTLDCB_DCBEVT1D_S  3
-#define EPWM_TZCTLDCB_DCBEVT1D_M  0x38        // DCBEVT1 Action On EPWMxA while
-                                              // Count direction is DOWN
-#define EPWM_TZCTLDCB_DCBEVT2U_S  6
-#define EPWM_TZCTLDCB_DCBEVT2U_M  0x1C0       // DCBEVT2 Action On EPWMxA while
-                                              // Count direction is UP
-#define EPWM_TZCTLDCB_DCBEVT2D_S  9
-#define EPWM_TZCTLDCB_DCBEVT2D_M  0xE00       // DCBEVT2 Action On EPWMxA while
-                                              // Count direction is DOWN
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZEINT register
-//
-//*****************************************************************************
-#define EPWM_TZEINT_CBC           0x2         // Trip Zones Cycle By Cycle Int
-                                              // Enable
-#define EPWM_TZEINT_OST           0x4         // Trip Zones One Shot Int Enable
-#define EPWM_TZEINT_DCAEVT1       0x8         // Digital Compare A Event 1 Int
-                                              // Enable
-#define EPWM_TZEINT_DCAEVT2       0x10        // Digital Compare A Event 2 Int
-                                              // Enable
-#define EPWM_TZEINT_DCBEVT1       0x20        // Digital Compare B Event 1 Int
-                                              // Enable
-#define EPWM_TZEINT_DCBEVT2       0x40        // Digital Compare B Event 2 Int
-                                              // Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZFLG register
-//
-//*****************************************************************************
-#define EPWM_TZFLG_INT            0x1         // Global Int Status Flag
-#define EPWM_TZFLG_CBC            0x2         // Trip Zones Cycle By Cycle Flag
-#define EPWM_TZFLG_OST            0x4         // Trip Zones One Shot Flag
-#define EPWM_TZFLG_DCAEVT1        0x8         // Digital Compare A Event 1 Flag
-#define EPWM_TZFLG_DCAEVT2        0x10        // Digital Compare A Event 2 Flag
-#define EPWM_TZFLG_DCBEVT1        0x20        // Digital Compare B Event 1 Flag
-#define EPWM_TZFLG_DCBEVT2        0x40        // Digital Compare B Event 2 Flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZCBCFLG register
-//
-//*****************************************************************************
-#define EPWM_TZCBCFLG_CBC1        0x1         // Latched Status Flag for CBC1
-                                              // Trip Latch
-#define EPWM_TZCBCFLG_CBC2        0x2         // Latched Status Flag for CBC2
-                                              // Trip Latch
-#define EPWM_TZCBCFLG_CBC3        0x4         // Latched Status Flag for CBC3
-                                              // Trip Latch
-#define EPWM_TZCBCFLG_CBC4        0x8         // Latched Status Flag for CBC4
-                                              // Trip Latch
-#define EPWM_TZCBCFLG_CBC5        0x10        // Latched Status Flag for CBC5
-                                              // Trip Latch
-#define EPWM_TZCBCFLG_CBC6        0x20        // Latched Status Flag for CBC6
-                                              // Trip Latch
-#define EPWM_TZCBCFLG_DCAEVT2     0x40        // Latched Status Flag for Digital
-                                              // Compare Output A Event 2
-#define EPWM_TZCBCFLG_DCBEVT2     0x80        // Latched Status Flag for Digital
-                                              // Compare Output B Event 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZOSTFLG register
-//
-//*****************************************************************************
-#define EPWM_TZOSTFLG_OST1        0x1         // Latched Status Flag for OST1
-                                              // Trip Latch
-#define EPWM_TZOSTFLG_OST2        0x2         // Latched Status Flag for OST2
-                                              // Trip Latch
-#define EPWM_TZOSTFLG_OST3        0x4         // Latched Status Flag for OST3
-                                              // Trip Latch
-#define EPWM_TZOSTFLG_OST4        0x8         // Latched Status Flag for OST4
-                                              // Trip Latch
-#define EPWM_TZOSTFLG_OST5        0x10        // Latched Status Flag for OST5
-                                              // Trip Latch
-#define EPWM_TZOSTFLG_OST6        0x20        // Latched Status Flag for OST6
-                                              // Trip Latch
-#define EPWM_TZOSTFLG_DCAEVT2     0x40        // Latched Status Flag for Digital
-                                              // Compare Output A Event 1
-#define EPWM_TZOSTFLG_DCBEVT2     0x80        // Latched Status Flag for Digital
-                                              // Compare Output B Event 1
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZCLR register
-//
-//*****************************************************************************
-#define EPWM_TZCLR_INT            0x1         // Global Interrupt Clear Flag
-#define EPWM_TZCLR_CBC            0x2         // Cycle-By-Cycle Flag Clear
-#define EPWM_TZCLR_OST            0x4         // One-Shot Flag Clear
-#define EPWM_TZCLR_DCAEVT1        0x8         // DCAVET1 Flag Clear
-#define EPWM_TZCLR_DCAEVT2        0x10        // DCAEVT2 Flag Clear
-#define EPWM_TZCLR_DCBEVT1        0x20        // DCBEVT1 Flag Clear
-#define EPWM_TZCLR_DCBEVT2        0x40        // DCBEVT2 Flag Clear
-#define EPWM_TZCLR_CBCPULSE_S     14
-#define EPWM_TZCLR_CBCPULSE_M     0xC000      // Clear Pulse for CBC Trip Latch
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZCBCCLR register
-//
-//*****************************************************************************
-#define EPWM_TZCBCCLR_CBC1        0x1         // Clear Flag for Cycle-By-Cycle
-                                              // (CBC1) Trip Latch
-#define EPWM_TZCBCCLR_CBC2        0x2         // Clear Flag for Cycle-By-Cycle
-                                              // (CBC2) Trip Latch
-#define EPWM_TZCBCCLR_CBC3        0x4         // Clear Flag for Cycle-By-Cycle
-                                              // (CBC3) Trip Latch
-#define EPWM_TZCBCCLR_CBC4        0x8         // Clear Flag for Cycle-By-Cycle
-                                              // (CBC4) Trip Latch
-#define EPWM_TZCBCCLR_CBC5        0x10        // Clear Flag for Cycle-By-Cycle
-                                              // (CBC5) Trip Latch
-#define EPWM_TZCBCCLR_CBC6        0x20        // Clear Flag for Cycle-By-Cycle
-                                              // (CBC6) Trip Latch
-#define EPWM_TZCBCCLR_DCAEVT2     0x40        // Clear Flag forDCAEVT2 selected
-                                              // for CBC
-#define EPWM_TZCBCCLR_DCBEVT2     0x80        // Clear Flag for DCBEVT2 selected
-                                              // for CBC
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZOSTCLR register
-//
-//*****************************************************************************
-#define EPWM_TZOSTCLR_OST1        0x1         // Clear Flag for Oneshot (OST1)
-                                              // Trip Latch
-#define EPWM_TZOSTCLR_OST2        0x2         // Clear Flag for Oneshot (OST2)
-                                              // Trip Latch
-#define EPWM_TZOSTCLR_OST3        0x4         // Clear Flag for Oneshot (OST3)
-                                              // Trip Latch
-#define EPWM_TZOSTCLR_OST4        0x8         // Clear Flag for Oneshot (OST4)
-                                              // Trip Latch
-#define EPWM_TZOSTCLR_OST5        0x10        // Clear Flag for Oneshot (OST5)
-                                              // Trip Latch
-#define EPWM_TZOSTCLR_OST6        0x20        // Clear Flag for Oneshot (OST6)
-                                              // Trip Latch
-#define EPWM_TZOSTCLR_DCAEVT2     0x40        // Clear Flag for DCAEVT1 selected
-                                              // for OST
-#define EPWM_TZOSTCLR_DCBEVT2     0x80        // Clear Flag for DCBEVT1 selected
-                                              // for OST
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TZFRC register
-//
-//*****************************************************************************
-#define EPWM_TZFRC_CBC            0x2         // Force Trip Zones Cycle By Cycle
-                                              // Event
-#define EPWM_TZFRC_OST            0x4         // Force Trip Zones One Shot Event
-#define EPWM_TZFRC_DCAEVT1        0x8         // Force Digital Compare A Event 1
-#define EPWM_TZFRC_DCAEVT2        0x10        // Force Digital Compare A Event 2
-#define EPWM_TZFRC_DCBEVT1        0x20        // Force Digital Compare B Event 1
-#define EPWM_TZFRC_DCBEVT2        0x40        // Force Digital Compare B Event 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ETSEL register
-//
-//*****************************************************************************
-#define EPWM_ETSEL_INTSEL_S       0
-#define EPWM_ETSEL_INTSEL_M       0x7         // EPWMxINTn Select
-#define EPWM_ETSEL_INTEN          0x8         // EPWMxINTn Enable
-#define EPWM_ETSEL_SOCASELCMP     0x10        // EPWMxSOCA Compare Select
-#define EPWM_ETSEL_SOCBSELCMP     0x20        // EPWMxSOCB Compare Select
-#define EPWM_ETSEL_INTSELCMP      0x40        // EPWMxINT Compare Select
-#define EPWM_ETSEL_SOCASEL_S      8
-#define EPWM_ETSEL_SOCASEL_M      0x700       // Start of Conversion A Select
-#define EPWM_ETSEL_SOCAEN         0x800       // Start of Conversion A Enable
-#define EPWM_ETSEL_SOCBSEL_S      12
-#define EPWM_ETSEL_SOCBSEL_M      0x7000      // Start of Conversion B Select
-#define EPWM_ETSEL_SOCBEN         0x8000      // Start of Conversion B Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ETPS register
-//
-//*****************************************************************************
-#define EPWM_ETPS_INTPRD_S        0
-#define EPWM_ETPS_INTPRD_M        0x3         // EPWMxINTn Period Select
-#define EPWM_ETPS_INTCNT_S        2
-#define EPWM_ETPS_INTCNT_M        0xC         // EPWMxINTn Counter Register
-#define EPWM_ETPS_INTPSSEL        0x10        // EPWMxINTn Pre-Scale Selection
-                                              // Bits
-#define EPWM_ETPS_SOCPSSEL        0x20        // EPWMxSOC A/B  Pre-Scale
-                                              // Selection Bits
-#define EPWM_ETPS_SOCAPRD_S       8
-#define EPWM_ETPS_SOCAPRD_M       0x300       // EPWMxSOCA Period Select
-#define EPWM_ETPS_SOCACNT_S       10
-#define EPWM_ETPS_SOCACNT_M       0xC00       // EPWMxSOCA Counter Register
-#define EPWM_ETPS_SOCBPRD_S       12
-#define EPWM_ETPS_SOCBPRD_M       0x3000      // EPWMxSOCB Period Select
-#define EPWM_ETPS_SOCBCNT_S       14
-#define EPWM_ETPS_SOCBCNT_M       0xC000      // EPWMxSOCB Counter
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ETFLG register
-//
-//*****************************************************************************
-#define EPWM_ETFLG_INT            0x1         // EPWMxINTn Flag
-#define EPWM_ETFLG_SOCA           0x4         // EPWMxSOCA Flag
-#define EPWM_ETFLG_SOCB           0x8         // EPWMxSOCB Flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ETCLR register
-//
-//*****************************************************************************
-#define EPWM_ETCLR_INT            0x1         // EPWMxINTn Clear
-#define EPWM_ETCLR_SOCA           0x4         // EPWMxSOCA Clear
-#define EPWM_ETCLR_SOCB           0x8         // EPWMxSOCB Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ETFRC register
-//
-//*****************************************************************************
-#define EPWM_ETFRC_INT            0x1         // EPWMxINTn Force
-#define EPWM_ETFRC_SOCA           0x4         // EPWMxSOCA Force
-#define EPWM_ETFRC_SOCB           0x8         // EPWMxSOCB Force
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ETINTPS register
-//
-//*****************************************************************************
-#define EPWM_ETINTPS_INTPRD2_S    0
-#define EPWM_ETINTPS_INTPRD2_M    0xF         // EPWMxINTn Period Select
-#define EPWM_ETINTPS_INTCNT2_S    4
-#define EPWM_ETINTPS_INTCNT2_M    0xF0        // EPWMxINTn Counter Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ETSOCPS register
-//
-//*****************************************************************************
-#define EPWM_ETSOCPS_SOCAPRD2_S   0
-#define EPWM_ETSOCPS_SOCAPRD2_M   0xF         // EPWMxSOCA Period Select
-#define EPWM_ETSOCPS_SOCACNT2_S   4
-#define EPWM_ETSOCPS_SOCACNT2_M   0xF0        // EPWMxSOCA Counter Register
-#define EPWM_ETSOCPS_SOCBPRD2_S   8
-#define EPWM_ETSOCPS_SOCBPRD2_M   0xF00       // EPWMxSOCB Period Select
-#define EPWM_ETSOCPS_SOCBCNT2_S   12
-#define EPWM_ETSOCPS_SOCBCNT2_M   0xF000      // EPWMxSOCB Counter Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ETCNTINITCTL register
-//
-//*****************************************************************************
-#define EPWM_ETCNTINITCTL_INTINITFRC  0x400       // EPWMxINT Counter Initialization
-                                              // Force
-#define EPWM_ETCNTINITCTL_SOCAINITFRC  0x800       // EPWMxSOCA Counter
-                                              // Initialization Force
-#define EPWM_ETCNTINITCTL_SOCBINITFRC  0x1000      // EPWMxSOCB Counter
-                                              // Initialization Force
-#define EPWM_ETCNTINITCTL_INTINITEN  0x2000      // EPWMxINT Counter Initialization
-                                              // Enable
-#define EPWM_ETCNTINITCTL_SOCAINITEN  0x4000      // EPWMxSOCA Counter
-                                              // Initialization Enable
-#define EPWM_ETCNTINITCTL_SOCBINITEN  0x8000      // EPWMxSOCB Counter
-                                              // Initialization Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ETCNTINIT register
-//
-//*****************************************************************************
-#define EPWM_ETCNTINIT_INTINIT_S  0
-#define EPWM_ETCNTINIT_INTINIT_M  0xF         // EPWMxINT Counter Initialization
-                                              // Bits
-#define EPWM_ETCNTINIT_SOCAINIT_S  4
-#define EPWM_ETCNTINIT_SOCAINIT_M  0xF0        // EPWMxSOCA Counter
-                                              // Initialization Bits
-#define EPWM_ETCNTINIT_SOCBINIT_S  8
-#define EPWM_ETCNTINIT_SOCBINIT_M  0xF00       // EPWMxSOCB Counter
-                                              // Initialization Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCTRIPSEL register
-//
-//*****************************************************************************
-#define EPWM_DCTRIPSEL_DCAHCOMPSEL_S  0
-#define EPWM_DCTRIPSEL_DCAHCOMPSEL_M  0xF         // Digital Compare A High COMP
-                                              // Input Select
-#define EPWM_DCTRIPSEL_DCALCOMPSEL_S  4
-#define EPWM_DCTRIPSEL_DCALCOMPSEL_M  0xF0        // Digital Compare A Low COMP
-                                              // Input Select
-#define EPWM_DCTRIPSEL_DCBHCOMPSEL_S  8
-#define EPWM_DCTRIPSEL_DCBHCOMPSEL_M  0xF00       // Digital Compare B High COMP
-                                              // Input Select
-#define EPWM_DCTRIPSEL_DCBLCOMPSEL_S  12
-#define EPWM_DCTRIPSEL_DCBLCOMPSEL_M  0xF000      // Digital Compare B Low COMP
-                                              // Input Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCACTL register
-//
-//*****************************************************************************
-#define EPWM_DCACTL_EVT1SRCSEL    0x1         // DCAEVT1 Source Signal
-#define EPWM_DCACTL_EVT1FRCSYNCSEL  0x2         // DCAEVT1 Force Sync Signal
-#define EPWM_DCACTL_EVT1SOCE      0x4         // DCAEVT1 SOC Enable
-#define EPWM_DCACTL_EVT1SYNCE     0x8         // DCAEVT1 SYNC Enable
-#define EPWM_DCACTL_EVT2SRCSEL    0x100       // DCAEVT2 Source Signal
-#define EPWM_DCACTL_EVT2FRCSYNCSEL  0x200       // DCAEVT2 Force Sync Signal
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCBCTL register
-//
-//*****************************************************************************
-#define EPWM_DCBCTL_EVT1SRCSEL    0x1         // DCBEVT1 Source Signal
-#define EPWM_DCBCTL_EVT1FRCSYNCSEL  0x2         // DCBEVT1 Force Sync Signal
-#define EPWM_DCBCTL_EVT1SOCE      0x4         // DCBEVT1 SOC Enable
-#define EPWM_DCBCTL_EVT1SYNCE     0x8         // DCBEVT1 SYNC Enable
-#define EPWM_DCBCTL_EVT2SRCSEL    0x100       // DCBEVT2 Source Signal
-#define EPWM_DCBCTL_EVT2FRCSYNCSEL  0x200       // DCBEVT2 Force Sync Signal
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCFCTL register
-//
-//*****************************************************************************
-#define EPWM_DCFCTL_SRCSEL_S      0
-#define EPWM_DCFCTL_SRCSEL_M      0x3         // Filter Block Signal Source
-                                              // Select
-#define EPWM_DCFCTL_BLANKE        0x4         // Blanking Enable/Disable
-#define EPWM_DCFCTL_BLANKINV      0x8         // Blanking Window Inversion
-#define EPWM_DCFCTL_PULSESEL_S    4
-#define EPWM_DCFCTL_PULSESEL_M    0x30        // Pulse Select for Blanking &
-                                              // Capture Alignment
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCCAPCTL register
-//
-//*****************************************************************************
-#define EPWM_DCCAPCTL_CAPE        0x1         // Counter Capture Enable
-#define EPWM_DCCAPCTL_SHDWMODE    0x2         // Counter Capture Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCFOFFSET register
-//
-//*****************************************************************************
-#define EPWM_DCFOFFSET_DCFOFFSET_S  0
-#define EPWM_DCFOFFSET_DCFOFFSET_M  0xFFFF      // Blanking Offset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCFOFFSETCNT register
-//
-//*****************************************************************************
-#define EPWM_DCFOFFSETCNT_DCFOFFSETCNT_S  0
-#define EPWM_DCFOFFSETCNT_DCFOFFSETCNT_M  0xFFFF      // Blanking Offset Counter
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCFWINDOW register
-//
-//*****************************************************************************
-#define EPWM_DCFWINDOW_DCFWINDOW_S  0
-#define EPWM_DCFWINDOW_DCFWINDOW_M  0xFFFF      // Digital Compare Filter Window
-                                              // Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCFWINDOWCNT register
-//
-//*****************************************************************************
-#define EPWM_DCFWINDOWCNT_DCFWINDOWCNT_S  0
-#define EPWM_DCFWINDOWCNT_DCFWINDOWCNT_M  0xFFFF      // Digital Compare Filter Window
-                                              // Counter Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCCAP register
-//
-//*****************************************************************************
-#define EPWM_DCCAP_DCCAP_S        0
-#define EPWM_DCCAP_DCCAP_M        0xFFFF      // Time Base Counter Capture
-                                              // Register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCAHTRIPSEL register
-//
-//*****************************************************************************
-#define EPWM_DCAHTRIPSEL_TRIPINPUT1  0x1         // Trip Input 1 Select to DCAH Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT2  0x2         // Trip Input 2 Select to DCAH Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT3  0x4         // Trip Input 3 Select to DCAH Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT4  0x8         // Trip Input 4 Select to DCAH Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT5  0x10        // Trip Input 5 Select to DCAH Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT6  0x20        // Trip Input 6 Select to DCAH Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT7  0x40        // Trip Input 7 Select to DCAH Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT8  0x80        // Trip Input 8 Select to DCAH Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT9  0x100       // Trip Input 9 Select to DCAH Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT10  0x200       // Trip Input 10 Select to DCAH
-                                              // Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT11  0x400       // Trip Input 11 Select to DCAH
-                                              // Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT12  0x800       // Trip Input 12 Select to DCAH
-                                              // Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT13  0x1000      // Trip Input 13 Select to DCAH
-                                              // Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT14  0x2000      // Trip Input 14 Select to DCAH
-                                              // Mux
-#define EPWM_DCAHTRIPSEL_TRIPINPUT15  0x4000      // Trip Input 15 Select to DCAH
-                                              // Mux
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCALTRIPSEL register
-//
-//*****************************************************************************
-#define EPWM_DCALTRIPSEL_TRIPINPUT1  0x1         // Trip Input 1 Select to DCAL Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT2  0x2         // Trip Input 2 Select to DCAL Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT3  0x4         // Trip Input 3 Select to DCAL Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT4  0x8         // Trip Input 4 Select to DCAL Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT5  0x10        // Trip Input 5 Select to DCAL Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT6  0x20        // Trip Input 6 Select to DCAL Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT7  0x40        // Trip Input 7 Select to DCAL Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT8  0x80        // Trip Input 8 Select to DCAL Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT9  0x100       // Trip Input 9 Select to DCAL Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT10  0x200       // Trip Input 10 Select to DCAL
-                                              // Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT11  0x400       // Trip Input 11 Select to DCAL
-                                              // Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT12  0x800       // Trip Input 12 Select to DCAL
-                                              // Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT13  0x1000      // Trip Input 13 Select to DCAL
-                                              // Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT14  0x2000      // Trip Input 14 Select to DCAL
-                                              // Mux
-#define EPWM_DCALTRIPSEL_TRIPINPUT15  0x4000      // Trip Input 15 Select to DCAL
-                                              // Mux
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCBHTRIPSEL register
-//
-//*****************************************************************************
-#define EPWM_DCBHTRIPSEL_TRIPINPUT1  0x1         // Trip Input 1 Select to DCBH Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT2  0x2         // Trip Input 2 Select to DCBH Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT3  0x4         // Trip Input 3 Select to DCBH Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT4  0x8         // Trip Input 4 Select to DCBH Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT5  0x10        // Trip Input 5 Select to DCBH Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT6  0x20        // Trip Input 6 Select to DCBH Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT7  0x40        // Trip Input 7 Select to DCBH Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT8  0x80        // Trip Input 8 Select to DCBH Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT9  0x100       // Trip Input 9 Select to DCBH Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT10  0x200       // Trip Input 10 Select to DCBH
-                                              // Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT11  0x400       // Trip Input 11 Select to DCBH
-                                              // Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT12  0x800       // Trip Input 12 Select to DCBH
-                                              // Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT13  0x1000      // Trip Input 13 Select to DCBH
-                                              // Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT14  0x2000      // Trip Input 14 Select to DCBH
-                                              // Mux
-#define EPWM_DCBHTRIPSEL_TRIPINPUT15  0x4000      // Trip Input 15 Select to DCBH
-                                              // Mux
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the DCBLTRIPSEL register
-//
-//*****************************************************************************
-#define EPWM_DCBLTRIPSEL_TRIPINPUT1  0x1         // Trip Input 1 Select to DCBL Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT2  0x2         // Trip Input 2 Select to DCBL Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT3  0x4         // Trip Input 3 Select to DCBL Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT4  0x8         // Trip Input 4 Select to DCBL Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT5  0x10        // Trip Input 5 Select to DCBL Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT6  0x20        // Trip Input 6 Select to DCBL Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT7  0x40        // Trip Input 7 Select to DCBL Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT8  0x80        // Trip Input 8 Select to DCBL Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT9  0x100       // Trip Input 9 Select to DCBL Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT10  0x200       // Trip Input 10 Select to DCBL
-                                              // Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT11  0x400       // Trip Input 11 Select to DCBL
-                                              // Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT12  0x800       // Trip Input 12 Select to DCBL
-                                              // Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT13  0x1000      // Trip Input 13 Select to DCBL
-                                              // Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT14  0x2000      // Trip Input 14 Select to DCBL
-                                              // Mux
-#define EPWM_DCBLTRIPSEL_TRIPINPUT15  0x4000      // Trip Input 15 Select to DCBL
-                                              // Mux
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_eqep.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_eqep.h
deleted file mode 100644
index 6d5f37b5eb..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_eqep.h
+++ /dev/null
@@ -1,391 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_eqep.h
-//
-// TITLE:   Definitions for the C28x EQEP registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_EQEP_H__
-#define __HW_EQEP_H__
-
-//*****************************************************************************
-//
-// The following are defines for the EQEP register offsets
-//
-//*****************************************************************************
-#define EQEP_O_QPOSCNT            0x0         // Position Counter
-#define EQEP_O_QPOSINIT           0x2         // Position Counter Init
-#define EQEP_O_QPOSMAX            0x4         // Maximum Position Count
-#define EQEP_O_QPOSCMP            0x6         // Position Compare
-#define EQEP_O_QPOSILAT           0x8         // Index Position Latch
-#define EQEP_O_QPOSSLAT           0xA         // Strobe Position Latch
-#define EQEP_O_QPOSLAT            0xC         // Position Latch
-#define EQEP_O_QUTMR              0xE         // QEP Unit Timer
-#define EQEP_O_QUPRD              0x10        // QEP Unit Period
-#define EQEP_O_QWDTMR             0x12        // QEP Watchdog Timer
-#define EQEP_O_QWDPRD             0x13        // QEP Watchdog Period
-#define EQEP_O_QDECCTL            0x14        // Quadrature Decoder Control
-#define EQEP_O_QEPCTL             0x15        // QEP Control
-#define EQEP_O_QCAPCTL            0x16        // Qaudrature Capture Control
-#define EQEP_O_QPOSCTL            0x17        // Position Compare Control
-#define EQEP_O_QEINT              0x18        // QEP Interrupt Control
-#define EQEP_O_QFLG               0x19        // QEP Interrupt Flag
-#define EQEP_O_QCLR               0x1A        // QEP Interrupt Clear
-#define EQEP_O_QFRC               0x1B        // QEP Interrupt Force
-#define EQEP_O_QEPSTS             0x1C        // QEP Status
-#define EQEP_O_QCTMR              0x1D        // QEP Capture Timer
-#define EQEP_O_QCPRD              0x1E        // QEP Capture Period
-#define EQEP_O_QCTMRLAT           0x1F        // QEP Capture Latch
-#define EQEP_O_QCPRDLAT           0x20        // QEP Capture Period Latch
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QPOSCNT register
-//
-//*****************************************************************************
-#define EQEP_QPOSCNT_QPOSCNT_S    0
-#define EQEP_QPOSCNT_QPOSCNT_M    0xFFFFFFFF  // Position Counter
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QPOSINIT register
-//
-//*****************************************************************************
-#define EQEP_QPOSINIT_QPOSINIT_S  0
-#define EQEP_QPOSINIT_QPOSINIT_M  0xFFFFFFFF  // Position Counter Init
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QPOSMAX register
-//
-//*****************************************************************************
-#define EQEP_QPOSMAX_QPOSMAX_S    0
-#define EQEP_QPOSMAX_QPOSMAX_M    0xFFFFFFFF  // Maximum Position Count
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QPOSCMP register
-//
-//*****************************************************************************
-#define EQEP_QPOSCMP_QPOSCMP_S    0
-#define EQEP_QPOSCMP_QPOSCMP_M    0xFFFFFFFF  // Position Compare
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QPOSILAT register
-//
-//*****************************************************************************
-#define EQEP_QPOSILAT_QPOSILAT_S  0
-#define EQEP_QPOSILAT_QPOSILAT_M  0xFFFFFFFF  // Index Position Latch
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QPOSSLAT register
-//
-//*****************************************************************************
-#define EQEP_QPOSSLAT_QPOSSLAT_S  0
-#define EQEP_QPOSSLAT_QPOSSLAT_M  0xFFFFFFFF  // Strobe Position Latch
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QPOSLAT register
-//
-//*****************************************************************************
-#define EQEP_QPOSLAT_QPOSLAT_S    0
-#define EQEP_QPOSLAT_QPOSLAT_M    0xFFFFFFFF  // Position Latch
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QUTMR register
-//
-//*****************************************************************************
-#define EQEP_QUTMR_QUTMR_S        0
-#define EQEP_QUTMR_QUTMR_M        0xFFFFFFFF  // QEP Unit Timer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QUPRD register
-//
-//*****************************************************************************
-#define EQEP_QUPRD_QUPRD_S        0
-#define EQEP_QUPRD_QUPRD_M        0xFFFFFFFF  // QEP Unit Period
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QWDTMR register
-//
-//*****************************************************************************
-#define EQEP_QWDTMR_QWDTMR_S      0
-#define EQEP_QWDTMR_QWDTMR_M      0xFFFF      // QEP Watchdog Timer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QWDPRD register
-//
-//*****************************************************************************
-#define EQEP_QWDPRD_QWDPRD_S      0
-#define EQEP_QWDPRD_QWDPRD_M      0xFFFF      // QEP Watchdog Period
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QDECCTL register
-//
-//*****************************************************************************
-#define EQEP_QDECCTL_QSP          0x20        // QEPS input polarity
-#define EQEP_QDECCTL_QIP          0x40        // QEPI input polarity
-#define EQEP_QDECCTL_QBP          0x80        // QEPB input polarity
-#define EQEP_QDECCTL_QAP          0x100       // QEPA input polarity
-#define EQEP_QDECCTL_IGATE        0x200       // Index pulse gating option
-#define EQEP_QDECCTL_SWAP         0x400       // CLK/DIR Signal Source for
-                                              // Position Counter
-#define EQEP_QDECCTL_XCR          0x800       // External Clock Rate
-#define EQEP_QDECCTL_SPSEL        0x1000      // Sync output pin selection
-#define EQEP_QDECCTL_SOEN         0x2000      // Sync output-enable
-#define EQEP_QDECCTL_QSRC_S       14
-#define EQEP_QDECCTL_QSRC_M       0xC000      // Position-counter source
-                                              // selection
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEPCTL register
-//
-//*****************************************************************************
-#define EQEP_QEPCTL_WDE           0x1         // QEP watchdog enable
-#define EQEP_QEPCTL_UTE           0x2         // QEP unit timer enable
-#define EQEP_QEPCTL_QCLM          0x4         // QEP capture latch mode
-#define EQEP_QEPCTL_QPEN          0x8         // Quadrature postotion counter
-                                              // enable
-#define EQEP_QEPCTL_IEL_S         4
-#define EQEP_QEPCTL_IEL_M         0x30        // Index event latch
-#define EQEP_QEPCTL_SEL           0x40        // Strobe event latch
-#define EQEP_QEPCTL_SWI           0x80        // Software init position counter
-#define EQEP_QEPCTL_IEI_S         8
-#define EQEP_QEPCTL_IEI_M         0x300       // Index event init of position
-                                              // count
-#define EQEP_QEPCTL_SEI_S         10
-#define EQEP_QEPCTL_SEI_M         0xC00       // Strobe event init
-#define EQEP_QEPCTL_PCRM_S        12
-#define EQEP_QEPCTL_PCRM_M        0x3000      // Postion counter reset
-#define EQEP_QEPCTL_FREE_SOFT_S   14
-#define EQEP_QEPCTL_FREE_SOFT_M   0xC000      // Emulation mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QCAPCTL register
-//
-//*****************************************************************************
-#define EQEP_QCAPCTL_UPPS_S       0
-#define EQEP_QCAPCTL_UPPS_M       0xF         // Unit position event prescaler
-#define EQEP_QCAPCTL_CCPS_S       4
-#define EQEP_QCAPCTL_CCPS_M       0x70        // eQEP capture timer clock
-                                              // prescaler
-#define EQEP_QCAPCTL_CEN          0x8000      // Enable eQEP capture
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QPOSCTL register
-//
-//*****************************************************************************
-#define EQEP_QPOSCTL_PCSPW_S      0
-#define EQEP_QPOSCTL_PCSPW_M      0xFFF       // Position compare sync pulse
-                                              // width
-#define EQEP_QPOSCTL_PCE          0x1000      // Position compare enable/disable
-#define EQEP_QPOSCTL_PCPOL        0x2000      // Polarity of sync output
-#define EQEP_QPOSCTL_PCLOAD       0x4000      // Position compare of shadow load
-#define EQEP_QPOSCTL_PCSHDW       0x8000      // Position compare of shadow
-                                              // enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEINT register
-//
-//*****************************************************************************
-#define EQEP_QEINT_PCE            0x2         // Position counter error
-                                              // interrupt enable
-#define EQEP_QEINT_QPE            0x4         // Quadrature phase error
-                                              // interrupt enable
-#define EQEP_QEINT_QDC            0x8         // Quadrature direction change
-                                              // interrupt enable
-#define EQEP_QEINT_WTO            0x10        // Watchdog time out interrupt
-                                              // enable
-#define EQEP_QEINT_PCU            0x20        // Position counter underflow
-                                              // interrupt enable
-#define EQEP_QEINT_PCO            0x40        // Position counter overflow
-                                              // interrupt enable
-#define EQEP_QEINT_PCR            0x80        // Position-compare ready
-                                              // interrupt enable
-#define EQEP_QEINT_PCM            0x100       // Position-compare match
-                                              // interrupt enable
-#define EQEP_QEINT_SEL            0x200       // Strobe event latch interrupt
-                                              // enable
-#define EQEP_QEINT_IEL            0x400       // Index event latch interrupt
-                                              // enable
-#define EQEP_QEINT_UTO            0x800       // Unit time out interrupt enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QFLG register
-//
-//*****************************************************************************
-#define EQEP_QFLG_INT             0x1         // Global interrupt status flag
-#define EQEP_QFLG_PCE             0x2         // Position counter error
-                                              // interrupt flag
-#define EQEP_QFLG_PHE             0x4         // Quadrature phase error
-                                              // interrupt flag
-#define EQEP_QFLG_QDC             0x8         // Quadrature direction change
-                                              // interrupt flag
-#define EQEP_QFLG_WTO             0x10        // Watchdog timeout interrupt flag
-#define EQEP_QFLG_PCU             0x20        // Position counter underflow
-                                              // interrupt flag
-#define EQEP_QFLG_PCO             0x40        // Position counter overflow
-                                              // interrupt flag
-#define EQEP_QFLG_PCR             0x80        // Position-compare ready
-                                              // interrupt flag
-#define EQEP_QFLG_PCM             0x100       // eQEP compare match event
-                                              // interrupt flag
-#define EQEP_QFLG_SEL             0x200       // Strobe event latch interrupt
-                                              // flag
-#define EQEP_QFLG_IEL             0x400       // Index event latch interrupt
-                                              // flag
-#define EQEP_QFLG_UTO             0x800       // Unit time out interrupt flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QCLR register
-//
-//*****************************************************************************
-#define EQEP_QCLR_INT             0x1         // Global interrupt clear flag
-#define EQEP_QCLR_PCE             0x2         // Clear position counter error
-                                              // interrupt flag
-#define EQEP_QCLR_PHE             0x4         // Clear quadrature phase error
-                                              // interrupt flag
-#define EQEP_QCLR_QDC             0x8         // Clear quadrature direction
-                                              // change interrupt flag
-#define EQEP_QCLR_WTO             0x10        // Clear watchdog timeout
-                                              // interrupt flag
-#define EQEP_QCLR_PCU             0x20        // Clear position counter
-                                              // underflow interrupt flag
-#define EQEP_QCLR_PCO             0x40        // Clear position counter overflow
-                                              // interrupt flag
-#define EQEP_QCLR_PCR             0x80        // Clear position-compare ready
-                                              // interrupt flag
-#define EQEP_QCLR_PCM             0x100       // Clear eQEP compare match event
-                                              // interrupt flag
-#define EQEP_QCLR_SEL             0x200       // Clear strobe event latch
-                                              // interrupt flag
-#define EQEP_QCLR_IEL             0x400       // Clear index event latch
-                                              // interrupt flag
-#define EQEP_QCLR_UTO             0x800       // Clear unit time out interrupt
-                                              // flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QFRC register
-//
-//*****************************************************************************
-#define EQEP_QFRC_PCE             0x2         // Force position counter error
-                                              // interrupt
-#define EQEP_QFRC_PHE             0x4         // Force quadrature phase error
-                                              // interrupt
-#define EQEP_QFRC_QDC             0x8         // Force quadrature direction
-                                              // change interrupt
-#define EQEP_QFRC_WTO             0x10        // Force watchdog time out
-                                              // interrupt
-#define EQEP_QFRC_PCU             0x20        // Force position counter
-                                              // underflow interrupt
-#define EQEP_QFRC_PCO             0x40        // Force position counter overflow
-                                              // interrupt
-#define EQEP_QFRC_PCR             0x80        // Force position-compare ready
-                                              // interrupt
-#define EQEP_QFRC_PCM             0x100       // Force position-compare match
-                                              // interrupt
-#define EQEP_QFRC_SEL             0x200       // Force strobe event latch
-                                              // interrupt
-#define EQEP_QFRC_IEL             0x400       // Force index event latch
-                                              // interrupt
-#define EQEP_QFRC_UTO             0x800       // Force unit time out interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEPSTS register
-//
-//*****************************************************************************
-#define EQEP_QEPSTS_PCEF          0x1         // Position counter error flag.
-#define EQEP_QEPSTS_FIMF          0x2         // First index marker flag
-#define EQEP_QEPSTS_CDEF          0x4         // Capture direction error flag
-#define EQEP_QEPSTS_COEF          0x8         // Capture overflow error flag
-#define EQEP_QEPSTS_QDLF          0x10        // eQEP direction latch flag
-#define EQEP_QEPSTS_QDF           0x20        // Quadrature direction flag
-#define EQEP_QEPSTS_FIDF          0x40        // The first index marker
-#define EQEP_QEPSTS_UPEVNT        0x80        // Unit position event flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QCTMR register
-//
-//*****************************************************************************
-#define EQEP_QCTMR_QCTMR_S        0
-#define EQEP_QCTMR_QCTMR_M        0xFFFF      // This register provides time
-                                              // base for edge capture unit.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QCPRD register
-//
-//*****************************************************************************
-#define EQEP_QCPRD_QCPRD_S        0
-#define EQEP_QCPRD_QCPRD_M        0xFFFF      // Period count value between 
-                                              // eQEP position events
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QCTMRLAT register
-//
-//*****************************************************************************
-#define EQEP_QCTMRLAT_QCTMRLAT_S  0
-#define EQEP_QCTMRLAT_QCTMRLAT_M  0xFFFF      // The eQEP capture timer latch
-                                              // value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QCPRDLAT register
-//
-//*****************************************************************************
-#define EQEP_QCPRDLAT_QCPRDLAT_S  0
-#define EQEP_QCPRDLAT_QCPRDLAT_M  0xFFFF      // eQEP capture period latch value
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_gpio.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_gpio.h
deleted file mode 100644
index 63c4f62a1e..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_gpio.h
+++ /dev/null
@@ -1,5662 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_gpio.h
-//
-// TITLE:   Definitions for the C28x GPIO registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_GPIO_H__
-#define __HW_GPIO_H__
-
-//*****************************************************************************
-//
-// The following are defines for the GPIO register offsets
-//
-//*****************************************************************************
-#define GPIO_O_GPACTRL            0x0         // GPIO A Qualification Sampling
-                                              // Period Control (GPIO0 to 31)
-#define GPIO_O_GPAQSEL1           0x2         // GPIO A Qualifier Select 1
-                                              // Register (GPIO0 to 15)
-#define GPIO_O_GPAQSEL2           0x4         // GPIO A Qualifier Select 2
-                                              // Register (GPIO16 to 31)
-#define GPIO_O_GPAMUX1            0x6         // GPIO A Mux 1 Register (GPIO0 to
-                                              // 15)
-#define GPIO_O_GPAMUX2            0x8         // GPIO A Mux 2 Register (GPIO16
-                                              // to 31)
-#define GPIO_O_GPADIR             0xA         // GPIO A Direction Register
-                                              // (GPIO0 to 31)
-#define GPIO_O_GPAPUD             0xC         // GPIO A Pull Up Disable Register
-                                              // (GPIO0 to 31)
-#define GPIO_O_GPAINV             0x10        // GPIO A Input Polarity Invert
-                                              // Registers (GPIO0 to 31)
-#define GPIO_O_GPAODR             0x12        // GPIO A Open Drain Output
-                                              // Register (GPIO0 to GPIO31)
-#define GPIO_O_GPAGMUX1           0x20        // GPIO A Peripheral Group Mux
-                                              // (GPIO0 to 15)
-#define GPIO_O_GPAGMUX2           0x22        // GPIO A Peripheral Group Mux
-                                              // (GPIO16 to 31)
-#define GPIO_O_GPACSEL1           0x28        // GPIO A Core Select Register
-                                              // (GPIO0 to 7)
-#define GPIO_O_GPACSEL2           0x2A        // GPIO A Core Select Register
-                                              // (GPIO8 to 15)
-#define GPIO_O_GPACSEL3           0x2C        // GPIO A Core Select Register
-                                              // (GPIO16 to 23)
-#define GPIO_O_GPACSEL4           0x2E        // GPIO A Core Select Register
-                                              // (GPIO24 to 31)
-#define GPIO_O_GPALOCK            0x3C        // GPIO A Lock Configuration
-                                              // Register (GPIO0 to 31)
-#define GPIO_O_GPACR              0x3E        // GPIO A Lock Commit Register
-                                              // (GPIO0 to 31)
-#define GPIO_O_GPBCTRL            0x40        // GPIO B Qualification Sampling
-                                              // Period Control (GPIO32 to 63)
-#define GPIO_O_GPBQSEL1           0x42        // GPIO B Qualifier Select 1
-                                              // Register (GPIO32 to 47)
-#define GPIO_O_GPBQSEL2           0x44        // GPIO B Qualifier Select 2
-                                              // Register (GPIO48 to 63)
-#define GPIO_O_GPBMUX1            0x46        // GPIO B Mux 1 Register (GPIO32
-                                              // to 47)
-#define GPIO_O_GPBMUX2            0x48        // GPIO B Mux 2 Register (GPIO48
-                                              // to 63)
-#define GPIO_O_GPBDIR             0x4A        // GPIO B Direction Register
-                                              // (GPIO32 to 63)
-#define GPIO_O_GPBPUD             0x4C        // GPIO B Pull Up Disable Register
-                                              // (GPIO32 to 63)
-#define GPIO_O_GPBINV             0x50        // GPIO B Input Polarity Invert
-                                              // Registers (GPIO32 to 63)
-#define GPIO_O_GPBODR             0x52        // GPIO B Open Drain Output
-                                              // Register (GPIO32 to GPIO63)
-#define GPIO_O_GPBAMSEL           0x54        // GPIO B Analog Mode Select
-                                              // register (GPIO32 to GPIO63)
-#define GPIO_O_GPBGMUX1           0x60        // GPIO B Peripheral Group Mux
-                                              // (GPIO32 to 47)
-#define GPIO_O_GPBGMUX2           0x62        // GPIO B Peripheral Group Mux
-                                              // (GPIO48 to 63)
-#define GPIO_O_GPBCSEL1           0x68        // GPIO B Core Select Register
-                                              // (GPIO32 to 39)
-#define GPIO_O_GPBCSEL2           0x6A        // GPIO B Core Select Register
-                                              // (GPIO40 to 47)
-#define GPIO_O_GPBCSEL3           0x6C        // GPIO B Core Select Register
-                                              // (GPIO48 to 55)
-#define GPIO_O_GPBCSEL4           0x6E        // GPIO B Core Select Register
-                                              // (GPIO56 to 63)
-#define GPIO_O_GPBLOCK            0x7C        // GPIO B Lock Configuration
-                                              // Register (GPIO32 to 63)
-#define GPIO_O_GPBCR              0x7E        // GPIO B Lock Commit Register
-                                              // (GPIO32 to 63)
-#define GPIO_O_GPCCTRL            0x80        // GPIO C Qualification Sampling
-                                              // Period Control (GPIO64 to 95)
-#define GPIO_O_GPCQSEL1           0x82        // GPIO C Qualifier Select 1
-                                              // Register (GPIO64 to 79)
-#define GPIO_O_GPCQSEL2           0x84        // GPIO C Qualifier Select 2
-                                              // Register (GPIO80  to 95)
-#define GPIO_O_GPCMUX1            0x86        // GPIO C Mux 1 Register (GPIO64
-                                              // to 79)
-#define GPIO_O_GPCMUX2            0x88        // GPIO C Mux 2 Register (GPIO80 
-                                              // to 95)
-#define GPIO_O_GPCDIR             0x8A        // GPIO C Direction Register
-                                              // (GPIO64 to 95)
-#define GPIO_O_GPCPUD             0x8C        // GPIO C Pull Up Disable Register
-                                              // (GPIO64 to 95)
-#define GPIO_O_GPCINV             0x90        // GPIO C Input Polarity Invert
-                                              // Registers (GPIO64 to 95)
-#define GPIO_O_GPCODR             0x92        // GPIO C Open Drain Output
-                                              // Register (GPIO64 to GPIO95)
-#define GPIO_O_GPCGMUX1           0xA0        // GPIO C Peripheral Group Mux
-                                              // (GPIO64 to 79)
-#define GPIO_O_GPCGMUX2           0xA2        // GPIO C Peripheral Group Mux
-                                              // (GPIO80  to 95)
-#define GPIO_O_GPCCSEL1           0xA8        // GPIO C Core Select Register
-                                              // (GPIO64 to 71)
-#define GPIO_O_GPCCSEL2           0xAA        // GPIO C Core Select Register
-                                              // (GPIO72 to 79)
-#define GPIO_O_GPCCSEL3           0xAC        // GPIO C Core Select Register
-                                              // (GPIO80  to 87)
-#define GPIO_O_GPCCSEL4           0xAE        // GPIO C Core Select Register
-                                              // (GPIO88 to 95)
-#define GPIO_O_GPCLOCK            0xBC        // GPIO C Lock Configuration
-                                              // Register (GPIO64 to 95)
-#define GPIO_O_GPCCR              0xBE        // GPIO C Lock Commit Register
-                                              // (GPIO64 to 95)
-#define GPIO_O_GPDCTRL            0xC0        // GPIO D Qualification Sampling
-                                              // Period Control (GPIO96 to 127)
-#define GPIO_O_GPDQSEL1           0xC2        // GPIO D Qualifier Select 1
-                                              // Register (GPIO96 to 111)
-#define GPIO_O_GPDQSEL2           0xC4        // GPIO D Qualifier Select 2
-                                              // Register (GPIO112 to 127)
-#define GPIO_O_GPDMUX1            0xC6        // GPIO D Mux 1 Register (GPIO96
-                                              // to 111)
-#define GPIO_O_GPDMUX2            0xC8        // GPIO D Mux 2 Register (GPIO112
-                                              // to 127)
-#define GPIO_O_GPDDIR             0xCA        // GPIO D Direction Register
-                                              // (GPIO96 to 127)
-#define GPIO_O_GPDPUD             0xCC        // GPIO D Pull Up Disable Register
-                                              // (GPIO96 to 127)
-#define GPIO_O_GPDINV             0xD0        // GPIO D Input Polarity Invert
-                                              // Registers (GPIO96 to 127)
-#define GPIO_O_GPDODR             0xD2        // GPIO D Open Drain Output
-                                              // Register (GPIO96 to GPIO127)
-#define GPIO_O_GPDGMUX1           0xE0        // GPIO D Peripheral Group Mux
-                                              // (GPIO96 to 111)
-#define GPIO_O_GPDGMUX2           0xE2        // GPIO D Peripheral Group Mux
-                                              // (GPIO112 to 127)
-#define GPIO_O_GPDCSEL1           0xE8        // GPIO D Core Select Register
-                                              // (GPIO96 to 103)
-#define GPIO_O_GPDCSEL2           0xEA        // GPIO D Core Select Register
-                                              // (GPIO104 to 111)
-#define GPIO_O_GPDCSEL3           0xEC        // GPIO D Core Select Register
-                                              // (GPIO112 to 119)
-#define GPIO_O_GPDCSEL4           0xEE        // GPIO D Core Select Register
-                                              // (GPIO120 to 127)
-#define GPIO_O_GPDLOCK            0xFC        // GPIO D Lock Configuration
-                                              // Register (GPIO96 to 127)
-#define GPIO_O_GPDCR              0xFE        // GPIO D Lock Commit Register
-                                              // (GPIO96 to 127)
-#define GPIO_O_GPECTRL            0x100       // GPIO E Qualification Sampling
-                                              // Period Control (GPIO128 to
-                                              // 159)
-#define GPIO_O_GPEQSEL1           0x102       // GPIO E Qualifier Select 1
-                                              // Register (GPIO128 to 143)
-#define GPIO_O_GPEQSEL2           0x104       // GPIO E Qualifier Select 2
-                                              // Register (GPIO144  to 159)
-#define GPIO_O_GPEMUX1            0x106       // GPIO E Mux 1 Register (GPIO128
-                                              // to 143)
-#define GPIO_O_GPEMUX2            0x108       // GPIO E Mux 2 Register (GPIO144 
-                                              // to 159)
-#define GPIO_O_GPEDIR             0x10A       // GPIO E Direction Register
-                                              // (GPIO128 to 159)
-#define GPIO_O_GPEPUD             0x10C       // GPIO E Pull Up Disable Register
-                                              // (GPIO128 to 159)
-#define GPIO_O_GPEINV             0x110       // GPIO E Input Polarity Invert
-                                              // Registers (GPIO128 to 159)
-#define GPIO_O_GPEODR             0x112       // GPIO E Open Drain Output
-                                              // Register (GPIO128 to GPIO159)
-#define GPIO_O_GPEGMUX1           0x120       // GPIO E Peripheral Group Mux
-                                              // (GPIO128 to 143)
-#define GPIO_O_GPEGMUX2           0x122       // GPIO E Peripheral Group Mux
-                                              // (GPIO144  to 159)
-#define GPIO_O_GPECSEL1           0x128       // GPIO E Core Select Register
-                                              // (GPIO128 to 135)
-#define GPIO_O_GPECSEL2           0x12A       // GPIO E Core Select Register
-                                              // (GPIO136 to 143)
-#define GPIO_O_GPECSEL3           0x12C       // GPIO E Core Select Register
-                                              // (GPIO144  to 151)
-#define GPIO_O_GPECSEL4           0x12E       // GPIO E Core Select Register
-                                              // (GPIO152 to 159)
-#define GPIO_O_GPELOCK            0x13C       // GPIO E Lock Configuration
-                                              // Register (GPIO128 to 159)
-#define GPIO_O_GPECR              0x13E       // GPIO E Lock Commit Register
-                                              // (GPIO128 to 159)
-#define GPIO_O_GPFCTRL            0x140       // GPIO F Qualification Sampling
-                                              // Period Control (GPIO160 to
-                                              // 168)
-#define GPIO_O_GPFQSEL1           0x142       // GPIO F Qualifier Select 1
-                                              // Register (GPIO160 to 168)
-#define GPIO_O_GPFMUX1            0x146       // GPIO F Mux 1 Register (GPIO160
-                                              // to 168)
-#define GPIO_O_GPFDIR             0x14A       // GPIO F Direction Register
-                                              // (GPIO160 to 168)
-#define GPIO_O_GPFPUD             0x14C       // GPIO F Pull Up Disable Register
-                                              // (GPIO160 to 168)
-#define GPIO_O_GPFINV             0x150       // GPIO F Input Polarity Invert
-                                              // Registers (GPIO160 to 168)
-#define GPIO_O_GPFODR             0x152       // GPIO F Open Drain Output
-                                              // Register (GPIO160 to GPIO168)
-#define GPIO_O_GPFGMUX1           0x160       // GPIO F Peripheral Group Mux
-                                              // (GPIO160 to 168)
-#define GPIO_O_GPFCSEL1           0x168       // GPIO F Core Select Register
-                                              // (GPIO160 to 167)
-#define GPIO_O_GPFCSEL2           0x16A       // GPIO F Core Select Register
-                                              // (GPIO168)
-#define GPIO_O_GPFLOCK            0x17C       // GPIO F Lock Configuration
-                                              // Register (GPIO160 to 168)
-#define GPIO_O_GPFCR              0x17E       // GPIO F Lock Commit Register
-                                              // (GPIO160 to 168)
-#define GPIO_O_GPADAT             0x0         // GPIO A Data Register (GPIO0 to
-                                              // 31)
-#define GPIO_O_GPASET             0x2         // GPIO A Data Set Register (GPIO0
-                                              // to 31)
-#define GPIO_O_GPACLEAR           0x4         // GPIO A Data Clear Register
-                                              // (GPIO0 to 31)
-#define GPIO_O_GPATOGGLE          0x6         // GPIO A Data Toggle Register
-                                              // (GPIO0 to 31)
-#define GPIO_O_GPBDAT             0x8         // GPIO B Data Register (GPIO32 to
-                                              // 63)
-#define GPIO_O_GPBSET             0xA         // GPIO B Data Set Register
-                                              // (GPIO32 to 63)
-#define GPIO_O_GPBCLEAR           0xC         // GPIO B Data Clear Register
-                                              // (GPIO32 to 63)
-#define GPIO_O_GPBTOGGLE          0xE         // GPIO B Data Toggle Register
-                                              // (GPIO32 to 63)
-#define GPIO_O_GPCDAT             0x10        // GPIO C Data Register (GPIO64 to
-                                              // 95)
-#define GPIO_O_GPCSET             0x12        // GPIO C Data Set Register
-                                              // (GPIO64 to 95)
-#define GPIO_O_GPCCLEAR           0x14        // GPIO C Data Clear Register
-                                              // (GPIO64 to 95)
-#define GPIO_O_GPCTOGGLE          0x16        // GPIO C Data Toggle Register
-                                              // (GPIO64 to 95)
-#define GPIO_O_GPDDAT             0x18        // GPIO D Data Register (GPIO96 to
-                                              // 127)
-#define GPIO_O_GPDSET             0x1A        // GPIO D Data Set Register
-                                              // (GPIO96 to 127)
-#define GPIO_O_GPDCLEAR           0x1C        // GPIO D Data Clear Register
-                                              // (GPIO96 to 127)
-#define GPIO_O_GPDTOGGLE          0x1E        // GPIO D Data Toggle Register
-                                              // (GPIO96 to 127)
-#define GPIO_O_GPEDAT             0x20        // GPIO E Data Register (GPIO128
-                                              // to 159)
-#define GPIO_O_GPESET             0x22        // GPIO E Data Set Register
-                                              // (GPIO128 to 159)
-#define GPIO_O_GPECLEAR           0x24        // GPIO E Data Clear Register
-                                              // (GPIO128 to 159)
-#define GPIO_O_GPETOGGLE          0x26        // GPIO E Data Toggle Register
-                                              // (GPIO128 to 159)
-#define GPIO_O_GPFDAT             0x28        // GPIO F Data Register (GPIO160
-                                              // to 168)
-#define GPIO_O_GPFSET             0x2A        // GPIO F Data Set Register
-                                              // (GPIO160 to 168)
-#define GPIO_O_GPFCLEAR           0x2C        // GPIO F Data Clear Register
-                                              // (GPIO160 to 168)
-#define GPIO_O_GPFTOGGLE          0x2E        // GPIO F Data Toggle Register
-                                              // (GPIO160 to 168)
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPACTRL register
-//
-//*****************************************************************************
-#define GPIO_GPACTRL_QUALPRD0_S   0
-#define GPIO_GPACTRL_QUALPRD0_M   0xFF        // Qualification sampling period
-                                              // for GPIO0 to GPIO7
-#define GPIO_GPACTRL_QUALPRD1_S   8
-#define GPIO_GPACTRL_QUALPRD1_M   0xFF00      // Qualification sampling period
-                                              // for GPIO8 to GPIO15
-#define GPIO_GPACTRL_QUALPRD2_S   16
-#define GPIO_GPACTRL_QUALPRD2_M   0xFF0000    // Qualification sampling period
-                                              // for GPIO16 to GPIO23
-#define GPIO_GPACTRL_QUALPRD3_S   24
-#define GPIO_GPACTRL_QUALPRD3_M   0xFF000000  // Qualification sampling period
-                                              // for GPIO24 to GPIO31
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPAQSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPAQSEL1_GPIO0_S     0
-#define GPIO_GPAQSEL1_GPIO0_M     0x3         // Select input qualification type
-                                              // for GPIO0
-#define GPIO_GPAQSEL1_GPIO1_S     2
-#define GPIO_GPAQSEL1_GPIO1_M     0xC         // Select input qualification type
-                                              // for GPIO1
-#define GPIO_GPAQSEL1_GPIO2_S     4
-#define GPIO_GPAQSEL1_GPIO2_M     0x30        // Select input qualification type
-                                              // for GPIO2
-#define GPIO_GPAQSEL1_GPIO3_S     6
-#define GPIO_GPAQSEL1_GPIO3_M     0xC0        // Select input qualification type
-                                              // for GPIO3
-#define GPIO_GPAQSEL1_GPIO4_S     8
-#define GPIO_GPAQSEL1_GPIO4_M     0x300       // Select input qualification type
-                                              // for GPIO4
-#define GPIO_GPAQSEL1_GPIO5_S     10
-#define GPIO_GPAQSEL1_GPIO5_M     0xC00       // Select input qualification type
-                                              // for GPIO5
-#define GPIO_GPAQSEL1_GPIO6_S     12
-#define GPIO_GPAQSEL1_GPIO6_M     0x3000      // Select input qualification type
-                                              // for GPIO6
-#define GPIO_GPAQSEL1_GPIO7_S     14
-#define GPIO_GPAQSEL1_GPIO7_M     0xC000      // Select input qualification type
-                                              // for GPIO7
-#define GPIO_GPAQSEL1_GPIO8_S     16
-#define GPIO_GPAQSEL1_GPIO8_M     0x30000     // Select input qualification type
-                                              // for GPIO8
-#define GPIO_GPAQSEL1_GPIO9_S     18
-#define GPIO_GPAQSEL1_GPIO9_M     0xC0000     // Select input qualification type
-                                              // for GPIO9
-#define GPIO_GPAQSEL1_GPIO10_S    20
-#define GPIO_GPAQSEL1_GPIO10_M    0x300000    // Select input qualification type
-                                              // for GPIO10
-#define GPIO_GPAQSEL1_GPIO11_S    22
-#define GPIO_GPAQSEL1_GPIO11_M    0xC00000    // Select input qualification type
-                                              // for GPIO11
-#define GPIO_GPAQSEL1_GPIO12_S    24
-#define GPIO_GPAQSEL1_GPIO12_M    0x3000000   // Select input qualification type
-                                              // for GPIO12
-#define GPIO_GPAQSEL1_GPIO13_S    26
-#define GPIO_GPAQSEL1_GPIO13_M    0xC000000   // Select input qualification type
-                                              // for GPIO13
-#define GPIO_GPAQSEL1_GPIO14_S    28
-#define GPIO_GPAQSEL1_GPIO14_M    0x30000000  // Select input qualification type
-                                              // for GPIO14
-#define GPIO_GPAQSEL1_GPIO15_S    30
-#define GPIO_GPAQSEL1_GPIO15_M    0xC0000000  // Select input qualification type
-                                              // for GPIO15
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPAQSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPAQSEL2_GPIO16_S    0
-#define GPIO_GPAQSEL2_GPIO16_M    0x3         // Select input qualification type
-                                              // for GPIO16
-#define GPIO_GPAQSEL2_GPIO17_S    2
-#define GPIO_GPAQSEL2_GPIO17_M    0xC         // Select input qualification type
-                                              // for GPIO17
-#define GPIO_GPAQSEL2_GPIO18_S    4
-#define GPIO_GPAQSEL2_GPIO18_M    0x30        // Select input qualification type
-                                              // for GPIO18
-#define GPIO_GPAQSEL2_GPIO19_S    6
-#define GPIO_GPAQSEL2_GPIO19_M    0xC0        // Select input qualification type
-                                              // for GPIO19
-#define GPIO_GPAQSEL2_GPIO20_S    8
-#define GPIO_GPAQSEL2_GPIO20_M    0x300       // Select input qualification type
-                                              // for GPIO20
-#define GPIO_GPAQSEL2_GPIO21_S    10
-#define GPIO_GPAQSEL2_GPIO21_M    0xC00       // Select input qualification type
-                                              // for GPIO21
-#define GPIO_GPAQSEL2_GPIO22_S    12
-#define GPIO_GPAQSEL2_GPIO22_M    0x3000      // Select input qualification type
-                                              // for GPIO22
-#define GPIO_GPAQSEL2_GPIO23_S    14
-#define GPIO_GPAQSEL2_GPIO23_M    0xC000      // Select input qualification type
-                                              // for GPIO23
-#define GPIO_GPAQSEL2_GPIO24_S    16
-#define GPIO_GPAQSEL2_GPIO24_M    0x30000     // Select input qualification type
-                                              // for GPIO24
-#define GPIO_GPAQSEL2_GPIO25_S    18
-#define GPIO_GPAQSEL2_GPIO25_M    0xC0000     // Select input qualification type
-                                              // for GPIO25
-#define GPIO_GPAQSEL2_GPIO26_S    20
-#define GPIO_GPAQSEL2_GPIO26_M    0x300000    // Select input qualification type
-                                              // for GPIO26
-#define GPIO_GPAQSEL2_GPIO27_S    22
-#define GPIO_GPAQSEL2_GPIO27_M    0xC00000    // Select input qualification type
-                                              // for GPIO27
-#define GPIO_GPAQSEL2_GPIO28_S    24
-#define GPIO_GPAQSEL2_GPIO28_M    0x3000000   // Select input qualification type
-                                              // for GPIO28
-#define GPIO_GPAQSEL2_GPIO29_S    26
-#define GPIO_GPAQSEL2_GPIO29_M    0xC000000   // Select input qualification type
-                                              // for GPIO29
-#define GPIO_GPAQSEL2_GPIO30_S    28
-#define GPIO_GPAQSEL2_GPIO30_M    0x30000000  // Select input qualification type
-                                              // for GPIO30
-#define GPIO_GPAQSEL2_GPIO31_S    30
-#define GPIO_GPAQSEL2_GPIO31_M    0xC0000000  // Select input qualification type
-                                              // for GPIO31
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPAMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPAMUX1_GPIO0_S      0
-#define GPIO_GPAMUX1_GPIO0_M      0x3         // Defines pin-muxing selection
-                                              // for GPIO0
-#define GPIO_GPAMUX1_GPIO1_S      2
-#define GPIO_GPAMUX1_GPIO1_M      0xC         // Defines pin-muxing selection
-                                              // for GPIO1
-#define GPIO_GPAMUX1_GPIO2_S      4
-#define GPIO_GPAMUX1_GPIO2_M      0x30        // Defines pin-muxing selection
-                                              // for GPIO2
-#define GPIO_GPAMUX1_GPIO3_S      6
-#define GPIO_GPAMUX1_GPIO3_M      0xC0        // Defines pin-muxing selection
-                                              // for GPIO3
-#define GPIO_GPAMUX1_GPIO4_S      8
-#define GPIO_GPAMUX1_GPIO4_M      0x300       // Defines pin-muxing selection
-                                              // for GPIO4
-#define GPIO_GPAMUX1_GPIO5_S      10
-#define GPIO_GPAMUX1_GPIO5_M      0xC00       // Defines pin-muxing selection
-                                              // for GPIO5
-#define GPIO_GPAMUX1_GPIO6_S      12
-#define GPIO_GPAMUX1_GPIO6_M      0x3000      // Defines pin-muxing selection
-                                              // for GPIO6
-#define GPIO_GPAMUX1_GPIO7_S      14
-#define GPIO_GPAMUX1_GPIO7_M      0xC000      // Defines pin-muxing selection
-                                              // for GPIO7
-#define GPIO_GPAMUX1_GPIO8_S      16
-#define GPIO_GPAMUX1_GPIO8_M      0x30000     // Defines pin-muxing selection
-                                              // for GPIO8
-#define GPIO_GPAMUX1_GPIO9_S      18
-#define GPIO_GPAMUX1_GPIO9_M      0xC0000     // Defines pin-muxing selection
-                                              // for GPIO9
-#define GPIO_GPAMUX1_GPIO10_S     20
-#define GPIO_GPAMUX1_GPIO10_M     0x300000    // Defines pin-muxing selection
-                                              // for GPIO10
-#define GPIO_GPAMUX1_GPIO11_S     22
-#define GPIO_GPAMUX1_GPIO11_M     0xC00000    // Defines pin-muxing selection
-                                              // for GPIO11
-#define GPIO_GPAMUX1_GPIO12_S     24
-#define GPIO_GPAMUX1_GPIO12_M     0x3000000   // Defines pin-muxing selection
-                                              // for GPIO12
-#define GPIO_GPAMUX1_GPIO13_S     26
-#define GPIO_GPAMUX1_GPIO13_M     0xC000000   // Defines pin-muxing selection
-                                              // for GPIO13
-#define GPIO_GPAMUX1_GPIO14_S     28
-#define GPIO_GPAMUX1_GPIO14_M     0x30000000  // Defines pin-muxing selection
-                                              // for GPIO14
-#define GPIO_GPAMUX1_GPIO15_S     30
-#define GPIO_GPAMUX1_GPIO15_M     0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO15
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPAMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPAMUX2_GPIO16_S     0
-#define GPIO_GPAMUX2_GPIO16_M     0x3         // Defines pin-muxing selection
-                                              // for GPIO16
-#define GPIO_GPAMUX2_GPIO17_S     2
-#define GPIO_GPAMUX2_GPIO17_M     0xC         // Defines pin-muxing selection
-                                              // for GPIO17
-#define GPIO_GPAMUX2_GPIO18_S     4
-#define GPIO_GPAMUX2_GPIO18_M     0x30        // Defines pin-muxing selection
-                                              // for GPIO18
-#define GPIO_GPAMUX2_GPIO19_S     6
-#define GPIO_GPAMUX2_GPIO19_M     0xC0        // Defines pin-muxing selection
-                                              // for GPIO19
-#define GPIO_GPAMUX2_GPIO20_S     8
-#define GPIO_GPAMUX2_GPIO20_M     0x300       // Defines pin-muxing selection
-                                              // for GPIO20
-#define GPIO_GPAMUX2_GPIO21_S     10
-#define GPIO_GPAMUX2_GPIO21_M     0xC00       // Defines pin-muxing selection
-                                              // for GPIO21
-#define GPIO_GPAMUX2_GPIO22_S     12
-#define GPIO_GPAMUX2_GPIO22_M     0x3000      // Defines pin-muxing selection
-                                              // for GPIO22
-#define GPIO_GPAMUX2_GPIO23_S     14
-#define GPIO_GPAMUX2_GPIO23_M     0xC000      // Defines pin-muxing selection
-                                              // for GPIO23
-#define GPIO_GPAMUX2_GPIO24_S     16
-#define GPIO_GPAMUX2_GPIO24_M     0x30000     // Defines pin-muxing selection
-                                              // for GPIO24
-#define GPIO_GPAMUX2_GPIO25_S     18
-#define GPIO_GPAMUX2_GPIO25_M     0xC0000     // Defines pin-muxing selection
-                                              // for GPIO25
-#define GPIO_GPAMUX2_GPIO26_S     20
-#define GPIO_GPAMUX2_GPIO26_M     0x300000    // Defines pin-muxing selection
-                                              // for GPIO26
-#define GPIO_GPAMUX2_GPIO27_S     22
-#define GPIO_GPAMUX2_GPIO27_M     0xC00000    // Defines pin-muxing selection
-                                              // for GPIO27
-#define GPIO_GPAMUX2_GPIO28_S     24
-#define GPIO_GPAMUX2_GPIO28_M     0x3000000   // Defines pin-muxing selection
-                                              // for GPIO28
-#define GPIO_GPAMUX2_GPIO29_S     26
-#define GPIO_GPAMUX2_GPIO29_M     0xC000000   // Defines pin-muxing selection
-                                              // for GPIO29
-#define GPIO_GPAMUX2_GPIO30_S     28
-#define GPIO_GPAMUX2_GPIO30_M     0x30000000  // Defines pin-muxing selection
-                                              // for GPIO30
-#define GPIO_GPAMUX2_GPIO31_S     30
-#define GPIO_GPAMUX2_GPIO31_M     0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO31
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPADIR register
-//
-//*****************************************************************************
-#define GPIO_GPADIR_GPIO0         0x1         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO1         0x2         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO2         0x4         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO3         0x8         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO4         0x10        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO5         0x20        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO6         0x40        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO7         0x80        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO8         0x100       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO9         0x200       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO10        0x400       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO11        0x800       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO12        0x1000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO13        0x2000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO14        0x4000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO15        0x8000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO16        0x10000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO17        0x20000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO18        0x40000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO19        0x80000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO20        0x100000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO21        0x200000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO22        0x400000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO23        0x800000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO24        0x1000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO25        0x2000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO26        0x4000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO27        0x8000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO28        0x10000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO29        0x20000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO30        0x40000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPADIR_GPIO31        0x80000000  // Defines direction for this pin
-                                              // in GPIO mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPAPUD register
-//
-//*****************************************************************************
-#define GPIO_GPAPUD_GPIO0         0x1         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO1         0x2         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO2         0x4         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO3         0x8         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO4         0x10        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO5         0x20        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO6         0x40        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO7         0x80        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO8         0x100       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO9         0x200       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO10        0x400       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO11        0x800       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO12        0x1000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO13        0x2000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO14        0x4000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO15        0x8000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO16        0x10000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO17        0x20000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO18        0x40000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO19        0x80000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO20        0x100000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO21        0x200000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO22        0x400000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO23        0x800000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO24        0x1000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO25        0x2000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO26        0x4000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO27        0x8000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO28        0x10000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO29        0x20000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO30        0x40000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPAPUD_GPIO31        0x80000000  // Pull-Up Disable control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPAINV register
-//
-//*****************************************************************************
-#define GPIO_GPAINV_GPIO0         0x1         // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO1         0x2         // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO2         0x4         // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO3         0x8         // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO4         0x10        // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO5         0x20        // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO6         0x40        // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO7         0x80        // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO8         0x100       // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO9         0x200       // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO10        0x400       // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO11        0x800       // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO12        0x1000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO13        0x2000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO14        0x4000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO15        0x8000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO16        0x10000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO17        0x20000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO18        0x40000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO19        0x80000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO20        0x100000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO21        0x200000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO22        0x400000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO23        0x800000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO24        0x1000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO25        0x2000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO26        0x4000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO27        0x8000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO28        0x10000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO29        0x20000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO30        0x40000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPAINV_GPIO31        0x80000000  // Input inversion control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPAODR register
-//
-//*****************************************************************************
-#define GPIO_GPAODR_GPIO0         0x1         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO1         0x2         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO2         0x4         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO3         0x8         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO4         0x10        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO5         0x20        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO6         0x40        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO7         0x80        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO8         0x100       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO9         0x200       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO10        0x400       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO11        0x800       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO12        0x1000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO13        0x2000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO14        0x4000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO15        0x8000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO16        0x10000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO17        0x20000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO18        0x40000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO19        0x80000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO20        0x100000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO21        0x200000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO22        0x400000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO23        0x800000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO24        0x1000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO25        0x2000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO26        0x4000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO27        0x8000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO28        0x10000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO29        0x20000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO30        0x40000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPAODR_GPIO31        0x80000000  // Outpout Open-Drain control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPAGMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPAGMUX1_GPIO0_S     0
-#define GPIO_GPAGMUX1_GPIO0_M     0x3         // Defines pin-muxing selection
-                                              // for GPIO0
-#define GPIO_GPAGMUX1_GPIO1_S     2
-#define GPIO_GPAGMUX1_GPIO1_M     0xC         // Defines pin-muxing selection
-                                              // for GPIO1
-#define GPIO_GPAGMUX1_GPIO2_S     4
-#define GPIO_GPAGMUX1_GPIO2_M     0x30        // Defines pin-muxing selection
-                                              // for GPIO2
-#define GPIO_GPAGMUX1_GPIO3_S     6
-#define GPIO_GPAGMUX1_GPIO3_M     0xC0        // Defines pin-muxing selection
-                                              // for GPIO3
-#define GPIO_GPAGMUX1_GPIO4_S     8
-#define GPIO_GPAGMUX1_GPIO4_M     0x300       // Defines pin-muxing selection
-                                              // for GPIO4
-#define GPIO_GPAGMUX1_GPIO5_S     10
-#define GPIO_GPAGMUX1_GPIO5_M     0xC00       // Defines pin-muxing selection
-                                              // for GPIO5
-#define GPIO_GPAGMUX1_GPIO6_S     12
-#define GPIO_GPAGMUX1_GPIO6_M     0x3000      // Defines pin-muxing selection
-                                              // for GPIO6
-#define GPIO_GPAGMUX1_GPIO7_S     14
-#define GPIO_GPAGMUX1_GPIO7_M     0xC000      // Defines pin-muxing selection
-                                              // for GPIO7
-#define GPIO_GPAGMUX1_GPIO8_S     16
-#define GPIO_GPAGMUX1_GPIO8_M     0x30000     // Defines pin-muxing selection
-                                              // for GPIO8
-#define GPIO_GPAGMUX1_GPIO9_S     18
-#define GPIO_GPAGMUX1_GPIO9_M     0xC0000     // Defines pin-muxing selection
-                                              // for GPIO9
-#define GPIO_GPAGMUX1_GPIO10_S    20
-#define GPIO_GPAGMUX1_GPIO10_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO10
-#define GPIO_GPAGMUX1_GPIO11_S    22
-#define GPIO_GPAGMUX1_GPIO11_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO11
-#define GPIO_GPAGMUX1_GPIO12_S    24
-#define GPIO_GPAGMUX1_GPIO12_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO12
-#define GPIO_GPAGMUX1_GPIO13_S    26
-#define GPIO_GPAGMUX1_GPIO13_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO13
-#define GPIO_GPAGMUX1_GPIO14_S    28
-#define GPIO_GPAGMUX1_GPIO14_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO14
-#define GPIO_GPAGMUX1_GPIO15_S    30
-#define GPIO_GPAGMUX1_GPIO15_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO15
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPAGMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPAGMUX2_GPIO16_S    0
-#define GPIO_GPAGMUX2_GPIO16_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO16
-#define GPIO_GPAGMUX2_GPIO17_S    2
-#define GPIO_GPAGMUX2_GPIO17_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO17
-#define GPIO_GPAGMUX2_GPIO18_S    4
-#define GPIO_GPAGMUX2_GPIO18_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO18
-#define GPIO_GPAGMUX2_GPIO19_S    6
-#define GPIO_GPAGMUX2_GPIO19_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO19
-#define GPIO_GPAGMUX2_GPIO20_S    8
-#define GPIO_GPAGMUX2_GPIO20_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO20
-#define GPIO_GPAGMUX2_GPIO21_S    10
-#define GPIO_GPAGMUX2_GPIO21_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO21
-#define GPIO_GPAGMUX2_GPIO22_S    12
-#define GPIO_GPAGMUX2_GPIO22_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO22
-#define GPIO_GPAGMUX2_GPIO23_S    14
-#define GPIO_GPAGMUX2_GPIO23_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO23
-#define GPIO_GPAGMUX2_GPIO24_S    16
-#define GPIO_GPAGMUX2_GPIO24_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO24
-#define GPIO_GPAGMUX2_GPIO25_S    18
-#define GPIO_GPAGMUX2_GPIO25_M    0xC0000     // Defines pin-muxing selection
-                                              // for GPIO25
-#define GPIO_GPAGMUX2_GPIO26_S    20
-#define GPIO_GPAGMUX2_GPIO26_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO26
-#define GPIO_GPAGMUX2_GPIO27_S    22
-#define GPIO_GPAGMUX2_GPIO27_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO27
-#define GPIO_GPAGMUX2_GPIO28_S    24
-#define GPIO_GPAGMUX2_GPIO28_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO28
-#define GPIO_GPAGMUX2_GPIO29_S    26
-#define GPIO_GPAGMUX2_GPIO29_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO29
-#define GPIO_GPAGMUX2_GPIO30_S    28
-#define GPIO_GPAGMUX2_GPIO30_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO30
-#define GPIO_GPAGMUX2_GPIO31_S    30
-#define GPIO_GPAGMUX2_GPIO31_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO31
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPACSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPACSEL1_GPIO0_S     0
-#define GPIO_GPACSEL1_GPIO0_M     0xF         // GPIO0 Master CPU Select
-#define GPIO_GPACSEL1_GPIO1_S     4
-#define GPIO_GPACSEL1_GPIO1_M     0xF0        // GPIO1 Master CPU Select
-#define GPIO_GPACSEL1_GPIO2_S     8
-#define GPIO_GPACSEL1_GPIO2_M     0xF00       // GPIO2 Master CPU Select
-#define GPIO_GPACSEL1_GPIO3_S     12
-#define GPIO_GPACSEL1_GPIO3_M     0xF000      // GPIO3 Master CPU Select
-#define GPIO_GPACSEL1_GPIO4_S     16
-#define GPIO_GPACSEL1_GPIO4_M     0xF0000     // GPIO4 Master CPU Select
-#define GPIO_GPACSEL1_GPIO5_S     20
-#define GPIO_GPACSEL1_GPIO5_M     0xF00000    // GPIO5 Master CPU Select
-#define GPIO_GPACSEL1_GPIO6_S     24
-#define GPIO_GPACSEL1_GPIO6_M     0xF000000   // GPIO6 Master CPU Select
-#define GPIO_GPACSEL1_GPIO7_S     28
-#define GPIO_GPACSEL1_GPIO7_M     0xF0000000  // GPIO7 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPACSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPACSEL2_GPIO8_S     0
-#define GPIO_GPACSEL2_GPIO8_M     0xF         // GPIO8 Master CPU Select
-#define GPIO_GPACSEL2_GPIO9_S     4
-#define GPIO_GPACSEL2_GPIO9_M     0xF0        // GPIO9 Master CPU Select
-#define GPIO_GPACSEL2_GPIO10_S    8
-#define GPIO_GPACSEL2_GPIO10_M    0xF00       // GPIO10 Master CPU Select
-#define GPIO_GPACSEL2_GPIO11_S    12
-#define GPIO_GPACSEL2_GPIO11_M    0xF000      // GPIO11 Master CPU Select
-#define GPIO_GPACSEL2_GPIO12_S    16
-#define GPIO_GPACSEL2_GPIO12_M    0xF0000     // GPIO12 Master CPU Select
-#define GPIO_GPACSEL2_GPIO13_S    20
-#define GPIO_GPACSEL2_GPIO13_M    0xF00000    // GPIO13 Master CPU Select
-#define GPIO_GPACSEL2_GPIO14_S    24
-#define GPIO_GPACSEL2_GPIO14_M    0xF000000   // GPIO14 Master CPU Select
-#define GPIO_GPACSEL2_GPIO15_S    28
-#define GPIO_GPACSEL2_GPIO15_M    0xF0000000  // GPIO15 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPACSEL3 register
-//
-//*****************************************************************************
-#define GPIO_GPACSEL3_GPIO16_S    0
-#define GPIO_GPACSEL3_GPIO16_M    0xF         // GPIO16 Master CPU Select
-#define GPIO_GPACSEL3_GPIO17_S    4
-#define GPIO_GPACSEL3_GPIO17_M    0xF0        // GPIO17 Master CPU Select
-#define GPIO_GPACSEL3_GPIO18_S    8
-#define GPIO_GPACSEL3_GPIO18_M    0xF00       // GPIO18 Master CPU Select
-#define GPIO_GPACSEL3_GPIO19_S    12
-#define GPIO_GPACSEL3_GPIO19_M    0xF000      // GPIO19 Master CPU Select
-#define GPIO_GPACSEL3_GPIO20_S    16
-#define GPIO_GPACSEL3_GPIO20_M    0xF0000     // GPIO20 Master CPU Select
-#define GPIO_GPACSEL3_GPIO21_S    20
-#define GPIO_GPACSEL3_GPIO21_M    0xF00000    // GPIO21 Master CPU Select
-#define GPIO_GPACSEL3_GPIO22_S    24
-#define GPIO_GPACSEL3_GPIO22_M    0xF000000   // GPIO22 Master CPU Select
-#define GPIO_GPACSEL3_GPIO23_S    28
-#define GPIO_GPACSEL3_GPIO23_M    0xF0000000  // GPIO23 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPACSEL4 register
-//
-//*****************************************************************************
-#define GPIO_GPACSEL4_GPIO24_S    0
-#define GPIO_GPACSEL4_GPIO24_M    0xF         // GPIO24 Master CPU Select
-#define GPIO_GPACSEL4_GPIO25_S    4
-#define GPIO_GPACSEL4_GPIO25_M    0xF0        // GPIO25 Master CPU Select
-#define GPIO_GPACSEL4_GPIO26_S    8
-#define GPIO_GPACSEL4_GPIO26_M    0xF00       // GPIO26 Master CPU Select
-#define GPIO_GPACSEL4_GPIO27_S    12
-#define GPIO_GPACSEL4_GPIO27_M    0xF000      // GPIO27 Master CPU Select
-#define GPIO_GPACSEL4_GPIO28_S    16
-#define GPIO_GPACSEL4_GPIO28_M    0xF0000     // GPIO28 Master CPU Select
-#define GPIO_GPACSEL4_GPIO29_S    20
-#define GPIO_GPACSEL4_GPIO29_M    0xF00000    // GPIO29 Master CPU Select
-#define GPIO_GPACSEL4_GPIO30_S    24
-#define GPIO_GPACSEL4_GPIO30_M    0xF000000   // GPIO30 Master CPU Select
-#define GPIO_GPACSEL4_GPIO31_S    28
-#define GPIO_GPACSEL4_GPIO31_M    0xF0000000  // GPIO31 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPALOCK register
-//
-//*****************************************************************************
-#define GPIO_GPALOCK_GPIO0        0x1         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO1        0x2         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO2        0x4         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO3        0x8         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO4        0x10        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO5        0x20        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO6        0x40        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO7        0x80        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO8        0x100       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO9        0x200       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO10       0x400       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO11       0x800       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO12       0x1000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO13       0x2000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO14       0x4000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO15       0x8000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO16       0x10000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO17       0x20000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO18       0x40000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO19       0x80000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO20       0x100000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO21       0x200000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO22       0x400000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO23       0x800000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO24       0x1000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO25       0x2000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO26       0x4000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO27       0x8000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO28       0x10000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO29       0x20000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO30       0x40000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPALOCK_GPIO31       0x80000000  // Configuration Lock bit for this
-                                              // pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPACR register
-//
-//*****************************************************************************
-#define GPIO_GPACR_GPIO0          0x1         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO1          0x2         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO2          0x4         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO3          0x8         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO4          0x10        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO5          0x20        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO6          0x40        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO7          0x80        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO8          0x100       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO9          0x200       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO10         0x400       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO11         0x800       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO12         0x1000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO13         0x2000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO14         0x4000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO15         0x8000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO16         0x10000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO17         0x20000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO18         0x40000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO19         0x80000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO20         0x100000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO21         0x200000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO22         0x400000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO23         0x800000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO24         0x1000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO25         0x2000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO26         0x4000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO27         0x8000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO28         0x10000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO29         0x20000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO30         0x40000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPACR_GPIO31         0x80000000  // Configuration lock commit bit
-                                              // for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBCTRL register
-//
-//*****************************************************************************
-#define GPIO_GPBCTRL_QUALPRD0_S   0
-#define GPIO_GPBCTRL_QUALPRD0_M   0xFF        // Qualification sampling period
-                                              // for GPIO32 to GPIO39
-#define GPIO_GPBCTRL_QUALPRD1_S   8
-#define GPIO_GPBCTRL_QUALPRD1_M   0xFF00      // Qualification sampling period
-                                              // for GPIO40 to GPIO47
-#define GPIO_GPBCTRL_QUALPRD2_S   16
-#define GPIO_GPBCTRL_QUALPRD2_M   0xFF0000    // Qualification sampling period
-                                              // for GPIO48 to GPIO55
-#define GPIO_GPBCTRL_QUALPRD3_S   24
-#define GPIO_GPBCTRL_QUALPRD3_M   0xFF000000  // Qualification sampling period
-                                              // for GPIO56 to GPIO63
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBQSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPBQSEL1_GPIO32_S    0
-#define GPIO_GPBQSEL1_GPIO32_M    0x3         // Select input qualification type
-                                              // for GPIO32
-#define GPIO_GPBQSEL1_GPIO33_S    2
-#define GPIO_GPBQSEL1_GPIO33_M    0xC         // Select input qualification type
-                                              // for GPIO33
-#define GPIO_GPBQSEL1_GPIO34_S    4
-#define GPIO_GPBQSEL1_GPIO34_M    0x30        // Select input qualification type
-                                              // for GPIO34
-#define GPIO_GPBQSEL1_GPIO35_S    6
-#define GPIO_GPBQSEL1_GPIO35_M    0xC0        // Select input qualification type
-                                              // for GPIO35
-#define GPIO_GPBQSEL1_GPIO36_S    8
-#define GPIO_GPBQSEL1_GPIO36_M    0x300       // Select input qualification type
-                                              // for GPIO36
-#define GPIO_GPBQSEL1_GPIO37_S    10
-#define GPIO_GPBQSEL1_GPIO37_M    0xC00       // Select input qualification type
-                                              // for GPIO37
-#define GPIO_GPBQSEL1_GPIO38_S    12
-#define GPIO_GPBQSEL1_GPIO38_M    0x3000      // Select input qualification type
-                                              // for GPIO38
-#define GPIO_GPBQSEL1_GPIO39_S    14
-#define GPIO_GPBQSEL1_GPIO39_M    0xC000      // Select input qualification type
-                                              // for GPIO39
-#define GPIO_GPBQSEL1_GPIO40_S    16
-#define GPIO_GPBQSEL1_GPIO40_M    0x30000     // Select input qualification type
-                                              // for GPIO40
-#define GPIO_GPBQSEL1_GPIO41_S    18
-#define GPIO_GPBQSEL1_GPIO41_M    0xC0000     // Select input qualification type
-                                              // for GPIO41
-#define GPIO_GPBQSEL1_GPIO42_S    20
-#define GPIO_GPBQSEL1_GPIO42_M    0x300000    // Select input qualification type
-                                              // for GPIO42
-#define GPIO_GPBQSEL1_GPIO43_S    22
-#define GPIO_GPBQSEL1_GPIO43_M    0xC00000    // Select input qualification type
-                                              // for GPIO43
-#define GPIO_GPBQSEL1_GPIO44_S    24
-#define GPIO_GPBQSEL1_GPIO44_M    0x3000000   // Select input qualification type
-                                              // for GPIO44
-#define GPIO_GPBQSEL1_GPIO45_S    26
-#define GPIO_GPBQSEL1_GPIO45_M    0xC000000   // Select input qualification type
-                                              // for GPIO45
-#define GPIO_GPBQSEL1_GPIO46_S    28
-#define GPIO_GPBQSEL1_GPIO46_M    0x30000000  // Select input qualification type
-                                              // for GPIO46
-#define GPIO_GPBQSEL1_GPIO47_S    30
-#define GPIO_GPBQSEL1_GPIO47_M    0xC0000000  // Select input qualification type
-                                              // for GPIO47
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBQSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPBQSEL2_GPIO48_S    0
-#define GPIO_GPBQSEL2_GPIO48_M    0x3         // Select input qualification type
-                                              // for GPIO48
-#define GPIO_GPBQSEL2_GPIO49_S    2
-#define GPIO_GPBQSEL2_GPIO49_M    0xC         // Select input qualification type
-                                              // for GPIO49
-#define GPIO_GPBQSEL2_GPIO50_S    4
-#define GPIO_GPBQSEL2_GPIO50_M    0x30        // Select input qualification type
-                                              // for GPIO50
-#define GPIO_GPBQSEL2_GPIO51_S    6
-#define GPIO_GPBQSEL2_GPIO51_M    0xC0        // Select input qualification type
-                                              // for GPIO51
-#define GPIO_GPBQSEL2_GPIO52_S    8
-#define GPIO_GPBQSEL2_GPIO52_M    0x300       // Select input qualification type
-                                              // for GPIO52
-#define GPIO_GPBQSEL2_GPIO53_S    10
-#define GPIO_GPBQSEL2_GPIO53_M    0xC00       // Select input qualification type
-                                              // for GPIO53
-#define GPIO_GPBQSEL2_GPIO54_S    12
-#define GPIO_GPBQSEL2_GPIO54_M    0x3000      // Select input qualification type
-                                              // for GPIO54
-#define GPIO_GPBQSEL2_GPIO55_S    14
-#define GPIO_GPBQSEL2_GPIO55_M    0xC000      // Select input qualification type
-                                              // for GPIO55
-#define GPIO_GPBQSEL2_GPIO56_S    16
-#define GPIO_GPBQSEL2_GPIO56_M    0x30000     // Select input qualification type
-                                              // for GPIO56
-#define GPIO_GPBQSEL2_GPIO57_S    18
-#define GPIO_GPBQSEL2_GPIO57_M    0xC0000     // Select input qualification type
-                                              // for GPIO57
-#define GPIO_GPBQSEL2_GPIO58_S    20
-#define GPIO_GPBQSEL2_GPIO58_M    0x300000    // Select input qualification type
-                                              // for GPIO58
-#define GPIO_GPBQSEL2_GPIO59_S    22
-#define GPIO_GPBQSEL2_GPIO59_M    0xC00000    // Select input qualification type
-                                              // for GPIO59
-#define GPIO_GPBQSEL2_GPIO60_S    24
-#define GPIO_GPBQSEL2_GPIO60_M    0x3000000   // Select input qualification type
-                                              // for GPIO60
-#define GPIO_GPBQSEL2_GPIO61_S    26
-#define GPIO_GPBQSEL2_GPIO61_M    0xC000000   // Select input qualification type
-                                              // for GPIO61
-#define GPIO_GPBQSEL2_GPIO62_S    28
-#define GPIO_GPBQSEL2_GPIO62_M    0x30000000  // Select input qualification type
-                                              // for GPIO62
-#define GPIO_GPBQSEL2_GPIO63_S    30
-#define GPIO_GPBQSEL2_GPIO63_M    0xC0000000  // Select input qualification type
-                                              // for GPIO63
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPBMUX1_GPIO32_S     0
-#define GPIO_GPBMUX1_GPIO32_M     0x3         // Defines pin-muxing selection
-                                              // for GPIO32
-#define GPIO_GPBMUX1_GPIO33_S     2
-#define GPIO_GPBMUX1_GPIO33_M     0xC         // Defines pin-muxing selection
-                                              // for GPIO33
-#define GPIO_GPBMUX1_GPIO34_S     4
-#define GPIO_GPBMUX1_GPIO34_M     0x30        // Defines pin-muxing selection
-                                              // for GPIO34
-#define GPIO_GPBMUX1_GPIO35_S     6
-#define GPIO_GPBMUX1_GPIO35_M     0xC0        // Defines pin-muxing selection
-                                              // for GPIO35
-#define GPIO_GPBMUX1_GPIO36_S     8
-#define GPIO_GPBMUX1_GPIO36_M     0x300       // Defines pin-muxing selection
-                                              // for GPIO36
-#define GPIO_GPBMUX1_GPIO37_S     10
-#define GPIO_GPBMUX1_GPIO37_M     0xC00       // Defines pin-muxing selection
-                                              // for GPIO37
-#define GPIO_GPBMUX1_GPIO38_S     12
-#define GPIO_GPBMUX1_GPIO38_M     0x3000      // Defines pin-muxing selection
-                                              // for GPIO38
-#define GPIO_GPBMUX1_GPIO39_S     14
-#define GPIO_GPBMUX1_GPIO39_M     0xC000      // Defines pin-muxing selection
-                                              // for GPIO39
-#define GPIO_GPBMUX1_GPIO40_S     16
-#define GPIO_GPBMUX1_GPIO40_M     0x30000     // Defines pin-muxing selection
-                                              // for GPIO40
-#define GPIO_GPBMUX1_GPIO41_S     18
-#define GPIO_GPBMUX1_GPIO41_M     0xC0000     // Defines pin-muxing selection
-                                              // for GPIO41
-#define GPIO_GPBMUX1_GPIO42_S     20
-#define GPIO_GPBMUX1_GPIO42_M     0x300000    // Defines pin-muxing selection
-                                              // for GPIO42
-#define GPIO_GPBMUX1_GPIO43_S     22
-#define GPIO_GPBMUX1_GPIO43_M     0xC00000    // Defines pin-muxing selection
-                                              // for GPIO43
-#define GPIO_GPBMUX1_GPIO44_S     24
-#define GPIO_GPBMUX1_GPIO44_M     0x3000000   // Defines pin-muxing selection
-                                              // for GPIO44
-#define GPIO_GPBMUX1_GPIO45_S     26
-#define GPIO_GPBMUX1_GPIO45_M     0xC000000   // Defines pin-muxing selection
-                                              // for GPIO45
-#define GPIO_GPBMUX1_GPIO46_S     28
-#define GPIO_GPBMUX1_GPIO46_M     0x30000000  // Defines pin-muxing selection
-                                              // for GPIO46
-#define GPIO_GPBMUX1_GPIO47_S     30
-#define GPIO_GPBMUX1_GPIO47_M     0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO47
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPBMUX2_GPIO48_S     0
-#define GPIO_GPBMUX2_GPIO48_M     0x3         // Defines pin-muxing selection
-                                              // for GPIO48
-#define GPIO_GPBMUX2_GPIO49_S     2
-#define GPIO_GPBMUX2_GPIO49_M     0xC         // Defines pin-muxing selection
-                                              // for GPIO49
-#define GPIO_GPBMUX2_GPIO50_S     4
-#define GPIO_GPBMUX2_GPIO50_M     0x30        // Defines pin-muxing selection
-                                              // for GPIO50
-#define GPIO_GPBMUX2_GPIO51_S     6
-#define GPIO_GPBMUX2_GPIO51_M     0xC0        // Defines pin-muxing selection
-                                              // for GPIO51
-#define GPIO_GPBMUX2_GPIO52_S     8
-#define GPIO_GPBMUX2_GPIO52_M     0x300       // Defines pin-muxing selection
-                                              // for GPIO52
-#define GPIO_GPBMUX2_GPIO53_S     10
-#define GPIO_GPBMUX2_GPIO53_M     0xC00       // Defines pin-muxing selection
-                                              // for GPIO53
-#define GPIO_GPBMUX2_GPIO54_S     12
-#define GPIO_GPBMUX2_GPIO54_M     0x3000      // Defines pin-muxing selection
-                                              // for GPIO54
-#define GPIO_GPBMUX2_GPIO55_S     14
-#define GPIO_GPBMUX2_GPIO55_M     0xC000      // Defines pin-muxing selection
-                                              // for GPIO55
-#define GPIO_GPBMUX2_GPIO56_S     16
-#define GPIO_GPBMUX2_GPIO56_M     0x30000     // Defines pin-muxing selection
-                                              // for GPIO56
-#define GPIO_GPBMUX2_GPIO57_S     18
-#define GPIO_GPBMUX2_GPIO57_M     0xC0000     // Defines pin-muxing selection
-                                              // for GPIO57
-#define GPIO_GPBMUX2_GPIO58_S     20
-#define GPIO_GPBMUX2_GPIO58_M     0x300000    // Defines pin-muxing selection
-                                              // for GPIO58
-#define GPIO_GPBMUX2_GPIO59_S     22
-#define GPIO_GPBMUX2_GPIO59_M     0xC00000    // Defines pin-muxing selection
-                                              // for GPIO59
-#define GPIO_GPBMUX2_GPIO60_S     24
-#define GPIO_GPBMUX2_GPIO60_M     0x3000000   // Defines pin-muxing selection
-                                              // for GPIO60
-#define GPIO_GPBMUX2_GPIO61_S     26
-#define GPIO_GPBMUX2_GPIO61_M     0xC000000   // Defines pin-muxing selection
-                                              // for GPIO61
-#define GPIO_GPBMUX2_GPIO62_S     28
-#define GPIO_GPBMUX2_GPIO62_M     0x30000000  // Defines pin-muxing selection
-                                              // for GPIO62
-#define GPIO_GPBMUX2_GPIO63_S     30
-#define GPIO_GPBMUX2_GPIO63_M     0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO63
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBDIR register
-//
-//*****************************************************************************
-#define GPIO_GPBDIR_GPIO32        0x1         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO33        0x2         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO34        0x4         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO35        0x8         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO36        0x10        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO37        0x20        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO38        0x40        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO39        0x80        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO40        0x100       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO41        0x200       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO42        0x400       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO43        0x800       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO44        0x1000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO45        0x2000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO46        0x4000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO47        0x8000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO48        0x10000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO49        0x20000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO50        0x40000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO51        0x80000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO52        0x100000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO53        0x200000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO54        0x400000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO55        0x800000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO56        0x1000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO57        0x2000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO58        0x4000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO59        0x8000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO60        0x10000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO61        0x20000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO62        0x40000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPBDIR_GPIO63        0x80000000  // Defines direction for this pin
-                                              // in GPIO mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBPUD register
-//
-//*****************************************************************************
-#define GPIO_GPBPUD_GPIO32        0x1         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO33        0x2         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO34        0x4         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO35        0x8         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO36        0x10        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO37        0x20        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO38        0x40        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO39        0x80        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO40        0x100       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO41        0x200       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO42        0x400       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO43        0x800       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO44        0x1000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO45        0x2000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO46        0x4000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO47        0x8000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO48        0x10000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO49        0x20000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO50        0x40000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO51        0x80000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO52        0x100000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO53        0x200000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO54        0x400000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO55        0x800000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO56        0x1000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO57        0x2000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO58        0x4000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO59        0x8000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO60        0x10000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO61        0x20000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO62        0x40000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPBPUD_GPIO63        0x80000000  // Pull-Up Disable control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBINV register
-//
-//*****************************************************************************
-#define GPIO_GPBINV_GPIO32        0x1         // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO33        0x2         // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO34        0x4         // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO35        0x8         // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO36        0x10        // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO37        0x20        // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO38        0x40        // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO39        0x80        // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO40        0x100       // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO41        0x200       // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO42        0x400       // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO43        0x800       // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO44        0x1000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO45        0x2000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO46        0x4000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO47        0x8000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO48        0x10000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO49        0x20000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO50        0x40000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO51        0x80000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO52        0x100000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO53        0x200000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO54        0x400000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO55        0x800000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO56        0x1000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO57        0x2000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO58        0x4000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO59        0x8000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO60        0x10000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO61        0x20000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO62        0x40000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPBINV_GPIO63        0x80000000  // Input inversion control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBODR register
-//
-//*****************************************************************************
-#define GPIO_GPBODR_GPIO32        0x1         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO33        0x2         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO34        0x4         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO35        0x8         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO36        0x10        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO37        0x20        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO38        0x40        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO39        0x80        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO40        0x100       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO41        0x200       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO42        0x400       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO43        0x800       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO44        0x1000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO45        0x2000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO46        0x4000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO47        0x8000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO48        0x10000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO49        0x20000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO50        0x40000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO51        0x80000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO52        0x100000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO53        0x200000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO54        0x400000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO55        0x800000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO56        0x1000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO57        0x2000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO58        0x4000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO59        0x8000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO60        0x10000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO61        0x20000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO62        0x40000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPBODR_GPIO63        0x80000000  // Outpout Open-Drain control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBAMSEL register
-//
-//*****************************************************************************
-#define GPIO_GPBAMSEL_GPIO42      0x400       // Analog Mode select for this pin
-#define GPIO_GPBAMSEL_GPIO43      0x800       // Analog Mode select for this pin
-#define GPIO_GPBAMSEL_GPIO46      0x4000      // Analog Mode select for this pin
-#define GPIO_GPBAMSEL_GPIO47      0x8000      // Analog Mode select for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBGMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPBGMUX1_GPIO32_S    0
-#define GPIO_GPBGMUX1_GPIO32_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO32
-#define GPIO_GPBGMUX1_GPIO33_S    2
-#define GPIO_GPBGMUX1_GPIO33_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO33
-#define GPIO_GPBGMUX1_GPIO34_S    4
-#define GPIO_GPBGMUX1_GPIO34_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO34
-#define GPIO_GPBGMUX1_GPIO35_S    6
-#define GPIO_GPBGMUX1_GPIO35_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO35
-#define GPIO_GPBGMUX1_GPIO36_S    8
-#define GPIO_GPBGMUX1_GPIO36_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO36
-#define GPIO_GPBGMUX1_GPIO37_S    10
-#define GPIO_GPBGMUX1_GPIO37_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO37
-#define GPIO_GPBGMUX1_GPIO38_S    12
-#define GPIO_GPBGMUX1_GPIO38_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO38
-#define GPIO_GPBGMUX1_GPIO39_S    14
-#define GPIO_GPBGMUX1_GPIO39_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO39
-#define GPIO_GPBGMUX1_GPIO40_S    16
-#define GPIO_GPBGMUX1_GPIO40_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO40
-#define GPIO_GPBGMUX1_GPIO41_S    18
-#define GPIO_GPBGMUX1_GPIO41_M    0xC0000     // Defines pin-muxing selection
-                                              // for GPIO41
-#define GPIO_GPBGMUX1_GPIO42_S    20
-#define GPIO_GPBGMUX1_GPIO42_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO42
-#define GPIO_GPBGMUX1_GPIO43_S    22
-#define GPIO_GPBGMUX1_GPIO43_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO43
-#define GPIO_GPBGMUX1_GPIO44_S    24
-#define GPIO_GPBGMUX1_GPIO44_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO44
-#define GPIO_GPBGMUX1_GPIO45_S    26
-#define GPIO_GPBGMUX1_GPIO45_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO45
-#define GPIO_GPBGMUX1_GPIO46_S    28
-#define GPIO_GPBGMUX1_GPIO46_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO46
-#define GPIO_GPBGMUX1_GPIO47_S    30
-#define GPIO_GPBGMUX1_GPIO47_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO47
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBGMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPBGMUX2_GPIO48_S    0
-#define GPIO_GPBGMUX2_GPIO48_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO48
-#define GPIO_GPBGMUX2_GPIO49_S    2
-#define GPIO_GPBGMUX2_GPIO49_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO49
-#define GPIO_GPBGMUX2_GPIO50_S    4
-#define GPIO_GPBGMUX2_GPIO50_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO50
-#define GPIO_GPBGMUX2_GPIO51_S    6
-#define GPIO_GPBGMUX2_GPIO51_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO51
-#define GPIO_GPBGMUX2_GPIO52_S    8
-#define GPIO_GPBGMUX2_GPIO52_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO52
-#define GPIO_GPBGMUX2_GPIO53_S    10
-#define GPIO_GPBGMUX2_GPIO53_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO53
-#define GPIO_GPBGMUX2_GPIO54_S    12
-#define GPIO_GPBGMUX2_GPIO54_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO54
-#define GPIO_GPBGMUX2_GPIO55_S    14
-#define GPIO_GPBGMUX2_GPIO55_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO55
-#define GPIO_GPBGMUX2_GPIO56_S    16
-#define GPIO_GPBGMUX2_GPIO56_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO56
-#define GPIO_GPBGMUX2_GPIO57_S    18
-#define GPIO_GPBGMUX2_GPIO57_M    0xC0000     // Defines pin-muxing selection
-                                              // for GPIO57
-#define GPIO_GPBGMUX2_GPIO58_S    20
-#define GPIO_GPBGMUX2_GPIO58_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO58
-#define GPIO_GPBGMUX2_GPIO59_S    22
-#define GPIO_GPBGMUX2_GPIO59_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO59
-#define GPIO_GPBGMUX2_GPIO60_S    24
-#define GPIO_GPBGMUX2_GPIO60_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO60
-#define GPIO_GPBGMUX2_GPIO61_S    26
-#define GPIO_GPBGMUX2_GPIO61_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO61
-#define GPIO_GPBGMUX2_GPIO62_S    28
-#define GPIO_GPBGMUX2_GPIO62_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO62
-#define GPIO_GPBGMUX2_GPIO63_S    30
-#define GPIO_GPBGMUX2_GPIO63_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO63
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBCSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPBCSEL1_GPIO32_S    0
-#define GPIO_GPBCSEL1_GPIO32_M    0xF         // GPIO32 Master CPU Select
-#define GPIO_GPBCSEL1_GPIO33_S    4
-#define GPIO_GPBCSEL1_GPIO33_M    0xF0        // GPIO33 Master CPU Select
-#define GPIO_GPBCSEL1_GPIO34_S    8
-#define GPIO_GPBCSEL1_GPIO34_M    0xF00       // GPIO34 Master CPU Select
-#define GPIO_GPBCSEL1_GPIO35_S    12
-#define GPIO_GPBCSEL1_GPIO35_M    0xF000      // GPIO35 Master CPU Select
-#define GPIO_GPBCSEL1_GPIO36_S    16
-#define GPIO_GPBCSEL1_GPIO36_M    0xF0000     // GPIO36 Master CPU Select
-#define GPIO_GPBCSEL1_GPIO37_S    20
-#define GPIO_GPBCSEL1_GPIO37_M    0xF00000    // GPIO37 Master CPU Select
-#define GPIO_GPBCSEL1_GPIO38_S    24
-#define GPIO_GPBCSEL1_GPIO38_M    0xF000000   // GPIO38 Master CPU Select
-#define GPIO_GPBCSEL1_GPIO39_S    28
-#define GPIO_GPBCSEL1_GPIO39_M    0xF0000000  // GPIO39 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBCSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPBCSEL2_GPIO40_S    0
-#define GPIO_GPBCSEL2_GPIO40_M    0xF         // GPIO40 Master CPU Select
-#define GPIO_GPBCSEL2_GPIO41_S    4
-#define GPIO_GPBCSEL2_GPIO41_M    0xF0        // GPIO41 Master CPU Select
-#define GPIO_GPBCSEL2_GPIO42_S    8
-#define GPIO_GPBCSEL2_GPIO42_M    0xF00       // GPIO42 Master CPU Select
-#define GPIO_GPBCSEL2_GPIO43_S    12
-#define GPIO_GPBCSEL2_GPIO43_M    0xF000      // GPIO43 Master CPU Select
-#define GPIO_GPBCSEL2_GPIO44_S    16
-#define GPIO_GPBCSEL2_GPIO44_M    0xF0000     // GPIO44 Master CPU Select
-#define GPIO_GPBCSEL2_GPIO45_S    20
-#define GPIO_GPBCSEL2_GPIO45_M    0xF00000    // GPIO45 Master CPU Select
-#define GPIO_GPBCSEL2_GPIO46_S    24
-#define GPIO_GPBCSEL2_GPIO46_M    0xF000000   // GPIO46 Master CPU Select
-#define GPIO_GPBCSEL2_GPIO47_S    28
-#define GPIO_GPBCSEL2_GPIO47_M    0xF0000000  // GPIO47 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBCSEL3 register
-//
-//*****************************************************************************
-#define GPIO_GPBCSEL3_GPIO48_S    0
-#define GPIO_GPBCSEL3_GPIO48_M    0xF         // GPIO48 Master CPU Select
-#define GPIO_GPBCSEL3_GPIO49_S    4
-#define GPIO_GPBCSEL3_GPIO49_M    0xF0        // GPIO49 Master CPU Select
-#define GPIO_GPBCSEL3_GPIO50_S    8
-#define GPIO_GPBCSEL3_GPIO50_M    0xF00       // GPIO50 Master CPU Select
-#define GPIO_GPBCSEL3_GPIO51_S    12
-#define GPIO_GPBCSEL3_GPIO51_M    0xF000      // GPIO51 Master CPU Select
-#define GPIO_GPBCSEL3_GPIO52_S    16
-#define GPIO_GPBCSEL3_GPIO52_M    0xF0000     // GPIO52 Master CPU Select
-#define GPIO_GPBCSEL3_GPIO53_S    20
-#define GPIO_GPBCSEL3_GPIO53_M    0xF00000    // GPIO53 Master CPU Select
-#define GPIO_GPBCSEL3_GPIO54_S    24
-#define GPIO_GPBCSEL3_GPIO54_M    0xF000000   // GPIO54 Master CPU Select
-#define GPIO_GPBCSEL3_GPIO55_S    28
-#define GPIO_GPBCSEL3_GPIO55_M    0xF0000000  // GPIO55 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBCSEL4 register
-//
-//*****************************************************************************
-#define GPIO_GPBCSEL4_GPIO56_S    0
-#define GPIO_GPBCSEL4_GPIO56_M    0xF         // GPIO56 Master CPU Select
-#define GPIO_GPBCSEL4_GPIO57_S    4
-#define GPIO_GPBCSEL4_GPIO57_M    0xF0        // GPIO57 Master CPU Select
-#define GPIO_GPBCSEL4_GPIO58_S    8
-#define GPIO_GPBCSEL4_GPIO58_M    0xF00       // GPIO58 Master CPU Select
-#define GPIO_GPBCSEL4_GPIO59_S    12
-#define GPIO_GPBCSEL4_GPIO59_M    0xF000      // GPIO59 Master CPU Select
-#define GPIO_GPBCSEL4_GPIO60_S    16
-#define GPIO_GPBCSEL4_GPIO60_M    0xF0000     // GPIO60 Master CPU Select
-#define GPIO_GPBCSEL4_GPIO61_S    20
-#define GPIO_GPBCSEL4_GPIO61_M    0xF00000    // GPIO61 Master CPU Select
-#define GPIO_GPBCSEL4_GPIO62_S    24
-#define GPIO_GPBCSEL4_GPIO62_M    0xF000000   // GPIO62 Master CPU Select
-#define GPIO_GPBCSEL4_GPIO63_S    28
-#define GPIO_GPBCSEL4_GPIO63_M    0xF0000000  // GPIO63 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBLOCK register
-//
-//*****************************************************************************
-#define GPIO_GPBLOCK_GPIO32       0x1         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO33       0x2         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO34       0x4         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO35       0x8         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO36       0x10        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO37       0x20        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO38       0x40        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO39       0x80        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO40       0x100       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO41       0x200       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO42       0x400       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO43       0x800       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO44       0x1000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO45       0x2000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO46       0x4000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO47       0x8000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO48       0x10000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO49       0x20000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO50       0x40000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO51       0x80000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO52       0x100000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO53       0x200000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO54       0x400000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO55       0x800000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO56       0x1000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO57       0x2000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO58       0x4000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO59       0x8000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO60       0x10000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO61       0x20000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO62       0x40000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPBLOCK_GPIO63       0x80000000  // Configuration Lock bit for this
-                                              // pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBCR register
-//
-//*****************************************************************************
-#define GPIO_GPBCR_GPIO32         0x1         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO33         0x2         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO34         0x4         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO35         0x8         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO36         0x10        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO37         0x20        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO38         0x40        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO39         0x80        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO40         0x100       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO41         0x200       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO42         0x400       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO43         0x800       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO44         0x1000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO45         0x2000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO46         0x4000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO47         0x8000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO48         0x10000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO49         0x20000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO50         0x40000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO51         0x80000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO52         0x100000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO53         0x200000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO54         0x400000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO55         0x800000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO56         0x1000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO57         0x2000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO58         0x4000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO59         0x8000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO60         0x10000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO61         0x20000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO62         0x40000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPBCR_GPIO63         0x80000000  // Configuration lock commit bit
-                                              // for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCCTRL register
-//
-//*****************************************************************************
-#define GPIO_GPCCTRL_QUALPRD0_S   0
-#define GPIO_GPCCTRL_QUALPRD0_M   0xFF        // Qualification sampling period
-                                              // for GPIO64 to GPIO71
-#define GPIO_GPCCTRL_QUALPRD1_S   8
-#define GPIO_GPCCTRL_QUALPRD1_M   0xFF00      // Qualification sampling period
-                                              // for GPIO72 to GPIO79
-#define GPIO_GPCCTRL_QUALPRD2_S   16
-#define GPIO_GPCCTRL_QUALPRD2_M   0xFF0000    // Qualification sampling period
-                                              // for GPIO80 to GPIO87
-#define GPIO_GPCCTRL_QUALPRD3_S   24
-#define GPIO_GPCCTRL_QUALPRD3_M   0xFF000000  // Qualification sampling period
-                                              // for GPIO88 to GPIO95
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCQSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPCQSEL1_GPIO64_S    0
-#define GPIO_GPCQSEL1_GPIO64_M    0x3         // Select input qualification type
-                                              // for GPIO64
-#define GPIO_GPCQSEL1_GPIO65_S    2
-#define GPIO_GPCQSEL1_GPIO65_M    0xC         // Select input qualification type
-                                              // for GPIO65
-#define GPIO_GPCQSEL1_GPIO66_S    4
-#define GPIO_GPCQSEL1_GPIO66_M    0x30        // Select input qualification type
-                                              // for GPIO66
-#define GPIO_GPCQSEL1_GPIO67_S    6
-#define GPIO_GPCQSEL1_GPIO67_M    0xC0        // Select input qualification type
-                                              // for GPIO67
-#define GPIO_GPCQSEL1_GPIO68_S    8
-#define GPIO_GPCQSEL1_GPIO68_M    0x300       // Select input qualification type
-                                              // for GPIO68
-#define GPIO_GPCQSEL1_GPIO69_S    10
-#define GPIO_GPCQSEL1_GPIO69_M    0xC00       // Select input qualification type
-                                              // for GPIO69
-#define GPIO_GPCQSEL1_GPIO70_S    12
-#define GPIO_GPCQSEL1_GPIO70_M    0x3000      // Select input qualification type
-                                              // for GPIO70
-#define GPIO_GPCQSEL1_GPIO71_S    14
-#define GPIO_GPCQSEL1_GPIO71_M    0xC000      // Select input qualification type
-                                              // for GPIO71
-#define GPIO_GPCQSEL1_GPIO72_S    16
-#define GPIO_GPCQSEL1_GPIO72_M    0x30000     // Select input qualification type
-                                              // for GPIO72
-#define GPIO_GPCQSEL1_GPIO73_S    18
-#define GPIO_GPCQSEL1_GPIO73_M    0xC0000     // Select input qualification type
-                                              // for GPIO73
-#define GPIO_GPCQSEL1_GPIO74_S    20
-#define GPIO_GPCQSEL1_GPIO74_M    0x300000    // Select input qualification type
-                                              // for GPIO74
-#define GPIO_GPCQSEL1_GPIO75_S    22
-#define GPIO_GPCQSEL1_GPIO75_M    0xC00000    // Select input qualification type
-                                              // for GPIO75
-#define GPIO_GPCQSEL1_GPIO76_S    24
-#define GPIO_GPCQSEL1_GPIO76_M    0x3000000   // Select input qualification type
-                                              // for GPIO76
-#define GPIO_GPCQSEL1_GPIO77_S    26
-#define GPIO_GPCQSEL1_GPIO77_M    0xC000000   // Select input qualification type
-                                              // for GPIO77
-#define GPIO_GPCQSEL1_GPIO78_S    28
-#define GPIO_GPCQSEL1_GPIO78_M    0x30000000  // Select input qualification type
-                                              // for GPIO78
-#define GPIO_GPCQSEL1_GPIO79_S    30
-#define GPIO_GPCQSEL1_GPIO79_M    0xC0000000  // Select input qualification type
-                                              // for GPIO79
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCQSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPCQSEL2_GPIO80_S    0
-#define GPIO_GPCQSEL2_GPIO80_M    0x3         // Select input qualification type
-                                              // for GPIO80
-#define GPIO_GPCQSEL2_GPIO81_S    2
-#define GPIO_GPCQSEL2_GPIO81_M    0xC         // Select input qualification type
-                                              // for GPIO81
-#define GPIO_GPCQSEL2_GPIO82_S    4
-#define GPIO_GPCQSEL2_GPIO82_M    0x30        // Select input qualification type
-                                              // for GPIO82
-#define GPIO_GPCQSEL2_GPIO83_S    6
-#define GPIO_GPCQSEL2_GPIO83_M    0xC0        // Select input qualification type
-                                              // for GPIO83
-#define GPIO_GPCQSEL2_GPIO84_S    8
-#define GPIO_GPCQSEL2_GPIO84_M    0x300       // Select input qualification type
-                                              // for GPIO84
-#define GPIO_GPCQSEL2_GPIO85_S    10
-#define GPIO_GPCQSEL2_GPIO85_M    0xC00       // Select input qualification type
-                                              // for GPIO85
-#define GPIO_GPCQSEL2_GPIO86_S    12
-#define GPIO_GPCQSEL2_GPIO86_M    0x3000      // Select input qualification type
-                                              // for GPIO86
-#define GPIO_GPCQSEL2_GPIO87_S    14
-#define GPIO_GPCQSEL2_GPIO87_M    0xC000      // Select input qualification type
-                                              // for GPIO87
-#define GPIO_GPCQSEL2_GPIO88_S    16
-#define GPIO_GPCQSEL2_GPIO88_M    0x30000     // Select input qualification type
-                                              // for GPIO88
-#define GPIO_GPCQSEL2_GPIO89_S    18
-#define GPIO_GPCQSEL2_GPIO89_M    0xC0000     // Select input qualification type
-                                              // for GPIO89
-#define GPIO_GPCQSEL2_GPIO90_S    20
-#define GPIO_GPCQSEL2_GPIO90_M    0x300000    // Select input qualification type
-                                              // for GPIO90
-#define GPIO_GPCQSEL2_GPIO91_S    22
-#define GPIO_GPCQSEL2_GPIO91_M    0xC00000    // Select input qualification type
-                                              // for GPIO91
-#define GPIO_GPCQSEL2_GPIO92_S    24
-#define GPIO_GPCQSEL2_GPIO92_M    0x3000000   // Select input qualification type
-                                              // for GPIO92
-#define GPIO_GPCQSEL2_GPIO93_S    26
-#define GPIO_GPCQSEL2_GPIO93_M    0xC000000   // Select input qualification type
-                                              // for GPIO93
-#define GPIO_GPCQSEL2_GPIO94_S    28
-#define GPIO_GPCQSEL2_GPIO94_M    0x30000000  // Select input qualification type
-                                              // for GPIO94
-#define GPIO_GPCQSEL2_GPIO95_S    30
-#define GPIO_GPCQSEL2_GPIO95_M    0xC0000000  // Select input qualification type
-                                              // for GPIO95
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPCMUX1_GPIO64_S     0
-#define GPIO_GPCMUX1_GPIO64_M     0x3         // Defines pin-muxing selection
-                                              // for GPIO64
-#define GPIO_GPCMUX1_GPIO65_S     2
-#define GPIO_GPCMUX1_GPIO65_M     0xC         // Defines pin-muxing selection
-                                              // for GPIO65
-#define GPIO_GPCMUX1_GPIO66_S     4
-#define GPIO_GPCMUX1_GPIO66_M     0x30        // Defines pin-muxing selection
-                                              // for GPIO66
-#define GPIO_GPCMUX1_GPIO67_S     6
-#define GPIO_GPCMUX1_GPIO67_M     0xC0        // Defines pin-muxing selection
-                                              // for GPIO67
-#define GPIO_GPCMUX1_GPIO68_S     8
-#define GPIO_GPCMUX1_GPIO68_M     0x300       // Defines pin-muxing selection
-                                              // for GPIO68
-#define GPIO_GPCMUX1_GPIO69_S     10
-#define GPIO_GPCMUX1_GPIO69_M     0xC00       // Defines pin-muxing selection
-                                              // for GPIO69
-#define GPIO_GPCMUX1_GPIO70_S     12
-#define GPIO_GPCMUX1_GPIO70_M     0x3000      // Defines pin-muxing selection
-                                              // for GPIO70
-#define GPIO_GPCMUX1_GPIO71_S     14
-#define GPIO_GPCMUX1_GPIO71_M     0xC000      // Defines pin-muxing selection
-                                              // for GPIO71
-#define GPIO_GPCMUX1_GPIO72_S     16
-#define GPIO_GPCMUX1_GPIO72_M     0x30000     // Defines pin-muxing selection
-                                              // for GPIO72
-#define GPIO_GPCMUX1_GPIO73_S     18
-#define GPIO_GPCMUX1_GPIO73_M     0xC0000     // Defines pin-muxing selection
-                                              // for GPIO73
-#define GPIO_GPCMUX1_GPIO74_S     20
-#define GPIO_GPCMUX1_GPIO74_M     0x300000    // Defines pin-muxing selection
-                                              // for GPIO74
-#define GPIO_GPCMUX1_GPIO75_S     22
-#define GPIO_GPCMUX1_GPIO75_M     0xC00000    // Defines pin-muxing selection
-                                              // for GPIO75
-#define GPIO_GPCMUX1_GPIO76_S     24
-#define GPIO_GPCMUX1_GPIO76_M     0x3000000   // Defines pin-muxing selection
-                                              // for GPIO76
-#define GPIO_GPCMUX1_GPIO77_S     26
-#define GPIO_GPCMUX1_GPIO77_M     0xC000000   // Defines pin-muxing selection
-                                              // for GPIO77
-#define GPIO_GPCMUX1_GPIO78_S     28
-#define GPIO_GPCMUX1_GPIO78_M     0x30000000  // Defines pin-muxing selection
-                                              // for GPIO78
-#define GPIO_GPCMUX1_GPIO79_S     30
-#define GPIO_GPCMUX1_GPIO79_M     0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO79
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPCMUX2_GPIO80_S     0
-#define GPIO_GPCMUX2_GPIO80_M     0x3         // Defines pin-muxing selection
-                                              // for GPIO80
-#define GPIO_GPCMUX2_GPIO81_S     2
-#define GPIO_GPCMUX2_GPIO81_M     0xC         // Defines pin-muxing selection
-                                              // for GPIO81
-#define GPIO_GPCMUX2_GPIO82_S     4
-#define GPIO_GPCMUX2_GPIO82_M     0x30        // Defines pin-muxing selection
-                                              // for GPIO82
-#define GPIO_GPCMUX2_GPIO83_S     6
-#define GPIO_GPCMUX2_GPIO83_M     0xC0        // Defines pin-muxing selection
-                                              // for GPIO83
-#define GPIO_GPCMUX2_GPIO84_S     8
-#define GPIO_GPCMUX2_GPIO84_M     0x300       // Defines pin-muxing selection
-                                              // for GPIO84
-#define GPIO_GPCMUX2_GPIO85_S     10
-#define GPIO_GPCMUX2_GPIO85_M     0xC00       // Defines pin-muxing selection
-                                              // for GPIO85
-#define GPIO_GPCMUX2_GPIO86_S     12
-#define GPIO_GPCMUX2_GPIO86_M     0x3000      // Defines pin-muxing selection
-                                              // for GPIO86
-#define GPIO_GPCMUX2_GPIO87_S     14
-#define GPIO_GPCMUX2_GPIO87_M     0xC000      // Defines pin-muxing selection
-                                              // for GPIO87
-#define GPIO_GPCMUX2_GPIO88_S     16
-#define GPIO_GPCMUX2_GPIO88_M     0x30000     // Defines pin-muxing selection
-                                              // for GPIO88
-#define GPIO_GPCMUX2_GPIO89_S     18
-#define GPIO_GPCMUX2_GPIO89_M     0xC0000     // Defines pin-muxing selection
-                                              // for GPIO89
-#define GPIO_GPCMUX2_GPIO90_S     20
-#define GPIO_GPCMUX2_GPIO90_M     0x300000    // Defines pin-muxing selection
-                                              // for GPIO90
-#define GPIO_GPCMUX2_GPIO91_S     22
-#define GPIO_GPCMUX2_GPIO91_M     0xC00000    // Defines pin-muxing selection
-                                              // for GPIO91
-#define GPIO_GPCMUX2_GPIO92_S     24
-#define GPIO_GPCMUX2_GPIO92_M     0x3000000   // Defines pin-muxing selection
-                                              // for GPIO92
-#define GPIO_GPCMUX2_GPIO93_S     26
-#define GPIO_GPCMUX2_GPIO93_M     0xC000000   // Defines pin-muxing selection
-                                              // for GPIO93
-#define GPIO_GPCMUX2_GPIO94_S     28
-#define GPIO_GPCMUX2_GPIO94_M     0x30000000  // Defines pin-muxing selection
-                                              // for GPIO94
-#define GPIO_GPCMUX2_GPIO95_S     30
-#define GPIO_GPCMUX2_GPIO95_M     0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO95
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCDIR register
-//
-//*****************************************************************************
-#define GPIO_GPCDIR_GPIO64        0x1         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO65        0x2         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO66        0x4         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO67        0x8         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO68        0x10        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO69        0x20        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO70        0x40        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO71        0x80        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO72        0x100       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO73        0x200       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO74        0x400       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO75        0x800       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO76        0x1000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO77        0x2000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO78        0x4000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO79        0x8000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO80        0x10000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO81        0x20000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO82        0x40000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO83        0x80000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO84        0x100000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO85        0x200000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO86        0x400000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO87        0x800000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO88        0x1000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO89        0x2000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO90        0x4000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO91        0x8000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO92        0x10000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO93        0x20000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO94        0x40000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPCDIR_GPIO95        0x80000000  // Defines direction for this pin
-                                              // in GPIO mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCPUD register
-//
-//*****************************************************************************
-#define GPIO_GPCPUD_GPIO64        0x1         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO65        0x2         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO66        0x4         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO67        0x8         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO68        0x10        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO69        0x20        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO70        0x40        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO71        0x80        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO72        0x100       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO73        0x200       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO74        0x400       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO75        0x800       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO76        0x1000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO77        0x2000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO78        0x4000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO79        0x8000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO80        0x10000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO81        0x20000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO82        0x40000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO83        0x80000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO84        0x100000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO85        0x200000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO86        0x400000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO87        0x800000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO88        0x1000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO89        0x2000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO90        0x4000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO91        0x8000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO92        0x10000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO93        0x20000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO94        0x40000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPCPUD_GPIO95        0x80000000  // Pull-Up Disable control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCINV register
-//
-//*****************************************************************************
-#define GPIO_GPCINV_GPIO64        0x1         // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO65        0x2         // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO66        0x4         // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO67        0x8         // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO68        0x10        // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO69        0x20        // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO70        0x40        // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO71        0x80        // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO72        0x100       // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO73        0x200       // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO74        0x400       // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO75        0x800       // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO76        0x1000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO77        0x2000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO78        0x4000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO79        0x8000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO80        0x10000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO81        0x20000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO82        0x40000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO83        0x80000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO84        0x100000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO85        0x200000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO86        0x400000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO87        0x800000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO88        0x1000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO89        0x2000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO90        0x4000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO91        0x8000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO92        0x10000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO93        0x20000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO94        0x40000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPCINV_GPIO95        0x80000000  // Input inversion control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCODR register
-//
-//*****************************************************************************
-#define GPIO_GPCODR_GPIO64        0x1         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO65        0x2         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO66        0x4         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO67        0x8         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO68        0x10        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO69        0x20        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO70        0x40        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO71        0x80        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO72        0x100       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO73        0x200       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO74        0x400       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO75        0x800       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO76        0x1000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO77        0x2000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO78        0x4000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO79        0x8000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO80        0x10000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO81        0x20000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO82        0x40000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO83        0x80000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO84        0x100000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO85        0x200000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO86        0x400000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO87        0x800000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO88        0x1000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO89        0x2000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO90        0x4000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO91        0x8000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO92        0x10000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO93        0x20000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO94        0x40000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPCODR_GPIO95        0x80000000  // Outpout Open-Drain control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCGMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPCGMUX1_GPIO64_S    0
-#define GPIO_GPCGMUX1_GPIO64_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO64
-#define GPIO_GPCGMUX1_GPIO65_S    2
-#define GPIO_GPCGMUX1_GPIO65_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO65
-#define GPIO_GPCGMUX1_GPIO66_S    4
-#define GPIO_GPCGMUX1_GPIO66_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO66
-#define GPIO_GPCGMUX1_GPIO67_S    6
-#define GPIO_GPCGMUX1_GPIO67_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO67
-#define GPIO_GPCGMUX1_GPIO68_S    8
-#define GPIO_GPCGMUX1_GPIO68_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO68
-#define GPIO_GPCGMUX1_GPIO69_S    10
-#define GPIO_GPCGMUX1_GPIO69_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO69
-#define GPIO_GPCGMUX1_GPIO70_S    12
-#define GPIO_GPCGMUX1_GPIO70_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO70
-#define GPIO_GPCGMUX1_GPIO71_S    14
-#define GPIO_GPCGMUX1_GPIO71_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO71
-#define GPIO_GPCGMUX1_GPIO72_S    16
-#define GPIO_GPCGMUX1_GPIO72_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO72
-#define GPIO_GPCGMUX1_GPIO73_S    18
-#define GPIO_GPCGMUX1_GPIO73_M    0xC0000     // Defines pin-muxing selection
-                                              // for GPIO73
-#define GPIO_GPCGMUX1_GPIO74_S    20
-#define GPIO_GPCGMUX1_GPIO74_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO74
-#define GPIO_GPCGMUX1_GPIO75_S    22
-#define GPIO_GPCGMUX1_GPIO75_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO75
-#define GPIO_GPCGMUX1_GPIO76_S    24
-#define GPIO_GPCGMUX1_GPIO76_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO76
-#define GPIO_GPCGMUX1_GPIO77_S    26
-#define GPIO_GPCGMUX1_GPIO77_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO77
-#define GPIO_GPCGMUX1_GPIO78_S    28
-#define GPIO_GPCGMUX1_GPIO78_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO78
-#define GPIO_GPCGMUX1_GPIO79_S    30
-#define GPIO_GPCGMUX1_GPIO79_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO79
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCGMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPCGMUX2_GPIO80_S    0
-#define GPIO_GPCGMUX2_GPIO80_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO80
-#define GPIO_GPCGMUX2_GPIO81_S    2
-#define GPIO_GPCGMUX2_GPIO81_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO81
-#define GPIO_GPCGMUX2_GPIO82_S    4
-#define GPIO_GPCGMUX2_GPIO82_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO82
-#define GPIO_GPCGMUX2_GPIO83_S    6
-#define GPIO_GPCGMUX2_GPIO83_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO83
-#define GPIO_GPCGMUX2_GPIO84_S    8
-#define GPIO_GPCGMUX2_GPIO84_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO84
-#define GPIO_GPCGMUX2_GPIO85_S    10
-#define GPIO_GPCGMUX2_GPIO85_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO85
-#define GPIO_GPCGMUX2_GPIO86_S    12
-#define GPIO_GPCGMUX2_GPIO86_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO86
-#define GPIO_GPCGMUX2_GPIO87_S    14
-#define GPIO_GPCGMUX2_GPIO87_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO87
-#define GPIO_GPCGMUX2_GPIO88_S    16
-#define GPIO_GPCGMUX2_GPIO88_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO88
-#define GPIO_GPCGMUX2_GPIO89_S    18
-#define GPIO_GPCGMUX2_GPIO89_M    0xC0000     // Defines pin-muxing selection
-                                              // for GPIO89
-#define GPIO_GPCGMUX2_GPIO90_S    20
-#define GPIO_GPCGMUX2_GPIO90_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO90
-#define GPIO_GPCGMUX2_GPIO91_S    22
-#define GPIO_GPCGMUX2_GPIO91_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO91
-#define GPIO_GPCGMUX2_GPIO92_S    24
-#define GPIO_GPCGMUX2_GPIO92_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO92
-#define GPIO_GPCGMUX2_GPIO93_S    26
-#define GPIO_GPCGMUX2_GPIO93_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO93
-#define GPIO_GPCGMUX2_GPIO94_S    28
-#define GPIO_GPCGMUX2_GPIO94_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO94
-#define GPIO_GPCGMUX2_GPIO95_S    30
-#define GPIO_GPCGMUX2_GPIO95_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO95
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCCSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPCCSEL1_GPIO64_S    0
-#define GPIO_GPCCSEL1_GPIO64_M    0xF         // GPIO64 Master CPU Select
-#define GPIO_GPCCSEL1_GPIO65_S    4
-#define GPIO_GPCCSEL1_GPIO65_M    0xF0        // GPIO65 Master CPU Select
-#define GPIO_GPCCSEL1_GPIO66_S    8
-#define GPIO_GPCCSEL1_GPIO66_M    0xF00       // GPIO66 Master CPU Select
-#define GPIO_GPCCSEL1_GPIO67_S    12
-#define GPIO_GPCCSEL1_GPIO67_M    0xF000      // GPIO67 Master CPU Select
-#define GPIO_GPCCSEL1_GPIO68_S    16
-#define GPIO_GPCCSEL1_GPIO68_M    0xF0000     // GPIO68 Master CPU Select
-#define GPIO_GPCCSEL1_GPIO69_S    20
-#define GPIO_GPCCSEL1_GPIO69_M    0xF00000    // GPIO69 Master CPU Select
-#define GPIO_GPCCSEL1_GPIO70_S    24
-#define GPIO_GPCCSEL1_GPIO70_M    0xF000000   // GPIO70 Master CPU Select
-#define GPIO_GPCCSEL1_GPIO71_S    28
-#define GPIO_GPCCSEL1_GPIO71_M    0xF0000000  // GPIO71 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCCSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPCCSEL2_GPIO72_S    0
-#define GPIO_GPCCSEL2_GPIO72_M    0xF         // GPIO72 Master CPU Select
-#define GPIO_GPCCSEL2_GPIO73_S    4
-#define GPIO_GPCCSEL2_GPIO73_M    0xF0        // GPIO73 Master CPU Select
-#define GPIO_GPCCSEL2_GPIO74_S    8
-#define GPIO_GPCCSEL2_GPIO74_M    0xF00       // GPIO74 Master CPU Select
-#define GPIO_GPCCSEL2_GPIO75_S    12
-#define GPIO_GPCCSEL2_GPIO75_M    0xF000      // GPIO75 Master CPU Select
-#define GPIO_GPCCSEL2_GPIO76_S    16
-#define GPIO_GPCCSEL2_GPIO76_M    0xF0000     // GPIO76 Master CPU Select
-#define GPIO_GPCCSEL2_GPIO77_S    20
-#define GPIO_GPCCSEL2_GPIO77_M    0xF00000    // GPIO77 Master CPU Select
-#define GPIO_GPCCSEL2_GPIO78_S    24
-#define GPIO_GPCCSEL2_GPIO78_M    0xF000000   // GPIO78 Master CPU Select
-#define GPIO_GPCCSEL2_GPIO79_S    28
-#define GPIO_GPCCSEL2_GPIO79_M    0xF0000000  // GPIO79 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCCSEL3 register
-//
-//*****************************************************************************
-#define GPIO_GPCCSEL3_GPIO80_S    0
-#define GPIO_GPCCSEL3_GPIO80_M    0xF         // GPIO80 Master CPU Select
-#define GPIO_GPCCSEL3_GPIO81_S    4
-#define GPIO_GPCCSEL3_GPIO81_M    0xF0        // GPIO81 Master CPU Select
-#define GPIO_GPCCSEL3_GPIO82_S    8
-#define GPIO_GPCCSEL3_GPIO82_M    0xF00       // GPIO82 Master CPU Select
-#define GPIO_GPCCSEL3_GPIO83_S    12
-#define GPIO_GPCCSEL3_GPIO83_M    0xF000      // GPIO83 Master CPU Select
-#define GPIO_GPCCSEL3_GPIO84_S    16
-#define GPIO_GPCCSEL3_GPIO84_M    0xF0000     // GPIO84 Master CPU Select
-#define GPIO_GPCCSEL3_GPIO85_S    20
-#define GPIO_GPCCSEL3_GPIO85_M    0xF00000    // GPIO85 Master CPU Select
-#define GPIO_GPCCSEL3_GPIO86_S    24
-#define GPIO_GPCCSEL3_GPIO86_M    0xF000000   // GPIO86 Master CPU Select
-#define GPIO_GPCCSEL3_GPIO87_S    28
-#define GPIO_GPCCSEL3_GPIO87_M    0xF0000000  // GPIO87 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCCSEL4 register
-//
-//*****************************************************************************
-#define GPIO_GPCCSEL4_GPIO88_S    0
-#define GPIO_GPCCSEL4_GPIO88_M    0xF         // GPIO88 Master CPU Select
-#define GPIO_GPCCSEL4_GPIO89_S    4
-#define GPIO_GPCCSEL4_GPIO89_M    0xF0        // GPIO89 Master CPU Select
-#define GPIO_GPCCSEL4_GPIO90_S    8
-#define GPIO_GPCCSEL4_GPIO90_M    0xF00       // GPIO90 Master CPU Select
-#define GPIO_GPCCSEL4_GPIO91_S    12
-#define GPIO_GPCCSEL4_GPIO91_M    0xF000      // GPIO91 Master CPU Select
-#define GPIO_GPCCSEL4_GPIO92_S    16
-#define GPIO_GPCCSEL4_GPIO92_M    0xF0000     // GPIO92 Master CPU Select
-#define GPIO_GPCCSEL4_GPIO93_S    20
-#define GPIO_GPCCSEL4_GPIO93_M    0xF00000    // GPIO93 Master CPU Select
-#define GPIO_GPCCSEL4_GPIO94_S    24
-#define GPIO_GPCCSEL4_GPIO94_M    0xF000000   // GPIO94 Master CPU Select
-#define GPIO_GPCCSEL4_GPIO95_S    28
-#define GPIO_GPCCSEL4_GPIO95_M    0xF0000000  // GPIO95 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCLOCK register
-//
-//*****************************************************************************
-#define GPIO_GPCLOCK_GPIO64       0x1         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO65       0x2         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO66       0x4         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO67       0x8         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO68       0x10        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO69       0x20        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO70       0x40        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO71       0x80        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO72       0x100       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO73       0x200       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO74       0x400       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO75       0x800       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO76       0x1000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO77       0x2000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO78       0x4000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO79       0x8000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO80       0x10000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO81       0x20000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO82       0x40000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO83       0x80000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO84       0x100000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO85       0x200000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO86       0x400000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO87       0x800000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO88       0x1000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO89       0x2000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO90       0x4000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO91       0x8000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO92       0x10000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO93       0x20000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO94       0x40000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPCLOCK_GPIO95       0x80000000  // Configuration Lock bit for this
-                                              // pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCCR register
-//
-//*****************************************************************************
-#define GPIO_GPCCR_GPIO64         0x1         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO65         0x2         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO66         0x4         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO67         0x8         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO68         0x10        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO69         0x20        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO70         0x40        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO71         0x80        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO72         0x100       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO73         0x200       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO74         0x400       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO75         0x800       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO76         0x1000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO77         0x2000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO78         0x4000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO79         0x8000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO80         0x10000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO81         0x20000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO82         0x40000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO83         0x80000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO84         0x100000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO85         0x200000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO86         0x400000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO87         0x800000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO88         0x1000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO89         0x2000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO90         0x4000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO91         0x8000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO92         0x10000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO93         0x20000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO94         0x40000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPCCR_GPIO95         0x80000000  // Configuration lock commit bit
-                                              // for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDCTRL register
-//
-//*****************************************************************************
-#define GPIO_GPDCTRL_QUALPRD0_S   0
-#define GPIO_GPDCTRL_QUALPRD0_M   0xFF        // Qualification sampling period
-                                              // for GPIO96 to GPIO103
-#define GPIO_GPDCTRL_QUALPRD1_S   8
-#define GPIO_GPDCTRL_QUALPRD1_M   0xFF00      // Qualification sampling period
-                                              // for GPIO104 to GPIO111
-#define GPIO_GPDCTRL_QUALPRD2_S   16
-#define GPIO_GPDCTRL_QUALPRD2_M   0xFF0000    // Qualification sampling period
-                                              // for GPIO112 to GPIO119
-#define GPIO_GPDCTRL_QUALPRD3_S   24
-#define GPIO_GPDCTRL_QUALPRD3_M   0xFF000000  // Qualification sampling period
-                                              // for GPIO120 to GPIO127
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDQSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPDQSEL1_GPIO96_S    0
-#define GPIO_GPDQSEL1_GPIO96_M    0x3         // Select input qualification type
-                                              // for GPIO96
-#define GPIO_GPDQSEL1_GPIO97_S    2
-#define GPIO_GPDQSEL1_GPIO97_M    0xC         // Select input qualification type
-                                              // for GPIO97
-#define GPIO_GPDQSEL1_GPIO98_S    4
-#define GPIO_GPDQSEL1_GPIO98_M    0x30        // Select input qualification type
-                                              // for GPIO98
-#define GPIO_GPDQSEL1_GPIO99_S    6
-#define GPIO_GPDQSEL1_GPIO99_M    0xC0        // Select input qualification type
-                                              // for GPIO99
-#define GPIO_GPDQSEL1_GPIO100_S   8
-#define GPIO_GPDQSEL1_GPIO100_M   0x300       // Select input qualification type
-                                              // for GPIO100
-#define GPIO_GPDQSEL1_GPIO101_S   10
-#define GPIO_GPDQSEL1_GPIO101_M   0xC00       // Select input qualification type
-                                              // for GPIO101
-#define GPIO_GPDQSEL1_GPIO102_S   12
-#define GPIO_GPDQSEL1_GPIO102_M   0x3000      // Select input qualification type
-                                              // for GPIO102
-#define GPIO_GPDQSEL1_GPIO103_S   14
-#define GPIO_GPDQSEL1_GPIO103_M   0xC000      // Select input qualification type
-                                              // for GPIO103
-#define GPIO_GPDQSEL1_GPIO104_S   16
-#define GPIO_GPDQSEL1_GPIO104_M   0x30000     // Select input qualification type
-                                              // for GPIO104
-#define GPIO_GPDQSEL1_GPIO105_S   18
-#define GPIO_GPDQSEL1_GPIO105_M   0xC0000     // Select input qualification type
-                                              // for GPIO105
-#define GPIO_GPDQSEL1_GPIO106_S   20
-#define GPIO_GPDQSEL1_GPIO106_M   0x300000    // Select input qualification type
-                                              // for GPIO106
-#define GPIO_GPDQSEL1_GPIO107_S   22
-#define GPIO_GPDQSEL1_GPIO107_M   0xC00000    // Select input qualification type
-                                              // for GPIO107
-#define GPIO_GPDQSEL1_GPIO108_S   24
-#define GPIO_GPDQSEL1_GPIO108_M   0x3000000   // Select input qualification type
-                                              // for GPIO108
-#define GPIO_GPDQSEL1_GPIO109_S   26
-#define GPIO_GPDQSEL1_GPIO109_M   0xC000000   // Select input qualification type
-                                              // for GPIO109
-#define GPIO_GPDQSEL1_GPIO110_S   28
-#define GPIO_GPDQSEL1_GPIO110_M   0x30000000  // Select input qualification type
-                                              // for GPIO110
-#define GPIO_GPDQSEL1_GPIO111_S   30
-#define GPIO_GPDQSEL1_GPIO111_M   0xC0000000  // Select input qualification type
-                                              // for GPIO111
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDQSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPDQSEL2_GPIO112_S   0
-#define GPIO_GPDQSEL2_GPIO112_M   0x3         // Select input qualification type
-                                              // for GPIO112
-#define GPIO_GPDQSEL2_GPIO113_S   2
-#define GPIO_GPDQSEL2_GPIO113_M   0xC         // Select input qualification type
-                                              // for GPIO113
-#define GPIO_GPDQSEL2_GPIO114_S   4
-#define GPIO_GPDQSEL2_GPIO114_M   0x30        // Select input qualification type
-                                              // for GPIO114
-#define GPIO_GPDQSEL2_GPIO115_S   6
-#define GPIO_GPDQSEL2_GPIO115_M   0xC0        // Select input qualification type
-                                              // for GPIO115
-#define GPIO_GPDQSEL2_GPIO116_S   8
-#define GPIO_GPDQSEL2_GPIO116_M   0x300       // Select input qualification type
-                                              // for GPIO116
-#define GPIO_GPDQSEL2_GPIO117_S   10
-#define GPIO_GPDQSEL2_GPIO117_M   0xC00       // Select input qualification type
-                                              // for GPIO117
-#define GPIO_GPDQSEL2_GPIO118_S   12
-#define GPIO_GPDQSEL2_GPIO118_M   0x3000      // Select input qualification type
-                                              // for GPIO118
-#define GPIO_GPDQSEL2_GPIO119_S   14
-#define GPIO_GPDQSEL2_GPIO119_M   0xC000      // Select input qualification type
-                                              // for GPIO119
-#define GPIO_GPDQSEL2_GPIO120_S   16
-#define GPIO_GPDQSEL2_GPIO120_M   0x30000     // Select input qualification type
-                                              // for GPIO120
-#define GPIO_GPDQSEL2_GPIO121_S   18
-#define GPIO_GPDQSEL2_GPIO121_M   0xC0000     // Select input qualification type
-                                              // for GPIO121
-#define GPIO_GPDQSEL2_GPIO122_S   20
-#define GPIO_GPDQSEL2_GPIO122_M   0x300000    // Select input qualification type
-                                              // for GPIO122
-#define GPIO_GPDQSEL2_GPIO123_S   22
-#define GPIO_GPDQSEL2_GPIO123_M   0xC00000    // Select input qualification type
-                                              // for GPIO123
-#define GPIO_GPDQSEL2_GPIO124_S   24
-#define GPIO_GPDQSEL2_GPIO124_M   0x3000000   // Select input qualification type
-                                              // for GPIO124
-#define GPIO_GPDQSEL2_GPIO125_S   26
-#define GPIO_GPDQSEL2_GPIO125_M   0xC000000   // Select input qualification type
-                                              // for GPIO125
-#define GPIO_GPDQSEL2_GPIO126_S   28
-#define GPIO_GPDQSEL2_GPIO126_M   0x30000000  // Select input qualification type
-                                              // for GPIO126
-#define GPIO_GPDQSEL2_GPIO127_S   30
-#define GPIO_GPDQSEL2_GPIO127_M   0xC0000000  // Select input qualification type
-                                              // for GPIO127
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPDMUX1_GPIO96_S     0
-#define GPIO_GPDMUX1_GPIO96_M     0x3         // Defines pin-muxing selection
-                                              // for GPIO96
-#define GPIO_GPDMUX1_GPIO97_S     2
-#define GPIO_GPDMUX1_GPIO97_M     0xC         // Defines pin-muxing selection
-                                              // for GPIO97
-#define GPIO_GPDMUX1_GPIO98_S     4
-#define GPIO_GPDMUX1_GPIO98_M     0x30        // Defines pin-muxing selection
-                                              // for GPIO98
-#define GPIO_GPDMUX1_GPIO99_S     6
-#define GPIO_GPDMUX1_GPIO99_M     0xC0        // Defines pin-muxing selection
-                                              // for GPIO99
-#define GPIO_GPDMUX1_GPIO100_S    8
-#define GPIO_GPDMUX1_GPIO100_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO100
-#define GPIO_GPDMUX1_GPIO101_S    10
-#define GPIO_GPDMUX1_GPIO101_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO101
-#define GPIO_GPDMUX1_GPIO102_S    12
-#define GPIO_GPDMUX1_GPIO102_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO102
-#define GPIO_GPDMUX1_GPIO103_S    14
-#define GPIO_GPDMUX1_GPIO103_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO103
-#define GPIO_GPDMUX1_GPIO104_S    16
-#define GPIO_GPDMUX1_GPIO104_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO104
-#define GPIO_GPDMUX1_GPIO105_S    18
-#define GPIO_GPDMUX1_GPIO105_M    0xC0000     // Defines pin-muxing selection
-                                              // for GPIO105
-#define GPIO_GPDMUX1_GPIO106_S    20
-#define GPIO_GPDMUX1_GPIO106_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO106
-#define GPIO_GPDMUX1_GPIO107_S    22
-#define GPIO_GPDMUX1_GPIO107_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO107
-#define GPIO_GPDMUX1_GPIO108_S    24
-#define GPIO_GPDMUX1_GPIO108_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO108
-#define GPIO_GPDMUX1_GPIO109_S    26
-#define GPIO_GPDMUX1_GPIO109_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO109
-#define GPIO_GPDMUX1_GPIO110_S    28
-#define GPIO_GPDMUX1_GPIO110_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO110
-#define GPIO_GPDMUX1_GPIO111_S    30
-#define GPIO_GPDMUX1_GPIO111_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO111
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPDMUX2_GPIO112_S    0
-#define GPIO_GPDMUX2_GPIO112_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO112
-#define GPIO_GPDMUX2_GPIO113_S    2
-#define GPIO_GPDMUX2_GPIO113_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO113
-#define GPIO_GPDMUX2_GPIO114_S    4
-#define GPIO_GPDMUX2_GPIO114_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO114
-#define GPIO_GPDMUX2_GPIO115_S    6
-#define GPIO_GPDMUX2_GPIO115_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO115
-#define GPIO_GPDMUX2_GPIO116_S    8
-#define GPIO_GPDMUX2_GPIO116_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO116
-#define GPIO_GPDMUX2_GPIO117_S    10
-#define GPIO_GPDMUX2_GPIO117_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO117
-#define GPIO_GPDMUX2_GPIO118_S    12
-#define GPIO_GPDMUX2_GPIO118_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO118
-#define GPIO_GPDMUX2_GPIO119_S    14
-#define GPIO_GPDMUX2_GPIO119_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO119
-#define GPIO_GPDMUX2_GPIO120_S    16
-#define GPIO_GPDMUX2_GPIO120_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO120
-#define GPIO_GPDMUX2_GPIO121_S    18
-#define GPIO_GPDMUX2_GPIO121_M    0xC0000     // Defines pin-muxing selection
-                                              // for GPIO121
-#define GPIO_GPDMUX2_GPIO122_S    20
-#define GPIO_GPDMUX2_GPIO122_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO122
-#define GPIO_GPDMUX2_GPIO123_S    22
-#define GPIO_GPDMUX2_GPIO123_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO123
-#define GPIO_GPDMUX2_GPIO124_S    24
-#define GPIO_GPDMUX2_GPIO124_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO124
-#define GPIO_GPDMUX2_GPIO125_S    26
-#define GPIO_GPDMUX2_GPIO125_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO125
-#define GPIO_GPDMUX2_GPIO126_S    28
-#define GPIO_GPDMUX2_GPIO126_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO126
-#define GPIO_GPDMUX2_GPIO127_S    30
-#define GPIO_GPDMUX2_GPIO127_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO127
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDDIR register
-//
-//*****************************************************************************
-#define GPIO_GPDDIR_GPIO96        0x1         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO97        0x2         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO98        0x4         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO99        0x8         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO100       0x10        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO101       0x20        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO102       0x40        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO103       0x80        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO104       0x100       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO105       0x200       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO106       0x400       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO107       0x800       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO108       0x1000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO109       0x2000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO110       0x4000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO111       0x8000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO112       0x10000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO113       0x20000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO114       0x40000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO115       0x80000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO116       0x100000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO117       0x200000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO118       0x400000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO119       0x800000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO120       0x1000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO121       0x2000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO122       0x4000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO123       0x8000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO124       0x10000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO125       0x20000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO126       0x40000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPDDIR_GPIO127       0x80000000  // Defines direction for this pin
-                                              // in GPIO mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDPUD register
-//
-//*****************************************************************************
-#define GPIO_GPDPUD_GPIO96        0x1         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO97        0x2         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO98        0x4         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO99        0x8         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO100       0x10        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO101       0x20        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO102       0x40        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO103       0x80        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO104       0x100       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO105       0x200       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO106       0x400       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO107       0x800       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO108       0x1000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO109       0x2000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO110       0x4000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO111       0x8000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO112       0x10000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO113       0x20000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO114       0x40000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO115       0x80000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO116       0x100000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO117       0x200000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO118       0x400000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO119       0x800000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO120       0x1000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO121       0x2000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO122       0x4000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO123       0x8000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO124       0x10000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO125       0x20000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO126       0x40000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPDPUD_GPIO127       0x80000000  // Pull-Up Disable control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDINV register
-//
-//*****************************************************************************
-#define GPIO_GPDINV_GPIO96        0x1         // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO97        0x2         // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO98        0x4         // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO99        0x8         // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO100       0x10        // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO101       0x20        // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO102       0x40        // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO103       0x80        // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO104       0x100       // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO105       0x200       // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO106       0x400       // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO107       0x800       // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO108       0x1000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO109       0x2000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO110       0x4000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO111       0x8000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO112       0x10000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO113       0x20000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO114       0x40000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO115       0x80000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO116       0x100000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO117       0x200000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO118       0x400000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO119       0x800000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO120       0x1000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO121       0x2000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO122       0x4000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO123       0x8000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO124       0x10000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO125       0x20000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO126       0x40000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPDINV_GPIO127       0x80000000  // Input inversion control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDODR register
-//
-//*****************************************************************************
-#define GPIO_GPDODR_GPIO96        0x1         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO97        0x2         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO98        0x4         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO99        0x8         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO100       0x10        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO101       0x20        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO102       0x40        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO103       0x80        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO104       0x100       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO105       0x200       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO106       0x400       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO107       0x800       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO108       0x1000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO109       0x2000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO110       0x4000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO111       0x8000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO112       0x10000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO113       0x20000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO114       0x40000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO115       0x80000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO116       0x100000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO117       0x200000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO118       0x400000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO119       0x800000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO120       0x1000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO121       0x2000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO122       0x4000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO123       0x8000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO124       0x10000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO125       0x20000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO126       0x40000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPDODR_GPIO127       0x80000000  // Outpout Open-Drain control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDGMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPDGMUX1_GPIO96_S    0
-#define GPIO_GPDGMUX1_GPIO96_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO96
-#define GPIO_GPDGMUX1_GPIO97_S    2
-#define GPIO_GPDGMUX1_GPIO97_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO97
-#define GPIO_GPDGMUX1_GPIO98_S    4
-#define GPIO_GPDGMUX1_GPIO98_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO98
-#define GPIO_GPDGMUX1_GPIO99_S    6
-#define GPIO_GPDGMUX1_GPIO99_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO99
-#define GPIO_GPDGMUX1_GPIO100_S   8
-#define GPIO_GPDGMUX1_GPIO100_M   0x300       // Defines pin-muxing selection
-                                              // for GPIO100
-#define GPIO_GPDGMUX1_GPIO101_S   10
-#define GPIO_GPDGMUX1_GPIO101_M   0xC00       // Defines pin-muxing selection
-                                              // for GPIO101
-#define GPIO_GPDGMUX1_GPIO102_S   12
-#define GPIO_GPDGMUX1_GPIO102_M   0x3000      // Defines pin-muxing selection
-                                              // for GPIO102
-#define GPIO_GPDGMUX1_GPIO103_S   14
-#define GPIO_GPDGMUX1_GPIO103_M   0xC000      // Defines pin-muxing selection
-                                              // for GPIO103
-#define GPIO_GPDGMUX1_GPIO104_S   16
-#define GPIO_GPDGMUX1_GPIO104_M   0x30000     // Defines pin-muxing selection
-                                              // for GPIO104
-#define GPIO_GPDGMUX1_GPIO105_S   18
-#define GPIO_GPDGMUX1_GPIO105_M   0xC0000     // Defines pin-muxing selection
-                                              // for GPIO105
-#define GPIO_GPDGMUX1_GPIO106_S   20
-#define GPIO_GPDGMUX1_GPIO106_M   0x300000    // Defines pin-muxing selection
-                                              // for GPIO106
-#define GPIO_GPDGMUX1_GPIO107_S   22
-#define GPIO_GPDGMUX1_GPIO107_M   0xC00000    // Defines pin-muxing selection
-                                              // for GPIO107
-#define GPIO_GPDGMUX1_GPIO108_S   24
-#define GPIO_GPDGMUX1_GPIO108_M   0x3000000   // Defines pin-muxing selection
-                                              // for GPIO108
-#define GPIO_GPDGMUX1_GPIO109_S   26
-#define GPIO_GPDGMUX1_GPIO109_M   0xC000000   // Defines pin-muxing selection
-                                              // for GPIO109
-#define GPIO_GPDGMUX1_GPIO110_S   28
-#define GPIO_GPDGMUX1_GPIO110_M   0x30000000  // Defines pin-muxing selection
-                                              // for GPIO110
-#define GPIO_GPDGMUX1_GPIO111_S   30
-#define GPIO_GPDGMUX1_GPIO111_M   0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO111
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDGMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPDGMUX2_GPIO112_S   0
-#define GPIO_GPDGMUX2_GPIO112_M   0x3         // Defines pin-muxing selection
-                                              // for GPIO112
-#define GPIO_GPDGMUX2_GPIO113_S   2
-#define GPIO_GPDGMUX2_GPIO113_M   0xC         // Defines pin-muxing selection
-                                              // for GPIO113
-#define GPIO_GPDGMUX2_GPIO114_S   4
-#define GPIO_GPDGMUX2_GPIO114_M   0x30        // Defines pin-muxing selection
-                                              // for GPIO114
-#define GPIO_GPDGMUX2_GPIO115_S   6
-#define GPIO_GPDGMUX2_GPIO115_M   0xC0        // Defines pin-muxing selection
-                                              // for GPIO115
-#define GPIO_GPDGMUX2_GPIO116_S   8
-#define GPIO_GPDGMUX2_GPIO116_M   0x300       // Defines pin-muxing selection
-                                              // for GPIO116
-#define GPIO_GPDGMUX2_GPIO117_S   10
-#define GPIO_GPDGMUX2_GPIO117_M   0xC00       // Defines pin-muxing selection
-                                              // for GPIO117
-#define GPIO_GPDGMUX2_GPIO118_S   12
-#define GPIO_GPDGMUX2_GPIO118_M   0x3000      // Defines pin-muxing selection
-                                              // for GPIO118
-#define GPIO_GPDGMUX2_GPIO119_S   14
-#define GPIO_GPDGMUX2_GPIO119_M   0xC000      // Defines pin-muxing selection
-                                              // for GPIO119
-#define GPIO_GPDGMUX2_GPIO120_S   16
-#define GPIO_GPDGMUX2_GPIO120_M   0x30000     // Defines pin-muxing selection
-                                              // for GPIO120
-#define GPIO_GPDGMUX2_GPIO121_S   18
-#define GPIO_GPDGMUX2_GPIO121_M   0xC0000     // Defines pin-muxing selection
-                                              // for GPIO121
-#define GPIO_GPDGMUX2_GPIO122_S   20
-#define GPIO_GPDGMUX2_GPIO122_M   0x300000    // Defines pin-muxing selection
-                                              // for GPIO122
-#define GPIO_GPDGMUX2_GPIO123_S   22
-#define GPIO_GPDGMUX2_GPIO123_M   0xC00000    // Defines pin-muxing selection
-                                              // for GPIO123
-#define GPIO_GPDGMUX2_GPIO124_S   24
-#define GPIO_GPDGMUX2_GPIO124_M   0x3000000   // Defines pin-muxing selection
-                                              // for GPIO124
-#define GPIO_GPDGMUX2_GPIO125_S   26
-#define GPIO_GPDGMUX2_GPIO125_M   0xC000000   // Defines pin-muxing selection
-                                              // for GPIO125
-#define GPIO_GPDGMUX2_GPIO126_S   28
-#define GPIO_GPDGMUX2_GPIO126_M   0x30000000  // Defines pin-muxing selection
-                                              // for GPIO126
-#define GPIO_GPDGMUX2_GPIO127_S   30
-#define GPIO_GPDGMUX2_GPIO127_M   0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO127
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDCSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPDCSEL1_GPIO96_S    0
-#define GPIO_GPDCSEL1_GPIO96_M    0xF         // GPIO96 Master CPU Select
-#define GPIO_GPDCSEL1_GPIO97_S    4
-#define GPIO_GPDCSEL1_GPIO97_M    0xF0        // GPIO97 Master CPU Select
-#define GPIO_GPDCSEL1_GPIO98_S    8
-#define GPIO_GPDCSEL1_GPIO98_M    0xF00       // GPIO98 Master CPU Select
-#define GPIO_GPDCSEL1_GPIO99_S    12
-#define GPIO_GPDCSEL1_GPIO99_M    0xF000      // GPIO99 Master CPU Select
-#define GPIO_GPDCSEL1_GPIO100_S   16
-#define GPIO_GPDCSEL1_GPIO100_M   0xF0000     // GPIO100 Master CPU Select
-#define GPIO_GPDCSEL1_GPIO101_S   20
-#define GPIO_GPDCSEL1_GPIO101_M   0xF00000    // GPIO101 Master CPU Select
-#define GPIO_GPDCSEL1_GPIO102_S   24
-#define GPIO_GPDCSEL1_GPIO102_M   0xF000000   // GPIO102 Master CPU Select
-#define GPIO_GPDCSEL1_GPIO103_S   28
-#define GPIO_GPDCSEL1_GPIO103_M   0xF0000000  // GPIO103 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDCSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPDCSEL2_GPIO104_S   0
-#define GPIO_GPDCSEL2_GPIO104_M   0xF         // GPIO104 Master CPU Select
-#define GPIO_GPDCSEL2_GPIO105_S   4
-#define GPIO_GPDCSEL2_GPIO105_M   0xF0        // GPIO105 Master CPU Select
-#define GPIO_GPDCSEL2_GPIO106_S   8
-#define GPIO_GPDCSEL2_GPIO106_M   0xF00       // GPIO106 Master CPU Select
-#define GPIO_GPDCSEL2_GPIO107_S   12
-#define GPIO_GPDCSEL2_GPIO107_M   0xF000      // GPIO107 Master CPU Select
-#define GPIO_GPDCSEL2_GPIO108_S   16
-#define GPIO_GPDCSEL2_GPIO108_M   0xF0000     // GPIO108 Master CPU Select
-#define GPIO_GPDCSEL2_GPIO109_S   20
-#define GPIO_GPDCSEL2_GPIO109_M   0xF00000    // GPIO109 Master CPU Select
-#define GPIO_GPDCSEL2_GPIO110_S   24
-#define GPIO_GPDCSEL2_GPIO110_M   0xF000000   // GPIO110 Master CPU Select
-#define GPIO_GPDCSEL2_GPIO111_S   28
-#define GPIO_GPDCSEL2_GPIO111_M   0xF0000000  // GPIO111 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDCSEL3 register
-//
-//*****************************************************************************
-#define GPIO_GPDCSEL3_GPIO112_S   0
-#define GPIO_GPDCSEL3_GPIO112_M   0xF         // GPIO112 Master CPU Select
-#define GPIO_GPDCSEL3_GPIO113_S   4
-#define GPIO_GPDCSEL3_GPIO113_M   0xF0        // GPIO113 Master CPU Select
-#define GPIO_GPDCSEL3_GPIO114_S   8
-#define GPIO_GPDCSEL3_GPIO114_M   0xF00       // GPIO114 Master CPU Select
-#define GPIO_GPDCSEL3_GPIO115_S   12
-#define GPIO_GPDCSEL3_GPIO115_M   0xF000      // GPIO115 Master CPU Select
-#define GPIO_GPDCSEL3_GPIO116_S   16
-#define GPIO_GPDCSEL3_GPIO116_M   0xF0000     // GPIO116 Master CPU Select
-#define GPIO_GPDCSEL3_GPIO117_S   20
-#define GPIO_GPDCSEL3_GPIO117_M   0xF00000    // GPIO117 Master CPU Select
-#define GPIO_GPDCSEL3_GPIO118_S   24
-#define GPIO_GPDCSEL3_GPIO118_M   0xF000000   // GPIO118 Master CPU Select
-#define GPIO_GPDCSEL3_GPIO119_S   28
-#define GPIO_GPDCSEL3_GPIO119_M   0xF0000000  // GPIO119 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDCSEL4 register
-//
-//*****************************************************************************
-#define GPIO_GPDCSEL4_GPIO120_S   0
-#define GPIO_GPDCSEL4_GPIO120_M   0xF         // GPIO120 Master CPU Select
-#define GPIO_GPDCSEL4_GPIO121_S   4
-#define GPIO_GPDCSEL4_GPIO121_M   0xF0        // GPIO121 Master CPU Select
-#define GPIO_GPDCSEL4_GPIO122_S   8
-#define GPIO_GPDCSEL4_GPIO122_M   0xF00       // GPIO122 Master CPU Select
-#define GPIO_GPDCSEL4_GPIO123_S   12
-#define GPIO_GPDCSEL4_GPIO123_M   0xF000      // GPIO123 Master CPU Select
-#define GPIO_GPDCSEL4_GPIO124_S   16
-#define GPIO_GPDCSEL4_GPIO124_M   0xF0000     // GPIO124 Master CPU Select
-#define GPIO_GPDCSEL4_GPIO125_S   20
-#define GPIO_GPDCSEL4_GPIO125_M   0xF00000    // GPIO125 Master CPU Select
-#define GPIO_GPDCSEL4_GPIO126_S   24
-#define GPIO_GPDCSEL4_GPIO126_M   0xF000000   // GPIO126 Master CPU Select
-#define GPIO_GPDCSEL4_GPIO127_S   28
-#define GPIO_GPDCSEL4_GPIO127_M   0xF0000000  // GPIO127 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDLOCK register
-//
-//*****************************************************************************
-#define GPIO_GPDLOCK_GPIO96       0x1         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO97       0x2         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO98       0x4         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO99       0x8         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO100      0x10        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO101      0x20        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO102      0x40        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO103      0x80        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO104      0x100       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO105      0x200       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO106      0x400       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO107      0x800       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO108      0x1000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO109      0x2000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO110      0x4000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO111      0x8000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO112      0x10000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO113      0x20000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO114      0x40000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO115      0x80000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO116      0x100000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO117      0x200000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO118      0x400000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO119      0x800000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO120      0x1000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO121      0x2000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO122      0x4000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO123      0x8000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO124      0x10000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO125      0x20000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO126      0x40000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPDLOCK_GPIO127      0x80000000  // Configuration Lock bit for this
-                                              // pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDCR register
-//
-//*****************************************************************************
-#define GPIO_GPDCR_GPIO96         0x1         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO97         0x2         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO98         0x4         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO99         0x8         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO100        0x10        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO101        0x20        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO102        0x40        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO103        0x80        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO104        0x100       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO105        0x200       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO106        0x400       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO107        0x800       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO108        0x1000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO109        0x2000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO110        0x4000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO111        0x8000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO112        0x10000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO113        0x20000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO114        0x40000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO115        0x80000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO116        0x100000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO117        0x200000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO118        0x400000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO119        0x800000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO120        0x1000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO121        0x2000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO122        0x4000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO123        0x8000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO124        0x10000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO125        0x20000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO126        0x40000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPDCR_GPIO127        0x80000000  // Configuration lock commit bit
-                                              // for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPECTRL register
-//
-//*****************************************************************************
-#define GPIO_GPECTRL_QUALPRD0_S   0
-#define GPIO_GPECTRL_QUALPRD0_M   0xFF        // Qualification sampling period
-                                              // for GPIO128 to GPIO135
-#define GPIO_GPECTRL_QUALPRD1_S   8
-#define GPIO_GPECTRL_QUALPRD1_M   0xFF00      // Qualification sampling period
-                                              // for GPIO136 to GPIO143
-#define GPIO_GPECTRL_QUALPRD2_S   16
-#define GPIO_GPECTRL_QUALPRD2_M   0xFF0000    // Qualification sampling period
-                                              // for GPIO144 to GPIO151
-#define GPIO_GPECTRL_QUALPRD3_S   24
-#define GPIO_GPECTRL_QUALPRD3_M   0xFF000000  // Qualification sampling period
-                                              // for GPIO152 to GPIO159
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEQSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPEQSEL1_GPIO128_S   0
-#define GPIO_GPEQSEL1_GPIO128_M   0x3         // Select input qualification type
-                                              // for GPIO128
-#define GPIO_GPEQSEL1_GPIO129_S   2
-#define GPIO_GPEQSEL1_GPIO129_M   0xC         // Select input qualification type
-                                              // for GPIO129
-#define GPIO_GPEQSEL1_GPIO130_S   4
-#define GPIO_GPEQSEL1_GPIO130_M   0x30        // Select input qualification type
-                                              // for GPIO130
-#define GPIO_GPEQSEL1_GPIO131_S   6
-#define GPIO_GPEQSEL1_GPIO131_M   0xC0        // Select input qualification type
-                                              // for GPIO131
-#define GPIO_GPEQSEL1_GPIO132_S   8
-#define GPIO_GPEQSEL1_GPIO132_M   0x300       // Select input qualification type
-                                              // for GPIO132
-#define GPIO_GPEQSEL1_GPIO133_S   10
-#define GPIO_GPEQSEL1_GPIO133_M   0xC00       // Select input qualification type
-                                              // for GPIO133
-#define GPIO_GPEQSEL1_GPIO134_S   12
-#define GPIO_GPEQSEL1_GPIO134_M   0x3000      // Select input qualification type
-                                              // for GPIO134
-#define GPIO_GPEQSEL1_GPIO135_S   14
-#define GPIO_GPEQSEL1_GPIO135_M   0xC000      // Select input qualification type
-                                              // for GPIO135
-#define GPIO_GPEQSEL1_GPIO136_S   16
-#define GPIO_GPEQSEL1_GPIO136_M   0x30000     // Select input qualification type
-                                              // for GPIO136
-#define GPIO_GPEQSEL1_GPIO137_S   18
-#define GPIO_GPEQSEL1_GPIO137_M   0xC0000     // Select input qualification type
-                                              // for GPIO137
-#define GPIO_GPEQSEL1_GPIO138_S   20
-#define GPIO_GPEQSEL1_GPIO138_M   0x300000    // Select input qualification type
-                                              // for GPIO138
-#define GPIO_GPEQSEL1_GPIO139_S   22
-#define GPIO_GPEQSEL1_GPIO139_M   0xC00000    // Select input qualification type
-                                              // for GPIO139
-#define GPIO_GPEQSEL1_GPIO140_S   24
-#define GPIO_GPEQSEL1_GPIO140_M   0x3000000   // Select input qualification type
-                                              // for GPIO140
-#define GPIO_GPEQSEL1_GPIO141_S   26
-#define GPIO_GPEQSEL1_GPIO141_M   0xC000000   // Select input qualification type
-                                              // for GPIO141
-#define GPIO_GPEQSEL1_GPIO142_S   28
-#define GPIO_GPEQSEL1_GPIO142_M   0x30000000  // Select input qualification type
-                                              // for GPIO142
-#define GPIO_GPEQSEL1_GPIO143_S   30
-#define GPIO_GPEQSEL1_GPIO143_M   0xC0000000  // Select input qualification type
-                                              // for GPIO143
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEQSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPEQSEL2_GPIO144_S   0
-#define GPIO_GPEQSEL2_GPIO144_M   0x3         // Select input qualification type
-                                              // for GPIO144
-#define GPIO_GPEQSEL2_GPIO145_S   2
-#define GPIO_GPEQSEL2_GPIO145_M   0xC         // Select input qualification type
-                                              // for GPIO145
-#define GPIO_GPEQSEL2_GPIO146_S   4
-#define GPIO_GPEQSEL2_GPIO146_M   0x30        // Select input qualification type
-                                              // for GPIO146
-#define GPIO_GPEQSEL2_GPIO147_S   6
-#define GPIO_GPEQSEL2_GPIO147_M   0xC0        // Select input qualification type
-                                              // for GPIO147
-#define GPIO_GPEQSEL2_GPIO148_S   8
-#define GPIO_GPEQSEL2_GPIO148_M   0x300       // Select input qualification type
-                                              // for GPIO148
-#define GPIO_GPEQSEL2_GPIO149_S   10
-#define GPIO_GPEQSEL2_GPIO149_M   0xC00       // Select input qualification type
-                                              // for GPIO149
-#define GPIO_GPEQSEL2_GPIO150_S   12
-#define GPIO_GPEQSEL2_GPIO150_M   0x3000      // Select input qualification type
-                                              // for GPIO150
-#define GPIO_GPEQSEL2_GPIO151_S   14
-#define GPIO_GPEQSEL2_GPIO151_M   0xC000      // Select input qualification type
-                                              // for GPIO151
-#define GPIO_GPEQSEL2_GPIO152_S   16
-#define GPIO_GPEQSEL2_GPIO152_M   0x30000     // Select input qualification type
-                                              // for GPIO152
-#define GPIO_GPEQSEL2_GPIO153_S   18
-#define GPIO_GPEQSEL2_GPIO153_M   0xC0000     // Select input qualification type
-                                              // for GPIO153
-#define GPIO_GPEQSEL2_GPIO154_S   20
-#define GPIO_GPEQSEL2_GPIO154_M   0x300000    // Select input qualification type
-                                              // for GPIO154
-#define GPIO_GPEQSEL2_GPIO155_S   22
-#define GPIO_GPEQSEL2_GPIO155_M   0xC00000    // Select input qualification type
-                                              // for GPIO155
-#define GPIO_GPEQSEL2_GPIO156_S   24
-#define GPIO_GPEQSEL2_GPIO156_M   0x3000000   // Select input qualification type
-                                              // for GPIO156
-#define GPIO_GPEQSEL2_GPIO157_S   26
-#define GPIO_GPEQSEL2_GPIO157_M   0xC000000   // Select input qualification type
-                                              // for GPIO157
-#define GPIO_GPEQSEL2_GPIO158_S   28
-#define GPIO_GPEQSEL2_GPIO158_M   0x30000000  // Select input qualification type
-                                              // for GPIO158
-#define GPIO_GPEQSEL2_GPIO159_S   30
-#define GPIO_GPEQSEL2_GPIO159_M   0xC0000000  // Select input qualification type
-                                              // for GPIO159
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPEMUX1_GPIO128_S    0
-#define GPIO_GPEMUX1_GPIO128_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO128
-#define GPIO_GPEMUX1_GPIO129_S    2
-#define GPIO_GPEMUX1_GPIO129_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO129
-#define GPIO_GPEMUX1_GPIO130_S    4
-#define GPIO_GPEMUX1_GPIO130_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO130
-#define GPIO_GPEMUX1_GPIO131_S    6
-#define GPIO_GPEMUX1_GPIO131_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO131
-#define GPIO_GPEMUX1_GPIO132_S    8
-#define GPIO_GPEMUX1_GPIO132_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO132
-#define GPIO_GPEMUX1_GPIO133_S    10
-#define GPIO_GPEMUX1_GPIO133_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO133
-#define GPIO_GPEMUX1_GPIO134_S    12
-#define GPIO_GPEMUX1_GPIO134_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO134
-#define GPIO_GPEMUX1_GPIO135_S    14
-#define GPIO_GPEMUX1_GPIO135_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO135
-#define GPIO_GPEMUX1_GPIO136_S    16
-#define GPIO_GPEMUX1_GPIO136_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO136
-#define GPIO_GPEMUX1_GPIO137_S    18
-#define GPIO_GPEMUX1_GPIO137_M    0xC0000     // Defines pin-muxing selection
-                                              // for GPIO137
-#define GPIO_GPEMUX1_GPIO138_S    20
-#define GPIO_GPEMUX1_GPIO138_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO138
-#define GPIO_GPEMUX1_GPIO139_S    22
-#define GPIO_GPEMUX1_GPIO139_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO139
-#define GPIO_GPEMUX1_GPIO140_S    24
-#define GPIO_GPEMUX1_GPIO140_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO140
-#define GPIO_GPEMUX1_GPIO141_S    26
-#define GPIO_GPEMUX1_GPIO141_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO141
-#define GPIO_GPEMUX1_GPIO142_S    28
-#define GPIO_GPEMUX1_GPIO142_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO142
-#define GPIO_GPEMUX1_GPIO143_S    30
-#define GPIO_GPEMUX1_GPIO143_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO143
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPEMUX2_GPIO144_S    0
-#define GPIO_GPEMUX2_GPIO144_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO144
-#define GPIO_GPEMUX2_GPIO145_S    2
-#define GPIO_GPEMUX2_GPIO145_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO145
-#define GPIO_GPEMUX2_GPIO146_S    4
-#define GPIO_GPEMUX2_GPIO146_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO146
-#define GPIO_GPEMUX2_GPIO147_S    6
-#define GPIO_GPEMUX2_GPIO147_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO147
-#define GPIO_GPEMUX2_GPIO148_S    8
-#define GPIO_GPEMUX2_GPIO148_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO148
-#define GPIO_GPEMUX2_GPIO149_S    10
-#define GPIO_GPEMUX2_GPIO149_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO149
-#define GPIO_GPEMUX2_GPIO150_S    12
-#define GPIO_GPEMUX2_GPIO150_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO150
-#define GPIO_GPEMUX2_GPIO151_S    14
-#define GPIO_GPEMUX2_GPIO151_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO151
-#define GPIO_GPEMUX2_GPIO152_S    16
-#define GPIO_GPEMUX2_GPIO152_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO152
-#define GPIO_GPEMUX2_GPIO153_S    18
-#define GPIO_GPEMUX2_GPIO153_M    0xC0000     // Defines pin-muxing selection
-                                              // for GPIO153
-#define GPIO_GPEMUX2_GPIO154_S    20
-#define GPIO_GPEMUX2_GPIO154_M    0x300000    // Defines pin-muxing selection
-                                              // for GPIO154
-#define GPIO_GPEMUX2_GPIO155_S    22
-#define GPIO_GPEMUX2_GPIO155_M    0xC00000    // Defines pin-muxing selection
-                                              // for GPIO155
-#define GPIO_GPEMUX2_GPIO156_S    24
-#define GPIO_GPEMUX2_GPIO156_M    0x3000000   // Defines pin-muxing selection
-                                              // for GPIO156
-#define GPIO_GPEMUX2_GPIO157_S    26
-#define GPIO_GPEMUX2_GPIO157_M    0xC000000   // Defines pin-muxing selection
-                                              // for GPIO157
-#define GPIO_GPEMUX2_GPIO158_S    28
-#define GPIO_GPEMUX2_GPIO158_M    0x30000000  // Defines pin-muxing selection
-                                              // for GPIO158
-#define GPIO_GPEMUX2_GPIO159_S    30
-#define GPIO_GPEMUX2_GPIO159_M    0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO159
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEDIR register
-//
-//*****************************************************************************
-#define GPIO_GPEDIR_GPIO128       0x1         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO129       0x2         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO130       0x4         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO131       0x8         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO132       0x10        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO133       0x20        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO134       0x40        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO135       0x80        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO136       0x100       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO137       0x200       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO138       0x400       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO139       0x800       // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO140       0x1000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO141       0x2000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO142       0x4000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO143       0x8000      // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO144       0x10000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO145       0x20000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO146       0x40000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO147       0x80000     // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO148       0x100000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO149       0x200000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO150       0x400000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO151       0x800000    // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO152       0x1000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO153       0x2000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO154       0x4000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO155       0x8000000   // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO156       0x10000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO157       0x20000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO158       0x40000000  // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPEDIR_GPIO159       0x80000000  // Defines direction for this pin
-                                              // in GPIO mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEPUD register
-//
-//*****************************************************************************
-#define GPIO_GPEPUD_GPIO128       0x1         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO129       0x2         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO130       0x4         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO131       0x8         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO132       0x10        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO133       0x20        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO134       0x40        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO135       0x80        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO136       0x100       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO137       0x200       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO138       0x400       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO139       0x800       // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO140       0x1000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO141       0x2000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO142       0x4000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO143       0x8000      // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO144       0x10000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO145       0x20000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO146       0x40000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO147       0x80000     // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO148       0x100000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO149       0x200000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO150       0x400000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO151       0x800000    // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO152       0x1000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO153       0x2000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO154       0x4000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO155       0x8000000   // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO156       0x10000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO157       0x20000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO158       0x40000000  // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPEPUD_GPIO159       0x80000000  // Pull-Up Disable control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEINV register
-//
-//*****************************************************************************
-#define GPIO_GPEINV_GPIO128       0x1         // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO129       0x2         // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO130       0x4         // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO131       0x8         // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO132       0x10        // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO133       0x20        // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO134       0x40        // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO135       0x80        // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO136       0x100       // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO137       0x200       // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO138       0x400       // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO139       0x800       // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO140       0x1000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO141       0x2000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO142       0x4000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO143       0x8000      // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO144       0x10000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO145       0x20000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO146       0x40000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO147       0x80000     // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO148       0x100000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO149       0x200000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO150       0x400000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO151       0x800000    // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO152       0x1000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO153       0x2000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO154       0x4000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO155       0x8000000   // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO156       0x10000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO157       0x20000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO158       0x40000000  // Input inversion control for
-                                              // this pin
-#define GPIO_GPEINV_GPIO159       0x80000000  // Input inversion control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEODR register
-//
-//*****************************************************************************
-#define GPIO_GPEODR_GPIO128       0x1         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO129       0x2         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO130       0x4         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO131       0x8         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO132       0x10        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO133       0x20        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO134       0x40        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO135       0x80        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO136       0x100       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO137       0x200       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO138       0x400       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO139       0x800       // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO140       0x1000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO141       0x2000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO142       0x4000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO143       0x8000      // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO144       0x10000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO145       0x20000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO146       0x40000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO147       0x80000     // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO148       0x100000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO149       0x200000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO150       0x400000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO151       0x800000    // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO152       0x1000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO153       0x2000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO154       0x4000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO155       0x8000000   // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO156       0x10000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO157       0x20000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO158       0x40000000  // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPEODR_GPIO159       0x80000000  // Outpout Open-Drain control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEGMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPEGMUX1_GPIO128_S   0
-#define GPIO_GPEGMUX1_GPIO128_M   0x3         // Defines pin-muxing selection
-                                              // for GPIO128
-#define GPIO_GPEGMUX1_GPIO129_S   2
-#define GPIO_GPEGMUX1_GPIO129_M   0xC         // Defines pin-muxing selection
-                                              // for GPIO129
-#define GPIO_GPEGMUX1_GPIO130_S   4
-#define GPIO_GPEGMUX1_GPIO130_M   0x30        // Defines pin-muxing selection
-                                              // for GPIO130
-#define GPIO_GPEGMUX1_GPIO131_S   6
-#define GPIO_GPEGMUX1_GPIO131_M   0xC0        // Defines pin-muxing selection
-                                              // for GPIO131
-#define GPIO_GPEGMUX1_GPIO132_S   8
-#define GPIO_GPEGMUX1_GPIO132_M   0x300       // Defines pin-muxing selection
-                                              // for GPIO132
-#define GPIO_GPEGMUX1_GPIO133_S   10
-#define GPIO_GPEGMUX1_GPIO133_M   0xC00       // Defines pin-muxing selection
-                                              // for GPIO133
-#define GPIO_GPEGMUX1_GPIO134_S   12
-#define GPIO_GPEGMUX1_GPIO134_M   0x3000      // Defines pin-muxing selection
-                                              // for GPIO134
-#define GPIO_GPEGMUX1_GPIO135_S   14
-#define GPIO_GPEGMUX1_GPIO135_M   0xC000      // Defines pin-muxing selection
-                                              // for GPIO135
-#define GPIO_GPEGMUX1_GPIO136_S   16
-#define GPIO_GPEGMUX1_GPIO136_M   0x30000     // Defines pin-muxing selection
-                                              // for GPIO136
-#define GPIO_GPEGMUX1_GPIO137_S   18
-#define GPIO_GPEGMUX1_GPIO137_M   0xC0000     // Defines pin-muxing selection
-                                              // for GPIO137
-#define GPIO_GPEGMUX1_GPIO138_S   20
-#define GPIO_GPEGMUX1_GPIO138_M   0x300000    // Defines pin-muxing selection
-                                              // for GPIO138
-#define GPIO_GPEGMUX1_GPIO139_S   22
-#define GPIO_GPEGMUX1_GPIO139_M   0xC00000    // Defines pin-muxing selection
-                                              // for GPIO139
-#define GPIO_GPEGMUX1_GPIO140_S   24
-#define GPIO_GPEGMUX1_GPIO140_M   0x3000000   // Defines pin-muxing selection
-                                              // for GPIO140
-#define GPIO_GPEGMUX1_GPIO141_S   26
-#define GPIO_GPEGMUX1_GPIO141_M   0xC000000   // Defines pin-muxing selection
-                                              // for GPIO141
-#define GPIO_GPEGMUX1_GPIO142_S   28
-#define GPIO_GPEGMUX1_GPIO142_M   0x30000000  // Defines pin-muxing selection
-                                              // for GPIO142
-#define GPIO_GPEGMUX1_GPIO143_S   30
-#define GPIO_GPEGMUX1_GPIO143_M   0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO143
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEGMUX2 register
-//
-//*****************************************************************************
-#define GPIO_GPEGMUX2_GPIO144_S   0
-#define GPIO_GPEGMUX2_GPIO144_M   0x3         // Defines pin-muxing selection
-                                              // for GPIO144
-#define GPIO_GPEGMUX2_GPIO145_S   2
-#define GPIO_GPEGMUX2_GPIO145_M   0xC         // Defines pin-muxing selection
-                                              // for GPIO145
-#define GPIO_GPEGMUX2_GPIO146_S   4
-#define GPIO_GPEGMUX2_GPIO146_M   0x30        // Defines pin-muxing selection
-                                              // for GPIO146
-#define GPIO_GPEGMUX2_GPIO147_S   6
-#define GPIO_GPEGMUX2_GPIO147_M   0xC0        // Defines pin-muxing selection
-                                              // for GPIO147
-#define GPIO_GPEGMUX2_GPIO148_S   8
-#define GPIO_GPEGMUX2_GPIO148_M   0x300       // Defines pin-muxing selection
-                                              // for GPIO148
-#define GPIO_GPEGMUX2_GPIO149_S   10
-#define GPIO_GPEGMUX2_GPIO149_M   0xC00       // Defines pin-muxing selection
-                                              // for GPIO149
-#define GPIO_GPEGMUX2_GPIO150_S   12
-#define GPIO_GPEGMUX2_GPIO150_M   0x3000      // Defines pin-muxing selection
-                                              // for GPIO150
-#define GPIO_GPEGMUX2_GPIO151_S   14
-#define GPIO_GPEGMUX2_GPIO151_M   0xC000      // Defines pin-muxing selection
-                                              // for GPIO151
-#define GPIO_GPEGMUX2_GPIO152_S   16
-#define GPIO_GPEGMUX2_GPIO152_M   0x30000     // Defines pin-muxing selection
-                                              // for GPIO152
-#define GPIO_GPEGMUX2_GPIO153_S   18
-#define GPIO_GPEGMUX2_GPIO153_M   0xC0000     // Defines pin-muxing selection
-                                              // for GPIO153
-#define GPIO_GPEGMUX2_GPIO154_S   20
-#define GPIO_GPEGMUX2_GPIO154_M   0x300000    // Defines pin-muxing selection
-                                              // for GPIO154
-#define GPIO_GPEGMUX2_GPIO155_S   22
-#define GPIO_GPEGMUX2_GPIO155_M   0xC00000    // Defines pin-muxing selection
-                                              // for GPIO155
-#define GPIO_GPEGMUX2_GPIO156_S   24
-#define GPIO_GPEGMUX2_GPIO156_M   0x3000000   // Defines pin-muxing selection
-                                              // for GPIO156
-#define GPIO_GPEGMUX2_GPIO157_S   26
-#define GPIO_GPEGMUX2_GPIO157_M   0xC000000   // Defines pin-muxing selection
-                                              // for GPIO157
-#define GPIO_GPEGMUX2_GPIO158_S   28
-#define GPIO_GPEGMUX2_GPIO158_M   0x30000000  // Defines pin-muxing selection
-                                              // for GPIO158
-#define GPIO_GPEGMUX2_GPIO159_S   30
-#define GPIO_GPEGMUX2_GPIO159_M   0xC0000000  // Defines pin-muxing selection
-                                              // for GPIO159
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPECSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPECSEL1_GPIO128_S   0
-#define GPIO_GPECSEL1_GPIO128_M   0xF         // GPIO128 Master CPU Select
-#define GPIO_GPECSEL1_GPIO129_S   4
-#define GPIO_GPECSEL1_GPIO129_M   0xF0        // GPIO129 Master CPU Select
-#define GPIO_GPECSEL1_GPIO130_S   8
-#define GPIO_GPECSEL1_GPIO130_M   0xF00       // GPIO130 Master CPU Select
-#define GPIO_GPECSEL1_GPIO131_S   12
-#define GPIO_GPECSEL1_GPIO131_M   0xF000      // GPIO131 Master CPU Select
-#define GPIO_GPECSEL1_GPIO132_S   16
-#define GPIO_GPECSEL1_GPIO132_M   0xF0000     // GPIO132 Master CPU Select
-#define GPIO_GPECSEL1_GPIO133_S   20
-#define GPIO_GPECSEL1_GPIO133_M   0xF00000    // GPIO133 Master CPU Select
-#define GPIO_GPECSEL1_GPIO134_S   24
-#define GPIO_GPECSEL1_GPIO134_M   0xF000000   // GPIO134 Master CPU Select
-#define GPIO_GPECSEL1_GPIO135_S   28
-#define GPIO_GPECSEL1_GPIO135_M   0xF0000000  // GPIO135 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPECSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPECSEL2_GPIO136_S   0
-#define GPIO_GPECSEL2_GPIO136_M   0xF         // GPIO136 Master CPU Select
-#define GPIO_GPECSEL2_GPIO137_S   4
-#define GPIO_GPECSEL2_GPIO137_M   0xF0        // GPIO137 Master CPU Select
-#define GPIO_GPECSEL2_GPIO138_S   8
-#define GPIO_GPECSEL2_GPIO138_M   0xF00       // GPIO138 Master CPU Select
-#define GPIO_GPECSEL2_GPIO139_S   12
-#define GPIO_GPECSEL2_GPIO139_M   0xF000      // GPIO139 Master CPU Select
-#define GPIO_GPECSEL2_GPIO140_S   16
-#define GPIO_GPECSEL2_GPIO140_M   0xF0000     // GPIO140 Master CPU Select
-#define GPIO_GPECSEL2_GPIO141_S   20
-#define GPIO_GPECSEL2_GPIO141_M   0xF00000    // GPIO141 Master CPU Select
-#define GPIO_GPECSEL2_GPIO142_S   24
-#define GPIO_GPECSEL2_GPIO142_M   0xF000000   // GPIO142 Master CPU Select
-#define GPIO_GPECSEL2_GPIO143_S   28
-#define GPIO_GPECSEL2_GPIO143_M   0xF0000000  // GPIO143 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPECSEL3 register
-//
-//*****************************************************************************
-#define GPIO_GPECSEL3_GPIO144_S   0
-#define GPIO_GPECSEL3_GPIO144_M   0xF         // GPIO144 Master CPU Select
-#define GPIO_GPECSEL3_GPIO145_S   4
-#define GPIO_GPECSEL3_GPIO145_M   0xF0        // GPIO145 Master CPU Select
-#define GPIO_GPECSEL3_GPIO146_S   8
-#define GPIO_GPECSEL3_GPIO146_M   0xF00       // GPIO146 Master CPU Select
-#define GPIO_GPECSEL3_GPIO147_S   12
-#define GPIO_GPECSEL3_GPIO147_M   0xF000      // GPIO147 Master CPU Select
-#define GPIO_GPECSEL3_GPIO148_S   16
-#define GPIO_GPECSEL3_GPIO148_M   0xF0000     // GPIO148 Master CPU Select
-#define GPIO_GPECSEL3_GPIO149_S   20
-#define GPIO_GPECSEL3_GPIO149_M   0xF00000    // GPIO149 Master CPU Select
-#define GPIO_GPECSEL3_GPIO150_S   24
-#define GPIO_GPECSEL3_GPIO150_M   0xF000000   // GPIO150 Master CPU Select
-#define GPIO_GPECSEL3_GPIO151_S   28
-#define GPIO_GPECSEL3_GPIO151_M   0xF0000000  // GPIO151 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPECSEL4 register
-//
-//*****************************************************************************
-#define GPIO_GPECSEL4_GPIO152_S   0
-#define GPIO_GPECSEL4_GPIO152_M   0xF         // GPIO152 Master CPU Select
-#define GPIO_GPECSEL4_GPIO153_S   4
-#define GPIO_GPECSEL4_GPIO153_M   0xF0        // GPIO153 Master CPU Select
-#define GPIO_GPECSEL4_GPIO154_S   8
-#define GPIO_GPECSEL4_GPIO154_M   0xF00       // GPIO154 Master CPU Select
-#define GPIO_GPECSEL4_GPIO155_S   12
-#define GPIO_GPECSEL4_GPIO155_M   0xF000      // GPIO155 Master CPU Select
-#define GPIO_GPECSEL4_GPIO156_S   16
-#define GPIO_GPECSEL4_GPIO156_M   0xF0000     // GPIO156 Master CPU Select
-#define GPIO_GPECSEL4_GPIO157_S   20
-#define GPIO_GPECSEL4_GPIO157_M   0xF00000    // GPIO157 Master CPU Select
-#define GPIO_GPECSEL4_GPIO158_S   24
-#define GPIO_GPECSEL4_GPIO158_M   0xF000000   // GPIO158 Master CPU Select
-#define GPIO_GPECSEL4_GPIO159_S   28
-#define GPIO_GPECSEL4_GPIO159_M   0xF0000000  // GPIO159 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPELOCK register
-//
-//*****************************************************************************
-#define GPIO_GPELOCK_GPIO128      0x1         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO129      0x2         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO130      0x4         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO131      0x8         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO132      0x10        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO133      0x20        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO134      0x40        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO135      0x80        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO136      0x100       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO137      0x200       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO138      0x400       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO139      0x800       // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO140      0x1000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO141      0x2000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO142      0x4000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO143      0x8000      // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO144      0x10000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO145      0x20000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO146      0x40000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO147      0x80000     // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO148      0x100000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO149      0x200000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO150      0x400000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO151      0x800000    // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO152      0x1000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO153      0x2000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO154      0x4000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO155      0x8000000   // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO156      0x10000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO157      0x20000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO158      0x40000000  // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPELOCK_GPIO159      0x80000000  // Configuration Lock bit for this
-                                              // pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPECR register
-//
-//*****************************************************************************
-#define GPIO_GPECR_GPIO128        0x1         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO129        0x2         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO130        0x4         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO131        0x8         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO132        0x10        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO133        0x20        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO134        0x40        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO135        0x80        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO136        0x100       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO137        0x200       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO138        0x400       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO139        0x800       // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO140        0x1000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO141        0x2000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO142        0x4000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO143        0x8000      // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO144        0x10000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO145        0x20000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO146        0x40000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO147        0x80000     // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO148        0x100000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO149        0x200000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO150        0x400000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO151        0x800000    // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO152        0x1000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO153        0x2000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO154        0x4000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO155        0x8000000   // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO156        0x10000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO157        0x20000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO158        0x40000000  // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPECR_GPIO159        0x80000000  // Configuration lock commit bit
-                                              // for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFCTRL register
-//
-//*****************************************************************************
-#define GPIO_GPFCTRL_QUALPRD0_S   0
-#define GPIO_GPFCTRL_QUALPRD0_M   0xFF        // Qualification sampling period
-                                              // for GPIO160 to GPIO167
-#define GPIO_GPFCTRL_QUALPRD1_S   8
-#define GPIO_GPFCTRL_QUALPRD1_M   0xFF00      // Qualification sampling period
-                                              // for GPIO168
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFQSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPFQSEL1_GPIO160_S   0
-#define GPIO_GPFQSEL1_GPIO160_M   0x3         // Select input qualification type
-                                              // for GPIO160
-#define GPIO_GPFQSEL1_GPIO161_S   2
-#define GPIO_GPFQSEL1_GPIO161_M   0xC         // Select input qualification type
-                                              // for GPIO161
-#define GPIO_GPFQSEL1_GPIO162_S   4
-#define GPIO_GPFQSEL1_GPIO162_M   0x30        // Select input qualification type
-                                              // for GPIO162
-#define GPIO_GPFQSEL1_GPIO163_S   6
-#define GPIO_GPFQSEL1_GPIO163_M   0xC0        // Select input qualification type
-                                              // for GPIO163
-#define GPIO_GPFQSEL1_GPIO164_S   8
-#define GPIO_GPFQSEL1_GPIO164_M   0x300       // Select input qualification type
-                                              // for GPIO164
-#define GPIO_GPFQSEL1_GPIO165_S   10
-#define GPIO_GPFQSEL1_GPIO165_M   0xC00       // Select input qualification type
-                                              // for GPIO165
-#define GPIO_GPFQSEL1_GPIO166_S   12
-#define GPIO_GPFQSEL1_GPIO166_M   0x3000      // Select input qualification type
-                                              // for GPIO166
-#define GPIO_GPFQSEL1_GPIO167_S   14
-#define GPIO_GPFQSEL1_GPIO167_M   0xC000      // Select input qualification type
-                                              // for GPIO167
-#define GPIO_GPFQSEL1_GPIO168_S   16
-#define GPIO_GPFQSEL1_GPIO168_M   0x30000     // Select input qualification type
-                                              // for GPIO168
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPFMUX1_GPIO160_S    0
-#define GPIO_GPFMUX1_GPIO160_M    0x3         // Defines pin-muxing selection
-                                              // for GPIO160
-#define GPIO_GPFMUX1_GPIO161_S    2
-#define GPIO_GPFMUX1_GPIO161_M    0xC         // Defines pin-muxing selection
-                                              // for GPIO161
-#define GPIO_GPFMUX1_GPIO162_S    4
-#define GPIO_GPFMUX1_GPIO162_M    0x30        // Defines pin-muxing selection
-                                              // for GPIO162
-#define GPIO_GPFMUX1_GPIO163_S    6
-#define GPIO_GPFMUX1_GPIO163_M    0xC0        // Defines pin-muxing selection
-                                              // for GPIO163
-#define GPIO_GPFMUX1_GPIO164_S    8
-#define GPIO_GPFMUX1_GPIO164_M    0x300       // Defines pin-muxing selection
-                                              // for GPIO164
-#define GPIO_GPFMUX1_GPIO165_S    10
-#define GPIO_GPFMUX1_GPIO165_M    0xC00       // Defines pin-muxing selection
-                                              // for GPIO165
-#define GPIO_GPFMUX1_GPIO166_S    12
-#define GPIO_GPFMUX1_GPIO166_M    0x3000      // Defines pin-muxing selection
-                                              // for GPIO166
-#define GPIO_GPFMUX1_GPIO167_S    14
-#define GPIO_GPFMUX1_GPIO167_M    0xC000      // Defines pin-muxing selection
-                                              // for GPIO167
-#define GPIO_GPFMUX1_GPIO168_S    16
-#define GPIO_GPFMUX1_GPIO168_M    0x30000     // Defines pin-muxing selection
-                                              // for GPIO168
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFDIR register
-//
-//*****************************************************************************
-#define GPIO_GPFDIR_GPIO160       0x1         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPFDIR_GPIO161       0x2         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPFDIR_GPIO162       0x4         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPFDIR_GPIO163       0x8         // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPFDIR_GPIO164       0x10        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPFDIR_GPIO165       0x20        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPFDIR_GPIO166       0x40        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPFDIR_GPIO167       0x80        // Defines direction for this pin
-                                              // in GPIO mode
-#define GPIO_GPFDIR_GPIO168       0x100       // Defines direction for this pin
-                                              // in GPIO mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFPUD register
-//
-//*****************************************************************************
-#define GPIO_GPFPUD_GPIO160       0x1         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPFPUD_GPIO161       0x2         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPFPUD_GPIO162       0x4         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPFPUD_GPIO163       0x8         // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPFPUD_GPIO164       0x10        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPFPUD_GPIO165       0x20        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPFPUD_GPIO166       0x40        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPFPUD_GPIO167       0x80        // Pull-Up Disable control for
-                                              // this pin
-#define GPIO_GPFPUD_GPIO168       0x100       // Pull-Up Disable control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFINV register
-//
-//*****************************************************************************
-#define GPIO_GPFINV_GPIO160       0x1         // Input inversion control for
-                                              // this pin
-#define GPIO_GPFINV_GPIO161       0x2         // Input inversion control for
-                                              // this pin
-#define GPIO_GPFINV_GPIO162       0x4         // Input inversion control for
-                                              // this pin
-#define GPIO_GPFINV_GPIO163       0x8         // Input inversion control for
-                                              // this pin
-#define GPIO_GPFINV_GPIO164       0x10        // Input inversion control for
-                                              // this pin
-#define GPIO_GPFINV_GPIO165       0x20        // Input inversion control for
-                                              // this pin
-#define GPIO_GPFINV_GPIO166       0x40        // Input inversion control for
-                                              // this pin
-#define GPIO_GPFINV_GPIO167       0x80        // Input inversion control for
-                                              // this pin
-#define GPIO_GPFINV_GPIO168       0x100       // Input inversion control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFODR register
-//
-//*****************************************************************************
-#define GPIO_GPFODR_GPIO160       0x1         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPFODR_GPIO161       0x2         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPFODR_GPIO162       0x4         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPFODR_GPIO163       0x8         // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPFODR_GPIO164       0x10        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPFODR_GPIO165       0x20        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPFODR_GPIO166       0x40        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPFODR_GPIO167       0x80        // Outpout Open-Drain control for
-                                              // this pin
-#define GPIO_GPFODR_GPIO168       0x100       // Outpout Open-Drain control for
-                                              // this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFGMUX1 register
-//
-//*****************************************************************************
-#define GPIO_GPFGMUX1_GPIO160_S   0
-#define GPIO_GPFGMUX1_GPIO160_M   0x3         // Defines pin-muxing selection
-                                              // for GPIO160
-#define GPIO_GPFGMUX1_GPIO161_S   2
-#define GPIO_GPFGMUX1_GPIO161_M   0xC         // Defines pin-muxing selection
-                                              // for GPIO161
-#define GPIO_GPFGMUX1_GPIO162_S   4
-#define GPIO_GPFGMUX1_GPIO162_M   0x30        // Defines pin-muxing selection
-                                              // for GPIO162
-#define GPIO_GPFGMUX1_GPIO163_S   6
-#define GPIO_GPFGMUX1_GPIO163_M   0xC0        // Defines pin-muxing selection
-                                              // for GPIO163
-#define GPIO_GPFGMUX1_GPIO164_S   8
-#define GPIO_GPFGMUX1_GPIO164_M   0x300       // Defines pin-muxing selection
-                                              // for GPIO164
-#define GPIO_GPFGMUX1_GPIO165_S   10
-#define GPIO_GPFGMUX1_GPIO165_M   0xC00       // Defines pin-muxing selection
-                                              // for GPIO165
-#define GPIO_GPFGMUX1_GPIO166_S   12
-#define GPIO_GPFGMUX1_GPIO166_M   0x3000      // Defines pin-muxing selection
-                                              // for GPIO166
-#define GPIO_GPFGMUX1_GPIO167_S   14
-#define GPIO_GPFGMUX1_GPIO167_M   0xC000      // Defines pin-muxing selection
-                                              // for GPIO167
-#define GPIO_GPFGMUX1_GPIO168_S   16
-#define GPIO_GPFGMUX1_GPIO168_M   0x30000     // Defines pin-muxing selection
-                                              // for GPIO168
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFCSEL1 register
-//
-//*****************************************************************************
-#define GPIO_GPFCSEL1_GPIO160_S   0
-#define GPIO_GPFCSEL1_GPIO160_M   0xF         // GPIO160 Master CPU Select
-#define GPIO_GPFCSEL1_GPIO161_S   4
-#define GPIO_GPFCSEL1_GPIO161_M   0xF0        // GPIO161 Master CPU Select
-#define GPIO_GPFCSEL1_GPIO162_S   8
-#define GPIO_GPFCSEL1_GPIO162_M   0xF00       // GPIO162 Master CPU Select
-#define GPIO_GPFCSEL1_GPIO163_S   12
-#define GPIO_GPFCSEL1_GPIO163_M   0xF000      // GPIO163 Master CPU Select
-#define GPIO_GPFCSEL1_GPIO164_S   16
-#define GPIO_GPFCSEL1_GPIO164_M   0xF0000     // GPIO164 Master CPU Select
-#define GPIO_GPFCSEL1_GPIO165_S   20
-#define GPIO_GPFCSEL1_GPIO165_M   0xF00000    // GPIO165 Master CPU Select
-#define GPIO_GPFCSEL1_GPIO166_S   24
-#define GPIO_GPFCSEL1_GPIO166_M   0xF000000   // GPIO166 Master CPU Select
-#define GPIO_GPFCSEL1_GPIO167_S   28
-#define GPIO_GPFCSEL1_GPIO167_M   0xF0000000  // GPIO167 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFCSEL2 register
-//
-//*****************************************************************************
-#define GPIO_GPFCSEL2_GPIO168_S   0
-#define GPIO_GPFCSEL2_GPIO168_M   0xF         // GPIO168 Master CPU Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFLOCK register
-//
-//*****************************************************************************
-#define GPIO_GPFLOCK_GPIO160      0x1         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPFLOCK_GPIO161      0x2         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPFLOCK_GPIO162      0x4         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPFLOCK_GPIO163      0x8         // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPFLOCK_GPIO164      0x10        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPFLOCK_GPIO165      0x20        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPFLOCK_GPIO166      0x40        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPFLOCK_GPIO167      0x80        // Configuration Lock bit for this
-                                              // pin
-#define GPIO_GPFLOCK_GPIO168      0x100       // Configuration Lock bit for this
-                                              // pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFCR register
-//
-//*****************************************************************************
-#define GPIO_GPFCR_GPIO160        0x1         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPFCR_GPIO161        0x2         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPFCR_GPIO162        0x4         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPFCR_GPIO163        0x8         // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPFCR_GPIO164        0x10        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPFCR_GPIO165        0x20        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPFCR_GPIO166        0x40        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPFCR_GPIO167        0x80        // Configuration lock commit bit
-                                              // for this pin
-#define GPIO_GPFCR_GPIO168        0x100       // Configuration lock commit bit
-                                              // for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPADAT register
-//
-//*****************************************************************************
-#define GPIO_GPADAT_GPIO0         0x1         // Data Register for this pin
-#define GPIO_GPADAT_GPIO1         0x2         // Data Register for this pin
-#define GPIO_GPADAT_GPIO2         0x4         // Data Register for this pin
-#define GPIO_GPADAT_GPIO3         0x8         // Data Register for this pin
-#define GPIO_GPADAT_GPIO4         0x10        // Data Register for this pin
-#define GPIO_GPADAT_GPIO5         0x20        // Data Register for this pin
-#define GPIO_GPADAT_GPIO6         0x40        // Data Register for this pin
-#define GPIO_GPADAT_GPIO7         0x80        // Data Register for this pin
-#define GPIO_GPADAT_GPIO8         0x100       // Data Register for this pin
-#define GPIO_GPADAT_GPIO9         0x200       // Data Register for this pin
-#define GPIO_GPADAT_GPIO10        0x400       // Data Register for this pin
-#define GPIO_GPADAT_GPIO11        0x800       // Data Register for this pin
-#define GPIO_GPADAT_GPIO12        0x1000      // Data Register for this pin
-#define GPIO_GPADAT_GPIO13        0x2000      // Data Register for this pin
-#define GPIO_GPADAT_GPIO14        0x4000      // Data Register for this pin
-#define GPIO_GPADAT_GPIO15        0x8000      // Data Register for this pin
-#define GPIO_GPADAT_GPIO16        0x10000     // Data Register for this pin
-#define GPIO_GPADAT_GPIO17        0x20000     // Data Register for this pin
-#define GPIO_GPADAT_GPIO18        0x40000     // Data Register for this pin
-#define GPIO_GPADAT_GPIO19        0x80000     // Data Register for this pin
-#define GPIO_GPADAT_GPIO20        0x100000    // Data Register for this pin
-#define GPIO_GPADAT_GPIO21        0x200000    // Data Register for this pin
-#define GPIO_GPADAT_GPIO22        0x400000    // Data Register for this pin
-#define GPIO_GPADAT_GPIO23        0x800000    // Data Register for this pin
-#define GPIO_GPADAT_GPIO24        0x1000000   // Data Register for this pin
-#define GPIO_GPADAT_GPIO25        0x2000000   // Data Register for this pin
-#define GPIO_GPADAT_GPIO26        0x4000000   // Data Register for this pin
-#define GPIO_GPADAT_GPIO27        0x8000000   // Data Register for this pin
-#define GPIO_GPADAT_GPIO28        0x10000000  // Data Register for this pin
-#define GPIO_GPADAT_GPIO29        0x20000000  // Data Register for this pin
-#define GPIO_GPADAT_GPIO30        0x40000000  // Data Register for this pin
-#define GPIO_GPADAT_GPIO31        0x80000000  // Data Register for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPASET register
-//
-//*****************************************************************************
-#define GPIO_GPASET_GPIO0         0x1         // Output Set bit for this pin
-#define GPIO_GPASET_GPIO1         0x2         // Output Set bit for this pin
-#define GPIO_GPASET_GPIO2         0x4         // Output Set bit for this pin
-#define GPIO_GPASET_GPIO3         0x8         // Output Set bit for this pin
-#define GPIO_GPASET_GPIO4         0x10        // Output Set bit for this pin
-#define GPIO_GPASET_GPIO5         0x20        // Output Set bit for this pin
-#define GPIO_GPASET_GPIO6         0x40        // Output Set bit for this pin
-#define GPIO_GPASET_GPIO7         0x80        // Output Set bit for this pin
-#define GPIO_GPASET_GPIO8         0x100       // Output Set bit for this pin
-#define GPIO_GPASET_GPIO9         0x200       // Output Set bit for this pin
-#define GPIO_GPASET_GPIO10        0x400       // Output Set bit for this pin
-#define GPIO_GPASET_GPIO11        0x800       // Output Set bit for this pin
-#define GPIO_GPASET_GPIO12        0x1000      // Output Set bit for this pin
-#define GPIO_GPASET_GPIO13        0x2000      // Output Set bit for this pin
-#define GPIO_GPASET_GPIO14        0x4000      // Output Set bit for this pin
-#define GPIO_GPASET_GPIO15        0x8000      // Output Set bit for this pin
-#define GPIO_GPASET_GPIO16        0x10000     // Output Set bit for this pin
-#define GPIO_GPASET_GPIO17        0x20000     // Output Set bit for this pin
-#define GPIO_GPASET_GPIO18        0x40000     // Output Set bit for this pin
-#define GPIO_GPASET_GPIO19        0x80000     // Output Set bit for this pin
-#define GPIO_GPASET_GPIO20        0x100000    // Output Set bit for this pin
-#define GPIO_GPASET_GPIO21        0x200000    // Output Set bit for this pin
-#define GPIO_GPASET_GPIO22        0x400000    // Output Set bit for this pin
-#define GPIO_GPASET_GPIO23        0x800000    // Output Set bit for this pin
-#define GPIO_GPASET_GPIO24        0x1000000   // Output Set bit for this pin
-#define GPIO_GPASET_GPIO25        0x2000000   // Output Set bit for this pin
-#define GPIO_GPASET_GPIO26        0x4000000   // Output Set bit for this pin
-#define GPIO_GPASET_GPIO27        0x8000000   // Output Set bit for this pin
-#define GPIO_GPASET_GPIO28        0x10000000  // Output Set bit for this pin
-#define GPIO_GPASET_GPIO29        0x20000000  // Output Set bit for this pin
-#define GPIO_GPASET_GPIO30        0x40000000  // Output Set bit for this pin
-#define GPIO_GPASET_GPIO31        0x80000000  // Output Set bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPACLEAR register
-//
-//*****************************************************************************
-#define GPIO_GPACLEAR_GPIO0       0x1         // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO1       0x2         // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO2       0x4         // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO3       0x8         // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO4       0x10        // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO5       0x20        // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO6       0x40        // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO7       0x80        // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO8       0x100       // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO9       0x200       // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO10      0x400       // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO11      0x800       // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO12      0x1000      // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO13      0x2000      // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO14      0x4000      // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO15      0x8000      // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO16      0x10000     // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO17      0x20000     // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO18      0x40000     // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO19      0x80000     // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO20      0x100000    // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO21      0x200000    // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO22      0x400000    // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO23      0x800000    // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO24      0x1000000   // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO25      0x2000000   // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO26      0x4000000   // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO27      0x8000000   // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO28      0x10000000  // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO29      0x20000000  // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO30      0x40000000  // Output Clear bit for this pin
-#define GPIO_GPACLEAR_GPIO31      0x80000000  // Output Clear bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPATOGGLE register
-//
-//*****************************************************************************
-#define GPIO_GPATOGGLE_GPIO0      0x1         // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO1      0x2         // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO2      0x4         // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO3      0x8         // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO4      0x10        // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO5      0x20        // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO6      0x40        // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO7      0x80        // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO8      0x100       // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO9      0x200       // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO10     0x400       // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO11     0x800       // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO12     0x1000      // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO13     0x2000      // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO14     0x4000      // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO15     0x8000      // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO16     0x10000     // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO17     0x20000     // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO18     0x40000     // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO19     0x80000     // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO20     0x100000    // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO21     0x200000    // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO22     0x400000    // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO23     0x800000    // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO24     0x1000000   // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO25     0x2000000   // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO26     0x4000000   // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO27     0x8000000   // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO28     0x10000000  // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO29     0x20000000  // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO30     0x40000000  // Output Toggle bit for this pin
-#define GPIO_GPATOGGLE_GPIO31     0x80000000  // Output Toggle bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBDAT register
-//
-//*****************************************************************************
-#define GPIO_GPBDAT_GPIO32        0x1         // Data Register for this pin
-#define GPIO_GPBDAT_GPIO33        0x2         // Data Register for this pin
-#define GPIO_GPBDAT_GPIO34        0x4         // Data Register for this pin
-#define GPIO_GPBDAT_GPIO35        0x8         // Data Register for this pin
-#define GPIO_GPBDAT_GPIO36        0x10        // Data Register for this pin
-#define GPIO_GPBDAT_GPIO37        0x20        // Data Register for this pin
-#define GPIO_GPBDAT_GPIO38        0x40        // Data Register for this pin
-#define GPIO_GPBDAT_GPIO39        0x80        // Data Register for this pin
-#define GPIO_GPBDAT_GPIO40        0x100       // Data Register for this pin
-#define GPIO_GPBDAT_GPIO41        0x200       // Data Register for this pin
-#define GPIO_GPBDAT_GPIO42        0x400       // Data Register for this pin
-#define GPIO_GPBDAT_GPIO43        0x800       // Data Register for this pin
-#define GPIO_GPBDAT_GPIO44        0x1000      // Data Register for this pin
-#define GPIO_GPBDAT_GPIO45        0x2000      // Data Register for this pin
-#define GPIO_GPBDAT_GPIO46        0x4000      // Data Register for this pin
-#define GPIO_GPBDAT_GPIO47        0x8000      // Data Register for this pin
-#define GPIO_GPBDAT_GPIO48        0x10000     // Data Register for this pin
-#define GPIO_GPBDAT_GPIO49        0x20000     // Data Register for this pin
-#define GPIO_GPBDAT_GPIO50        0x40000     // Data Register for this pin
-#define GPIO_GPBDAT_GPIO51        0x80000     // Data Register for this pin
-#define GPIO_GPBDAT_GPIO52        0x100000    // Data Register for this pin
-#define GPIO_GPBDAT_GPIO53        0x200000    // Data Register for this pin
-#define GPIO_GPBDAT_GPIO54        0x400000    // Data Register for this pin
-#define GPIO_GPBDAT_GPIO55        0x800000    // Data Register for this pin
-#define GPIO_GPBDAT_GPIO56        0x1000000   // Data Register for this pin
-#define GPIO_GPBDAT_GPIO57        0x2000000   // Data Register for this pin
-#define GPIO_GPBDAT_GPIO58        0x4000000   // Data Register for this pin
-#define GPIO_GPBDAT_GPIO59        0x8000000   // Data Register for this pin
-#define GPIO_GPBDAT_GPIO60        0x10000000  // Data Register for this pin
-#define GPIO_GPBDAT_GPIO61        0x20000000  // Data Register for this pin
-#define GPIO_GPBDAT_GPIO62        0x40000000  // Data Register for this pin
-#define GPIO_GPBDAT_GPIO63        0x80000000  // Data Register for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBSET register
-//
-//*****************************************************************************
-#define GPIO_GPBSET_GPIO32        0x1         // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO33        0x2         // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO34        0x4         // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO35        0x8         // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO36        0x10        // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO37        0x20        // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO38        0x40        // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO39        0x80        // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO40        0x100       // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO41        0x200       // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO42        0x400       // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO43        0x800       // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO44        0x1000      // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO45        0x2000      // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO46        0x4000      // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO47        0x8000      // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO48        0x10000     // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO49        0x20000     // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO50        0x40000     // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO51        0x80000     // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO52        0x100000    // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO53        0x200000    // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO54        0x400000    // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO55        0x800000    // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO56        0x1000000   // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO57        0x2000000   // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO58        0x4000000   // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO59        0x8000000   // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO60        0x10000000  // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO61        0x20000000  // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO62        0x40000000  // Output Set bit for this pin
-#define GPIO_GPBSET_GPIO63        0x80000000  // Output Set bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBCLEAR register
-//
-//*****************************************************************************
-#define GPIO_GPBCLEAR_GPIO32      0x1         // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO33      0x2         // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO34      0x4         // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO35      0x8         // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO36      0x10        // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO37      0x20        // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO38      0x40        // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO39      0x80        // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO40      0x100       // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO41      0x200       // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO42      0x400       // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO43      0x800       // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO44      0x1000      // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO45      0x2000      // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO46      0x4000      // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO47      0x8000      // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO48      0x10000     // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO49      0x20000     // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO50      0x40000     // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO51      0x80000     // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO52      0x100000    // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO53      0x200000    // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO54      0x400000    // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO55      0x800000    // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO56      0x1000000   // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO57      0x2000000   // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO58      0x4000000   // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO59      0x8000000   // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO60      0x10000000  // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO61      0x20000000  // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO62      0x40000000  // Output Clear bit for this pin
-#define GPIO_GPBCLEAR_GPIO63      0x80000000  // Output Clear bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPBTOGGLE register
-//
-//*****************************************************************************
-#define GPIO_GPBTOGGLE_GPIO32     0x1         // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO33     0x2         // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO34     0x4         // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO35     0x8         // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO36     0x10        // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO37     0x20        // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO38     0x40        // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO39     0x80        // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO40     0x100       // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO41     0x200       // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO42     0x400       // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO43     0x800       // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO44     0x1000      // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO45     0x2000      // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO46     0x4000      // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO47     0x8000      // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO48     0x10000     // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO49     0x20000     // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO50     0x40000     // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO51     0x80000     // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO52     0x100000    // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO53     0x200000    // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO54     0x400000    // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO55     0x800000    // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO56     0x1000000   // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO57     0x2000000   // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO58     0x4000000   // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO59     0x8000000   // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO60     0x10000000  // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO61     0x20000000  // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO62     0x40000000  // Output Toggle bit for this pin
-#define GPIO_GPBTOGGLE_GPIO63     0x80000000  // Output Toggle bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCDAT register
-//
-//*****************************************************************************
-#define GPIO_GPCDAT_GPIO64        0x1         // Data Register for this pin
-#define GPIO_GPCDAT_GPIO65        0x2         // Data Register for this pin
-#define GPIO_GPCDAT_GPIO66        0x4         // Data Register for this pin
-#define GPIO_GPCDAT_GPIO67        0x8         // Data Register for this pin
-#define GPIO_GPCDAT_GPIO68        0x10        // Data Register for this pin
-#define GPIO_GPCDAT_GPIO69        0x20        // Data Register for this pin
-#define GPIO_GPCDAT_GPIO70        0x40        // Data Register for this pin
-#define GPIO_GPCDAT_GPIO71        0x80        // Data Register for this pin
-#define GPIO_GPCDAT_GPIO72        0x100       // Data Register for this pin
-#define GPIO_GPCDAT_GPIO73        0x200       // Data Register for this pin
-#define GPIO_GPCDAT_GPIO74        0x400       // Data Register for this pin
-#define GPIO_GPCDAT_GPIO75        0x800       // Data Register for this pin
-#define GPIO_GPCDAT_GPIO76        0x1000      // Data Register for this pin
-#define GPIO_GPCDAT_GPIO77        0x2000      // Data Register for this pin
-#define GPIO_GPCDAT_GPIO78        0x4000      // Data Register for this pin
-#define GPIO_GPCDAT_GPIO79        0x8000      // Data Register for this pin
-#define GPIO_GPCDAT_GPIO80        0x10000     // Data Register for this pin
-#define GPIO_GPCDAT_GPIO81        0x20000     // Data Register for this pin
-#define GPIO_GPCDAT_GPIO82        0x40000     // Data Register for this pin
-#define GPIO_GPCDAT_GPIO83        0x80000     // Data Register for this pin
-#define GPIO_GPCDAT_GPIO84        0x100000    // Data Register for this pin
-#define GPIO_GPCDAT_GPIO85        0x200000    // Data Register for this pin
-#define GPIO_GPCDAT_GPIO86        0x400000    // Data Register for this pin
-#define GPIO_GPCDAT_GPIO87        0x800000    // Data Register for this pin
-#define GPIO_GPCDAT_GPIO88        0x1000000   // Data Register for this pin
-#define GPIO_GPCDAT_GPIO89        0x2000000   // Data Register for this pin
-#define GPIO_GPCDAT_GPIO90        0x4000000   // Data Register for this pin
-#define GPIO_GPCDAT_GPIO91        0x8000000   // Data Register for this pin
-#define GPIO_GPCDAT_GPIO92        0x10000000  // Data Register for this pin
-#define GPIO_GPCDAT_GPIO93        0x20000000  // Data Register for this pin
-#define GPIO_GPCDAT_GPIO94        0x40000000  // Data Register for this pin
-#define GPIO_GPCDAT_GPIO95        0x80000000  // Data Register for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCSET register
-//
-//*****************************************************************************
-#define GPIO_GPCSET_GPIO64        0x1         // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO65        0x2         // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO66        0x4         // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO67        0x8         // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO68        0x10        // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO69        0x20        // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO70        0x40        // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO71        0x80        // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO72        0x100       // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO73        0x200       // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO74        0x400       // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO75        0x800       // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO76        0x1000      // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO77        0x2000      // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO78        0x4000      // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO79        0x8000      // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO80        0x10000     // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO81        0x20000     // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO82        0x40000     // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO83        0x80000     // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO84        0x100000    // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO85        0x200000    // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO86        0x400000    // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO87        0x800000    // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO88        0x1000000   // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO89        0x2000000   // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO90        0x4000000   // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO91        0x8000000   // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO92        0x10000000  // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO93        0x20000000  // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO94        0x40000000  // Output Set bit for this pin
-#define GPIO_GPCSET_GPIO95        0x80000000  // Output Set bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCCLEAR register
-//
-//*****************************************************************************
-#define GPIO_GPCCLEAR_GPIO64      0x1         // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO65      0x2         // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO66      0x4         // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO67      0x8         // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO68      0x10        // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO69      0x20        // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO70      0x40        // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO71      0x80        // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO72      0x100       // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO73      0x200       // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO74      0x400       // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO75      0x800       // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO76      0x1000      // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO77      0x2000      // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO78      0x4000      // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO79      0x8000      // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO80      0x10000     // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO81      0x20000     // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO82      0x40000     // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO83      0x80000     // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO84      0x100000    // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO85      0x200000    // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO86      0x400000    // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO87      0x800000    // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO88      0x1000000   // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO89      0x2000000   // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO90      0x4000000   // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO91      0x8000000   // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO92      0x10000000  // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO93      0x20000000  // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO94      0x40000000  // Output Clear bit for this pin
-#define GPIO_GPCCLEAR_GPIO95      0x80000000  // Output Clear bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPCTOGGLE register
-//
-//*****************************************************************************
-#define GPIO_GPCTOGGLE_GPIO64     0x1         // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO65     0x2         // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO66     0x4         // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO67     0x8         // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO68     0x10        // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO69     0x20        // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO70     0x40        // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO71     0x80        // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO72     0x100       // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO73     0x200       // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO74     0x400       // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO75     0x800       // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO76     0x1000      // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO77     0x2000      // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO78     0x4000      // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO79     0x8000      // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO80     0x10000     // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO81     0x20000     // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO82     0x40000     // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO83     0x80000     // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO84     0x100000    // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO85     0x200000    // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO86     0x400000    // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO87     0x800000    // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO88     0x1000000   // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO89     0x2000000   // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO90     0x4000000   // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO91     0x8000000   // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO92     0x10000000  // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO93     0x20000000  // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO94     0x40000000  // Output Toggle bit for this pin
-#define GPIO_GPCTOGGLE_GPIO95     0x80000000  // Output Toggle bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDDAT register
-//
-//*****************************************************************************
-#define GPIO_GPDDAT_GPIO96        0x1         // Data Register for this pin
-#define GPIO_GPDDAT_GPIO97        0x2         // Data Register for this pin
-#define GPIO_GPDDAT_GPIO98        0x4         // Data Register for this pin
-#define GPIO_GPDDAT_GPIO99        0x8         // Data Register for this pin
-#define GPIO_GPDDAT_GPIO100       0x10        // Data Register for this pin
-#define GPIO_GPDDAT_GPIO101       0x20        // Data Register for this pin
-#define GPIO_GPDDAT_GPIO102       0x40        // Data Register for this pin
-#define GPIO_GPDDAT_GPIO103       0x80        // Data Register for this pin
-#define GPIO_GPDDAT_GPIO104       0x100       // Data Register for this pin
-#define GPIO_GPDDAT_GPIO105       0x200       // Data Register for this pin
-#define GPIO_GPDDAT_GPIO106       0x400       // Data Register for this pin
-#define GPIO_GPDDAT_GPIO107       0x800       // Data Register for this pin
-#define GPIO_GPDDAT_GPIO108       0x1000      // Data Register for this pin
-#define GPIO_GPDDAT_GPIO109       0x2000      // Data Register for this pin
-#define GPIO_GPDDAT_GPIO110       0x4000      // Data Register for this pin
-#define GPIO_GPDDAT_GPIO111       0x8000      // Data Register for this pin
-#define GPIO_GPDDAT_GPIO112       0x10000     // Data Register for this pin
-#define GPIO_GPDDAT_GPIO113       0x20000     // Data Register for this pin
-#define GPIO_GPDDAT_GPIO114       0x40000     // Data Register for this pin
-#define GPIO_GPDDAT_GPIO115       0x80000     // Data Register for this pin
-#define GPIO_GPDDAT_GPIO116       0x100000    // Data Register for this pin
-#define GPIO_GPDDAT_GPIO117       0x200000    // Data Register for this pin
-#define GPIO_GPDDAT_GPIO118       0x400000    // Data Register for this pin
-#define GPIO_GPDDAT_GPIO119       0x800000    // Data Register for this pin
-#define GPIO_GPDDAT_GPIO120       0x1000000   // Data Register for this pin
-#define GPIO_GPDDAT_GPIO121       0x2000000   // Data Register for this pin
-#define GPIO_GPDDAT_GPIO122       0x4000000   // Data Register for this pin
-#define GPIO_GPDDAT_GPIO123       0x8000000   // Data Register for this pin
-#define GPIO_GPDDAT_GPIO124       0x10000000  // Data Register for this pin
-#define GPIO_GPDDAT_GPIO125       0x20000000  // Data Register for this pin
-#define GPIO_GPDDAT_GPIO126       0x40000000  // Data Register for this pin
-#define GPIO_GPDDAT_GPIO127       0x80000000  // Data Register for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDSET register
-//
-//*****************************************************************************
-#define GPIO_GPDSET_GPIO96        0x1         // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO97        0x2         // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO98        0x4         // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO99        0x8         // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO100       0x10        // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO101       0x20        // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO102       0x40        // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO103       0x80        // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO104       0x100       // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO105       0x200       // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO106       0x400       // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO107       0x800       // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO108       0x1000      // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO109       0x2000      // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO110       0x4000      // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO111       0x8000      // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO112       0x10000     // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO113       0x20000     // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO114       0x40000     // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO115       0x80000     // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO116       0x100000    // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO117       0x200000    // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO118       0x400000    // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO119       0x800000    // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO120       0x1000000   // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO121       0x2000000   // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO122       0x4000000   // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO123       0x8000000   // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO124       0x10000000  // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO125       0x20000000  // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO126       0x40000000  // Output Set bit for this pin
-#define GPIO_GPDSET_GPIO127       0x80000000  // Output Set bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDCLEAR register
-//
-//*****************************************************************************
-#define GPIO_GPDCLEAR_GPIO96      0x1         // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO97      0x2         // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO98      0x4         // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO99      0x8         // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO100     0x10        // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO101     0x20        // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO102     0x40        // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO103     0x80        // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO104     0x100       // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO105     0x200       // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO106     0x400       // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO107     0x800       // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO108     0x1000      // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO109     0x2000      // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO110     0x4000      // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO111     0x8000      // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO112     0x10000     // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO113     0x20000     // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO114     0x40000     // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO115     0x80000     // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO116     0x100000    // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO117     0x200000    // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO118     0x400000    // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO119     0x800000    // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO120     0x1000000   // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO121     0x2000000   // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO122     0x4000000   // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO123     0x8000000   // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO124     0x10000000  // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO125     0x20000000  // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO126     0x40000000  // Output Clear bit for this pin
-#define GPIO_GPDCLEAR_GPIO127     0x80000000  // Output Clear bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPDTOGGLE register
-//
-//*****************************************************************************
-#define GPIO_GPDTOGGLE_GPIO96     0x1         // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO97     0x2         // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO98     0x4         // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO99     0x8         // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO100    0x10        // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO101    0x20        // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO102    0x40        // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO103    0x80        // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO104    0x100       // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO105    0x200       // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO106    0x400       // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO107    0x800       // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO108    0x1000      // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO109    0x2000      // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO110    0x4000      // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO111    0x8000      // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO112    0x10000     // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO113    0x20000     // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO114    0x40000     // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO115    0x80000     // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO116    0x100000    // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO117    0x200000    // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO118    0x400000    // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO119    0x800000    // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO120    0x1000000   // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO121    0x2000000   // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO122    0x4000000   // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO123    0x8000000   // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO124    0x10000000  // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO125    0x20000000  // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO126    0x40000000  // Output Toggle bit for this pin
-#define GPIO_GPDTOGGLE_GPIO127    0x80000000  // Output Toggle bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPEDAT register
-//
-//*****************************************************************************
-#define GPIO_GPEDAT_GPIO128       0x1         // Data Register for this pin
-#define GPIO_GPEDAT_GPIO129       0x2         // Data Register for this pin
-#define GPIO_GPEDAT_GPIO130       0x4         // Data Register for this pin
-#define GPIO_GPEDAT_GPIO131       0x8         // Data Register for this pin
-#define GPIO_GPEDAT_GPIO132       0x10        // Data Register for this pin
-#define GPIO_GPEDAT_GPIO133       0x20        // Data Register for this pin
-#define GPIO_GPEDAT_GPIO134       0x40        // Data Register for this pin
-#define GPIO_GPEDAT_GPIO135       0x80        // Data Register for this pin
-#define GPIO_GPEDAT_GPIO136       0x100       // Data Register for this pin
-#define GPIO_GPEDAT_GPIO137       0x200       // Data Register for this pin
-#define GPIO_GPEDAT_GPIO138       0x400       // Data Register for this pin
-#define GPIO_GPEDAT_GPIO139       0x800       // Data Register for this pin
-#define GPIO_GPEDAT_GPIO140       0x1000      // Data Register for this pin
-#define GPIO_GPEDAT_GPIO141       0x2000      // Data Register for this pin
-#define GPIO_GPEDAT_GPIO142       0x4000      // Data Register for this pin
-#define GPIO_GPEDAT_GPIO143       0x8000      // Data Register for this pin
-#define GPIO_GPEDAT_GPIO144       0x10000     // Data Register for this pin
-#define GPIO_GPEDAT_GPIO145       0x20000     // Data Register for this pin
-#define GPIO_GPEDAT_GPIO146       0x40000     // Data Register for this pin
-#define GPIO_GPEDAT_GPIO147       0x80000     // Data Register for this pin
-#define GPIO_GPEDAT_GPIO148       0x100000    // Data Register for this pin
-#define GPIO_GPEDAT_GPIO149       0x200000    // Data Register for this pin
-#define GPIO_GPEDAT_GPIO150       0x400000    // Data Register for this pin
-#define GPIO_GPEDAT_GPIO151       0x800000    // Data Register for this pin
-#define GPIO_GPEDAT_GPIO152       0x1000000   // Data Register for this pin
-#define GPIO_GPEDAT_GPIO153       0x2000000   // Data Register for this pin
-#define GPIO_GPEDAT_GPIO154       0x4000000   // Data Register for this pin
-#define GPIO_GPEDAT_GPIO155       0x8000000   // Data Register for this pin
-#define GPIO_GPEDAT_GPIO156       0x10000000  // Data Register for this pin
-#define GPIO_GPEDAT_GPIO157       0x20000000  // Data Register for this pin
-#define GPIO_GPEDAT_GPIO158       0x40000000  // Data Register for this pin
-#define GPIO_GPEDAT_GPIO159       0x80000000  // Data Register for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPESET register
-//
-//*****************************************************************************
-#define GPIO_GPESET_GPIO128       0x1         // Output Set bit for this pin
-#define GPIO_GPESET_GPIO129       0x2         // Output Set bit for this pin
-#define GPIO_GPESET_GPIO130       0x4         // Output Set bit for this pin
-#define GPIO_GPESET_GPIO131       0x8         // Output Set bit for this pin
-#define GPIO_GPESET_GPIO132       0x10        // Output Set bit for this pin
-#define GPIO_GPESET_GPIO133       0x20        // Output Set bit for this pin
-#define GPIO_GPESET_GPIO134       0x40        // Output Set bit for this pin
-#define GPIO_GPESET_GPIO135       0x80        // Output Set bit for this pin
-#define GPIO_GPESET_GPIO136       0x100       // Output Set bit for this pin
-#define GPIO_GPESET_GPIO137       0x200       // Output Set bit for this pin
-#define GPIO_GPESET_GPIO138       0x400       // Output Set bit for this pin
-#define GPIO_GPESET_GPIO139       0x800       // Output Set bit for this pin
-#define GPIO_GPESET_GPIO140       0x1000      // Output Set bit for this pin
-#define GPIO_GPESET_GPIO141       0x2000      // Output Set bit for this pin
-#define GPIO_GPESET_GPIO142       0x4000      // Output Set bit for this pin
-#define GPIO_GPESET_GPIO143       0x8000      // Output Set bit for this pin
-#define GPIO_GPESET_GPIO144       0x10000     // Output Set bit for this pin
-#define GPIO_GPESET_GPIO145       0x20000     // Output Set bit for this pin
-#define GPIO_GPESET_GPIO146       0x40000     // Output Set bit for this pin
-#define GPIO_GPESET_GPIO147       0x80000     // Output Set bit for this pin
-#define GPIO_GPESET_GPIO148       0x100000    // Output Set bit for this pin
-#define GPIO_GPESET_GPIO149       0x200000    // Output Set bit for this pin
-#define GPIO_GPESET_GPIO150       0x400000    // Output Set bit for this pin
-#define GPIO_GPESET_GPIO151       0x800000    // Output Set bit for this pin
-#define GPIO_GPESET_GPIO152       0x1000000   // Output Set bit for this pin
-#define GPIO_GPESET_GPIO153       0x2000000   // Output Set bit for this pin
-#define GPIO_GPESET_GPIO154       0x4000000   // Output Set bit for this pin
-#define GPIO_GPESET_GPIO155       0x8000000   // Output Set bit for this pin
-#define GPIO_GPESET_GPIO156       0x10000000  // Output Set bit for this pin
-#define GPIO_GPESET_GPIO157       0x20000000  // Output Set bit for this pin
-#define GPIO_GPESET_GPIO158       0x40000000  // Output Set bit for this pin
-#define GPIO_GPESET_GPIO159       0x80000000  // Output Set bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPECLEAR register
-//
-//*****************************************************************************
-#define GPIO_GPECLEAR_GPIO128     0x1         // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO129     0x2         // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO130     0x4         // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO131     0x8         // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO132     0x10        // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO133     0x20        // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO134     0x40        // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO135     0x80        // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO136     0x100       // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO137     0x200       // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO138     0x400       // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO139     0x800       // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO140     0x1000      // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO141     0x2000      // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO142     0x4000      // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO143     0x8000      // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO144     0x10000     // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO145     0x20000     // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO146     0x40000     // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO147     0x80000     // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO148     0x100000    // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO149     0x200000    // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO150     0x400000    // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO151     0x800000    // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO152     0x1000000   // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO153     0x2000000   // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO154     0x4000000   // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO155     0x8000000   // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO156     0x10000000  // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO157     0x20000000  // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO158     0x40000000  // Output Clear bit for this pin
-#define GPIO_GPECLEAR_GPIO159     0x80000000  // Output Clear bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPETOGGLE register
-//
-//*****************************************************************************
-#define GPIO_GPETOGGLE_GPIO128    0x1         // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO129    0x2         // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO130    0x4         // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO131    0x8         // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO132    0x10        // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO133    0x20        // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO134    0x40        // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO135    0x80        // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO136    0x100       // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO137    0x200       // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO138    0x400       // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO139    0x800       // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO140    0x1000      // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO141    0x2000      // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO142    0x4000      // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO143    0x8000      // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO144    0x10000     // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO145    0x20000     // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO146    0x40000     // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO147    0x80000     // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO148    0x100000    // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO149    0x200000    // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO150    0x400000    // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO151    0x800000    // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO152    0x1000000   // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO153    0x2000000   // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO154    0x4000000   // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO155    0x8000000   // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO156    0x10000000  // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO157    0x20000000  // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO158    0x40000000  // Output Toggle bit for this pin
-#define GPIO_GPETOGGLE_GPIO159    0x80000000  // Output Toggle bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFDAT register
-//
-//*****************************************************************************
-#define GPIO_GPFDAT_GPIO160       0x1         // Data Register for this pin
-#define GPIO_GPFDAT_GPIO161       0x2         // Data Register for this pin
-#define GPIO_GPFDAT_GPIO162       0x4         // Data Register for this pin
-#define GPIO_GPFDAT_GPIO163       0x8         // Data Register for this pin
-#define GPIO_GPFDAT_GPIO164       0x10        // Data Register for this pin
-#define GPIO_GPFDAT_GPIO165       0x20        // Data Register for this pin
-#define GPIO_GPFDAT_GPIO166       0x40        // Data Register for this pin
-#define GPIO_GPFDAT_GPIO167       0x80        // Data Register for this pin
-#define GPIO_GPFDAT_GPIO168       0x100       // Data Register for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFSET register
-//
-//*****************************************************************************
-#define GPIO_GPFSET_GPIO160       0x1         // Output Set bit for this pin
-#define GPIO_GPFSET_GPIO161       0x2         // Output Set bit for this pin
-#define GPIO_GPFSET_GPIO162       0x4         // Output Set bit for this pin
-#define GPIO_GPFSET_GPIO163       0x8         // Output Set bit for this pin
-#define GPIO_GPFSET_GPIO164       0x10        // Output Set bit for this pin
-#define GPIO_GPFSET_GPIO165       0x20        // Output Set bit for this pin
-#define GPIO_GPFSET_GPIO166       0x40        // Output Set bit for this pin
-#define GPIO_GPFSET_GPIO167       0x80        // Output Set bit for this pin
-#define GPIO_GPFSET_GPIO168       0x100       // Output Set bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFCLEAR register
-//
-//*****************************************************************************
-#define GPIO_GPFCLEAR_GPIO160     0x1         // Output Clear bit for this pin
-#define GPIO_GPFCLEAR_GPIO161     0x2         // Output Clear bit for this pin
-#define GPIO_GPFCLEAR_GPIO162     0x4         // Output Clear bit for this pin
-#define GPIO_GPFCLEAR_GPIO163     0x8         // Output Clear bit for this pin
-#define GPIO_GPFCLEAR_GPIO164     0x10        // Output Clear bit for this pin
-#define GPIO_GPFCLEAR_GPIO165     0x20        // Output Clear bit for this pin
-#define GPIO_GPFCLEAR_GPIO166     0x40        // Output Clear bit for this pin
-#define GPIO_GPFCLEAR_GPIO167     0x80        // Output Clear bit for this pin
-#define GPIO_GPFCLEAR_GPIO168     0x100       // Output Clear bit for this pin
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPFTOGGLE register
-//
-//*****************************************************************************
-#define GPIO_GPFTOGGLE_GPIO160    0x1         // Output Toggle bit for this pin
-#define GPIO_GPFTOGGLE_GPIO161    0x2         // Output Toggle bit for this pin
-#define GPIO_GPFTOGGLE_GPIO162    0x4         // Output Toggle bit for this pin
-#define GPIO_GPFTOGGLE_GPIO163    0x8         // Output Toggle bit for this pin
-#define GPIO_GPFTOGGLE_GPIO164    0x10        // Output Toggle bit for this pin
-#define GPIO_GPFTOGGLE_GPIO165    0x20        // Output Toggle bit for this pin
-#define GPIO_GPFTOGGLE_GPIO166    0x40        // Output Toggle bit for this pin
-#define GPIO_GPFTOGGLE_GPIO167    0x80        // Output Toggle bit for this pin
-#define GPIO_GPFTOGGLE_GPIO168    0x100       // Output Toggle bit for this pin
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_i2c.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_i2c.h
deleted file mode 100644
index 57a045c8f2..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_i2c.h
+++ /dev/null
@@ -1,244 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_i2c.h
-//
-// TITLE:   Definitions for the C28x I2C registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_I2C_H__
-#define __HW_I2C_H__
-
-//*****************************************************************************
-//
-// The following are defines for the I2C register offsets
-//
-//*****************************************************************************
-#define I2C_O_OAR                 0x0         // I2C Own address
-#define I2C_O_IER                 0x1         // I2C Interrupt Enable
-#define I2C_O_STR                 0x2         // I2C Status
-#define I2C_O_CLKL                0x3         // I2C Clock low-time divider
-#define I2C_O_CLKH                0x4         // I2C Clock high-time divider
-#define I2C_O_CNT                 0x5         // I2C Data count
-#define I2C_O_DRR                 0x6         // I2C Data receive
-#define I2C_O_SAR                 0x7         // I2C Slave address
-#define I2C_O_DXR                 0x8         // I2C Data Transmit
-#define I2C_O_MDR                 0x9         // I2C Mode
-#define I2C_O_ISRC                0xA         // I2C Interrupt Source
-#define I2C_O_EMDR                0xB         // I2C Extended Mode
-#define I2C_O_PSC                 0xC         // I2C Prescaler
-#define I2C_O_FFTX                0x20        // I2C FIFO Transmit
-#define I2C_O_FFRX                0x21        // I2C FIFO Receive
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2COAR register
-//
-//*****************************************************************************
-#define I2C_OAR_OAR_S             0
-#define I2C_OAR_OAR_M             0x3FF       // I2C Own address
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CIER register
-//
-//*****************************************************************************
-#define I2C_IER_ARBL              0x1         // Arbitration-lost interrupt
-                                              // enable
-#define I2C_IER_NACK              0x2         // No-acknowledgment interrupt
-                                              // enable
-#define I2C_IER_ARDY              0x4         // Register-access-ready interrupt
-                                              // enable
-#define I2C_IER_RRDY              0x8         // Receive-data-ready interrupt
-                                              // enable
-#define I2C_IER_XRDY              0x10        // Transmit-data-ready interrupt
-                                              // enable
-#define I2C_IER_SCD               0x20        // Stop condition detected
-                                              // interrupt enable
-#define I2C_IER_AAS               0x40        // Addressed as slave interrupt
-                                              // enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CSTR register
-//
-//*****************************************************************************
-#define I2C_STR_ARBL              0x1         // Arbitration-lost interrupt flag
-                                              // bit
-#define I2C_STR_NACK              0x2         // No-acknowledgment interrupt
-                                              // flag bit.
-#define I2C_STR_ARDY              0x4         // Register-access-ready interrupt
-                                              // flag bit
-#define I2C_STR_RRDY              0x8         // Receive-data-ready interrupt
-                                              // flag bit.
-#define I2C_STR_XRDY              0x10        // Transmit-data-ready interrupt
-                                              // flag bit.
-#define I2C_STR_SCD               0x20        // Stop condition detected bit.
-#define I2C_STR_AD0               0x100       // Address 0 bits
-#define I2C_STR_AAS               0x200       // Addressed-as-slave bit
-#define I2C_STR_XSMT              0x400       // Transmit shift register empty
-                                              // bit.
-#define I2C_STR_RSFULL            0x800       // Receive shift register full
-                                              // bit.
-#define I2C_STR_BB                0x1000      // Bus busy bit.
-#define I2C_STR_NACKSNT           0x2000      // NACK sent bit.
-#define I2C_STR_SDIR              0x4000      // Slave direction bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CCLKL register
-//
-//*****************************************************************************
-#define I2C_CLKL_I2CCLKL_S        0
-#define I2C_CLKL_I2CCLKL_M        0xFFFF      // Clock low-time divide-down
-                                              // value.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CCLKH register
-//
-//*****************************************************************************
-#define I2C_CLKH_I2CCLKH_S        0
-#define I2C_CLKH_I2CCLKH_M        0xFFFF      // Clock high-time divide-down
-                                              // value.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CCNT register
-//
-//*****************************************************************************
-#define I2C_CNT_I2CCNT_S          0
-#define I2C_CNT_I2CCNT_M          0xFFFF      // Data count value.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CDRR register
-//
-//*****************************************************************************
-#define I2C_DRR_DATA_S            0
-#define I2C_DRR_DATA_M            0xFF        // Receive data
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CSAR register
-//
-//*****************************************************************************
-#define I2C_SAR_SAR_S             0
-#define I2C_SAR_SAR_M             0x3FF       // Slave Address
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CDXR register
-//
-//*****************************************************************************
-#define I2C_DXR_DATA_S            0
-#define I2C_DXR_DATA_M            0xFF        // Transmit data
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CMDR register
-//
-//*****************************************************************************
-#define I2C_MDR_BC_S              0
-#define I2C_MDR_BC_M              0x7         // Bit count bits.
-#define I2C_MDR_FDF               0x8         // Free Data Format
-#define I2C_MDR_STB               0x10        // START Byte Mode
-#define I2C_MDR_IRS               0x20        // I2C Module Reset
-#define I2C_MDR_DLB               0x40        // Digital Loopback Mode
-#define I2C_MDR_RM                0x80        // Repeat Mode
-#define I2C_MDR_XA                0x100       // Expanded Address Mode
-#define I2C_MDR_TRX               0x200       // Transmitter Mode
-#define I2C_MDR_MST               0x400       // Master Mode
-#define I2C_MDR_STP               0x800       // STOP Condition
-#define I2C_MDR_STT               0x2000      // START condition bit
-#define I2C_MDR_FREE              0x4000      // Debug Action
-#define I2C_MDR_NACKMOD           0x8000      // NACK mode bit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CISRC register
-//
-//*****************************************************************************
-#define I2C_ISRC_INTCODE_S        0
-#define I2C_ISRC_INTCODE_M        0x7         // Interrupt code bits.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CEMDR register
-//
-//*****************************************************************************
-#define I2C_EMDR_BC               0x1         // Backwards compatibility mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CPSC register
-//
-//*****************************************************************************
-#define I2C_PSC_IPSC_S            0
-#define I2C_PSC_IPSC_M            0xFF        // I2C Prescaler Divide Down
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CFFTX register
-//
-//*****************************************************************************
-#define I2C_FFTX_TXFFIL_S         0
-#define I2C_FFTX_TXFFIL_M         0x1F        // Transmit FIFO Interrupt Level
-#define I2C_FFTX_TXFFIENA         0x20        // Transmit FIFO Interrupt Enable
-#define I2C_FFTX_TXFFINTCLR       0x40        // Transmit FIFO Interrupt Flag
-                                              // Clear
-#define I2C_FFTX_TXFFINT          0x80        // Transmit FIFO Interrupt Flag
-#define I2C_FFTX_TXFFST_S         8
-#define I2C_FFTX_TXFFST_M         0x1F00      // Transmit FIFO Status
-#define I2C_FFTX_TXFFRST          0x2000      // Transmit FIFO Reset
-#define I2C_FFTX_I2CFFEN          0x4000      // Transmit FIFO Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CFFRX register
-//
-//*****************************************************************************
-#define I2C_FFRX_RXFFIL_S         0
-#define I2C_FFRX_RXFFIL_M         0x1F        // Receive FIFO Interrupt Level
-#define I2C_FFRX_RXFFIENA         0x20        // Receive FIFO Interrupt Enable
-#define I2C_FFRX_RXFFINTCLR       0x40        // Receive FIFO Interrupt Flag
-                                              // Clear
-#define I2C_FFRX_RXFFINT          0x80        // Receive FIFO Interrupt Flag
-#define I2C_FFRX_RXFFST_S         8
-#define I2C_FFRX_RXFFST_M         0x1F00      // Receive FIFO Status
-#define I2C_FFRX_RXFFRST          0x2000      // Receive FIFO Reset
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ints.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ints.h
deleted file mode 100644
index 8f2ca7471f..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ints.h
+++ /dev/null
@@ -1,299 +0,0 @@
-//###########################################################################
-//
-// FILE:   hw_ints.h
-//
-// TITLE:  Definitions of interrupt numbers for use with interrupt.c.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_INTS_H__
-#define __HW_INTS_H__
-
-//*****************************************************************************
-//
-// PIE Interrupt Numbers
-//
-// 0x00FF = PIE Table Row #
-// 0xFF00 = PIE Table Column #
-// 0xFFFF0000 = PIE Vector ID
-//
-//*****************************************************************************
-
-// Lower PIE Group 1
-#define INT_ADCA_CH1            0x200101        //ADC-A Interrupt 1
-#define INT_ADCB_CH1            0x210102        //ADC-B Interrupt 1
-#define INT_ADCC_CH1            0x220103        //ADC-C Interrupt 1
-#define INT_XINT1               0x230104        //External Interrupt 1
-#define INT_XINT2               0x240105        //External Interrupt 2
-#define INT_ADCD_CH1            0x250106        //ADC-D Interrupt 1
-#define INT_TINT0               0x260107        //Timer Interrupt 0
-#define INT_WAKEINT             0x270108        //Wakeup Interrupt
-
-// Lower PIE Group 2
-#define INT_PWM1TZ              0x280201        //PWM TZ Interrupt 1
-#define INT_PWM2TZ              0x290202        //PWM TZ Interrupt 2
-#define INT_PWM3TZ              0x2A0203        //PWM TZ Interrupt 3
-#define INT_PWM4TZ              0x2B0204        //PWM TZ Interrupt 4
-#define INT_PWM5TZ              0x2C0205        //PWM TZ Interrupt 5
-#define INT_PWM6TZ              0x2D0206        //PWM TZ Interrupt 6
-#define INT_PWM7TZ              0x2E0207        //PWM TZ Interrupt 7
-#define INT_PWM8TZ              0x2F0208        //PWM TZ Interrupt 8
-
-// Lower PIE Group 3
-#define INT_PWM1INT             0x300301        //PWM Interrupt 1
-#define INT_PWM2INT             0x310302        //PWM Interrupt 2
-#define INT_PWM3INT             0x320303        //PWM Interrupt 3
-#define INT_PWM4INT             0x330304        //PWM Interrupt 4
-#define INT_PWM5INT             0x340305        //PWM Interrupt 5
-#define INT_PWM6INT             0x350306        //PWM Interrupt 6
-#define INT_PWM7INT             0x360307        //PWM Interrupt 7
-#define INT_PWM8INT             0x370308        //PWM Interrupt 8
-
-// Lower PIE Group 4
-#define INT_CAP1INT             0x380401        //Capture Interrupt 1
-#define INT_CAP2INT             0x390402        //Capture Interrupt 2
-#define INT_CAP3INT             0x3A0403        //Capture Interrupt 3
-#define INT_CAP4INT             0x3B0404        //Capture Interrupt 4
-#define INT_CAP5INT             0x3C0405        //Capture Interrupt 5
-#define INT_CAP6INT             0x3D0406        //Capture Interrupt 6
-#define INT_CAP7INT             0x3E0407        //Capture Interrupt 7
-#define INT_CAP8INT             0x3F0408        //Capture Interrupt 8
-
-// Lower PIE Group 5
-#define INT_EQEP1INT            0x400501        //Quadrature Interrupt 1
-#define INT_EQEP2INT            0x410502        //Quadrature Interrupt 2
-#define INT_EQEP3INT            0x420503        //Quadrature Interrupt 3
-#define INT_EQEP4INT            0x430504        //Quadrature Interrupt 4
-#define INT_CLB1INT             0x440505        //CLB Interrupt 1
-#define INT_CLB2INT             0x450506        //CLB Interrupt 2
-#define INT_CLB3INT             0x460507        //CLB Interrupt 3
-#define INT_CLB4INT             0x470508        //CLB Interrupt 4
-
-// Lower PIE Group 6
-#define INT_SPIRXINTA           0x480601        //SPI-A Receive Interrupt
-#define INT_SPITXINTA           0x490602        //SPI-A Transmit Interrupt
-#define INT_SPIRXINTB           0x4A0603        //SPI-B Receive Interrupt
-#define INT_SPITXINTB           0x4B0604        //SPI-B Transmit Interrupt
-#define INT_MRINTA              0x4C0605        //McBSP-A Receive Interrupt
-#define INT_MXINTA              0x4D0606        //McBSP-A Transmit Interrupt
-#define INT_MRINTB              0x4E0607        //McBSP-B Receive Interrupt
-#define INT_MXINTB              0x4F0608        //McBSP-B Transmit Interrupt
-
-// Lower PIE Group 7
-#define INT_DMA1INT             0x500701        //DMA Channel 1 Interrupt
-#define INT_DMA2INT             0x510702        //DMA Channel 2 Interrupt
-#define INT_DMA3INT             0x520703        //DMA Channel 3 Interrupt
-#define INT_DMA4INT             0x530704        //DMA Channel 4 Interrupt
-#define INT_DMA5INT             0x540705        //DMA Channel 5 Interrupt
-#define INT_DMA6INT             0x550706        //DMA Channel 6 Interrupt
-
-// Lower PIE Group 8
-#define INT_I2CINT1A            0x580801        //I2C-A Basic Interrupts
-#define INT_I2CINT2A            0x590802        //I2C-A FIFO Interrupts
-#define INT_I2CINT1B            0x5A0803        //I2C-B Basic Interrupts
-#define INT_I2CINT2B            0x5B0804        //I2C-B FIFO Interrupts
-#define INT_SCICRX              0x5C0805        //SCI-C Receive Interrupt
-#define INT_SCICTX              0x5D0806        //SCI-C Transmit Interrupt
-#define INT_SCIDRX              0x5E0807        //SCI-D Receive Interrupt
-#define INT_SCIDTX              0x5F0808        //SCI-D Transmit Interrupt
-
-// Lower PIE Group 9
-#define INT_SCIRXINTA           0x600901        //SCI-A RX Interrupt
-#define INT_SCITXINTA           0x610902        //SCI-A TX Interrupt
-#define INT_SCIRXINTB           0x620903        //SCI-B RX Interrupt
-#define INT_SCITXINTB           0x630904        //SCI-B TX Interrupt
-#define INT_CANA_0              0x640905        //CANA 0 Interrupt
-#define INT_CANA_1              0x650906        //CANA 1 Interrupt
-#define INT_CANB_0              0x660907        //CANB 0 Interrupt
-#define INT_CANB_1              0x670908        //CANB 1 Interrupt
-
-// Lower PIE Group 10
-#define INT_ADCA_EVT            0x680A01        //ADCA_EVT Interrupt
-#define INT_ADCA_CH2            0x690A02        //ADCA_CH2 Interrupt 2
-#define INT_ADCA_CH3            0x6A0A03        //ADCA_CH3 Interrupt 3
-#define INT_ADCA_CH4            0x6B0A04        //ADCA_CH4 Interrupt 4
-#define INT_ADCB_EVT            0x6C0A05        //ADCB_EVT Interrupt
-#define INT_ADCB_CH2            0x6D0A06        //ADCB_CH2 Interrupt 2
-#define INT_ADCB_CH3            0x6E0A07        //ADCB_CH3 Interrupt 3
-#define INT_ADCB_CH4            0x6F0A08        //ADCB_CH4 Interrupt 4
-
-// Lower PIE Group 11
-#define INT_CLA1INT1            0x700B01        //CLA_1 Interrupt 1
-#define INT_CLA1INT2            0x710B02        //CLA_1 Interrupt 2
-#define INT_CLA1INT3            0x720B03        //CLA_1 Interrupt 3
-#define INT_CLA1INT4            0x730B04        //CLA_1 Interrupt 4
-#define INT_CLA1INT5            0x740B05        //CLA_1 Interrupt 5
-#define INT_CLA1INT6            0x750B06        //CLA_1 Interrupt 6
-#define INT_CLA1INT7            0x760B07        //CLA_1 Interrupt 7
-#define INT_CLA1INT8            0x770B08        //CLA_1 Interrupt 8
-
-// Lower PIE Group 12
-#define INT_XINT3               0x780C01        //External Interrupt 3
-#define INT_XINT4               0x790C02        //External Interrupt 4
-#define INT_XINT5               0x7A0C03        //External Interrupt 5
-#define INT_FMC                 0x7C0C05        //FMC Interrupt
-#define INT_VCU                 0x7D0C06        //VCU Interrupt
-#define INT_LVF                 0x7E0C07        //Latched Overflow
-#define INT_LUF                 0x7F0C08        //Latched Underflow
-
-// Upper PIE Group 1
-#define INT_IPC0INT             0x84010D        //IPC Interrupt 1
-#define INT_IPC1INT             0x85010E        //IPC Interrupt 2
-#define INT_IPC2INT             0x86010F        //IPC Interrupt 3
-#define INT_IPC3INT             0x870110        //IPC Interrupt 4
-
-// Upper PIE Group 2
-#define INT_PWM9TZ              0x880209        //PWM TZ Interrupt 9
-#define INT_PWM10TZ             0x89020A        //PWM TZ Interrupt 10
-#define INT_PWM11TZ             0x8A020B        //PWM TZ Interrupt 11
-#define INT_PWM12TZ             0x8B020C        //PWM TZ Interrupt 12
-
-// Upper PIE Group 3
-#define INT_PWM9INT             0x900309        //PWM Interrupt 9
-#define INT_PWM10INT            0x91030A        //PWN Interrupt 10
-#define INT_PWM11INT            0x92030B        //PWM Interrupt 11
-#define INT_PWM12INT            0x93030C        //PWM Interrupt 12
-
-// Upper PIE Group 4
-#define INT_HRCAP1INT           0x980409        //High-Res Capture Interrupt 1
-#define INT_HRCAP2INT           0x99040A        //High-Res Capture Interrupt 2
-#define INT_HRCAP3INT           0x9A040B        //High-Res Capture Interrupt 3
-#define INT_HRCAP4INT           0x9B040C        //High-Res Capture Interrupt 4
-#define INT_HRCAP5INT           0x9C040D        //High-Res Capture Interrupt 1
-#define INT_HRCAP6INT           0x9D040E        //High-Res Capture Interrupt 2
-#define INT_HRCAP7INT           0x9E040F        //High-Res Capture Interrupt 3
-#define INT_HRCAP8INT           0x9F0410        //High-Res Capture Interrupt 4
-
-// Upper PIE Group 5
-#define INT_SDFM1INT            0xA00509        //SDFM Interrupt 1
-#define INT_SDFM2INT            0xA1050A        //SDFM Interrupt 2
-#define INT_SDFM3INT            0xA2050B        //SDFM Interrupt 3
-#define INT_SDFM4INT            0xA3050C        //SDFM Interrupt 4
-#define INT_SDFM5INT            0xA4050D        //SDFM Interrupt 5
-#define INT_SDFM6INT            0xA5050E        //SDFM Interrupt 6
-#define INT_SDFM7INT            0xA6050F        //SDFM Interrupt 7
-#define INT_SDFM8INT            0xA70510        //SDFM Interrupt 8
-
-// Upper PIE Group 6
-#define INT_SPIRXINTC           0xA80609        //SPI-A Receive Interrupt
-#define INT_SPITXINTC           0xA9060A        //SPI-A Transmit Interrupt
-#define INT_SPIRXINTD           0xAA060B        //SPI-B Receive Interrupt
-#define INT_SPITXINTD           0xAB060C        //SPI-B Transmit Interrupt
-
-// Upper PIE Group 8
-#define INT_UPPAINT             0xBE080F        //UPP-A Interrupt
-#define INT_UPPBINT             0xBF0810        //UPP-B Interrupt
-
-// Upper PIE Group 9
-#define INT_CANCINT1            0xC00909        //CANC 1 Interrupt
-#define INT_CANCINT2            0xC1090A        //CANC 2 Interrupt
-#define INT_CANDINT1            0xC2090B        //CAND 1 Interrupt
-#define INT_CANDINT2            0xC3090C        //CAND 2 Interrupt
-#define INT_USBAINT             0xC6090F        //USBA Interrupt
-#define INT_USBBINT             0xC70910        //USBB Interrupt
-
-// Upper PIE Group 10
-#define INT_ADCC_EVT            0xC80A09        //ADCC_EVT Interrupt
-#define INT_ADCC_CH2            0xC90A0A        //ADCC_CH2 Interrupt 2
-#define INT_ADCC_CH3            0xCA0A0B        //ADCC_CH3 Interrupt 3
-#define INT_ADCC_CH4            0xCB0A0C        //ADCC_CH4 Interrupt 4
-#define INT_ADCD_EVT            0xCC0A0D        //ADCD_EVT Interrupt
-#define INT_ADCD_CH2            0xCD0A0E        //ADCD_CH2 Interrupt 2
-#define INT_ADCD_CH3            0xCE0A0F        //ADCD_CH3 Interrupt 3
-#define INT_ADCD_CH4            0xCF0A10        //ADCD_CH4 Interrupt 4
-
-// Upper PIE Group 11
-#define INT_CLA2INT1            0xD00B09        //CLA_2 Interrupt 1
-#define INT_CLA2INT2            0xD10B0A        //CLA_2 Interrupt 2
-#define INT_CLA2INT3            0xD20B0B        //CLA_2 Interrupt 3
-#define INT_CLA2INT4            0xD30B0C        //CLA_2 Interrupt 4
-#define INT_CLA2INT5            0xD40B0D        //CLA_2 Interrupt 1
-#define INT_CLA2INT6            0xD50B0E        //CLA_2 Interrupt 2
-#define INT_CLA2INT7            0xD60B0F        //CLA_2 Interrupt 3
-#define INT_CLA2INT8            0xD70B10        //CLA_2 Interrupt 4
-
-// Upper PIE Group 12
-#define INT_EMIF_ERR            0xD80C09        //EMIF Error Interrupt
-#define INT_RAM_CORR_ERR        0xD90C0A        //RAM Correctable Error Interrupt
-#define INT_FLASH_CORR_ERR      0xDA0C0B        //Flash correctable Error Interrupt
-#define INT_RAM_ACC_VIO         0xDB0C0C        //RAM Access Violation Interrupt
-#define INT_SYS_PLL_SLIP        0xDC0C0D        //System PLL Slip Interrupt
-#define INT_AUX_PLL_SLIP        0xDD0C0E        //Auxillary PLL Slip Interrupt
-#define INT_CLA_OF              0xDE0C0F        //CLA Overflow Interrupt
-#define INT_CLA_UF              0xDF0C10        //CLA Underflow Interrupt
-
-//Workaround for  Stellaris code
-#define INT_USB0                INT_USBAINT     // USB 0 Controller
-
-//Workaround for other interrupts
-#define INT_RESET               0x000000        //Reset Interrupt
-#define INT_INT1                0x010000        //Not Used
-#define INT_INT2                0x020000        //Not Used
-#define INT_INT3                0x030000        //Not Used
-#define INT_INT4                0x040000        //Not Used
-#define INT_INT5                0x050000        //Not Used
-#define INT_INT6                0x060000        //Not Used
-#define INT_INT7                0x070000        //Not Used
-#define INT_INT8                0x080000        //Not Used
-#define INT_INT9                0x090000        //Not Used
-#define INT_INT10               0x0A0000        //Not Used
-#define INT_INT11               0x0B0000        //Not Used
-#define INT_INT12               0x0C0000        //Not Used
-#define INT_TINT1               0x0D0D00        //Timer Interrupt 1
-#define INT_TINT2               0x0E0E00        //Timer Interrupt 2
-#define INT_DATALOG             0x0F0F00        //CPU Data Logging Interrupt
-#define INT_RTOSINT             0x101000        //CPU Real Time OS Interrupt
-#define INT_EMUINT              0x110000        //CPU Emulation Interrupt
-#define INT_NMI                 0x120000        //External Non-Maskable Interrupt
-#define INT_ILLEGAL             0x130000        //Illegal Operation
-#define INT_USER1               0x140000        //User-defined
-#define INT_USER2               0x150000        //User-defined
-#define INT_USER3               0x160000        //User-defined
-#define INT_USER4               0x170000        //User-defined
-#define INT_USER5               0x180000        //User-defined
-#define INT_USER6               0x190000        //User-defined
-#define INT_USER7               0x1A0000        //User-defined
-#define INT_USER8               0x1B0000        //User-defined
-#define INT_USER9               0x1C0000        //User-defined
-#define INT_USER10              0x1D0000        //User-defined
-#define INT_USER11              0x1E0000        //User-defined
-#define INT_USER12              0x1F0000        //User-defined
-
-
-#endif // __HW_INTS_H__
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_memmap.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_memmap.h
deleted file mode 100644
index 94c774807a..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_memmap.h
+++ /dev/null
@@ -1,96 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_memmap.h
-//
-// TITLE:   Macros defining the memory map of the C28x.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_MEMMAP_H__
-#define __HW_MEMMAP_H__
-
-//*****************************************************************************
-//
-// The following are defines for the base address of the memories and
-// peripherals.
-//
-//*****************************************************************************
-
-#define USB0_BASE               0x00040000  // USB 0 Controller
-
-#define ADCA_RESULT_BASE        0x00000B00   // ADC-A Result
-#define ADCB_RESULT_BASE        0x00000B20   // ADC-B Result
-#define ADCC_RESULT_BASE        0x00000B40   // ADC-C Result
-#define ADCD_RESULT_BASE        0x00000B60   // ADC-D Result
-
-#define ADCA_BASE               0x00007400   // ADC-A
-#define ADCB_BASE               0x00007480   // ADC-B
-#define ADCC_BASE               0x00007500   // ADC-C
-#define ADCD_BASE               0x00007580   // ADC-D
-
-#define CMPSS1_BASE             0x00005C80   // CMPSS-1
-#define CMPSS2_BASE             0x00005CA0   // CMPSS-2
-#define CMPSS3_BASE             0x00005CC0   // CMPSS-3
-#define CMPSS4_BASE             0x00005CE0   // CMPSS-4
-#define CMPSS5_BASE             0x00005D00   // CMPSS-5
-#define CMPSS6_BASE             0x00005D20   // CMPSS-6
-#define CMPSS7_BASE             0x00005D40   // CMPSS-7
-#define CMPSS8_BASE             0x00005D60   // CMPSS-8
-
-#define I2CA_BASE               0x00007300   // I2C-A
-#define I2CB_BASE               0x00007340   // I2C-B
-
-#define UARTA_BASE              0x00007200   // SCI-A
-#define UARTB_BASE              0x00007210   // SCI-B
-#define UARTC_BASE              0x00007220   // SCI-C
-#define UARTD_BASE              0x00007230   // SCI-D
-
-#define EQEP1_BASE              0x00005100   // Enhanced EQEP-1
-#define EQEP2_BASE              0x00005140   // Enhanced EQEP-2
-#define EQEP3_BASE              0x00005180   // Enhanced EQEP-3
-
-#define SPIA_BASE               0x00006100   // SPI-A
-#define SPIB_BASE               0x00006110   // SPI-B
-#define SPIC_BASE               0x00006120   // SPI-C
-
-#define CANA_BASE               0x00048000   // CAN-A
-#define CANB_BASE               0x0004A000   // CAN-B
-#define CANA_MSG_RAM            0x00049000
-#define CANB_MSG_RAM            0x0004B000
-
-#endif // __HW_MEMMAP_H__
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_types.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_types.h
deleted file mode 100644
index 59edb8ce16..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_types.h
+++ /dev/null
@@ -1,88 +0,0 @@
-//###########################################################################
-//
-// FILE:   hw_types.h
-//
-// TITLE:  Type definitions used in ALL driverlib functions.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_TYPES_H__
-#define __HW_TYPES_H__
-
-//*****************************************************************************
-//
-// Define fake 8 bit types for USB related code.
-//
-//*****************************************************************************
-
-typedef uint16_t uint8_t;
-typedef int16_t int8_t;
-	 
-//*****************************************************************************
-//
-// Macros for hardware access, both direct and via the bit-band region.
-//
-//*****************************************************************************
-#define HWREG(x)                                                              \
-        (*((volatile uint32_t *)(x)))
-#define HWREGH(x)                                                             \
-        (*((volatile uint16_t *)(x)))
-#define HWREGB(x)                                                            \
-        __byte((int *)(x),0)
-//Emulated Bitbanded write        
-#define HWREGBITW(address, mask, value)                                       \
-        (*(volatile uint32_t *)(address)) =                              \
-       ((*(volatile uint32_t *)(address)) & ~((uint32_t)1 << mask)) \
-       | ((uint32_t)value << mask)
-//Emulated Bitbanded read      
-#define HWREGBITR(address, mask)                                              \
-        (((*(volatile uint32_t *)(address)) & ((uint32_t)1 << mask)) >> mask)
-
-//Emulated Bitbanded write
-#define HWREGBITHW(address, mask, value)                                       \
-        (*(volatile uint16_t *)(address)) =                              \
-       ((*(volatile uint16_t *)(address)) & ~((uint16_t)1 << mask)) \
-       | ((uint16_t)value << mask)
-//Emulated Bitbanded read
-#define HWREGBITHR(address, mask)                                              \
-        (((*(volatile uint16_t *)(address)) & ((uint16_t)1 << mask)) >> mask)
-
-
-
-#endif // __HW_TYPES_H__
-
-
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_uart.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_uart.h
deleted file mode 100644
index c788095feb..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_uart.h
+++ /dev/null
@@ -1,208 +0,0 @@
-//###########################################################################
-//
-// FILE:    hw_uart.h
-//
-// TITLE:   Definitions for the C28x SCI registers.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __HW_UART_H__
-#define __HW_UART_H__
-
-//*****************************************************************************
-//
-// The following are defines for the SCI register offsets
-//
-//*****************************************************************************
-#define UART_O_CCR                 0x0        // Communications control register
-#define UART_O_CTL1                0x1        // Control register 1
-#define UART_O_HBAUD               0x2        // Baud rate (high) register
-#define UART_O_LBAUD               0x3        // Baud rate (low) register
-#define UART_O_CTL2                0x4        // Control register 2
-#define UART_O_RXST                0x5        // Receive status register
-#define UART_O_RXEMU               0x6        // Receive emulation buffer
-                                              // register
-#define UART_O_RXBUF               0x7        // Receive data buffer
-#define UART_O_TXBUF               0x9        // Transmit data buffer
-#define UART_O_FFTX                0xA        // FIFO transmit register
-#define UART_O_FFRX                0xB        // FIFO receive register
-#define UART_O_FFCT                0xC        // FIFO control register
-#define UART_O_PRI                 0xF        // FIFO Priority control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCICCR register
-//
-//*****************************************************************************
-#define UART_CCR_SCICHAR_S         0
-#define UART_CCR_SCICHAR_M         0x7        // Character length control
-#define UART_CCR_ADDRIDLE_MODE     0x8        // ADDR/IDLE Mode control
-#define UART_CCR_LOOPBKENA         0x10       // Loop Back enable
-#define UART_CCR_PARITYENA         0x20       // Parity enable
-#define UART_CCR_PARITY            0x40       // Even or Odd Parity
-#define UART_CCR_STOPBITS          0x80       // Number of Stop Bits
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCICTL1 register
-//
-//*****************************************************************************
-#define UART_CTL1_RXENA            0x1        // SCI receiver enable
-#define UART_CTL1_TXENA            0x2        // SCI transmitter enable
-#define UART_CTL1_SLEEP            0x4        // SCI sleep
-#define UART_CTL1_TXWAKE           0x8        // Transmitter wakeup method
-#define UART_CTL1_SWRESET          0x20       // Software reset
-#define UART_CTL1_RXERRINTENA      0x40       // Receive __interrupt enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCIHBAUD register
-//
-//*****************************************************************************
-#define UART_HBAUD_BAUD_S          0
-#define UART_HBAUD_BAUD_M          0xFFFF     // SCI 16-bit baud selection
-                                              // Registers SCIHBAUD
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCILBAUD register
-//
-//*****************************************************************************
-#define UART_LBAUD_BAUD_S          0
-#define UART_LBAUD_BAUD_M          0xFFFF     // SCI 16-bit baud selection
-                                              // Registers SCILBAUD
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCICTL2 register
-//
-//*****************************************************************************
-#define UART_CTL2_TXINTENA         0x1        // Transmit __interrupt enable
-#define UART_CTL2_RXBKINTENA       0x2        // Receiver-buffer break enable
-#define UART_CTL2_TXEMPTY          0x40       // Transmitter empty flag
-#define UART_CTL2_TXRDY            0x80       // Transmitter ready flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCIRXST register
-//
-//*****************************************************************************
-#define UART_RXST_RXWAKE           0x2        // Receiver wakeup detect flag
-#define UART_RXST_PE               0x4        // Parity error flag
-#define UART_RXST_OE               0x8        // Overrun error flag
-#define UART_RXST_FE               0x10       // Framing error flag
-#define UART_RXST_BRKDT            0x20       // Break-detect flag
-#define UART_RXST_RXRDY            0x40       // Receiver ready flag
-#define UART_RXST_RXERROR          0x80       // Receiver error flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCIRXEMU register
-//
-//*****************************************************************************
-#define UART_RXEMU_ERXDT_S         0
-#define UART_RXEMU_ERXDT_M         0xFF       // Receive emulation buffer data
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCIRXBUF register
-//
-//*****************************************************************************
-#define UART_RXBUF_SAR_S           0
-#define UART_RXBUF_SAR_M           0xFF       // Receive Character bits
-#define UART_RXBUF_SCIFFPE         0x4000     // Receiver error flag
-#define UART_RXBUF_SCIFFFE         0x8000     // Receiver error flag
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCITXBUF register
-//
-//*****************************************************************************
-#define UART_TXBUF_TXDT_S          0
-#define UART_TXBUF_TXDT_M          0xFF       // Transmit data buffer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCIFFTX register
-//
-//*****************************************************************************
-#define UART_FFTX_TXFFIL_S         0
-#define UART_FFTX_TXFFIL_M         0x1F       // Interrupt level
-#define UART_FFTX_TXFFIENA         0x20       // Interrupt enable
-#define UART_FFTX_TXFFINTCLR       0x40       // Clear INT flag
-#define UART_FFTX_TXFFINT          0x80       // INT flag
-#define UART_FFTX_TXFFST_S         8
-#define UART_FFTX_TXFFST_M         0x1F00     // FIFO status
-#define UART_FFTX_TXFIFORESET     0x2000     // FIFO reset
-#define UART_FFTX_SCIFFENA         0x4000     // Enhancement enable
-#define UART_FFTX_SCIRST           0x8000     // SCI reset rx/tx channels
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCIFFRX register
-//
-//*****************************************************************************
-#define UART_FFRX_RXFFIL_S         0
-#define UART_FFRX_RXFFIL_M         0x1F       // Interrupt level
-#define UART_FFRX_RXFFIENA         0x20       // Interrupt enable
-#define UART_FFRX_RXFFINTCLR       0x40       // Clear INT flag
-#define UART_FFRX_RXFFINT          0x80       // INT flag
-#define UART_FFRX_RXFFST_S         8
-#define UART_FFRX_RXFFST_M         0x1F00     // FIFO status
-#define UART_FFRX_RXFIFORESET      0x2000     // FIFO reset
-#define UART_FFRX_RXFFOVRCLR       0x4000     // Clear overflow
-#define UART_FFRX_RXFFOVF          0x8000     // FIFO overflow
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCIFFCT register
-//
-//*****************************************************************************
-#define UART_FFCT_FFTXDLY_S        0
-#define UART_FFCT_FFTXDLY_M        0xFF       // FIFO transmit delay
-#define UART_FFCT_CDC              0x2000     // Auto baud mode enable
-#define UART_FFCT_ABDCLR           0x4000     // Auto baud clear
-#define UART_FFCT_ABD              0x8000     // Auto baud detect
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SCIPRI register
-//
-//*****************************************************************************
-#define UART_PRI_FREESOFT_S        3
-#define UART_PRI_FREESOFT_M        0x18       // Emulation modes
-#endif
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_usb.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_usb.h
deleted file mode 100644
index 9602cb7a15..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_usb.h
+++ /dev/null
@@ -1,4611 +0,0 @@
-//*****************************************************************************
-//
-// hw_usb.h - Macros for use in accessing the USB registers.
-//
-// Copyright (c) 2007-2012 Texas Instruments Incorporated.  All rights reserved.
-// Software License Agreement
-// 
-//   Redistribution and use in source and binary forms, with or without
-//   modification, are permitted provided that the following conditions
-//   are met:
-// 
-//   Redistributions of source code must retain the above copyright
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the
-//   documentation and/or other materials provided with the  
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// 
-// This is part of revision 9453 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_USB_H__
-#define __HW_USB_H__
-
-//*****************************************************************************
-//
-// The following are defines for the Univeral Serial Bus register offsets.
-//
-//*****************************************************************************
-#define USB_O_FADDR             0x00000000  // USB Device Functional Address
-#define USB_O_POWER             0x00000001  // USB Power
-#define USB_O_TXIS              0x00000002  // USB Transmit Interrupt Status
-#define USB_O_RXIS              0x00000004  // USB Receive Interrupt Status
-#define USB_O_TXIE              0x00000006  // USB Transmit Interrupt Enable
-#define USB_O_RXIE              0x00000008  // USB Receive Interrupt Enable
-#define USB_O_IS                0x0000000A  // USB General Interrupt Status
-#define USB_O_IE                0x0000000B  // USB Interrupt Enable
-#define USB_O_FRAME             0x0000000C  // USB Frame Value
-#define USB_O_EPIDX             0x0000000E  // USB Endpoint Index
-#define USB_O_TEST              0x0000000F  // USB Test Mode
-#define USB_O_FIFO0             0x00000020  // USB FIFO Endpoint 0
-#define USB_O_FIFO1             0x00000024  // USB FIFO Endpoint 1
-#define USB_O_FIFO2             0x00000028  // USB FIFO Endpoint 2
-#define USB_O_FIFO3             0x0000002C  // USB FIFO Endpoint 3
-#define USB_O_FIFO4             0x00000030  // USB FIFO Endpoint 4
-#define USB_O_FIFO5             0x00000034  // USB FIFO Endpoint 5
-#define USB_O_FIFO6             0x00000038  // USB FIFO Endpoint 6
-#define USB_O_FIFO7             0x0000003C  // USB FIFO Endpoint 7
-#define USB_O_FIFO8             0x00000040  // USB FIFO Endpoint 8
-#define USB_O_FIFO9             0x00000044  // USB FIFO Endpoint 9
-#define USB_O_FIFO10            0x00000048  // USB FIFO Endpoint 10
-#define USB_O_FIFO11            0x0000004C  // USB FIFO Endpoint 11
-#define USB_O_FIFO12            0x00000050  // USB FIFO Endpoint 12
-#define USB_O_FIFO13            0x00000054  // USB FIFO Endpoint 13
-#define USB_O_FIFO14            0x00000058  // USB FIFO Endpoint 14
-#define USB_O_FIFO15            0x0000005C  // USB FIFO Endpoint 15
-#define USB_O_DEVCTL            0x00000060  // USB Device Control
-#define USB_O_TXFIFOSZ          0x00000062  // USB Transmit Dynamic FIFO Sizing
-#define USB_O_RXFIFOSZ          0x00000063  // USB Receive Dynamic FIFO Sizing
-#define USB_O_TXFIFOADD         0x00000064  // USB Transmit FIFO Start Address
-#define USB_O_RXFIFOADD         0x00000066  // USB Receive FIFO Start Address
-#define USB_O_CONTIM            0x0000007A  // USB Connect Timing
-#define USB_O_VPLEN             0x0000007B  // USB OTG VBUS Pulse Timing
-#define USB_O_FSEOF             0x0000007D  // USB Full-Speed Last Transaction
-                                            // to End of Frame Timing
-#define USB_O_LSEOF             0x0000007E  // USB Low-Speed Last Transaction
-                                            // to End of Frame Timing
-#define USB_O_TXFUNCADDR0       0x00000080  // USB Transmit Functional Address
-                                            // Endpoint 0
-#define USB_O_TXHUBADDR0        0x00000082  // USB Transmit Hub Address
-                                            // Endpoint 0
-#define USB_O_TXHUBPORT0        0x00000083  // USB Transmit Hub Port Endpoint 0
-#define USB_O_TXFUNCADDR1       0x00000088  // USB Transmit Functional Address
-                                            // Endpoint 1
-#define USB_O_TXHUBADDR1        0x0000008A  // USB Transmit Hub Address
-                                            // Endpoint 1
-#define USB_O_TXHUBPORT1        0x0000008B  // USB Transmit Hub Port Endpoint 1
-#define USB_O_RXFUNCADDR1       0x0000008C  // USB Receive Functional Address
-                                            // Endpoint 1
-#define USB_O_RXHUBADDR1        0x0000008E  // USB Receive Hub Address Endpoint
-                                            // 1
-#define USB_O_RXHUBPORT1        0x0000008F  // USB Receive Hub Port Endpoint 1
-#define USB_O_TXFUNCADDR2       0x00000090  // USB Transmit Functional Address
-                                            // Endpoint 2
-#define USB_O_TXHUBADDR2        0x00000092  // USB Transmit Hub Address
-                                            // Endpoint 2
-#define USB_O_TXHUBPORT2        0x00000093  // USB Transmit Hub Port Endpoint 2
-#define USB_O_RXFUNCADDR2       0x00000094  // USB Receive Functional Address
-                                            // Endpoint 2
-#define USB_O_RXHUBADDR2        0x00000096  // USB Receive Hub Address Endpoint
-                                            // 2
-#define USB_O_RXHUBPORT2        0x00000097  // USB Receive Hub Port Endpoint 2
-#define USB_O_TXFUNCADDR3       0x00000098  // USB Transmit Functional Address
-                                            // Endpoint 3
-#define USB_O_TXHUBADDR3        0x0000009A  // USB Transmit Hub Address
-                                            // Endpoint 3
-#define USB_O_TXHUBPORT3        0x0000009B  // USB Transmit Hub Port Endpoint 3
-#define USB_O_RXFUNCADDR3       0x0000009C  // USB Receive Functional Address
-                                            // Endpoint 3
-#define USB_O_RXHUBADDR3        0x0000009E  // USB Receive Hub Address Endpoint
-                                            // 3
-#define USB_O_RXHUBPORT3        0x0000009F  // USB Receive Hub Port Endpoint 3
-#define USB_O_TXFUNCADDR4       0x000000A0  // USB Transmit Functional Address
-                                            // Endpoint 4
-#define USB_O_TXHUBADDR4        0x000000A2  // USB Transmit Hub Address
-                                            // Endpoint 4
-#define USB_O_TXHUBPORT4        0x000000A3  // USB Transmit Hub Port Endpoint 4
-#define USB_O_RXFUNCADDR4       0x000000A4  // USB Receive Functional Address
-                                            // Endpoint 4
-#define USB_O_RXHUBADDR4        0x000000A6  // USB Receive Hub Address Endpoint
-                                            // 4
-#define USB_O_RXHUBPORT4        0x000000A7  // USB Receive Hub Port Endpoint 4
-#define USB_O_TXFUNCADDR5       0x000000A8  // USB Transmit Functional Address
-                                            // Endpoint 5
-#define USB_O_TXHUBADDR5        0x000000AA  // USB Transmit Hub Address
-                                            // Endpoint 5
-#define USB_O_TXHUBPORT5        0x000000AB  // USB Transmit Hub Port Endpoint 5
-#define USB_O_RXFUNCADDR5       0x000000AC  // USB Receive Functional Address
-                                            // Endpoint 5
-#define USB_O_RXHUBADDR5        0x000000AE  // USB Receive Hub Address Endpoint
-                                            // 5
-#define USB_O_RXHUBPORT5        0x000000AF  // USB Receive Hub Port Endpoint 5
-#define USB_O_TXFUNCADDR6       0x000000B0  // USB Transmit Functional Address
-                                            // Endpoint 6
-#define USB_O_TXHUBADDR6        0x000000B2  // USB Transmit Hub Address
-                                            // Endpoint 6
-#define USB_O_TXHUBPORT6        0x000000B3  // USB Transmit Hub Port Endpoint 6
-#define USB_O_RXFUNCADDR6       0x000000B4  // USB Receive Functional Address
-                                            // Endpoint 6
-#define USB_O_RXHUBADDR6        0x000000B6  // USB Receive Hub Address Endpoint
-                                            // 6
-#define USB_O_RXHUBPORT6        0x000000B7  // USB Receive Hub Port Endpoint 6
-#define USB_O_TXFUNCADDR7       0x000000B8  // USB Transmit Functional Address
-                                            // Endpoint 7
-#define USB_O_TXHUBADDR7        0x000000BA  // USB Transmit Hub Address
-                                            // Endpoint 7
-#define USB_O_TXHUBPORT7        0x000000BB  // USB Transmit Hub Port Endpoint 7
-#define USB_O_RXFUNCADDR7       0x000000BC  // USB Receive Functional Address
-                                            // Endpoint 7
-#define USB_O_RXHUBADDR7        0x000000BE  // USB Receive Hub Address Endpoint
-                                            // 7
-#define USB_O_RXHUBPORT7        0x000000BF  // USB Receive Hub Port Endpoint 7
-#define USB_O_TXFUNCADDR8       0x000000C0  // USB Transmit Functional Address
-                                            // Endpoint 8
-#define USB_O_TXHUBADDR8        0x000000C2  // USB Transmit Hub Address
-                                            // Endpoint 8
-#define USB_O_TXHUBPORT8        0x000000C3  // USB Transmit Hub Port Endpoint 8
-#define USB_O_RXFUNCADDR8       0x000000C4  // USB Receive Functional Address
-                                            // Endpoint 8
-#define USB_O_RXHUBADDR8        0x000000C6  // USB Receive Hub Address Endpoint
-                                            // 8
-#define USB_O_RXHUBPORT8        0x000000C7  // USB Receive Hub Port Endpoint 8
-#define USB_O_TXFUNCADDR9       0x000000C8  // USB Transmit Functional Address
-                                            // Endpoint 9
-#define USB_O_TXHUBADDR9        0x000000CA  // USB Transmit Hub Address
-                                            // Endpoint 9
-#define USB_O_TXHUBPORT9        0x000000CB  // USB Transmit Hub Port Endpoint 9
-#define USB_O_RXFUNCADDR9       0x000000CC  // USB Receive Functional Address
-                                            // Endpoint 9
-#define USB_O_RXHUBADDR9        0x000000CE  // USB Receive Hub Address Endpoint
-                                            // 9
-#define USB_O_RXHUBPORT9        0x000000CF  // USB Receive Hub Port Endpoint 9
-#define USB_O_TXFUNCADDR10      0x000000D0  // USB Transmit Functional Address
-                                            // Endpoint 10
-#define USB_O_TXHUBADDR10       0x000000D2  // USB Transmit Hub Address
-                                            // Endpoint 10
-#define USB_O_TXHUBPORT10       0x000000D3  // USB Transmit Hub Port Endpoint
-                                            // 10
-#define USB_O_RXFUNCADDR10      0x000000D4  // USB Receive Functional Address
-                                            // Endpoint 10
-#define USB_O_RXHUBADDR10       0x000000D6  // USB Receive Hub Address Endpoint
-                                            // 10
-#define USB_O_RXHUBPORT10       0x000000D7  // USB Receive Hub Port Endpoint 10
-#define USB_O_TXFUNCADDR11      0x000000D8  // USB Transmit Functional Address
-                                            // Endpoint 11
-#define USB_O_TXHUBADDR11       0x000000DA  // USB Transmit Hub Address
-                                            // Endpoint 11
-#define USB_O_TXHUBPORT11       0x000000DB  // USB Transmit Hub Port Endpoint
-                                            // 11
-#define USB_O_RXFUNCADDR11      0x000000DC  // USB Receive Functional Address
-                                            // Endpoint 11
-#define USB_O_RXHUBADDR11       0x000000DE  // USB Receive Hub Address Endpoint
-                                            // 11
-#define USB_O_RXHUBPORT11       0x000000DF  // USB Receive Hub Port Endpoint 11
-#define USB_O_TXFUNCADDR12      0x000000E0  // USB Transmit Functional Address
-                                            // Endpoint 12
-#define USB_O_TXHUBADDR12       0x000000E2  // USB Transmit Hub Address
-                                            // Endpoint 12
-#define USB_O_TXHUBPORT12       0x000000E3  // USB Transmit Hub Port Endpoint
-                                            // 12
-#define USB_O_RXFUNCADDR12      0x000000E4  // USB Receive Functional Address
-                                            // Endpoint 12
-#define USB_O_RXHUBADDR12       0x000000E6  // USB Receive Hub Address Endpoint
-                                            // 12
-#define USB_O_RXHUBPORT12       0x000000E7  // USB Receive Hub Port Endpoint 12
-#define USB_O_TXFUNCADDR13      0x000000E8  // USB Transmit Functional Address
-                                            // Endpoint 13
-#define USB_O_TXHUBADDR13       0x000000EA  // USB Transmit Hub Address
-                                            // Endpoint 13
-#define USB_O_TXHUBPORT13       0x000000EB  // USB Transmit Hub Port Endpoint
-                                            // 13
-#define USB_O_RXFUNCADDR13      0x000000EC  // USB Receive Functional Address
-                                            // Endpoint 13
-#define USB_O_RXHUBADDR13       0x000000EE  // USB Receive Hub Address Endpoint
-                                            // 13
-#define USB_O_RXHUBPORT13       0x000000EF  // USB Receive Hub Port Endpoint 13
-#define USB_O_TXFUNCADDR14      0x000000F0  // USB Transmit Functional Address
-                                            // Endpoint 14
-#define USB_O_TXHUBADDR14       0x000000F2  // USB Transmit Hub Address
-                                            // Endpoint 14
-#define USB_O_TXHUBPORT14       0x000000F3  // USB Transmit Hub Port Endpoint
-                                            // 14
-#define USB_O_RXFUNCADDR14      0x000000F4  // USB Receive Functional Address
-                                            // Endpoint 14
-#define USB_O_RXHUBADDR14       0x000000F6  // USB Receive Hub Address Endpoint
-                                            // 14
-#define USB_O_RXHUBPORT14       0x000000F7  // USB Receive Hub Port Endpoint 14
-#define USB_O_TXFUNCADDR15      0x000000F8  // USB Transmit Functional Address
-                                            // Endpoint 15
-#define USB_O_TXHUBADDR15       0x000000FA  // USB Transmit Hub Address
-                                            // Endpoint 15
-#define USB_O_TXHUBPORT15       0x000000FB  // USB Transmit Hub Port Endpoint
-                                            // 15
-#define USB_O_RXFUNCADDR15      0x000000FC  // USB Receive Functional Address
-                                            // Endpoint 15
-#define USB_O_RXHUBADDR15       0x000000FE  // USB Receive Hub Address Endpoint
-                                            // 15
-#define USB_O_RXHUBPORT15       0x000000FF  // USB Receive Hub Port Endpoint 15
-#define USB_O_CSRL0             0x00000102  // USB Control and Status Endpoint
-                                            // 0 Low
-#define USB_O_CSRH0             0x00000103  // USB Control and Status Endpoint
-                                            // 0 High
-#define USB_O_COUNT0            0x00000108  // USB Receive Byte Count Endpoint
-                                            // 0
-#define USB_O_TYPE0             0x0000010A  // USB Type Endpoint 0
-#define USB_O_NAKLMT            0x0000010B  // USB NAK Limit
-#define USB_O_TXMAXP1           0x00000110  // USB Maximum Transmit Data
-                                            // Endpoint 1
-#define USB_O_TXCSRL1           0x00000112  // USB Transmit Control and Status
-                                            // Endpoint 1 Low
-#define USB_O_TXCSRH1           0x00000113  // USB Transmit Control and Status
-                                            // Endpoint 1 High
-#define USB_O_RXMAXP1           0x00000114  // USB Maximum Receive Data
-                                            // Endpoint 1
-#define USB_O_RXCSRL1           0x00000116  // USB Receive Control and Status
-                                            // Endpoint 1 Low
-#define USB_O_RXCSRH1           0x00000117  // USB Receive Control and Status
-                                            // Endpoint 1 High
-#define USB_O_RXCOUNT1          0x00000118  // USB Receive Byte Count Endpoint
-                                            // 1
-#define USB_O_TXTYPE1           0x0000011A  // USB Host Transmit Configure Type
-                                            // Endpoint 1
-#define USB_O_TXINTERVAL1       0x0000011B  // USB Host Transmit Interval
-                                            // Endpoint 1
-#define USB_O_RXTYPE1           0x0000011C  // USB Host Configure Receive Type
-                                            // Endpoint 1
-#define USB_O_RXINTERVAL1       0x0000011D  // USB Host Receive Polling
-                                            // Interval Endpoint 1
-#define USB_O_TXMAXP2           0x00000120  // USB Maximum Transmit Data
-                                            // Endpoint 2
-#define USB_O_TXCSRL2           0x00000122  // USB Transmit Control and Status
-                                            // Endpoint 2 Low
-#define USB_O_TXCSRH2           0x00000123  // USB Transmit Control and Status
-                                            // Endpoint 2 High
-#define USB_O_RXMAXP2           0x00000124  // USB Maximum Receive Data
-                                            // Endpoint 2
-#define USB_O_RXCSRL2           0x00000126  // USB Receive Control and Status
-                                            // Endpoint 2 Low
-#define USB_O_RXCSRH2           0x00000127  // USB Receive Control and Status
-                                            // Endpoint 2 High
-#define USB_O_RXCOUNT2          0x00000128  // USB Receive Byte Count Endpoint
-                                            // 2
-#define USB_O_TXTYPE2           0x0000012A  // USB Host Transmit Configure Type
-                                            // Endpoint 2
-#define USB_O_TXINTERVAL2       0x0000012B  // USB Host Transmit Interval
-                                            // Endpoint 2
-#define USB_O_RXTYPE2           0x0000012C  // USB Host Configure Receive Type
-                                            // Endpoint 2
-#define USB_O_RXINTERVAL2       0x0000012D  // USB Host Receive Polling
-                                            // Interval Endpoint 2
-#define USB_O_TXMAXP3           0x00000130  // USB Maximum Transmit Data
-                                            // Endpoint 3
-#define USB_O_TXCSRL3           0x00000132  // USB Transmit Control and Status
-                                            // Endpoint 3 Low
-#define USB_O_TXCSRH3           0x00000133  // USB Transmit Control and Status
-                                            // Endpoint 3 High
-#define USB_O_RXMAXP3           0x00000134  // USB Maximum Receive Data
-                                            // Endpoint 3
-#define USB_O_RXCSRL3           0x00000136  // USB Receive Control and Status
-                                            // Endpoint 3 Low
-#define USB_O_RXCSRH3           0x00000137  // USB Receive Control and Status
-                                            // Endpoint 3 High
-#define USB_O_RXCOUNT3          0x00000138  // USB Receive Byte Count Endpoint
-                                            // 3
-#define USB_O_TXTYPE3           0x0000013A  // USB Host Transmit Configure Type
-                                            // Endpoint 3
-#define USB_O_TXINTERVAL3       0x0000013B  // USB Host Transmit Interval
-                                            // Endpoint 3
-#define USB_O_RXTYPE3           0x0000013C  // USB Host Configure Receive Type
-                                            // Endpoint 3
-#define USB_O_RXINTERVAL3       0x0000013D  // USB Host Receive Polling
-                                            // Interval Endpoint 3
-#define USB_O_TXMAXP4           0x00000140  // USB Maximum Transmit Data
-                                            // Endpoint 4
-#define USB_O_TXCSRL4           0x00000142  // USB Transmit Control and Status
-                                            // Endpoint 4 Low
-#define USB_O_TXCSRH4           0x00000143  // USB Transmit Control and Status
-                                            // Endpoint 4 High
-#define USB_O_RXMAXP4           0x00000144  // USB Maximum Receive Data
-                                            // Endpoint 4
-#define USB_O_RXCSRL4           0x00000146  // USB Receive Control and Status
-                                            // Endpoint 4 Low
-#define USB_O_RXCSRH4           0x00000147  // USB Receive Control and Status
-                                            // Endpoint 4 High
-#define USB_O_RXCOUNT4          0x00000148  // USB Receive Byte Count Endpoint
-                                            // 4
-#define USB_O_TXTYPE4           0x0000014A  // USB Host Transmit Configure Type
-                                            // Endpoint 4
-#define USB_O_TXINTERVAL4       0x0000014B  // USB Host Transmit Interval
-                                            // Endpoint 4
-#define USB_O_RXTYPE4           0x0000014C  // USB Host Configure Receive Type
-                                            // Endpoint 4
-#define USB_O_RXINTERVAL4       0x0000014D  // USB Host Receive Polling
-                                            // Interval Endpoint 4
-#define USB_O_TXMAXP5           0x00000150  // USB Maximum Transmit Data
-                                            // Endpoint 5
-#define USB_O_TXCSRL5           0x00000152  // USB Transmit Control and Status
-                                            // Endpoint 5 Low
-#define USB_O_TXCSRH5           0x00000153  // USB Transmit Control and Status
-                                            // Endpoint 5 High
-#define USB_O_RXMAXP5           0x00000154  // USB Maximum Receive Data
-                                            // Endpoint 5
-#define USB_O_RXCSRL5           0x00000156  // USB Receive Control and Status
-                                            // Endpoint 5 Low
-#define USB_O_RXCSRH5           0x00000157  // USB Receive Control and Status
-                                            // Endpoint 5 High
-#define USB_O_RXCOUNT5          0x00000158  // USB Receive Byte Count Endpoint
-                                            // 5
-#define USB_O_TXTYPE5           0x0000015A  // USB Host Transmit Configure Type
-                                            // Endpoint 5
-#define USB_O_TXINTERVAL5       0x0000015B  // USB Host Transmit Interval
-                                            // Endpoint 5
-#define USB_O_RXTYPE5           0x0000015C  // USB Host Configure Receive Type
-                                            // Endpoint 5
-#define USB_O_RXINTERVAL5       0x0000015D  // USB Host Receive Polling
-                                            // Interval Endpoint 5
-#define USB_O_TXMAXP6           0x00000160  // USB Maximum Transmit Data
-                                            // Endpoint 6
-#define USB_O_TXCSRL6           0x00000162  // USB Transmit Control and Status
-                                            // Endpoint 6 Low
-#define USB_O_TXCSRH6           0x00000163  // USB Transmit Control and Status
-                                            // Endpoint 6 High
-#define USB_O_RXMAXP6           0x00000164  // USB Maximum Receive Data
-                                            // Endpoint 6
-#define USB_O_RXCSRL6           0x00000166  // USB Receive Control and Status
-                                            // Endpoint 6 Low
-#define USB_O_RXCSRH6           0x00000167  // USB Receive Control and Status
-                                            // Endpoint 6 High
-#define USB_O_RXCOUNT6          0x00000168  // USB Receive Byte Count Endpoint
-                                            // 6
-#define USB_O_TXTYPE6           0x0000016A  // USB Host Transmit Configure Type
-                                            // Endpoint 6
-#define USB_O_TXINTERVAL6       0x0000016B  // USB Host Transmit Interval
-                                            // Endpoint 6
-#define USB_O_RXTYPE6           0x0000016C  // USB Host Configure Receive Type
-                                            // Endpoint 6
-#define USB_O_RXINTERVAL6       0x0000016D  // USB Host Receive Polling
-                                            // Interval Endpoint 6
-#define USB_O_TXMAXP7           0x00000170  // USB Maximum Transmit Data
-                                            // Endpoint 7
-#define USB_O_TXCSRL7           0x00000172  // USB Transmit Control and Status
-                                            // Endpoint 7 Low
-#define USB_O_TXCSRH7           0x00000173  // USB Transmit Control and Status
-                                            // Endpoint 7 High
-#define USB_O_RXMAXP7           0x00000174  // USB Maximum Receive Data
-                                            // Endpoint 7
-#define USB_O_RXCSRL7           0x00000176  // USB Receive Control and Status
-                                            // Endpoint 7 Low
-#define USB_O_RXCSRH7           0x00000177  // USB Receive Control and Status
-                                            // Endpoint 7 High
-#define USB_O_RXCOUNT7          0x00000178  // USB Receive Byte Count Endpoint
-                                            // 7
-#define USB_O_TXTYPE7           0x0000017A  // USB Host Transmit Configure Type
-                                            // Endpoint 7
-#define USB_O_TXINTERVAL7       0x0000017B  // USB Host Transmit Interval
-                                            // Endpoint 7
-#define USB_O_RXTYPE7           0x0000017C  // USB Host Configure Receive Type
-                                            // Endpoint 7
-#define USB_O_RXINTERVAL7       0x0000017D  // USB Host Receive Polling
-                                            // Interval Endpoint 7
-#define USB_O_TXMAXP8           0x00000180  // USB Maximum Transmit Data
-                                            // Endpoint 8
-#define USB_O_TXCSRL8           0x00000182  // USB Transmit Control and Status
-                                            // Endpoint 8 Low
-#define USB_O_TXCSRH8           0x00000183  // USB Transmit Control and Status
-                                            // Endpoint 8 High
-#define USB_O_RXMAXP8           0x00000184  // USB Maximum Receive Data
-                                            // Endpoint 8
-#define USB_O_RXCSRL8           0x00000186  // USB Receive Control and Status
-                                            // Endpoint 8 Low
-#define USB_O_RXCSRH8           0x00000187  // USB Receive Control and Status
-                                            // Endpoint 8 High
-#define USB_O_RXCOUNT8          0x00000188  // USB Receive Byte Count Endpoint
-                                            // 8
-#define USB_O_TXTYPE8           0x0000018A  // USB Host Transmit Configure Type
-                                            // Endpoint 8
-#define USB_O_TXINTERVAL8       0x0000018B  // USB Host Transmit Interval
-                                            // Endpoint 8
-#define USB_O_RXTYPE8           0x0000018C  // USB Host Configure Receive Type
-                                            // Endpoint 8
-#define USB_O_RXINTERVAL8       0x0000018D  // USB Host Receive Polling
-                                            // Interval Endpoint 8
-#define USB_O_TXMAXP9           0x00000190  // USB Maximum Transmit Data
-                                            // Endpoint 9
-#define USB_O_TXCSRL9           0x00000192  // USB Transmit Control and Status
-                                            // Endpoint 9 Low
-#define USB_O_TXCSRH9           0x00000193  // USB Transmit Control and Status
-                                            // Endpoint 9 High
-#define USB_O_RXMAXP9           0x00000194  // USB Maximum Receive Data
-                                            // Endpoint 9
-#define USB_O_RXCSRL9           0x00000196  // USB Receive Control and Status
-                                            // Endpoint 9 Low
-#define USB_O_RXCSRH9           0x00000197  // USB Receive Control and Status
-                                            // Endpoint 9 High
-#define USB_O_RXCOUNT9          0x00000198  // USB Receive Byte Count Endpoint
-                                            // 9
-#define USB_O_TXTYPE9           0x0000019A  // USB Host Transmit Configure Type
-                                            // Endpoint 9
-#define USB_O_TXINTERVAL9       0x0000019B  // USB Host Transmit Interval
-                                            // Endpoint 9
-#define USB_O_RXTYPE9           0x0000019C  // USB Host Configure Receive Type
-                                            // Endpoint 9
-#define USB_O_RXINTERVAL9       0x0000019D  // USB Host Receive Polling
-                                            // Interval Endpoint 9
-#define USB_O_TXMAXP10          0x000001A0  // USB Maximum Transmit Data
-                                            // Endpoint 10
-#define USB_O_TXCSRL10          0x000001A2  // USB Transmit Control and Status
-                                            // Endpoint 10 Low
-#define USB_O_TXCSRH10          0x000001A3  // USB Transmit Control and Status
-                                            // Endpoint 10 High
-#define USB_O_RXMAXP10          0x000001A4  // USB Maximum Receive Data
-                                            // Endpoint 10
-#define USB_O_RXCSRL10          0x000001A6  // USB Receive Control and Status
-                                            // Endpoint 10 Low
-#define USB_O_RXCSRH10          0x000001A7  // USB Receive Control and Status
-                                            // Endpoint 10 High
-#define USB_O_RXCOUNT10         0x000001A8  // USB Receive Byte Count Endpoint
-                                            // 10
-#define USB_O_TXTYPE10          0x000001AA  // USB Host Transmit Configure Type
-                                            // Endpoint 10
-#define USB_O_TXINTERVAL10      0x000001AB  // USB Host Transmit Interval
-                                            // Endpoint 10
-#define USB_O_RXTYPE10          0x000001AC  // USB Host Configure Receive Type
-                                            // Endpoint 10
-#define USB_O_RXINTERVAL10      0x000001AD  // USB Host Receive Polling
-                                            // Interval Endpoint 10
-#define USB_O_TXMAXP11          0x000001B0  // USB Maximum Transmit Data
-                                            // Endpoint 11
-#define USB_O_TXCSRL11          0x000001B2  // USB Transmit Control and Status
-                                            // Endpoint 11 Low
-#define USB_O_TXCSRH11          0x000001B3  // USB Transmit Control and Status
-                                            // Endpoint 11 High
-#define USB_O_RXMAXP11          0x000001B4  // USB Maximum Receive Data
-                                            // Endpoint 11
-#define USB_O_RXCSRL11          0x000001B6  // USB Receive Control and Status
-                                            // Endpoint 11 Low
-#define USB_O_RXCSRH11          0x000001B7  // USB Receive Control and Status
-                                            // Endpoint 11 High
-#define USB_O_RXCOUNT11         0x000001B8  // USB Receive Byte Count Endpoint
-                                            // 11
-#define USB_O_TXTYPE11          0x000001BA  // USB Host Transmit Configure Type
-                                            // Endpoint 11
-#define USB_O_TXINTERVAL11      0x000001BB  // USB Host Transmit Interval
-                                            // Endpoint 11
-#define USB_O_RXTYPE11          0x000001BC  // USB Host Configure Receive Type
-                                            // Endpoint 11
-#define USB_O_RXINTERVAL11      0x000001BD  // USB Host Receive Polling
-                                            // Interval Endpoint 11
-#define USB_O_TXMAXP12          0x000001C0  // USB Maximum Transmit Data
-                                            // Endpoint 12
-#define USB_O_TXCSRL12          0x000001C2  // USB Transmit Control and Status
-                                            // Endpoint 12 Low
-#define USB_O_TXCSRH12          0x000001C3  // USB Transmit Control and Status
-                                            // Endpoint 12 High
-#define USB_O_RXMAXP12          0x000001C4  // USB Maximum Receive Data
-                                            // Endpoint 12
-#define USB_O_RXCSRL12          0x000001C6  // USB Receive Control and Status
-                                            // Endpoint 12 Low
-#define USB_O_RXCSRH12          0x000001C7  // USB Receive Control and Status
-                                            // Endpoint 12 High
-#define USB_O_RXCOUNT12         0x000001C8  // USB Receive Byte Count Endpoint
-                                            // 12
-#define USB_O_TXTYPE12          0x000001CA  // USB Host Transmit Configure Type
-                                            // Endpoint 12
-#define USB_O_TXINTERVAL12      0x000001CB  // USB Host Transmit Interval
-                                            // Endpoint 12
-#define USB_O_RXTYPE12          0x000001CC  // USB Host Configure Receive Type
-                                            // Endpoint 12
-#define USB_O_RXINTERVAL12      0x000001CD  // USB Host Receive Polling
-                                            // Interval Endpoint 12
-#define USB_O_TXMAXP13          0x000001D0  // USB Maximum Transmit Data
-                                            // Endpoint 13
-#define USB_O_TXCSRL13          0x000001D2  // USB Transmit Control and Status
-                                            // Endpoint 13 Low
-#define USB_O_TXCSRH13          0x000001D3  // USB Transmit Control and Status
-                                            // Endpoint 13 High
-#define USB_O_RXMAXP13          0x000001D4  // USB Maximum Receive Data
-                                            // Endpoint 13
-#define USB_O_RXCSRL13          0x000001D6  // USB Receive Control and Status
-                                            // Endpoint 13 Low
-#define USB_O_RXCSRH13          0x000001D7  // USB Receive Control and Status
-                                            // Endpoint 13 High
-#define USB_O_RXCOUNT13         0x000001D8  // USB Receive Byte Count Endpoint
-                                            // 13
-#define USB_O_TXTYPE13          0x000001DA  // USB Host Transmit Configure Type
-                                            // Endpoint 13
-#define USB_O_TXINTERVAL13      0x000001DB  // USB Host Transmit Interval
-                                            // Endpoint 13
-#define USB_O_RXTYPE13          0x000001DC  // USB Host Configure Receive Type
-                                            // Endpoint 13
-#define USB_O_RXINTERVAL13      0x000001DD  // USB Host Receive Polling
-                                            // Interval Endpoint 13
-#define USB_O_TXMAXP14          0x000001E0  // USB Maximum Transmit Data
-                                            // Endpoint 14
-#define USB_O_TXCSRL14          0x000001E2  // USB Transmit Control and Status
-                                            // Endpoint 14 Low
-#define USB_O_TXCSRH14          0x000001E3  // USB Transmit Control and Status
-                                            // Endpoint 14 High
-#define USB_O_RXMAXP14          0x000001E4  // USB Maximum Receive Data
-                                            // Endpoint 14
-#define USB_O_RXCSRL14          0x000001E6  // USB Receive Control and Status
-                                            // Endpoint 14 Low
-#define USB_O_RXCSRH14          0x000001E7  // USB Receive Control and Status
-                                            // Endpoint 14 High
-#define USB_O_RXCOUNT14         0x000001E8  // USB Receive Byte Count Endpoint
-                                            // 14
-#define USB_O_TXTYPE14          0x000001EA  // USB Host Transmit Configure Type
-                                            // Endpoint 14
-#define USB_O_TXINTERVAL14      0x000001EB  // USB Host Transmit Interval
-                                            // Endpoint 14
-#define USB_O_RXTYPE14          0x000001EC  // USB Host Configure Receive Type
-                                            // Endpoint 14
-#define USB_O_RXINTERVAL14      0x000001ED  // USB Host Receive Polling
-                                            // Interval Endpoint 14
-#define USB_O_TXMAXP15          0x000001F0  // USB Maximum Transmit Data
-                                            // Endpoint 15
-#define USB_O_TXCSRL15          0x000001F2  // USB Transmit Control and Status
-                                            // Endpoint 15 Low
-#define USB_O_TXCSRH15          0x000001F3  // USB Transmit Control and Status
-                                            // Endpoint 15 High
-#define USB_O_RXMAXP15          0x000001F4  // USB Maximum Receive Data
-                                            // Endpoint 15
-#define USB_O_RXCSRL15          0x000001F6  // USB Receive Control and Status
-                                            // Endpoint 15 Low
-#define USB_O_RXCSRH15          0x000001F7  // USB Receive Control and Status
-                                            // Endpoint 15 High
-#define USB_O_RXCOUNT15         0x000001F8  // USB Receive Byte Count Endpoint
-                                            // 15
-#define USB_O_TXTYPE15          0x000001FA  // USB Host Transmit Configure Type
-                                            // Endpoint 15
-#define USB_O_TXINTERVAL15      0x000001FB  // USB Host Transmit Interval
-                                            // Endpoint 15
-#define USB_O_RXTYPE15          0x000001FC  // USB Host Configure Receive Type
-                                            // Endpoint 15
-#define USB_O_RXINTERVAL15      0x000001FD  // USB Host Receive Polling
-                                            // Interval Endpoint 15
-#define USB_O_RQPKTCOUNT1       0x00000304  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 1
-#define USB_O_RQPKTCOUNT2       0x00000308  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 2
-#define USB_O_RQPKTCOUNT3       0x0000030C  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 3
-#define USB_O_RQPKTCOUNT4       0x00000310  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 4
-#define USB_O_RQPKTCOUNT5       0x00000314  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 5
-#define USB_O_RQPKTCOUNT6       0x00000318  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 6
-#define USB_O_RQPKTCOUNT7       0x0000031C  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 7
-#define USB_O_RQPKTCOUNT8       0x00000320  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 8
-#define USB_O_RQPKTCOUNT9       0x00000324  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 9
-#define USB_O_RQPKTCOUNT10      0x00000328  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 10
-#define USB_O_RQPKTCOUNT11      0x0000032C  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 11
-#define USB_O_RQPKTCOUNT12      0x00000330  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 12
-#define USB_O_RQPKTCOUNT13      0x00000334  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 13
-#define USB_O_RQPKTCOUNT14      0x00000338  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 14
-#define USB_O_RQPKTCOUNT15      0x0000033C  // USB Request Packet Count in
-                                            // Block Transfer Endpoint 15
-#define USB_O_RXDPKTBUFDIS      0x00000340  // USB Receive Double Packet Buffer
-                                            // Disable
-#define USB_O_TXDPKTBUFDIS      0x00000342  // USB Transmit Double Packet
-                                            // Buffer Disable
-#define USB_O_EPC               0x00000400  // USB External Power Control
-#define USB_O_EPCRIS            0x00000404  // USB External Power Control Raw
-                                            // Interrupt Status
-#define USB_O_EPCIM             0x00000408  // USB External Power Control
-                                            // Interrupt Mask
-#define USB_O_EPCISC            0x0000040C  // USB External Power Control
-                                            // Interrupt Status and Clear
-#define USB_O_DRRIS             0x00000410  // USB Device RESUME Raw Interrupt
-                                            // Status
-#define USB_O_DRIM              0x00000414  // USB Device RESUME Interrupt Mask
-#define USB_O_DRISC             0x00000418  // USB Device RESUME Interrupt
-                                            // Status and Clear
-#define USB_O_GPCS              0x0000041C  // USB General-Purpose Control and
-                                            // Status
-#define USB_O_VDC               0x00000430  // USB VBUS Droop Control
-#define USB_O_VDCRIS            0x00000434  // USB VBUS Droop Control Raw
-                                            // Interrupt Status
-#define USB_O_VDCIM             0x00000438  // USB VBUS Droop Control Interrupt
-                                            // Mask
-#define USB_O_VDCISC            0x0000043C  // USB VBUS Droop Control Interrupt
-                                            // Status and Clear
-#define USB_O_IDVRIS            0x00000444  // USB ID Valid Detect Raw
-                                            // Interrupt Status
-#define USB_O_IDVIM             0x00000448  // USB ID Valid Detect Interrupt
-                                            // Mask
-#define USB_O_IDVISC            0x0000044C  // USB ID Valid Detect Interrupt
-                                            // Status and Clear
-#define USB_O_DMASEL            0x00000450  // USB DMA Select
-#define USB_O_PP                0x00000FC0  // USB Peripheral Properties
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FADDR register.
-//
-//*****************************************************************************
-#define USB_FADDR_M             0x0000007F  // Function Address
-#define USB_FADDR_S             0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_POWER register.
-//
-//*****************************************************************************
-#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
-#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
-#define USB_POWER_RESET         0x00000008  // RESET Signaling
-#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
-#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
-#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXIS register.
-//
-//*****************************************************************************
-#define USB_TXIS_EP15           0x00008000  // TX Endpoint 15 Interrupt
-#define USB_TXIS_EP14           0x00004000  // TX Endpoint 14 Interrupt
-#define USB_TXIS_EP13           0x00002000  // TX Endpoint 13 Interrupt
-#define USB_TXIS_EP12           0x00001000  // TX Endpoint 12 Interrupt
-#define USB_TXIS_EP11           0x00000800  // TX Endpoint 11 Interrupt
-#define USB_TXIS_EP10           0x00000400  // TX Endpoint 10 Interrupt
-#define USB_TXIS_EP9            0x00000200  // TX Endpoint 9 Interrupt
-#define USB_TXIS_EP8            0x00000100  // TX Endpoint 8 Interrupt
-#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
-#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
-#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
-#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
-#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
-#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
-#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
-#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXIS register.
-//
-//*****************************************************************************
-#define USB_RXIS_EP15           0x00008000  // RX Endpoint 15 Interrupt
-#define USB_RXIS_EP14           0x00004000  // RX Endpoint 14 Interrupt
-#define USB_RXIS_EP13           0x00002000  // RX Endpoint 13 Interrupt
-#define USB_RXIS_EP12           0x00001000  // RX Endpoint 12 Interrupt
-#define USB_RXIS_EP11           0x00000800  // RX Endpoint 11 Interrupt
-#define USB_RXIS_EP10           0x00000400  // RX Endpoint 10 Interrupt
-#define USB_RXIS_EP9            0x00000200  // RX Endpoint 9 Interrupt
-#define USB_RXIS_EP8            0x00000100  // RX Endpoint 8 Interrupt
-#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
-#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
-#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
-#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
-#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
-#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
-#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXIE register.
-//
-//*****************************************************************************
-#define USB_TXIE_EP15           0x00008000  // TX Endpoint 15 Interrupt Enable
-#define USB_TXIE_EP14           0x00004000  // TX Endpoint 14 Interrupt Enable
-#define USB_TXIE_EP13           0x00002000  // TX Endpoint 13 Interrupt Enable
-#define USB_TXIE_EP12           0x00001000  // TX Endpoint 12 Interrupt Enable
-#define USB_TXIE_EP11           0x00000800  // TX Endpoint 11 Interrupt Enable
-#define USB_TXIE_EP10           0x00000400  // TX Endpoint 10 Interrupt Enable
-#define USB_TXIE_EP9            0x00000200  // TX Endpoint 9 Interrupt Enable
-#define USB_TXIE_EP8            0x00000100  // TX Endpoint 8 Interrupt Enable
-#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
-#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
-#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
-#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
-#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
-#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
-#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
-#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
-                                            // Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXIE register.
-//
-//*****************************************************************************
-#define USB_RXIE_EP15           0x00008000  // RX Endpoint 15 Interrupt Enable
-#define USB_RXIE_EP14           0x00004000  // RX Endpoint 14 Interrupt Enable
-#define USB_RXIE_EP13           0x00002000  // RX Endpoint 13 Interrupt Enable
-#define USB_RXIE_EP12           0x00001000  // RX Endpoint 12 Interrupt Enable
-#define USB_RXIE_EP11           0x00000800  // RX Endpoint 11 Interrupt Enable
-#define USB_RXIE_EP10           0x00000400  // RX Endpoint 10 Interrupt Enable
-#define USB_RXIE_EP9            0x00000200  // RX Endpoint 9 Interrupt Enable
-#define USB_RXIE_EP8            0x00000100  // RX Endpoint 8 Interrupt Enable
-#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
-#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
-#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
-#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
-#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
-#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
-#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IS register.
-//
-//*****************************************************************************
-#define USB_IS_VBUSERR          0x00000080  // VBUS Error
-#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST
-#define USB_IS_DISCON           0x00000020  // Session Disconnect
-#define USB_IS_CONN             0x00000010  // Session Connect
-#define USB_IS_SOF              0x00000008  // Start of Frame
-#define USB_IS_BABBLE           0x00000004  // Babble Detected
-#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
-#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
-#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IE register.
-//
-//*****************************************************************************
-#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt
-#define USB_IE_SESREQ           0x00000040  // Enable Session Request
-#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
-#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
-#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
-#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
-#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
-#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
-#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FRAME register.
-//
-//*****************************************************************************
-#define USB_FRAME_M             0x000007FF  // Frame Number
-#define USB_FRAME_S             0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPIDX register.
-//
-//*****************************************************************************
-#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
-#define USB_EPIDX_EPIDX_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TEST register.
-//
-//*****************************************************************************
-#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
-#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
-#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO0 register.
-//
-//*****************************************************************************
-#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO0_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO1 register.
-//
-//*****************************************************************************
-#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO1_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO2 register.
-//
-//*****************************************************************************
-#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO2_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO3 register.
-//
-//*****************************************************************************
-#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO3_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO4 register.
-//
-//*****************************************************************************
-#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO4_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO5 register.
-//
-//*****************************************************************************
-#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO5_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO6 register.
-//
-//*****************************************************************************
-#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO6_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO7 register.
-//
-//*****************************************************************************
-#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO7_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO8 register.
-//
-//*****************************************************************************
-#define USB_FIFO8_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO8_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO9 register.
-//
-//*****************************************************************************
-#define USB_FIFO9_EPDATA_M      0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO9_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO10 register.
-//
-//*****************************************************************************
-#define USB_FIFO10_EPDATA_M     0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO10_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO11 register.
-//
-//*****************************************************************************
-#define USB_FIFO11_EPDATA_M     0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO11_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO12 register.
-//
-//*****************************************************************************
-#define USB_FIFO12_EPDATA_M     0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO12_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO13 register.
-//
-//*****************************************************************************
-#define USB_FIFO13_EPDATA_M     0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO13_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO14 register.
-//
-//*****************************************************************************
-#define USB_FIFO14_EPDATA_M     0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO14_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO15 register.
-//
-//*****************************************************************************
-#define USB_FIFO15_EPDATA_M     0xFFFFFFFF  // Endpoint Data
-#define USB_FIFO15_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DEVCTL register.
-//
-//*****************************************************************************
-#define USB_DEVCTL_DEV          0x00000080  // Device Mode
-#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
-#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
-#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level
-#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
-#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
-#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
-#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
-#define USB_DEVCTL_HOST         0x00000004  // Host Mode
-#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request
-#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
-//
-//*****************************************************************************
-#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
-#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
-#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
-#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
-#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
-#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64
-#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128
-#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256
-#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512
-#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024
-#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
-//
-//*****************************************************************************
-#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
-#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
-#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
-#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
-#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
-#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64
-#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128
-#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256
-#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512
-#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024
-#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFIFOADD
-// register.
-//
-//*****************************************************************************
-#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
-#define USB_TXFIFOADD_ADDR_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFIFOADD
-// register.
-//
-//*****************************************************************************
-#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
-#define USB_RXFIFOADD_ADDR_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CONTIM register.
-//
-//*****************************************************************************
-#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
-#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
-#define USB_CONTIM_WTCON_S      4
-#define USB_CONTIM_WTID_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VPLEN register.
-//
-//*****************************************************************************
-#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
-#define USB_VPLEN_VPLEN_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FSEOF register.
-//
-//*****************************************************************************
-#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
-#define USB_FSEOF_FSEOFG_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LSEOF register.
-//
-//*****************************************************************************
-#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
-#define USB_LSEOF_LSEOFG_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR0_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR0
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR0_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT0
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT0_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR1_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR1_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT1
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT1_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR1_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR1_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT1
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT1_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR2_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR2
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR2_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT2
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT2_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR2_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR2
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR2_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT2
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT2_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR3_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR3
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR3_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT3
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT3_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR3_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR3
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR3_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT3
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT3_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR4_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR4_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT4
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT4_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR4_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR4_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT4
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT4_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR5_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR5_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT5
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT5_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR5_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR5_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT5
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT5_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR6_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR6_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT6
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT6_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR6_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR6_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT6
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT6_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR7_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR7_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT7
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT7_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR7_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR7_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT7
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT7_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR8
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR8_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR8_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR8
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR8_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR8_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT8
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT8_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT8_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR8
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR8_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR8_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR8
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR8_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR8_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT8
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT8_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT8_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR9
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR9_ADDR_M  0x0000007F  // Device Address
-#define USB_TXFUNCADDR9_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR9
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR9_ADDR_M   0x0000007F  // Hub Address
-#define USB_TXHUBADDR9_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT9
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT9_PORT_M   0x0000007F  // Hub Port
-#define USB_TXHUBPORT9_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR9
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR9_ADDR_M  0x0000007F  // Device Address
-#define USB_RXFUNCADDR9_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR9
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR9_ADDR_M   0x0000007F  // Hub Address
-#define USB_RXHUBADDR9_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT9
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT9_PORT_M   0x0000007F  // Hub Port
-#define USB_RXHUBPORT9_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR10
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR10_ADDR_M 0x0000007F  // Device Address
-#define USB_TXFUNCADDR10_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR10
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR10_ADDR_M  0x0000007F  // Hub Address
-#define USB_TXHUBADDR10_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT10
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT10_PORT_M  0x0000007F  // Hub Port
-#define USB_TXHUBPORT10_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR10
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR10_ADDR_M 0x0000007F  // Device Address
-#define USB_RXFUNCADDR10_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR10
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR10_ADDR_M  0x0000007F  // Hub Address
-#define USB_RXHUBADDR10_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT10
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT10_PORT_M  0x0000007F  // Hub Port
-#define USB_RXHUBPORT10_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR11
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR11_ADDR_M 0x0000007F  // Device Address
-#define USB_TXFUNCADDR11_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR11
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR11_ADDR_M  0x0000007F  // Hub Address
-#define USB_TXHUBADDR11_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT11
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT11_PORT_M  0x0000007F  // Hub Port
-#define USB_TXHUBPORT11_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR11
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR11_ADDR_M 0x0000007F  // Device Address
-#define USB_RXFUNCADDR11_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR11
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR11_ADDR_M  0x0000007F  // Hub Address
-#define USB_RXHUBADDR11_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT11
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT11_PORT_M  0x0000007F  // Hub Port
-#define USB_RXHUBPORT11_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR12
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR12_ADDR_M 0x0000007F  // Device Address
-#define USB_TXFUNCADDR12_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR12
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR12_ADDR_M  0x0000007F  // Hub Address
-#define USB_TXHUBADDR12_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT12
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT12_PORT_M  0x0000007F  // Hub Port
-#define USB_TXHUBPORT12_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR12
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR12_ADDR_M 0x0000007F  // Device Address
-#define USB_RXFUNCADDR12_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR12
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR12_ADDR_M  0x0000007F  // Hub Address
-#define USB_RXHUBADDR12_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT12
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT12_PORT_M  0x0000007F  // Hub Port
-#define USB_RXHUBPORT12_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR13
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR13_ADDR_M 0x0000007F  // Device Address
-#define USB_TXFUNCADDR13_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR13
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR13_ADDR_M  0x0000007F  // Hub Address
-#define USB_TXHUBADDR13_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT13
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT13_PORT_M  0x0000007F  // Hub Port
-#define USB_TXHUBPORT13_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR13
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR13_ADDR_M 0x0000007F  // Device Address
-#define USB_RXFUNCADDR13_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR13
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR13_ADDR_M  0x0000007F  // Hub Address
-#define USB_RXHUBADDR13_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT13
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT13_PORT_M  0x0000007F  // Hub Port
-#define USB_RXHUBPORT13_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR14
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR14_ADDR_M 0x0000007F  // Device Address
-#define USB_TXFUNCADDR14_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR14
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR14_ADDR_M  0x0000007F  // Hub Address
-#define USB_TXHUBADDR14_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT14
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT14_PORT_M  0x0000007F  // Hub Port
-#define USB_TXHUBPORT14_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR14
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR14_ADDR_M 0x0000007F  // Device Address
-#define USB_RXFUNCADDR14_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR14
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR14_ADDR_M  0x0000007F  // Hub Address
-#define USB_RXHUBADDR14_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT14
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT14_PORT_M  0x0000007F  // Hub Port
-#define USB_RXHUBPORT14_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR15
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR15_ADDR_M 0x0000007F  // Device Address
-#define USB_TXFUNCADDR15_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR15
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR15_ADDR_M  0x0000007F  // Hub Address
-#define USB_TXHUBADDR15_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT15
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT15_PORT_M  0x0000007F  // Hub Port
-#define USB_TXHUBPORT15_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR15
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR15_ADDR_M 0x0000007F  // Device Address
-#define USB_RXFUNCADDR15_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR15
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR15_ADDR_M  0x0000007F  // Hub Address
-#define USB_RXHUBADDR15_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT15
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT15_PORT_M  0x0000007F  // Hub Port
-#define USB_RXHUBPORT15_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CSRL0 register.
-//
-//*****************************************************************************
-#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
-#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
-#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
-#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
-#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
-#define USB_CSRL0_STALL         0x00000020  // Send Stall
-#define USB_CSRL0_SETEND        0x00000010  // Setup End
-#define USB_CSRL0_ERROR         0x00000010  // Error
-#define USB_CSRL0_DATAEND       0x00000008  // Data End
-#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
-#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
-#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
-#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CSRH0 register.
-//
-//*****************************************************************************
-#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
-#define USB_CSRH0_DT            0x00000002  // Data Toggle
-#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_COUNT0 register.
-//
-//*****************************************************************************
-#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
-#define USB_COUNT0_COUNT_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TYPE0 register.
-//
-//*****************************************************************************
-#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
-#define USB_TYPE0_SPEED_FULL    0x00000080  // Full
-#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_NAKLMT register.
-//
-//*****************************************************************************
-#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
-#define USB_NAKLMT_NAKLMT_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP1_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL1_ERROR       0x00000004  // Error
-#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH1_MODE        0x00000020  // Mode
-#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP1_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL1_OVER        0x00000004  // Overrun
-#define USB_RXCSRL1_ERROR       0x00000004  // Error
-#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT1_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE1_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL1
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL1_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL1_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL1_TXPOLL_S \
-                                0
-#define USB_TXINTERVAL1_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE1_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL1
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL1_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL1_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL1_TXPOLL_S \
-                                0
-#define USB_RXINTERVAL1_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP2_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL2_ERROR       0x00000004  // Error
-#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH2_MODE        0x00000020  // Mode
-#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP2_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL2_ERROR       0x00000004  // Error
-#define USB_RXCSRL2_OVER        0x00000004  // Overrun
-#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT2_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE2_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL2
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL2_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL2_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL2_NAKLMT_S \
-                                0
-#define USB_TXINTERVAL2_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE2_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL2
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL2_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL2_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL2_TXPOLL_S \
-                                0
-#define USB_RXINTERVAL2_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP3_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL3_ERROR       0x00000004  // Error
-#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH3_MODE        0x00000020  // Mode
-#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP3_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL3_ERROR       0x00000004  // Error
-#define USB_RXCSRL3_OVER        0x00000004  // Overrun
-#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT3_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE3_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL3
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL3_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL3_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL3_TXPOLL_S \
-                                0
-#define USB_TXINTERVAL3_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE3_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL3
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL3_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL3_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL3_TXPOLL_S \
-                                0
-#define USB_RXINTERVAL3_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP4_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL4_ERROR       0x00000004  // Error
-#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH4_MODE        0x00000020  // Mode
-#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP4_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL4_OVER        0x00000004  // Overrun
-#define USB_RXCSRL4_ERROR       0x00000004  // Error
-#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT4_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE4_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL4
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL4_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL4_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL4_NAKLMT_S \
-                                0
-#define USB_TXINTERVAL4_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE4_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL4
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL4_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL4_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL4_NAKLMT_S \
-                                0
-#define USB_RXINTERVAL4_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP5_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL5_ERROR       0x00000004  // Error
-#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH5_MODE        0x00000020  // Mode
-#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP5_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL5_ERROR       0x00000004  // Error
-#define USB_RXCSRL5_OVER        0x00000004  // Overrun
-#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT5_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE5_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL5
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL5_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL5_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL5_NAKLMT_S \
-                                0
-#define USB_TXINTERVAL5_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE5_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL5
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL5_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL5_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL5_TXPOLL_S \
-                                0
-#define USB_RXINTERVAL5_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP6_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL6_ERROR       0x00000004  // Error
-#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH6_MODE        0x00000020  // Mode
-#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP6_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL6_ERROR       0x00000004  // Error
-#define USB_RXCSRL6_OVER        0x00000004  // Overrun
-#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT6_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE6_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL6
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL6_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL6_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL6_TXPOLL_S \
-                                0
-#define USB_TXINTERVAL6_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE6_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL6
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL6_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL6_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL6_NAKLMT_S \
-                                0
-#define USB_RXINTERVAL6_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP7_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL7_ERROR       0x00000004  // Error
-#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH7_MODE        0x00000020  // Mode
-#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP7_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL7_ERROR       0x00000004  // Error
-#define USB_RXCSRL7_OVER        0x00000004  // Overrun
-#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT7_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE7_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL7
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL7_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL7_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL7_NAKLMT_S \
-                                0
-#define USB_TXINTERVAL7_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE7_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL7
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL7_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL7_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL7_NAKLMT_S \
-                                0
-#define USB_RXINTERVAL7_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP8 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP8_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL8 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL8_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL8_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL8_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL8_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL8_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL8_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL8_ERROR       0x00000004  // Error
-#define USB_TXCSRL8_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL8_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL8_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH8 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH8_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH8_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH8_MODE        0x00000020  // Mode
-#define USB_TXCSRH8_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH8_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH8_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH8_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH8_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP8 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP8_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL8 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL8_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL8_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL8_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL8_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL8_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL8_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL8_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL8_OVER        0x00000004  // Overrun
-#define USB_RXCSRL8_ERROR       0x00000004  // Error
-#define USB_RXCSRL8_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL8_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH8 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH8_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH8_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH8_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH8_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH8_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH8_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH8_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH8_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH8_DT          0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT8 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT8_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT8_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE8 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE8_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE8_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE8_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE8_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE8_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE8_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE8_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE8_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE8_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE8_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL8
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL8_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL8_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL8_NAKLMT_S \
-                                0
-#define USB_TXINTERVAL8_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE8 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE8_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE8_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE8_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE8_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE8_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE8_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE8_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE8_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE8_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE8_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL8
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL8_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL8_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL8_NAKLMT_S \
-                                0
-#define USB_RXINTERVAL8_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP9 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_TXMAXP9_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL9 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL9_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL9_CLRDT       0x00000040  // Clear Data Toggle
-#define USB_TXCSRL9_STALLED     0x00000020  // Endpoint Stalled
-#define USB_TXCSRL9_SETUP       0x00000010  // Setup Packet
-#define USB_TXCSRL9_STALL       0x00000010  // Send STALL
-#define USB_TXCSRL9_FLUSH       0x00000008  // Flush FIFO
-#define USB_TXCSRL9_ERROR       0x00000004  // Error
-#define USB_TXCSRL9_UNDRN       0x00000004  // Underrun
-#define USB_TXCSRL9_FIFONE      0x00000002  // FIFO Not Empty
-#define USB_TXCSRL9_TXRDY       0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH9 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH9_AUTOSET     0x00000080  // Auto Set
-#define USB_TXCSRH9_ISO         0x00000040  // Isochronous Transfers
-#define USB_TXCSRH9_MODE        0x00000020  // Mode
-#define USB_TXCSRH9_DMAEN       0x00000010  // DMA Request Enable
-#define USB_TXCSRH9_FDT         0x00000008  // Force Data Toggle
-#define USB_TXCSRH9_DMAMOD      0x00000004  // DMA Request Mode
-#define USB_TXCSRH9_DTWE        0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH9_DT          0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP9 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload
-#define USB_RXMAXP9_MAXLOAD_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL9 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL9_CLRDT       0x00000080  // Clear Data Toggle
-#define USB_RXCSRL9_STALLED     0x00000040  // Endpoint Stalled
-#define USB_RXCSRL9_STALL       0x00000020  // Send STALL
-#define USB_RXCSRL9_REQPKT      0x00000020  // Request Packet
-#define USB_RXCSRL9_FLUSH       0x00000010  // Flush FIFO
-#define USB_RXCSRL9_DATAERR     0x00000008  // Data Error
-#define USB_RXCSRL9_NAKTO       0x00000008  // NAK Timeout
-#define USB_RXCSRL9_ERROR       0x00000004  // Error
-#define USB_RXCSRL9_OVER        0x00000004  // Overrun
-#define USB_RXCSRL9_FULL        0x00000002  // FIFO Full
-#define USB_RXCSRL9_RXRDY       0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH9 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH9_AUTOCL      0x00000080  // Auto Clear
-#define USB_RXCSRH9_ISO         0x00000040  // Isochronous Transfers
-#define USB_RXCSRH9_AUTORQ      0x00000040  // Auto Request
-#define USB_RXCSRH9_DMAEN       0x00000020  // DMA Request Enable
-#define USB_RXCSRH9_PIDERR      0x00000010  // PID Error
-#define USB_RXCSRH9_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH9_DMAMOD      0x00000008  // DMA Request Mode
-#define USB_RXCSRH9_DTWE        0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH9_DT          0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT9 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT9_COUNT_M    0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT9_COUNT_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE9 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE9_SPEED_M     0x000000C0  // Operating Speed
-#define USB_TXTYPE9_SPEED_DFLT  0x00000000  // Default
-#define USB_TXTYPE9_SPEED_FULL  0x00000080  // Full
-#define USB_TXTYPE9_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE9_PROTO_M     0x00000030  // Protocol
-#define USB_TXTYPE9_PROTO_CTRL  0x00000000  // Control
-#define USB_TXTYPE9_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_TXTYPE9_PROTO_BULK  0x00000020  // Bulk
-#define USB_TXTYPE9_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE9_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL9
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL9_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL9_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL9_TXPOLL_S \
-                                0
-#define USB_TXINTERVAL9_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE9 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE9_SPEED_M     0x000000C0  // Operating Speed
-#define USB_RXTYPE9_SPEED_DFLT  0x00000000  // Default
-#define USB_RXTYPE9_SPEED_FULL  0x00000080  // Full
-#define USB_RXTYPE9_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE9_PROTO_M     0x00000030  // Protocol
-#define USB_RXTYPE9_PROTO_CTRL  0x00000000  // Control
-#define USB_RXTYPE9_PROTO_ISOC  0x00000010  // Isochronous
-#define USB_RXTYPE9_PROTO_BULK  0x00000020  // Bulk
-#define USB_RXTYPE9_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE9_TEP_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL9
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL9_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL9_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL9_NAKLMT_S \
-                                0
-#define USB_RXINTERVAL9_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP10 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_TXMAXP10_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL10 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL10_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL10_CLRDT      0x00000040  // Clear Data Toggle
-#define USB_TXCSRL10_STALLED    0x00000020  // Endpoint Stalled
-#define USB_TXCSRL10_SETUP      0x00000010  // Setup Packet
-#define USB_TXCSRL10_STALL      0x00000010  // Send STALL
-#define USB_TXCSRL10_FLUSH      0x00000008  // Flush FIFO
-#define USB_TXCSRL10_UNDRN      0x00000004  // Underrun
-#define USB_TXCSRL10_ERROR      0x00000004  // Error
-#define USB_TXCSRL10_FIFONE     0x00000002  // FIFO Not Empty
-#define USB_TXCSRL10_TXRDY      0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH10 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH10_AUTOSET    0x00000080  // Auto Set
-#define USB_TXCSRH10_ISO        0x00000040  // Isochronous Transfers
-#define USB_TXCSRH10_MODE       0x00000020  // Mode
-#define USB_TXCSRH10_DMAEN      0x00000010  // DMA Request Enable
-#define USB_TXCSRH10_FDT        0x00000008  // Force Data Toggle
-#define USB_TXCSRH10_DMAMOD     0x00000004  // DMA Request Mode
-#define USB_TXCSRH10_DTWE       0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH10_DT         0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP10 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_RXMAXP10_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL10 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL10_CLRDT      0x00000080  // Clear Data Toggle
-#define USB_RXCSRL10_STALLED    0x00000040  // Endpoint Stalled
-#define USB_RXCSRL10_STALL      0x00000020  // Send STALL
-#define USB_RXCSRL10_REQPKT     0x00000020  // Request Packet
-#define USB_RXCSRL10_FLUSH      0x00000010  // Flush FIFO
-#define USB_RXCSRL10_NAKTO      0x00000008  // NAK Timeout
-#define USB_RXCSRL10_DATAERR    0x00000008  // Data Error
-#define USB_RXCSRL10_OVER       0x00000004  // Overrun
-#define USB_RXCSRL10_ERROR      0x00000004  // Error
-#define USB_RXCSRL10_FULL       0x00000002  // FIFO Full
-#define USB_RXCSRL10_RXRDY      0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH10 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH10_AUTOCL     0x00000080  // Auto Clear
-#define USB_RXCSRH10_AUTORQ     0x00000040  // Auto Request
-#define USB_RXCSRH10_ISO        0x00000040  // Isochronous Transfers
-#define USB_RXCSRH10_DMAEN      0x00000020  // DMA Request Enable
-#define USB_RXCSRH10_PIDERR     0x00000010  // PID Error
-#define USB_RXCSRH10_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH10_DMAMOD     0x00000008  // DMA Request Mode
-#define USB_RXCSRH10_DTWE       0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH10_DT         0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT10
-// register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT10_COUNT_M   0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT10_COUNT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE10 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE10_SPEED_M    0x000000C0  // Operating Speed
-#define USB_TXTYPE10_SPEED_DFLT 0x00000000  // Default
-#define USB_TXTYPE10_SPEED_FULL 0x00000080  // Full
-#define USB_TXTYPE10_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE10_PROTO_M    0x00000030  // Protocol
-#define USB_TXTYPE10_PROTO_CTRL 0x00000000  // Control
-#define USB_TXTYPE10_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_TXTYPE10_PROTO_BULK 0x00000020  // Bulk
-#define USB_TXTYPE10_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE10_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL10
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL10_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL10_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL10_TXPOLL_S \
-                                0
-#define USB_TXINTERVAL10_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE10 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE10_SPEED_M    0x000000C0  // Operating Speed
-#define USB_RXTYPE10_SPEED_DFLT 0x00000000  // Default
-#define USB_RXTYPE10_SPEED_FULL 0x00000080  // Full
-#define USB_RXTYPE10_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE10_PROTO_M    0x00000030  // Protocol
-#define USB_RXTYPE10_PROTO_CTRL 0x00000000  // Control
-#define USB_RXTYPE10_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_RXTYPE10_PROTO_BULK 0x00000020  // Bulk
-#define USB_RXTYPE10_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE10_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL10
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL10_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL10_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL10_TXPOLL_S \
-                                0
-#define USB_RXINTERVAL10_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP11 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_TXMAXP11_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL11 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL11_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL11_CLRDT      0x00000040  // Clear Data Toggle
-#define USB_TXCSRL11_STALLED    0x00000020  // Endpoint Stalled
-#define USB_TXCSRL11_STALL      0x00000010  // Send STALL
-#define USB_TXCSRL11_SETUP      0x00000010  // Setup Packet
-#define USB_TXCSRL11_FLUSH      0x00000008  // Flush FIFO
-#define USB_TXCSRL11_ERROR      0x00000004  // Error
-#define USB_TXCSRL11_UNDRN      0x00000004  // Underrun
-#define USB_TXCSRL11_FIFONE     0x00000002  // FIFO Not Empty
-#define USB_TXCSRL11_TXRDY      0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH11 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH11_AUTOSET    0x00000080  // Auto Set
-#define USB_TXCSRH11_ISO        0x00000040  // Isochronous Transfers
-#define USB_TXCSRH11_MODE       0x00000020  // Mode
-#define USB_TXCSRH11_DMAEN      0x00000010  // DMA Request Enable
-#define USB_TXCSRH11_FDT        0x00000008  // Force Data Toggle
-#define USB_TXCSRH11_DMAMOD     0x00000004  // DMA Request Mode
-#define USB_TXCSRH11_DTWE       0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH11_DT         0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP11 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_RXMAXP11_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL11 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL11_CLRDT      0x00000080  // Clear Data Toggle
-#define USB_RXCSRL11_STALLED    0x00000040  // Endpoint Stalled
-#define USB_RXCSRL11_STALL      0x00000020  // Send STALL
-#define USB_RXCSRL11_REQPKT     0x00000020  // Request Packet
-#define USB_RXCSRL11_FLUSH      0x00000010  // Flush FIFO
-#define USB_RXCSRL11_DATAERR    0x00000008  // Data Error
-#define USB_RXCSRL11_NAKTO      0x00000008  // NAK Timeout
-#define USB_RXCSRL11_OVER       0x00000004  // Overrun
-#define USB_RXCSRL11_ERROR      0x00000004  // Error
-#define USB_RXCSRL11_FULL       0x00000002  // FIFO Full
-#define USB_RXCSRL11_RXRDY      0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH11 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH11_AUTOCL     0x00000080  // Auto Clear
-#define USB_RXCSRH11_ISO        0x00000040  // Isochronous Transfers
-#define USB_RXCSRH11_AUTORQ     0x00000040  // Auto Request
-#define USB_RXCSRH11_DMAEN      0x00000020  // DMA Request Enable
-#define USB_RXCSRH11_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH11_PIDERR     0x00000010  // PID Error
-#define USB_RXCSRH11_DMAMOD     0x00000008  // DMA Request Mode
-#define USB_RXCSRH11_DTWE       0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH11_DT         0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT11
-// register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT11_COUNT_M   0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT11_COUNT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE11 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE11_SPEED_M    0x000000C0  // Operating Speed
-#define USB_TXTYPE11_SPEED_DFLT 0x00000000  // Default
-#define USB_TXTYPE11_SPEED_FULL 0x00000080  // Full
-#define USB_TXTYPE11_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE11_PROTO_M    0x00000030  // Protocol
-#define USB_TXTYPE11_PROTO_CTRL 0x00000000  // Control
-#define USB_TXTYPE11_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_TXTYPE11_PROTO_BULK 0x00000020  // Bulk
-#define USB_TXTYPE11_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE11_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL11
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL11_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL11_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL11_NAKLMT_S \
-                                0
-#define USB_TXINTERVAL11_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE11 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE11_SPEED_M    0x000000C0  // Operating Speed
-#define USB_RXTYPE11_SPEED_DFLT 0x00000000  // Default
-#define USB_RXTYPE11_SPEED_FULL 0x00000080  // Full
-#define USB_RXTYPE11_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE11_PROTO_M    0x00000030  // Protocol
-#define USB_RXTYPE11_PROTO_CTRL 0x00000000  // Control
-#define USB_RXTYPE11_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_RXTYPE11_PROTO_BULK 0x00000020  // Bulk
-#define USB_RXTYPE11_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE11_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL11
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL11_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL11_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL11_TXPOLL_S \
-                                0
-#define USB_RXINTERVAL11_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP12 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_TXMAXP12_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL12 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL12_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL12_CLRDT      0x00000040  // Clear Data Toggle
-#define USB_TXCSRL12_STALLED    0x00000020  // Endpoint Stalled
-#define USB_TXCSRL12_SETUP      0x00000010  // Setup Packet
-#define USB_TXCSRL12_STALL      0x00000010  // Send STALL
-#define USB_TXCSRL12_FLUSH      0x00000008  // Flush FIFO
-#define USB_TXCSRL12_UNDRN      0x00000004  // Underrun
-#define USB_TXCSRL12_ERROR      0x00000004  // Error
-#define USB_TXCSRL12_FIFONE     0x00000002  // FIFO Not Empty
-#define USB_TXCSRL12_TXRDY      0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH12 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH12_AUTOSET    0x00000080  // Auto Set
-#define USB_TXCSRH12_ISO        0x00000040  // Isochronous Transfers
-#define USB_TXCSRH12_MODE       0x00000020  // Mode
-#define USB_TXCSRH12_DMAEN      0x00000010  // DMA Request Enable
-#define USB_TXCSRH12_FDT        0x00000008  // Force Data Toggle
-#define USB_TXCSRH12_DMAMOD     0x00000004  // DMA Request Mode
-#define USB_TXCSRH12_DTWE       0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH12_DT         0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP12 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_RXMAXP12_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL12 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL12_CLRDT      0x00000080  // Clear Data Toggle
-#define USB_RXCSRL12_STALLED    0x00000040  // Endpoint Stalled
-#define USB_RXCSRL12_STALL      0x00000020  // Send STALL
-#define USB_RXCSRL12_REQPKT     0x00000020  // Request Packet
-#define USB_RXCSRL12_FLUSH      0x00000010  // Flush FIFO
-#define USB_RXCSRL12_NAKTO      0x00000008  // NAK Timeout
-#define USB_RXCSRL12_DATAERR    0x00000008  // Data Error
-#define USB_RXCSRL12_ERROR      0x00000004  // Error
-#define USB_RXCSRL12_OVER       0x00000004  // Overrun
-#define USB_RXCSRL12_FULL       0x00000002  // FIFO Full
-#define USB_RXCSRL12_RXRDY      0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH12 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH12_AUTOCL     0x00000080  // Auto Clear
-#define USB_RXCSRH12_ISO        0x00000040  // Isochronous Transfers
-#define USB_RXCSRH12_AUTORQ     0x00000040  // Auto Request
-#define USB_RXCSRH12_DMAEN      0x00000020  // DMA Request Enable
-#define USB_RXCSRH12_PIDERR     0x00000010  // PID Error
-#define USB_RXCSRH12_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH12_DMAMOD     0x00000008  // DMA Request Mode
-#define USB_RXCSRH12_DTWE       0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH12_DT         0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT12
-// register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT12_COUNT_M   0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT12_COUNT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE12 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE12_SPEED_M    0x000000C0  // Operating Speed
-#define USB_TXTYPE12_SPEED_DFLT 0x00000000  // Default
-#define USB_TXTYPE12_SPEED_FULL 0x00000080  // Full
-#define USB_TXTYPE12_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE12_PROTO_M    0x00000030  // Protocol
-#define USB_TXTYPE12_PROTO_CTRL 0x00000000  // Control
-#define USB_TXTYPE12_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_TXTYPE12_PROTO_BULK 0x00000020  // Bulk
-#define USB_TXTYPE12_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE12_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL12
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL12_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL12_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL12_TXPOLL_S \
-                                0
-#define USB_TXINTERVAL12_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE12 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE12_SPEED_M    0x000000C0  // Operating Speed
-#define USB_RXTYPE12_SPEED_DFLT 0x00000000  // Default
-#define USB_RXTYPE12_SPEED_FULL 0x00000080  // Full
-#define USB_RXTYPE12_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE12_PROTO_M    0x00000030  // Protocol
-#define USB_RXTYPE12_PROTO_CTRL 0x00000000  // Control
-#define USB_RXTYPE12_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_RXTYPE12_PROTO_BULK 0x00000020  // Bulk
-#define USB_RXTYPE12_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE12_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL12
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL12_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL12_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL12_NAKLMT_S \
-                                0
-#define USB_RXINTERVAL12_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP13 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_TXMAXP13_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL13 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL13_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL13_CLRDT      0x00000040  // Clear Data Toggle
-#define USB_TXCSRL13_STALLED    0x00000020  // Endpoint Stalled
-#define USB_TXCSRL13_SETUP      0x00000010  // Setup Packet
-#define USB_TXCSRL13_STALL      0x00000010  // Send STALL
-#define USB_TXCSRL13_FLUSH      0x00000008  // Flush FIFO
-#define USB_TXCSRL13_UNDRN      0x00000004  // Underrun
-#define USB_TXCSRL13_ERROR      0x00000004  // Error
-#define USB_TXCSRL13_FIFONE     0x00000002  // FIFO Not Empty
-#define USB_TXCSRL13_TXRDY      0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH13 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH13_AUTOSET    0x00000080  // Auto Set
-#define USB_TXCSRH13_ISO        0x00000040  // Isochronous Transfers
-#define USB_TXCSRH13_MODE       0x00000020  // Mode
-#define USB_TXCSRH13_DMAEN      0x00000010  // DMA Request Enable
-#define USB_TXCSRH13_FDT        0x00000008  // Force Data Toggle
-#define USB_TXCSRH13_DMAMOD     0x00000004  // DMA Request Mode
-#define USB_TXCSRH13_DTWE       0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH13_DT         0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP13 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_RXMAXP13_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL13 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL13_CLRDT      0x00000080  // Clear Data Toggle
-#define USB_RXCSRL13_STALLED    0x00000040  // Endpoint Stalled
-#define USB_RXCSRL13_REQPKT     0x00000020  // Request Packet
-#define USB_RXCSRL13_STALL      0x00000020  // Send STALL
-#define USB_RXCSRL13_FLUSH      0x00000010  // Flush FIFO
-#define USB_RXCSRL13_NAKTO      0x00000008  // NAK Timeout
-#define USB_RXCSRL13_DATAERR    0x00000008  // Data Error
-#define USB_RXCSRL13_OVER       0x00000004  // Overrun
-#define USB_RXCSRL13_ERROR      0x00000004  // Error
-#define USB_RXCSRL13_FULL       0x00000002  // FIFO Full
-#define USB_RXCSRL13_RXRDY      0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH13 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH13_AUTOCL     0x00000080  // Auto Clear
-#define USB_RXCSRH13_ISO        0x00000040  // Isochronous Transfers
-#define USB_RXCSRH13_AUTORQ     0x00000040  // Auto Request
-#define USB_RXCSRH13_DMAEN      0x00000020  // DMA Request Enable
-#define USB_RXCSRH13_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH13_PIDERR     0x00000010  // PID Error
-#define USB_RXCSRH13_DMAMOD     0x00000008  // DMA Request Mode
-#define USB_RXCSRH13_DTWE       0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH13_DT         0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT13
-// register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT13_COUNT_M   0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT13_COUNT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE13 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE13_SPEED_M    0x000000C0  // Operating Speed
-#define USB_TXTYPE13_SPEED_DFLT 0x00000000  // Default
-#define USB_TXTYPE13_SPEED_FULL 0x00000080  // Full
-#define USB_TXTYPE13_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE13_PROTO_M    0x00000030  // Protocol
-#define USB_TXTYPE13_PROTO_CTRL 0x00000000  // Control
-#define USB_TXTYPE13_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_TXTYPE13_PROTO_BULK 0x00000020  // Bulk
-#define USB_TXTYPE13_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE13_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL13
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL13_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL13_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL13_TXPOLL_S \
-                                0
-#define USB_TXINTERVAL13_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE13 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE13_SPEED_M    0x000000C0  // Operating Speed
-#define USB_RXTYPE13_SPEED_DFLT 0x00000000  // Default
-#define USB_RXTYPE13_SPEED_FULL 0x00000080  // Full
-#define USB_RXTYPE13_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE13_PROTO_M    0x00000030  // Protocol
-#define USB_RXTYPE13_PROTO_CTRL 0x00000000  // Control
-#define USB_RXTYPE13_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_RXTYPE13_PROTO_BULK 0x00000020  // Bulk
-#define USB_RXTYPE13_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE13_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL13
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL13_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL13_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL13_TXPOLL_S \
-                                0
-#define USB_RXINTERVAL13_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP14 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_TXMAXP14_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL14 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL14_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL14_CLRDT      0x00000040  // Clear Data Toggle
-#define USB_TXCSRL14_STALLED    0x00000020  // Endpoint Stalled
-#define USB_TXCSRL14_STALL      0x00000010  // Send STALL
-#define USB_TXCSRL14_SETUP      0x00000010  // Setup Packet
-#define USB_TXCSRL14_FLUSH      0x00000008  // Flush FIFO
-#define USB_TXCSRL14_ERROR      0x00000004  // Error
-#define USB_TXCSRL14_UNDRN      0x00000004  // Underrun
-#define USB_TXCSRL14_FIFONE     0x00000002  // FIFO Not Empty
-#define USB_TXCSRL14_TXRDY      0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH14 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH14_AUTOSET    0x00000080  // Auto Set
-#define USB_TXCSRH14_ISO        0x00000040  // Isochronous Transfers
-#define USB_TXCSRH14_MODE       0x00000020  // Mode
-#define USB_TXCSRH14_DMAEN      0x00000010  // DMA Request Enable
-#define USB_TXCSRH14_FDT        0x00000008  // Force Data Toggle
-#define USB_TXCSRH14_DMAMOD     0x00000004  // DMA Request Mode
-#define USB_TXCSRH14_DTWE       0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH14_DT         0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP14 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_RXMAXP14_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL14 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL14_CLRDT      0x00000080  // Clear Data Toggle
-#define USB_RXCSRL14_STALLED    0x00000040  // Endpoint Stalled
-#define USB_RXCSRL14_REQPKT     0x00000020  // Request Packet
-#define USB_RXCSRL14_STALL      0x00000020  // Send STALL
-#define USB_RXCSRL14_FLUSH      0x00000010  // Flush FIFO
-#define USB_RXCSRL14_DATAERR    0x00000008  // Data Error
-#define USB_RXCSRL14_NAKTO      0x00000008  // NAK Timeout
-#define USB_RXCSRL14_OVER       0x00000004  // Overrun
-#define USB_RXCSRL14_ERROR      0x00000004  // Error
-#define USB_RXCSRL14_FULL       0x00000002  // FIFO Full
-#define USB_RXCSRL14_RXRDY      0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH14 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH14_AUTOCL     0x00000080  // Auto Clear
-#define USB_RXCSRH14_AUTORQ     0x00000040  // Auto Request
-#define USB_RXCSRH14_ISO        0x00000040  // Isochronous Transfers
-#define USB_RXCSRH14_DMAEN      0x00000020  // DMA Request Enable
-#define USB_RXCSRH14_PIDERR     0x00000010  // PID Error
-#define USB_RXCSRH14_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH14_DMAMOD     0x00000008  // DMA Request Mode
-#define USB_RXCSRH14_DTWE       0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH14_DT         0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT14
-// register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT14_COUNT_M   0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT14_COUNT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE14 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE14_SPEED_M    0x000000C0  // Operating Speed
-#define USB_TXTYPE14_SPEED_DFLT 0x00000000  // Default
-#define USB_TXTYPE14_SPEED_FULL 0x00000080  // Full
-#define USB_TXTYPE14_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE14_PROTO_M    0x00000030  // Protocol
-#define USB_TXTYPE14_PROTO_CTRL 0x00000000  // Control
-#define USB_TXTYPE14_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_TXTYPE14_PROTO_BULK 0x00000020  // Bulk
-#define USB_TXTYPE14_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE14_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL14
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL14_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL14_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL14_TXPOLL_S \
-                                0
-#define USB_TXINTERVAL14_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE14 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE14_SPEED_M    0x000000C0  // Operating Speed
-#define USB_RXTYPE14_SPEED_DFLT 0x00000000  // Default
-#define USB_RXTYPE14_SPEED_FULL 0x00000080  // Full
-#define USB_RXTYPE14_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE14_PROTO_M    0x00000030  // Protocol
-#define USB_RXTYPE14_PROTO_CTRL 0x00000000  // Control
-#define USB_RXTYPE14_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_RXTYPE14_PROTO_BULK 0x00000020  // Bulk
-#define USB_RXTYPE14_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE14_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL14
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL14_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL14_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL14_TXPOLL_S \
-                                0
-#define USB_RXINTERVAL14_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP15 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_TXMAXP15_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL15 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL15_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL15_CLRDT      0x00000040  // Clear Data Toggle
-#define USB_TXCSRL15_STALLED    0x00000020  // Endpoint Stalled
-#define USB_TXCSRL15_SETUP      0x00000010  // Setup Packet
-#define USB_TXCSRL15_STALL      0x00000010  // Send STALL
-#define USB_TXCSRL15_FLUSH      0x00000008  // Flush FIFO
-#define USB_TXCSRL15_UNDRN      0x00000004  // Underrun
-#define USB_TXCSRL15_ERROR      0x00000004  // Error
-#define USB_TXCSRL15_FIFONE     0x00000002  // FIFO Not Empty
-#define USB_TXCSRL15_TXRDY      0x00000001  // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH15 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH15_AUTOSET    0x00000080  // Auto Set
-#define USB_TXCSRH15_ISO        0x00000040  // Isochronous Transfers
-#define USB_TXCSRH15_MODE       0x00000020  // Mode
-#define USB_TXCSRH15_DMAEN      0x00000010  // DMA Request Enable
-#define USB_TXCSRH15_FDT        0x00000008  // Force Data Toggle
-#define USB_TXCSRH15_DMAMOD     0x00000004  // DMA Request Mode
-#define USB_TXCSRH15_DTWE       0x00000002  // Data Toggle Write Enable
-#define USB_TXCSRH15_DT         0x00000001  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP15 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload
-#define USB_RXMAXP15_MAXLOAD_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL15 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL15_CLRDT      0x00000080  // Clear Data Toggle
-#define USB_RXCSRL15_STALLED    0x00000040  // Endpoint Stalled
-#define USB_RXCSRL15_STALL      0x00000020  // Send STALL
-#define USB_RXCSRL15_REQPKT     0x00000020  // Request Packet
-#define USB_RXCSRL15_FLUSH      0x00000010  // Flush FIFO
-#define USB_RXCSRL15_DATAERR    0x00000008  // Data Error
-#define USB_RXCSRL15_NAKTO      0x00000008  // NAK Timeout
-#define USB_RXCSRL15_ERROR      0x00000004  // Error
-#define USB_RXCSRL15_OVER       0x00000004  // Overrun
-#define USB_RXCSRL15_FULL       0x00000002  // FIFO Full
-#define USB_RXCSRL15_RXRDY      0x00000001  // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH15 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH15_AUTOCL     0x00000080  // Auto Clear
-#define USB_RXCSRH15_AUTORQ     0x00000040  // Auto Request
-#define USB_RXCSRH15_ISO        0x00000040  // Isochronous Transfers
-#define USB_RXCSRH15_DMAEN      0x00000020  // DMA Request Enable
-#define USB_RXCSRH15_PIDERR     0x00000010  // PID Error
-#define USB_RXCSRH15_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH15_DMAMOD     0x00000008  // DMA Request Mode
-#define USB_RXCSRH15_DTWE       0x00000004  // Data Toggle Write Enable
-#define USB_RXCSRH15_DT         0x00000002  // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT15
-// register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT15_COUNT_M   0x00001FFF  // Receive Packet Count
-#define USB_RXCOUNT15_COUNT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE15 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE15_SPEED_M    0x000000C0  // Operating Speed
-#define USB_TXTYPE15_SPEED_DFLT 0x00000000  // Default
-#define USB_TXTYPE15_SPEED_FULL 0x00000080  // Full
-#define USB_TXTYPE15_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE15_PROTO_M    0x00000030  // Protocol
-#define USB_TXTYPE15_PROTO_CTRL 0x00000000  // Control
-#define USB_TXTYPE15_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_TXTYPE15_PROTO_BULK 0x00000020  // Bulk
-#define USB_TXTYPE15_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_TXTYPE15_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL15
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL15_TXPOLL_M \
-                                0x000000FF  // TX Polling
-#define USB_TXINTERVAL15_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_TXINTERVAL15_NAKLMT_S \
-                                0
-#define USB_TXINTERVAL15_TXPOLL_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE15 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE15_SPEED_M    0x000000C0  // Operating Speed
-#define USB_RXTYPE15_SPEED_DFLT 0x00000000  // Default
-#define USB_RXTYPE15_SPEED_FULL 0x00000080  // Full
-#define USB_RXTYPE15_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE15_PROTO_M    0x00000030  // Protocol
-#define USB_RXTYPE15_PROTO_CTRL 0x00000000  // Control
-#define USB_RXTYPE15_PROTO_ISOC 0x00000010  // Isochronous
-#define USB_RXTYPE15_PROTO_BULK 0x00000020  // Bulk
-#define USB_RXTYPE15_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number
-#define USB_RXTYPE15_TEP_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL15
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL15_TXPOLL_M \
-                                0x000000FF  // RX Polling
-#define USB_RXINTERVAL15_NAKLMT_M \
-                                0x000000FF  // NAK Limit
-#define USB_RXINTERVAL15_TXPOLL_S \
-                                0
-#define USB_RXINTERVAL15_NAKLMT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT1_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT2_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT3_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT4_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT5_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT6_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT7_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT8_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT9_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT10_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT10_COUNT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT11_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT11_COUNT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT12_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT12_COUNT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT13_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT13_COUNT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT14_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT14_COUNT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT15_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count
-#define USB_RQPKTCOUNT15_COUNT_S \
-                                0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_RXDPKTBUFDIS_EP15   0x00008000  // EP15 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP14   0x00004000  // EP14 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP13   0x00002000  // EP13 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP12   0x00001000  // EP12 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP11   0x00000800  // EP11 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP10   0x00000400  // EP10 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP9    0x00000200  // EP9 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP8    0x00000100  // EP8 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
-                                            // Disable
-#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
-                                            // Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_TXDPKTBUFDIS_EP15   0x00008000  // EP15 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP14   0x00004000  // EP14 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP13   0x00002000  // EP13 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP12   0x00001000  // EP12 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP11   0x00000800  // EP11 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP10   0x00000400  // EP10 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP9    0x00000200  // EP9 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP8    0x00000100  // EP8 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
-                                            // Disable
-#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
-                                            // Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPC register.
-//
-//*****************************************************************************
-#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
-#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
-#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
-#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
-#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
-#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
-#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
-#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
-#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
-#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
-                                            // Configuration
-#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
-#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
-#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
-#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCRIS register.
-//
-//*****************************************************************************
-#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCIM register.
-//
-//*****************************************************************************
-#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCISC register.
-//
-//*****************************************************************************
-#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
-                                            // and Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRRIS register.
-//
-//*****************************************************************************
-#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRIM register.
-//
-//*****************************************************************************
-#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRISC register.
-//
-//*****************************************************************************
-#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
-                                            // Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_GPCS register.
-//
-//*****************************************************************************
-#define USB_GPCS_DEVMODOTG      0x00000002  // Enable Device Mode
-#define USB_GPCS_DEVMOD         0x00000001  // Device Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDC register.
-//
-//*****************************************************************************
-#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCRIS register.
-//
-//*****************************************************************************
-#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCIM register.
-//
-//*****************************************************************************
-#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCISC register.
-//
-//*****************************************************************************
-#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
-                                            // Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IDVRIS register.
-//
-//*****************************************************************************
-#define USB_IDVRIS_ID           0x00000001  // ID Valid Detect Raw Interrupt
-                                            // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IDVIM register.
-//
-//*****************************************************************************
-#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IDVISC register.
-//
-//*****************************************************************************
-#define USB_IDVISC_ID           0x00000001  // ID Valid Detect Interrupt Status
-                                            // and Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMASEL register.
-//
-//*****************************************************************************
-#define USB_DMASEL_DMACTX_M     0x00F00000  // DMA C TX Select
-#define USB_DMASEL_DMACRX_M     0x000F0000  // DMA C RX Select
-#define USB_DMASEL_DMABTX_M     0x0000F000  // DMA B TX Select
-#define USB_DMASEL_DMABRX_M     0x00000F00  // DMA B RX Select
-#define USB_DMASEL_DMAATX_M     0x000000F0  // DMA A TX Select
-#define USB_DMASEL_DMAARX_M     0x0000000F  // DMA A RX Select
-#define USB_DMASEL_DMACTX_S     20
-#define USB_DMASEL_DMACRX_S     16
-#define USB_DMASEL_DMABTX_S     12
-#define USB_DMASEL_DMABRX_S     8
-#define USB_DMASEL_DMAATX_S     4
-#define USB_DMASEL_DMAARX_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_PP register.
-//
-//*****************************************************************************
-#define USB_PP_ECNT_M           0x0000FF00  // Endpoint Count
-#define USB_PP_USB_M            0x000000C0  // USB Capability
-#define USB_PP_USB_DEVICE       0x00000040  // DEVICE
-#define USB_PP_USB_HOSTDEVICE   0x00000080  // HOST
-#define USB_PP_USB_OTG          0x000000C0  // OTG
-#define USB_PP_PHY              0x00000010  // PHY Present
-#define USB_PP_TYPE_M           0x0000000F  // Controller Type
-#define USB_PP_TYPE_0           0x00000000  // The first-generation USB
-                                            // controller
-#define USB_PP_ECNT_S           8
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// USB_O_TXFIFOADD register.
-//
-//*****************************************************************************
-#define USB_TXFIFOADD_ADDR_2048 0x00000009  // 2048
-#define USB_TXFIFOADD_ADDR_1024 0x00000008  // 1024
-#define USB_TXFIFOADD_ADDR_512  0x00000007  // 512
-#define USB_TXFIFOADD_ADDR_256  0x00000006  // 256
-#define USB_TXFIFOADD_ADDR_128  0x00000005  // 128
-#define USB_TXFIFOADD_ADDR_64   0x00000004  // 64
-#define USB_TXFIFOADD_ADDR_32   0x00000003  // 32
-#define USB_TXFIFOADD_ADDR_16   0x00000002  // 16
-#define USB_TXFIFOADD_ADDR_8    0x00000001  // 8
-#define USB_TXFIFOADD_ADDR_0    0x00000000  // 0
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// USB_O_RXFIFOADD register.
-//
-//*****************************************************************************
-#define USB_RXFIFOADD_ADDR_2048 0x00000009  // 2048
-#define USB_RXFIFOADD_ADDR_1024 0x00000008  // 1024
-#define USB_RXFIFOADD_ADDR_512  0x00000007  // 512
-#define USB_RXFIFOADD_ADDR_256  0x00000006  // 256
-#define USB_RXFIFOADD_ADDR_128  0x00000005  // 128
-#define USB_RXFIFOADD_ADDR_64   0x00000004  // 64
-#define USB_RXFIFOADD_ADDR_32   0x00000003  // 32
-#define USB_RXFIFOADD_ADDR_16   0x00000002  // 16
-#define USB_RXFIFOADD_ADDR_8    0x00000001  // 8
-#define USB_RXFIFOADD_ADDR_0    0x00000000  // 0
-
-#endif
-
-#endif // __HW_USB_H__
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.c b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.c
deleted file mode 100644
index a58927013e..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.c
+++ /dev/null
@@ -1,214 +0,0 @@
-//###########################################################################
-//
-// FILE:   cmdline.c
-//
-// TITLE:  Functions to help with processing command lines.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-//*****************************************************************************
-//
-//! \addtogroup cmdline_api
-//! @{
-//
-//*****************************************************************************
-
-//
-// Included Files
-//
-#include <stdint.h>
-#include <stdbool.h>
-#include <string.h>
-#include "utils/cmdline.h"
-
-//
-// Defines the maximum number of arguments that can be parsed.
-//
-#ifndef CMDLINE_MAX_ARGS
-#define CMDLINE_MAX_ARGS        8
-#endif
-
-//
-// An array to hold the pointers to the command line arguments.
-//
-static char *g_ppcArgv[CMDLINE_MAX_ARGS + 1];
-
-//*****************************************************************************
-//
-//! Process a command line string into arguments and execute the command.
-//!
-//! \param pcCmdLine points to a string that contains a command line that was
-//! obtained by an application by some means.
-//!
-//! This function will take the supplied command line string and break it up
-//! into individual arguments.  The first argument is treated as a command and
-//! is searched for in the command table.  If the command is found, then the
-//! command function is called and all of the command line arguments are passed
-//! in the normal argc, argv form.
-//!
-//! The command table is contained in an array named <tt>g_psCmdTable</tt>
-//! containing <tt>tCmdLineEntry</tt> structures which must be provided by the
-//! application.  The array must be terminated with an entry whose \b pcCmd
-//! field contains a NULL pointer.
-//!
-//! \return Returns \b CMDLINE_BAD_CMD if the command is not found,
-//! \b CMDLINE_TOO_MANY_ARGS if there are more arguments than can be parsed.
-//! Otherwise it returns the code that was returned by the command function.
-//
-//*****************************************************************************
-int
-CmdLineProcess(char *pcCmdLine)
-{
-    char *pcChar;
-    uint_fast8_t ui8Argc;
-    bool bFindArg = true;
-    tCmdLineEntry *psCmdEntry;
-
-    //
-    // Initialize the argument counter, and point to the beginning of the
-    // command line string.
-    //
-    ui8Argc = 0;
-    pcChar = pcCmdLine;
-
-    //
-    // Advance through the command line until a zero character is found.
-    //
-    while(*pcChar)
-    {
-        //
-        // If there is a space, then replace it with a zero, and set the flag
-        // to search for the next argument.
-        //
-        if(*pcChar == ' ')
-        {
-            *pcChar = 0;
-            bFindArg = true;
-        }
-
-        //
-        // Otherwise it is not a space, so it must be a character that is part
-        // of an argument.
-        //
-        else
-        {
-            //
-            // If bFindArg is set, then that means we are looking for the start
-            // of the next argument.
-            //
-            if(bFindArg)
-            {
-                //
-                // As long as the maximum number of arguments has not been
-                // reached, then save the pointer to the start of this new arg
-                // in the argv array, and increment the count of args, argc.
-                //
-                if(ui8Argc < CMDLINE_MAX_ARGS)
-                {
-                    g_ppcArgv[ui8Argc] = pcChar;
-                    ui8Argc++;
-                    bFindArg = false;
-                }
-
-                //
-                // The maximum number of arguments has been reached so return
-                // the error.
-                //
-                else
-                {
-                    return(CMDLINE_TOO_MANY_ARGS);
-                }
-            }
-        }
-
-        //
-        // Advance to the next character in the command line.
-        //
-        pcChar++;
-    }
-
-    //
-    // If one or more arguments was found, then process the command.
-    //
-    if(ui8Argc)
-    {
-        //
-        // Start at the beginning of the command table, to look for a matching
-        // command.
-        //
-        psCmdEntry = &g_psCmdTable[0];
-
-        //
-        // Search through the command table until a null command string is
-        // found, which marks the end of the table.
-        //
-        while(psCmdEntry->pcCmd)
-        {
-            //
-            // If this command entry command string matches argv[0], then call
-            // the function for this command, passing the command line
-            // arguments.
-            //
-            if(!strcmp(g_ppcArgv[0], psCmdEntry->pcCmd))
-            {
-                return(psCmdEntry->pfnCmd(ui8Argc, g_ppcArgv));
-            }
-
-            //
-            // Not found, so advance to the next entry.
-            //
-            psCmdEntry++;
-        }
-    }
-
-    //
-    // Fall through to here means that no matching command was found, so return
-    // an error.
-    //
-    return(CMDLINE_BAD_CMD);
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
-
-//
-// End of file
-//
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.h b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.h
deleted file mode 100644
index 47c3fa1b23..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.h
+++ /dev/null
@@ -1,143 +0,0 @@
-//###########################################################################
-//
-// FILE:   cmdline.h
-//
-// TITLE:  Prototypes for command line processing functions.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __CMDLINE_H__
-#define __CMDLINE_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-//! \addtogroup cmdline_api
-//! @{
-//
-//*****************************************************************************
-
-//
-//! Defines the value that is returned if the command is not found.
-//
-#define CMDLINE_BAD_CMD         (-1)
-
-//
-//! Defines the value that is returned if there are too many arguments.
-//
-#define CMDLINE_TOO_MANY_ARGS   (-2)
-
-//
-//! Defines the value that is returned if there are too few arguments.
-//
-#define CMDLINE_TOO_FEW_ARGS   (-3)
-
-//
-//! Defines the value that is returned if an argument is invalid.
-//
-#define CMDLINE_INVALID_ARG   (-4)
-
-//
-// Command line function callback type.
-//
-typedef int (*pfnCmdLine)(int argc, char *argv[]);
-
-//
-//! Structure for an entry in the command list table.
-//
-typedef struct
-{
-    //
-    //! A pointer to a string containing the name of the command.
-    //
-    const char *pcCmd;
-
-    //
-    //! A function pointer to the implementation of the command.
-    //
-    pfnCmdLine pfnCmd;
-
-    //
-    //! A pointer to a string of brief help text for the command.
-    //
-    const char *pcHelp;
-}
-tCmdLineEntry;
-
-//
-//! This is the command table that must be provided by the application.  The
-//! last element of the array must be a structure whose pcCmd field contains
-//! a NULL pointer.
-//
-extern tCmdLineEntry g_psCmdTable[];
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
-
-//
-// Function Prototypes
-//
-extern int CmdLineProcess(char *pcCmdLine);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __CMDLINE_H__
-
-//
-// End of file
-//
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.c b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.c
deleted file mode 100644
index 07354f184d..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.c
+++ /dev/null
@@ -1,1773 +0,0 @@
-//###########################################################################
-//
-// FILE:   uartstdio.c
-//
-// TITLE:  Utility driver to provide simple UART console functions.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-//
-// Included Files
-//
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdarg.h>
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_types.h"
-#include "inc/hw_uart.h"
-#include "driverlib/debug.h"
-#include "driverlib/interrupt.h"
-#include "driverlib/rom.h"
-#include "driverlib/rom_map.h"
-#include "driverlib/sysctl.h"
-#include "driverlib/uart.h"
-#include "utils/uartstdio.h"
-
-//*****************************************************************************
-//
-//! \addtogroup uartstdio_api
-//! @{
-//
-//*****************************************************************************
-
-//
-// If buffered mode is defined, set aside RX and TX buffers and read/write
-// pointers to control them.
-//
-#ifdef UART_BUFFERED
-
-//
-// This global controls whether or not we are echoing characters back to the
-// transmitter.  By default, echo is enabled but if using this module as a
-// convenient method of implementing a buffered serial interface over which
-// you will be running an application protocol, you are likely to want to
-// disable echo by calling UARTEchoSet(false).
-//
-static bool g_bDisableEcho;
-
-//
-// Output ring buffer.  Buffer is full if g_ui32UARTTxReadIndex is one ahead of
-// g_ui32UARTTxWriteIndex.  Buffer is empty if the two indices are the same.
-//
-static unsigned char g_pcUARTTxBuffer[UART_TX_BUFFER_SIZE];
-static volatile uint32_t g_ui32UARTTxWriteIndex = 0;
-static volatile uint32_t g_ui32UARTTxReadIndex = 0;
-
-//
-// Input ring buffer.  Buffer is full if g_ui32UARTTxReadIndex is one ahead of
-// g_ui32UARTTxWriteIndex.  Buffer is empty if the two indices are the same.
-//
-static unsigned char g_pcUARTRxBuffer[UART_RX_BUFFER_SIZE];
-static volatile uint32_t g_ui32UARTRxWriteIndex = 0;
-static volatile uint32_t g_ui32UARTRxReadIndex = 0;
-
-//
-// Macros to determine number of free and used bytes in the transmit buffer.
-//
-#define TX_BUFFER_USED          (GetBufferCount(&g_ui32UARTTxReadIndex,  \
-                                                &g_ui32UARTTxWriteIndex, \
-                                                UART_TX_BUFFER_SIZE))
-#define TX_BUFFER_FREE          (UART_TX_BUFFER_SIZE - TX_BUFFER_USED)
-#define TX_BUFFER_EMPTY         (IsBufferEmpty(&g_ui32UARTTxReadIndex,   \
-                                               &g_ui32UARTTxWriteIndex))
-#define TX_BUFFER_FULL          (IsBufferFull(&g_ui32UARTTxReadIndex,  \
-                                              &g_ui32UARTTxWriteIndex, \
-                                              UART_TX_BUFFER_SIZE))
-#define ADVANCE_TX_BUFFER_INDEX(Index) \
-                                (Index) = ((Index) + 1) % UART_TX_BUFFER_SIZE
-
-//
-// Macros to determine number of free and used bytes in the receive buffer.
-//
-#define RX_BUFFER_USED          (GetBufferCount(&g_ui32UARTRxReadIndex,  \
-                                                &g_ui32UARTRxWriteIndex, \
-                                                UART_RX_BUFFER_SIZE))
-#define RX_BUFFER_FREE          (UART_RX_BUFFER_SIZE - RX_BUFFER_USED)
-#define RX_BUFFER_EMPTY         (IsBufferEmpty(&g_ui32UARTRxReadIndex,   \
-                                               &g_ui32UARTRxWriteIndex))
-#define RX_BUFFER_FULL          (IsBufferFull(&g_ui32UARTRxReadIndex,  \
-                                              &g_ui32UARTRxWriteIndex, \
-                                              UART_RX_BUFFER_SIZE))
-#define ADVANCE_RX_BUFFER_INDEX(Index) \
-                                (Index) = ((Index) + 1) % UART_RX_BUFFER_SIZE
-#endif
-
-//
-// The base address of the chosen UART.
-//
-static uint32_t g_ui32Base = 0;
-
-//
-// A mapping from an integer between 0 and 15 to its ASCII character
-// equivalent.
-//
-static const char * const g_pcHex = "0123456789abcdef";
-
-//
-// The list of possible base addresses for the console UART.
-//
-static const uint32_t g_ui32UARTBase[4] =
-{
-    UARTA_BASE, UARTB_BASE, UARTC_BASE, UARTD_BASE
-};
-
-#ifdef UART_BUFFERED
-//
-// The list of possible interrupts for the console UART.
-//
-static const uint32_t g_ui32UARTInt[3] =
-{
-    INT_UART0, INT_UART1, INT_UART2
-};
-
-//
-// The port number in use.
-//
-static uint32_t g_ui32PortNum;
-#endif
-
-//
-// The list of UART peripherals.
-//
-static const uint32_t g_ui32UARTPeriph[3] =
-{
-    SYSCTL_PERIPH_SCI1, SYSCTL_PERIPH_SCI2, SYSCTL_PERIPH_SCI3
-};
-
-//*****************************************************************************
-//
-//! Determines whether the ring buffer whose pointers and size are provided
-//! is full or not.
-//!
-//! \param pui32Read points to the read index for the buffer.
-//! \param pui32Write points to the write index for the buffer.
-//! \param ui32Size is the size of the buffer in bytes.
-//!
-//! This function is used to determine whether or not a given ring buffer is
-//! full.  The structure of the code is specifically to ensure that we do not
-//! see warnings from the compiler related to the order of volatile accesses
-//! being undefined.
-//!
-//! \return Returns \b true if the buffer is full or \b false otherwise.
-//
-//*****************************************************************************
-#ifdef UART_BUFFERED
-static bool
-IsBufferFull(volatile uint32_t *pui32Read,
-             volatile uint32_t *pui32Write, uint32_t ui32Size)
-{
-    uint32_t ui32Write;
-    uint32_t ui32Read;
-
-    ui32Write = *pui32Write;
-    ui32Read = *pui32Read;
-
-    return((((ui32Write + 1) % ui32Size) == ui32Read) ? true : false);
-}
-#endif
-
-//*****************************************************************************
-//
-//! Determines whether the ring buffer whose pointers and size are provided
-//! is empty or not.
-//!
-//! \param pui32Read points to the read index for the buffer.
-//! \param pui32Write points to the write index for the buffer.
-//!
-//! This function is used to determine whether or not a given ring buffer is
-//! empty.  The structure of the code is specifically to ensure that we do not
-//! see warnings from the compiler related to the order of volatile accesses
-//! being undefined.
-//!
-//! \return Returns \b true if the buffer is empty or \b false otherwise.
-//
-//*****************************************************************************
-#ifdef UART_BUFFERED
-static bool
-IsBufferEmpty(volatile uint32_t *pui32Read,
-              volatile uint32_t *pui32Write)
-{
-    uint32_t ui32Write;
-    uint32_t ui32Read;
-
-    ui32Write = *pui32Write;
-    ui32Read = *pui32Read;
-
-    return((ui32Write == ui32Read) ? true : false);
-}
-#endif
-
-//*****************************************************************************
-//
-//! Determines the number of bytes of data contained in a ring buffer.
-//!
-//! \param pui32Read points to the read index for the buffer.
-//! \param pui32Write points to the write index for the buffer.
-//! \param ui32Size is the size of the buffer in bytes.
-//!
-//! This function is used to determine how many bytes of data a given ring
-//! buffer currently contains.  The structure of the code is specifically to
-//! ensure that we do not see warnings from the compiler related to the order
-//! of volatile accesses being undefined.
-//!
-//! \return Returns the number of bytes of data currently in the buffer.
-//
-//*****************************************************************************
-#ifdef UART_BUFFERED
-static uint32_t
-GetBufferCount(volatile uint32_t *pui32Read,
-               volatile uint32_t *pui32Write, uint32_t ui32Size)
-{
-    uint32_t ui32Write;
-    uint32_t ui32Read;
-
-    ui32Write = *pui32Write;
-    ui32Read = *pui32Read;
-
-    return((ui32Write >= ui32Read) ? (ui32Write - ui32Read) :
-           (ui32Size - (ui32Read - ui32Write)));
-}
-#endif
-
-//*****************************************************************************
-//
-// Take as many bytes from the transmit buffer as we have space for and move
-// them into the UART transmit FIFO.
-//
-//*****************************************************************************
-#ifdef UART_BUFFERED
-static void
-UARTPrimeTransmit(uint32_t ui32Base)
-{
-    //
-    // Do we have any data to transmit?
-    //
-    if(!TX_BUFFER_EMPTY)
-    {
-        //
-        // Disable the UART interrupt.  If we don't do this there is a race
-        // condition which can cause the read index to be corrupted.
-        //
-        MAP_IntDisable(g_ui32UARTInt[g_ui32PortNum]);
-
-        //
-        // Yes - take some characters out of the transmit buffer and feed
-        // them to the UART transmit FIFO.
-        //
-        while(MAP_UARTSpaceAvail(ui32Base) && !TX_BUFFER_EMPTY)
-        {
-            MAP_UARTCharPutNonBlocking(ui32Base,
-                                      g_pcUARTTxBuffer[g_ui32UARTTxReadIndex]);
-            ADVANCE_TX_BUFFER_INDEX(g_ui32UARTTxReadIndex);
-        }
-
-        //
-        // Reenable the UART interrupt.
-        //
-        MAP_IntEnable(g_ui32UARTInt[g_ui32PortNum]);
-    }
-}
-#endif
-
-//*****************************************************************************
-//
-//! Configures the UART console.
-//!
-//! \param ui32PortNum is the number of UART port to use for the serial console
-//! (0-2)
-//! \param ui32Baud is the bit rate that the UART is to be configured to use.
-//! \param ui32SrcClock is the frequency of the source clock for the UART
-//! module.
-//!
-//! This function will configure the specified serial port to be used as a
-//! serial console.  The serial parameters are set to the baud rate
-//! specified by the \e ui32Baud parameter and use 8 bit, no parity, and 1 stop
-//! bit.
-//!
-//! This function must be called prior to using any of the other UART console
-//! functions: UARTprintf() or UARTgets().  This function assumes that the
-//! caller has previously configured the relevant UART pins for operation as a
-//! UART rather than as GPIOs.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTStdioConfig(uint32_t ui32PortNum, uint32_t ui32Baud, uint32_t ui32SrcClock)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ui32PortNum == 0) || (ui32PortNum == 1) ||
-           (ui32PortNum == 2));
-
-#ifdef UART_BUFFERED
-    //
-    // In buffered mode, we only allow a single instance to be opened.
-    //
-    ASSERT(g_ui32Base == 0);
-#endif
-
-    //
-    // Check to make sure the UART peripheral is present.
-    //
-    if(!MAP_SysCtlPeripheralPresent(g_ui32UARTPeriph[ui32PortNum]))
-    {
-        return;
-    }
-
-    //
-    // Select the base address of the UART.
-    //
-    g_ui32Base = g_ui32UARTBase[ui32PortNum];
-
-    //
-    // Enable the UART peripheral for use.
-    //
-    MAP_SysCtlPeripheralEnable(g_ui32UARTPeriph[ui32PortNum]);
-
-    //
-    // Configure the UART for 115200, n, 8, 1
-    //
-    MAP_UARTConfigSetExpClk(g_ui32Base, ui32SrcClock, ui32Baud,
-                            (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
-                             UART_CONFIG_WLEN_8));
-
-#ifdef UART_BUFFERED
-    //
-    // Set the UART to interrupt whenever the TX FIFO is almost empty or
-    // when any character is received.
-    //
-    MAP_UARTFIFOLevelSet(g_ui32Base, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
-
-    //
-    // Flush both the buffers.
-    //
-    UARTFlushRx();
-    UARTFlushTx(true);
-
-    //
-    // Remember which interrupt we are dealing with.
-    //
-    g_ui32PortNum = ui32PortNum;
-
-    //
-    // We are configured for buffered output so enable the master interrupt
-    // for this UART and the receive interrupts.  We don't actually enable the
-    // transmit interrupt in the UART itself until some data has been placed
-    // in the transmit buffer.
-    //
-    MAP_UARTIntDisable(g_ui32Base, 0xFFFFFFFF);
-    MAP_UARTIntEnable(g_ui32Base, UART_INT_RX | UART_INT_RT);
-    MAP_IntEnable(g_ui32UARTInt[ui32PortNum]);
-#endif
-
-    //
-    // Enable the UART operation.
-    //
-    MAP_UARTEnable(g_ui32Base);
-}
-
-//*****************************************************************************
-//
-//! Writes a string of characters to the UART output.
-//!
-//! \param pcBuf points to a buffer containing the string to transmit.
-//! \param ui32Len is the length of the string to transmit.
-//!
-//! This function will transmit the string to the UART output.  The number of
-//! characters transmitted is determined by the \e ui32Len parameter.  This
-//! function does no interpretation or translation of any characters.  Since
-//! the output is sent to a UART, any LF (/n) characters encountered will be
-//! replaced with a CRLF pair.
-//!
-//! Besides using the \e ui32Len parameter to stop transmitting the string, if
-//! a null character (0) is encountered, then no more characters will be
-//! transmitted and the function will return.
-//!
-//! In non-buffered mode, this function is blocking and will not return until
-//! all the characters have been written to the output FIFO.  In buffered mode,
-//! the characters are written to the UART transmit buffer and the call returns
-//! immediately.  If insufficient space remains in the transmit buffer,
-//! additional characters are discarded.
-//!
-//! \return Returns the count of characters written.
-//
-//*****************************************************************************
-int
-UARTwrite(const char *pcBuf, uint32_t ui32Len)
-{
-#ifdef UART_BUFFERED
-    unsigned int uIdx;
-
-    //
-    // Check for valid arguments.
-    //
-    ASSERT(pcBuf != 0);
-    ASSERT(g_ui32Base != 0);
-
-    //
-    // Send the characters
-    //
-    for(uIdx = 0; uIdx < ui32Len; uIdx++)
-    {
-        //
-        // If the character to the UART is \n, then add a \r before it so that
-        // \n is translated to \n\r in the output.
-        //
-        if(pcBuf[uIdx] == '\n')
-        {
-            if(!TX_BUFFER_FULL)
-            {
-                g_pcUARTTxBuffer[g_ui32UARTTxWriteIndex] = '\r';
-                ADVANCE_TX_BUFFER_INDEX(g_ui32UARTTxWriteIndex);
-            }
-            else
-            {
-                //
-                // Buffer is full - discard remaining characters and return.
-                //
-                break;
-            }
-        }
-
-        //
-        // Send the character to the UART output.
-        //
-        if(!TX_BUFFER_FULL)
-        {
-            g_pcUARTTxBuffer[g_ui32UARTTxWriteIndex] = pcBuf[uIdx];
-            ADVANCE_TX_BUFFER_INDEX(g_ui32UARTTxWriteIndex);
-        }
-        else
-        {
-            //
-            // Buffer is full - discard remaining characters and return.
-            //
-            break;
-        }
-    }
-
-    //
-    // If we have anything in the buffer, make sure that the UART is set
-    // up to transmit it.
-    //
-    if(!TX_BUFFER_EMPTY)
-    {
-        UARTPrimeTransmit(g_ui32Base);
-        MAP_UARTIntEnable(g_ui32Base, UART_INT_TX);
-    }
-
-    //
-    // Return the number of characters written.
-    //
-    return(uIdx);
-#else
-    unsigned int uIdx;
-
-    //
-    // Check for valid UART base address, and valid arguments.
-    //
-    ASSERT(g_ui32Base != 0);
-    ASSERT(pcBuf != 0);
-
-    //
-    // Send the characters
-    //
-    for(uIdx = 0; uIdx < ui32Len; uIdx++)
-    {
-        //
-        // If the character to the UART is \n, then add a \r before it so that
-        // \n is translated to \n\r in the output.
-        //
-        if(pcBuf[uIdx] == '\n')
-        {
-            MAP_UARTCharPut(g_ui32Base, '\r');
-        }
-
-        //
-        // Send the character to the UART output.
-        //
-        MAP_UARTCharPut(g_ui32Base, pcBuf[uIdx]);
-    }
-
-    //
-    // Return the number of characters written.
-    //
-    return(uIdx);
-#endif
-}
-
-//*****************************************************************************
-//
-//! A simple UART based get string function, with some line processing.
-//!
-//! \param pcBuf points to a buffer for the incoming string from the UART.
-//! \param ui32Len is the length of the buffer for storage of the string,
-//! including the trailing 0.
-//!
-//! This function will receive a string from the UART input and store the
-//! characters in the buffer pointed to by \e pcBuf.  The characters will
-//! continue to be stored until a termination character is received.  The
-//! termination characters are CR, LF, or ESC.  A CRLF pair is treated as a
-//! single termination character.  The termination characters are not stored in
-//! the string.  The string will be terminated with a 0 and the function will
-//! return.
-//!
-//! In both buffered and unbuffered modes, this function will block until
-//! a termination character is received.  If non-blocking operation is required
-//! in buffered mode, a call to UARTPeek() may be made to determine whether
-//! a termination character already exists in the receive buffer prior to
-//! calling UARTgets().
-//!
-//! Since the string will be null terminated, the user must ensure that the
-//! buffer is sized to allow for the additional null character.
-//!
-//! \return Returns the count of characters that were stored, not including
-//! the trailing 0.
-//
-//*****************************************************************************
-int
-UARTgets(char *pcBuf, uint32_t ui32Len)
-{
-#ifdef UART_BUFFERED
-    uint32_t ui32Count = 0;
-    int8_t cChar;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(pcBuf != 0);
-    ASSERT(ui32Len != 0);
-    ASSERT(g_ui32Base != 0);
-
-    //
-    // Adjust the length back by 1 to leave space for the trailing
-    // null terminator.
-    //
-    ui32Len--;
-
-    //
-    // Process characters until a newline is received.
-    //
-    while(1)
-    {
-        //
-        // Read the next character from the receive buffer.
-        //
-        if(!RX_BUFFER_EMPTY)
-        {
-            cChar = g_pcUARTRxBuffer[g_ui32UARTRxReadIndex];
-            ADVANCE_RX_BUFFER_INDEX(g_ui32UARTRxReadIndex);
-
-            //
-            // See if a newline or escape character was received.
-            //
-            if((cChar == '\r') || (cChar == '\n') || (cChar == 0x1b))
-            {
-                //
-                // Stop processing the input and end the line.
-                //
-                break;
-            }
-
-            //
-            // Process the received character as long as we are not at the end
-            // of the buffer.  If the end of the buffer has been reached then
-            // all additional characters are ignored until a newline is
-            // received.
-            //
-            if(ui32Count < ui32Len)
-            {
-                //
-                // Store the character in the caller supplied buffer.
-                //
-                pcBuf[ui32Count] = cChar;
-
-                //
-                // Increment the count of characters received.
-                //
-                ui32Count++;
-            }
-        }
-    }
-
-    //
-    // Add a null termination to the string.
-    //
-    pcBuf[ui32Count] = 0;
-
-    //
-    // Return the count of int8_ts in the buffer, not counting the trailing 0.
-    //
-    return(ui32Count);
-#else
-    uint32_t ui32Count = 0;
-    int8_t cChar;
-    static int8_t bLastWasCR = 0;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(pcBuf != 0);
-    ASSERT(ui32Len != 0);
-    ASSERT(g_ui32Base != 0);
-
-    //
-    // Adjust the length back by 1 to leave space for the trailing
-    // null terminator.
-    //
-    ui32Len--;
-
-    //
-    // Process characters until a newline is received.
-    //
-    while(1)
-    {
-        //
-        // Read the next character from the console.
-        //
-        cChar = MAP_UARTCharGet(g_ui32Base);
-
-        //
-        // See if the backspace key was pressed.
-        //
-        if(cChar == '\b')
-        {
-            //
-            // If there are any characters already in the buffer, then delete
-            // the last.
-            //
-            if(ui32Count)
-            {
-                //
-                // Rub out the previous character.
-                //
-                UARTwrite("\b \b", 3);
-
-                //
-                // Decrement the number of characters in the buffer.
-                //
-                ui32Count--;
-            }
-
-            //
-            // Skip ahead to read the next character.
-            //
-            continue;
-        }
-
-        //
-        // If this character is LF and last was CR, then just gobble up the
-        // character because the EOL processing was taken care of with the CR.
-        //
-        if((cChar == '\n') && bLastWasCR)
-        {
-            bLastWasCR = 0;
-            continue;
-        }
-
-        //
-        // See if a newline or escape character was received.
-        //
-        if((cChar == '\r') || (cChar == '\n') || (cChar == 0x1b))
-        {
-            //
-            // If the character is a CR, then it may be followed by a LF which
-            // should be paired with the CR.  So remember that a CR was
-            // received.
-            //
-            if(cChar == '\r')
-            {
-                bLastWasCR = 1;
-            }
-
-            //
-            // Stop processing the input and end the line.
-            //
-            break;
-        }
-
-        //
-        // Process the received character as long as we are not at the end of
-        // the buffer.  If the end of the buffer has been reached then all
-        // additional characters are ignored until a newline is received.
-        //
-        if(ui32Count < ui32Len)
-        {
-            //
-            // Store the character in the caller supplied buffer.
-            //
-            pcBuf[ui32Count] = cChar;
-
-            //
-            // Increment the count of characters received.
-            //
-            ui32Count++;
-
-            //
-            // Reflect the character back to the user.
-            //
-            MAP_UARTCharPut(g_ui32Base, cChar);
-        }
-    }
-
-    //
-    // Add a null termination to the string.
-    //
-    pcBuf[ui32Count] = 0;
-
-    //
-    // Send a CRLF pair to the terminal to end the line.
-    //
-    UARTwrite("\r\n", 2);
-
-    //
-    // Return the count of int8_ts in the buffer, not counting the trailing 0.
-    //
-    return(ui32Count);
-#endif
-}
-
-//*****************************************************************************
-//
-//! Read a single character from the UART, blocking if necessary.
-//!
-//! This function will receive a single character from the UART and store it at
-//! the supplied address.
-//!
-//! In both buffered and unbuffered modes, this function will block until a
-//! character is received.  If non-blocking operation is required in buffered
-//! mode, a call to UARTRxAvail() may be made to determine whether any
-//! characters are currently available for reading.
-//!
-//! \return Returns the character read.
-//
-//*****************************************************************************
-unsigned char
-UARTgetc(void)
-{
-#ifdef UART_BUFFERED
-    unsigned char cChar;
-
-    //
-    // Wait for a character to be received.
-    //
-    while(RX_BUFFER_EMPTY)
-    {
-        //
-        // Block waiting for a character to be received (if the buffer is
-        // currently empty).
-        //
-    }
-
-    //
-    // Read a character from the buffer.
-    //
-    cChar = g_pcUARTRxBuffer[g_ui32UARTRxReadIndex];
-    ADVANCE_RX_BUFFER_INDEX(g_ui32UARTRxReadIndex);
-
-    //
-    // Return the character to the caller.
-    //
-    return(cChar);
-#else
-    //
-    // Block until a character is received by the UART then return it to
-    // the caller.
-    //
-    return(MAP_UARTCharGet(g_ui32Base));
-#endif
-}
-
-//*****************************************************************************
-//
-//! A simple UART based vprintf function supporting \%c, \%d, \%p, \%s, \%u,
-//! \%x, and \%X.
-//!
-//! \param pcString is the format string.
-//! \param vaArgP is a variable argument list pointer whose content will depend
-//! upon the format string passed in \e pcString.
-//!
-//! This function is very similar to the C library <tt>vprintf()</tt> function.
-//! All of its output will be sent to the UART.  Only the following formatting
-//! characters are supported:
-//!
-//! - \%c to print a character
-//! - \%d or \%i to print a decimal value
-//! - \%l to print a long decimal value
-//! - \%s to print a string
-//! - \%u to print an unsigned decimal value
-//! - \%x to print a hexadecimal value using lower case letters
-//! - \%X to print a hexadecimal value using lower case letters (not upper case
-//! letters as would typically be used)
-//! - \%p to print a pointer as a hexadecimal value
-//! - \%\% to print out a \% character
-//!
-//! For \%s, \%d, \%i, \%u, \%p, \%x, and \%X, an optional number may reside
-//! between the \% and the format character, which specifies the minimum number
-//! of characters to use for that value; if preceded by a 0 then the extra
-//! characters will be filled with zeros instead of spaces.  For example,
-//! ``\%8d'' will use eight characters to print the decimal value with spaces
-//! added to reach eight; ``\%08d'' will use eight characters as well but will
-//! add zeroes instead of spaces.
-//!
-//! The type of the arguments in the variable arguments list must match the
-//! requirements of the format string.  For example, if an integer was passed
-//! where a string was expected, an error of some kind will most likely occur.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTvprintf(const char *pcString, va_list vaArgP)
-{
-    uint32_t ui32Idx, ui32Value, ui32Pos, ui32Count, ui32Base, ui32Neg;
-    char *pcStr, pcBuf[16], cFill;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(pcString != 0);
-
-    //
-    // Loop while there are more characters in the string.
-    //
-    while(*pcString)
-    {
-        //
-        // Find the first non-% character, or the end of the string.
-        //
-        for(ui32Idx = 0;
-            (pcString[ui32Idx] != '%') && (pcString[ui32Idx] != '\0');
-            ui32Idx++)
-        {
-        }
-
-        //
-        // Write this portion of the string.
-        //
-        UARTwrite(pcString, ui32Idx);
-
-        //
-        // Skip the portion of the string that was written.
-        //
-        pcString += ui32Idx;
-
-        //
-        // See if the next character is a %.
-        //
-        if(*pcString == '%')
-        {
-            //
-            // Skip the %.
-            //
-            pcString++;
-
-            //
-            // Set the digit count to zero, and the fill character to space
-            // (in other words, to the defaults).
-            //
-            ui32Count = 0;
-            cFill = ' ';
-
-            //
-            // It may be necessary to get back here to process more characters.
-            // Goto's aren't pretty, but effective.  I feel extremely dirty for
-            // using not one but two of the beasts.
-            //
-again:
-
-            //
-            // Determine how to handle the next character.
-            //
-            switch(*pcString++)
-            {
-                //
-                // Handle the digit characters.
-                //
-                case '0':
-                case '1':
-                case '2':
-                case '3':
-                case '4':
-                case '5':
-                case '6':
-                case '7':
-                case '8':
-                case '9':
-                {
-                    //
-                    // If this is a zero, and it is the first digit, then the
-                    // fill character is a zero instead of a space.
-                    //
-                    if((pcString[-1] == '0') && (ui32Count == 0))
-                    {
-                        cFill = '0';
-                    }
-
-                    //
-                    // Update the digit count.
-                    //
-                    ui32Count *= 10;
-                    ui32Count += pcString[-1] - '0';
-
-                    //
-                    // Get the next character.
-                    //
-                    goto again;
-                }
-
-                //
-                // Handle the %c command.
-                //
-                case 'c':
-                {
-                    //
-                    // Get the value from the varargs.
-                    //
-                    ui32Value = va_arg(vaArgP, uint32_t);
-
-                    //
-                    // Print out the character.
-                    //
-                    UARTwrite((char *)&ui32Value, 1);
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-
-                //
-                // Handle the %d and %i commands.
-                //
-                case 'd':
-                case 'i':
-                {
-                    //
-                    // Get the value from the varargs.
-                    //
-                    ui32Value = va_arg(vaArgP, uint16_t);
-
-                    //
-                    // Reset the buffer position.
-                    //
-                    ui32Pos = 0;
-
-                    //
-                    // If the value is negative, make it positive and indicate
-                    // that a minus sign is needed.
-                    //
-                    if((int32_t)ui32Value < 0)
-                    {
-                        //
-                        // Make the value positive.
-                        //
-                        ui32Value = -(int32_t)ui32Value;
-
-                        //
-                        // Indicate that the value is negative.
-                        //
-                        ui32Neg = 1;
-                    }
-                    else
-                    {
-                        //
-                        // Indicate that the value is positive so that a minus
-                        // sign isn't inserted.
-                        //
-                        ui32Neg = 0;
-                    }
-
-                    //
-                    // Set the base to 10.
-                    //
-                    ui32Base = 10;
-
-                    //
-                    // Convert the value to ASCII.
-                    //
-                    goto convert;
-                }
-
-                //
-                // Handle the %l command.
-                //
-                case 'l':
-                {
-                	//
-                    // Get the value from the varargs.
-                    //
-                    ui32Value = va_arg(vaArgP, uint32_t);
-
-                    //
-                    // Reset the buffer position.
-                    //
-                    ui32Pos = 0;
-
-                    //
-                    // If the value is negative, make it positive and indicate
-                    // that a minus sign is needed.
-                    //
-                    if((int32_t)ui32Value < 0)
-                    {
-                    	//
-                    	// Make the value positive.
-                    	//
-                    	ui32Value = -(int32_t)ui32Value;
-
-                    	//
-                    	// Indicate that the value is negative.
-                    	//
-                    	ui32Neg = 1;
-                    }
-                    else
-                    {
-                    	//
-                    	// Indicate that the value is positive so that a minus
-                    	// sign isn't inserted.
-                    	//
-                    	ui32Neg = 0;
-                    }
-
-                    //
-                    // Set the base to 10.
-                    //
-                    ui32Base = 10;
-
-                    //
-                    // Convert the value to ASCII.
-                    //
-                    goto convert;
-                }
-
-                //
-                // Handle the %s command.
-                //
-                case 's':
-                {
-                    //
-                    // Get the string pointer from the varargs.
-                    //
-                    pcStr = va_arg(vaArgP, char *);
-
-                    //
-                    // Determine the length of the string.
-                    //
-                    for(ui32Idx = 0; pcStr[ui32Idx] != '\0'; ui32Idx++)
-                    {
-                    }
-
-                    //
-                    // Write the string.
-                    //
-                    UARTwrite(pcStr, ui32Idx);
-
-                    //
-                    // Write any required padding spaces
-                    //
-                    if(ui32Count > ui32Idx)
-                    {
-                        ui32Count -= ui32Idx;
-                        while(ui32Count--)
-                        {
-                            UARTwrite(" ", 1);
-                        }
-                    }
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-
-                //
-                // Handle the %u command.
-                //
-                case 'u':
-                {
-                    //
-                    // Get the value from the varargs.
-                    //
-                    ui32Value = va_arg(vaArgP, uint32_t);
-
-                    //
-                    // Reset the buffer position.
-                    //
-                    ui32Pos = 0;
-
-                    //
-                    // Set the base to 10.
-                    //
-                    ui32Base = 10;
-
-                    //
-                    // Indicate that the value is positive so that a minus sign
-                    // isn't inserted.
-                    //
-                    ui32Neg = 0;
-
-                    //
-                    // Convert the value to ASCII.
-                    //
-                    goto convert;
-                }
-
-                //
-                // Handle the %x and %X commands.  Note that they are treated
-                // identically; in other words, %X will use lower case letters
-                // for a-f instead of the upper case letters it should use.  We
-                // also alias %p to %x.
-                //
-                case 'x':
-                case 'X':
-                case 'p':
-                {
-                    //
-                    // Get the value from the varargs.
-                    //
-                    ui32Value = va_arg(vaArgP, uint32_t);
-
-                    //
-                    // Reset the buffer position.
-                    //
-                    ui32Pos = 0;
-
-                    //
-                    // Set the base to 16.
-                    //
-                    ui32Base = 16;
-
-                    //
-                    // Indicate that the value is positive so that a minus sign
-                    // isn't inserted.
-                    //
-                    ui32Neg = 0;
-
-                    //
-                    // Determine the number of digits in the string version of
-                    // the value.
-                    //
-convert:
-                    for(ui32Idx = 1;
-                        (((ui32Idx * ui32Base) <= ui32Value) &&
-                         (((ui32Idx * ui32Base) / ui32Base) == ui32Idx));
-                        ui32Idx *= ui32Base, ui32Count--)
-                    {
-                    }
-
-                    //
-                    // If the value is negative, reduce the count of padding
-                    // characters needed.
-                    //
-                    if(ui32Neg)
-                    {
-                        ui32Count--;
-                    }
-
-                    //
-                    // If the value is negative and the value is padded with
-                    // zeros, then place the minus sign before the padding.
-                    //
-                    if(ui32Neg && (cFill == '0'))
-                    {
-                        //
-                        // Place the minus sign in the output buffer.
-                        //
-                        pcBuf[ui32Pos++] = '-';
-
-                        //
-                        // The minus sign has been placed, so turn off the
-                        // negative flag.
-                        //
-                        ui32Neg = 0;
-                    }
-
-                    //
-                    // Provide additional padding at the beginning of the
-                    // string conversion if needed.
-                    //
-                    if((ui32Count > 1) && (ui32Count < 16))
-                    {
-                        for(ui32Count--; ui32Count; ui32Count--)
-                        {
-                            pcBuf[ui32Pos++] = cFill;
-                        }
-                    }
-
-                    //
-                    // If the value is negative, then place the minus sign
-                    // before the number.
-                    //
-                    if(ui32Neg)
-                    {
-                        //
-                        // Place the minus sign in the output buffer.
-                        //
-                        pcBuf[ui32Pos++] = '-';
-                    }
-
-                    //
-                    // Convert the value into a string.
-                    //
-                    for(; ui32Idx; ui32Idx /= ui32Base)
-                    {
-                        pcBuf[ui32Pos++] =
-                            g_pcHex[(ui32Value / ui32Idx) % ui32Base];
-                    }
-
-                    //
-                    // Write the string.
-                    //
-                    UARTwrite(pcBuf, ui32Pos);
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-
-                //
-                // Handle the %% command.
-                //
-                case '%':
-                {
-                    //
-                    // Simply write a single %.
-                    //
-                    UARTwrite(pcString - 1, 1);
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-
-                //
-                // Handle all other commands.
-                //
-                default:
-                {
-                    //
-                    // Indicate an error.
-                    //
-                    UARTwrite("ERROR", 5);
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-            }
-        }
-    }
-}
-
-//*****************************************************************************
-//
-//! A simple UART based printf function supporting \%c, \%d, \%p, \%s, \%u,
-//! \%x, and \%X.
-//!
-//! \param pcString is the format string.
-//! \param ... are the optional arguments, which depend on the contents of the
-//! format string.
-//!
-//! This function is very similar to the C library <tt>fprintf()</tt> function.
-//! All of its output will be sent to the UART.  Only the following formatting
-//! characters are supported:
-//!
-//! - \%c to print a character
-//! - \%d or \%i to print a decimal value
-//! - \%s to print a string
-//! - \%u to print an unsigned decimal value
-//! - \%x to print a hexadecimal value using lower case letters
-//! - \%X to print a hexadecimal value using lower case letters (not upper case
-//! letters as would typically be used)
-//! - \%p to print a pointer as a hexadecimal value
-//! - \%\% to print out a \% character
-//!
-//! For \%s, \%d, \%i, \%u, \%p, \%x, and \%X, an optional number may reside
-//! between the \% and the format character, which specifies the minimum number
-//! of characters to use for that value; if preceded by a 0 then the extra
-//! characters will be filled with zeros instead of spaces.  For example,
-//! ``\%8d'' will use eight characters to print the decimal value with spaces
-//! added to reach eight; ``\%08d'' will use eight characters as well but will
-//! add zeroes instead of spaces.
-//!
-//! The type of the arguments after \e pcString must match the requirements of
-//! the format string.  For example, if an integer was passed where a string
-//! was expected, an error of some kind will most likely occur.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTprintf(const char *pcString, ...)
-{
-    va_list vaArgP;
-
-    //
-    // Start the varargs processing.
-    //
-    va_start(vaArgP, pcString);
-
-    UARTvprintf(pcString, vaArgP);
-
-    //
-    // We're finished with the varargs now.
-    //
-    va_end(vaArgP);
-}
-
-//*****************************************************************************
-//
-//! Returns the number of bytes available in the receive buffer.
-//!
-//! This function, available only when the module is built to operate in
-//! buffered mode using \b UART_BUFFERED, may be used to determine the number
-//! of bytes of data currently available in the receive buffer.
-//!
-//! \return Returns the number of available bytes.
-//
-//*****************************************************************************
-#if defined(UART_BUFFERED) || defined(DOXYGEN)
-int
-UARTRxBytesAvail(void)
-{
-    return(RX_BUFFER_USED);
-}
-#endif
-
-#if defined(UART_BUFFERED) || defined(DOXYGEN)
-//*****************************************************************************
-//
-//! Returns the number of bytes free in the transmit buffer.
-//!
-//! This function, available only when the module is built to operate in
-//! buffered mode using \b UART_BUFFERED, may be used to determine the amount
-//! of space currently available in the transmit buffer.
-//!
-//! \return Returns the number of free bytes.
-//
-//*****************************************************************************
-int
-UARTTxBytesFree(void)
-{
-    return(TX_BUFFER_FREE);
-}
-#endif
-
-//*****************************************************************************
-//
-//! Looks ahead in the receive buffer for a particular character.
-//!
-//! \param ucChar is the character that is to be searched for.
-//!
-//! This function, available only when the module is built to operate in
-//! buffered mode using \b UART_BUFFERED, may be used to look ahead in the
-//! receive buffer for a particular character and report its position if found.
-//! It is typically used to determine whether a complete line of user input is
-//! available, in which case ucChar should be set to CR ('\\r') which is used
-//! as the line end marker in the receive buffer.
-//!
-//! \return Returns -1 to indicate that the requested character does not exist
-//! in the receive buffer.  Returns a non-negative number if the character was
-//! found in which case the value represents the position of the first instance
-//! of \e ucChar relative to the receive buffer read pointer.
-//
-//*****************************************************************************
-#if defined(UART_BUFFERED) || defined(DOXYGEN)
-int
-UARTPeek(unsigned char ucChar)
-{
-    int iCount;
-    int iAvail;
-    uint32_t ui32ReadIndex;
-
-    //
-    // How many characters are there in the receive buffer?
-    //
-    iAvail = (int)RX_BUFFER_USED;
-    ui32ReadIndex = g_ui32UARTRxReadIndex;
-
-    //
-    // Check all the unread characters looking for the one passed.
-    //
-    for(iCount = 0; iCount < iAvail; iCount++)
-    {
-        if(g_pcUARTRxBuffer[ui32ReadIndex] == ucChar)
-        {
-            //
-            // We found it so return the index
-            //
-            return(iCount);
-        }
-        else
-        {
-            //
-            // This one didn't match so move on to the next character.
-            //
-            ADVANCE_RX_BUFFER_INDEX(ui32ReadIndex);
-        }
-    }
-
-    //
-    // If we drop out of the loop, we didn't find the character in the receive
-    // buffer.
-    //
-    return(-1);
-}
-#endif
-
-//*****************************************************************************
-//
-//! Flushes the receive buffer.
-//!
-//! This function, available only when the module is built to operate in
-//! buffered mode using \b UART_BUFFERED, may be used to discard any data
-//! received from the UART but not yet read using UARTgets().
-//!
-//! \return None.
-//
-//*****************************************************************************
-#if defined(UART_BUFFERED) || defined(DOXYGEN)
-void
-UARTFlushRx(void)
-{
-    uint32_t ui32Int;
-
-    //
-    // Temporarily turn off interrupts.
-    //
-    ui32Int = MAP_IntMasterDisable();
-
-    //
-    // Flush the receive buffer.
-    //
-    g_ui32UARTRxReadIndex = 0;
-    g_ui32UARTRxWriteIndex = 0;
-
-    //
-    // If interrupts were enabled when we turned them off, turn them
-    // back on again.
-    //
-    if(!ui32Int)
-    {
-        MAP_IntMasterEnable();
-    }
-}
-#endif
-
-//*****************************************************************************
-//
-//! Flushes the transmit buffer.
-//!
-//! \param bDiscard indicates whether any remaining data in the buffer should
-//! be discarded (\b true) or transmitted (\b false).
-//!
-//! This function, available only when the module is built to operate in
-//! buffered mode using \b UART_BUFFERED, may be used to flush the transmit
-//! buffer, either discarding or transmitting any data received via calls to
-//! UARTprintf() that is waiting to be transmitted.  On return, the transmit
-//! buffer will be empty.
-//!
-//! \return None.
-//
-//*****************************************************************************
-#if defined(UART_BUFFERED) || defined(DOXYGEN)
-void
-UARTFlushTx(bool bDiscard)
-{
-    uint32_t ui32Int;
-
-    //
-    // Should the remaining data be discarded or transmitted?
-    //
-    if(bDiscard)
-    {
-        //
-        // The remaining data should be discarded, so temporarily turn off
-        // interrupts.
-        //
-        ui32Int = MAP_IntMasterDisable();
-
-        //
-        // Flush the transmit buffer.
-        //
-        g_ui32UARTTxReadIndex = 0;
-        g_ui32UARTTxWriteIndex = 0;
-
-        //
-        // If interrupts were enabled when we turned them off, turn them
-        // back on again.
-        //
-        if(!ui32Int)
-        {
-            MAP_IntMasterEnable();
-        }
-    }
-    else
-    {
-        //
-        // Wait for all remaining data to be transmitted before returning.
-        //
-        while(!TX_BUFFER_EMPTY)
-        {
-        }
-    }
-}
-#endif
-
-//*****************************************************************************
-//
-//! Enables or disables echoing of received characters to the transmitter.
-//!
-//! \param bEnable must be set to \b true to enable echo or \b false to
-//! disable it.
-//!
-//! This function, available only when the module is built to operate in
-//! buffered mode using \b UART_BUFFERED, may be used to control whether or not
-//! received characters are automatically echoed back to the transmitter.  By
-//! default, echo is enabled and this is typically the desired behavior if
-//! the module is being used to support a serial command line.  In applications
-//! where this module is being used to provide a convenient, buffered serial
-//! interface over which application-specific binary protocols are being run,
-//! however, echo may be undesirable and this function can be used to disable
-//! it.
-//!
-//! \return None.
-//
-//*****************************************************************************
-#if defined(UART_BUFFERED) || defined(DOXYGEN)
-void
-UARTEchoSet(bool bEnable)
-{
-    g_bDisableEcho = !bEnable;
-}
-#endif
-
-//*****************************************************************************
-//
-//! Handles UART interrupts.
-//!
-//! This function handles interrupts from the UART.  It will copy data from the
-//! transmit buffer to the UART transmit FIFO if space is available, and it
-//! will copy data from the UART receive FIFO to the receive buffer if data is
-//! available.
-//!
-//! \return None.
-//
-//*****************************************************************************
-#if defined(UART_BUFFERED) || defined(DOXYGEN)
-void
-UARTStdioIntHandler(void)
-{
-    uint32_t ui32Ints;
-    int8_t cChar;
-    int32_t i32Char;
-    static bool bLastWasCR = false;
-
-    //
-    // Get and clear the current interrupt source(s)
-    //
-    ui32Ints = MAP_UARTIntStatus(g_ui32Base, true);
-    MAP_UARTIntClear(g_ui32Base, ui32Ints);
-
-    //
-    // Are we being interrupted because the TX FIFO has space available?
-    //
-    if(ui32Ints & UART_INT_TX)
-    {
-        //
-        // Move as many bytes as we can into the transmit FIFO.
-        //
-        UARTPrimeTransmit(g_ui32Base);
-
-        //
-        // If the output buffer is empty, turn off the transmit interrupt.
-        //
-        if(TX_BUFFER_EMPTY)
-        {
-            MAP_UARTIntDisable(g_ui32Base, UART_INT_TX);
-        }
-    }
-
-    //
-    // Are we being interrupted due to a received character?
-    //
-    if(ui32Ints & (UART_INT_RX | UART_INT_RT))
-    {
-        //
-        // Get all the available characters from the UART.
-        //
-        while(MAP_UARTCharsAvail(g_ui32Base))
-        {
-            //
-            // Read a character
-            //
-            i32Char = MAP_UARTCharGetNonBlocking(g_ui32Base);
-            cChar = (unsigned char)(i32Char & 0xFF);
-
-            //
-            // If echo is disabled, we skip the various text filtering
-            // operations that would typically be required when supporting a
-            // command line.
-            //
-            if(!g_bDisableEcho)
-            {
-                //
-                // Handle backspace by erasing the last character in the
-                // buffer.
-                //
-                if(cChar == '\b')
-                {
-                    //
-                    // If there are any characters already in the buffer, then
-                    // delete the last.
-                    //
-                    if(!RX_BUFFER_EMPTY)
-                    {
-                        //
-                        // Rub out the previous character on the users
-                        // terminal.
-                        //
-                        UARTwrite("\b \b", 3);
-
-                        //
-                        // Decrement the number of characters in the buffer.
-                        //
-                        if(g_ui32UARTRxWriteIndex == 0)
-                        {
-                            g_ui32UARTRxWriteIndex = UART_RX_BUFFER_SIZE - 1;
-                        }
-                        else
-                        {
-                            g_ui32UARTRxWriteIndex--;
-                        }
-                    }
-
-                    //
-                    // Skip ahead to read the next character.
-                    //
-                    continue;
-                }
-
-                //
-                // If this character is LF and last was CR, then just gobble up
-                // the character since we already echoed the previous CR and we
-                // don't want to store 2 characters in the buffer if we don't
-                // need to.
-                //
-                if((cChar == '\n') && bLastWasCR)
-                {
-                    bLastWasCR = false;
-                    continue;
-                }
-
-                //
-                // See if a newline or escape character was received.
-                //
-                if((cChar == '\r') || (cChar == '\n') || (cChar == 0x1b))
-                {
-                    //
-                    // If the character is a CR, then it may be followed by an
-                    // LF which should be paired with the CR.  So remember that
-                    // a CR was received.
-                    //
-                    if(cChar == '\r')
-                    {
-                        bLastWasCR = 1;
-                    }
-
-                    //
-                    // Regardless of the line termination character received,
-                    // put a CR in the receive buffer as a marker telling
-                    // UARTgets() where the line ends.  We also send an
-                    // additional LF to ensure that the local terminal echo
-                    // receives both CR and LF.
-                    //
-                    cChar = '\r';
-                    UARTwrite("\n", 1);
-                }
-            }
-
-            //
-            // If there is space in the receive buffer, put the character
-            // there, otherwise throw it away.
-            //
-            if(!RX_BUFFER_FULL)
-            {
-                //
-                // Store the new character in the receive buffer
-                //
-                g_pcUARTRxBuffer[g_ui32UARTRxWriteIndex] =
-                    (unsigned char)(i32Char & 0xFF);
-                ADVANCE_RX_BUFFER_INDEX(g_ui32UARTRxWriteIndex);
-
-                //
-                // If echo is enabled, write the character to the transmit
-                // buffer so that the user gets some immediate feedback.
-                //
-                if(!g_bDisableEcho)
-                {
-                    UARTwrite((const char *)&cChar, 1);
-                }
-            }
-        }
-
-        //
-        // If we wrote anything to the transmit buffer, make sure it actually
-        // gets transmitted.
-        //
-        UARTPrimeTransmit(g_ui32Base);
-        MAP_UARTIntEnable(g_ui32Base, UART_INT_TX);
-    }
-}
-#endif
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
-
-//
-// End of file
-//
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.h b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.h
deleted file mode 100644
index 1176091bbb..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.h
+++ /dev/null
@@ -1,107 +0,0 @@
-//###########################################################################
-//
-// FILE:   uartstdio.h
-//
-// TITLE:  Prototypes for the UART console functions.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __UARTSTDIO_H__
-#define __UARTSTDIO_H__
-
-//
-// Included Files
-//
-#include <stdarg.h>
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//
-// If built for buffered operation, the following labels define the sizes of
-// the transmit and receive buffers respectively.
-//
-#ifdef UART_BUFFERED
-#ifndef UART_RX_BUFFER_SIZE
-#define UART_RX_BUFFER_SIZE     128
-#endif
-#ifndef UART_TX_BUFFER_SIZE
-#define UART_TX_BUFFER_SIZE     1024
-#endif
-#endif
-
-//
-// Function Prototypes
-//
-extern void UARTStdioConfig(uint32_t ui32Port, uint32_t ui32Baud,
-                            uint32_t ui32SrcClock);
-extern int UARTgets(char *pcBuf, uint32_t ui32Len);
-extern unsigned char UARTgetc(void);
-extern void UARTprintf(const char *pcString, ...);
-extern void UARTvprintf(const char *pcString, va_list vaArgP);
-extern int UARTwrite(const char *pcBuf, uint32_t ui32Len);
-#ifdef UART_BUFFERED
-extern int UARTPeek(unsigned char ucChar);
-extern void UARTFlushTx(bool bDiscard);
-extern void UARTFlushRx(void);
-extern int UARTRxBytesAvail(void);
-extern int UARTTxBytesFree(void);
-extern void UARTEchoSet(bool bEnable);
-#endif
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __UARTSTDIO_H__
-
-//
-// End of file
-//
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.c b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.c
deleted file mode 100644
index 05e0ce7be2..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.c
+++ /dev/null
@@ -1,1853 +0,0 @@
-//###########################################################################
-//
-// FILE:   ustdlib.c
-//
-// TITLE:  Simple standard library functions.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-//
-// Included Files
-//
-#include <stdint.h>
-#include <stdbool.h>
-#include "driverlib/debug.h"
-#include "utils/ustdlib.h"
-
-//*****************************************************************************
-//
-//! \addtogroup ustdlib_api
-//! @{
-//
-//*****************************************************************************
-
-//
-// Globals
-//
-
-//
-// A mapping from an integer between 0 and 15 to its ASCII character
-// equivalent.
-//
-static const char * const g_pcHex = "0123456789abcdef";
-
-//
-// Functions
-//
-
-//*****************************************************************************
-//
-//! Copies a certain number of characters from one string to another.
-//!
-//! \param s1 is a pointer to the destination buffer into which characters
-//! are to be copied.
-//! \param s2 is a pointer to the string from which characters are to be
-//! copied.
-//! \param n is the number of characters to copy to the destination buffer.
-//!
-//! This function copies at most \e n characters from the string pointed to
-//! by \e s2 into the buffer pointed to by \e s1.  If the end of \e s2 is found
-//! before \e n characters have been copied, remaining characters in \e s1
-//! will be padded with zeroes until \e n characters have been written.  Note
-//! that the destination string will only be NULL terminated if the number of
-//! characters to be copied is greater than the length of \e s2.
-//!
-//! \return Returns \e s1.
-//
-//*****************************************************************************
-char *
-ustrncpy(char * restrict s1, const char * restrict s2, size_t n)
-{
-    size_t count;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(s1);
-    ASSERT(s2);
-
-    //
-    // Start at the beginning of the source string.
-    //
-    count = 0;
-
-    //
-    // Copy the source string until we run out of source characters or
-    // destination space.
-    //
-    while(n && s2[count])
-    {
-        s1[count] = s2[count];
-        count++;
-        n--;
-    }
-
-    //
-    // Pad the destination if we are not yet done.
-    //
-    while(n)
-    {
-        s1[count++] = (char)0;
-        n--;
-    }
-
-    //
-    // Pass the destination pointer back to the caller.
-    //
-    return(s1);
-}
-
-//*****************************************************************************
-//
-//! A simple vsnprintf function supporting \%c, \%d, \%p, \%s, \%u, \%x, and
-//! \%X.
-//!
-//! \param s points to the buffer where the converted string is stored.
-//! \param n is the size of the buffer.
-//! \param format is the format string.
-//! \param arg is the list of optional arguments, which depend on the
-//! contents of the format string.
-//!
-//! This function is very similar to the C library <tt>vsnprintf()</tt>
-//! function.  Only the following formatting characters are supported:
-//!
-//! - \%c to print a character
-//! - \%d or \%i to print a decimal value
-//! - \%s to print a string
-//! - \%u to print an unsigned decimal value
-//! - \%x to print a hexadecimal value using lower case letters
-//! - \%X to print a hexadecimal value using lower case letters (not upper case
-//! letters as would typically be used)
-//! - \%p to print a pointer as a hexadecimal value
-//! - \%\% to print out a \% character
-//!
-//! For \%d, \%i, \%p, \%s, \%u, \%x, and \%X, an optional number may reside
-//! between the \% and the format character, which specifies the minimum number
-//! of characters to use for that value; if preceded by a 0 then the extra
-//! characters will be filled with zeros instead of spaces.  For example,
-//! ``\%8d'' will use eight characters to print the decimal value with spaces
-//! added to reach eight; ``\%08d'' will use eight characters as well but will
-//! add zeroes instead of spaces.
-//!
-//! The type of the arguments after \e format must match the requirements of
-//! the format string.  For example, if an integer was passed where a string
-//! was expected, an error of some kind will most likely occur.
-//!
-//! The \e n parameter limits the number of characters that will be
-//! stored  in the buffer pointed to by \e s to prevent the possibility of
-//! a buffer  overflow.  The buffer size should be large enough to hold the
-//! expected converted output string, including the null termination character.
-//!
-//! The function will return the number of characters that would be converted
-//! as if there were no limit on the buffer size.  Therefore it is possible for
-//! the function to return a count that is greater than the specified buffer
-//! size.  If this happens, it means that the output was truncated.
-//!
-//! \return Returns the number of characters that were to be stored, not
-//! including the NULL termination character, regardless of space in the
-//! buffer.
-//
-//*****************************************************************************
-int
-uvsnprintf(char * restrict s, size_t n, const char * restrict format,
-           va_list arg)
-{
-    unsigned long ulIdx, ulValue, ulCount, ulBase, ulNeg;
-    char *pcStr, cFill;
-    int iConvertCount = 0;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(s);
-    ASSERT(n);
-    ASSERT(format);
-
-    //
-    // Adjust buffer size limit to allow one space for null termination.
-    //
-    if(n)
-    {
-        n--;
-    }
-
-    //
-    // Initialize the count of characters converted.
-    //
-    iConvertCount = 0;
-
-    //
-    // Loop while there are more characters in the format string.
-    //
-    while(*format)
-    {
-        //
-        // Find the first non-% character, or the end of the string.
-        //
-        for(ulIdx = 0; (format[ulIdx] != '%') && (format[ulIdx] != '\0');
-            ulIdx++)
-        {
-        }
-
-        //
-        // Write this portion of the string to the output buffer.  If there are
-        // more characters to write than there is space in the buffer, then
-        // only write as much as will fit in the buffer.
-        //
-        if(ulIdx > n)
-        {
-            ustrncpy(s, format, n);
-            s += n;
-            n = 0;
-        }
-        else
-        {
-            ustrncpy(s, format, ulIdx);
-            s += ulIdx;
-            n -= ulIdx;
-        }
-
-        //
-        // Update the conversion count.  This will be the number of characters
-        // that should have been written, even if there was not room in the
-        // buffer.
-        //
-        iConvertCount += ulIdx;
-
-        //
-        // Skip the portion of the format string that was written.
-        //
-        format += ulIdx;
-
-        //
-        // See if the next character is a %.
-        //
-        if(*format == '%')
-        {
-            //
-            // Skip the %.
-            //
-            format++;
-
-            //
-            // Set the digit count to zero, and the fill character to space
-            // (that is, to the defaults).
-            //
-            ulCount = 0;
-            cFill = ' ';
-
-            //
-            // It may be necessary to get back here to process more characters.
-            // Goto's aren't pretty, but effective.  I feel extremely dirty for
-            // using not one but two of the beasts.
-            //
-again:
-
-            //
-            // Determine how to handle the next character.
-            //
-            switch(*format++)
-            {
-                //
-                // Handle the digit characters.
-                //
-                case '0':
-                case '1':
-                case '2':
-                case '3':
-                case '4':
-                case '5':
-                case '6':
-                case '7':
-                case '8':
-                case '9':
-                {
-                    //
-                    // If this is a zero, and it is the first digit, then the
-                    // fill character is a zero instead of a space.
-                    //
-                    if((format[-1] == '0') && (ulCount == 0))
-                    {
-                        cFill = '0';
-                    }
-
-                    //
-                    // Update the digit count.
-                    //
-                    ulCount *= 10;
-                    ulCount += format[-1] - '0';
-
-                    //
-                    // Get the next character.
-                    //
-                    goto again;
-                }
-
-                //
-                // Handle the %c command.
-                //
-                case 'c':
-                {
-                    //
-                    // Get the value from the varargs.
-                    //
-                    ulValue = va_arg(arg, unsigned long);
-
-                    //
-                    // Copy the character to the output buffer, if there is
-                    // room.  Update the buffer size remaining.
-                    //
-                    if(n != 0)
-                    {
-                        *s++ = (char)ulValue;
-                        n--;
-                    }
-
-                    //
-                    // Update the conversion count.
-                    //
-                    iConvertCount++;
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-
-                //
-                // Handle the %d and %i commands.
-                //
-                case 'd':
-                case 'i':
-                {
-                    //
-                    // Get the value from the varargs.
-                    //
-                    ulValue = va_arg(arg, unsigned long);
-
-                    //
-                    // If the value is negative, make it positive and indicate
-                    // that a minus sign is needed.
-                    //
-                    if((long)ulValue < 0)
-                    {
-                        //
-                        // Make the value positive.
-                        //
-                        ulValue = -(long)ulValue;
-
-                        //
-                        // Indicate that the value is negative.
-                        //
-                        ulNeg = 1;
-                    }
-                    else
-                    {
-                        //
-                        // Indicate that the value is positive so that a
-                        // negative sign isn't inserted.
-                        //
-                        ulNeg = 0;
-                    }
-
-                    //
-                    // Set the base to 10.
-                    //
-                    ulBase = 10;
-
-                    //
-                    // Convert the value to ASCII.
-                    //
-                    goto convert;
-                }
-
-                //
-                // Handle the %s command.
-                //
-                case 's':
-                {
-                    //
-                    // Get the string pointer from the varargs.
-                    //
-                    pcStr = va_arg(arg, char *);
-
-                    //
-                    // Determine the length of the string.
-                    //
-                    for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++)
-                    {
-                    }
-
-                    //
-                    // Update the convert count to include any padding that
-                    // should be necessary (regardless of whether we have space
-                    // to write it or not).
-                    //
-                    if(ulCount > ulIdx)
-                    {
-                        iConvertCount += (ulCount - ulIdx);
-                    }
-
-                    //
-                    // Copy the string to the output buffer.  Only copy as much
-                    // as will fit in the buffer.  Update the output buffer
-                    // pointer and the space remaining.
-                    //
-                    if(ulIdx > n)
-                    {
-                        ustrncpy(s, pcStr, n);
-                        s += n;
-                        n = 0;
-                    }
-                    else
-                    {
-                        ustrncpy(s, pcStr, ulIdx);
-                        s += ulIdx;
-                        n -= ulIdx;
-
-                        //
-                        // Write any required padding spaces assuming there is
-                        // still space in the buffer.
-                        //
-                        if(ulCount > ulIdx)
-                        {
-                            ulCount -= ulIdx;
-                            if(ulCount > n)
-                            {
-                                ulCount = n;
-                            }
-                            n = -ulCount;
-
-                            while(ulCount--)
-                            {
-                                *s++ = ' ';
-                            }
-                        }
-                    }
-
-                    //
-                    // Update the conversion count.  This will be the number of
-                    // characters that should have been written, even if there
-                    // was not room in the buffer.
-                    //
-                    iConvertCount += ulIdx;
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-
-                //
-                // Handle the %u command.
-                //
-                case 'u':
-                {
-                    //
-                    // Get the value from the varargs.
-                    //
-                    ulValue = va_arg(arg, unsigned long);
-
-                    //
-                    // Set the base to 10.
-                    //
-                    ulBase = 10;
-
-                    //
-                    // Indicate that the value is positive so that a minus sign
-                    // isn't inserted.
-                    //
-                    ulNeg = 0;
-
-                    //
-                    // Convert the value to ASCII.
-                    //
-                    goto convert;
-                }
-
-                //
-                // Handle the %x and %X commands.  Note that they are treated
-                // identically; that is, %X will use lower case letters for a-f
-                // instead of the upper case letters is should use.  We also
-                // alias %p to %x.
-                //
-                case 'x':
-                case 'X':
-                case 'p':
-                {
-                    //
-                    // Get the value from the varargs.
-                    //
-                    ulValue = va_arg(arg, unsigned long);
-
-                    //
-                    // Set the base to 16.
-                    //
-                    ulBase = 16;
-
-                    //
-                    // Indicate that the value is positive so that a minus sign
-                    // isn't inserted.
-                    //
-                    ulNeg = 0;
-
-                    //
-                    // Determine the number of digits in the string version of
-                    // the value.
-                    //
-convert:
-                    for(ulIdx = 1;
-                        (((ulIdx * ulBase) <= ulValue) &&
-                         (((ulIdx * ulBase) / ulBase) == ulIdx));
-                        ulIdx *= ulBase, ulCount--)
-                    {
-                    }
-
-                    //
-                    // If the value is negative, reduce the count of padding
-                    // characters needed.
-                    //
-                    if(ulNeg)
-                    {
-                        ulCount--;
-                    }
-
-                    //
-                    // If the value is negative and the value is padded with
-                    // zeros, then place the minus sign before the padding.
-                    //
-                    if(ulNeg && (n != 0) && (cFill == '0'))
-                    {
-                        //
-                        // Place the minus sign in the output buffer.
-                        //
-                        *s++ = '-';
-                        n--;
-
-                        //
-                        // Update the conversion count.
-                        //
-                        iConvertCount++;
-
-                        //
-                        // The minus sign has been placed, so turn off the
-                        // negative flag.
-                        //
-                        ulNeg = 0;
-                    }
-
-                    //
-                    // See if there are more characters in the specified field
-                    // width than there are in the conversion of this value.
-                    //
-                    if((ulCount > 1) && (ulCount < 65536))
-                    {
-                        //
-                        // Loop through the required padding characters.
-                        //
-                        for(ulCount--; ulCount; ulCount--)
-                        {
-                            //
-                            // Copy the character to the output buffer if there
-                            // is room.
-                            //
-                            if(n != 0)
-                            {
-                                *s++ = cFill;
-                                n--;
-                            }
-
-                            //
-                            // Update the conversion count.
-                            //
-                            iConvertCount++;
-                        }
-                    }
-
-                    //
-                    // If the value is negative, then place the minus sign
-                    // before the number.
-                    //
-                    if(ulNeg && (n != 0))
-                    {
-                        //
-                        // Place the minus sign in the output buffer.
-                        //
-                        *s++ = '-';
-                        n--;
-
-                        //
-                        // Update the conversion count.
-                        //
-                        iConvertCount++;
-                    }
-
-                    //
-                    // Convert the value into a string.
-                    //
-                    for(; ulIdx; ulIdx /= ulBase)
-                    {
-                        //
-                        // Copy the character to the output buffer if there is
-                        // room.
-                        //
-                        if(n != 0)
-                        {
-                            *s++ = g_pcHex[(ulValue / ulIdx) % ulBase];
-                            n--;
-                        }
-
-                        //
-                        // Update the conversion count.
-                        //
-                        iConvertCount++;
-                    }
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-
-                //
-                // Handle the %% command.
-                //
-                case '%':
-                {
-                    //
-                    // Simply write a single %.
-                    //
-                    if(n != 0)
-                    {
-                        *s++ = format[-1];
-                        n--;
-                    }
-
-                    //
-                    // Update the conversion count.
-                    //
-                    iConvertCount++;
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-
-                //
-                // Handle all other commands.
-                //
-                default:
-                {
-                    //
-                    // Indicate an error.
-                    //
-                    if(n >= 5)
-                    {
-                        ustrncpy(s, "ERROR", 5);
-                        s += 5;
-                        n -= 5;
-                    }
-                    else
-                    {
-                        ustrncpy(s, "ERROR", n);
-                        s += n;
-                        n = 0;
-                    }
-
-                    //
-                    // Update the conversion count.
-                    //
-                    iConvertCount += 5;
-
-                    //
-                    // This command has been handled.
-                    //
-                    break;
-                }
-            }
-        }
-    }
-
-    //
-    // Null terminate the string in the buffer.
-    //
-    *s = 0;
-
-    //
-    // Return the number of characters in the full converted string.
-    //
-    return(iConvertCount);
-}
-
-//*****************************************************************************
-//
-//! A simple sprintf function supporting \%c, \%d, \%p, \%s, \%u, \%x, and \%X.
-//!
-//! \param s is the buffer where the converted string is stored.
-//! \param format is the format string.
-//! \param ... are the optional arguments, which depend on the contents of the
-//! format string.
-//!
-//! This function is very similar to the C library <tt>sprintf()</tt> function.
-//! Only the following formatting characters are supported:
-//!
-//! - \%c to print a character
-//! - \%d or \%i to print a decimal value
-//! - \%s to print a string
-//! - \%u to print an unsigned decimal value
-//! - \%x to print a hexadecimal value using lower case letters
-//! - \%X to print a hexadecimal value using lower case letters (not upper case
-//! letters as would typically be used)
-//! - \%p to print a pointer as a hexadecimal value
-//! - \%\% to print out a \% character
-//!
-//! For \%d, \%i, \%p, \%s, \%u, \%x, and \%X, an optional number may reside
-//! between the \% and the format character, which specifies the minimum number
-//! of characters to use for that value; if preceded by a 0 then the extra
-//! characters will be filled with zeros instead of spaces.  For example,
-//! ``\%8d'' will use eight characters to print the decimal value with spaces
-//! added to reach eight; ``\%08d'' will use eight characters as well but will
-//! add zeros instead of spaces.
-//!
-//! The type of the arguments after \e format must match the requirements of
-//! the format string.  For example, if an integer was passed where a string
-//! was expected, an error of some kind will most likely occur.
-//!
-//! The caller must ensure that the buffer \e s is large enough to hold the
-//! entire converted string, including the null termination character.
-//!
-//! \return Returns the count of characters that were written to the output
-//! buffer, not including the NULL termination character.
-//
-//*****************************************************************************
-int
-usprintf(char * restrict s, const char *format, ...)
-{
-    va_list arg;
-    int ret;
-
-    //
-    // Start the varargs processing.
-    //
-    va_start(arg, format);
-
-    //
-    // Call vsnprintf to perform the conversion.  Use a large number for the
-    // buffer size.
-    //
-    ret = uvsnprintf(s, 0xffff, format, arg);
-
-    //
-    // End the varargs processing.
-    //
-    va_end(arg);
-
-    //
-    // Return the conversion count.
-    //
-    return(ret);
-}
-
-//*****************************************************************************
-//
-//! A simple snprintf function supporting \%c, \%d, \%p, \%s, \%u, \%x, and
-//! \%X.
-//!
-//! \param s is the buffer where the converted string is stored.
-//! \param n is the size of the buffer.
-//! \param format is the format string.
-//! \param ... are the optional arguments, which depend on the contents of the
-//! format string.
-//!
-//! This function is very similar to the C library <tt>sprintf()</tt> function.
-//! Only the following formatting characters are supported:
-//!
-//! - \%c to print a character
-//! - \%d or \%i to print a decimal value
-//! - \%s to print a string
-//! - \%u to print an unsigned decimal value
-//! - \%x to print a hexadecimal value using lower case letters
-//! - \%X to print a hexadecimal value using lower case letters (not upper case
-//! letters as would typically be used)
-//! - \%p to print a pointer as a hexadecimal value
-//! - \%\% to print out a \% character
-//!
-//! For \%d, \%i, \%p, \%s, \%u, \%x, and \%X, an optional number may reside
-//! between the \% and the format character, which specifies the minimum number
-//! of characters to use for that value; if preceded by a 0 then the extra
-//! characters will be filled with zeros instead of spaces.  For example,
-//! ``\%8d'' will use eight characters to print the decimal value with spaces
-//! added to reach eight; ``\%08d'' will use eight characters as well but will
-//! add zeros instead of spaces.
-//!
-//! The type of the arguments after \e format must match the requirements of
-//! the format string.  For example, if an integer was passed where a string
-//! was expected, an error of some kind will most likely occur.
-//!
-//! The function will copy at most \e n - 1 characters into the buffer
-//! \e s.  One space is reserved in the buffer for the null termination
-//! character.
-//!
-//! The function will return the number of characters that would be converted
-//! as if there were no limit on the buffer size.  Therefore it is possible for
-//! the function to return a count that is greater than the specified buffer
-//! size.  If this happens, it means that the output was truncated.
-//!
-//! \return Returns the number of characters that were to be stored, not
-//! including the NULL termination character, regardless of space in the
-//! buffer.
-//
-//*****************************************************************************
-int
-usnprintf(char * restrict s, size_t n, const char * restrict format, ...)
-{
-    va_list arg;
-    int ret;
-
-    //
-    // Start the varargs processing.
-    //
-    va_start(arg, format);
-
-    //
-    // Call vsnprintf to perform the conversion.
-    //
-    ret = uvsnprintf(s, n, format, arg);
-
-    //
-    // End the varargs processing.
-    //
-    va_end(arg);
-
-    //
-    // Return the conversion count.
-    //
-    return(ret);
-}
-
-
-//
-// This array contains the number of days in a year at the beginning of each
-// month of the year, in a non-leap year.
-//
-static const time_t g_psDaysToMonth[12] =
-{
-    0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
-};
-
-//*****************************************************************************
-//
-//! Converts from seconds to calendar date and time.
-//!
-//! \param timer is the number of seconds.
-//! \param tm is a pointer to the time structure that is filled in with the
-//! broken down date and time.
-//!
-//! This function converts a number of seconds since midnight GMT on January 1,
-//! 1970 (traditional Unix epoch) into the equivalent month, day, year, hours,
-//! minutes, and seconds representation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-ulocaltime(time_t timer, struct tm *tm)
-{
-    time_t temp, months;
-
-    //
-    // Extract the number of seconds, converting time to the number of minutes.
-    //
-    temp = timer / 60;
-    tm->tm_sec = timer - (temp * 60);
-    timer = temp;
-
-    //
-    // Extract the number of minutes, converting time to the number of hours.
-    //
-    temp = timer / 60;
-    tm->tm_min = timer - (temp * 60);
-    timer = temp;
-
-    //
-    // Extract the number of hours, converting time to the number of days.
-    //
-    temp = timer / 24;
-    tm->tm_hour = timer - (temp * 24);
-    timer = temp;
-
-    //
-    // Compute the day of the week.
-    //
-    tm->tm_wday = (timer + 4) % 7;
-
-    //
-    // Compute the number of leap years that have occurred since 1968, the
-    // first leap year before 1970.  For the beginning of a leap year, cut the
-    // month loop below at March so that the leap day is classified as February
-    // 29 followed by March 1, instead of March 1 followed by another March 1.
-    //
-    timer += 366 + 365;
-    temp = timer / ((4 * 365) + 1);
-    if((timer - (temp * ((4 * 365) + 1))) > (31 + 28))
-    {
-        temp++;
-        months = 12;
-    }
-    else
-    {
-        months = 2;
-    }
-
-    //
-    // Extract the year.
-    //
-    tm->tm_year = ((timer - temp) / 365) + 68;
-    timer -= ((tm->tm_year - 68) * 365) + temp;
-
-    //
-    // Extract the month.
-    //
-    for(temp = 0; temp < months; temp++)
-    {
-        if(g_psDaysToMonth[temp] > timer)
-        {
-            break;
-        }
-    }
-    tm->tm_mon = temp - 1;
-
-    //
-    // Extract the day of the month.
-    //
-    tm->tm_mday = timer - g_psDaysToMonth[temp - 1] + 1;
-}
-
-//*****************************************************************************
-//
-//! Compares two time structures and determines if one is greater than,
-//! less than, or equal to the other.
-//!
-//! \param t1 is the first time structure to compare.
-//! \param t2 is the second time structure to compare.
-//!
-//! This function compares two time structures and returns a signed number
-//! to indicate the result of the comparison.  If the time represented by
-//! \e t1 is greater than the time represented by \e t2 then a positive
-//! number is returned.  Likewise if \e t1 is less than \e t2 then a
-//! negative number is returned.  If the two times are equal then the function
-//! returns 0.
-//!
-//! \return Returns 0 if the two times are equal, +1 if \e t1 is greater
-//! than \e t2, and -1 if \e t1 is less than \e t2.
-//
-//*****************************************************************************
-static int
-ucmptime(struct tm *t1, struct tm *t2)
-{
-    //
-    // Compare each field in descending significance to determine if
-    // greater than, less than, or equal.
-    //
-    if(t1->tm_year > t2->tm_year)
-    {
-        return(1);
-    }
-    else if(t1->tm_year < t2->tm_year)
-    {
-        return(-1);
-    }
-    else if(t1->tm_mon > t2->tm_mon)
-    {
-        return(1);
-    }
-    else if(t1->tm_mon < t2->tm_mon)
-    {
-        return(-1);
-    }
-    else if(t1->tm_mday > t2->tm_mday)
-    {
-        return(1);
-    }
-    else if(t1->tm_mday < t2->tm_mday)
-    {
-        return(-1);
-    }
-    else if(t1->tm_hour > t2->tm_hour)
-    {
-        return(1);
-    }
-    else if(t1->tm_hour < t2->tm_hour)
-    {
-        return(-1);
-    }
-    else if(t1->tm_min > t2->tm_min)
-    {
-        return(1);
-    }
-    else if(t1->tm_min < t2->tm_min)
-    {
-        return(-1);
-    }
-    else if(t1->tm_sec > t2->tm_sec)
-    {
-        return(1);
-    }
-    else if(t1->tm_sec < t2->tm_sec)
-    {
-        return(-1);
-    }
-    else
-    {
-        //
-        // Reaching this branch of the conditional means that all of the
-        // fields are equal, and thus the two times are equal.
-        //
-        return(0);
-    }
-}
-
-//*****************************************************************************
-//
-//! Converts calendar date and time to seconds.
-//!
-//! \param timeptr is a pointer to the time structure that is filled in with
-//! the broken down date and time.
-//!
-//! This function converts the date and time represented by the \e timeptr
-//! structure pointer to the number of seconds since midnight GMT on January 1,
-//! 1970 (traditional Unix epoch).
-//!
-//! \return Returns the calendar time and date as seconds.  If the conversion
-//! was not possible then the function returns (uint32_t)(-1).
-//
-//*****************************************************************************
-time_t
-umktime(struct tm *timeptr)
-{
-    struct tm sTimeGuess;
-    unsigned long ulTimeGuess = 0x80000000;
-    unsigned long ulAdjust = 0x40000000;
-    int iSign;
-
-    //
-    // Seed the binary search with the first guess.
-    //
-    ulocaltime(ulTimeGuess, &sTimeGuess);
-    iSign = ucmptime(timeptr, &sTimeGuess);
-
-    //
-    // While the time is not yet found, execute a binary search.
-    //
-    while(iSign && ulAdjust)
-    {
-        //
-        // Adjust the time guess up or down depending on the result of the
-        // last compare.
-        //
-        ulTimeGuess = ((iSign > 0) ? (ulTimeGuess + ulAdjust) :
-                       (ulTimeGuess - ulAdjust));
-        ulAdjust /= 2;
-
-        //
-        // Compare the new time guess against the time pointed at by the
-        // function parameters.
-        //
-        ulocaltime(ulTimeGuess, &sTimeGuess);
-        iSign = ucmptime(timeptr, &sTimeGuess);
-    }
-
-    //
-    // If the above loop was exited with iSign == 0, that means that the
-    // time in seconds was found, so return that value to the caller.
-    //
-    if(iSign == 0)
-    {
-        return(ulTimeGuess);
-    }
-
-    //
-    // Otherwise the time could not be converted so return an error.
-    //
-    else
-    {
-        return((unsigned long)-1);
-    }
-}
-
-//*****************************************************************************
-//
-//! Converts a string into its numeric equivalent.
-//!
-//! \param nptr is a pointer to the string containing the integer.
-//! \param endptr is a pointer that will be set to the first character past
-//! the integer in the string.
-//! \param base is the radix to use for the conversion; can be zero to
-//! auto-select the radix or between 2 and 16 to explicitly specify the radix.
-//!
-//! This function is very similar to the C library <tt>strtoul()</tt> function.
-//! It scans a string for the first token (that is, non-white space) and
-//! converts the value at that location in the string into an integer value.
-//!
-//! \return Returns the result of the conversion.
-//
-//*****************************************************************************
-unsigned long
-ustrtoul(const char * restrict nptr, const char ** restrict endptr, int base)
-{
-    unsigned long ulRet, ulDigit, ulNeg, ulValid;
-    const char *pcPtr;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(nptr);
-    ASSERT((base == 0) || ((base > 1) && (base <= 16)));
-
-    //
-    // Initially, the result is zero.
-    //
-    ulRet = 0;
-    ulNeg = 0;
-    ulValid = 0;
-
-    //
-    // Skip past any leading white space.
-    //
-    pcPtr = nptr;
-    while((*pcPtr == ' ') || (*pcPtr == '\t'))
-    {
-        pcPtr++;
-    }
-
-    //
-    // Take a leading + or - from the value.
-    //
-    if(*pcPtr == '-')
-    {
-        ulNeg = 1;
-        pcPtr++;
-    }
-    else if(*pcPtr == '+')
-    {
-        pcPtr++;
-    }
-
-    //
-    // See if the radix was not specified, or is 16, and the value starts with
-    // "0x" or "0X" (to indicate a hex value).
-    //
-    if(((base == 0) || (base == 16)) && (*pcPtr == '0') &&
-       ((pcPtr[1] == 'x') || (pcPtr[1] == 'X')))
-    {
-        //
-        // Skip the leading "0x".
-        //
-        pcPtr += 2;
-
-        //
-        // Set the radix to 16.
-        //
-        base = 16;
-    }
-
-    //
-    // See if the radix was not specified.
-    //
-    if(base == 0)
-    {
-        //
-        // See if the value starts with "0".
-        //
-        if(*pcPtr == '0')
-        {
-            //
-            // Values that start with "0" are assumed to be radix 8.
-            //
-            base = 8;
-        }
-        else
-        {
-            //
-            // Otherwise, the values are assumed to be radix 10.
-            //
-            base = 10;
-        }
-    }
-
-    //
-    // Loop while there are more valid digits to consume.
-    //
-    while(1)
-    {
-        //
-        // See if this character is a number.
-        //
-        if((*pcPtr >= '0') && (*pcPtr <= '9'))
-        {
-            //
-            // Convert the character to its integer equivalent.
-            //
-            ulDigit = *pcPtr++ - '0';
-        }
-
-        //
-        // Otherwise, see if this character is an upper case letter.
-        //
-        else if((*pcPtr >= 'A') && (*pcPtr <= 'Z'))
-        {
-            //
-            // Convert the character to its integer equivalent.
-            //
-            ulDigit = *pcPtr++ - 'A' + 10;
-        }
-
-        //
-        // Otherwise, see if this character is a lower case letter.
-        //
-        else if((*pcPtr >= 'a') && (*pcPtr <= 'z'))
-        {
-            //
-            // Convert the character to its integer equivalent.
-            //
-            ulDigit = *pcPtr++ - 'a' + 10;
-        }
-
-        //
-        // Otherwise, this is not a valid character.
-        //
-        else
-        {
-            //
-            // Stop converting this value.
-            //
-            break;
-        }
-
-        //
-        // See if this digit is valid for the chosen radix.
-        //
-        if(ulDigit >= base)
-        {
-            //
-            // Since this was not a valid digit, move the pointer back to the
-            // character that therefore should not have been consumed.
-            //
-            pcPtr--;
-
-            //
-            // Stop converting this value.
-            //
-            break;
-        }
-
-        //
-        // Add this digit to the converted value.
-        //
-        ulRet *= base;
-        ulRet += ulDigit;
-
-        //
-        // Since a digit has been added, this is now a valid result.
-        //
-        ulValid = 1;
-    }
-
-    //
-    // Set the return string pointer to the first character not consumed.
-    //
-    if(endptr)
-    {
-        *endptr = ulValid ? pcPtr : nptr;
-    }
-
-    //
-    // Return the converted value.
-    //
-    return(ulNeg ? (0 - ulRet) : ulRet);
-}
-
-//
-// An array of the value of ten raised to the power-of-two exponents.  This is
-// used for converting the decimal exponent into the floating-point value of
-// 10^exp.
-//
-static const float g_pfExponents[] =
-{
-    1.0e+01,
-    1.0e+02,
-    1.0e+04,
-    1.0e+08,
-    1.0e+16,
-    1.0e+32,
-};
-
-//*****************************************************************************
-//
-//! Converts a string into its floating-point equivalent.
-//!
-//! \param nptr is a pointer to the string containing the floating-point
-//! value.
-//! \param endptr is a pointer that will be set to the first character past
-//! the floating-point value in the string.
-//!
-//! This function is very similar to the C library <tt>strtof()</tt> function.
-//! It scans a string for the first token (that is, non-white space) and
-//! converts the value at that location in the string into a floating-point
-//! value.
-//!
-//! \return Returns the result of the conversion.
-//
-//*****************************************************************************
-float
-ustrtof(const char *nptr, const char **endptr)
-{
-    unsigned long ulNeg, ulExp, ulExpNeg, ulValid, ulIdx;
-    float fRet, fDigit, fExp;
-    const char *pcPtr;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(nptr);
-
-    //
-    // Initially, the result is zero.
-    //
-    fRet = 0;
-    ulNeg = 0;
-    ulValid = 0;
-
-    //
-    // Skip past any leading white space.
-    //
-    pcPtr = nptr;
-    while((*pcPtr == ' ') || (*pcPtr == '\t'))
-    {
-        pcPtr++;
-    }
-
-    //
-    // Take a leading + or - from the value.
-    //
-    if(*pcPtr == '-')
-    {
-        ulNeg = 1;
-        pcPtr++;
-    }
-    else if(*pcPtr == '+')
-    {
-        pcPtr++;
-    }
-
-    //
-    // Loop while there are valid digits to consume.
-    //
-    while((*pcPtr >= '0') && (*pcPtr <= '9'))
-    {
-        //
-        // Add this digit to the converted value.
-        //
-        fRet *= 10;
-        fRet += *pcPtr++ - '0';
-
-        //
-        // Since a digit has been added, this is now a valid result.
-        //
-        ulValid = 1;
-    }
-
-    //
-    // See if the next character is a period and the character after that is a
-    // digit, indicating the start of the fractional portion of the value.
-    //
-    if((*pcPtr == '.') && (pcPtr[1] >= '0') && (pcPtr[1] <= '9'))
-    {
-        //
-        // Skip the period.
-        //
-        pcPtr++;
-
-        //
-        // Loop while there are valid fractional digits to consume.
-        //
-        fDigit = 0.1;
-        while((*pcPtr >= '0') && (*pcPtr <= '9'))
-        {
-            //
-            // Add this digit to the converted value.
-            //
-            fRet += (*pcPtr++ - '0') * fDigit;
-            fDigit /= (float)10.0;
-
-            //
-            // Since a digit has been added, this is now a valid result.
-            //
-            ulValid = 1;
-        }
-    }
-
-    //
-    // See if the next character is an "e" and a valid number has been
-    // converted, indicating the start of the exponent.
-    //
-    if(((pcPtr[0] == 'e') || (pcPtr[0] == 'E')) && (ulValid == 1) &&
-       (((pcPtr[1] >= '0') && (pcPtr[1] <= '9')) ||
-        (((pcPtr[1] == '+') || (pcPtr[1] == '-')) &&
-         (pcPtr[2] >= '0') && (pcPtr[2] <= '9'))))
-    {
-        //
-        // Skip the "e".
-        //
-        pcPtr++;
-
-        //
-        // Take a leading + or - from the exponent.
-        //
-        ulExpNeg = 0;
-        if(*pcPtr == '-')
-        {
-            ulExpNeg = 1;
-            pcPtr++;
-        }
-        else if(*pcPtr == '+')
-        {
-            pcPtr++;
-        }
-
-        //
-        // Loop while there are valid digits in the exponent.
-        //
-        ulExp = 0;
-        while((*pcPtr >= '0') && (*pcPtr <= '9'))
-        {
-            //
-            // Add this digit to the converted value.
-            //
-            ulExp *= 10;
-            ulExp += *pcPtr++ - '0';
-        }
-
-        //
-        // Raise ten to the power of the exponent.  Do this via binary
-        // decomposition; for each binary bit set in the exponent, multiply the
-        // floating-point representation by ten raised to that binary value
-        // (extracted from the table above).
-        //
-        fExp = 1;
-        for(ulIdx = 0; ulIdx < 7; ulIdx++)
-        {
-            if(ulExp & (1 << ulIdx))
-            {
-                fExp *= g_pfExponents[ulIdx];
-            }
-        }
-
-        //
-        // If the exponent is negative, then the exponent needs to be inverted.
-        //
-        if(ulExpNeg == 1)
-        {
-            fExp = 1 / fExp;
-        }
-
-        //
-        // Multiply the result by the computed exponent value.
-        //
-        fRet *= fExp;
-    }
-
-    //
-    // Set the return string pointer to the first character not consumed.
-    //
-    if(endptr)
-    {
-        *endptr = ulValid ? pcPtr : nptr;
-    }
-
-    //
-    // Return the converted value.
-    //
-    return(ulNeg ? (0 - fRet) : fRet);
-}
-
-//*****************************************************************************
-//
-//! Returns the length of a null-terminated string.
-//!
-//! \param s is a pointer to the string whose length is to be found.
-//!
-//! This function is very similar to the C library <tt>strlen()</tt> function.
-//! It determines the length of the null-terminated string passed and returns
-//! this to the caller.
-//!
-//! This implementation assumes that single byte character strings are passed
-//! and will return incorrect values if passed some UTF-8 strings.
-//!
-//! \return Returns the length of the string pointed to by \e s.
-//
-//*****************************************************************************
-size_t
-ustrlen(const char *s)
-{
-    size_t len;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(s);
-
-    //
-    // Initialize the length.
-    //
-    len = 0;
-
-    //
-    // Step through the string looking for a zero character (marking its end).
-    //
-    while(s[len])
-    {
-        //
-        // Zero not found so move on to the next character.
-        //
-        len++;
-    }
-
-    return(len);
-}
-
-//*****************************************************************************
-//
-//! Finds a substring within a string.
-//!
-//! \param s1 is a pointer to the string that will be searched.
-//! \param s2 is a pointer to the substring that is to be found within
-//! \e s1.
-//!
-//! This function is very similar to the C library <tt>strstr()</tt> function.
-//! It scans a string for the first instance of a given substring and returns
-//! a pointer to that substring.  If the substring cannot be found, a NULL
-//! pointer is returned.
-//!
-//! \return Returns a pointer to the first occurrence of \e s2 within
-//! \e s1 or NULL if no match is found.
-//
-//*****************************************************************************
-char *
-ustrstr(const char *s1, const char *s2)
-{
-    size_t n;
-
-    //
-    // Get the length of the string to be found.
-    //
-    n = ustrlen(s2);
-
-    //
-    // Loop while we have not reached the end of the string.
-    //
-    while(*s1)
-    {
-        //
-        // Check to see if the substring appears at this position.
-        //
-        if(ustrncmp(s2, s1, n) == 0)
-        {
-            //
-            // It does so return the pointer.
-            //
-            return((char *)s1);
-        }
-
-        //
-        // Move to the next position in the string being searched.
-        //
-        s1++;
-    }
-
-    //
-    // We reached the end of the string without finding the substring so
-    // return NULL.
-    //
-    return((char *)0);
-}
-
-//*****************************************************************************
-//
-//! Compares two strings without regard to case.
-//!
-//! \param s1 points to the first string to be compared.
-//! \param s2 points to the second string to be compared.
-//! \param n is the maximum number of characters to compare.
-//!
-//! This function is very similar to the C library <tt>strncasecmp()</tt>
-//! function.  It compares at most \e n characters of two strings without
-//! regard to case.  The comparison ends if a terminating NULL character is
-//! found in either string before \e n characters are compared.  In this case,
-//! the shorter string is deemed the lesser.
-//!
-//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less
-//! than \e s2 and 1 if \e s1 is greater than \e s2.
-//
-//*****************************************************************************
-int
-ustrncasecmp(const char *s1, const char *s2, size_t n)
-{
-    char c1, c2;
-
-    //
-    // Loop while there are more characters to compare.
-    //
-    while(n)
-    {
-        //
-        // If we reached a NULL in both strings, they must be equal so
-        // we end the comparison and return 0
-        //
-        if(!*s1 && !*s2)
-        {
-            return(0);
-        }
-
-        //
-        // Lower case the characters at the current position before we compare.
-        //
-        c1 = (((*s1 >= 'A') && (*s1 <= 'Z')) ? (*s1 + ('a' - 'A')) : *s1);
-        c2 = (((*s2 >= 'A') && (*s2 <= 'Z')) ? (*s2 + ('a' - 'A')) : *s2);
-
-        //
-        // Compare the two characters and, if different, return the relevant
-        // return code.
-        //
-        if(c2 < c1)
-        {
-            return(1);
-        }
-        if(c1 < c2)
-        {
-            return(-1);
-        }
-
-        //
-        // Move on to the next character.
-        //
-        s1++;
-        s2++;
-        n--;
-    }
-
-    //
-    // If we fall out, the strings must be equal for at least the first n
-    // characters so return 0 to indicate this.
-    //
-    return(0);
-}
-
-//*****************************************************************************
-//
-//! Compares two strings without regard to case.
-//!
-//! \param s1 points to the first string to be compared.
-//! \param s2 points to the second string to be compared.
-//!
-//! This function is very similar to the C library <tt>strcasecmp()</tt>
-//! function.  It compares two strings without regard to case.  The comparison
-//! ends if a terminating NULL character is found in either string.  In this
-//! case, the int16_ter string is deemed the lesser.
-//!
-//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less
-//! than \e s2 and 1 if \e s1 is greater than \e s2.
-//
-//*****************************************************************************
-int
-ustrcasecmp(const char *s1, const char *s2)
-{
-    //
-    // Just let ustrncasecmp() handle this.
-    //
-    return(ustrncasecmp(s1, s2, (size_t)-1));
-}
-
-//*****************************************************************************
-//
-//! Compares two strings.
-//!
-//! \param s1 points to the first string to be compared.
-//! \param s2 points to the second string to be compared.
-//! \param n is the maximum number of characters to compare.
-//!
-//! This function is very similar to the C library <tt>strncmp()</tt> function.
-//! It compares at most \e n characters of two strings taking case into
-//! account.  The comparison ends if a terminating NULL character is found in
-//! either string before \e n characters are compared.  In this case, the
-//! int16_ter string is deemed the lesser.
-//!
-//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less
-//! than \e s2 and 1 if \e s1 is greater than \e s2.
-//
-//*****************************************************************************
-int
-ustrncmp(const char *s1, const char *s2, size_t n)
-{
-    //
-    // Loop while there are more characters.
-    //
-    while(n)
-    {
-        //
-        // If we reached a NULL in both strings, they must be equal so we end
-        // the comparison and return 0
-        //
-        if(!*s1 && !*s2)
-        {
-            return(0);
-        }
-
-        //
-        // Compare the two characters and, if different, return the relevant
-        // return code.
-        //
-        if(*s2 < *s1)
-        {
-            return(1);
-        }
-        if(*s1 < *s2)
-        {
-            return(-1);
-        }
-
-        //
-        // Move on to the next character.
-        //
-        s1++;
-        s2++;
-        n--;
-    }
-
-    //
-    // If we fall out, the strings must be equal for at least the first n
-    // characters so return 0 to indicate this.
-    //
-    return(0);
-}
-
-//*****************************************************************************
-//
-//! Compares two strings.
-//!
-//! \param s1 points to the first string to be compared.
-//! \param s2 points to the second string to be compared.
-//!
-//! This function is very similar to the C library <tt>strcmp()</tt>
-//! function.  It compares two strings, taking case into account.  The
-//! comparison ends if a terminating NULL character is found in either string.
-//! In this case, the int16_ter string is deemed the lesser.
-//!
-//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less
-//! than \e s2 and 1 if \e s1 is greater than \e s2.
-//
-//*****************************************************************************
-int
-ustrcmp(const char *s1, const char *s2)
-{
-    //
-    // Pass this on to ustrncmp.
-    //
-    return(ustrncmp(s1, s2, (size_t)-1));
-}
-
-//
-// Random Number Generator Seed Value
-//
-static unsigned int g_iRandomSeed = 1;
-
-//*****************************************************************************
-//
-//! Set the random number generator seed.
-//!
-//! \param seed is the new seed value to use for the random number
-//! generator.
-//!
-//! This function is very similar to the C library <tt>srand()</tt> function.
-//! It will set the seed value used in the <tt>urand()</tt> function.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-usrand(unsigned int seed)
-{
-    g_iRandomSeed = seed;
-}
-
-//*****************************************************************************
-//
-//! Generate a new (pseudo) random number
-//!
-//! This function is very similar to the C library <tt>rand()</tt> function.
-//! It will generate a pseudo-random number sequence based on the seed value.
-//!
-//! \return A pseudo-random number will be returned.
-//
-//*****************************************************************************
-int
-urand(void)
-{
-    //
-    // Generate a new pseudo-random number with a linear congruence random
-    // number generator.  This new random number becomes the seed for the next
-    // random number.
-    //
-    g_iRandomSeed = (g_iRandomSeed * 1664525) + 1013904223;
-
-    //
-    // Return the new random number.
-    //
-    return((int)g_iRandomSeed);
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
-
-//
-// End of file
-//
diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.h b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.h
deleted file mode 100644
index 2cb92ed3a1..0000000000
--- a/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.h
+++ /dev/null
@@ -1,96 +0,0 @@
-//###########################################################################
-//
-// FILE:   ustdlib.h
-//
-// TITLE:  Prototypes for simple standard library functions.
-//
-//###########################################################################
-// $TI Release: F2837xD Support Library v3.05.00.00 $
-// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
-// $Copyright:
-// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without 
-// modification, are permitted provided that the following conditions 
-// are met:
-// 
-//   Redistributions of source code must retain the above copyright 
-//   notice, this list of conditions and the following disclaimer.
-// 
-//   Redistributions in binary form must reproduce the above copyright
-//   notice, this list of conditions and the following disclaimer in the 
-//   documentation and/or other materials provided with the   
-//   distribution.
-// 
-//   Neither the name of Texas Instruments Incorporated nor the names of
-//   its contributors may be used to endorse or promote products derived
-//   from this software without specific prior written permission.
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// $
-//###########################################################################
-
-#ifndef __USTDLIB_H__
-#define __USTDLIB_H__
-
-//
-// Included Files
-//
-#include <stdarg.h>
-#include <time.h>
-
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//
-// Function Prototypes
-//
-extern void ulocaltime(time_t timer, struct tm *tm);
-extern time_t umktime(struct tm *timeptr);
-extern int urand(void);
-extern int usnprintf(char * restrict s, size_t n, const char * restrict format,
-                     ...);
-extern int usprintf(char * restrict s, const char * restrict format, ...);
-extern void usrand(unsigned int seed);
-extern int ustrcasecmp(const char *s1, const char *s2);
-extern int ustrcmp(const char *s1, const char *s2);
-extern size_t ustrlen(const char *s);
-extern int ustrncasecmp(const char *s1, const char *s2, size_t n);
-extern int ustrncmp(const char *s1, const char *s2, size_t n);
-extern char *ustrncpy(char * restrict s1, const char * restrict s2, size_t n);
-extern char *ustrstr(const char *s1, const char *s2);
-extern float ustrtof(const char * restrict nptr,
-                     const char ** restrict endptr);
-extern unsigned long int ustrtoul(const char * restrict nptr,
-                                  const char ** restrict endptr, int base);
-extern int uvsnprintf(char * restrict s, size_t n,
-                      const char * restrict format, va_list arg);
-
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __USTDLIB_H__
-
-//
-// End of file
-//
diff --git a/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28377D.ccxml b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28377D.ccxml
deleted file mode 100644
index 79dd5cc44e..0000000000
--- a/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28377D.ccxml
+++ /dev/null
@@ -1,22 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<configurations XML_version="1.2" id="configurations_0">
-<configuration XML_version="1.2" id="Texas Instruments XDS100v2 USB Debug Probe_0">
-        <instance XML_version="1.2" desc="Texas Instruments XDS100v2 USB Debug Probe_0" href="connections/TIXDS100v2_Connection.xml" id="Texas Instruments XDS100v2 USB Debug Probe_0" xml="TIXDS100v2_Connection.xml" xmlpath="connections"/>
-        <connection XML_version="1.2" id="Texas Instruments XDS100v2 USB Debug Probe_0">
-            <instance XML_version="1.2" href="drivers/tixds100v2icepick_c.xml" id="drivers" xml="tixds100v2icepick_c.xml" xmlpath="drivers"/>
-            <instance XML_version="1.2" href="drivers/tixds100v2c28x.xml" id="drivers" xml="tixds100v2c28x.xml" xmlpath="drivers"/>
-            <instance XML_version="1.2" href="drivers/tixds100v2cla1.xml" id="drivers" xml="tixds100v2cla1.xml" xmlpath="drivers"/>
-            <instance XML_version="1.2" href="drivers/tixds100v2cs_child.xml" id="drivers" xml="tixds100v2cs_child.xml" xmlpath="drivers"/>
-            <platform XML_version="1.2" id="platform_0">
-                <instance XML_version="1.2" desc="TMS320F28377D_0" href="devices/tms320f28377d.xml" id="TMS320F28377D_0" xml="tms320f28377d.xml" xmlpath="devices"/>
-                <device HW_revision="1" XML_version="1.2" description="" id="TMS320F28377D_0" partnum="TMS320F28377D">
-                    <router HW_revision="1.0" XML_version="1.2" description="ICEPick_C router" id="IcePick_C_0" isa="ICEPICK_C">
-                        <subpath id="Subpath_1">
-                            <property Type="numericfield" Value="0x11" desc="Port Number_0" id="Port Number"/>
-                        </subpath>
-                    </router>
-                </device>
-            </platform>
-        </connection>
-    </configuration>
-</configurations>
diff --git a/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28379D.ccxml b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28379D.ccxml
deleted file mode 100644
index bd5fa49893..0000000000
--- a/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28379D.ccxml
+++ /dev/null
@@ -1,22 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<configurations XML_version="1.2" id="configurations_0">
-<configuration XML_version="1.2" id="Texas Instruments XDS100v2 USB Debug Probe_0">
-        <instance XML_version="1.2" desc="Texas Instruments XDS100v2 USB Debug Probe_0" href="connections/TIXDS100v2_Connection.xml" id="Texas Instruments XDS100v2 USB Debug Probe_0" xml="TIXDS100v2_Connection.xml" xmlpath="connections"/>
-        <connection XML_version="1.2" id="Texas Instruments XDS100v2 USB Debug Probe_0">
-            <instance XML_version="1.2" href="drivers/tixds100v2icepick_c.xml" id="drivers" xml="tixds100v2icepick_c.xml" xmlpath="drivers"/>
-            <instance XML_version="1.2" href="drivers/tixds100v2c28x.xml" id="drivers" xml="tixds100v2c28x.xml" xmlpath="drivers"/>
-            <instance XML_version="1.2" href="drivers/tixds100v2cla1.xml" id="drivers" xml="tixds100v2cla1.xml" xmlpath="drivers"/>
-            <instance XML_version="1.2" href="drivers/tixds100v2cs_child.xml" id="drivers" xml="tixds100v2cs_child.xml" xmlpath="drivers"/>
-            <platform XML_version="1.2" id="platform_0">
-                <instance XML_version="1.2" desc="TMS320F28379D_0" href="devices/f28379d.xml" id="TMS320F28379D_0" xml="f28379d.xml" xmlpath="devices"/>
-                <device HW_revision="1" XML_version="1.2" description="" id="TMS320F28379D_0" partnum="TMS320F28379D">
-                    <router HW_revision="1.0" XML_version="1.2" description="ICEPick_C router" id="IcePick_C_0" isa="ICEPICK_C">
-                        <subpath id="Subpath_1">
-                            <property Type="numericfield" Value="0x11" desc="Port Number_0" id="Port Number"/>
-                        </subpath>
-                    </router>
-                </device>
-            </platform>
-        </connection>
-    </configuration>
-</configurations>