[bsp][c28x] add driver for GPIO and improve pwm's driver (#6493)

1. 增加PWM模块的配置kconfig代码
2. 调整目录结构,新增c28x文件夹,将原有tms320f28379的porting移动至c28x文件夹下,通用设备驱动移动至c28x/libraries下
3. 增加gpio驱动代码以及外部中断触发驱动代码

目前已经在tms320f28379上通过测试
This commit is contained in:
YuQi 2022-10-09 11:24:05 +08:00 committed by GitHub
parent e80facfd06
commit 7c122cca25
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
204 changed files with 2884 additions and 34538 deletions

1
.gitignore vendored
View File

@ -48,3 +48,4 @@ tags
.history
CMakeLists.txt
cmake-build-debug
*.mk

View File

@ -15,10 +15,6 @@
#include "rtthread.h"
#include "drv_config.h"
#define BSP_USING_PWM1
#define BSP_USING_PWM2
#define BSP_USING_PWM3
#define BSP_USING_PWM4
#ifdef __cplusplus
extern "C" {
#endif
@ -58,18 +54,6 @@ extern "C" {
}
#endif
#endif
#define EPWM1_MAX_DB 0x03FF
#define EPWM2_MAX_DB 0x03FF
#define EPWM3_MAX_DB 0x03FF
#define EPWM1_MIN_DB 0
#define EPWM2_MIN_DB 0
#define EPWM3_MIN_DB 0
#define DB_UP 1
#define DB_DOWN 0
#define RT_HSPCLKDIV TB_DIV4
#define RT_CLKDIV TB_DIV4
#define RT_CTRMODE TB_COUNT_UPDOWN
#define TZ_OFF 2
#define TZ_ON 1

View File

@ -0,0 +1,439 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-08-28 qiyu first version
*/
#include <rthw.h>
#include "drv_gpio.h"
#include "F2837xD_device.h"
#include "F28x_Project.h" // Device Headerfile and Examples Include File
#ifdef RT_USING_PIN
// the gpio pin number for each port is 32, while it is 16 for ARM
#define PIN_NUM(port, no) (((((port) & 0xFu) << 5) | ((no) & 0x1F)))
#define PIN_PORT(pin) ((rt_uint16_t)(((pin) >> 5) & 0xFu))
#define PIN_NO(pin) ((rt_uint16_t)((pin) & 0x1Fu))
#define PIN_c28x_PORT(pin) (volatile Uint32 *)&GpioDataRegs + (PIN_PORT(pin))*GPY_DATA_OFFSET
#define PIN_c28x_PIN(pin) ((rt_uint32_t)(1u << PIN_NO(pin)))
#define PIN_c28x_PORT_MAX 6 /* gpioA to GPIOF in total*/
#define PIN_IRQ_MAX 5 /* XINT1 to XINT5 in total */
static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args);
static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin);
static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled);
static rt_base_t c28x_pin_get(const char *name)
{
int hw_pin_num = 0;
int i, name_len;
name_len = rt_strlen(name);
if ((name_len < 3) || (name_len >= 7))
{
return -RT_EINVAL;
}
/*
* PX.y
*/
if ((name[0] != 'P') || (name[2] != '.'))
{
return -RT_EINVAL;
}
for (i = 3; i < name_len; i++)
{
hw_pin_num *= 10;
hw_pin_num += name[i] - '0';
}
return hw_pin_num;
}
static void c28x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
volatile Uint32 *gpioDataReg;
Uint32 pinMask;
if (PIN_PORT(pin) < PIN_c28x_PORT_MAX)
{
gpioDataReg = PIN_c28x_PORT(pin);
pinMask = 1UL << (PIN_NO(pin));
if (value == 0)
{
gpioDataReg[GPYCLEAR] = pinMask;
}
else
{
gpioDataReg[GPYSET] = pinMask;
}
}
}
static int c28x_pin_read(rt_device_t dev, rt_base_t pin)
{
volatile Uint32 *gpioDataReg;
int value = PIN_LOW;
if (PIN_PORT(pin) < PIN_c28x_PORT_MAX)
{
gpioDataReg = PIN_c28x_PORT(pin);
value = (gpioDataReg[GPYDAT] >> PIN_NO(pin)) & 0x1;
}
return value;
}
static void c28x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
volatile Uint32 *gpioBaseAddr;
volatile Uint32 *dir, *pud, *odr;
if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
{
return;
}
rt_uint32_t pinMask;
pinMask = 1UL << PIN_NO(pin);
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (PIN_PORT(pin))*GPY_CTRL_OFFSET;
dir = gpioBaseAddr + GPYDIR;
pud = gpioBaseAddr + GPYPUD;
odr = gpioBaseAddr + GPYODR;
EALLOW;
if (mode == PIN_MODE_OUTPUT)
{
*dir |= pinMask;
}
else if (mode == PIN_MODE_INPUT)
{
*dir &= ~pinMask;
}
else if (mode == PIN_MODE_INPUT_PULLUP)
{
*dir &= ~pinMask;
*pud &= ~pinMask;
}
else if (mode == PIN_MODE_INPUT_PULLDOWN)
{
/* input setting: pull down. */
*dir &= ~pinMask;
*pud |= pinMask;
}
else if (mode == PIN_MODE_OUTPUT_OD)
{
/* output setting: od. */
*dir |= pinMask;
*odr |= pinMask;
}
EDIS;
}
const static struct rt_pin_ops _c28x_pin_ops =
{
c28x_pin_mode,
c28x_pin_write,
c28x_pin_read,
c28x_pin_attach_irq,
c28x_pin_dettach_irq,
c28x_pin_irq_enable,
c28x_pin_get,
};
int rt_hw_pin_init(void)
{
return rt_device_pin_register("pin", &_c28x_pin_ops, RT_NULL);
}
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
static rt_int16_t pin_irq_xint_tab[] =
{
BSP_XINT1_PIN,
BSP_XINT2_PIN,
BSP_XINT3_PIN,
BSP_XINT4_PIN,
BSP_XINT5_PIN
};
rt_inline rt_int32_t get_irq_index(rt_uint32_t pin)
{
int i;
for(i = 0 ; i < PIN_IRQ_MAX ; i++)
{
if(pin_irq_xint_tab[i] == pin)
{
return i;
}
}
return -1;
}
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
rt_base_t level;
rt_int32_t irqindex = -1;
if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
{
return -RT_ENOSYS;
}
irqindex = get_irq_index(pin);
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return -RT_EBUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
pin_irq_hdr_tab[irqindex].mode = mode;
pin_irq_hdr_tab[irqindex].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_base_t level;
rt_int32_t irqindex = -1;
rt_uint16_t i;
if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
{
return -RT_ENOSYS;
}
for(i = 0 ; i < PIN_IRQ_MAX ; i++)
{
if(pin_irq_hdr_tab[i].pin == pin)
{
irqindex = i;
break;
}
}
if (irqindex == -1)
{
return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
pin_irq_hdr_tab[irqindex].pin = -1;
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
pin_irq_hdr_tab[irqindex].mode = 0;
pin_irq_hdr_tab[irqindex].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
rt_base_t level;
rt_int32_t irqindex = -1;
rt_uint16_t channel;
rt_uint16_t edge_mode,pin_mode;
if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
{
return -RT_ENOSYS;
}
irqindex = get_irq_index(pin);
/* irqindex+1 = channel*/
if (irqindex < 0 || irqindex >= PIN_IRQ_MAX)
{
return -RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return -RT_ENOSYS;
}
/*
* 1. set the edge mode of interrupt triggering
* 2. set the GPIO mode
* 3. enable XINT channel and set the input source
*/
channel = irqindex+1;
switch (pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
edge_mode = 1;
pin_mode = PIN_MODE_INPUT_PULLDOWN;
break;
case PIN_IRQ_MODE_FALLING:
edge_mode = 0;
pin_mode = PIN_MODE_INPUT_PULLUP;
break;
case PIN_IRQ_MODE_RISING_FALLING:
edge_mode = 3;
pin_mode = PIN_MODE_INPUT;
break;
}
if(channel == 1)
{
XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1
EALLOW;
InputXbarRegs.INPUT4SELECT = pin; //Set XINT1 source to GPIO-pin
EDIS;
XintRegs.XINT1CR.bit.POLARITY = edge_mode; // Falling edge interrupt
}
else if(channel == 2)
{
XintRegs.XINT2CR.bit.ENABLE = 1; // Enable XINT2
EALLOW;
InputXbarRegs.INPUT5SELECT = pin; //Set XINT1 source to GPIO-pin
EDIS;
XintRegs.XINT2CR.bit.POLARITY = edge_mode; // Falling edge interrupt
}
else if(channel == 3)
{
XintRegs.XINT3CR.bit.ENABLE = 1; // Enable XINT2
EALLOW;
InputXbarRegs.INPUT6SELECT = pin; //Set XINT1 source to GPIO-pin
EDIS;
XintRegs.XINT3CR.bit.POLARITY = edge_mode; // Falling edge interrupt
}
else if(channel == 4)
{
XintRegs.XINT4CR.bit.ENABLE = 1; // Enable XINT2
EALLOW;
InputXbarRegs.INPUT13SELECT = pin; //Set XINT1 source to GPIO-pin
EDIS;
XintRegs.XINT4CR.bit.POLARITY = edge_mode; // Falling edge interrupt
}
else if(channel == 5)
{
XintRegs.XINT5CR.bit.ENABLE = 1; // Enable XINT2
EALLOW;
InputXbarRegs.INPUT14SELECT = pin; //Set XINT1 source to GPIO-pin
EDIS;
XintRegs.XINT5CR.bit.POLARITY = edge_mode; // Falling edge interrupt
}
c28x_pin_mode(device, pin, pin_mode);
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
level = rt_hw_interrupt_disable();
channel = irqindex+1;
/*
* TODO modify this simpler
*/
if(channel == 1)
{
XintRegs.XINT1CR.bit.ENABLE = 0; // Disable XINT1
}
else if(channel == 2)
{
XintRegs.XINT2CR.bit.ENABLE = 0; // Disable XINT2
}
else if(channel == 3)
{
XintRegs.XINT3CR.bit.ENABLE = 0; // Disable XINT2
}
else if(channel == 4)
{
XintRegs.XINT4CR.bit.ENABLE = 0; // Disable XINT2
}
else if(channel == 5)
{
XintRegs.XINT5CR.bit.ENABLE = 0; // Disable XINT2
}
rt_hw_interrupt_enable(level);
}
else
{
return -RT_ENOSYS;
}
return RT_EOK;
}
void GPIO_XINT_Callback(rt_int16_t XINT_number);
interrupt void XINT1_Handler(void)
{
rt_interrupt_enter();
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
GPIO_XINT_Callback(1);
rt_interrupt_leave();
}
interrupt void XINT2_Handler(void)
{
rt_interrupt_enter();
GPIO_XINT_Callback(2);
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
rt_interrupt_leave();
}
interrupt void XINT3_Handler(void)
{
rt_interrupt_enter();
GPIO_XINT_Callback(3);
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
rt_interrupt_leave();
}
interrupt void XINT4_Handler(void)
{
rt_interrupt_enter();
GPIO_XINT_Callback(4);
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
rt_interrupt_leave();
}
interrupt void XINT5_Handler(void)
{
rt_interrupt_enter();
GPIO_XINT_Callback(5);
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
rt_interrupt_leave();
}
void GPIO_XINT_Callback(rt_int16_t XINT_number)
{
rt_int32_t irqindex = XINT_number - 1;
if(pin_irq_hdr_tab[irqindex].hdr)
{
pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
}
}
#endif /* RT_USING_PIN */

View File

@ -0,0 +1,44 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-08-28 qiyu first version
*/
#ifndef DRIVERS_DRV_GPIO_H_
#define DRIVERS_DRV_GPIO_H_
#include <board.h>
#include "rtdevice.h"
#ifdef __cplusplus
extern "C" {
#endif
int rt_hw_pin_init(void);
#ifndef BSP_XINT1_PIN
#define BSP_XINT1_PIN -1
#endif
#ifndef BSP_XINT2_PIN
#define BSP_XINT2_PIN -1
#endif
#ifndef BSP_XINT3_PIN
#define BSP_XINT3_PIN -1
#endif
#ifndef BSP_XINT4_PIN
#define BSP_XINT4_PIN -1
#endif
#ifndef BSP_XINT5_PIN
#define BSP_XINT5_PIN -1
#endif
#ifdef __cplusplus
}
#endif
#endif /* DRIVERS_DRV_GPIO_H_ */

View File

@ -17,7 +17,7 @@
/*
* for now, cpu rate is a fixed value, waiting to be modified to an auto-ajustable variable.
*/
#ifdef BSP_USING_PWM
rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data);
#define CPU_FREQUENCY 200e6
@ -120,8 +120,6 @@ static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_config
{
return -RT_ERROR;
}
/*
* TODO Unknown problem
* the clock division configuration of PWM module is 1
@ -136,13 +134,8 @@ static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_config
epwm->TBPRD = prd; /* Set timer period*/
epwm->TBCTR = 0x0000; /* Clear counter*/
epwm->TBCTL.bit.CTRMODE = RT_CTRMODE; /* Count up*/
epwm->TBCTL.bit.HSPCLKDIV = TB_DIV1; /* Clock ratio to SYSCLKOUT*/
epwm->TBCTL.bit.CLKDIV = TB_DIV1;
epwm->CMPCTL.bit.SHDWAMODE = RT_SHADOW_MODE; /* Load registers every ZERO*/
epwm->CMPCTL.bit.SHDWBMODE = RT_SHADOW_MODE;
epwm->CMPCTL.bit.LOADAMODE = RT_LOAD_TIME;
epwm->CMPCTL.bit.LOADBMODE = RT_LOAD_TIME;
/* Setup compare */
if(configuration->channel == CHANNEL_A)
{
@ -180,9 +173,7 @@ static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_config
epwm->DBCTL.bit.IN_MODE = DBA_ALL;
/* if disable dead time, set dead_time to 0 */
epwm->ETSEL.bit.INTSEL = ET_CTR_ZERO; /* Select INT on Zero event */
epwm->ETPS.bit.INTPRD = ET_1ST; /* Generate INT on 1st event */
#ifdef BSP_PWM1_CTR_MODE_UPDOWN
if(phase<180)
{
epwm->TBPHS.bit.TBPHS = prd * phase/180;
@ -192,6 +183,7 @@ static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_config
epwm->TBPHS.bit.TBPHS = prd-prd * (phase-180)/180;
epwm->TBCTL.bit.PHSDIR = 1; /* count up*/
}
#endif
if(epwm == &EPwm1Regs)
{
epwm->TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
@ -374,52 +366,168 @@ static void pwm_isr(struct rt_device_pwm *rt_pwm)
rt_interrupt_leave(); \
}
#ifdef BSP_USING_PWM1
#ifdef BSP_PWM1_IT_ENABLE
EPWM_ISR_DEFINE(1)
void EPWM1_Isr();
#endif
#ifdef BSP_PWM2_IT_ENABLE
EPWM_ISR_DEFINE(2)
void EPWM2_Isr();
#endif
#ifdef BSP_PWM3_IT_ENABLE
EPWM_ISR_DEFINE(3)
void EPWM3_Isr();
#endif
#ifdef BSP_PWM4_IT_ENABLE
EPWM_ISR_DEFINE(4)
void EPWM4_Isr();
#endif
void EPWM1_Isr();
static int c28x_hw_pwm_init(struct c28x_pwm *device)
{
EALLOW;
/* Assigning ISR to PIE */
PieVectTable.EPWM1_INT = &EPWM1_Isr;
/* ENABLE Interrupt */
EDIS;
IER |= M_INT3;
rt_err_t result = 0;
EALLOW;
#ifdef BSP_USING_PWM1
GpioCtrlRegs.GPAPUD.all |= 5<<(1-1)*4; /* Disable pull-up on GPIO0 (EPWM1A) */
GpioCtrlRegs.GPAMUX1.all|= 5<<(1-1)*4; /* Configure GPIO0 as EPWM1A */
GpioCtrlRegs.GPAPUD.all |= 5<<(1-1)*4; /* Disable pull-up(EPWM1A) */
GpioCtrlRegs.GPAMUX1.all|= 5<<(1-1)*4; /* Configure as EPWM1A */
EPwm1Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */
EPwm1Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */
EPwm1Regs.TBCTL.bit.CTRMODE = BSP_PWM1_CTRMODE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM1_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/
EPwm1Regs.TBCTL.bit.CLKDIV = BSP_PWM1_CLKDIV;
EPwm1Regs.CMPCTL.bit.LOADAMODE = BSP_PWM1_LOADAMODE;
EPwm1Regs.CMPCTL.bit.LOADBMODE = BSP_PWM1_LOADAMODE;
#ifdef BSP_PWM1_IT_ENABLE
EPwm1Regs.ETSEL.bit.INTEN = 1; /* Enable INT */
EPwm1Regs.ETSEL.bit.INTSEL = BSP_PWM1_INTSEL;
EPwm1Regs.ETPS.bit.INTPRD = BSP_PWM1_INTPRD;
/* Assigning ISR to PIE */
PieVectTable.EPWM1_INT = &EPWM1_Isr;
/* ENABLE Interrupt */
#else
EPwm1Regs.ETSEL.bit.INTEN = 0; /* Disable INT */
#endif
#ifdef BSP_PWM1_ADC_TRIGGER
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = BSP_PWM1_SOCASEL; // Select SOC from zero
EPwm1Regs.ETPS.bit.SOCAPRD = BSP_PWM1_SOCAPRD; // Generate pulse on 1st event
#else
EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
#endif
#ifdef BSP_PWM1_MASTER
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
#else
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
#endif
#endif
#ifdef BSP_USING_PWM2
GpioCtrlRegs.GPAPUD.all |= 5<<(2-1)*4; /* Disable pull-up on GPIO0 (EPWM1A) */
GpioCtrlRegs.GPAMUX1.all|= 5<<(2-1)*4; /* Configure GPIO0 as EPWM1A */
GpioCtrlRegs.GPAPUD.all |= 5<<(2-1)*4; /* Disable pull-up on (EPWM2A) */
GpioCtrlRegs.GPAMUX1.all|= 5<<(2-1)*4; /* Configure as EPWM2A */
EPwm2Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */
EPwm2Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */
EPwm2Regs.TBCTL.bit.CTRMODE = BSP_PWM2_CTRMODE;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM2_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/
EPwm2Regs.TBCTL.bit.CLKDIV = BSP_PWM2_CLKDIV;
EPwm2Regs.CMPCTL.bit.LOADAMODE = BSP_PWM2_LOADAMODE;
EPwm2Regs.CMPCTL.bit.LOADBMODE = BSP_PWM2_LOADAMODE;
#ifdef BSP_PWM2_IT_ENABLE
EPwm2Regs.ETSEL.bit.INTEN = 1; /* Enable INT */
EPwm2Regs.ETSEL.bit.INTSEL = BSP_PWM2_INTSEL;
EPwm2Regs.ETPS.bit.INTPRD = BSP_PWM2_INTPRD;
/* Assigning ISR to PIE */
PieVectTable.EPWM2_INT = &EPWM2_Isr;
/* ENABLE Interrupt */
#else
EPwm2Regs.ETSEL.bit.INTEN = 0; /* Disable INT */
#endif
#ifdef BSP_PWM2_ADC_TRIGGER
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm2Regs.ETSEL.bit.SOCASEL = BSP_PWM2_SOCASEL; // Select SOC from zero
EPwm2Regs.ETPS.bit.SOCAPRD = BSP_PWM2_SOCAPRD; // Generate pulse on 1st event
#else
EPwm2Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
#endif
#ifdef BSP_PWM2_MASTER
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
#else
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
#endif
#endif
#ifdef BSP_USING_PWM3
GpioCtrlRegs.GPAPUD.all |= 5<<(3-1)*4; /* Disable pull-up on GPIO0 (EPWM1A) */
GpioCtrlRegs.GPAMUX1.all|= 5<<(3-1)*4; /* Configure GPIO0 as EPWM1A */
GpioCtrlRegs.GPAPUD.all |= 5<<(3-1)*4; /* Disable pull-up on (EPWM3A) */
GpioCtrlRegs.GPAMUX1.all|= 5<<(3-1)*4; /* Configure as EPWM3A */
EPwm3Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */
EPwm3Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */
EPwm3Regs.TBCTL.bit.CTRMODE = BSP_PWM3_CTRMODE;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM3_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/
EPwm3Regs.TBCTL.bit.CLKDIV = BSP_PWM3_CLKDIV;
EPwm3Regs.CMPCTL.bit.LOADAMODE = BSP_PWM3_LOADAMODE;
EPwm3Regs.CMPCTL.bit.LOADBMODE = BSP_PWM3_LOADAMODE;
#ifdef BSP_PWM3_IT_ENABLE
EPwm3Regs.ETSEL.bit.INTEN = 1; /* Enable INT */
EPwm3Regs.ETSEL.bit.INTSEL = BSP_PWM3_INTSEL;
EPwm3Regs.ETPS.bit.INTPRD = BSP_PWM3_INTPRD;
/* Assigning ISR to PIE */
PieVectTable.EPWM3_INT = &EPWM3_Isr;
/* ENABLE Interrupt */
#else
EPwm3Regs.ETSEL.bit.INTEN = 0; /* Disable INT */
#endif
#ifdef BSP_PWM3_ADC_TRIGGER
EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL = BSP_PWM3_SOCASEL; // Select SOC from zero
EPwm3Regs.ETPS.bit.SOCAPRD = BSP_PWM3_SOCAPRD; // Generate pulse on 1st event
#else
EPwm3Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
#endif
#ifdef BSP_PWM3_MASTER
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
#else
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
#endif
#endif
#ifdef BSP_USING_PWM4
GpioCtrlRegs.GPAPUD.all |= 5<<(4-1)*4; /* Disable pull-up on GPIO0 (EPWM1A) */
GpioCtrlRegs.GPAMUX1.all|= 5<<(4-1)*4; /* Configure GPIO0 as EPWM1A */
GpioCtrlRegs.GPAPUD.all |= 5<<(4-1)*4; /* Disable pull-up on (EPWM4A) */
GpioCtrlRegs.GPAMUX1.all|= 5<<(4-1)*4; /* Configure as EPWM4A */
EPwm4Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */
EPwm4Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */
#endif
#ifdef BSP_USING_PWM5
GpioCtrlRegs.GPAPUD.all |= 5<<(5-1)*4; /* Disable pull-up on GPIO0 (EPWM1A) */
GpioCtrlRegs.GPAMUX1.all|= 5<<(5-1)*4; /* Configure GPIO0 as EPWM1A */
EPwm5Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */
EPwm5Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */
EPwm4Regs.TBCTL.bit.CTRMODE = BSP_PWM4_CTRMODE;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM4_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/
EPwm4Regs.TBCTL.bit.CLKDIV = BSP_PWM4_CLKDIV;
EPwm4Regs.CMPCTL.bit.LOADAMODE = BSP_PWM4_LOADAMODE;
EPwm4Regs.CMPCTL.bit.LOADBMODE = BSP_PWM4_LOADAMODE;
#ifdef BSP_PWM4_IT_ENABLE
EPwm4Regs.ETSEL.bit.INTEN = 1; /* Enable INT */
EPwm4Regs.ETSEL.bit.INTSEL = BSP_PWM4_INTSEL;
EPwm4Regs.ETPS.bit.INTPRD = BSP_PWM4_INTPRD;
/* Assigning ISR to PIE */
PieVectTable.EPWM4_INT = &EPWM4_Isr;
/* ENABLE Interrupt */
#else
EPwm4Regs.ETSEL.bit.INTEN = 0; /* Disable INT */
#endif
#ifdef BSP_PWM4_ADC_TRIGGER
EPwm4Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm4Regs.ETSEL.bit.SOCASEL = BSP_PWM4_SOCASEL; // Select SOC from zero
EPwm4Regs.ETPS.bit.SOCAPRD = BSP_PWM4_SOCAPRD; // Generate pulse on 1st event
#else
EPwm4Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
#endif
#ifdef BSP_PWM4_MASTER
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
#else
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
#endif
#endif
EDIS;
@ -459,20 +567,21 @@ int c28x_pwm_init(void)
struct rt_pwm_configuration config_tmp1 =
{
.channel = CHANNEL_A,
.period = 10000,
.pulse = 5000,
.dead_time = 100,
.period = BSP_PWM1_INIT_PERIOD,
.pulse = BSP_PWM1_INIT_PULSE,
.dead_time = BSP_PWM1_DB,
.phase = 0,
.complementary = RT_TRUE
};
drv_pwm_set(c28x_pwm_obj[0].pwm_regs,&config_tmp1);
config_tmp1.phase = 180;
drv_pwm_set(c28x_pwm_obj[1].pwm_regs,&config_tmp1);
config_tmp1.phase = 90;
drv_pwm_set(c28x_pwm_obj[2].pwm_regs,&config_tmp1);
config_tmp1.phase = 270;
drv_pwm_set(c28x_pwm_obj[3].pwm_regs,&config_tmp1);
// config_tmp1.phase = BSP_PWM2_PHASE;
// drv_pwm_set(c28x_pwm_obj[1].pwm_regs,&config_tmp1);
// config_tmp1.phase = BSP_PWM3_PHASE;
// drv_pwm_set(c28x_pwm_obj[2].pwm_regs,&config_tmp1);
// config_tmp1.phase = BSP_PWM4_PHASE;
// drv_pwm_set(c28x_pwm_obj[3].pwm_regs,&config_tmp1);
return result;
}
INIT_DEVICE_EXPORT(c28x_pwm_init);
#endif /* BSP_USING_PWM */

View File

@ -13,6 +13,7 @@
#include <board.h>
#include "rtdevice.h"
#ifdef BSP_USING_PWM
struct c28x_pwm
{
struct rt_device_pwm pwm_device;
@ -21,5 +22,5 @@ struct c28x_pwm
};
int c28x_pwm_init(void);
#endif /* BSP_USING_PWM */
#endif /* DRIVERS_DRV_PWM_H_ */

View File

@ -14,7 +14,7 @@
#include "F2837xD_device.h"
#include "F2837xD_sci.h"
typedef long off_t;
//typedef long off_t;
#include "F2837xD_sci_io.h"
#ifdef RT_USING_SERIAL

Some files were not shown because too many files have changed in this diff Show More