Add Infineon Doc and modify file structure

bsp/Infineon/docs/PSOC6系列BSP制作教程.md

@@ -79,7 +79,7 @@ BSP 的制作过程分为如下四个步骤：
 
 #### 3.2.1 堆内存配置讲解
 
-通常情况下，系统 RAM 中的一部分内存空间会被用作堆内存。下面代码的作用是，在不同编译器下规定堆内存的起始地址 **HEAP_BEGIN** 和结束地址 **HEAP_END**。这里 **HEAP_BEGIN** 和 **HEAP_END** 的值需要和后面 [3.5.1 修改链接脚本](# 3.5.1 修改链接脚本) 章节所修改的配置相一致。
+通常情况下，系统 RAM 中的一部分内存空间会被用作堆内存。下面代码的作用是，在不同编译器下规定堆内存的起始地址 **HEAP_BEGIN** 和结束地址 **HEAP_END**。这里 **HEAP_BEGIN** 和 **HEAP_END** 的值需要和后面  [3.5.1 修改链接脚本](# 3.5.1 修改链接脚本) 章节所修改的配置相一致。
 
 在某些系列的芯片中，芯片 RAM 可能分布在不连续的多块内存区域上。此时堆内存的位置可以和系统内存在同一片连续的内存区域，也可以存放在一片独立的内存区域中。
 
@@ -96,8 +96,8 @@ BSP 的制作过程分为如下四个步骤：
 
 | 宏定义               | 意义     | 格式                   |
 | -------------------- | -------- | ---------------------- |
-| SOC_IFX_PSOC6_43012  | 芯片型号 | SOC_IFX_PSOC6_xxx      |
+| SOC_CY8C624ABZI_S2D44 | 芯片型号 | SOC_CY8C6xxx_xxxx  |
-| SOC_SERIES_IFX_PSOC6 | 芯片系列 | SOC_SERIES_IFX_PSOC6xx |
+| SOC_SERIES_IFX_PSOC62 | 芯片系列 | SOC_SERIES_IFX_PSOC6x |
 
 关于 BSP 上的外设支持选项，一个初次提交的 BSP 仅仅需要支持串口驱动即可，因此在配置选项中只需保留这两个驱动配置项，如下图所示：
 
@@ -107,26 +107,42 @@ BSP 的制作过程分为如下四个步骤：
 
 #### 3.4.1 添加底层外设库
 
-![](./figures/hal_config1.png)
+接下来为 BSP 添加底层外设库文件，下图的文件是从 Modus 生成的文件夹中拷贝而来。
-
-接下来为 BSP 添加底层外设库文件，下图的文件是从 Modus 生成的文件中拷贝而来。
 
 ![](./figures/hal_config2.png)
 
-源库文件路径如下图：
+Modus 生成的源库文件路径如下图，在 Modus 工作空间下的 `mtb_shared` 文件夹下：
 
 ![](./figures/hal_config3.png)
 
-同时拷贝 **TARGET_CY8CKIT-062S2-43012** 文件（需根据不同芯片型号拷贝不同名称的文件夹），该文件夹路径如下：
+将以上文件拷贝至 BSP 的 `libraries/IFX_PSOC6_HAL` 文件夹下。
+
+![](./figures/hal_config1.png)
+
+同时复制 **TARGET_CY8CKIT-062S2-43012** 文件（需根据不同芯片型号拷贝不同名称的文件夹），该文件夹路径如下。
 
 ![](./figures/hal_config4.png)
 
+拷贝至具体 BSP 的 libs 文件夹下，例如下图：
+
+![](./figures/hal_config4-1.png)
+
 #### 3.4.1 修改外设配置脚本
 
+根据具体的路径添加通用外设配置（只有移植新的系列才需要做此步骤）
+
 ![](./figures/hal_config5.png)
 
+添加专有芯片相关文件，如下图：
+
+![](./figures/hal_config5-1.png)
+
+首次移植，需要使用串口外设（只有移植新的系列才需要做此步骤）:
+
 ![](./figures/hal_config6.png)
 
+添加库所使用到的头文件路径，如下图：
+
 ![](./figures/hal_config7.png)
 
 ### 3.5 修改工程构建相关文件
@@ -153,7 +169,7 @@ GCC 使用：
 
 ![](./figures/linkscripts_change.png)
 
-本次制作 BSP 使用的芯片为  CY8CKIT-062S2-43012 ，FLASH 为 2M，因此修改 FLASH_SIZE 的参数为 0x00020000。RAM 的大小为 1M， 因此修改 RAM_SIZE 的参数为 0x000FD800。这样的修改方式在一般的应用下就够用了，后续如果有特殊要求，则需要按照链接脚本的语法来根据需求修改。修改链接脚本时，可以参考 [**3.2.1 堆内存配置讲解**](# 3.2.1 堆内存配置讲解) 章节来确定 BSP 的内存分配。
+本次制作 BSP 使用的芯片为  `CY8CKIT-062S2-43012` ，FLASH 为 2M，因此修改 FLASH_SIZE 的参数为 `0x00020000`。RAM 的大小为 1M， 因此修改 RAM_SIZE 的参数为 `0x000FD800`。这样的修改方式在一般的应用下就够用了，后续如果有特殊要求，则需要按照链接脚本的语法来根据需求修改。修改链接脚本时，可以参考 [**3.2.1 堆内存配置讲解**](# 3.2.1 堆内存配置讲解) 章节来确定 BSP 的内存分配。
 
 其他两个链接脚本的文件为 iar 使用的 link.icf 和 gcc 编译器使用的 link.lds，修改的方式也是类似的，如下图所示：
 
@@ -165,13 +181,15 @@ GCC 使用：
 
 **SConscript** 脚本决定 MDK/IAR/RT-Thread Studio 工程的生成以及编译过程中要添加文件。
 
-在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：其中 CPPDEFINES  的参数要根据芯片的 low level（hal) 库中定义的芯片型号去填写。
+在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：其中 **CPPDEFINES**  的参数要根据芯片的 low level（hal)  库中定义的芯片型号去填写。
 
-![](./figures/SConscript.png)
+![](./figures/SConscript1.png)
+
+![](./figures/SConscript2.png)
 
 #### 3.5.3 修改编译选项
 
-rtconfig.py 用于选择编译工具链，可以自行在 CROSS_TOOL 后面选择修改编译工程所需要的工具链，目前 PSCOC6 支持 gcc 和 armclang。
+rtconfig.py 用于选择编译工具链，可以自行在 **CROSS_TOOL** 后面选择修改编译工程所需要的工具链，目前 PSCOC6 支持 gcc 和 armclang。
 
 ![](./figures/rt_configpy.png)
 
@@ -193,36 +211,30 @@ rtconfig.py 用于选择编译工具链，可以自行在 CROSS_TOOL 后面选
 
 以 RT-Thread Studio 为例，介绍如何导入，修改模板配置：
 
-首先打开 RT-Thread Studio ，在 IDE 的左上角点击 `文件—>导入—>RT-Thread Bsp 到工作空间中`
+1、打开 ENV 工具，在工程目录使用 `scons --dist` 命令将工程打包。（整个过程需要保证没有错误）
+
+![](./figures/dist1.png)
+
+打包完成后，可以在 BSP 目录下看到生成的 `dist` 文件夹：
+
+![](./figures/dist2.png)
+
+使用 dist 后生成的工程就可以直接导入到 RT-Thread Studio 中进行开发了。
+
+![](./figures/dist3.png)
+
+打开 RT-Thread Studio ，在 IDE 的左上角点击 `文件—>导入—>RT-Thread Studio 项目到工作空间中`
 
 ![](./figures/studio1.png)
 
-![](./figures/studio2.png)
+选择 dist 出来工程的路径：
-
-导入成功后，文件资源管理器窗口中会显示如下结构，其中 RT-Thread Settings 为图形化工程配置文件，双击打开即可。
-
-![](./figures/studio3.png)
-
-RT-Thread Settings 中硬件相关配置是在 board/Kconfig 中描述的。移植过程如需添加/修改配置，请修改此文件。
-
-![](./figures/studio4.png)
-
-### 3.5 重新生成工程
-
-* MDK5 ：重新生成工程需要使用 Env 工具。
-
-* RT-Thread Studio：使用 Env 工具/同步 scons 配置至项目
-
-同步 scons 配置至项目：
-
-![](./figures/studio5.png)
-
-首先打开 RT-Thread Studio ，在 IDE 的左上角点击 `文件—>导入—>RT-Thread Bsp 到工作空间中`
-
-![](./figures/studio1.png)
 
 ![](./figures/studio2.png)
 
+点击 finsh 即可导入到 Studio 中：
+
+![](./figures/studio2-1.png)
+
 导入成功后，文件资源管理器窗口中会显示如下结构，其中 RT-Thread Settings 为图形化工程配置文件，双击打开即可。
 
 ![](./figures/studio3.png)
@@ -259,10 +271,6 @@ RT-Thread Settings 中硬件相关配置是在 board/Kconfig 中描述的。移
 
 #### 3.6.2 重新生成 MDK 工程
 
-使用上述方法/点击同步 scons 配置至项目
-
-#### 3.5.2 重新生成 MDK 工程
-
 以重新生成 MDK 工程为例，介绍如何重新生成 BSP 工程。
 
 使用 env 工具输入命令 `scons --target=mdk5` 重新生成工程，如下图所示：

bsp/Infineon/libraries/IFX_PSOC6_HAL/SConscript

@@ -20,10 +20,6 @@ src = Split('''
             mtb-hal-cat1/source/cyhal_utils.c
             mtb-hal-cat1/source/cyhal_lptimer.c
             mtb-hal-cat1/source/cyhal_irq_psoc.c
-            mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_02.c
-            mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c
-            mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c
-            mtb-pdl-cat1/drivers/source/cy_scb_common.c
             mtb-pdl-cat1/drivers/source/cy_sysclk.c
             mtb-pdl-cat1/drivers/source/cy_systick.c
             mtb-pdl-cat1/drivers/source/cy_gpio.c
@@ -37,18 +33,14 @@ src = Split('''
             mtb-pdl-cat1/drivers/source/cy_ipc_drv.c
             mtb-pdl-cat1/drivers/source/cy_trigmux.c
             mtb-pdl-cat1/drivers/source/cy_prot.c
-            TARGET_CY8CKIT-062S2-43012/cybsp.c
+            mtb-pdl-cat1/drivers/source/cy_scb_common.c
-            TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c
-            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
-            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
-            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
-            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
-            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
-            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
-            lib/cy_capsense.lib
             ''')
 
-src += Glob(cwd + '/psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
+if GetDepend(['SOC_CY8C624ABZI_S2D44']):
+    src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_02.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c']
+    src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
 
 if GetDepend(['RT_USING_SERIAL']):
     src += ['retarget-io/cy_retarget_io.c']
@@ -59,8 +51,8 @@ if GetDepend(['RT_USING_ADC']):
     src += ['mtb-hal-cat1/source/cyhal_dma_dw.c']
     src += ['mtb-hal-cat1/source/cyhal_dma_dmac.c']
     src += ['mtb-hal-cat1/source/cyhal_dma.c']
-    src += ['mtb-hal-cat1/source/cyhal_analog_common.c']
     src += ['mtb-hal-cat1/source/cyhal_adc_sar.c']
+    src += ['mtb-hal-cat1/source/cyhal_analog_common.c']
     src += ['mtb-pdl-cat1/drivers/source/cy_dma.c']
     src += ['mtb-pdl-cat1/drivers/source/cy_sar.c']
     src += ['mtb-pdl-cat1/drivers/source/cy_dmac.c']
@@ -70,15 +62,6 @@ if GetDepend(['RT_USING_SDIO']):
     src += ['mtb-hal-cat1/source/cyhal_sdhc.c']
     src += ['mtb-pdl-cat1/drivers/source/cy_sd_host.c']
 
-if GetDepend(['RT_USING_QSPI']):
-    src += ['mtb-hal-cat1/source/cyhal_qspi.c']
-    src += ['mtb-pdl-cat1/drivers/source/cy_dma.c']
-    src += ['mtb-pdl-cat1/drivers/source/cy_smif.c']
-    src += ['mtb-pdl-cat1/drivers/source/cy_smif_sfdp.c']
-    src += ['mtb-pdl-cat1/drivers/source/cy_smif_memslot.c']
-    src += ['mtb_shared/serial-flash/cy_serial_flash_qspi.c']
-    src += ['TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c']
-
 if GetDepend(['RT_USING_PWM']):
     src += ['mtb-hal-cat1/source/cyhal_pwm.c']
     src += ['mtb-hal-cat1/source/cyhal_timer.c']
@@ -93,23 +76,13 @@ if GetDepend(['RT_USING_SPI']):
 if GetDepend(['RT_USING_I2C']):
     src += ['mtb-hal-cat1/source/cyhal_i2c.c']
 
-if GetDepend('BSP_USING_USBD'):
-    src += ['mtb_shared/usbdev/cy_usb_dev.c']
-    src += ['mtb_shared/usbdev/cy_usb_dev_hid.c']
-    src += ['mtb-hal-cat1/source/cyhal_usb_dev.c']
-    src += ['mtb-pdl-cat1/drivers/source/cy_dma.c']
-    src += ['mtb-pdl-cat1/drivers/source/cy_usbfs_dev_drv.c']
-    src += ['mtb-pdl-cat1/drivers/source/cy_usbfs_dev_drv_io.c']
-    src += ['mtb-pdl-cat1/drivers/source/cy_usbfs_dev_drv_io_dma.c']
-    src += ['TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_usbdev.c']
-
 if GetDepend('BSP_USING_RTC'):
-    src += ['mtb-pdl-cat1/drivers/source/cy_rtc.c']
     src += ['mtb-hal-cat1/source/cyhal_rtc.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_rtc.c']
 
 if GetDepend('BSP_USING_ON_CHIP_FLASH'):
-    src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
     src += ['mtb-hal-cat1/source/cyhal_flash.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
 
 if GetDepend(['BSP_USING_SLIDER']):
     src += ['capsense/cy_capsense_control.c']
@@ -123,7 +96,8 @@ if GetDepend(['BSP_USING_SLIDER']):
     src += ['capsense/cy_capsense_centroid.c']
     src += ['capsense/cy_capsense_filter.c']
     src += ['mtb-pdl-cat1/drivers/source/cy_csd.c']
-    src += ['TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c']
+    if rtconfig.PLATFORM in ['armclang']:
+        src += ['lib/cy_capsense.lib']
 
 if GetDepend(['RT_USING_WDT']):
     src += ['mtb-pdl-cat1/drivers/source/cy_wdt.c']
@@ -135,21 +109,21 @@ if GetDepend(['RT_USING_DAC']):
 if GetDepend(['RT_USING_HWTIMER']):
     src += ['mtb-hal-cat1/source/cyhal_timer.c']
 
-path = [cwd + '/capsense',
+path = [cwd + '/retarget-io',
-        cwd + '/psoc6cm0p',
-        cwd + '/retarget-io',
         cwd + '/core-lib/include',
-        cwd + '/mtb_shared/serial-flash',
         cwd + '/mtb_shared/usbdev',
         cwd + '/mtb_shared/csdidac',
+        cwd + '/mtb_shared/serial-flash',
         cwd + '/mtb-pdl-cat1/cmsis/include',
         cwd + '/mtb-pdl-cat1/drivers/include',
-        cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include',
         cwd + '/mtb-hal-cat1/include_pvt',
-        cwd + '/mtb-hal-cat1/include',
+        cwd + '/mtb-hal-cat1/include']
-        cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include',
+
-        cwd + '/TARGET_CY8CKIT-062S2-43012',
+if GetDepend(['SOC_CY8C624ABZI_S2D44']):
-        cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
+    path += [cwd + '/psoc6cm0p']
+    path += [cwd + '/capsense']
+    path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
+    path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
 
 group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)
 

bsp/Infineon/libraries/Kconfig

@@ -1,7 +1,7 @@
 config SOC_FAMILY_IFX
     bool
 
-config SOC_SERIES_IFX_PSOC6
+config SOC_SERIES_IFX_PSOC62
     bool
     select ARCH_ARM_CORTEX_M4
     select SOC_FAMILY_IFX

bsp/Infineon/libraries/templates/PSOC62/.config

@@ -60,6 +60,7 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
 #
 # Memory Management
 #
+CONFIG_RT_PAGE_MAX_ORDER=11
 CONFIG_RT_USING_MEMPOOL=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
@@ -117,7 +118,6 @@ CONFIG_FINSH_USING_DESCRIPTION=y
 CONFIG_FINSH_ARG_MAX=10
 # CONFIG_RT_USING_DFS is not set
 # CONFIG_RT_USING_FAL is not set
-# CONFIG_RT_USING_LWP is not set
 
 #
 # Device Drivers
@@ -706,12 +706,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 CONFIG_SOC_FAMILY_IFX=y
-CONFIG_SOC_SERIES_IFX_PSOC6=y
+CONFIG_SOC_SERIES_IFX_PSOC62=y
 
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_IFX_PSOC6_43012=y
+CONFIG_SOC_CY8C624ABZI_S2D44=y
 
 #
 # Onboard Peripheral Drivers

bsp/Infineon/libraries/templates/PSOC62/.project

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
-  <name>1111</name>
+  <name>project</name>
   <comment />
   <projects>
 	</projects>

bsp/Infineon/libraries/templates/PSOC62/.settings/language.settings.xml

@@ -5,7 +5,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1451646591856031841" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1522148012290462689" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>

bsp/Infineon/libraries/templates/PSOC62/.settings/projcfg.ini

@@ -1,5 +1,5 @@
 #RT-Thread Studio Project Configuration
-#Fri Jan 06 10:38:41 CST 2023
+#Thu Jan 12 11:11:44 CST 2023
 project_type=rt-thread
 chip_name=CY8C624ABZI
 os_branch=full
@@ -14,7 +14,7 @@ project_base_bsp=true
 hardware_adapter=KitProg3
 project_name=1111
 is_base_example_project=False
-board_name=PSOC62-IFX-PROTO-KIT
+board_name=psoc6-cy8ckit-062S2-43012
 device_vendor=Infineon 
-bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0
 bsp_version=1.0.0
+bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0

bsp/Infineon/libraries/templates/PSOC62/board/Kconfig

@@ -1,8 +1,8 @@
 menu "Hardware Drivers Config"
 
-config SOC_IFX_PSOC6_43012
+config SOC_CY8C624ABZI_S2D44
     bool
-    select SOC_SERIES_IFX_PSOC6
+    select SOC_SERIES_IFX_PSOC62
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y

bsp/Infineon/libraries/templates/PSOC62/board/SConscript

@@ -28,17 +28,13 @@ path += [cwd + '/ports']
 startup_path_prefix = SDK_LIB
 
 if rtconfig.PLATFORM in ['gcc']:
-    src += [startup_path_prefix +
-            '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S']
     src += [startup_path_prefix +
             '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S']
-elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+elif rtconfig.PLATFORM in ['armclang']:
-    src += [startup_path_prefix +
-            '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S']
     src += [startup_path_prefix +
             '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S']
 
-CPPDEFINES = ['CY8C624ABZI_S2D44', 'IFX_PSOC6_43012', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
+CPPDEFINES = ['CY8C624ABZI_S2D44', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
 group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
 
 Return('group')

bsp/Infineon/libraries/templates/PSOC62/libs/SConscript

@@ -0,0 +1,26 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm']:
+    print("\nThe current project does not support IAR build\n")
+    Return('group')
+elif rtconfig.PLATFORM in ['gcc', 'armclang']:
+    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/cybsp.c']
+    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c']
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')
+
+    CPPPATH = [ cwd + '/TARGET_CY8CKIT-062S2-43012',
+                cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
+    if rtconfig.PLATFORM in ['gcc']:
+        src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S']
+    elif rtconfig.PLATFORM in ['armclang']:
+        src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S']
+
+group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')

bsp/Infineon/libraries/templates/PSOC62/rtconfig.h

@@ -36,6 +36,7 @@
 
 /* Memory Management */
 
+#define RT_PAGE_MAX_ORDER 11
 #define RT_USING_MEMPOOL
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
@@ -197,11 +198,11 @@
 /* Project libraries */
 
 #define SOC_FAMILY_IFX
-#define SOC_SERIES_IFX_PSOC6
+#define SOC_SERIES_IFX_PSOC62
 
 /* Hardware Drivers Config */
 
-#define SOC_IFX_PSOC6_43012
+#define SOC_CY8C624ABZI_S2D44
 
 /* Onboard Peripheral Drivers */
 

bsp/Infineon/psoc6-cy8ckit-062S2-43012/.config

@@ -8,6 +8,7 @@
 #
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
@@ -59,6 +60,7 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
 #
 # Memory Management
 #
+CONFIG_RT_PAGE_MAX_ORDER=11
 CONFIG_RT_USING_MEMPOOL=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
@@ -77,16 +79,19 @@ CONFIG_RT_USING_HEAP=y
 #
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart5"
-CONFIG_RT_VER_NUM=0x40101
+CONFIG_RT_VER_NUM=0x50000
-CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M4=y
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -113,12 +118,12 @@ CONFIG_FINSH_USING_DESCRIPTION=y
 CONFIG_FINSH_ARG_MAX=10
 # CONFIG_RT_USING_DFS is not set
 # CONFIG_RT_USING_FAL is not set
-# CONFIG_RT_USING_LWP is not set
 
 #
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
@@ -133,10 +138,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+CONFIG_RT_USING_PWM=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@@ -144,10 +153,13 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
 # CONFIG_RT_USING_PULSE_ENCODER is not set
 # CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
 # CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
 
 #
 # Using USB
@@ -426,6 +438,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_HASH_MATCH is not set
 # CONFIG_PKG_USING_FIRE_PID_CURVE is not set
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
 
 #
 # system packages
@@ -461,7 +474,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
-# CONFIG_PKG_USING_RTDUINO is not set
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
@@ -664,68 +676,42 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_QPARAM is not set
 
 #
-# Privated Packages of RealThread
+# Arduino libraries
 #
-# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_RTDUINO is not set
-# CONFIG_PKG_USING_PLAYER is not set
-# CONFIG_PKG_USING_MPLAYER is not set
-# CONFIG_PKG_USING_PERSIMMON_SRC is not set
-# CONFIG_PKG_USING_JS_PERSIMMON is not set
-# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
 
 #
-# Network Utilities
+# Sensor libraries
 #
-# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
-# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
-# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
-# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
-# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
-# CONFIG_PKG_USING_SMARTCONFIG is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
-# CONFIG_PKG_USING_RTX is not set
-# CONFIG_RT_USING_TESTCASE is not set
-# CONFIG_PKG_USING_NGHTTP2 is not set
-# CONFIG_PKG_USING_AVS is not set
-# CONFIG_PKG_USING_ALI_LINKKIT is not set
-# CONFIG_PKG_USING_STS is not set
-# CONFIG_PKG_USING_DLMS is not set
-# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
-# CONFIG_PKG_USING_ZBAR is not set
-# CONFIG_PKG_USING_MCF is not set
-# CONFIG_PKG_USING_URPC is not set
-# CONFIG_PKG_USING_DCM is not set
-# CONFIG_PKG_USING_EMQ is not set
-# CONFIG_PKG_USING_CFGM is not set
-# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
-# CONFIG_PKG_USING_SMODULE is not set
-# CONFIG_PKG_USING_SNFD is not set
-# CONFIG_PKG_USING_UDBD is not set
-# CONFIG_PKG_USING_BENCHMARK is not set
-# CONFIG_PKG_USING_UBJSON is not set
-# CONFIG_PKG_USING_DATATYPE is not set
-# CONFIG_PKG_USING_FASTFS is not set
-# CONFIG_PKG_USING_RIL is not set
-# CONFIG_PKG_USING_WATCH_DCM_SVC is not set
-# CONFIG_PKG_USING_WATCH_APP_FWK is not set
-# CONFIG_PKG_USING_GUI_TEST is not set
-# CONFIG_PKG_USING_PMEM is not set
-# CONFIG_PKG_USING_LWRDP is not set
-# CONFIG_PKG_USING_MASAN is not set
-# CONFIG_PKG_USING_BSDIFF_LIB is not set
-# CONFIG_PKG_USING_PRC_DIFF is not set
 
 #
-# RT-Thread Smart
+# Display libraries
 #
-# CONFIG_PKG_USING_UKERNEL is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
-# CONFIG_PKG_USING_TRACE_AGENT is not set
+
+#
+# Timing libraries
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Project libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 CONFIG_SOC_FAMILY_IFX=y
-CONFIG_SOC_SERIES_IFX_PSOC6=y
+CONFIG_SOC_SERIES_IFX_PSOC62=y
 
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_IFX_PSOC6_43012=y
+CONFIG_SOC_CY8C624ABZI_S2D44=y
 
 #
 # Onboard Peripheral Drivers
@@ -743,7 +729,11 @@ CONFIG_BSP_USING_UART=y
 # CONFIG_BSP_USING_UART3 is not set
 # CONFIG_BSP_USING_UART4 is not set
 CONFIG_BSP_USING_UART5=y
-# CONFIG_BSP_USING_PWM is not set
+CONFIG_BSP_USING_PWM=y
+CONFIG_BSP_USING_PWM0=y
+CONFIG_BSP_USING_PWM0_CH3=y
+CONFIG_BSP_USING_PWM0_PORT13=y
+# CONFIG_BSP_USING_PWM0_CH7 is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ADC is not set
 # CONFIG_BSP_USING_SDMMC is not set

bsp/Infineon/psoc6-cy8ckit-062S2-43012/.project

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
-  <name>1111</name>
+  <name>project</name>
   <comment />
   <projects>
 	</projects>

bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/language.settings.xml

@@ -5,7 +5,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1451646591856031841" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1478398809956314721" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>

bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/projcfg.ini

@@ -1,5 +1,5 @@
 #RT-Thread Studio Project Configuration
-#Fri Jan 06 10:38:41 CST 2023
+#Thu Jan 12 11:11:44 CST 2023
 project_type=rt-thread
 chip_name=CY8C624ABZI
 os_branch=full
@@ -14,7 +14,7 @@ project_base_bsp=true
 hardware_adapter=KitProg3
 project_name=1111
 is_base_example_project=False
-board_name=PSOC62-IFX-PROTO-KIT
+board_name=psoc6-cy8ckit-062S2-43012
 device_vendor=Infineon 
-bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0
 bsp_version=1.0.0
+bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0

bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/Kconfig

@@ -1,8 +1,8 @@
 menu "Hardware Drivers Config"
 
-config SOC_IFX_PSOC6_43012
+config SOC_CY8C624ABZI_S2D44
     bool
-    select SOC_SERIES_IFX_PSOC6
+    select SOC_SERIES_IFX_PSOC62
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y

bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/SConscript

@@ -28,17 +28,13 @@ path += [cwd + '/ports']
 startup_path_prefix = SDK_LIB
 
 if rtconfig.PLATFORM in ['gcc']:
-    src += [startup_path_prefix +
-            '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S']
     src += [startup_path_prefix +
             '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S']
-elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+elif rtconfig.PLATFORM in ['armclang']:
-    src += [startup_path_prefix +
-            '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S']
     src += [startup_path_prefix +
             '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S']
 
-CPPDEFINES = ['CY8C624ABZI_S2D44', 'IFX_PSOC6_43012', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
+CPPDEFINES = ['CY8C624ABZI_S2D44', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
 group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
 
 Return('group')

bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/SConscript

@@ -0,0 +1,26 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm']:
+    print("\nThe current project does not support IAR build\n")
+    Return('group')
+elif rtconfig.PLATFORM in ['gcc', 'armclang']:
+    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/cybsp.c']
+    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c']
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')
+
+    CPPPATH = [ cwd + '/TARGET_CY8CKIT-062S2-43012',
+                cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
+    if rtconfig.PLATFORM in ['gcc']:
+        src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S']
+    elif rtconfig.PLATFORM in ['armclang']:
+        src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S']
+
+group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')

bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/.gitignore

@@ -0,0 +1,9 @@
+docs
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 2)
+$(SEARCH_wifi-host-driver)/WiFi_Host_Driver/resources/nvram_deprecated/
+$(SEARCH_bluetooth-freertos)/firmware_deprecated/
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 1)
+../wifi-host-driver/WiFi_Host_Driver/resources/nvram_deprecated/
+../bluetooth-freertos/firmware_deprecated/

bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -0,0 +1,39 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+void init_cycfg_all(void)
+{
+    init_cycfg_system();
+    init_cycfg_clocks();
+    init_cycfg_routing();
+    init_cycfg_peripherals();
+    init_cycfg_pins();
+}

bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -0,0 +1,53 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_connectivity_bt.h"
+#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */

bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -0,0 +1,29 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+