From 7b35c8d3532948fe9f6ea84f5750f760bec43ece Mon Sep 17 00:00:00 2001 From: Rbb666 Date: Thu, 12 Jan 2023 15:12:14 +0800 Subject: [PATCH] Add Infineon Doc and modify file structure --- bsp/Infineon/docs/PSOC6系列BSP制作教程.md | 88 +- bsp/Infineon/docs/figures/Kconfig.png | Bin 76375 -> 77951 bytes bsp/Infineon/docs/figures/SConscript.png | Bin 69963 -> 0 bytes bsp/Infineon/docs/figures/SConscript1.png | Bin 0 -> 89167 bytes bsp/Infineon/docs/figures/SConscript2.png | Bin 0 -> 60721 bytes bsp/Infineon/docs/figures/dist1.png | Bin 0 -> 20106 bytes bsp/Infineon/docs/figures/dist2.png | Bin 0 -> 22721 bytes bsp/Infineon/docs/figures/dist3.png | Bin 0 -> 34495 bytes bsp/Infineon/docs/figures/frame.png | Bin 29733 -> 35800 bytes bsp/Infineon/docs/figures/hal_config4-1.png | Bin 0 -> 15833 bytes bsp/Infineon/docs/figures/hal_config5-1.png | Bin 0 -> 38876 bytes bsp/Infineon/docs/figures/hal_config7.png | Bin 64471 -> 82699 bytes bsp/Infineon/docs/figures/studio1.png | Bin 27432 -> 42815 bytes bsp/Infineon/docs/figures/studio2-1.png | Bin 0 -> 39297 bytes bsp/Infineon/docs/figures/studio2.png | Bin 48461 -> 38421 bytes bsp/Infineon/docs/figures/studio3.png | Bin 12040 -> 12790 bytes .../libraries/IFX_PSOC6_HAL/SConscript | 66 +- bsp/Infineon/libraries/Kconfig | 2 +- .../libraries/templates/PSOC62/.config | 6 +- .../libraries/templates/PSOC62/.cproject | 17 +- .../libraries/templates/PSOC62/.project | 2 +- .../PSOC62/.settings/language.settings.xml | 2 +- .../templates/PSOC62/.settings/projcfg.ini | 6 +- .../libraries/templates/PSOC62/board/Kconfig | 4 +- .../templates/PSOC62/board/SConscript | 8 +- .../templates/PSOC62/libs/SConscript | 26 + .../TARGET_CY8CKIT-062S2-43012/.gitignore | 0 .../GeneratedSource/cycfg.c | 0 .../GeneratedSource/cycfg.h | 0 .../GeneratedSource/cycfg.timestamp | 0 .../GeneratedSource/cycfg_capsense.c | 0 .../GeneratedSource/cycfg_capsense.h | 0 .../GeneratedSource/cycfg_capsense_defines.h | 0 .../cycfg_capsense_tuner_regmap.h | 0 .../GeneratedSource/cycfg_clocks.c | 0 .../GeneratedSource/cycfg_clocks.h | 0 .../GeneratedSource/cycfg_connectivity_bt.c | 0 .../GeneratedSource/cycfg_connectivity_bt.h | 0 .../GeneratedSource/cycfg_dmas.c | 0 .../GeneratedSource/cycfg_dmas.h | 0 .../GeneratedSource/cycfg_notices.h | 0 .../GeneratedSource/cycfg_peripherals.c | 0 .../GeneratedSource/cycfg_peripherals.h | 0 .../GeneratedSource/cycfg_pins.c | 0 .../GeneratedSource/cycfg_pins.h | 0 .../GeneratedSource/cycfg_qspi_memslot.c | 0 .../GeneratedSource/cycfg_qspi_memslot.h | 0 .../GeneratedSource/cycfg_routing.c | 0 .../GeneratedSource/cycfg_routing.h | 0 .../GeneratedSource/cycfg_system.c | 0 .../GeneratedSource/cycfg_system.h | 0 .../GeneratedSource/qspi_config.cfg | 0 .../cyreservedresources.list | 0 .../design.cycapsense | 0 .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 0 .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 0 .../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 0 .../TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s | 0 .../startup_psoc6_02_cm0plus.S | 0 .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld | 0 .../startup_psoc6_02_cm0plus.S | 0 .../TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf | 0 .../TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s | 0 .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 0 .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 0 .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.s | 0 .../TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S | 0 .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S | 0 .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 0 .../TOOLCHAIN_IAR/startup_psoc6_02_cm4.s | 0 .../COMPONENT_CM4/system_psoc6_cm4.c | 0 .../libs}/TARGET_CY8CKIT-062S2-43012/EULA | 0 .../libs}/TARGET_CY8CKIT-062S2-43012/LICENSE | 0 .../TARGET_CY8CKIT-062S2-43012/README.md | 0 .../TARGET_CY8CKIT-062S2-43012/RELEASE.md | 0 .../bluetooth/cybsp_bt_config.c | 0 .../bluetooth/cybsp_bt_config.h | 0 .../libs}/TARGET_CY8CKIT-062S2-43012/cybsp.c | 0 .../libs}/TARGET_CY8CKIT-062S2-43012/cybsp.h | 0 .../TARGET_CY8CKIT-062S2-43012/cybsp_doc.h | 0 .../TARGET_CY8CKIT-062S2-43012/cybsp_types.h | 0 .../dependencies-v1.txt | 0 .../dependencies-v2.txt | 0 .../dependencies-v3.txt | 0 .../TARGET_CY8CKIT-062S2-43012/system_psoc6.h | 0 .../TARGET_CY8CKIT-062S2-43012/version.xml | 0 .../libraries/templates/PSOC62/rtconfig.h | 5 +- .../psoc6-cy8ckit-062S2-43012/.config | 104 +- .../psoc6-cy8ckit-062S2-43012/.cproject | 17 +- .../psoc6-cy8ckit-062S2-43012/.project | 2 +- .../.settings/language.settings.xml | 2 +- .../.settings/projcfg.ini | 6 +- .../psoc6-cy8ckit-062S2-43012/board/Kconfig | 4 +- .../board/SConscript | 8 +- .../psoc6-cy8ckit-062S2-43012/libs/SConscript | 26 + .../TARGET_CY8CKIT-062S2-43012/.gitignore | 9 + .../GeneratedSource/cycfg.c | 39 + .../GeneratedSource/cycfg.h | 53 + .../GeneratedSource/cycfg.timestamp | 29 + .../GeneratedSource/cycfg_capsense.c | 877 +++++++ .../GeneratedSource/cycfg_capsense.h | 2330 +++++++++++++++++ .../GeneratedSource/cycfg_capsense_defines.h | 140 + .../cycfg_capsense_tuner_regmap.h | 973 +++++++ .../GeneratedSource/cycfg_clocks.c | 60 + .../GeneratedSource/cycfg_clocks.h | 66 + .../GeneratedSource/cycfg_connectivity_bt.c | 31 + .../GeneratedSource/cycfg_connectivity_bt.h | 55 + .../GeneratedSource/cycfg_dmas.c | 181 ++ .../GeneratedSource/cycfg_dmas.h | 76 + .../GeneratedSource/cycfg_notices.h | 41 + .../GeneratedSource/cycfg_peripherals.c | 66 + .../GeneratedSource/cycfg_peripherals.h | 87 + .../GeneratedSource/cycfg_pins.c | 581 ++++ .../GeneratedSource/cycfg_pins.h | 936 +++++++ .../GeneratedSource/cycfg_qspi_memslot.c | 271 ++ .../GeneratedSource/cycfg_qspi_memslot.h | 65 + .../GeneratedSource/cycfg_routing.c | 44 + .../GeneratedSource/cycfg_routing.h | 62 + .../GeneratedSource/cycfg_system.c | 1212 +++++++++ .../GeneratedSource/cycfg_system.h | 116 + .../GeneratedSource/qspi_config.cfg | 29 + .../cyreservedresources.list | 20 + .../design.cycapsense | 415 +++ .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 63 + .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 727 +++++ .../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 272 ++ .../TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s | 223 ++ .../startup_psoc6_02_cm0plus.S | 254 ++ .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld | 441 ++++ .../startup_psoc6_02_cm0plus.S | 372 +++ .../TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf | 253 ++ .../TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s | 331 +++ .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 536 ++++ .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 277 ++ .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.s | 708 +++++ .../TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S | 565 ++++ .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 465 ++++ .../TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S | 697 +++++ .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 247 ++ .../TOOLCHAIN_IAR/startup_psoc6_02_cm4.s | 1280 +++++++++ .../COMPONENT_CM4/system_psoc6_cm4.c | 400 +++ .../libs/TARGET_CY8CKIT-062S2-43012/EULA | 55 + .../libs/TARGET_CY8CKIT-062S2-43012/LICENSE | 165 ++ .../libs/TARGET_CY8CKIT-062S2-43012/README.md | 76 + .../TARGET_CY8CKIT-062S2-43012/RELEASE.md | 92 + .../bluetooth/cybsp_bt_config.c | 92 + .../bluetooth/cybsp_bt_config.h | 71 + .../libs/TARGET_CY8CKIT-062S2-43012/cybsp.c | 161 ++ .../libs/TARGET_CY8CKIT-062S2-43012/cybsp.h | 97 + .../TARGET_CY8CKIT-062S2-43012/cybsp_doc.h | 844 ++++++ .../TARGET_CY8CKIT-062S2-43012/cybsp_types.h | 63 + .../dependencies-v1.txt | 7 + .../dependencies-v2.txt | 7 + .../dependencies-v3.txt | 7 + .../TARGET_CY8CKIT-062S2-43012/system_psoc6.h | 734 ++++++ .../TARGET_CY8CKIT-062S2-43012/version.xml | 1 + .../psoc6-cy8ckit-062S2-43012/project.uvoptx | 1292 +++++++++ .../psoc6-cy8ckit-062S2-43012/project.uvprojx | 554 ++-- .../psoc6-cy8ckit-062S2-43012/rtconfig.h | 22 +- .../ra6m3-ek/.settings/standalone.prefs | 16 +- bsp/renesas/ra6m3-ek/configuration.xml | 69 +- .../ra6m3-ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 2 +- bsp/renesas/ra6m3-ek/ra_gen/hal_data.c | 22 + bsp/renesas/ra6m3-ek/ra_gen/hal_data.h | 8 + bsp/renesas/ra6m3-ek/ra_gen/pin_data.c | 42 +- 166 files changed, 21342 insertions(+), 533 deletions(-) delete mode 100644 bsp/Infineon/docs/figures/SConscript.png create mode 100644 bsp/Infineon/docs/figures/SConscript1.png create mode 100644 bsp/Infineon/docs/figures/SConscript2.png create mode 100644 bsp/Infineon/docs/figures/dist1.png create mode 100644 bsp/Infineon/docs/figures/dist2.png create mode 100644 bsp/Infineon/docs/figures/dist3.png create mode 100644 bsp/Infineon/docs/figures/hal_config4-1.png create mode 100644 bsp/Infineon/docs/figures/hal_config5-1.png create mode 100644 bsp/Infineon/docs/figures/studio2-1.png create mode 100644 bsp/Infineon/libraries/templates/PSOC62/libs/SConscript rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/.gitignore (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.modus (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/EULA (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/LICENSE (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/README.md (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/RELEASE.md (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/cybsp.c (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/cybsp.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/cybsp_types.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/system_psoc6.h (100%) rename bsp/Infineon/libraries/{IFX_PSOC6_HAL => templates/PSOC62/libs}/TARGET_CY8CKIT-062S2-43012/version.xml (100%) create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/SConscript create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/.gitignore create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h create mode 100644 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bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c create mode 100644 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bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/EULA create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/LICENSE create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/README.md create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/RELEASE.md create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.c create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.h create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp.c create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp.h create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp_types.h create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/system_psoc6.h create mode 100644 bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/version.xml diff --git a/bsp/Infineon/docs/PSOC6系列BSP制作教程.md b/bsp/Infineon/docs/PSOC6系列BSP制作教程.md index 2b9478ad4b..cf66a8c750 100644 --- a/bsp/Infineon/docs/PSOC6系列BSP制作教程.md +++ b/bsp/Infineon/docs/PSOC6系列BSP制作教程.md @@ -79,7 +79,7 @@ BSP 的制作过程分为如下四个步骤： #### 3.2.1 堆内存配置讲解 -通常情况下，系统 RAM 中的一部分内存空间会被用作堆内存。下面代码的作用是，在不同编译器下规定堆内存的起始地址 **HEAP_BEGIN** 和结束地址 **HEAP_END**。这里 **HEAP_BEGIN** 和 **HEAP_END** 的值需要和后面 [3.5.1 修改链接脚本](# 3.5.1 修改链接脚本) 章节所修改的配置相一致。 +通常情况下，系统 RAM 中的一部分内存空间会被用作堆内存。下面代码的作用是，在不同编译器下规定堆内存的起始地址 **HEAP_BEGIN** 和结束地址 **HEAP_END**。这里 **HEAP_BEGIN** 和 **HEAP_END** 的值需要和后面 [3.5.1 修改链接脚本](# 3.5.1 修改链接脚本) 章节所修改的配置相一致。 在某些系列的芯片中，芯片 RAM 可能分布在不连续的多块内存区域上。此时堆内存的位置可以和系统内存在同一片连续的内存区域，也可以存放在一片独立的内存区域中。 @@ -96,8 +96,8 @@ BSP 的制作过程分为如下四个步骤： | 宏定义 | 意义 | 格式 | | -------------------- | -------- | ---------------------- | -| SOC_IFX_PSOC6_43012 | 芯片型号 | SOC_IFX_PSOC6_xxx | -| SOC_SERIES_IFX_PSOC6 | 芯片系列 | SOC_SERIES_IFX_PSOC6xx | +| SOC_CY8C624ABZI_S2D44 | 芯片型号 | SOC_CY8C6xxx_xxxx | +| SOC_SERIES_IFX_PSOC62 | 芯片系列 | SOC_SERIES_IFX_PSOC6x | 关于 BSP 上的外设支持选项，一个初次提交的 BSP 仅仅需要支持串口驱动即可，因此在配置选项中只需保留这两个驱动配置项，如下图所示： @@ -107,26 +107,42 @@ BSP 的制作过程分为如下四个步骤： #### 3.4.1 添加底层外设库 -![](./figures/hal_config1.png) - -接下来为 BSP 添加底层外设库文件，下图的文件是从 Modus 生成的文件中拷贝而来。 +接下来为 BSP 添加底层外设库文件，下图的文件是从 Modus 生成的文件夹中拷贝而来。 ![](./figures/hal_config2.png) -源库文件路径如下图： +Modus 生成的源库文件路径如下图，在 Modus 工作空间下的 `mtb_shared` 文件夹下： ![](./figures/hal_config3.png) -同时拷贝 **TARGET_CY8CKIT-062S2-43012** 文件（需根据不同芯片型号拷贝不同名称的文件夹），该文件夹路径如下： +将以上文件拷贝至 BSP 的 `libraries/IFX_PSOC6_HAL` 文件夹下。 + +![](./figures/hal_config1.png) + +同时复制 **TARGET_CY8CKIT-062S2-43012** 文件（需根据不同芯片型号拷贝不同名称的文件夹），该文件夹路径如下。 ![](./figures/hal_config4.png) +拷贝至具体 BSP 的 libs 文件夹下，例如下图： + +![](./figures/hal_config4-1.png) + #### 3.4.1 修改外设配置脚本 +根据具体的路径添加通用外设配置（只有移植新的系列才需要做此步骤） + ![](./figures/hal_config5.png) +添加专有芯片相关文件，如下图： + +![](./figures/hal_config5-1.png) + +首次移植，需要使用串口外设（只有移植新的系列才需要做此步骤）: + ![](./figures/hal_config6.png) +添加库所使用到的头文件路径，如下图： + ![](./figures/hal_config7.png) ### 3.5 修改工程构建相关文件 @@ -153,7 +169,7 @@ GCC 使用： ![](./figures/linkscripts_change.png) -本次制作 BSP 使用的芯片为 CY8CKIT-062S2-43012 ，FLASH 为 2M，因此修改 FLASH_SIZE 的参数为 0x00020000。RAM 的大小为 1M， 因此修改 RAM_SIZE 的参数为 0x000FD800。这样的修改方式在一般的应用下就够用了，后续如果有特殊要求，则需要按照链接脚本的语法来根据需求修改。修改链接脚本时，可以参考 [**3.2.1 堆内存配置讲解**](# 3.2.1 堆内存配置讲解) 章节来确定 BSP 的内存分配。 +本次制作 BSP 使用的芯片为 `CY8CKIT-062S2-43012` ，FLASH 为 2M，因此修改 FLASH_SIZE 的参数为 `0x00020000`。RAM 的大小为 1M， 因此修改 RAM_SIZE 的参数为 `0x000FD800`。这样的修改方式在一般的应用下就够用了，后续如果有特殊要求，则需要按照链接脚本的语法来根据需求修改。修改链接脚本时，可以参考 [**3.2.1 堆内存配置讲解**](# 3.2.1 堆内存配置讲解) 章节来确定 BSP 的内存分配。 其他两个链接脚本的文件为 iar 使用的 link.icf 和 gcc 编译器使用的 link.lds，修改的方式也是类似的，如下图所示： @@ -165,13 +181,15 @@ GCC 使用： **SConscript** 脚本决定 MDK/IAR/RT-Thread Studio 工程的生成以及编译过程中要添加文件。 -在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：其中 CPPDEFINES 的参数要根据芯片的 low level（hal) 库中定义的芯片型号去填写。 +在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：其中 **CPPDEFINES** 的参数要根据芯片的 low level（hal) 库中定义的芯片型号去填写。 -![](./figures/SConscript.png) +![](./figures/SConscript1.png) + +![](./figures/SConscript2.png) #### 3.5.3 修改编译选项 -rtconfig.py 用于选择编译工具链，可以自行在 CROSS_TOOL 后面选择修改编译工程所需要的工具链，目前 PSCOC6 支持 gcc 和 armclang。 +rtconfig.py 用于选择编译工具链，可以自行在 **CROSS_TOOL** 后面选择修改编译工程所需要的工具链，目前 PSCOC6 支持 gcc 和 armclang。 ![](./figures/rt_configpy.png) @@ -193,36 +211,30 @@ rtconfig.py 用于选择编译工具链，可以自行在 CROSS_TOOL 后面选 以 RT-Thread Studio 为例，介绍如何导入，修改模板配置： -首先打开 RT-Thread Studio ，在 IDE 的左上角点击 `文件—>导入—>RT-Thread Bsp 到工作空间中` +1、打开 ENV 工具，在工程目录使用 `scons --dist` 命令将工程打包。（整个过程需要保证没有错误） + +![](./figures/dist1.png) + +打包完成后，可以在 BSP 目录下看到生成的 `dist` 文件夹： + +![](./figures/dist2.png) + +使用 dist 后生成的工程就可以直接导入到 RT-Thread Studio 中进行开发了。 + +![](./figures/dist3.png) + +打开 RT-Thread Studio ，在 IDE 的左上角点击 `文件—>导入—>RT-Thread Studio 项目到工作空间中` ![](./figures/studio1.png) -![](./figures/studio2.png) - -导入成功后，文件资源管理器窗口中会显示如下结构，其中 RT-Thread Settings 为图形化工程配置文件，双击打开即可。 - -![](./figures/studio3.png) - -RT-Thread Settings 中硬件相关配置是在 board/Kconfig 中描述的。移植过程如需添加/修改配置，请修改此文件。 - -![](./figures/studio4.png) - -### 3.5 重新生成工程 - -* MDK5 ：重新生成工程需要使用 Env 工具。 - -* RT-Thread Studio：使用 Env 工具/同步 scons 配置至项目 - -同步 scons 配置至项目： - -![](./figures/studio5.png) - -首先打开 RT-Thread Studio ，在 IDE 的左上角点击 `文件—>导入—>RT-Thread Bsp 到工作空间中` - -![](./figures/studio1.png) +选择 dist 出来工程的路径： ![](./figures/studio2.png) +点击 finsh 即可导入到 Studio 中： + +![](./figures/studio2-1.png) + 导入成功后，文件资源管理器窗口中会显示如下结构，其中 RT-Thread Settings 为图形化工程配置文件，双击打开即可。 ![](./figures/studio3.png) @@ -259,10 +271,6 @@ RT-Thread Settings 中硬件相关配置是在 board/Kconfig 中描述的。移 #### 3.6.2 重新生成 MDK 工程 -使用上述方法/点击同步 scons 配置至项目 - -#### 3.5.2 重新生成 MDK 工程 - 以重新生成 MDK 工程为例，介绍如何重新生成 BSP 工程。 使用 env 工具输入命令 `scons --target=mdk5` 重新生成工程，如下图所示： diff --git a/bsp/Infineon/docs/figures/Kconfig.png b/bsp/Infineon/docs/figures/Kconfig.png index 1bee388d1ce7205f61415528aad8ea84c55c84af..6199d8f4e47ced8c0aa5116898134411e9402a77 100644 GIT binary patch literal 77951 zcma%iV|ZNM*LNB;wr$&H!$ytS*tXHwc4IfToixS-jcwb0C%y0g^XmEVT-SU$bIzH) z_u6Z(AJ&9@laqjl!GQq*0fCp26jcNP0W}5z0V9L@47~FAqNWJ~LIffuDy;05anj-I zraZfN{#sL^l7Q_KNcMx}^OoL^f-q9HAGt`9BGaS|nph>~-gNHKR0M7Wht5bnm<$Y# z;PikJ0mjb4e#fnv#(J#Ns*o&7tXQEa5t;!}6460DJT%FNIHrVOvvc<`9rt5d{9Tj@ zW8h~1XZ!DCSq<~8_e+*{PkWu`4R`1X6#G75L{K8}*HYQ(3g*~h9AB`CZZgjIekv>F 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z@6A44?in!V0}#+G*X1(H%_4!zGKou8^hWsnw8n9C>Y*uT-XNyl&;6&mfgpL@9-e=* zU?*YldZ^@20v)jI1X_V>Q8jBjbbW7M`WWN6jYaQE=cxgD0B!Lo0g2HpKYW8A(%{4< zJDeO16XBJj96^b&0@A<34(HRp&Sp5-?8VX+tpbel~RWC~tro?WzcS};#M#6Im3uCgAb|a@5aDzI=0tOgh4T=r?S-gX&ou87+k0 zZ?@=}^5P0!wVfo7Ve08K>Y1~I#VUFx_nC7C>+s6*T5NtWeu_`n9j51BhPegX5ANDi z!XJGKEfHPmv>LuGLw&K@c|=R=f$lkpI=FCNq|XCgxkmo*7D~XUddVWuO}5DCONui@ zq80t{U8yNtU^a`^He$~Rrp?O)Duc+pnH+X}f6V22iD=S;*@Z+bfAuZ(-SfRwh(K*#IU6^W_u|d|LxH)>`f020$<$`bO`G1shiX%-sHYTS204vH@B<G4PFb$-UCSB9@ceZLkX-V_%o}UcV!Ma*TdD5HkO-RaE8)EPm z_-;l?`}|X)d@!F)Xkxp&{xTO=3k&>;YR^sUnwf+D)d!WO$lvdR^u7jSYJ8DHQ-m@7 z6S%@dX!?Pi6LNrT@_s+*p?12dpG0W&qDJ?r7YZaJvq;S8%TqV1Kk0OzV-v`&_(#TP zaPePM;rHiezT|xq&tQ^K-ANiq!qv38=6&0aMJ(`%Q8s-}x!4YBI|B??x;F}=; zxqQy4Lo1zW>Ffu$>XI1A9-D-B9b5O zN&Wmpr+7cLE-k(A@oBr8U##bBSj0WN!_!RN%GZ+(u|l`Xnky)9(R=H$xOHcNOg;wVISAC1oZ$C;!stQ*`5u2 z9G59-=06D^JqPGX5!OeoQCW2~(*Wd3`Z`ArT66Se-$bu}tdC|_q~rk+`PD`1Gd5^# zgN`!~74PTzZ?NiszTYz+3ro=TSlj+Gb0sF%J+Ikvvs^tA){UXtWwuJwKQ2d23+onH=!q5T#}#!(#@==N)KR6Vt^}FsrNc`J@*k>iBRs9j8=*~d;)z$ zjcmMt!FdLVH{=9j0#x^0^nZrB9-FFWpjvt2gMG=$#`Ch-JH~)#&;|FFd9H}8A2>Y8 zqhF(*cB@`x+tQ<8Y+=%>bG1qVKN@|Ws&h`u3>Kphffyt|;PP;{6TtQM#DNp;C=w#F KkixGz-v0}fpyJd3 diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/SConscript b/bsp/Infineon/libraries/IFX_PSOC6_HAL/SConscript index 53bbb37b2c..5639f0058b 100644 --- a/bsp/Infineon/libraries/IFX_PSOC6_HAL/SConscript +++ b/bsp/Infineon/libraries/IFX_PSOC6_HAL/SConscript @@ -20,10 +20,6 @@ src = Split(''' mtb-hal-cat1/source/cyhal_utils.c mtb-hal-cat1/source/cyhal_lptimer.c mtb-hal-cat1/source/cyhal_irq_psoc.c - mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_02.c - mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c - mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c - mtb-pdl-cat1/drivers/source/cy_scb_common.c mtb-pdl-cat1/drivers/source/cy_sysclk.c mtb-pdl-cat1/drivers/source/cy_systick.c mtb-pdl-cat1/drivers/source/cy_gpio.c @@ -37,18 +33,14 @@ src = Split(''' mtb-pdl-cat1/drivers/source/cy_ipc_drv.c mtb-pdl-cat1/drivers/source/cy_trigmux.c mtb-pdl-cat1/drivers/source/cy_prot.c - TARGET_CY8CKIT-062S2-43012/cybsp.c - TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c - TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c - TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c - TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c - TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c - TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c - TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c - lib/cy_capsense.lib + mtb-pdl-cat1/drivers/source/cy_scb_common.c ''') -src += Glob(cwd + '/psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c') +if GetDepend(['SOC_CY8C624ABZI_S2D44']): + src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c'] + src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_02.c'] + src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c'] + src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c') if GetDepend(['RT_USING_SERIAL']): src += ['retarget-io/cy_retarget_io.c'] @@ -59,8 +51,8 @@ if GetDepend(['RT_USING_ADC']): src += ['mtb-hal-cat1/source/cyhal_dma_dw.c'] src += ['mtb-hal-cat1/source/cyhal_dma_dmac.c'] src += ['mtb-hal-cat1/source/cyhal_dma.c'] - src += ['mtb-hal-cat1/source/cyhal_analog_common.c'] src += ['mtb-hal-cat1/source/cyhal_adc_sar.c'] + src += ['mtb-hal-cat1/source/cyhal_analog_common.c'] src += ['mtb-pdl-cat1/drivers/source/cy_dma.c'] src += ['mtb-pdl-cat1/drivers/source/cy_sar.c'] src += ['mtb-pdl-cat1/drivers/source/cy_dmac.c'] @@ -70,15 +62,6 @@ if GetDepend(['RT_USING_SDIO']): src += ['mtb-hal-cat1/source/cyhal_sdhc.c'] src += ['mtb-pdl-cat1/drivers/source/cy_sd_host.c'] -if GetDepend(['RT_USING_QSPI']): - src += ['mtb-hal-cat1/source/cyhal_qspi.c'] - src += ['mtb-pdl-cat1/drivers/source/cy_dma.c'] - src += ['mtb-pdl-cat1/drivers/source/cy_smif.c'] - src += ['mtb-pdl-cat1/drivers/source/cy_smif_sfdp.c'] - src += ['mtb-pdl-cat1/drivers/source/cy_smif_memslot.c'] - src += ['mtb_shared/serial-flash/cy_serial_flash_qspi.c'] - src += ['TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c'] - if GetDepend(['RT_USING_PWM']): src += ['mtb-hal-cat1/source/cyhal_pwm.c'] src += ['mtb-hal-cat1/source/cyhal_timer.c'] @@ -93,23 +76,13 @@ if GetDepend(['RT_USING_SPI']): if GetDepend(['RT_USING_I2C']): src += ['mtb-hal-cat1/source/cyhal_i2c.c'] -if GetDepend('BSP_USING_USBD'): - src += ['mtb_shared/usbdev/cy_usb_dev.c'] - src += ['mtb_shared/usbdev/cy_usb_dev_hid.c'] - src += ['mtb-hal-cat1/source/cyhal_usb_dev.c'] - src += ['mtb-pdl-cat1/drivers/source/cy_dma.c'] - src += ['mtb-pdl-cat1/drivers/source/cy_usbfs_dev_drv.c'] - src += ['mtb-pdl-cat1/drivers/source/cy_usbfs_dev_drv_io.c'] - src += ['mtb-pdl-cat1/drivers/source/cy_usbfs_dev_drv_io_dma.c'] - src += ['TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_usbdev.c'] - if GetDepend('BSP_USING_RTC'): - src += ['mtb-pdl-cat1/drivers/source/cy_rtc.c'] src += ['mtb-hal-cat1/source/cyhal_rtc.c'] + src += ['mtb-pdl-cat1/drivers/source/cy_rtc.c'] if GetDepend('BSP_USING_ON_CHIP_FLASH'): - src += ['mtb-pdl-cat1/drivers/source/cy_flash.c'] src += ['mtb-hal-cat1/source/cyhal_flash.c'] + src += ['mtb-pdl-cat1/drivers/source/cy_flash.c'] if GetDepend(['BSP_USING_SLIDER']): src += ['capsense/cy_capsense_control.c'] @@ -123,7 +96,8 @@ if GetDepend(['BSP_USING_SLIDER']): src += ['capsense/cy_capsense_centroid.c'] src += ['capsense/cy_capsense_filter.c'] src += ['mtb-pdl-cat1/drivers/source/cy_csd.c'] - src += ['TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c'] + if rtconfig.PLATFORM in ['armclang']: + src += ['lib/cy_capsense.lib'] if GetDepend(['RT_USING_WDT']): src += ['mtb-pdl-cat1/drivers/source/cy_wdt.c'] @@ -135,21 +109,21 @@ if GetDepend(['RT_USING_DAC']): if GetDepend(['RT_USING_HWTIMER']): src += ['mtb-hal-cat1/source/cyhal_timer.c'] -path = [cwd + '/capsense', - cwd + '/psoc6cm0p', - cwd + '/retarget-io', +path = [cwd + '/retarget-io', cwd + '/core-lib/include', - cwd + '/mtb_shared/serial-flash', cwd + '/mtb_shared/usbdev', cwd + '/mtb_shared/csdidac', + cwd + '/mtb_shared/serial-flash', cwd + '/mtb-pdl-cat1/cmsis/include', cwd + '/mtb-pdl-cat1/drivers/include', - cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include', cwd + '/mtb-hal-cat1/include_pvt', - cwd + '/mtb-hal-cat1/include', - cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include', - cwd + '/TARGET_CY8CKIT-062S2-43012', - cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource'] + cwd + '/mtb-hal-cat1/include'] + +if GetDepend(['SOC_CY8C624ABZI_S2D44']): + path += [cwd + '/psoc6cm0p'] + path += [cwd + '/capsense'] + path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include'] + path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include'] group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path) diff --git a/bsp/Infineon/libraries/Kconfig b/bsp/Infineon/libraries/Kconfig index e5f41e0579..ea38eed86a 100644 --- a/bsp/Infineon/libraries/Kconfig +++ b/bsp/Infineon/libraries/Kconfig @@ -1,7 +1,7 @@ config SOC_FAMILY_IFX bool -config SOC_SERIES_IFX_PSOC6 +config SOC_SERIES_IFX_PSOC62 bool select ARCH_ARM_CORTEX_M4 select SOC_FAMILY_IFX diff --git a/bsp/Infineon/libraries/templates/PSOC62/.config b/bsp/Infineon/libraries/templates/PSOC62/.config index 241a4dc5e7..ef095755d4 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/.config +++ b/bsp/Infineon/libraries/templates/PSOC62/.config @@ -60,6 +60,7 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # # Memory Management # +CONFIG_RT_PAGE_MAX_ORDER=11 CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set @@ -117,7 +118,6 @@ CONFIG_FINSH_USING_DESCRIPTION=y CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DFS is not set # CONFIG_RT_USING_FAL is not set -# CONFIG_RT_USING_LWP is not set # # Device Drivers @@ -706,12 +706,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set CONFIG_SOC_FAMILY_IFX=y -CONFIG_SOC_SERIES_IFX_PSOC6=y +CONFIG_SOC_SERIES_IFX_PSOC62=y # # Hardware Drivers Config # -CONFIG_SOC_IFX_PSOC6_43012=y +CONFIG_SOC_CY8C624ABZI_S2D44=y # # Onboard Peripheral Drivers diff --git a/bsp/Infineon/libraries/templates/PSOC62/.cproject b/bsp/Infineon/libraries/templates/PSOC62/.cproject index 9e31c68f0b..c941cd34df 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/.cproject +++ b/bsp/Infineon/libraries/templates/PSOC62/.cproject @@ -66,8 +66,6 @@ - - @@ -81,6 +79,8 @@ + + @@ -88,6 +88,7 @@ + @@ -110,6 +111,7 @@ @@ -119,7 +121,7 @@ @@ -177,8 +179,6 @@ - - @@ -192,6 +192,8 @@ + + @@ -199,6 +201,7 @@ + @@ -212,7 +215,7 @@ - + @@ -232,7 +235,7 @@ - + diff --git a/bsp/Infineon/libraries/templates/PSOC62/.project b/bsp/Infineon/libraries/templates/PSOC62/.project index 49424bb16d..5fb80e1bbf 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/.project +++ b/bsp/Infineon/libraries/templates/PSOC62/.project @@ -1,6 +1,6 @@ - 1111 + project diff --git a/bsp/Infineon/libraries/templates/PSOC62/.settings/language.settings.xml b/bsp/Infineon/libraries/templates/PSOC62/.settings/language.settings.xml index 10c41d4686..9e371a6fd8 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/.settings/language.settings.xml +++ b/bsp/Infineon/libraries/templates/PSOC62/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + diff --git a/bsp/Infineon/libraries/templates/PSOC62/.settings/projcfg.ini b/bsp/Infineon/libraries/templates/PSOC62/.settings/projcfg.ini index f3fd2c88e5..a75c8041be 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/.settings/projcfg.ini +++ b/bsp/Infineon/libraries/templates/PSOC62/.settings/projcfg.ini @@ -1,5 +1,5 @@ #RT-Thread Studio Project Configuration -#Fri Jan 06 10:38:41 CST 2023 +#Thu Jan 12 11:11:44 CST 2023 project_type=rt-thread chip_name=CY8C624ABZI os_branch=full @@ -14,7 +14,7 @@ project_base_bsp=true hardware_adapter=KitProg3 project_name=1111 is_base_example_project=False -board_name=PSOC62-IFX-PROTO-KIT +board_name=psoc6-cy8ckit-062S2-43012 device_vendor=Infineon -bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0 bsp_version=1.0.0 +bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0 diff --git a/bsp/Infineon/libraries/templates/PSOC62/board/Kconfig b/bsp/Infineon/libraries/templates/PSOC62/board/Kconfig index b186c44a0d..42927fbd98 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/board/Kconfig +++ b/bsp/Infineon/libraries/templates/PSOC62/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_IFX_PSOC6_43012 +config SOC_CY8C624ABZI_S2D44 bool - select SOC_SERIES_IFX_PSOC6 + select SOC_SERIES_IFX_PSOC62 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y diff --git a/bsp/Infineon/libraries/templates/PSOC62/board/SConscript b/bsp/Infineon/libraries/templates/PSOC62/board/SConscript index a8db6b8b1e..f9894af0d8 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/board/SConscript +++ b/bsp/Infineon/libraries/templates/PSOC62/board/SConscript @@ -28,17 +28,13 @@ path += [cwd + '/ports'] startup_path_prefix = SDK_LIB if rtconfig.PLATFORM in ['gcc']: - src += [startup_path_prefix + - '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S'] src += [startup_path_prefix + '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += [startup_path_prefix + - '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S'] +elif rtconfig.PLATFORM in ['armclang']: src += [startup_path_prefix + '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S'] -CPPDEFINES = ['CY8C624ABZI_S2D44', 'IFX_PSOC6_43012', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS'] +CPPDEFINES = ['CY8C624ABZI_S2D44', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS'] group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/Infineon/libraries/templates/PSOC62/libs/SConscript b/bsp/Infineon/libraries/templates/PSOC62/libs/SConscript new file mode 100644 index 0000000000..510e7267a0 --- /dev/null +++ b/bsp/Infineon/libraries/templates/PSOC62/libs/SConscript @@ -0,0 +1,26 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + print("\nThe current project does not support IAR build\n") + Return('group') +elif rtconfig.PLATFORM in ['gcc', 'armclang']: + src += [cwd + '/TARGET_CY8CKIT-062S2-43012/cybsp.c'] + src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c'] + src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c') + + CPPPATH = [ cwd + '/TARGET_CY8CKIT-062S2-43012', + cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource'] + if rtconfig.PLATFORM in ['gcc']: + src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S'] + elif rtconfig.PLATFORM in ['armclang']: + src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S'] + +group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/.gitignore b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/.gitignore similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/.gitignore rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/.gitignore diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.modus b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.modus similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.modus rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.modus diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/EULA b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/EULA similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/EULA rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/EULA diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/LICENSE b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/LICENSE similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/LICENSE rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/LICENSE diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/README.md b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/README.md similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/README.md rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/README.md diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/RELEASE.md b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/RELEASE.md similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/RELEASE.md rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/RELEASE.md diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp.c b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/cybsp.c similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp.c rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/cybsp.c diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/cybsp.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/cybsp.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp_types.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/cybsp_types.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp_types.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/cybsp_types.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/system_psoc6.h b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/system_psoc6.h similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/system_psoc6.h rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/system_psoc6.h diff --git a/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/version.xml b/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/version.xml similarity index 100% rename from bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/version.xml rename to bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/version.xml diff --git a/bsp/Infineon/libraries/templates/PSOC62/rtconfig.h b/bsp/Infineon/libraries/templates/PSOC62/rtconfig.h index c7735db3ea..c073228c56 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/rtconfig.h +++ b/bsp/Infineon/libraries/templates/PSOC62/rtconfig.h @@ -36,6 +36,7 @@ /* Memory Management */ +#define RT_PAGE_MAX_ORDER 11 #define RT_USING_MEMPOOL #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP @@ -197,11 +198,11 @@ /* Project libraries */ #define SOC_FAMILY_IFX -#define SOC_SERIES_IFX_PSOC6 +#define SOC_SERIES_IFX_PSOC62 /* Hardware Drivers Config */ -#define SOC_IFX_PSOC6_43012 +#define SOC_CY8C624ABZI_S2D44 /* Onboard Peripheral Drivers */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.config b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.config index 624e3f07d1..4bba2a1399 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.config +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -59,6 +60,7 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # # Memory Management # +CONFIG_RT_PAGE_MAX_ORDER=11 CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set @@ -77,16 +79,19 @@ CONFIG_RT_USING_HEAP=y # CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart5" -CONFIG_RT_VER_NUM=0x40101 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x50000 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -113,12 +118,12 @@ CONFIG_FINSH_USING_DESCRIPTION=y CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DFS is not set # CONFIG_RT_USING_FAL is not set -# CONFIG_RT_USING_LWP is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y @@ -133,10 +138,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set @@ -144,10 +153,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set # # Using USB @@ -426,6 +438,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_HASH_MATCH is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set # # system packages @@ -461,7 +474,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set @@ -664,68 +676,42 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QPARAM is not set # -# Privated Packages of RealThread +# Arduino libraries # -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set +# CONFIG_PKG_USING_RTDUINO is not set # -# Network Utilities +# Sensor libraries # -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set -# CONFIG_PKG_USING_RT_CMSIS_DAP is not set -# CONFIG_PKG_USING_SMODULE is not set -# CONFIG_PKG_USING_SNFD is not set -# CONFIG_PKG_USING_UDBD is not set -# CONFIG_PKG_USING_BENCHMARK is not set -# CONFIG_PKG_USING_UBJSON is not set -# CONFIG_PKG_USING_DATATYPE is not set -# CONFIG_PKG_USING_FASTFS is not set -# CONFIG_PKG_USING_RIL is not set -# CONFIG_PKG_USING_WATCH_DCM_SVC is not set -# CONFIG_PKG_USING_WATCH_APP_FWK is not set -# CONFIG_PKG_USING_GUI_TEST is not set -# CONFIG_PKG_USING_PMEM is not set -# CONFIG_PKG_USING_LWRDP is not set -# CONFIG_PKG_USING_MASAN is not set -# CONFIG_PKG_USING_BSDIFF_LIB is not set -# CONFIG_PKG_USING_PRC_DIFF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set # -# RT-Thread Smart +# Display libraries # -# CONFIG_PKG_USING_UKERNEL is not set -# CONFIG_PKG_USING_TRACE_AGENT is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set + +# +# Timing libraries +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Project libraries +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set CONFIG_SOC_FAMILY_IFX=y -CONFIG_SOC_SERIES_IFX_PSOC6=y +CONFIG_SOC_SERIES_IFX_PSOC62=y # # Hardware Drivers Config # -CONFIG_SOC_IFX_PSOC6_43012=y +CONFIG_SOC_CY8C624ABZI_S2D44=y # # Onboard Peripheral Drivers @@ -743,7 +729,11 @@ CONFIG_BSP_USING_UART=y # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_UART4 is not set CONFIG_BSP_USING_UART5=y -# CONFIG_BSP_USING_PWM is not set +CONFIG_BSP_USING_PWM=y +CONFIG_BSP_USING_PWM0=y +CONFIG_BSP_USING_PWM0_CH3=y +CONFIG_BSP_USING_PWM0_PORT13=y +# CONFIG_BSP_USING_PWM0_CH7 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_SDMMC is not set diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.cproject b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.cproject index 9e31c68f0b..c941cd34df 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.cproject +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.cproject @@ -66,8 +66,6 @@ - - @@ -81,6 +79,8 @@ + + @@ -88,6 +88,7 @@ + @@ -110,6 +111,7 @@ @@ -119,7 +121,7 @@ @@ -177,8 +179,6 @@ - - @@ -192,6 +192,8 @@ + + @@ -199,6 +201,7 @@ + @@ -212,7 +215,7 @@ - + @@ -232,7 +235,7 @@ - + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.project b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.project index 49424bb16d..5fb80e1bbf 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.project +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.project @@ -1,6 +1,6 @@ - 1111 + project diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/language.settings.xml b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/language.settings.xml index 10c41d4686..4b5091d23d 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/language.settings.xml +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/projcfg.ini b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/projcfg.ini index f3fd2c88e5..a75c8041be 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/projcfg.ini +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/projcfg.ini @@ -1,5 +1,5 @@ #RT-Thread Studio Project Configuration -#Fri Jan 06 10:38:41 CST 2023 +#Thu Jan 12 11:11:44 CST 2023 project_type=rt-thread chip_name=CY8C624ABZI os_branch=full @@ -14,7 +14,7 @@ project_base_bsp=true hardware_adapter=KitProg3 project_name=1111 is_base_example_project=False -board_name=PSOC62-IFX-PROTO-KIT +board_name=psoc6-cy8ckit-062S2-43012 device_vendor=Infineon -bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0 bsp_version=1.0.0 +bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0 diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/Kconfig b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/Kconfig index b186c44a0d..42927fbd98 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/Kconfig +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_IFX_PSOC6_43012 +config SOC_CY8C624ABZI_S2D44 bool - select SOC_SERIES_IFX_PSOC6 + select SOC_SERIES_IFX_PSOC62 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/SConscript b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/SConscript index a8db6b8b1e..f9894af0d8 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/SConscript +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/SConscript @@ -28,17 +28,13 @@ path += [cwd + '/ports'] startup_path_prefix = SDK_LIB if rtconfig.PLATFORM in ['gcc']: - src += [startup_path_prefix + - '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S'] src += [startup_path_prefix + '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += [startup_path_prefix + - '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S'] +elif rtconfig.PLATFORM in ['armclang']: src += [startup_path_prefix + '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S'] -CPPDEFINES = ['CY8C624ABZI_S2D44', 'IFX_PSOC6_43012', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS'] +CPPDEFINES = ['CY8C624ABZI_S2D44', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS'] group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/SConscript b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/SConscript new file mode 100644 index 0000000000..510e7267a0 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/SConscript @@ -0,0 +1,26 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + print("\nThe current project does not support IAR build\n") + Return('group') +elif rtconfig.PLATFORM in ['gcc', 'armclang']: + src += [cwd + '/TARGET_CY8CKIT-062S2-43012/cybsp.c'] + src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c'] + src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c') + + CPPPATH = [ cwd + '/TARGET_CY8CKIT-062S2-43012', + cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource'] + if rtconfig.PLATFORM in ['gcc']: + src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S'] + elif rtconfig.PLATFORM in ['armclang']: + src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S'] + +group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/.gitignore b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/.gitignore new file mode 100644 index 0000000000..41c4a77ddf --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/.gitignore @@ -0,0 +1,9 @@ +docs + +# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 2) +$(SEARCH_wifi-host-driver)/WiFi_Host_Driver/resources/nvram_deprecated/ +$(SEARCH_bluetooth-freertos)/firmware_deprecated/ + +# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 1) +../wifi-host-driver/WiFi_Host_Driver/resources/nvram_deprecated/ +../bluetooth-freertos/firmware_deprecated/ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c new file mode 100644 index 0000000000..154ddbd38f --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -0,0 +1,39 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_system(); + init_cycfg_clocks(); + init_cycfg_routing(); + init_cycfg_peripherals(); + init_cycfg_pins(); +} diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h new file mode 100644 index 0000000000..044dc8162e --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_system.h" +#include "cycfg_connectivity_bt.h" +#include "cycfg_clocks.h" +#include "cycfg_routing.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp new file mode 100644 index 0000000000..eeff5c9b0d --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -0,0 +1,29 @@ +/******************************************************************************* +* File Name: cycfg.timestamp +* +* Description: +* Sentinel file for determining if generated source is up to date. +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c new file mode 100644 index 0000000000..0361aa1b4b --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c @@ -0,0 +1,877 @@ +/******************************************************************************* +* File Name: cycfg_capsense.c +* +* Description: +* CAPSENSE Middleware configuration +* This file should not be modified. It was automatically generated by +* CapSense Configurator 4.0.0.6195 +* +******************************************************************************** +* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company) +* or an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cycfg_capsense.h" + +#if !defined(CY_DISABLE_CAPSENSE) + +#if (CY_CAPSENSE_CORE == __CORTEX_M) + +#ifndef CSD_CMODPADS_PORT +#define CSD_CMODPADS_PORT 0xFF +#endif +#ifndef CSD_CMODPADS_PIN +#define CSD_CMODPADS_PIN 0xFF +#endif +#ifndef CSD_CSH_TANKPADS_PORT +#define CSD_CSH_TANKPADS_PORT 0xFF +#endif +#ifndef CSD_CSH_TANKPADS_PIN +#define CSD_CSH_TANKPADS_PIN 0xFF +#endif +#ifndef CSD_CSHIELDPADS_PORT +#define CSD_CSHIELDPADS_PORT 0xFF +#endif +#ifndef CSD_CSHIELDPADS_PIN +#define CSD_CSHIELDPADS_PIN 0xFF +#endif +#ifndef CSD_VREF_EXT_PORT +#define CSD_VREF_EXT_PORT 0xFF +#endif +#ifndef CSD_VREF_EXT_PIN +#define CSD_VREF_EXT_PIN 0xFF +#endif + +static cy_stc_capsense_internal_context_t cy_capsense_internalContext; +static cy_stc_active_scan_sns_t cy_capsense_activeScanSns; + +#if (CY_CAPSENSE_DEBOUNCE_SIZE > 0) + static uint8_t cy_capsense_debounce[CY_CAPSENSE_DEBOUNCE_SIZE] = {0}; +#endif + +#if (CY_CAPSENSE_NOISE_ENVELOPE_SIZE > 0) + static cy_stc_capsense_smartsense_csd_noise_envelope_t cy_capsense_noiseEnvelope[CY_CAPSENSE_NOISE_ENVELOPE_SIZE]; +#endif + +#if (CY_CAPSENSE_RAW_HISTORY_SIZE > 0) + static uint16_t cy_capsense_rawFilterHistory[CY_CAPSENSE_RAW_HISTORY_SIZE] = {0}; +#endif + +#if (CY_CAPSENSE_IIR_HISTORY_LOW_SIZE > 0) + static uint8_t cy_capsense_iirHistoryLow[CY_CAPSENSE_IIR_HISTORY_LOW_SIZE] = {0}; +#endif + +#if (CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE > 0) + static cy_stc_capsense_position_t cy_capsense_positionFilterHistory[CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE]; +#endif + +#if (CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE > 0) + static cy_stc_capsense_touch_t cy_capsense_touchFilterHistory[CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE] = + { + }; +#endif + +#if (CY_CAPSENSE_DIPLEX_SIZE > 0) + static const uint8_t cy_capsense_diplexTable[CY_CAPSENSE_DIPLEX_SIZE] = + { + }; +#endif + +#if (CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE > 0) + static uint16_t cy_capsense_csdTouchBuffer[CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE] = {0}; +#endif + +#if (CY_CAPSENSE_CSX_TOUCH_BUFFER_ENABLE > 0) + static cy_stc_capsense_csx_touch_buffer_t cy_capsense_csxTouchBuffer; +#endif + +#if (CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE > 0) + static cy_stc_capsense_csx_touch_history_t cy_capsense_csxTouchHistory[CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE] = + { + }; +#endif + +#if (CY_CAPSENSE_BALLISTIC_WIDGET_COUNT > 0) + static cy_stc_capsense_ballistic_context_t cy_capsense_ballisticContext[CY_CAPSENSE_BALLISTIC_WIDGET_COUNT]; +#endif + +#if (CY_CAPSENSE_GESTURE_WIDGET_COUNT > 0) + static cy_stc_capsense_gesture_context_t cy_capsense_gestureContext[CY_CAPSENSE_GESTURE_WIDGET_COUNT]; +#endif + +#if (CY_CAPSENSE_BIST_SUPPORTED) +#if (CY_CAPSENSE_BIST_EN != 0) + uint16_t cy_capsense_bslnInv[CY_CAPSENSE_SENSOR_COUNT * CY_CAPSENSE_MFS_CH_NUMBER]; + uint32_t cy_capsense_eltdCap[CY_CAPSENSE_ELTD_COUNT]; + #if (CY_CAPSENSE_MW_VERSION >= 300) + uint32_t cy_capsense_snsCap[CY_CAPSENSE_SENSOR_COUNT]; + #endif + uint16_t cy_capsense_wdgtCrc[CY_CAPSENSE_WIDGET_COUNT]; +#endif +#endif + +static const cy_stc_capsense_common_config_t cy_capsense_commonConfig = +{ + .cpuClkHz = CY_CAPSENSE_CPU_CLK, + .periClkHz = CY_CAPSENSE_PERI_CLK, + .vdda = CY_CAPSENSE_VDDA_MV, + .numPin = CY_CAPSENSE_PIN_COUNT, + .numSns = CY_CAPSENSE_SENSOR_COUNT, + .numWd = CY_CAPSENSE_WIDGET_COUNT, + .csdEn = CY_CAPSENSE_ENABLE, + .csxEn = CY_CAPSENSE_ENABLE, + #if (CY_CAPSENSE_MW_VERSION < 300) + .mfsEn = CY_CAPSENSE_DISABLE, + #endif + #if (CY_CAPSENSE_BIST_SUPPORTED) + .bistEn = CY_CAPSENSE_DISABLE, + #endif + .positionFilterEn = CY_CAPSENSE_DISABLE, + .periDividerType = (uint8_t)CY_CAPSENSE_PERI_DIV_TYPE, + .periDividerIndex = CY_CAPSENSE_PERI_DIV_INDEX, + .analogWakeupDelay = 25u, + .ssIrefSource = CY_CAPSENSE_IREF_SRSS, + .ssVrefSource = CY_CAPSENSE_VREF_SRSS, + .proxTouchCoeff = 300u, + .swSensorAutoResetEn = CY_CAPSENSE_DISABLE, + .portCmodPadNum = CSD_CMODPADS_PORT, + .pinCmodPad = CSD_CMODPADS_PIN, + .portCshPadNum = CSD_CSH_TANKPADS_PORT, + .pinCshPad = CSD_CSH_TANKPADS_PIN, + .portShieldPadNum = CSD_CSHIELDPADS_PORT, + .pinShieldPad = CSD_CSHIELDPADS_PIN, + .portVrefExtPadNum = CSD_VREF_EXT_PORT, + .pinVrefExtPad = CSD_VREF_EXT_PIN, + .portCmodNum = Cmod_PORT_NUM, + .idacGainTable = { + {0x01000000u, 37500u}, + {0x03000000u, 75000u}, + {0x01400000u, 300000u}, + {0x03400000u, 600000u}, + {0x01800000u, 2400000u}, + {0x03800000u, 4800000u}, + }, + .ptrCsdBase = CSD0, + .ptrCsdContext = &cy_csd_0_context, + .portCmod = Cmod_PORT, + .portCsh = NULL, + .portCintA = CintA_PORT, + .portCintB = CintB_PORT, + .pinCmod = Cmod_PIN, + .portCshNum = 0u, + .pinCsh = 0u, + .pinCintA = CintA_PIN, + .pinCintB = CintB_PIN, + .csdShieldEn = CY_CAPSENSE_DISABLE, + .csdInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND, + #if (CY_CAPSENSE_MW_VERSION >= 300) + .csxInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND, + #endif + .csdShieldDelay = CY_CAPSENSE_SH_DELAY_0NS, + .csdVref = 0u, + .csdRConst = 1000u, + .csdCTankShieldEn = CY_CAPSENSE_DISABLE, + .csdShieldNumPin = 0u, + .csdShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_MEDIUM, + .csdInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM, + .csdChargeTransfer = CY_CAPSENSE_IDAC_SOURCING, + .csdRawTarget = 85u, + .csdAutotuneEn = CY_CAPSENSE_CSD_SS_HWTH_EN, + .csdIdacAutocalEn = CY_CAPSENSE_ENABLE, + .csdIdacAutoGainEn = CY_CAPSENSE_ENABLE, + .csdCalibrationError = 10u, + .csdIdacGainInitIndex = 4u, + .csdIdacMin = 20u, + .csdIdacCompEn = CY_CAPSENSE_ENABLE, + .csdFineInitTime = 10u, + .csdIdacRowColAlignEn = CY_CAPSENSE_ENABLE, + .csdMfsDividerOffsetF1 = 1u, + .csdMfsDividerOffsetF2 = 2u, + .csxRawTarget = 40u, + .csxIdacGainInitIndex = 2u, + .csxIdacAutocalEn = CY_CAPSENSE_ENABLE, + .csxCalibrationError = 20u, + .csxFineInitTime = 10u, + .csxInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM, + .csxScanSwRes = CY_CAPSENSE_INIT_SW_RES_LOW, + .csxInitShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_MEDIUM, + .csxScanShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_LOW, + .csxMfsDividerOffsetF1 = 1u, + .csxMfsDividerOffsetF2 = 2u, +}; + +#if (CY_CAPSENSE_MW_VERSION < 300) + static const cy_stc_capsense_fptr_config_t cy_capsense_fptrConfig = + { + #if (CY_CAPSENSE_CSD_EN == 0) + .fptrCSDSetupWidget = NULL, + .fptrCSDScan = NULL, + .fptrDpProcessCsdWidgetRawCounts = NULL, + .fptrDpProcessCsdWidgetStatus = NULL, + .fptrCSDDisableMode = NULL, + .fptrCSDInitialize = NULL, + .fptrCSDScanISR = NULL, + #else + .fptrCSDSetupWidget = &Cy_CapSense_CSDSetupWidget, + .fptrCSDScan = &Cy_CapSense_CSDScan, + .fptrDpProcessCsdWidgetRawCounts = &Cy_CapSense_DpProcessCsdWidgetRawCounts, + .fptrDpProcessCsdWidgetStatus = &Cy_CapSense_DpProcessCsdWidgetStatus, + .fptrCSDDisableMode = &Cy_CapSense_CSDDisableMode, + .fptrCSDInitialize = &Cy_CapSense_CSDInitialize, + .fptrCSDScanISR = &Cy_CapSense_CSDScanISR, + #endif + + #if (CY_CAPSENSE_CSX_EN == 0) + .fptrCSXSetupWidget = NULL, + .fptrCSXScan = NULL, + .fptrDpProcessCsxWidgetRawCounts = NULL, + .fptrDpProcessCsxWidgetStatus = NULL, + .fptrCSXInitialize = NULL, + .fptrCSXDisableMode = NULL, + .fptrCSXScanISR = NULL, + #else + .fptrCSXSetupWidget = &Cy_CapSense_CSXSetupWidget, + .fptrCSXScan = &Cy_CapSense_CSXScan, + .fptrDpProcessCsxWidgetRawCounts = &Cy_CapSense_DpProcessCsxWidgetRawCounts, + .fptrDpProcessCsxWidgetStatus = &Cy_CapSense_DpProcessCsxWidgetStatus, + .fptrCSXInitialize = &Cy_CapSense_CSXInitialize, + .fptrCSXDisableMode = &Cy_CapSense_CSXDisableMode, + .fptrCSXScanISR = &Cy_CapSense_CSXScanISR, + #endif + + #if (CY_CAPSENSE_ADAPTIVE_FILTER_EN == 0) + .fptrAdaptiveFilterInitializeLib = NULL, + .fptrAdaptiveFilterRunLib = NULL, + #else + .fptrAdaptiveFilterInitializeLib = &Cy_CapSense_AdaptiveFilterInitialize_Lib, + .fptrAdaptiveFilterRunLib = &Cy_CapSense_AdaptiveFilterRun_Lib, + #endif + + #if (CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN == 0) + .fptrBallisticMultiplierLib = NULL, + #else + .fptrBallisticMultiplierLib = &Cy_CapSense_BallisticMultiplier_Lib, + #endif + + #if (CY_CAPSENSE_RAWCOUNT_FILTER_EN == 0) + .fptrInitializeAllFilters = NULL, + .fptrFtRunEnabledFiltersInternal = NULL, + #else + .fptrInitializeAllFilters = &Cy_CapSense_InitializeAllFilters, + .fptrFtRunEnabledFiltersInternal = &Cy_CapSense_FtRunEnabledFiltersInternal, + #endif + + #if (CY_CAPSENSE_CSD_POSITION_FILTER_EN == 0) + .fptrProcessPositionFilters = NULL, + #else + .fptrProcessPositionFilters = &Cy_CapSense_ProcessPositionFilters, + #endif + + #if ((CY_CAPSENSE_CSX_POSITION_FILTER_EN == 0) && (CY_CAPSENSE_CSD_POSITION_FILTER_EN == 0)) + .fptrRunPositionFilters = NULL, + .fptrInitPositionFilters = NULL, + #else + .fptrRunPositionFilters = &Cy_CapSense_RunPositionFilters, + .fptrInitPositionFilters = &Cy_CapSense_InitPositionFilters, + #endif + + #if ((CY_CAPSENSE_CSD_BUTTON_EN == 0) && \ + (CY_CAPSENSE_CSX_BUTTON_EN == 0) && (CY_CAPSENSE_CSX_MATRIX_EN == 0)) + .fptrDpProcessButton = NULL, + #else + .fptrDpProcessButton = &Cy_CapSense_DpProcessButton, + #endif + + #if ((CY_CAPSENSE_CSD_SLIDER_EN == 0) && \ + (CY_CAPSENSE_CSX_SLIDER_EN == 0)) + .fptrDpProcessSlider = NULL, + #else + .fptrDpProcessSlider = &Cy_CapSense_DpProcessSlider, + #endif + + #if (CY_CAPSENSE_CSD_MATRIX_EN == 0) + .fptrDpProcessCsdMatrix = NULL, + #else + .fptrDpProcessCsdMatrix = &Cy_CapSense_DpProcessCsdMatrix, + #endif + + #if (CY_CAPSENSE_CSD_TOUCHPAD_EN == 0) + .fptrDpProcessCsdTouchpad = NULL, + #else + .fptrDpProcessCsdTouchpad = &Cy_CapSense_DpProcessCsdTouchpad, + #endif + + #if (CY_CAPSENSE_CSD_PROXIMITY_EN == 0) + .fptrDpProcessProximity = NULL, + #else + .fptrDpProcessProximity = &Cy_CapSense_DpProcessProximity, + #endif + + #if (CY_CAPSENSE_CSX_TOUCHPAD_EN == 0) + .fptrDpProcessCsxTouchpad = NULL, + #else + .fptrDpProcessCsxTouchpad = &Cy_CapSense_DpProcessCsxTouchpad, + #endif + + #if (CY_CAPSENSE_ADVANCED_CENTROID_5X5_EN == 0) + .fptrDpAdvancedCentroidTouchpad = NULL, + #else + .fptrDpAdvancedCentroidTouchpad = &Cy_CapSense_DpAdvancedCentroidTouchpad, + #endif + + #if ((CY_CAPSENSE_CSD_CALIBRATION_EN == 0) && (CY_CAPSENSE_SMARTSENSE_FULL_EN == 0)) + .fptrCSDCalibrateWidget = NULL, + .fptrCalibrateAllCsdWidgets = NULL, + #else + .fptrCSDCalibrateWidget = &Cy_CapSense_CSDCalibrateWidget, + .fptrCalibrateAllCsdWidgets = &Cy_CapSense_CalibrateAllCsdWidgets, + #endif + + #if (CY_CAPSENSE_CSX_CALIBRATION_EN == 0) + .fptrCalibrateAllCsxWidgets = NULL, + #else + .fptrCalibrateAllCsxWidgets = &Cy_CapSense_CalibrateAllCsxWidgets, + #endif + + #if (CY_CAPSENSE_SMARTSENSE_FULL_EN == 0) + .fptrRunNoiseEnvelopeLib = NULL, + .fptrDpUpdateThresholds = NULL, + .fptrInitializeNoiseEnvelopeLib = NULL, + #else + .fptrRunNoiseEnvelopeLib = &Cy_CapSense_RunNoiseEnvelope_Lib, + .fptrDpUpdateThresholds = &Cy_CapSense_DpUpdateThresholds, + .fptrInitializeNoiseEnvelopeLib = &Cy_CapSense_InitializeNoiseEnvelope_Lib, + #endif + + #if ((CY_CAPSENSE_SMARTSENSE_HW_EN == 0) && (CY_CAPSENSE_SMARTSENSE_FULL_EN == 0)) + .fptrSsAutoTune = NULL, + #else + .fptrSsAutoTune = &Cy_CapSense_SsAutoTune, + #endif + + #if (CY_CAPSENSE_BIST_SUPPORTED) + #if (CY_CAPSENSE_BIST_EN == 0) + .fptrBistInitialize = NULL, + .fptrBistDisableMode = NULL, + .fptrBistDsInitialize = NULL, + #else + .fptrBistInitialize = &Cy_CapSense_BistInitialize, + .fptrBistDisableMode = &Cy_CapSense_BistDisableMode, + .fptrBistDsInitialize = &Cy_CapSense_BistDsInitialize, + #endif + #endif + }; +#endif + +static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_COUNT] = +{ + { /* Button0_Rx0 */ + Button0_Rx0_PORT, + Button0_Rx0_PIN, + }, + { /* Button0_Tx */ + Button0_Tx_PORT, + Button0_Tx_PIN, + }, + { /* Button1_Rx0 */ + Button1_Rx0_PORT, + Button1_Rx0_PIN, + }, + { /* Button1_Tx */ + Button1_Tx_PORT, + Button1_Tx_PIN, + }, + { /* LinearSlider0_Sns0 */ + LinearSlider0_Sns0_PORT, + LinearSlider0_Sns0_PIN, + }, + { /* LinearSlider0_Sns1 */ + LinearSlider0_Sns1_PORT, + LinearSlider0_Sns1_PIN, + }, + { /* LinearSlider0_Sns2 */ + LinearSlider0_Sns2_PORT, + LinearSlider0_Sns2_PIN, + }, + { /* LinearSlider0_Sns3 */ + LinearSlider0_Sns3_PORT, + LinearSlider0_Sns3_PIN, + }, + { /* LinearSlider0_Sns4 */ + LinearSlider0_Sns4_PORT, + LinearSlider0_Sns4_PIN, + }, +}; + +#if (CY_CAPSENSE_SHIELD_PIN_COUNT > 0) + static const cy_stc_capsense_pin_config_t cy_capsense_shieldPinConfig[CY_CAPSENSE_SHIELD_PIN_COUNT] = + { + }; +#endif + +#if (CY_CAPSENSE_ELTD_COUNT > 0) + static const cy_stc_capsense_electrode_config_t cy_capsense_electrodeConfig[CY_CAPSENSE_ELTD_COUNT] = + { + { /* Button0_Rx0 */ + .ptrPin = &cy_capsense_pinConfig[0u], + .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_RX_E, + .numPins = 1u, + }, + { /* Button0_Tx */ + .ptrPin = &cy_capsense_pinConfig[1u], + .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_TX_E, + .numPins = 1u, + }, + { /* Button1_Rx0 */ + .ptrPin = &cy_capsense_pinConfig[2u], + .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_RX_E, + .numPins = 1u, + }, + { /* Button1_Tx */ + .ptrPin = &cy_capsense_pinConfig[3u], + .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_TX_E, + .numPins = 1u, + }, + { /* LinearSlider0_Sns0 */ + .ptrPin = &cy_capsense_pinConfig[4u], + .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E, + .numPins = 1u, + }, + { /* LinearSlider0_Sns1 */ + .ptrPin = &cy_capsense_pinConfig[5u], + .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E, + .numPins = 1u, + }, + { /* LinearSlider0_Sns2 */ + .ptrPin = &cy_capsense_pinConfig[6u], + .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E, + .numPins = 1u, + }, + { /* LinearSlider0_Sns3 */ + .ptrPin = &cy_capsense_pinConfig[7u], + .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E, + .numPins = 1u, + }, + { /* LinearSlider0_Sns4 */ + .ptrPin = &cy_capsense_pinConfig[8u], + .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E, + .numPins = 1u, + }, + }; +#endif + +static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENSE_WIDGET_COUNT] = +{ + { /* Button0 */ + .ptrWdContext = &cy_capsense_tuner.widgetContext[0u], + .ptrSnsContext = &cy_capsense_tuner.sensorContext[0u], + .ptrEltdConfig = &cy_capsense_electrodeConfig[0u], +#if (CY_CAPSENSE_BIST_SUPPORTED) + .ptrEltdCapacitance = NULL, + .ptrBslnInv = NULL, +#endif + .ptrNoiseEnvelope = NULL, + .ptrRawFilterHistory = NULL, + .ptrRawFilterHistoryLow = NULL, + .iirCoeff = 128u, + .ptrDebounceArr = &cy_capsense_debounce[0u], + .ptrDiplexTable = NULL, + .centroidConfig = 0u, + .xResolution = 0u, + .yResolution = 0u, + .numSns = 1u, + .numCols = 1u, + .numRows = 1u, + .ptrPosFilterHistory = NULL, + .ptrCsxTouchHistory = NULL, + .ptrCsxTouchBuffer = NULL, + .ptrCsdTouchBuffer = NULL, + .ptrGestureConfig = NULL, + .ptrGestureContext = NULL, + .ballisticConfig = { + .accelCoeff = 9u, + .speedCoeff = 2u, + .divisorValue = 4u, + .speedThresholdX = 3u, + .speedThresholdY = 4u, + }, + .ptrBallisticContext = NULL, + .aiirConfig = { + .maxK = 60u, + .minK = 1u, + .noMovTh = 3u, + .littleMovTh = 7u, + .largeMovTh = 12u, + .divVal = 64u, + }, + .advConfig = { + .penultimateTh = 100u, + .virtualSnsTh = 100u, + .crossCouplingTh = 5u, + }, + .posFilterConfig = 0u, + .rawFilterConfig = 0u, + #if (CY_CAPSENSE_MW_VERSION >= 300) + .senseMethod = CY_CAPSENSE_CSX_GROUP, + #else + .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSX_E, + #endif + .wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E, + }, + { /* Button1 */ + .ptrWdContext = &cy_capsense_tuner.widgetContext[1u], + .ptrSnsContext = &cy_capsense_tuner.sensorContext[1u], + .ptrEltdConfig = &cy_capsense_electrodeConfig[2u], +#if (CY_CAPSENSE_BIST_SUPPORTED) + .ptrEltdCapacitance = NULL, + .ptrBslnInv = NULL, +#endif + .ptrNoiseEnvelope = NULL, + .ptrRawFilterHistory = NULL, + .ptrRawFilterHistoryLow = NULL, + .iirCoeff = 128u, + .ptrDebounceArr = &cy_capsense_debounce[1u], + .ptrDiplexTable = NULL, + .centroidConfig = 0u, + .xResolution = 0u, + .yResolution = 0u, + .numSns = 1u, + .numCols = 1u, + .numRows = 1u, + .ptrPosFilterHistory = NULL, + .ptrCsxTouchHistory = NULL, + .ptrCsxTouchBuffer = NULL, + .ptrCsdTouchBuffer = NULL, + .ptrGestureConfig = NULL, + .ptrGestureContext = NULL, + .ballisticConfig = { + .accelCoeff = 9u, + .speedCoeff = 2u, + .divisorValue = 4u, + .speedThresholdX = 3u, + .speedThresholdY = 4u, + }, + .ptrBallisticContext = NULL, + .aiirConfig = { + .maxK = 60u, + .minK = 1u, + .noMovTh = 3u, + .littleMovTh = 7u, + .largeMovTh = 12u, + .divVal = 64u, + }, + .advConfig = { + .penultimateTh = 100u, + .virtualSnsTh = 100u, + .crossCouplingTh = 5u, + }, + .posFilterConfig = 0u, + .rawFilterConfig = 0u, + #if (CY_CAPSENSE_MW_VERSION >= 300) + .senseMethod = CY_CAPSENSE_CSX_GROUP, + #else + .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSX_E, + #endif + .wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E, + }, + { /* LinearSlider0 */ + .ptrWdContext = &cy_capsense_tuner.widgetContext[2u], + .ptrSnsContext = &cy_capsense_tuner.sensorContext[2u], + .ptrEltdConfig = &cy_capsense_electrodeConfig[4u], +#if (CY_CAPSENSE_BIST_SUPPORTED) + .ptrEltdCapacitance = NULL, + .ptrBslnInv = NULL, +#endif + .ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[0u], + .ptrRawFilterHistory = NULL, + .ptrRawFilterHistoryLow = NULL, + .iirCoeff = 128u, + .ptrDebounceArr = &cy_capsense_debounce[2u], + .ptrDiplexTable = NULL, + .centroidConfig = 1u, + .xResolution = 300u, + .yResolution = 0u, + .numSns = 5u, + .numCols = 5u, + .numRows = 0u, + .ptrPosFilterHistory = NULL, + .ptrCsxTouchHistory = NULL, + .ptrCsxTouchBuffer = NULL, + .ptrCsdTouchBuffer = NULL, + .ptrGestureConfig = NULL, + .ptrGestureContext = NULL, + .ballisticConfig = { + .accelCoeff = 9u, + .speedCoeff = 2u, + .divisorValue = 4u, + .speedThresholdX = 3u, + .speedThresholdY = 4u, + }, + .ptrBallisticContext = NULL, + .aiirConfig = { + .maxK = 60u, + .minK = 1u, + .noMovTh = 3u, + .littleMovTh = 7u, + .largeMovTh = 12u, + .divVal = 64u, + }, + .advConfig = { + .penultimateTh = 100u, + .virtualSnsTh = 100u, + .crossCouplingTh = 5u, + }, + .posFilterConfig = 0u, + .rawFilterConfig = 0u, + #if (CY_CAPSENSE_MW_VERSION >= 300) + .senseMethod = CY_CAPSENSE_CSD_GROUP, + #else + .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E, + #endif + .wdType = (uint8_t)CY_CAPSENSE_WD_LINEAR_SLIDER_E, + }, +}; + +cy_stc_capsense_tuner_t cy_capsense_tuner = +{ + .commonContext = { + #if (CY_CAPSENSE_MW_VERSION < 300) + .configId = 0x0990, + #else + .configId = 0x0991, + #endif + + .tunerCmd = 0u, + .scanCounter = 0u, + .tunerSt = 0u, + .initDone = 0u, + #if (CY_CAPSENSE_MW_VERSION < 300) + .ptrSSCallback = NULL, + .ptrEOSCallback = NULL, + .ptrTunerSendCallback = NULL, + .ptrTunerReceiveCallback = NULL, + #endif + .status = 0u, + .timestampInterval = 1u, + .timestamp = 0u, + .modCsdClk = 2u, + .modCsxClk = 2u, + .tunerCnt = 0u, + }, + .widgetContext = { + { /* Button0 */ + .fingerCap = 160u, + .sigPFC = 0u, + .resolution = 100u, + .maxRawCount = 0u, + #if (CY_CAPSENSE_MW_VERSION >= 300) + .maxRawCountRow = 0u, + #endif + .fingerTh = 100u, + .proxTh = 200u, + .lowBslnRst = 30u, + .snsClk = 32u, + .rowSnsClk = 16u, + .gestureDetected = 0u, + .gestureDirection = 0u, + .xDelta = 0, + .yDelta = 0, + .noiseTh = 40u, + .nNoiseTh = 40u, + .hysteresis = 10u, + .onDebounce = 3u, + .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK, + .idacMod = { 32u, 32u, 32u, }, + .idacGainIndex = 2u, + .rowIdacMod = { 32u, 32u, 32u, }, + .bslnCoeff = 1u, + .status = 0u, + .wdTouch = { + .ptrPosition = NULL, + .numPosition = 0, + }, + }, + { /* Button1 */ + .fingerCap = 160u, + .sigPFC = 0u, + .resolution = 100u, + .maxRawCount = 0u, + #if (CY_CAPSENSE_MW_VERSION >= 300) + .maxRawCountRow = 0u, + #endif + .fingerTh = 100u, + .proxTh = 200u, + .lowBslnRst = 30u, + .snsClk = 32u, + .rowSnsClk = 16u, + .gestureDetected = 0u, + .gestureDirection = 0u, + .xDelta = 0, + .yDelta = 0, + .noiseTh = 40u, + .nNoiseTh = 40u, + .hysteresis = 10u, + .onDebounce = 3u, + .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK, + .idacMod = { 32u, 32u, 32u, }, + .idacGainIndex = 2u, + .rowIdacMod = { 32u, 32u, 32u, }, + .bslnCoeff = 1u, + .status = 0u, + .wdTouch = { + .ptrPosition = NULL, + .numPosition = 0, + }, + }, + { /* LinearSlider0 */ + .fingerCap = 160u, + .sigPFC = 0u, + .resolution = 12u, + .maxRawCount = 0u, + #if (CY_CAPSENSE_MW_VERSION >= 300) + .maxRawCountRow = 0u, + #endif + .fingerTh = 100u, + .proxTh = 200u, + .lowBslnRst = 30u, + .snsClk = 16u, + .rowSnsClk = 16u, + .gestureDetected = 0u, + .gestureDirection = 0u, + .xDelta = 0, + .yDelta = 0, + .noiseTh = 40u, + .nNoiseTh = 40u, + .hysteresis = 10u, + .onDebounce = 3u, + .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK, + .idacMod = { 32u, 32u, 32u, }, + .idacGainIndex = 4u, + .rowIdacMod = { 32u, 32u, 32u, }, + .bslnCoeff = 1u, + .status = 0u, + .wdTouch = { + .ptrPosition = &cy_capsense_tuner.position[0u], + .numPosition = 1, + }, + }, + }, + .sensorContext = { + { /* Button0_Rx0 */ + .raw = 0u, + .bsln = 0u, + .diff = 0u, + .status = 0u, + .negBslnRstCnt = 0u, + .idacComp = 32u, + .bslnExt = 0u, + }, + { /* Button1_Rx0 */ + .raw = 0u, + .bsln = 0u, + .diff = 0u, + .status = 0u, + .negBslnRstCnt = 0u, + .idacComp = 32u, + .bslnExt = 0u, + }, + { /* LinearSlider0_Sns0 */ + .raw = 0u, + .bsln = 0u, + .diff = 0u, + .status = 0u, + .negBslnRstCnt = 0u, + .idacComp = 32u, + .bslnExt = 0u, + }, + { /* LinearSlider0_Sns1 */ + .raw = 0u, + .bsln = 0u, + .diff = 0u, + .status = 0u, + .negBslnRstCnt = 0u, + .idacComp = 32u, + .bslnExt = 0u, + }, + { /* LinearSlider0_Sns2 */ + .raw = 0u, + .bsln = 0u, + .diff = 0u, + .status = 0u, + .negBslnRstCnt = 0u, + .idacComp = 32u, + .bslnExt = 0u, + }, + { /* LinearSlider0_Sns3 */ + .raw = 0u, + .bsln = 0u, + .diff = 0u, + .status = 0u, + .negBslnRstCnt = 0u, + .idacComp = 32u, + .bslnExt = 0u, + }, + { /* LinearSlider0_Sns4 */ + .raw = 0u, + .bsln = 0u, + .diff = 0u, + .status = 0u, + .negBslnRstCnt = 0u, + .idacComp = 32u, + .bslnExt = 0u, + }, + }, + .position = { + { /* LinearSlider0 */ + .x = 0u, + .y = 0u, + .z = 0u, + .id = 0u, + }, + }, +}; + +#if (CY_CAPSENSE_BIST_SUPPORTED) +#if (CY_CAPSENSE_BIST_EN != 0) +cy_stc_capsense_bist_context_t cy_capsense_bist_context = +{ +}; +#endif +#endif + +cy_stc_capsense_context_t cy_capsense_context = +{ + .ptrCommonConfig = &cy_capsense_commonConfig, + .ptrCommonContext = &cy_capsense_tuner.commonContext, + .ptrInternalContext = &cy_capsense_internalContext, + .ptrWdConfig = &cy_capsense_widgetConfig[0u], + .ptrWdContext = &cy_capsense_tuner.widgetContext[0u], + .ptrPinConfig = &cy_capsense_pinConfig[0u], + .ptrShieldPinConfig = NULL, + .ptrActiveScanSns = &cy_capsense_activeScanSns, + #if (CY_CAPSENSE_MW_VERSION < 300) + .ptrFptrConfig = (const void *) &cy_capsense_fptrConfig, + #endif + #if (CY_CAPSENSE_BIST_SUPPORTED) + .ptrBistContext = NULL, + #endif +}; + +#endif /* CY_CAPSENSE_CORE == __CORTEX_M */ + +#endif /* !defined(CY_DISABLE_CAPSENSE) */ + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h new file mode 100644 index 0000000000..b7d2ae0c5c --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h @@ -0,0 +1,2330 @@ +/******************************************************************************* +* File Name: cycfg_capsense.h +* +* Description: +* CAPSENSE Middleware configuration +* This file should not be modified. It was automatically generated by +* CapSense Configurator 4.0.0.6195 +* +******************************************************************************** +* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company) +* or an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#if !defined(CYCFG_CAPSENSE_H) +#define CYCFG_CAPSENSE_H + +#include +#include "cy_device_headers.h" +#include "cycfg_peripherals.h" +#include "cycfg_capsense_defines.h" + +#define CY_CAPSENSE_CFG_TOOL_VERSION (400) + +#if !defined(CY_DISABLE_CAPSENSE) + +#if (CY_CAPSENSE_CORE == __CORTEX_M) + + +#if !defined(Cmod_PORT) || !defined(Cmod_PIN) || !defined(Cmod_PORT_NUM) +#error Cmod Capacitor is not assigned: missing #define Cmod_PORT, #define Cmod_PIN, #define Cmod_PORT_NUM +#endif + +#if !defined(CintA_PORT) || !defined(CintA_PIN) || !defined(CintA_PORT_NUM) +#error CintA Capacitor is not assigned: missing #define CintA_PORT, #define CintA_PIN, #define CintA_PORT_NUM +#endif + +#if !defined(CintB_PORT) || !defined(CintB_PIN) || !defined(CintB_PORT_NUM) +#error CintB Capacitor is not assigned: missing #define CintB_PORT, #define CintB_PIN, #define CintB_PORT_NUM +#endif + +#if !defined(Button0_Rx0_PORT) || !defined(Button0_Rx0_PIN) +#error Button0_Rx0 Sensor is not assigned: missing #define Button0_Rx0_PORT, #define Button0_Rx0_PIN +#endif + +#if !defined(Button0_Tx_PORT) || !defined(Button0_Tx_PIN) +#error Button0_Tx Sensor is not assigned: missing #define Button0_Tx_PORT, #define Button0_Tx_PIN +#endif + +#if !defined(Button1_Rx0_PORT) || !defined(Button1_Rx0_PIN) +#error Button1_Rx0 Sensor is not assigned: missing #define Button1_Rx0_PORT, #define Button1_Rx0_PIN +#endif + +#if !defined(Button1_Tx_PORT) || !defined(Button1_Tx_PIN) +#error Button1_Tx Sensor is not assigned: missing #define Button1_Tx_PORT, #define Button1_Tx_PIN +#endif + +#if !defined(LinearSlider0_Sns0_PORT) || !defined(LinearSlider0_Sns0_PIN) +#error LinearSlider0_Sns0 Sensor is not assigned: missing #define LinearSlider0_Sns0_PORT, #define LinearSlider0_Sns0_PIN +#endif + +#if !defined(LinearSlider0_Sns1_PORT) || !defined(LinearSlider0_Sns1_PIN) +#error LinearSlider0_Sns1 Sensor is not assigned: missing #define LinearSlider0_Sns1_PORT, #define LinearSlider0_Sns1_PIN +#endif + +#if !defined(LinearSlider0_Sns2_PORT) || !defined(LinearSlider0_Sns2_PIN) +#error LinearSlider0_Sns2 Sensor is not assigned: missing #define LinearSlider0_Sns2_PORT, #define LinearSlider0_Sns2_PIN +#endif + +#if !defined(LinearSlider0_Sns3_PORT) || !defined(LinearSlider0_Sns3_PIN) +#error LinearSlider0_Sns3 Sensor is not assigned: missing #define LinearSlider0_Sns3_PORT, #define LinearSlider0_Sns3_PIN +#endif + +#if !defined(LinearSlider0_Sns4_PORT) || !defined(LinearSlider0_Sns4_PIN) +#error LinearSlider0_Sns4 Sensor is not assigned: missing #define LinearSlider0_Sns4_PORT, #define LinearSlider0_Sns4_PIN +#endif + +#if !defined(CY_CAPSENSE_CPU_CLK) +#error CPU clock frequency is not set: missing #define CY_CAPSENSE_CPU_CLK +#endif + +#if !defined(CY_CAPSENSE_PERI_CLK) +#error Peripheral clock core is not set: missing #define CY_CAPSENSE_PERI_CLK +#endif + +#if !defined(CY_CAPSENSE_VDDA_MV) +#error VDDA voltage is not set: missing #define CY_CAPSENSE_VDDA_MV +#endif + +#if !defined(CY_CAPSENSE_PERI_DIV_TYPE) +#error Peripheral clock divider type is not set: missing #define CY_CAPSENSE_PERI_DIV_TYPE +#endif + +#if !defined(CY_CAPSENSE_PERI_DIV_INDEX) +#error Peripheral clock divider index is not set: missing #define CY_CAPSENSE_PERI_DIV_INDEX +#endif + + + +#include "cy_capsense.h" + +/* Supported CapSense Middleware version */ +#define CY_CAPSENSE_MW_VERSION_REQUIRED (200) + +#if !defined (CY_CAPSENSE_MW_VERSION) + #if (CY_CAPSENSE_MW_VERSION_MAJOR == 2) + #define CY_CAPSENSE_MW_VERSION (200) + #elif (CY_CAPSENSE_MW_VERSION_MAJOR == 1) + #define CY_CAPSENSE_MW_VERSION (100) + #else + #define CY_CAPSENSE_MW_VERSION (100) + #endif +#endif + +/* Check the used Middleware version */ +#if (CY_CAPSENSE_MW_VERSION_REQUIRED > CY_CAPSENSE_MW_VERSION) + #error The CapSense Configurator requires a newer version of the CapSense Middleware. Update the CapSense Middleware in your project. +#endif + +#define CY_CAPSENSE_BIST_SUPPORTED (CY_CAPSENSE_MW_VERSION >= 210) + +#if defined(__cplusplus) +extern "C" { +#endif + +/* Widget names */ +#define CY_CAPSENSE_BUTTON0_WDGT_ID (0u) +#define CY_CAPSENSE_BUTTON1_WDGT_ID (1u) +#define CY_CAPSENSE_LINEARSLIDER0_WDGT_ID (2u) + +/* Button0 sensor names */ +#define CY_CAPSENSE_BUTTON0_SNS0_ID (0u) + +/* Button0 node names */ +#define CY_CAPSENSE_BUTTON0_RX0_TX0_ID (0u) + +/* Button0 sensor element IDs */ +#define CY_CAPSENSE_BUTTON0_RX0_ID (0u) +#define CY_CAPSENSE_BUTTON0_TX0_ID (1u) + +/* Button1 sensor names */ +#define CY_CAPSENSE_BUTTON1_SNS0_ID (0u) + +/* Button1 node names */ +#define CY_CAPSENSE_BUTTON1_RX0_TX0_ID (0u) + +/* Button1 sensor element IDs */ +#define CY_CAPSENSE_BUTTON1_RX0_ID (0u) +#define CY_CAPSENSE_BUTTON1_TX0_ID (1u) + +/* LinearSlider0 sensor names */ +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_ID (0u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_ID (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_ID (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_ID (3u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_ID (4u) + + +typedef struct { + cy_stc_capsense_common_context_t commonContext; + cy_stc_capsense_widget_context_t widgetContext[3]; + cy_stc_capsense_sensor_context_t sensorContext[7]; + cy_stc_capsense_position_t position[1]; +} cy_stc_capsense_tuner_t; + +extern cy_stc_capsense_tuner_t cy_capsense_tuner; + +extern cy_stc_capsense_context_t cy_capsense_context; + +/* RAM Data structure register definitions */ +#if (CY_CAPSENSE_MW_VERSION < 300) +#define CY_CAPSENSE_CONFIG_ID_VALUE (cy_capsense_tuner.commonContext.configId) +#define CY_CAPSENSE_CONFIG_ID_OFFSET (0u) +#define CY_CAPSENSE_CONFIG_ID_SIZE (2u) +#define CY_CAPSENSE_CONFIG_ID_PARAM_ID (0x02000000u) + +#define CY_CAPSENSE_TUNER_CMD_VALUE (cy_capsense_tuner.commonContext.tunerCmd) +#define CY_CAPSENSE_TUNER_CMD_OFFSET (2u) +#define CY_CAPSENSE_TUNER_CMD_SIZE (2u) +#define CY_CAPSENSE_TUNER_CMD_PARAM_ID (0x02000002u) + +#define CY_CAPSENSE_SCAN_COUNTER_VALUE (cy_capsense_tuner.commonContext.scanCounter) +#define CY_CAPSENSE_SCAN_COUNTER_OFFSET (4u) +#define CY_CAPSENSE_SCAN_COUNTER_SIZE (2u) +#define CY_CAPSENSE_SCAN_COUNTER_PARAM_ID (0x02000004u) + +#define CY_CAPSENSE_TUNER_ST_VALUE (cy_capsense_tuner.commonContext.tunerSt) +#define CY_CAPSENSE_TUNER_ST_OFFSET (6u) +#define CY_CAPSENSE_TUNER_ST_SIZE (1u) +#define CY_CAPSENSE_TUNER_ST_PARAM_ID (0x01000006u) + +#define CY_CAPSENSE_INITDONE_VALUE (cy_capsense_tuner.commonContext.initDone) +#define CY_CAPSENSE_INITDONE_OFFSET (7u) +#define CY_CAPSENSE_INITDONE_SIZE (1u) +#define CY_CAPSENSE_INITDONE_PARAM_ID (0x01000007u) + +#define CY_CAPSENSE_PTRSSCALLBACK_VALUE (cy_capsense_tuner.commonContext.ptrSSCallback) +#define CY_CAPSENSE_PTRSSCALLBACK_OFFSET (8u) +#define CY_CAPSENSE_PTRSSCALLBACK_SIZE (4u) +#define CY_CAPSENSE_PTRSSCALLBACK_PARAM_ID (0x03000008u) + +#define CY_CAPSENSE_PTREOSCALLBACK_VALUE (cy_capsense_tuner.commonContext.ptrEOSCallback) +#define CY_CAPSENSE_PTREOSCALLBACK_OFFSET (12u) +#define CY_CAPSENSE_PTREOSCALLBACK_SIZE (4u) +#define CY_CAPSENSE_PTREOSCALLBACK_PARAM_ID (0x0300000cu) + +#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_VALUE (cy_capsense_tuner.commonContext.ptrTunerSendCallback) +#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_OFFSET (16u) +#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_SIZE (4u) +#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_PARAM_ID (0x03000010u) + +#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_VALUE (cy_capsense_tuner.commonContext.ptrTunerReceiveCallback) +#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_OFFSET (20u) +#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_SIZE (4u) +#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_PARAM_ID (0x03000014u) + +#define CY_CAPSENSE_STATUS_VALUE (cy_capsense_tuner.commonContext.status) +#define CY_CAPSENSE_STATUS_OFFSET (24u) +#define CY_CAPSENSE_STATUS_SIZE (4u) +#define CY_CAPSENSE_STATUS_PARAM_ID (0x03000018u) + +#define CY_CAPSENSE_TIMESTAMPINTERVAL_VALUE (cy_capsense_tuner.commonContext.timestampInterval) +#define CY_CAPSENSE_TIMESTAMPINTERVAL_OFFSET (28u) +#define CY_CAPSENSE_TIMESTAMPINTERVAL_SIZE (4u) +#define CY_CAPSENSE_TIMESTAMPINTERVAL_PARAM_ID (0x0300001cu) + +#define CY_CAPSENSE_TIMESTAMP_VALUE (cy_capsense_tuner.commonContext.timestamp) +#define CY_CAPSENSE_TIMESTAMP_OFFSET (32u) +#define CY_CAPSENSE_TIMESTAMP_SIZE (4u) +#define CY_CAPSENSE_TIMESTAMP_PARAM_ID (0x03000020u) + +#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_VALUE (cy_capsense_tuner.commonContext.modCsdClk) +#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_OFFSET (36u) +#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_SIZE (1u) +#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_PARAM_ID (0x01000024u) + +#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_VALUE (cy_capsense_tuner.commonContext.modCsxClk) +#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_OFFSET (37u) +#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_SIZE (1u) +#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_PARAM_ID (0x01000025u) + +#define CY_CAPSENSE_TUNER_CNT_VALUE (cy_capsense_tuner.commonContext.tunerCnt) +#define CY_CAPSENSE_TUNER_CNT_OFFSET (38u) +#define CY_CAPSENSE_TUNER_CNT_SIZE (1u) +#define CY_CAPSENSE_TUNER_CNT_PARAM_ID (0x01000026u) + +#define CY_CAPSENSE_BUTTON0_FINGER_CP_VALUE (cy_capsense_tuner.widgetContext[0].fingerCap) +#define CY_CAPSENSE_BUTTON0_FINGER_CP_OFFSET (40u) +#define CY_CAPSENSE_BUTTON0_FINGER_CP_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_FINGER_CP_PARAM_ID (0x06000028u) + +#define CY_CAPSENSE_BUTTON0_SIGPFC_VALUE (cy_capsense_tuner.widgetContext[0].sigPFC) +#define CY_CAPSENSE_BUTTON0_SIGPFC_OFFSET (42u) +#define CY_CAPSENSE_BUTTON0_SIGPFC_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_SIGPFC_PARAM_ID (0x0600002au) + +#define CY_CAPSENSE_BUTTON0_NUM_CONV_VALUE (cy_capsense_tuner.widgetContext[0].resolution) +#define CY_CAPSENSE_BUTTON0_NUM_CONV_OFFSET (44u) +#define CY_CAPSENSE_BUTTON0_NUM_CONV_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_NUM_CONV_PARAM_ID (0x0600002cu) + +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_VALUE (cy_capsense_tuner.widgetContext[0].maxRawCount) +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_OFFSET (46u) +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_PARAM_ID (0x0200002eu) + +#define CY_CAPSENSE_BUTTON0_FINGER_TH_VALUE (cy_capsense_tuner.widgetContext[0].fingerTh) +#define CY_CAPSENSE_BUTTON0_FINGER_TH_OFFSET (48u) +#define CY_CAPSENSE_BUTTON0_FINGER_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_FINGER_TH_PARAM_ID (0x06000030u) + +#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_VALUE (cy_capsense_tuner.widgetContext[0].proxTh) +#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_OFFSET (50u) +#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_PARAM_ID (0x06000032u) + +#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_VALUE (cy_capsense_tuner.widgetContext[0].lowBslnRst) +#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_OFFSET (52u) +#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_PARAM_ID (0x06000034u) + +#define CY_CAPSENSE_BUTTON0_TX_CLK_VALUE (cy_capsense_tuner.widgetContext[0].snsClk) +#define CY_CAPSENSE_BUTTON0_TX_CLK_OFFSET (54u) +#define CY_CAPSENSE_BUTTON0_TX_CLK_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_TX_CLK_PARAM_ID (0x06000036u) + +#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_VALUE (cy_capsense_tuner.widgetContext[0].rowSnsClk) +#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_OFFSET (56u) +#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_PARAM_ID (0x06000038u) + +#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_VALUE (cy_capsense_tuner.widgetContext[0].gestureDetected) +#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_OFFSET (58u) +#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_PARAM_ID (0x0200003au) + +#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_VALUE (cy_capsense_tuner.widgetContext[0].gestureDirection) +#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_OFFSET (60u) +#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_PARAM_ID (0x0200003cu) + +#define CY_CAPSENSE_BUTTON0_XDELTA_VALUE (cy_capsense_tuner.widgetContext[0].xDelta) +#define CY_CAPSENSE_BUTTON0_XDELTA_OFFSET (62u) +#define CY_CAPSENSE_BUTTON0_XDELTA_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_XDELTA_PARAM_ID (0x0200003eu) + +#define CY_CAPSENSE_BUTTON0_YDELTA_VALUE (cy_capsense_tuner.widgetContext[0].yDelta) +#define CY_CAPSENSE_BUTTON0_YDELTA_OFFSET (64u) +#define CY_CAPSENSE_BUTTON0_YDELTA_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_YDELTA_PARAM_ID (0x02000040u) + +#define CY_CAPSENSE_BUTTON0_NOISE_TH_VALUE (cy_capsense_tuner.widgetContext[0].noiseTh) +#define CY_CAPSENSE_BUTTON0_NOISE_TH_OFFSET (66u) +#define CY_CAPSENSE_BUTTON0_NOISE_TH_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_NOISE_TH_PARAM_ID (0x05000042u) + +#define CY_CAPSENSE_BUTTON0_NNOISE_TH_VALUE (cy_capsense_tuner.widgetContext[0].nNoiseTh) +#define CY_CAPSENSE_BUTTON0_NNOISE_TH_OFFSET (67u) +#define CY_CAPSENSE_BUTTON0_NNOISE_TH_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_NNOISE_TH_PARAM_ID (0x05000043u) + +#define CY_CAPSENSE_BUTTON0_HYSTERESIS_VALUE (cy_capsense_tuner.widgetContext[0].hysteresis) +#define CY_CAPSENSE_BUTTON0_HYSTERESIS_OFFSET (68u) +#define CY_CAPSENSE_BUTTON0_HYSTERESIS_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_HYSTERESIS_PARAM_ID (0x05000044u) + +#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_VALUE (cy_capsense_tuner.widgetContext[0].onDebounce) +#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_OFFSET (69u) +#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_PARAM_ID (0x05000045u) + +#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_VALUE (cy_capsense_tuner.widgetContext[0].snsClkSource) +#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_OFFSET (70u) +#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_PARAM_ID (0x05000046u) + +#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[0].idacMod[0]) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_OFFSET (71u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_PARAM_ID (0x05000047u) + +#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[0].idacMod[1]) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_OFFSET (72u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_PARAM_ID (0x05000048u) + +#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[0].idacMod[2]) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_OFFSET (73u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_PARAM_ID (0x05000049u) + +#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_VALUE (cy_capsense_tuner.widgetContext[0].idacGainIndex) +#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_OFFSET (74u) +#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_PARAM_ID (0x0500004au) + +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[0].rowIdacMod[0]) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_OFFSET (75u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_PARAM_ID (0x0500004bu) + +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[0].rowIdacMod[1]) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_OFFSET (76u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_PARAM_ID (0x0500004cu) + +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[0].rowIdacMod[2]) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_OFFSET (77u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_PARAM_ID (0x0500004du) + +#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_VALUE (cy_capsense_tuner.widgetContext[0].bslnCoeff) +#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_OFFSET (78u) +#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_PARAM_ID (0x0100004eu) + +#define CY_CAPSENSE_BUTTON0_STATUS_VALUE (cy_capsense_tuner.widgetContext[0].status) +#define CY_CAPSENSE_BUTTON0_STATUS_OFFSET (79u) +#define CY_CAPSENSE_BUTTON0_STATUS_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_STATUS_PARAM_ID (0x0100004fu) + +#define CY_CAPSENSE_BUTTON0_PTRPOSITION_VALUE (cy_capsense_tuner.widgetContext[0].wdTouch.ptrPosition) +#define CY_CAPSENSE_BUTTON0_PTRPOSITION_OFFSET (80u) +#define CY_CAPSENSE_BUTTON0_PTRPOSITION_SIZE (4u) +#define CY_CAPSENSE_BUTTON0_PTRPOSITION_PARAM_ID (0x03000050u) + +#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_VALUE (cy_capsense_tuner.widgetContext[0].wdTouch.numPosition) +#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_OFFSET (84u) +#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_PARAM_ID (0x01000054u) + +#define CY_CAPSENSE_BUTTON1_FINGER_CP_VALUE (cy_capsense_tuner.widgetContext[1].fingerCap) +#define CY_CAPSENSE_BUTTON1_FINGER_CP_OFFSET (88u) +#define CY_CAPSENSE_BUTTON1_FINGER_CP_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_FINGER_CP_PARAM_ID (0x06010058u) + +#define CY_CAPSENSE_BUTTON1_SIGPFC_VALUE (cy_capsense_tuner.widgetContext[1].sigPFC) +#define CY_CAPSENSE_BUTTON1_SIGPFC_OFFSET (90u) +#define CY_CAPSENSE_BUTTON1_SIGPFC_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_SIGPFC_PARAM_ID (0x0601005au) + +#define CY_CAPSENSE_BUTTON1_NUM_CONV_VALUE (cy_capsense_tuner.widgetContext[1].resolution) +#define CY_CAPSENSE_BUTTON1_NUM_CONV_OFFSET (92u) +#define CY_CAPSENSE_BUTTON1_NUM_CONV_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_NUM_CONV_PARAM_ID (0x0601005cu) + +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_VALUE (cy_capsense_tuner.widgetContext[1].maxRawCount) +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_OFFSET (94u) +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_PARAM_ID (0x0201005eu) + +#define CY_CAPSENSE_BUTTON1_FINGER_TH_VALUE (cy_capsense_tuner.widgetContext[1].fingerTh) +#define CY_CAPSENSE_BUTTON1_FINGER_TH_OFFSET (96u) +#define CY_CAPSENSE_BUTTON1_FINGER_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_FINGER_TH_PARAM_ID (0x06010060u) + +#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_VALUE (cy_capsense_tuner.widgetContext[1].proxTh) +#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_OFFSET (98u) +#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_PARAM_ID (0x06010062u) + +#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_VALUE (cy_capsense_tuner.widgetContext[1].lowBslnRst) +#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_OFFSET (100u) +#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_PARAM_ID (0x06010064u) + +#define CY_CAPSENSE_BUTTON1_TX_CLK_VALUE (cy_capsense_tuner.widgetContext[1].snsClk) +#define CY_CAPSENSE_BUTTON1_TX_CLK_OFFSET (102u) +#define CY_CAPSENSE_BUTTON1_TX_CLK_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_TX_CLK_PARAM_ID (0x06010066u) + +#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_VALUE (cy_capsense_tuner.widgetContext[1].rowSnsClk) +#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_OFFSET (104u) +#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_PARAM_ID (0x06010068u) + +#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_VALUE (cy_capsense_tuner.widgetContext[1].gestureDetected) +#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_OFFSET (106u) +#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_PARAM_ID (0x0201006au) + +#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_VALUE (cy_capsense_tuner.widgetContext[1].gestureDirection) +#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_OFFSET (108u) +#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_PARAM_ID (0x0201006cu) + +#define CY_CAPSENSE_BUTTON1_XDELTA_VALUE (cy_capsense_tuner.widgetContext[1].xDelta) +#define CY_CAPSENSE_BUTTON1_XDELTA_OFFSET (110u) +#define CY_CAPSENSE_BUTTON1_XDELTA_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_XDELTA_PARAM_ID (0x0201006eu) + +#define CY_CAPSENSE_BUTTON1_YDELTA_VALUE (cy_capsense_tuner.widgetContext[1].yDelta) +#define CY_CAPSENSE_BUTTON1_YDELTA_OFFSET (112u) +#define CY_CAPSENSE_BUTTON1_YDELTA_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_YDELTA_PARAM_ID (0x02010070u) + +#define CY_CAPSENSE_BUTTON1_NOISE_TH_VALUE (cy_capsense_tuner.widgetContext[1].noiseTh) +#define CY_CAPSENSE_BUTTON1_NOISE_TH_OFFSET (114u) +#define CY_CAPSENSE_BUTTON1_NOISE_TH_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_NOISE_TH_PARAM_ID (0x05010072u) + +#define CY_CAPSENSE_BUTTON1_NNOISE_TH_VALUE (cy_capsense_tuner.widgetContext[1].nNoiseTh) +#define CY_CAPSENSE_BUTTON1_NNOISE_TH_OFFSET (115u) +#define CY_CAPSENSE_BUTTON1_NNOISE_TH_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_NNOISE_TH_PARAM_ID (0x05010073u) + +#define CY_CAPSENSE_BUTTON1_HYSTERESIS_VALUE (cy_capsense_tuner.widgetContext[1].hysteresis) +#define CY_CAPSENSE_BUTTON1_HYSTERESIS_OFFSET (116u) +#define CY_CAPSENSE_BUTTON1_HYSTERESIS_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_HYSTERESIS_PARAM_ID (0x05010074u) + +#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_VALUE (cy_capsense_tuner.widgetContext[1].onDebounce) +#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_OFFSET (117u) +#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_PARAM_ID (0x05010075u) + +#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_VALUE (cy_capsense_tuner.widgetContext[1].snsClkSource) +#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_OFFSET (118u) +#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_PARAM_ID (0x05010076u) + +#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[1].idacMod[0]) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_OFFSET (119u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_PARAM_ID (0x05010077u) + +#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[1].idacMod[1]) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_OFFSET (120u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_PARAM_ID (0x05010078u) + +#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[1].idacMod[2]) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_OFFSET (121u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_PARAM_ID (0x05010079u) + +#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_VALUE (cy_capsense_tuner.widgetContext[1].idacGainIndex) +#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_OFFSET (122u) +#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_PARAM_ID (0x0501007au) + +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[1].rowIdacMod[0]) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_OFFSET (123u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_PARAM_ID (0x0501007bu) + +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[1].rowIdacMod[1]) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_OFFSET (124u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_PARAM_ID (0x0501007cu) + +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[1].rowIdacMod[2]) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_OFFSET (125u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_PARAM_ID (0x0501007du) + +#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_VALUE (cy_capsense_tuner.widgetContext[1].bslnCoeff) +#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_OFFSET (126u) +#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_PARAM_ID (0x0101007eu) + +#define CY_CAPSENSE_BUTTON1_STATUS_VALUE (cy_capsense_tuner.widgetContext[1].status) +#define CY_CAPSENSE_BUTTON1_STATUS_OFFSET (127u) +#define CY_CAPSENSE_BUTTON1_STATUS_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_STATUS_PARAM_ID (0x0101007fu) + +#define CY_CAPSENSE_BUTTON1_PTRPOSITION_VALUE (cy_capsense_tuner.widgetContext[1].wdTouch.ptrPosition) +#define CY_CAPSENSE_BUTTON1_PTRPOSITION_OFFSET (128u) +#define CY_CAPSENSE_BUTTON1_PTRPOSITION_SIZE (4u) +#define CY_CAPSENSE_BUTTON1_PTRPOSITION_PARAM_ID (0x03010080u) + +#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_VALUE (cy_capsense_tuner.widgetContext[1].wdTouch.numPosition) +#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_OFFSET (132u) +#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_PARAM_ID (0x01010084u) + +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_VALUE (cy_capsense_tuner.widgetContext[2].fingerCap) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_OFFSET (136u) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_PARAM_ID (0x06020088u) + +#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_VALUE (cy_capsense_tuner.widgetContext[2].sigPFC) +#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_OFFSET (138u) +#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_PARAM_ID (0x0602008au) + +#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_VALUE (cy_capsense_tuner.widgetContext[2].resolution) +#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_OFFSET (140u) +#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_PARAM_ID (0x0602008cu) + +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_VALUE (cy_capsense_tuner.widgetContext[2].maxRawCount) +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_OFFSET (142u) +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_PARAM_ID (0x0202008eu) + +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_VALUE (cy_capsense_tuner.widgetContext[2].fingerTh) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_OFFSET (144u) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_PARAM_ID (0x02020090u) + +#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_VALUE (cy_capsense_tuner.widgetContext[2].proxTh) +#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET (146u) +#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_PARAM_ID (0x02020092u) + +#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_VALUE (cy_capsense_tuner.widgetContext[2].lowBslnRst) +#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_OFFSET (148u) +#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_PARAM_ID (0x06020094u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_VALUE (cy_capsense_tuner.widgetContext[2].snsClk) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_OFFSET (150u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_PARAM_ID (0x06020096u) + +#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_VALUE (cy_capsense_tuner.widgetContext[2].rowSnsClk) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_OFFSET (152u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_PARAM_ID (0x06020098u) + +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_VALUE (cy_capsense_tuner.widgetContext[2].gestureDetected) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_OFFSET (154u) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_PARAM_ID (0x0202009au) + +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_VALUE (cy_capsense_tuner.widgetContext[2].gestureDirection) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET (156u) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_PARAM_ID (0x0202009cu) + +#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_VALUE (cy_capsense_tuner.widgetContext[2].xDelta) +#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_OFFSET (158u) +#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_PARAM_ID (0x0202009eu) + +#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_VALUE (cy_capsense_tuner.widgetContext[2].yDelta) +#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_OFFSET (160u) +#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_PARAM_ID (0x020200a0u) + +#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_VALUE (cy_capsense_tuner.widgetContext[2].noiseTh) +#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_OFFSET (162u) +#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_PARAM_ID (0x010200a2u) + +#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_VALUE (cy_capsense_tuner.widgetContext[2].nNoiseTh) +#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_OFFSET (163u) +#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_PARAM_ID (0x010200a3u) + +#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_VALUE (cy_capsense_tuner.widgetContext[2].hysteresis) +#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_OFFSET (164u) +#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_PARAM_ID (0x010200a4u) + +#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_VALUE (cy_capsense_tuner.widgetContext[2].onDebounce) +#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_OFFSET (165u) +#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_PARAM_ID (0x050200a5u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_VALUE (cy_capsense_tuner.widgetContext[2].snsClkSource) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET (166u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_PARAM_ID (0x050200a6u) + +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[2].idacMod[0]) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_OFFSET (167u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_PARAM_ID (0x050200a7u) + +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[2].idacMod[1]) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_OFFSET (168u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_PARAM_ID (0x050200a8u) + +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[2].idacMod[2]) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_OFFSET (169u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_PARAM_ID (0x050200a9u) + +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_VALUE (cy_capsense_tuner.widgetContext[2].idacGainIndex) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET (170u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_PARAM_ID (0x050200aau) + +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[2].rowIdacMod[0]) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET (171u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_PARAM_ID (0x050200abu) + +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[2].rowIdacMod[1]) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET (172u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_PARAM_ID (0x050200acu) + +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[2].rowIdacMod[2]) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET (173u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_PARAM_ID (0x050200adu) + +#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_VALUE (cy_capsense_tuner.widgetContext[2].bslnCoeff) +#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET (174u) +#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_PARAM_ID (0x010200aeu) + +#define CY_CAPSENSE_LINEARSLIDER0_STATUS_VALUE (cy_capsense_tuner.widgetContext[2].status) +#define CY_CAPSENSE_LINEARSLIDER0_STATUS_OFFSET (175u) +#define CY_CAPSENSE_LINEARSLIDER0_STATUS_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_STATUS_PARAM_ID (0x010200afu) + +#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_VALUE (cy_capsense_tuner.widgetContext[2].wdTouch.ptrPosition) +#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_OFFSET (176u) +#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_SIZE (4u) +#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_PARAM_ID (0x030200b0u) + +#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_VALUE (cy_capsense_tuner.widgetContext[2].wdTouch.numPosition) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_OFFSET (180u) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_PARAM_ID (0x010200b4u) + +#define CY_CAPSENSE_BUTTON0_RX0_RAW0_VALUE (cy_capsense_tuner.sensorContext[0].raw) +#define CY_CAPSENSE_BUTTON0_RX0_RAW0_OFFSET (184u) +#define CY_CAPSENSE_BUTTON0_RX0_RAW0_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_RX0_RAW0_PARAM_ID (0x020000b8u) + +#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_VALUE (cy_capsense_tuner.sensorContext[0].bsln) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_OFFSET (186u) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_PARAM_ID (0x020000bau) + +#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_VALUE (cy_capsense_tuner.sensorContext[0].diff) +#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_OFFSET (188u) +#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_PARAM_ID (0x020000bcu) + +#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_VALUE (cy_capsense_tuner.sensorContext[0].status) +#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_OFFSET (190u) +#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_PARAM_ID (0x010000beu) + +#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[0].negBslnRstCnt) +#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_OFFSET (191u) +#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_PARAM_ID (0x010000bfu) + +#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_VALUE (cy_capsense_tuner.sensorContext[0].idacComp) +#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_OFFSET (192u) +#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_PARAM_ID (0x010000c0u) + +#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[0].bslnExt) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_OFFSET (193u) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_PARAM_ID (0x010000c1u) + +#define CY_CAPSENSE_BUTTON1_RX0_RAW0_VALUE (cy_capsense_tuner.sensorContext[1].raw) +#define CY_CAPSENSE_BUTTON1_RX0_RAW0_OFFSET (194u) +#define CY_CAPSENSE_BUTTON1_RX0_RAW0_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_RX0_RAW0_PARAM_ID (0x020100c2u) + +#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_VALUE (cy_capsense_tuner.sensorContext[1].bsln) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_OFFSET (196u) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_PARAM_ID (0x020100c4u) + +#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_VALUE (cy_capsense_tuner.sensorContext[1].diff) +#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_OFFSET (198u) +#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_PARAM_ID (0x020100c6u) + +#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_VALUE (cy_capsense_tuner.sensorContext[1].status) +#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_OFFSET (200u) +#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_PARAM_ID (0x010100c8u) + +#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[1].negBslnRstCnt) +#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_OFFSET (201u) +#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_PARAM_ID (0x010100c9u) + +#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_VALUE (cy_capsense_tuner.sensorContext[1].idacComp) +#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_OFFSET (202u) +#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_PARAM_ID (0x010100cau) + +#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[1].bslnExt) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_OFFSET (203u) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_PARAM_ID (0x010100cbu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_VALUE (cy_capsense_tuner.sensorContext[2].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_OFFSET (204u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_PARAM_ID (0x020200ccu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_VALUE (cy_capsense_tuner.sensorContext[2].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_OFFSET (206u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_PARAM_ID (0x020200ceu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_VALUE (cy_capsense_tuner.sensorContext[2].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_OFFSET (208u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_PARAM_ID (0x020200d0u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_VALUE (cy_capsense_tuner.sensorContext[2].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_OFFSET (210u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_PARAM_ID (0x010200d2u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[2].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET (211u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID (0x010200d3u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_VALUE (cy_capsense_tuner.sensorContext[2].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_OFFSET (212u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_PARAM_ID (0x010200d4u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[2].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET (213u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_PARAM_ID (0x010200d5u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_VALUE (cy_capsense_tuner.sensorContext[3].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_OFFSET (214u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_PARAM_ID (0x020200d6u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_VALUE (cy_capsense_tuner.sensorContext[3].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_OFFSET (216u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_PARAM_ID (0x020200d8u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_VALUE (cy_capsense_tuner.sensorContext[3].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_OFFSET (218u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_PARAM_ID (0x020200dau) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_VALUE (cy_capsense_tuner.sensorContext[3].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_OFFSET (220u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_PARAM_ID (0x010200dcu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[3].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET (221u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_PARAM_ID (0x010200ddu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_VALUE (cy_capsense_tuner.sensorContext[3].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_OFFSET (222u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_PARAM_ID (0x010200deu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[3].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET (223u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_PARAM_ID (0x010200dfu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_VALUE (cy_capsense_tuner.sensorContext[4].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_OFFSET (224u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_PARAM_ID (0x020200e0u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_VALUE (cy_capsense_tuner.sensorContext[4].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_OFFSET (226u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_PARAM_ID (0x020200e2u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_VALUE (cy_capsense_tuner.sensorContext[4].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_OFFSET (228u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_PARAM_ID (0x020200e4u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_VALUE (cy_capsense_tuner.sensorContext[4].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_OFFSET (230u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_PARAM_ID (0x010200e6u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[4].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET (231u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_PARAM_ID (0x010200e7u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_VALUE (cy_capsense_tuner.sensorContext[4].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_OFFSET (232u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_PARAM_ID (0x010200e8u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[4].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET (233u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_PARAM_ID (0x010200e9u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_VALUE (cy_capsense_tuner.sensorContext[5].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_OFFSET (234u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_PARAM_ID (0x020200eau) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_VALUE (cy_capsense_tuner.sensorContext[5].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_OFFSET (236u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_PARAM_ID (0x020200ecu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_VALUE (cy_capsense_tuner.sensorContext[5].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_OFFSET (238u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_PARAM_ID (0x020200eeu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_VALUE (cy_capsense_tuner.sensorContext[5].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_OFFSET (240u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_PARAM_ID (0x010200f0u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[5].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET (241u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_PARAM_ID (0x010200f1u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_VALUE (cy_capsense_tuner.sensorContext[5].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_OFFSET (242u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_PARAM_ID (0x010200f2u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[5].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET (243u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_PARAM_ID (0x010200f3u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_VALUE (cy_capsense_tuner.sensorContext[6].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_OFFSET (244u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_PARAM_ID (0x020200f4u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_VALUE (cy_capsense_tuner.sensorContext[6].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_OFFSET (246u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_PARAM_ID (0x020200f6u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_VALUE (cy_capsense_tuner.sensorContext[6].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_OFFSET (248u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_PARAM_ID (0x020200f8u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_VALUE (cy_capsense_tuner.sensorContext[6].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_OFFSET (250u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_PARAM_ID (0x010200fau) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[6].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET (251u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_PARAM_ID (0x010200fbu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_VALUE (cy_capsense_tuner.sensorContext[6].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_OFFSET (252u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_PARAM_ID (0x010200fcu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[6].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET (253u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_PARAM_ID (0x010200fdu) + +#define CY_CAPSENSE_LINEARSLIDER0_X0_VALUE (cy_capsense_tuner.position[0].x) +#define CY_CAPSENSE_LINEARSLIDER0_X0_OFFSET (254u) +#define CY_CAPSENSE_LINEARSLIDER0_X0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_X0_PARAM_ID (0x020200feu) + +#define CY_CAPSENSE_LINEARSLIDER0_Y0_VALUE (cy_capsense_tuner.position[0].y) +#define CY_CAPSENSE_LINEARSLIDER0_Y0_OFFSET (256u) +#define CY_CAPSENSE_LINEARSLIDER0_Y0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_Y0_PARAM_ID (0x02020100u) + +#define CY_CAPSENSE_LINEARSLIDER0_Z0_VALUE (cy_capsense_tuner.position[0].z) +#define CY_CAPSENSE_LINEARSLIDER0_Z0_OFFSET (258u) +#define CY_CAPSENSE_LINEARSLIDER0_Z0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_Z0_PARAM_ID (0x02020102u) + +#define CY_CAPSENSE_LINEARSLIDER0_ID0_VALUE (cy_capsense_tuner.position[0].id) +#define CY_CAPSENSE_LINEARSLIDER0_ID0_OFFSET (260u) +#define CY_CAPSENSE_LINEARSLIDER0_ID0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_ID0_PARAM_ID (0x02020104u) + +#else /* CY_CAPSENSE_MW_VERSION >= 300 */ +#define CY_CAPSENSE_CONFIG_ID_VALUE (cy_capsense_tuner.commonContext.configId) +#define CY_CAPSENSE_CONFIG_ID_OFFSET (0u) +#define CY_CAPSENSE_CONFIG_ID_SIZE (2u) +#define CY_CAPSENSE_CONFIG_ID_PARAM_ID (0x02000000u) + +#define CY_CAPSENSE_TUNER_CMD_VALUE (cy_capsense_tuner.commonContext.tunerCmd) +#define CY_CAPSENSE_TUNER_CMD_OFFSET (2u) +#define CY_CAPSENSE_TUNER_CMD_SIZE (2u) +#define CY_CAPSENSE_TUNER_CMD_PARAM_ID (0x02000002u) + +#define CY_CAPSENSE_SCAN_COUNTER_VALUE (cy_capsense_tuner.commonContext.scanCounter) +#define CY_CAPSENSE_SCAN_COUNTER_OFFSET (4u) +#define CY_CAPSENSE_SCAN_COUNTER_SIZE (2u) +#define CY_CAPSENSE_SCAN_COUNTER_PARAM_ID (0x02000004u) + +#define CY_CAPSENSE_TUNER_ST_VALUE (cy_capsense_tuner.commonContext.tunerSt) +#define CY_CAPSENSE_TUNER_ST_OFFSET (6u) +#define CY_CAPSENSE_TUNER_ST_SIZE (1u) +#define CY_CAPSENSE_TUNER_ST_PARAM_ID (0x01000006u) + +#define CY_CAPSENSE_INITDONE_VALUE (cy_capsense_tuner.commonContext.initDone) +#define CY_CAPSENSE_INITDONE_OFFSET (7u) +#define CY_CAPSENSE_INITDONE_SIZE (1u) +#define CY_CAPSENSE_INITDONE_PARAM_ID (0x01000007u) + +#define CY_CAPSENSE_STATUS_VALUE (cy_capsense_tuner.commonContext.status) +#define CY_CAPSENSE_STATUS_OFFSET (8u) +#define CY_CAPSENSE_STATUS_SIZE (4u) +#define CY_CAPSENSE_STATUS_PARAM_ID (0x03000008u) + +#define CY_CAPSENSE_TIMESTAMPINTERVAL_VALUE (cy_capsense_tuner.commonContext.timestampInterval) +#define CY_CAPSENSE_TIMESTAMPINTERVAL_OFFSET (12u) +#define CY_CAPSENSE_TIMESTAMPINTERVAL_SIZE (4u) +#define CY_CAPSENSE_TIMESTAMPINTERVAL_PARAM_ID (0x0300000cu) + +#define CY_CAPSENSE_TIMESTAMP_VALUE (cy_capsense_tuner.commonContext.timestamp) +#define CY_CAPSENSE_TIMESTAMP_OFFSET (16u) +#define CY_CAPSENSE_TIMESTAMP_SIZE (4u) +#define CY_CAPSENSE_TIMESTAMP_PARAM_ID (0x03000010u) + +#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_VALUE (cy_capsense_tuner.commonContext.modCsdClk) +#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_OFFSET (20u) +#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_SIZE (1u) +#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_PARAM_ID (0x01000014u) + +#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_VALUE (cy_capsense_tuner.commonContext.modCsxClk) +#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_OFFSET (21u) +#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_SIZE (1u) +#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_PARAM_ID (0x01000015u) + +#define CY_CAPSENSE_TUNER_CNT_VALUE (cy_capsense_tuner.commonContext.tunerCnt) +#define CY_CAPSENSE_TUNER_CNT_OFFSET (22u) +#define CY_CAPSENSE_TUNER_CNT_SIZE (1u) +#define CY_CAPSENSE_TUNER_CNT_PARAM_ID (0x01000016u) + +#define CY_CAPSENSE_BUTTON0_FINGER_CP_VALUE (cy_capsense_tuner.widgetContext[0].fingerCap) +#define CY_CAPSENSE_BUTTON0_FINGER_CP_OFFSET (24u) +#define CY_CAPSENSE_BUTTON0_FINGER_CP_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_FINGER_CP_PARAM_ID (0x06000018u) + +#define CY_CAPSENSE_BUTTON0_SIGPFC_VALUE (cy_capsense_tuner.widgetContext[0].sigPFC) +#define CY_CAPSENSE_BUTTON0_SIGPFC_OFFSET (26u) +#define CY_CAPSENSE_BUTTON0_SIGPFC_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_SIGPFC_PARAM_ID (0x0600001au) + +#define CY_CAPSENSE_BUTTON0_NUM_CONV_VALUE (cy_capsense_tuner.widgetContext[0].resolution) +#define CY_CAPSENSE_BUTTON0_NUM_CONV_OFFSET (28u) +#define CY_CAPSENSE_BUTTON0_NUM_CONV_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_NUM_CONV_PARAM_ID (0x0600001cu) + +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_VALUE (cy_capsense_tuner.widgetContext[0].maxRawCount) +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_OFFSET (30u) +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_PARAM_ID (0x0200001eu) + +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_VALUE (cy_capsense_tuner.widgetContext[0].maxRawCountRow) +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_OFFSET (32u) +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_PARAM_ID (0x02000020u) + +#define CY_CAPSENSE_BUTTON0_FINGER_TH_VALUE (cy_capsense_tuner.widgetContext[0].fingerTh) +#define CY_CAPSENSE_BUTTON0_FINGER_TH_OFFSET (34u) +#define CY_CAPSENSE_BUTTON0_FINGER_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_FINGER_TH_PARAM_ID (0x06000022u) + +#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_VALUE (cy_capsense_tuner.widgetContext[0].proxTh) +#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_OFFSET (36u) +#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_PARAM_ID (0x06000024u) + +#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_VALUE (cy_capsense_tuner.widgetContext[0].lowBslnRst) +#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_OFFSET (38u) +#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_PARAM_ID (0x06000026u) + +#define CY_CAPSENSE_BUTTON0_TX_CLK_VALUE (cy_capsense_tuner.widgetContext[0].snsClk) +#define CY_CAPSENSE_BUTTON0_TX_CLK_OFFSET (40u) +#define CY_CAPSENSE_BUTTON0_TX_CLK_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_TX_CLK_PARAM_ID (0x06000028u) + +#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_VALUE (cy_capsense_tuner.widgetContext[0].rowSnsClk) +#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_OFFSET (42u) +#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_PARAM_ID (0x0600002au) + +#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_VALUE (cy_capsense_tuner.widgetContext[0].gestureDetected) +#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_OFFSET (44u) +#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_PARAM_ID (0x0200002cu) + +#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_VALUE (cy_capsense_tuner.widgetContext[0].gestureDirection) +#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_OFFSET (46u) +#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_PARAM_ID (0x0200002eu) + +#define CY_CAPSENSE_BUTTON0_XDELTA_VALUE (cy_capsense_tuner.widgetContext[0].xDelta) +#define CY_CAPSENSE_BUTTON0_XDELTA_OFFSET (48u) +#define CY_CAPSENSE_BUTTON0_XDELTA_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_XDELTA_PARAM_ID (0x02000030u) + +#define CY_CAPSENSE_BUTTON0_YDELTA_VALUE (cy_capsense_tuner.widgetContext[0].yDelta) +#define CY_CAPSENSE_BUTTON0_YDELTA_OFFSET (50u) +#define CY_CAPSENSE_BUTTON0_YDELTA_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_YDELTA_PARAM_ID (0x02000032u) + +#define CY_CAPSENSE_BUTTON0_NOISE_TH_VALUE (cy_capsense_tuner.widgetContext[0].noiseTh) +#define CY_CAPSENSE_BUTTON0_NOISE_TH_OFFSET (52u) +#define CY_CAPSENSE_BUTTON0_NOISE_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_NOISE_TH_PARAM_ID (0x06000034u) + +#define CY_CAPSENSE_BUTTON0_NNOISE_TH_VALUE (cy_capsense_tuner.widgetContext[0].nNoiseTh) +#define CY_CAPSENSE_BUTTON0_NNOISE_TH_OFFSET (54u) +#define CY_CAPSENSE_BUTTON0_NNOISE_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_NNOISE_TH_PARAM_ID (0x06000036u) + +#define CY_CAPSENSE_BUTTON0_HYSTERESIS_VALUE (cy_capsense_tuner.widgetContext[0].hysteresis) +#define CY_CAPSENSE_BUTTON0_HYSTERESIS_OFFSET (56u) +#define CY_CAPSENSE_BUTTON0_HYSTERESIS_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_HYSTERESIS_PARAM_ID (0x06000038u) + +#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_VALUE (cy_capsense_tuner.widgetContext[0].onDebounce) +#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_OFFSET (58u) +#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_PARAM_ID (0x0500003au) + +#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_VALUE (cy_capsense_tuner.widgetContext[0].snsClkSource) +#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_OFFSET (59u) +#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_PARAM_ID (0x0500003bu) + +#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[0].idacMod[0]) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_OFFSET (60u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_PARAM_ID (0x0500003cu) + +#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[0].idacMod[1]) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_OFFSET (61u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_PARAM_ID (0x0500003du) + +#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[0].idacMod[2]) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_OFFSET (62u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_PARAM_ID (0x0500003eu) + +#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_VALUE (cy_capsense_tuner.widgetContext[0].idacGainIndex) +#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_OFFSET (63u) +#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_PARAM_ID (0x0500003fu) + +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[0].rowIdacMod[0]) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_OFFSET (64u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_PARAM_ID (0x05000040u) + +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[0].rowIdacMod[1]) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_OFFSET (65u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_PARAM_ID (0x05000041u) + +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[0].rowIdacMod[2]) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_OFFSET (66u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_PARAM_ID (0x05000042u) + +#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_VALUE (cy_capsense_tuner.widgetContext[0].bslnCoeff) +#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_OFFSET (67u) +#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_PARAM_ID (0x01000043u) + +#define CY_CAPSENSE_BUTTON0_STATUS_VALUE (cy_capsense_tuner.widgetContext[0].status) +#define CY_CAPSENSE_BUTTON0_STATUS_OFFSET (68u) +#define CY_CAPSENSE_BUTTON0_STATUS_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_STATUS_PARAM_ID (0x01000044u) + +#define CY_CAPSENSE_BUTTON0_PTRPOSITION_VALUE (cy_capsense_tuner.widgetContext[0].wdTouch.ptrPosition) +#define CY_CAPSENSE_BUTTON0_PTRPOSITION_OFFSET (72u) +#define CY_CAPSENSE_BUTTON0_PTRPOSITION_SIZE (4u) +#define CY_CAPSENSE_BUTTON0_PTRPOSITION_PARAM_ID (0x03000048u) + +#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_VALUE (cy_capsense_tuner.widgetContext[0].wdTouch.numPosition) +#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_OFFSET (76u) +#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_PARAM_ID (0x0100004cu) + +#define CY_CAPSENSE_BUTTON1_FINGER_CP_VALUE (cy_capsense_tuner.widgetContext[1].fingerCap) +#define CY_CAPSENSE_BUTTON1_FINGER_CP_OFFSET (80u) +#define CY_CAPSENSE_BUTTON1_FINGER_CP_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_FINGER_CP_PARAM_ID (0x06010050u) + +#define CY_CAPSENSE_BUTTON1_SIGPFC_VALUE (cy_capsense_tuner.widgetContext[1].sigPFC) +#define CY_CAPSENSE_BUTTON1_SIGPFC_OFFSET (82u) +#define CY_CAPSENSE_BUTTON1_SIGPFC_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_SIGPFC_PARAM_ID (0x06010052u) + +#define CY_CAPSENSE_BUTTON1_NUM_CONV_VALUE (cy_capsense_tuner.widgetContext[1].resolution) +#define CY_CAPSENSE_BUTTON1_NUM_CONV_OFFSET (84u) +#define CY_CAPSENSE_BUTTON1_NUM_CONV_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_NUM_CONV_PARAM_ID (0x06010054u) + +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_VALUE (cy_capsense_tuner.widgetContext[1].maxRawCount) +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_OFFSET (86u) +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_PARAM_ID (0x02010056u) + +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_VALUE (cy_capsense_tuner.widgetContext[1].maxRawCountRow) +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_OFFSET (88u) +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_PARAM_ID (0x02010058u) + +#define CY_CAPSENSE_BUTTON1_FINGER_TH_VALUE (cy_capsense_tuner.widgetContext[1].fingerTh) +#define CY_CAPSENSE_BUTTON1_FINGER_TH_OFFSET (90u) +#define CY_CAPSENSE_BUTTON1_FINGER_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_FINGER_TH_PARAM_ID (0x0601005au) + +#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_VALUE (cy_capsense_tuner.widgetContext[1].proxTh) +#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_OFFSET (92u) +#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_PARAM_ID (0x0601005cu) + +#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_VALUE (cy_capsense_tuner.widgetContext[1].lowBslnRst) +#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_OFFSET (94u) +#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_PARAM_ID (0x0601005eu) + +#define CY_CAPSENSE_BUTTON1_TX_CLK_VALUE (cy_capsense_tuner.widgetContext[1].snsClk) +#define CY_CAPSENSE_BUTTON1_TX_CLK_OFFSET (96u) +#define CY_CAPSENSE_BUTTON1_TX_CLK_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_TX_CLK_PARAM_ID (0x06010060u) + +#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_VALUE (cy_capsense_tuner.widgetContext[1].rowSnsClk) +#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_OFFSET (98u) +#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_PARAM_ID (0x06010062u) + +#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_VALUE (cy_capsense_tuner.widgetContext[1].gestureDetected) +#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_OFFSET (100u) +#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_PARAM_ID (0x02010064u) + +#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_VALUE (cy_capsense_tuner.widgetContext[1].gestureDirection) +#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_OFFSET (102u) +#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_PARAM_ID (0x02010066u) + +#define CY_CAPSENSE_BUTTON1_XDELTA_VALUE (cy_capsense_tuner.widgetContext[1].xDelta) +#define CY_CAPSENSE_BUTTON1_XDELTA_OFFSET (104u) +#define CY_CAPSENSE_BUTTON1_XDELTA_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_XDELTA_PARAM_ID (0x02010068u) + +#define CY_CAPSENSE_BUTTON1_YDELTA_VALUE (cy_capsense_tuner.widgetContext[1].yDelta) +#define CY_CAPSENSE_BUTTON1_YDELTA_OFFSET (106u) +#define CY_CAPSENSE_BUTTON1_YDELTA_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_YDELTA_PARAM_ID (0x0201006au) + +#define CY_CAPSENSE_BUTTON1_NOISE_TH_VALUE (cy_capsense_tuner.widgetContext[1].noiseTh) +#define CY_CAPSENSE_BUTTON1_NOISE_TH_OFFSET (108u) +#define CY_CAPSENSE_BUTTON1_NOISE_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_NOISE_TH_PARAM_ID (0x0601006cu) + +#define CY_CAPSENSE_BUTTON1_NNOISE_TH_VALUE (cy_capsense_tuner.widgetContext[1].nNoiseTh) +#define CY_CAPSENSE_BUTTON1_NNOISE_TH_OFFSET (110u) +#define CY_CAPSENSE_BUTTON1_NNOISE_TH_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_NNOISE_TH_PARAM_ID (0x0601006eu) + +#define CY_CAPSENSE_BUTTON1_HYSTERESIS_VALUE (cy_capsense_tuner.widgetContext[1].hysteresis) +#define CY_CAPSENSE_BUTTON1_HYSTERESIS_OFFSET (112u) +#define CY_CAPSENSE_BUTTON1_HYSTERESIS_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_HYSTERESIS_PARAM_ID (0x06010070u) + +#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_VALUE (cy_capsense_tuner.widgetContext[1].onDebounce) +#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_OFFSET (114u) +#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_PARAM_ID (0x05010072u) + +#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_VALUE (cy_capsense_tuner.widgetContext[1].snsClkSource) +#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_OFFSET (115u) +#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_PARAM_ID (0x05010073u) + +#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[1].idacMod[0]) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_OFFSET (116u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_PARAM_ID (0x05010074u) + +#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[1].idacMod[1]) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_OFFSET (117u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_PARAM_ID (0x05010075u) + +#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[1].idacMod[2]) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_OFFSET (118u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_PARAM_ID (0x05010076u) + +#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_VALUE (cy_capsense_tuner.widgetContext[1].idacGainIndex) +#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_OFFSET (119u) +#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_PARAM_ID (0x05010077u) + +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[1].rowIdacMod[0]) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_OFFSET (120u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_PARAM_ID (0x05010078u) + +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[1].rowIdacMod[1]) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_OFFSET (121u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_PARAM_ID (0x05010079u) + +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[1].rowIdacMod[2]) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_OFFSET (122u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_PARAM_ID (0x0501007au) + +#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_VALUE (cy_capsense_tuner.widgetContext[1].bslnCoeff) +#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_OFFSET (123u) +#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_PARAM_ID (0x0101007bu) + +#define CY_CAPSENSE_BUTTON1_STATUS_VALUE (cy_capsense_tuner.widgetContext[1].status) +#define CY_CAPSENSE_BUTTON1_STATUS_OFFSET (124u) +#define CY_CAPSENSE_BUTTON1_STATUS_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_STATUS_PARAM_ID (0x0101007cu) + +#define CY_CAPSENSE_BUTTON1_PTRPOSITION_VALUE (cy_capsense_tuner.widgetContext[1].wdTouch.ptrPosition) +#define CY_CAPSENSE_BUTTON1_PTRPOSITION_OFFSET (128u) +#define CY_CAPSENSE_BUTTON1_PTRPOSITION_SIZE (4u) +#define CY_CAPSENSE_BUTTON1_PTRPOSITION_PARAM_ID (0x03010080u) + +#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_VALUE (cy_capsense_tuner.widgetContext[1].wdTouch.numPosition) +#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_OFFSET (132u) +#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_PARAM_ID (0x01010084u) + +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_VALUE (cy_capsense_tuner.widgetContext[2].fingerCap) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_OFFSET (136u) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_PARAM_ID (0x06020088u) + +#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_VALUE (cy_capsense_tuner.widgetContext[2].sigPFC) +#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_OFFSET (138u) +#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_PARAM_ID (0x0602008au) + +#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_VALUE (cy_capsense_tuner.widgetContext[2].resolution) +#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_OFFSET (140u) +#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_PARAM_ID (0x0602008cu) + +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_VALUE (cy_capsense_tuner.widgetContext[2].maxRawCount) +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_OFFSET (142u) +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_PARAM_ID (0x0202008eu) + +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_VALUE (cy_capsense_tuner.widgetContext[2].maxRawCountRow) +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_OFFSET (144u) +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_PARAM_ID (0x02020090u) + +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_VALUE (cy_capsense_tuner.widgetContext[2].fingerTh) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_OFFSET (146u) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_PARAM_ID (0x02020092u) + +#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_VALUE (cy_capsense_tuner.widgetContext[2].proxTh) +#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET (148u) +#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_PARAM_ID (0x02020094u) + +#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_VALUE (cy_capsense_tuner.widgetContext[2].lowBslnRst) +#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_OFFSET (150u) +#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_PARAM_ID (0x06020096u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_VALUE (cy_capsense_tuner.widgetContext[2].snsClk) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_OFFSET (152u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_PARAM_ID (0x06020098u) + +#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_VALUE (cy_capsense_tuner.widgetContext[2].rowSnsClk) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_OFFSET (154u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_PARAM_ID (0x0602009au) + +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_VALUE (cy_capsense_tuner.widgetContext[2].gestureDetected) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_OFFSET (156u) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_PARAM_ID (0x0202009cu) + +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_VALUE (cy_capsense_tuner.widgetContext[2].gestureDirection) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET (158u) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_PARAM_ID (0x0202009eu) + +#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_VALUE (cy_capsense_tuner.widgetContext[2].xDelta) +#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_OFFSET (160u) +#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_PARAM_ID (0x020200a0u) + +#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_VALUE (cy_capsense_tuner.widgetContext[2].yDelta) +#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_OFFSET (162u) +#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_PARAM_ID (0x020200a2u) + +#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_VALUE (cy_capsense_tuner.widgetContext[2].noiseTh) +#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_OFFSET (164u) +#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_PARAM_ID (0x020200a4u) + +#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_VALUE (cy_capsense_tuner.widgetContext[2].nNoiseTh) +#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_OFFSET (166u) +#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_PARAM_ID (0x020200a6u) + +#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_VALUE (cy_capsense_tuner.widgetContext[2].hysteresis) +#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_OFFSET (168u) +#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_PARAM_ID (0x020200a8u) + +#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_VALUE (cy_capsense_tuner.widgetContext[2].onDebounce) +#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_OFFSET (170u) +#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_PARAM_ID (0x050200aau) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_VALUE (cy_capsense_tuner.widgetContext[2].snsClkSource) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET (171u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_PARAM_ID (0x050200abu) + +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[2].idacMod[0]) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_OFFSET (172u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_PARAM_ID (0x050200acu) + +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[2].idacMod[1]) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_OFFSET (173u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_PARAM_ID (0x050200adu) + +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[2].idacMod[2]) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_OFFSET (174u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_PARAM_ID (0x050200aeu) + +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_VALUE (cy_capsense_tuner.widgetContext[2].idacGainIndex) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET (175u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_PARAM_ID (0x050200afu) + +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_VALUE (cy_capsense_tuner.widgetContext[2].rowIdacMod[0]) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET (176u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_PARAM_ID (0x050200b0u) + +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_VALUE (cy_capsense_tuner.widgetContext[2].rowIdacMod[1]) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET (177u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_PARAM_ID (0x050200b1u) + +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_VALUE (cy_capsense_tuner.widgetContext[2].rowIdacMod[2]) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET (178u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_PARAM_ID (0x050200b2u) + +#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_VALUE (cy_capsense_tuner.widgetContext[2].bslnCoeff) +#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET (179u) +#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_PARAM_ID (0x010200b3u) + +#define CY_CAPSENSE_LINEARSLIDER0_STATUS_VALUE (cy_capsense_tuner.widgetContext[2].status) +#define CY_CAPSENSE_LINEARSLIDER0_STATUS_OFFSET (180u) +#define CY_CAPSENSE_LINEARSLIDER0_STATUS_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_STATUS_PARAM_ID (0x010200b4u) + +#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_VALUE (cy_capsense_tuner.widgetContext[2].wdTouch.ptrPosition) +#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_OFFSET (184u) +#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_SIZE (4u) +#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_PARAM_ID (0x030200b8u) + +#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_VALUE (cy_capsense_tuner.widgetContext[2].wdTouch.numPosition) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_OFFSET (188u) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_PARAM_ID (0x010200bcu) + +#define CY_CAPSENSE_BUTTON0_RX0_RAW0_VALUE (cy_capsense_tuner.sensorContext[0].raw) +#define CY_CAPSENSE_BUTTON0_RX0_RAW0_OFFSET (192u) +#define CY_CAPSENSE_BUTTON0_RX0_RAW0_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_RX0_RAW0_PARAM_ID (0x020000c0u) + +#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_VALUE (cy_capsense_tuner.sensorContext[0].bsln) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_OFFSET (194u) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_PARAM_ID (0x020000c2u) + +#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_VALUE (cy_capsense_tuner.sensorContext[0].diff) +#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_OFFSET (196u) +#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_SIZE (2u) +#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_PARAM_ID (0x020000c4u) + +#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_VALUE (cy_capsense_tuner.sensorContext[0].status) +#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_OFFSET (198u) +#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_PARAM_ID (0x010000c6u) + +#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[0].negBslnRstCnt) +#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_OFFSET (199u) +#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_PARAM_ID (0x010000c7u) + +#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_VALUE (cy_capsense_tuner.sensorContext[0].idacComp) +#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_OFFSET (200u) +#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_PARAM_ID (0x010000c8u) + +#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[0].bslnExt) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_OFFSET (201u) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_PARAM_ID (0x010000c9u) + +#define CY_CAPSENSE_BUTTON1_RX0_RAW0_VALUE (cy_capsense_tuner.sensorContext[1].raw) +#define CY_CAPSENSE_BUTTON1_RX0_RAW0_OFFSET (202u) +#define CY_CAPSENSE_BUTTON1_RX0_RAW0_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_RX0_RAW0_PARAM_ID (0x020100cau) + +#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_VALUE (cy_capsense_tuner.sensorContext[1].bsln) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_OFFSET (204u) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_PARAM_ID (0x020100ccu) + +#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_VALUE (cy_capsense_tuner.sensorContext[1].diff) +#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_OFFSET (206u) +#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_SIZE (2u) +#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_PARAM_ID (0x020100ceu) + +#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_VALUE (cy_capsense_tuner.sensorContext[1].status) +#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_OFFSET (208u) +#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_PARAM_ID (0x010100d0u) + +#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[1].negBslnRstCnt) +#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_OFFSET (209u) +#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_PARAM_ID (0x010100d1u) + +#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_VALUE (cy_capsense_tuner.sensorContext[1].idacComp) +#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_OFFSET (210u) +#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_PARAM_ID (0x010100d2u) + +#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[1].bslnExt) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_OFFSET (211u) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_PARAM_ID (0x010100d3u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_VALUE (cy_capsense_tuner.sensorContext[2].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_OFFSET (212u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_PARAM_ID (0x020200d4u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_VALUE (cy_capsense_tuner.sensorContext[2].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_OFFSET (214u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_PARAM_ID (0x020200d6u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_VALUE (cy_capsense_tuner.sensorContext[2].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_OFFSET (216u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_PARAM_ID (0x020200d8u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_VALUE (cy_capsense_tuner.sensorContext[2].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_OFFSET (218u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_PARAM_ID (0x010200dau) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[2].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET (219u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID (0x010200dbu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_VALUE (cy_capsense_tuner.sensorContext[2].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_OFFSET (220u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_PARAM_ID (0x010200dcu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[2].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET (221u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_PARAM_ID (0x010200ddu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_VALUE (cy_capsense_tuner.sensorContext[3].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_OFFSET (222u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_PARAM_ID (0x020200deu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_VALUE (cy_capsense_tuner.sensorContext[3].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_OFFSET (224u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_PARAM_ID (0x020200e0u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_VALUE (cy_capsense_tuner.sensorContext[3].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_OFFSET (226u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_PARAM_ID (0x020200e2u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_VALUE (cy_capsense_tuner.sensorContext[3].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_OFFSET (228u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_PARAM_ID (0x010200e4u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[3].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET (229u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_PARAM_ID (0x010200e5u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_VALUE (cy_capsense_tuner.sensorContext[3].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_OFFSET (230u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_PARAM_ID (0x010200e6u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[3].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET (231u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_PARAM_ID (0x010200e7u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_VALUE (cy_capsense_tuner.sensorContext[4].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_OFFSET (232u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_PARAM_ID (0x020200e8u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_VALUE (cy_capsense_tuner.sensorContext[4].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_OFFSET (234u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_PARAM_ID (0x020200eau) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_VALUE (cy_capsense_tuner.sensorContext[4].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_OFFSET (236u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_PARAM_ID (0x020200ecu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_VALUE (cy_capsense_tuner.sensorContext[4].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_OFFSET (238u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_PARAM_ID (0x010200eeu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[4].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET (239u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_PARAM_ID (0x010200efu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_VALUE (cy_capsense_tuner.sensorContext[4].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_OFFSET (240u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_PARAM_ID (0x010200f0u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[4].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET (241u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_PARAM_ID (0x010200f1u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_VALUE (cy_capsense_tuner.sensorContext[5].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_OFFSET (242u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_PARAM_ID (0x020200f2u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_VALUE (cy_capsense_tuner.sensorContext[5].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_OFFSET (244u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_PARAM_ID (0x020200f4u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_VALUE (cy_capsense_tuner.sensorContext[5].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_OFFSET (246u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_PARAM_ID (0x020200f6u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_VALUE (cy_capsense_tuner.sensorContext[5].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_OFFSET (248u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_PARAM_ID (0x010200f8u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[5].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET (249u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_PARAM_ID (0x010200f9u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_VALUE (cy_capsense_tuner.sensorContext[5].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_OFFSET (250u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_PARAM_ID (0x010200fau) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[5].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET (251u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_PARAM_ID (0x010200fbu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_VALUE (cy_capsense_tuner.sensorContext[6].raw) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_OFFSET (252u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_PARAM_ID (0x020200fcu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_VALUE (cy_capsense_tuner.sensorContext[6].bsln) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_OFFSET (254u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_PARAM_ID (0x020200feu) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_VALUE (cy_capsense_tuner.sensorContext[6].diff) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_OFFSET (256u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_PARAM_ID (0x02020100u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_VALUE (cy_capsense_tuner.sensorContext[6].status) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_OFFSET (258u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_PARAM_ID (0x01020102u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_VALUE (cy_capsense_tuner.sensorContext[6].negBslnRstCnt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET (259u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_PARAM_ID (0x01020103u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_VALUE (cy_capsense_tuner.sensorContext[6].idacComp) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_OFFSET (260u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_PARAM_ID (0x01020104u) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_VALUE (cy_capsense_tuner.sensorContext[6].bslnExt) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET (261u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE (1u) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_PARAM_ID (0x01020105u) + +#define CY_CAPSENSE_LINEARSLIDER0_X0_VALUE (cy_capsense_tuner.position[0].x) +#define CY_CAPSENSE_LINEARSLIDER0_X0_OFFSET (262u) +#define CY_CAPSENSE_LINEARSLIDER0_X0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_X0_PARAM_ID (0x02020106u) + +#define CY_CAPSENSE_LINEARSLIDER0_Y0_VALUE (cy_capsense_tuner.position[0].y) +#define CY_CAPSENSE_LINEARSLIDER0_Y0_OFFSET (264u) +#define CY_CAPSENSE_LINEARSLIDER0_Y0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_Y0_PARAM_ID (0x02020108u) + +#define CY_CAPSENSE_LINEARSLIDER0_Z0_VALUE (cy_capsense_tuner.position[0].z) +#define CY_CAPSENSE_LINEARSLIDER0_Z0_OFFSET (266u) +#define CY_CAPSENSE_LINEARSLIDER0_Z0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_Z0_PARAM_ID (0x0202010au) + +#define CY_CAPSENSE_LINEARSLIDER0_ID0_VALUE (cy_capsense_tuner.position[0].id) +#define CY_CAPSENSE_LINEARSLIDER0_ID0_OFFSET (268u) +#define CY_CAPSENSE_LINEARSLIDER0_ID0_SIZE (2u) +#define CY_CAPSENSE_LINEARSLIDER0_ID0_PARAM_ID (0x0202010cu) + +#endif +/* cy_capsense_context */ +#define CY_CAPSENSE_COMMON_CONFIG_PTR_VALUE (cy_capsense_context.ptrCommonConfig) +#define CY_CAPSENSE_COMMON_CONFIG_PTR_SIZE (sizeof(cy_capsense_context.ptrCommonConfig)) + +#define CY_CAPSENSE_COMMON_CONTEXT_PTR_VALUE (cy_capsense_context.ptrCommonContext) +#define CY_CAPSENSE_COMMON_CONTEXT_PTR_SIZE (sizeof(cy_capsense_context.ptrCommonContext)) + +#define CY_CAPSENSE_INTERNAL_CONTEXT_PTR_VALUE (cy_capsense_context.ptrInternalContext) +#define CY_CAPSENSE_INTERNAL_CONTEXT_PTR_SIZE (sizeof(cy_capsense_context.ptrInternalContext)) + +#define CY_CAPSENSE_WD_CONFIG_PTR_VALUE (cy_capsense_context.ptrWdConfig) +#define CY_CAPSENSE_WD_CONFIG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig)) + +#define CY_CAPSENSE_WD_CONTEXT_PTR_VALUE (cy_capsense_context.ptrWdContext) +#define CY_CAPSENSE_WD_CONTEXT_PTR_SIZE (sizeof(cy_capsense_context.ptrWdContext)) + +#define CY_CAPSENSE_PIN_CONFIG_PTR_VALUE (cy_capsense_context.ptrPinConfig) +#define CY_CAPSENSE_PIN_CONFIG_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig)) + +#define CY_CAPSENSE_SHIELD_PIN_CONFIG_PTR_VALUE (cy_capsense_context.ptrShieldPinConfig) +#define CY_CAPSENSE_SHIELD_PIN_CONFIG_PTR_SIZE (sizeof(cy_capsense_context.ptrShieldPinConfig)) + +#define CY_CAPSENSE_ACTIVE_SCAN_SNS_PTR_VALUE (cy_capsense_context.ptrActiveScanSns) +#define CY_CAPSENSE_ACTIVE_SCAN_SNS_PTR_SIZE (sizeof(cy_capsense_context.ptrActiveScanSns)) + +#if (CY_CAPSENSE_MW_VERSION < 300) +#define CY_CAPSENSE_FPTR_CONFIG_PTR_VALUE (cy_capsense_context.ptrFptrConfig) +#define CY_CAPSENSE_FPTR_CONFIG_PTR_SIZE (sizeof(cy_capsense_context.ptrFptrConfig)) +#endif + +#define CY_CAPSENSE_BIST_CONTEXT_PTR_VALUE (cy_capsense_context.ptrBistContext) +#define CY_CAPSENSE_BIST_CONTEXT_PTR_SIZE (sizeof(cy_capsense_context.ptrBistContext)) + +/* cy_capsense_commonConfig */ +#define CY_CAPSENSE_CPU_CLK_HZ_VALUE (cy_capsense_context.ptrCommonConfig->cpuClkHz) +#define CY_CAPSENSE_CPU_CLK_HZ_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->cpuClkHz)) + +#define CY_CAPSENSE_PERI_CLK_HZ_VALUE (cy_capsense_context.ptrCommonConfig->periClkHz) +#define CY_CAPSENSE_PERI_CLK_HZ_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->periClkHz)) + +#define CY_CAPSENSE_VDDA_VALUE (cy_capsense_context.ptrCommonConfig->vdda) +#define CY_CAPSENSE_VDDA_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->vdda)) + +#define CY_CAPSENSE_NUM_PIN_VALUE (cy_capsense_context.ptrCommonConfig->numPin) +#define CY_CAPSENSE_NUM_PIN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->numPin)) + +#define CY_CAPSENSE_NUM_SNS_VALUE (cy_capsense_context.ptrCommonConfig->numSns) +#define CY_CAPSENSE_NUM_SNS_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->numSns)) + +#define CY_CAPSENSE_NUM_WD_VALUE (cy_capsense_context.ptrCommonConfig->numWd) +#define CY_CAPSENSE_NUM_WD_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->numWd)) + +#define CY_CAPSENSE_CSD_EN_VALUE (cy_capsense_context.ptrCommonConfig->csdEn) +#define CY_CAPSENSE_CSD_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdEn)) + +#define CY_CAPSENSE_CSX_EN_VALUE (cy_capsense_context.ptrCommonConfig->csxEn) +#define CY_CAPSENSE_CSX_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxEn)) + +#if (CY_CAPSENSE_MW_VERSION < 300) +#define CY_CAPSENSE_MFS_EN_VALUE (cy_capsense_context.ptrCommonConfig->mfsEn) +#define CY_CAPSENSE_MFS_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->mfsEn)) +#endif + +#define CY_CAPSENSE_BIST_EN_VALUE (cy_capsense_context.ptrCommonConfig->bistEn) +#define CY_CAPSENSE_BIST_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->bistEn)) + +#define CY_CAPSENSE_POSITION_FILTER_EN_VALUE (cy_capsense_context.ptrCommonConfig->positionFilterEn) +#define CY_CAPSENSE_POSITION_FILTER_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->positionFilterEn)) + +#define CY_CAPSENSE_PERI_DIVIDER_TYPE_VALUE (cy_capsense_context.ptrCommonConfig->periDividerType) +#define CY_CAPSENSE_PERI_DIVIDER_TYPE_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->periDividerType)) + +#define CY_CAPSENSE_PERI_DIVIDER_INDEX_VALUE (cy_capsense_context.ptrCommonConfig->periDividerIndex) +#define CY_CAPSENSE_PERI_DIVIDER_INDEX_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->periDividerIndex)) + +#define CY_CAPSENSE_ANALOG_WAKEUP_DELAY_VALUE (cy_capsense_context.ptrCommonConfig->analogWakeupDelay) +#define CY_CAPSENSE_ANALOG_WAKEUP_DELAY_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->analogWakeupDelay)) + +#define CY_CAPSENSE_SS_IREF_SOURCE_VALUE (cy_capsense_context.ptrCommonConfig->ssIrefSource) +#define CY_CAPSENSE_SS_IREF_SOURCE_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->ssIrefSource)) + +#define CY_CAPSENSE_SS_VREF_SOURCE_VALUE (cy_capsense_context.ptrCommonConfig->ssVrefSource) +#define CY_CAPSENSE_SS_VREF_SOURCE_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->ssVrefSource)) + +#define CY_CAPSENSE_PROX_TOUCH_COEFF_VALUE (cy_capsense_context.ptrCommonConfig->proxTouchCoeff) +#define CY_CAPSENSE_PROX_TOUCH_COEFF_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->proxTouchCoeff)) + +#define CY_CAPSENSE_SW_SENSOR_AUTO_RESET_EN_VALUE (cy_capsense_context.ptrCommonConfig->swSensorAutoResetEn) +#define CY_CAPSENSE_SW_SENSOR_AUTO_RESET_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->swSensorAutoResetEn)) + +#define CY_CAPSENSE_PORT_CMOD_PAD_NUM_VALUE (cy_capsense_context.ptrCommonConfig->portCmodPadNum) +#define CY_CAPSENSE_PORT_CMOD_PAD_NUM_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portCmodPadNum)) + +#define CY_CAPSENSE_PIN_CMOD_PAD_VALUE (cy_capsense_context.ptrCommonConfig->pinCmodPad) +#define CY_CAPSENSE_PIN_CMOD_PAD_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->pinCmodPad)) + +#define CY_CAPSENSE_PORT_CSH_PAD_NUM_VALUE (cy_capsense_context.ptrCommonConfig->portCshPadNum) +#define CY_CAPSENSE_PORT_CSH_PAD_NUM_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portCshPadNum)) + +#define CY_CAPSENSE_PIN_CSH_PAD_VALUE (cy_capsense_context.ptrCommonConfig->pinCshPad) +#define CY_CAPSENSE_PIN_CSH_PAD_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->pinCshPad)) + +#define CY_CAPSENSE_PORT_SHIELD_PAD_NUM_VALUE (cy_capsense_context.ptrCommonConfig->portShieldPadNum) +#define CY_CAPSENSE_PORT_SHIELD_PAD_NUM_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portShieldPadNum)) + +#define CY_CAPSENSE_PIN_SHIELD_PAD_VALUE (cy_capsense_context.ptrCommonConfig->pinShieldPad) +#define CY_CAPSENSE_PIN_SHIELD_PAD_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->pinShieldPad)) + +#define CY_CAPSENSE_PORT_VREF_EXT_PAD_NUM_VALUE (cy_capsense_context.ptrCommonConfig->portVrefExtPadNum) +#define CY_CAPSENSE_PORT_VREF_EXT_PAD_NUM_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portVrefExtPadNum)) + +#define CY_CAPSENSE_PIN_VREF_EXT_PAD_VALUE (cy_capsense_context.ptrCommonConfig->pinVrefExtPad) +#define CY_CAPSENSE_PIN_VREF_EXT_PAD_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->pinVrefExtPad)) + +#define CY_CAPSENSE_PORT_CMOD_NUM_VALUE (cy_capsense_context.ptrCommonConfig->portCmodNum) +#define CY_CAPSENSE_PORT_CMOD_NUM_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portCmodNum)) + +#define CY_CAPSENSE_IDAC_GAIN_TABLE_PTR_VALUE (&cy_capsense_context.ptrCommonConfig->idacGainTable[0u]) +#define CY_CAPSENSE_IDAC_GAIN_TABLE_PTR_SIZE (sizeof(&cy_capsense_context.ptrCommonConfig->idacGainTable[0u])) + +#define CY_CAPSENSE_PTR_CSD_BASE_VALUE (cy_capsense_context.ptrCommonConfig->ptrCsdBase) +#define CY_CAPSENSE_PTR_CSD_BASE_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->ptrCsdBase)) + +#define CY_CAPSENSE_PTR_CSD_CONTEXT_VALUE (cy_capsense_context.ptrCommonConfig->ptrCsdContext) +#define CY_CAPSENSE_PTR_CSD_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->ptrCsdContext)) + +#define CY_CAPSENSE_PORT_CMOD_VALUE (cy_capsense_context.ptrCommonConfig->portCmod) +#define CY_CAPSENSE_PORT_CMOD_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portCmod)) + +#define CY_CAPSENSE_PORT_CSH_VALUE (cy_capsense_context.ptrCommonConfig->portCsh) +#define CY_CAPSENSE_PORT_CSH_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portCsh)) + +#define CY_CAPSENSE_PORT_CINT_A_VALUE (cy_capsense_context.ptrCommonConfig->portCintA) +#define CY_CAPSENSE_PORT_CINT_A_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portCintA)) + +#define CY_CAPSENSE_PORT_CINT_B_VALUE (cy_capsense_context.ptrCommonConfig->portCintB) +#define CY_CAPSENSE_PORT_CINT_B_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portCintB)) + +#define CY_CAPSENSE_PIN_CMOD_VALUE (cy_capsense_context.ptrCommonConfig->pinCmod) +#define CY_CAPSENSE_PIN_CMOD_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->pinCmod)) + +#define CY_CAPSENSE_PORT_CSH_NUM_VALUE (cy_capsense_context.ptrCommonConfig->portCshNum) +#define CY_CAPSENSE_PORT_CSH_NUM_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->portCshNum)) + +#define CY_CAPSENSE_PIN_CSH_VALUE (cy_capsense_context.ptrCommonConfig->pinCsh) +#define CY_CAPSENSE_PIN_CSH_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->pinCsh)) + +#define CY_CAPSENSE_PIN_CINT_A_VALUE (cy_capsense_context.ptrCommonConfig->pinCintA) +#define CY_CAPSENSE_PIN_CINT_A_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->pinCintA)) + +#define CY_CAPSENSE_PIN_CINT_B_VALUE (cy_capsense_context.ptrCommonConfig->pinCintB) +#define CY_CAPSENSE_PIN_CINT_B_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->pinCintB)) + +#define CY_CAPSENSE_CSD_SHIELD_EN_VALUE (cy_capsense_context.ptrCommonConfig->csdShieldEn) +#define CY_CAPSENSE_CSD_SHIELD_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldEn)) + +#define CY_CAPSENSE_CSD_INACTIVE_SNS_CONNECTION_VALUE (cy_capsense_context.ptrCommonConfig->csdInactiveSnsConnection) +#define CY_CAPSENSE_CSD_INACTIVE_SNS_CONNECTION_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdInactiveSnsConnection)) + +#if (CY_CAPSENSE_MW_VERSION >= 300) +#define CY_CAPSENSE_CSX_INACTIVE_SNS_CONNECTION_VALUE (cy_capsense_context.ptrCommonConfig->csxInactiveSnsConnection) +#define CY_CAPSENSE_CSX_INACTIVE_SNS_CONNECTION_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxInactiveSnsConnection)) +#endif + +#define CY_CAPSENSE_CSD_SHIELD_DELAY_VALUE (cy_capsense_context.ptrCommonConfig->csdShieldDelay) +#define CY_CAPSENSE_CSD_SHIELD_DELAY_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldDelay)) + +#define CY_CAPSENSE_CSD_VREF_VALUE (cy_capsense_context.ptrCommonConfig->csdVref) +#define CY_CAPSENSE_CSD_VREF_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdVref)) + +#define CY_CAPSENSE_CSD_R_CONST_VALUE (cy_capsense_context.ptrCommonConfig->csdRConst) +#define CY_CAPSENSE_CSD_R_CONST_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdRConst)) + +#define CY_CAPSENSE_CSD_C_TANK_SHIELD_EN_VALUE (cy_capsense_context.ptrCommonConfig->csdCTankShieldEn) +#define CY_CAPSENSE_CSD_C_TANK_SHIELD_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdCTankShieldEn)) + +#define CY_CAPSENSE_CSD_SHIELD_NUM_PIN_VALUE (cy_capsense_context.ptrCommonConfig->csdShieldNumPin) +#define CY_CAPSENSE_CSD_SHIELD_NUM_PIN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldNumPin)) + +#define CY_CAPSENSE_CSD_SHIELD_SW_RES_VALUE (cy_capsense_context.ptrCommonConfig->csdShieldSwRes) +#define CY_CAPSENSE_CSD_SHIELD_SW_RES_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldSwRes)) + +#define CY_CAPSENSE_CSD_INIT_SW_RES_VALUE (cy_capsense_context.ptrCommonConfig->csdInitSwRes) +#define CY_CAPSENSE_CSD_INIT_SW_RES_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdInitSwRes)) + +#define CY_CAPSENSE_CSD_CHARGE_TRANSFER_VALUE (cy_capsense_context.ptrCommonConfig->csdChargeTransfer) +#define CY_CAPSENSE_CSD_CHARGE_TRANSFER_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdChargeTransfer)) + +#define CY_CAPSENSE_CSD_RAW_TARGET_VALUE (cy_capsense_context.ptrCommonConfig->csdRawTarget) +#define CY_CAPSENSE_CSD_RAW_TARGET_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdRawTarget)) + +#define CY_CAPSENSE_CSD_AUTOTUNE_EN_VALUE (cy_capsense_context.ptrCommonConfig->csdAutotuneEn) +#define CY_CAPSENSE_CSD_AUTOTUNE_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdAutotuneEn)) + +#define CY_CAPSENSE_CSD_IDAC_AUTOCAL_EN_VALUE (cy_capsense_context.ptrCommonConfig->csdIdacAutocalEn) +#define CY_CAPSENSE_CSD_IDAC_AUTOCAL_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacAutocalEn)) + +#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN_VALUE (cy_capsense_context.ptrCommonConfig->csdIdacAutoGainEn) +#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacAutoGainEn)) + +#define CY_CAPSENSE_CSD_CALIBRATION_ERROR_VALUE (cy_capsense_context.ptrCommonConfig->csdCalibrationError) +#define CY_CAPSENSE_CSD_CALIBRATION_ERROR_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdCalibrationError)) + +#define CY_CAPSENSE_CSD_IDAC_GAIN_INIT_INDEX_VALUE (cy_capsense_context.ptrCommonConfig->csdIdacGainInitIndex) +#define CY_CAPSENSE_CSD_IDAC_GAIN_INIT_INDEX_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacGainInitIndex)) + +#define CY_CAPSENSE_CSD_IDAC_MIN_VALUE (cy_capsense_context.ptrCommonConfig->csdIdacMin) +#define CY_CAPSENSE_CSD_IDAC_MIN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacMin)) + +#define CY_CAPSENSE_CSD_IDAC_COMP_EN_VALUE (cy_capsense_context.ptrCommonConfig->csdIdacCompEn) +#define CY_CAPSENSE_CSD_IDAC_COMP_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacCompEn)) + +#define CY_CAPSENSE_CSD_FINE_INIT_TIME_VALUE (cy_capsense_context.ptrCommonConfig->csdFineInitTime) +#define CY_CAPSENSE_CSD_FINE_INIT_TIME_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdFineInitTime)) + +#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN_VALUE (cy_capsense_context.ptrCommonConfig->csdIdacRowColAlignEn) +#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacRowColAlignEn)) + +#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F1_VALUE (cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF1) +#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F1_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF1)) + +#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F2_VALUE (cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF2) +#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F2_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF2)) + +#define CY_CAPSENSE_CSX_RAW_TARGET_VALUE (cy_capsense_context.ptrCommonConfig->csxRawTarget) +#define CY_CAPSENSE_CSX_RAW_TARGET_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxRawTarget)) + +#define CY_CAPSENSE_CSX_IDAC_GAIN_INIT_INDEX_VALUE (cy_capsense_context.ptrCommonConfig->csxIdacGainInitIndex) +#define CY_CAPSENSE_CSX_IDAC_GAIN_INIT_INDEX_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxIdacGainInitIndex)) + +#define CY_CAPSENSE_CSX_REF_GAIN_VALUE (cy_capsense_context.ptrCommonConfig->csxRefGain) +#define CY_CAPSENSE_CSX_REF_GAIN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxRefGain)) + +#define CY_CAPSENSE_CSX_IDAC_AUTOCAL_EN_VALUE (cy_capsense_context.ptrCommonConfig->csxIdacAutocalEn) +#define CY_CAPSENSE_CSX_IDAC_AUTOCAL_EN_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxIdacAutocalEn)) + +#define CY_CAPSENSE_CSX_CALIBRATION_ERROR_VALUE (cy_capsense_context.ptrCommonConfig->csxCalibrationError) +#define CY_CAPSENSE_CSX_CALIBRATION_ERROR_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxCalibrationError)) + +#define CY_CAPSENSE_CSX_FINE_INIT_TIME_VALUE (cy_capsense_context.ptrCommonConfig->csxFineInitTime) +#define CY_CAPSENSE_CSX_FINE_INIT_TIME_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxFineInitTime)) + +#define CY_CAPSENSE_CSX_INIT_SW_RES_VALUE (cy_capsense_context.ptrCommonConfig->csxInitSwRes) +#define CY_CAPSENSE_CSX_INIT_SW_RES_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxInitSwRes)) + +#define CY_CAPSENSE_CSX_SCAN_SW_RES_VALUE (cy_capsense_context.ptrCommonConfig->csxScanSwRes) +#define CY_CAPSENSE_CSX_SCAN_SW_RES_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxScanSwRes)) + +#define CY_CAPSENSE_CSX_INIT_SHIELD_SW_RES_VALUE (cy_capsense_context.ptrCommonConfig->csxInitShieldSwRes) +#define CY_CAPSENSE_CSX_INIT_SHIELD_SW_RES_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxInitShieldSwRes)) + +#define CY_CAPSENSE_CSX_SCAN_SHIELD_SW_RES_VALUE (cy_capsense_context.ptrCommonConfig->csxScanShieldSwRes) +#define CY_CAPSENSE_CSX_SCAN_SHIELD_SW_RES_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxScanShieldSwRes)) + +#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F1_VALUE (cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF1) +#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F1_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF1)) + +#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F2_VALUE (cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF2) +#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F2_SIZE (sizeof(cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF2)) + +/* cy_capsense_widgetConfig */ +#define CY_CAPSENSE_BUTTON0_PTR_WD_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrWdContext) +#define CY_CAPSENSE_BUTTON0_PTR_WD_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrWdContext)) +#define CY_CAPSENSE_BUTTON0_PTR_SNS_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrSnsContext) +#define CY_CAPSENSE_BUTTON0_PTR_SNS_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrSnsContext)) +#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrEltdConfig) +#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrEltdConfig)) +#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CAPACITANCE_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrEltdCapacitance) +#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CAPACITANCE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrEltdCapacitance)) +#define CY_CAPSENSE_BUTTON0_PTR_BSLN_INV_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrBslnInv) +#define CY_CAPSENSE_BUTTON0_PTR_BSLN_INV_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrBslnInv)) +#define CY_CAPSENSE_BUTTON0_PTR_NOISE_ENVELOPE_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrNoiseEnvelope) +#define CY_CAPSENSE_BUTTON0_PTR_NOISE_ENVELOPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrNoiseEnvelope)) +#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistory) +#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistory)) +#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_LOW_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistoryLow) +#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_LOW_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistoryLow)) +#define CY_CAPSENSE_BUTTON0_IIR_COEFF_VALUE (cy_capsense_context.ptrWdConfig[0u].iirCoeff) +#define CY_CAPSENSE_BUTTON0_IIR_COEFF_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].iirCoeff)) +#define CY_CAPSENSE_BUTTON0_PTR_DEBOUNCE_ARR_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrDebounceArr) +#define CY_CAPSENSE_BUTTON0_PTR_DEBOUNCE_ARR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrDebounceArr)) +#define CY_CAPSENSE_BUTTON0_PTR_DIPLEX_TABLE_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrDiplexTable) +#define CY_CAPSENSE_BUTTON0_PTR_DIPLEX_TABLE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrDiplexTable)) +#define CY_CAPSENSE_BUTTON0_CENTROID_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[0u].centroidConfig) +#define CY_CAPSENSE_BUTTON0_CENTROID_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].centroidConfig)) +#define CY_CAPSENSE_BUTTON0_X_RESOLUTION_VALUE (cy_capsense_context.ptrWdConfig[0u].xResolution) +#define CY_CAPSENSE_BUTTON0_X_RESOLUTION_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].xResolution)) +#define CY_CAPSENSE_BUTTON0_Y_RESOLUTION_VALUE (cy_capsense_context.ptrWdConfig[0u].yResolution) +#define CY_CAPSENSE_BUTTON0_Y_RESOLUTION_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].yResolution)) +#define CY_CAPSENSE_BUTTON0_NUM_SNS_VALUE (cy_capsense_context.ptrWdConfig[0u].numSns) +#define CY_CAPSENSE_BUTTON0_NUM_SNS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].numSns)) +#define CY_CAPSENSE_BUTTON0_NUM_COLS_VALUE (cy_capsense_context.ptrWdConfig[0u].numCols) +#define CY_CAPSENSE_BUTTON0_NUM_COLS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].numCols)) +#define CY_CAPSENSE_BUTTON0_NUM_ROWS_VALUE (cy_capsense_context.ptrWdConfig[0u].numRows) +#define CY_CAPSENSE_BUTTON0_NUM_ROWS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].numRows)) +#define CY_CAPSENSE_BUTTON0_PTR_POS_FILTER_HISTORY_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrPosFilterHistory) +#define CY_CAPSENSE_BUTTON0_PTR_POS_FILTER_HISTORY_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrPosFilterHistory)) +#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_HISTORY_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchHistory) +#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_HISTORY_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchHistory)) +#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_BUFFER_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchBuffer) +#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_BUFFER_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchBuffer)) +#define CY_CAPSENSE_BUTTON0_PTR_CSD_TOUCH_BUFFER_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrCsdTouchBuffer) +#define CY_CAPSENSE_BUTTON0_PTR_CSD_TOUCH_BUFFER_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrCsdTouchBuffer)) +#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrGestureConfig) +#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrGestureConfig)) +#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrGestureContext) +#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrGestureContext)) +#define CY_CAPSENSE_BUTTON0_BALLISTIC_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[0u].ballisticConfig) +#define CY_CAPSENSE_BUTTON0_BALLISTIC_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ballisticConfig)) +#define CY_CAPSENSE_BUTTON0_PTR_BALLISTIC_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[0u].ptrBallisticContext) +#define CY_CAPSENSE_BUTTON0_PTR_BALLISTIC_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrBallisticContext)) +#define CY_CAPSENSE_BUTTON0_AIIR_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[0u].aiirConfig) +#define CY_CAPSENSE_BUTTON0_AIIR_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].aiirConfig)) +#define CY_CAPSENSE_BUTTON0_ADV_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[0u].advConfig) +#define CY_CAPSENSE_BUTTON0_ADV_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].advConfig)) +#define CY_CAPSENSE_BUTTON0_POS_FILTER_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[0u].posFilterConfig) +#define CY_CAPSENSE_BUTTON0_POS_FILTER_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].posFilterConfig)) +#define CY_CAPSENSE_BUTTON0_RAW_FILTER_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[0u].rawFilterConfig) +#define CY_CAPSENSE_BUTTON0_RAW_FILTER_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].rawFilterConfig)) +#define CY_CAPSENSE_BUTTON0_SENSE_METHOD_VALUE (cy_capsense_context.ptrWdConfig[0u].senseMethod) +#define CY_CAPSENSE_BUTTON0_SENSE_METHOD_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].senseMethod)) +#define CY_CAPSENSE_BUTTON0_WD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[0u].wdType) +#define CY_CAPSENSE_BUTTON0_WD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0u].wdType)) + +#define CY_CAPSENSE_BUTTON1_PTR_WD_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrWdContext) +#define CY_CAPSENSE_BUTTON1_PTR_WD_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrWdContext)) +#define CY_CAPSENSE_BUTTON1_PTR_SNS_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrSnsContext) +#define CY_CAPSENSE_BUTTON1_PTR_SNS_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrSnsContext)) +#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrEltdConfig) +#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrEltdConfig)) +#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CAPACITANCE_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrEltdCapacitance) +#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CAPACITANCE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrEltdCapacitance)) +#define CY_CAPSENSE_BUTTON1_PTR_BSLN_INV_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrBslnInv) +#define CY_CAPSENSE_BUTTON1_PTR_BSLN_INV_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrBslnInv)) +#define CY_CAPSENSE_BUTTON1_PTR_NOISE_ENVELOPE_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrNoiseEnvelope) +#define CY_CAPSENSE_BUTTON1_PTR_NOISE_ENVELOPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrNoiseEnvelope)) +#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistory) +#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistory)) +#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_LOW_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistoryLow) +#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_LOW_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistoryLow)) +#define CY_CAPSENSE_BUTTON1_IIR_COEFF_VALUE (cy_capsense_context.ptrWdConfig[1u].iirCoeff) +#define CY_CAPSENSE_BUTTON1_IIR_COEFF_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].iirCoeff)) +#define CY_CAPSENSE_BUTTON1_PTR_DEBOUNCE_ARR_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrDebounceArr) +#define CY_CAPSENSE_BUTTON1_PTR_DEBOUNCE_ARR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrDebounceArr)) +#define CY_CAPSENSE_BUTTON1_PTR_DIPLEX_TABLE_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrDiplexTable) +#define CY_CAPSENSE_BUTTON1_PTR_DIPLEX_TABLE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrDiplexTable)) +#define CY_CAPSENSE_BUTTON1_CENTROID_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[1u].centroidConfig) +#define CY_CAPSENSE_BUTTON1_CENTROID_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].centroidConfig)) +#define CY_CAPSENSE_BUTTON1_X_RESOLUTION_VALUE (cy_capsense_context.ptrWdConfig[1u].xResolution) +#define CY_CAPSENSE_BUTTON1_X_RESOLUTION_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].xResolution)) +#define CY_CAPSENSE_BUTTON1_Y_RESOLUTION_VALUE (cy_capsense_context.ptrWdConfig[1u].yResolution) +#define CY_CAPSENSE_BUTTON1_Y_RESOLUTION_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].yResolution)) +#define CY_CAPSENSE_BUTTON1_NUM_SNS_VALUE (cy_capsense_context.ptrWdConfig[1u].numSns) +#define CY_CAPSENSE_BUTTON1_NUM_SNS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].numSns)) +#define CY_CAPSENSE_BUTTON1_NUM_COLS_VALUE (cy_capsense_context.ptrWdConfig[1u].numCols) +#define CY_CAPSENSE_BUTTON1_NUM_COLS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].numCols)) +#define CY_CAPSENSE_BUTTON1_NUM_ROWS_VALUE (cy_capsense_context.ptrWdConfig[1u].numRows) +#define CY_CAPSENSE_BUTTON1_NUM_ROWS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].numRows)) +#define CY_CAPSENSE_BUTTON1_PTR_POS_FILTER_HISTORY_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrPosFilterHistory) +#define CY_CAPSENSE_BUTTON1_PTR_POS_FILTER_HISTORY_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrPosFilterHistory)) +#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_HISTORY_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchHistory) +#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_HISTORY_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchHistory)) +#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_BUFFER_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchBuffer) +#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_BUFFER_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchBuffer)) +#define CY_CAPSENSE_BUTTON1_PTR_CSD_TOUCH_BUFFER_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrCsdTouchBuffer) +#define CY_CAPSENSE_BUTTON1_PTR_CSD_TOUCH_BUFFER_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrCsdTouchBuffer)) +#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrGestureConfig) +#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrGestureConfig)) +#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrGestureContext) +#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrGestureContext)) +#define CY_CAPSENSE_BUTTON1_BALLISTIC_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[1u].ballisticConfig) +#define CY_CAPSENSE_BUTTON1_BALLISTIC_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ballisticConfig)) +#define CY_CAPSENSE_BUTTON1_PTR_BALLISTIC_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[1u].ptrBallisticContext) +#define CY_CAPSENSE_BUTTON1_PTR_BALLISTIC_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrBallisticContext)) +#define CY_CAPSENSE_BUTTON1_AIIR_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[1u].aiirConfig) +#define CY_CAPSENSE_BUTTON1_AIIR_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].aiirConfig)) +#define CY_CAPSENSE_BUTTON1_ADV_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[1u].advConfig) +#define CY_CAPSENSE_BUTTON1_ADV_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].advConfig)) +#define CY_CAPSENSE_BUTTON1_POS_FILTER_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[1u].posFilterConfig) +#define CY_CAPSENSE_BUTTON1_POS_FILTER_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].posFilterConfig)) +#define CY_CAPSENSE_BUTTON1_RAW_FILTER_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[1u].rawFilterConfig) +#define CY_CAPSENSE_BUTTON1_RAW_FILTER_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].rawFilterConfig)) +#define CY_CAPSENSE_BUTTON1_SENSE_METHOD_VALUE (cy_capsense_context.ptrWdConfig[1u].senseMethod) +#define CY_CAPSENSE_BUTTON1_SENSE_METHOD_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].senseMethod)) +#define CY_CAPSENSE_BUTTON1_WD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[1u].wdType) +#define CY_CAPSENSE_BUTTON1_WD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1u].wdType)) + +#define CY_CAPSENSE_LINEARSLIDER0_PTR_WD_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrWdContext) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_WD_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrWdContext)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_SNS_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrSnsContext) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_SNS_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrSnsContext)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrEltdConfig) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrEltdConfig)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CAPACITANCE_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrEltdCapacitance) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CAPACITANCE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrEltdCapacitance)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_BSLN_INV_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrBslnInv) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_BSLN_INV_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrBslnInv)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_NOISE_ENVELOPE_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrNoiseEnvelope) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_NOISE_ENVELOPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrNoiseEnvelope)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistory) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistory)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_LOW_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistoryLow) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_LOW_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistoryLow)) +#define CY_CAPSENSE_LINEARSLIDER0_IIR_COEFF_VALUE (cy_capsense_context.ptrWdConfig[2u].iirCoeff) +#define CY_CAPSENSE_LINEARSLIDER0_IIR_COEFF_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].iirCoeff)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_DEBOUNCE_ARR_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrDebounceArr) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_DEBOUNCE_ARR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrDebounceArr)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_DIPLEX_TABLE_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrDiplexTable) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_DIPLEX_TABLE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrDiplexTable)) +#define CY_CAPSENSE_LINEARSLIDER0_CENTROID_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[2u].centroidConfig) +#define CY_CAPSENSE_LINEARSLIDER0_CENTROID_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].centroidConfig)) +#define CY_CAPSENSE_LINEARSLIDER0_X_RESOLUTION_VALUE (cy_capsense_context.ptrWdConfig[2u].xResolution) +#define CY_CAPSENSE_LINEARSLIDER0_X_RESOLUTION_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].xResolution)) +#define CY_CAPSENSE_LINEARSLIDER0_Y_RESOLUTION_VALUE (cy_capsense_context.ptrWdConfig[2u].yResolution) +#define CY_CAPSENSE_LINEARSLIDER0_Y_RESOLUTION_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].yResolution)) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_SNS_VALUE (cy_capsense_context.ptrWdConfig[2u].numSns) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_SNS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].numSns)) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_COLS_VALUE (cy_capsense_context.ptrWdConfig[2u].numCols) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_COLS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].numCols)) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_ROWS_VALUE (cy_capsense_context.ptrWdConfig[2u].numRows) +#define CY_CAPSENSE_LINEARSLIDER0_NUM_ROWS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].numRows)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_POS_FILTER_HISTORY_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrPosFilterHistory) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_POS_FILTER_HISTORY_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrPosFilterHistory)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_HISTORY_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchHistory) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_HISTORY_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchHistory)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_BUFFER_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchBuffer) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_BUFFER_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchBuffer)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSD_TOUCH_BUFFER_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrCsdTouchBuffer) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSD_TOUCH_BUFFER_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrCsdTouchBuffer)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrGestureConfig) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrGestureConfig)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrGestureContext) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrGestureContext)) +#define CY_CAPSENSE_LINEARSLIDER0_BALLISTIC_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[2u].ballisticConfig) +#define CY_CAPSENSE_LINEARSLIDER0_BALLISTIC_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ballisticConfig)) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_BALLISTIC_CONTEXT_VALUE (cy_capsense_context.ptrWdConfig[2u].ptrBallisticContext) +#define CY_CAPSENSE_LINEARSLIDER0_PTR_BALLISTIC_CONTEXT_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrBallisticContext)) +#define CY_CAPSENSE_LINEARSLIDER0_AIIR_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[2u].aiirConfig) +#define CY_CAPSENSE_LINEARSLIDER0_AIIR_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].aiirConfig)) +#define CY_CAPSENSE_LINEARSLIDER0_ADV_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[2u].advConfig) +#define CY_CAPSENSE_LINEARSLIDER0_ADV_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].advConfig)) +#define CY_CAPSENSE_LINEARSLIDER0_POS_FILTER_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[2u].posFilterConfig) +#define CY_CAPSENSE_LINEARSLIDER0_POS_FILTER_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].posFilterConfig)) +#define CY_CAPSENSE_LINEARSLIDER0_RAW_FILTER_CONFIG_VALUE (cy_capsense_context.ptrWdConfig[2u].rawFilterConfig) +#define CY_CAPSENSE_LINEARSLIDER0_RAW_FILTER_CONFIG_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].rawFilterConfig)) +#define CY_CAPSENSE_LINEARSLIDER0_SENSE_METHOD_VALUE (cy_capsense_context.ptrWdConfig[2u].senseMethod) +#define CY_CAPSENSE_LINEARSLIDER0_SENSE_METHOD_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].senseMethod)) +#define CY_CAPSENSE_LINEARSLIDER0_WD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[2u].wdType) +#define CY_CAPSENSE_LINEARSLIDER0_WD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2u].wdType)) + +/* cy_capsense_pinConfig */ +#define CY_CAPSENSE_BUTTON0_RX0_PIN0_PC_PTR_VALUE (cy_capsense_context.ptrPinConfig[0].pcPtr) +#define CY_CAPSENSE_BUTTON0_RX0_PIN0_PC_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig[0].pcPtr)) +#define CY_CAPSENSE_BUTTON0_RX0_PIN0_NUMBER_VALUE (cy_capsense_context.ptrPinConfig[0].pinNumber) +#define CY_CAPSENSE_BUTTON0_RX0_PIN0_NUMBER_SIZE (sizeof(cy_capsense_context.ptrPinConfig[0].pinNumber)) + +#define CY_CAPSENSE_BUTTON0_TX_PIN0_PC_PTR_VALUE (cy_capsense_context.ptrPinConfig[1].pcPtr) +#define CY_CAPSENSE_BUTTON0_TX_PIN0_PC_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig[1].pcPtr)) +#define CY_CAPSENSE_BUTTON0_TX_PIN0_NUMBER_VALUE (cy_capsense_context.ptrPinConfig[1].pinNumber) +#define CY_CAPSENSE_BUTTON0_TX_PIN0_NUMBER_SIZE (sizeof(cy_capsense_context.ptrPinConfig[1].pinNumber)) + +#define CY_CAPSENSE_BUTTON1_RX0_PIN0_PC_PTR_VALUE (cy_capsense_context.ptrPinConfig[2].pcPtr) +#define CY_CAPSENSE_BUTTON1_RX0_PIN0_PC_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig[2].pcPtr)) +#define CY_CAPSENSE_BUTTON1_RX0_PIN0_NUMBER_VALUE (cy_capsense_context.ptrPinConfig[2].pinNumber) +#define CY_CAPSENSE_BUTTON1_RX0_PIN0_NUMBER_SIZE (sizeof(cy_capsense_context.ptrPinConfig[2].pinNumber)) + +#define CY_CAPSENSE_BUTTON1_TX_PIN0_PC_PTR_VALUE (cy_capsense_context.ptrPinConfig[3].pcPtr) +#define CY_CAPSENSE_BUTTON1_TX_PIN0_PC_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig[3].pcPtr)) +#define CY_CAPSENSE_BUTTON1_TX_PIN0_NUMBER_VALUE (cy_capsense_context.ptrPinConfig[3].pinNumber) +#define CY_CAPSENSE_BUTTON1_TX_PIN0_NUMBER_SIZE (sizeof(cy_capsense_context.ptrPinConfig[3].pinNumber)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_PC_PTR_VALUE (cy_capsense_context.ptrPinConfig[4].pcPtr) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_PC_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig[4].pcPtr)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_NUMBER_VALUE (cy_capsense_context.ptrPinConfig[4].pinNumber) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_NUMBER_SIZE (sizeof(cy_capsense_context.ptrPinConfig[4].pinNumber)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_PC_PTR_VALUE (cy_capsense_context.ptrPinConfig[5].pcPtr) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_PC_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig[5].pcPtr)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_NUMBER_VALUE (cy_capsense_context.ptrPinConfig[5].pinNumber) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_NUMBER_SIZE (sizeof(cy_capsense_context.ptrPinConfig[5].pinNumber)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_PC_PTR_VALUE (cy_capsense_context.ptrPinConfig[6].pcPtr) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_PC_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig[6].pcPtr)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_NUMBER_VALUE (cy_capsense_context.ptrPinConfig[6].pinNumber) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_NUMBER_SIZE (sizeof(cy_capsense_context.ptrPinConfig[6].pinNumber)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_PC_PTR_VALUE (cy_capsense_context.ptrPinConfig[7].pcPtr) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_PC_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig[7].pcPtr)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_NUMBER_VALUE (cy_capsense_context.ptrPinConfig[7].pinNumber) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_NUMBER_SIZE (sizeof(cy_capsense_context.ptrPinConfig[7].pinNumber)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_PC_PTR_VALUE (cy_capsense_context.ptrPinConfig[8].pcPtr) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_PC_PTR_SIZE (sizeof(cy_capsense_context.ptrPinConfig[8].pcPtr)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_NUMBER_VALUE (cy_capsense_context.ptrPinConfig[8].pinNumber) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_NUMBER_SIZE (sizeof(cy_capsense_context.ptrPinConfig[8].pinNumber)) + +/* cy_capsense_electrodeConfig */ +#define CY_CAPSENSE_BUTTON0_RX0_CFG_PTR_VALUE (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].ptrPin) +#define CY_CAPSENSE_BUTTON0_RX0_CFG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].ptrPin)) +#define CY_CAPSENSE_BUTTON0_RX0_ELTD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].type) +#define CY_CAPSENSE_BUTTON0_RX0_ELTD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].type)) +#define CY_CAPSENSE_BUTTON0_RX0_NUM_PINS_VALUE (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].numPins) +#define CY_CAPSENSE_BUTTON0_RX0_NUM_PINS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].numPins)) + +#define CY_CAPSENSE_BUTTON0_TX_CFG_PTR_VALUE (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].ptrPin) +#define CY_CAPSENSE_BUTTON0_TX_CFG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].ptrPin)) +#define CY_CAPSENSE_BUTTON0_TX_ELTD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].type) +#define CY_CAPSENSE_BUTTON0_TX_ELTD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].type)) +#define CY_CAPSENSE_BUTTON0_TX_NUM_PINS_VALUE (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].numPins) +#define CY_CAPSENSE_BUTTON0_TX_NUM_PINS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].numPins)) + +#define CY_CAPSENSE_BUTTON1_RX0_CFG_PTR_VALUE (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].ptrPin) +#define CY_CAPSENSE_BUTTON1_RX0_CFG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].ptrPin)) +#define CY_CAPSENSE_BUTTON1_RX0_ELTD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].type) +#define CY_CAPSENSE_BUTTON1_RX0_ELTD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].type)) +#define CY_CAPSENSE_BUTTON1_RX0_NUM_PINS_VALUE (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].numPins) +#define CY_CAPSENSE_BUTTON1_RX0_NUM_PINS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].numPins)) + +#define CY_CAPSENSE_BUTTON1_TX_CFG_PTR_VALUE (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].ptrPin) +#define CY_CAPSENSE_BUTTON1_TX_CFG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].ptrPin)) +#define CY_CAPSENSE_BUTTON1_TX_ELTD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].type) +#define CY_CAPSENSE_BUTTON1_TX_ELTD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].type)) +#define CY_CAPSENSE_BUTTON1_TX_NUM_PINS_VALUE (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].numPins) +#define CY_CAPSENSE_BUTTON1_TX_NUM_PINS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].numPins)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_CFG_PTR_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].ptrPin) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_CFG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].ptrPin)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_ELTD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].type) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_ELTD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].type)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NUM_PINS_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].numPins) +#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NUM_PINS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].numPins)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_CFG_PTR_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].ptrPin) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_CFG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].ptrPin)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_ELTD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].type) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_ELTD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].type)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NUM_PINS_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].numPins) +#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NUM_PINS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].numPins)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_CFG_PTR_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].ptrPin) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_CFG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].ptrPin)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_ELTD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].type) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_ELTD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].type)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NUM_PINS_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].numPins) +#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NUM_PINS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].numPins)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_CFG_PTR_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].ptrPin) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_CFG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].ptrPin)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_ELTD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].type) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_ELTD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].type)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NUM_PINS_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].numPins) +#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NUM_PINS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].numPins)) + +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_CFG_PTR_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].ptrPin) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_CFG_PTR_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].ptrPin)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_ELTD_TYPE_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].type) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_ELTD_TYPE_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].type)) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NUM_PINS_VALUE (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].numPins) +#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NUM_PINS_SIZE (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].numPins)) + + +#if ((CY_CAPSENSE_PERI_CLK / 2) > 50000000) + #warning The maximum CSD modulator clock frequency is 50 MHz: increase CSD modulator clock divider to meet the valid operation conditions +#endif + +#if ((CY_CAPSENSE_PERI_CLK / 2) > 50000000) + #warning The maximum CSX modulator clock frequency is 50 MHz: increase CSX modulator clock divider to meet the valid operation conditions +#endif + +#if ((CY_CAPSENSE_PERI_CLK / 2 / 32) > 3000000) + #warning The maximum Tx clock frequency is 3 MHz: increase Tx clock divider for widget Button0 to meet the valid operation conditions +#endif + +#if ((CY_CAPSENSE_PERI_CLK / 2 / 32) > 3000000) + #warning The maximum Tx clock frequency is 3 MHz: increase Tx clock divider for widget Button1 to meet the valid operation conditions +#endif + + + +#if (CY_CAPSENSE_BIST_SUPPORTED) +#if (CY_CAPSENSE_BIST_EN != 0) + extern uint32_t cy_capsense_eltdCap[]; + #if (CY_CAPSENSE_MW_VERSION >= 300) + extern uint32_t cy_capsense_snsCap[]; + #endif + extern uint16_t cy_capsense_bslnInv[]; +#endif +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_CAPSENSE_CORE == __CORTEX_M */ + +#endif /* !defined(CY_DISABLE_CAPSENSE) */ + +#endif /* CYCFG_CAPSENSE_H */ + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h new file mode 100644 index 0000000000..4a438d80db --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h @@ -0,0 +1,140 @@ +/******************************************************************************* +* File Name: cycfg_capsense_defines.h +* +* Description: +* CAPSENSE configuration defines. +* +* Note: This file is required for the CAPSENSE Middleware Library to build +* successfully. +* +* This file should not be modified. It was automatically generated by +* CapSense Configurator 4.0.0.6195 +* +******************************************************************************** +* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company) +* or an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#if !defined(CYCFG_CAPSENSE_DEFINES_H) +#define CYCFG_CAPSENSE_DEFINES_H + +#include + +/* General */ +#define CY_CAPSENSE_WIDGET_COUNT (3u) +#define CY_CAPSENSE_SENSOR_COUNT (7u) +#define CY_CAPSENSE_ELTD_COUNT (9u) +#define CY_CAPSENSE_PIN_COUNT (9u) +#define CY_CAPSENSE_SHIELD_PIN_COUNT (0u) +#define CY_CAPSENSE_POSITION_SIZE (1u) +#define CY_CAPSENSE_DEBOUNCE_SIZE (3u) +#define CY_CAPSENSE_NOISE_ENVELOPE_SIZE (5u) +#define CY_CAPSENSE_MFS_CH_NUMBER (1u) +#define CY_CAPSENSE_RAW_HISTORY_SIZE (0u) +#define CY_CAPSENSE_IIR_HISTORY_LOW_SIZE (0u) +#define CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE (0u) +#define CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE (0u) +#define CY_CAPSENSE_DIPLEX_SIZE (0u) +#define CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE (0u) +#define CY_CAPSENSE_CSX_TOUCH_BUFFER_ENABLE (0u) +#define CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE (0u) +#define CY_CAPSENSE_BALLISTIC_WIDGET_COUNT (0u) +#define CY_CAPSENSE_GESTURE_WIDGET_COUNT (0u) + +/* Sensing Methods */ +#define CY_CAPSENSE_CSD_EN (1u) +#define CY_CAPSENSE_CSX_EN (1u) +#define CY_CAPSENSE_CSD_CALIBRATION_EN (1u) +#define CY_CAPSENSE_CSX_CALIBRATION_EN (1u) +#define CY_CAPSENSE_SMARTSENSE_FULL_EN (1u) +#define CY_CAPSENSE_SMARTSENSE_HW_EN (0u) +#define CY_CAPSENSE_SMARTSENSE_DISABLED (0u) +#define CY_CAPSENSE_CSD_AUTOTUNE_EN (CY_CAPSENSE_SMARTSENSE_FULL_EN || CY_CAPSENSE_SMARTSENSE_HW_EN) +#define CY_CAPSENSE_CSD_SHIELD_EN (0u) +#define CY_CAPSENSE_CSD_SHIELD_CAP_EN (0u) +#define CY_CAPSENSE_CSD_CHARGE_TRANSFER (CY_CAPSENSE_IDAC_SOURCING) +#define CY_CAPSENSE_CSD_IDAC_COMP_EN (1u) +#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN (1u) +#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN (1u) +#define CY_CAPSENSE_LFSR_EN (1u) +#define CY_CAPSENSE_LFSR_AUTO_EN (1u) +#define CY_CAPSENSE_CLOCK_SOURCE_AUTO_EN (1u) + +/* Filtering */ +#define CY_CAPSENSE_ADAPTIVE_FILTER_EN (0u) +#define CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN (0u) +#define CY_CAPSENSE_RAWCOUNT_FILTER_EN (0u) +#define CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN (0u) +#define CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN (0u) +#define CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN (0u) +#define CY_CAPSENSE_REGULAR_RC_FILTER_EN (CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN || CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN) +#define CY_CAPSENSE_PROX_RC_IIR_FILTER_EN (0u) +#define CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN (0u) +#define CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN (0u) +#define CY_CAPSENSE_PROX_RC_FILTER_EN (CY_CAPSENSE_PROX_RC_IIR_FILTER_EN || CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN) +#define CY_CAPSENSE_POSITION_FILTER_EN (0u) +#define CY_CAPSENSE_CSD_POSITION_FILTER_EN (0u) +#define CY_CAPSENSE_CSX_POSITION_FILTER_EN (0u) +#define CY_CAPSENSE_POS_IIR_FILTER_EN (0u) +#define CY_CAPSENSE_POS_MEDIAN_FILTER_EN (0u) +#define CY_CAPSENSE_POS_AVERAGE_FILTER_EN (0u) +#define CY_CAPSENSE_POS_JITTER_FILTER_EN (0u) + +/* Widgets */ +#define CY_CAPSENSE_CSD_BUTTON_EN (0u) +#define CY_CAPSENSE_CSD_MATRIX_EN (0u) +#define CY_CAPSENSE_CSD_SLIDER_EN (1u) +#define CY_CAPSENSE_CSD_TOUCHPAD_EN (0u) +#define CY_CAPSENSE_CSD_PROXIMITY_EN (0u) +#define CY_CAPSENSE_CSX_BUTTON_EN (1u) +#define CY_CAPSENSE_CSX_SLIDER_EN (0u) +#define CY_CAPSENSE_CSX_MATRIX_EN (0u) +#define CY_CAPSENSE_CSX_TOUCHPAD_EN (0u) +#define CY_CAPSENSE_ADVANCED_CENTROID_5X5_EN (0u) +#define CY_CAPSENSE_CSD_LINEAR_SLIDER_EN (1u) +#define CY_CAPSENSE_CSD_RADIAL_SLIDER_EN (0u) +#define CY_CAPSENSE_CSD_DIPLEX_SLIDER_EN (0u) +#define CY_CAPSENSE_CSX_LINEAR_SLIDER_EN (0u) +#define CY_CAPSENSE_CSX_DIPLEX_SLIDER_EN (0u) +#define CY_CAPSENSE_GANGED_SNS_EN (0u) +#define CY_CAPSENSE_CSD_GANGED_SNS_EN (0u) +#define CY_CAPSENSE_CSX_GANGED_SNS_EN (0u) +#define CY_CAPSENSE_BUTTON_EN (1u) +#define CY_CAPSENSE_MATRIX_EN (0u) +#define CY_CAPSENSE_SLIDER_EN (1u) +#define CY_CAPSENSE_TOUCHPAD_EN (0u) + +/* Features */ +#define CY_CAPSENSE_GESTURE_EN (0u) +#define CY_CAPSENSE_MULTI_FREQUENCY_SCAN_EN (0u) +#define CY_CAPSENSE_MULTI_FREQUENCY_WIDGET_EN (0u) +#define CY_CAPSENSE_SNS_AUTO_RESET_EN (0u) + +/* Self-test */ +#define CY_CAPSENSE_BIST_EN (0u) +#define CY_CAPSENSE_TST_WDGT_CRC_EN (0u) +#define CY_CAPSENSE_TST_BSLN_INTEGRITY_EN (0u) +#define CY_CAPSENSE_TST_RAW_INTEGRITY_EN (0u) +#define CY_CAPSENSE_TST_SNS_SHORT_EN (0u) +#define CY_CAPSENSE_TST_SNS_CAP_EN (0u) +#define CY_CAPSENSE_TST_SH_CAP_EN (0u) +#define CY_CAPSENSE_TST_EXTERNAL_CAP_EN (0u) +#define CY_CAPSENSE_TST_VDDA_EN (0u) + + +#endif /* CYCFG_CAPSENSE_DEFINES_H */ + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h new file mode 100644 index 0000000000..9ed3e5855f --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h @@ -0,0 +1,973 @@ +/******************************************************************************* +* File Name: cycfg_capsense_tuner_regmap.h +* +* Description: +* CAPSENSE Tuner register map configuration. +* This file should not be modified. It was automatically generated by +* CapSense Configurator 4.0.0.6195 +* +******************************************************************************** +* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company) +* or an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#if !defined(CYCFG_CAPSENSE_TUNER_REGMAP_H) +#define CYCFG_CAPSENSE_TUNER_REGMAP_H + +#include "cy_capsense_common.h" + +#if !defined(CY_CAPSENSE_MW_VERSION) + #define CY_CAPSENSE_TUNER_MW_VERSION (200) +#else + #define CY_CAPSENSE_TUNER_MW_VERSION (CY_CAPSENSE_MW_VERSION) +#endif + +/* RAM Data structure register definitions */ +#if (CY_CAPSENSE_TUNER_MW_VERSION < 300) +#define CY_CAPSENSE_TUNER_CONFIG_ID_OFFSET (0u) +#define CY_CAPSENSE_TUNER_CONFIG_ID_SIZE (2u) + +#define CY_CAPSENSE_TUNER_TUNER_CMD_OFFSET (2u) +#define CY_CAPSENSE_TUNER_TUNER_CMD_SIZE (2u) + +#define CY_CAPSENSE_TUNER_SCAN_COUNTER_OFFSET (4u) +#define CY_CAPSENSE_TUNER_SCAN_COUNTER_SIZE (2u) + +#define CY_CAPSENSE_TUNER_TUNER_ST_OFFSET (6u) +#define CY_CAPSENSE_TUNER_TUNER_ST_SIZE (1u) + +#define CY_CAPSENSE_TUNER_INITDONE_OFFSET (7u) +#define CY_CAPSENSE_TUNER_INITDONE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_PTRSSCALLBACK_OFFSET (8u) +#define CY_CAPSENSE_TUNER_PTRSSCALLBACK_SIZE (4u) + +#define CY_CAPSENSE_TUNER_PTREOSCALLBACK_OFFSET (12u) +#define CY_CAPSENSE_TUNER_PTREOSCALLBACK_SIZE (4u) + +#define CY_CAPSENSE_TUNER_PTRTUNERSENDCALLBACK_OFFSET (16u) +#define CY_CAPSENSE_TUNER_PTRTUNERSENDCALLBACK_SIZE (4u) + +#define CY_CAPSENSE_TUNER_PTRTUNERRECEIVECALLBACK_OFFSET (20u) +#define CY_CAPSENSE_TUNER_PTRTUNERRECEIVECALLBACK_SIZE (4u) + +#define CY_CAPSENSE_TUNER_STATUS_OFFSET (24u) +#define CY_CAPSENSE_TUNER_STATUS_SIZE (4u) + +#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_OFFSET (28u) +#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_SIZE (4u) + +#define CY_CAPSENSE_TUNER_TIMESTAMP_OFFSET (32u) +#define CY_CAPSENSE_TUNER_TIMESTAMP_SIZE (4u) + +#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_OFFSET (36u) +#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_SIZE (1u) + +#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_OFFSET (37u) +#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_SIZE (1u) + +#define CY_CAPSENSE_TUNER_TUNER_CNT_OFFSET (38u) +#define CY_CAPSENSE_TUNER_TUNER_CNT_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_OFFSET (40u) +#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_OFFSET (42u) +#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_NUM_CONV_OFFSET (44u) +#define CY_CAPSENSE_TUNER_BUTTON0_NUM_CONV_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_OFFSET (46u) +#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_OFFSET (48u) +#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_OFFSET (50u) +#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_OFFSET (52u) +#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_OFFSET (54u) +#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_OFFSET (56u) +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_OFFSET (58u) +#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_OFFSET (60u) +#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_OFFSET (62u) +#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_OFFSET (64u) +#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_OFFSET (66u) +#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_OFFSET (67u) +#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_OFFSET (68u) +#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_OFFSET (69u) +#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SOURCE_OFFSET (70u) +#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SOURCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_OFFSET (71u) +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_OFFSET (72u) +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_OFFSET (73u) +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_OFFSET (74u) +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_OFFSET (75u) +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_OFFSET (76u) +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_OFFSET (77u) +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_OFFSET (78u) +#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_OFFSET (79u) +#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_OFFSET (80u) +#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_SIZE (4u) + +#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_OFFSET (84u) +#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_OFFSET (88u) +#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_OFFSET (90u) +#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_NUM_CONV_OFFSET (92u) +#define CY_CAPSENSE_TUNER_BUTTON1_NUM_CONV_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_OFFSET (94u) +#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_OFFSET (96u) +#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_OFFSET (98u) +#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_OFFSET (100u) +#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_OFFSET (102u) +#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_OFFSET (104u) +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_OFFSET (106u) +#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_OFFSET (108u) +#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_OFFSET (110u) +#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_OFFSET (112u) +#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_OFFSET (114u) +#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_OFFSET (115u) +#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_OFFSET (116u) +#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_OFFSET (117u) +#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SOURCE_OFFSET (118u) +#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SOURCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_OFFSET (119u) +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_OFFSET (120u) +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_OFFSET (121u) +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_OFFSET (122u) +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_OFFSET (123u) +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_OFFSET (124u) +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_OFFSET (125u) +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_OFFSET (126u) +#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_OFFSET (127u) +#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_OFFSET (128u) +#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_SIZE (4u) + +#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_OFFSET (132u) +#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET (136u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET (138u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET (140u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_OFFSET (142u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET (144u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET (146u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET (148u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET (150u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET (152u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET (154u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET (156u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET (158u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET (160u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET (162u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET (163u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET (164u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET (165u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET (166u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET (167u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET (168u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET (169u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET (170u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET (171u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET (172u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET (173u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET (174u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET (175u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET (176u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_SIZE (4u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET (180u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_RAW0_OFFSET (184u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN0_OFFSET (186u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_DIFF0_OFFSET (188u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_STATUS0_OFFSET (190u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_NEG_BSLN_RST_CNT0_OFFSET (191u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_IDAC0_OFFSET (192u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN_EXT0_OFFSET (193u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_RAW0_OFFSET (194u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN0_OFFSET (196u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_DIFF0_OFFSET (198u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_STATUS0_OFFSET (200u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_NEG_BSLN_RST_CNT0_OFFSET (201u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_IDAC0_OFFSET (202u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN_EXT0_OFFSET (203u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET (204u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET (206u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET (208u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET (210u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET (211u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET (212u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET (213u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET (214u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET (216u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET (218u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET (220u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET (221u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET (222u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET (223u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET (224u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET (226u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET (228u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET (230u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET (231u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET (232u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET (233u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET (234u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET (236u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET (238u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET (240u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET (241u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET (242u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET (243u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET (244u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET (246u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET (248u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET (250u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET (251u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET (252u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET (253u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET (254u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET (256u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET (258u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET (260u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_SIZE (2u) + +#else /* CY_CAPSENSE_TUNER_MW_VERSION >= 300 */ +#define CY_CAPSENSE_TUNER_CONFIG_ID_OFFSET (0u) +#define CY_CAPSENSE_TUNER_CONFIG_ID_SIZE (2u) + +#define CY_CAPSENSE_TUNER_TUNER_CMD_OFFSET (2u) +#define CY_CAPSENSE_TUNER_TUNER_CMD_SIZE (2u) + +#define CY_CAPSENSE_TUNER_SCAN_COUNTER_OFFSET (4u) +#define CY_CAPSENSE_TUNER_SCAN_COUNTER_SIZE (2u) + +#define CY_CAPSENSE_TUNER_TUNER_ST_OFFSET (6u) +#define CY_CAPSENSE_TUNER_TUNER_ST_SIZE (1u) + +#define CY_CAPSENSE_TUNER_INITDONE_OFFSET (7u) +#define CY_CAPSENSE_TUNER_INITDONE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_STATUS_OFFSET (8u) +#define CY_CAPSENSE_TUNER_STATUS_SIZE (4u) + +#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_OFFSET (12u) +#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_SIZE (4u) + +#define CY_CAPSENSE_TUNER_TIMESTAMP_OFFSET (16u) +#define CY_CAPSENSE_TUNER_TIMESTAMP_SIZE (4u) + +#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_OFFSET (20u) +#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_SIZE (1u) + +#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_OFFSET (21u) +#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_SIZE (1u) + +#define CY_CAPSENSE_TUNER_TUNER_CNT_OFFSET (22u) +#define CY_CAPSENSE_TUNER_TUNER_CNT_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_OFFSET (24u) +#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_OFFSET (26u) +#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_NUM_CONV_OFFSET (28u) +#define CY_CAPSENSE_TUNER_BUTTON0_NUM_CONV_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_OFFSET (30u) +#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNTROW_OFFSET (32u) +#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNTROW_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_OFFSET (34u) +#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_OFFSET (36u) +#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_OFFSET (38u) +#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_OFFSET (40u) +#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_OFFSET (42u) +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_OFFSET (44u) +#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_OFFSET (46u) +#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_OFFSET (48u) +#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_OFFSET (50u) +#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_OFFSET (52u) +#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_OFFSET (54u) +#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_OFFSET (56u) +#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_OFFSET (58u) +#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SOURCE_OFFSET (59u) +#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SOURCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_OFFSET (60u) +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_OFFSET (61u) +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_OFFSET (62u) +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_OFFSET (63u) +#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_OFFSET (64u) +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_OFFSET (65u) +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_OFFSET (66u) +#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_OFFSET (67u) +#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_OFFSET (68u) +#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_OFFSET (72u) +#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_SIZE (4u) + +#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_OFFSET (76u) +#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_OFFSET (80u) +#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_OFFSET (82u) +#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_NUM_CONV_OFFSET (84u) +#define CY_CAPSENSE_TUNER_BUTTON1_NUM_CONV_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_OFFSET (86u) +#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNTROW_OFFSET (88u) +#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNTROW_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_OFFSET (90u) +#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_OFFSET (92u) +#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_OFFSET (94u) +#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_OFFSET (96u) +#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_OFFSET (98u) +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_OFFSET (100u) +#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_OFFSET (102u) +#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_OFFSET (104u) +#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_OFFSET (106u) +#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_OFFSET (108u) +#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_OFFSET (110u) +#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_OFFSET (112u) +#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_OFFSET (114u) +#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SOURCE_OFFSET (115u) +#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SOURCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_OFFSET (116u) +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_OFFSET (117u) +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_OFFSET (118u) +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_OFFSET (119u) +#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_OFFSET (120u) +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_OFFSET (121u) +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_OFFSET (122u) +#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_OFFSET (123u) +#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_OFFSET (124u) +#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_OFFSET (128u) +#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_SIZE (4u) + +#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_OFFSET (132u) +#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET (136u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET (138u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET (140u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_OFFSET (142u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNTROW_OFFSET (144u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNTROW_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET (146u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET (148u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET (150u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET (152u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET (154u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET (156u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET (158u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET (160u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET (162u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET (164u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET (166u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET (168u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET (170u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET (171u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET (172u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET (173u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET (174u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET (175u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET (176u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET (177u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET (178u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET (179u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET (180u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET (184u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_SIZE (4u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET (188u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_RAW0_OFFSET (192u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN0_OFFSET (194u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_DIFF0_OFFSET (196u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_STATUS0_OFFSET (198u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_NEG_BSLN_RST_CNT0_OFFSET (199u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_IDAC0_OFFSET (200u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN_EXT0_OFFSET (201u) +#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_RAW0_OFFSET (202u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN0_OFFSET (204u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_DIFF0_OFFSET (206u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_STATUS0_OFFSET (208u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_NEG_BSLN_RST_CNT0_OFFSET (209u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_IDAC0_OFFSET (210u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN_EXT0_OFFSET (211u) +#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET (212u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET (214u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET (216u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET (218u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET (219u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET (220u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET (221u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET (222u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET (224u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET (226u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET (228u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET (229u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET (230u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET (231u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET (232u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET (234u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET (236u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET (238u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET (239u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET (240u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET (241u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET (242u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET (244u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET (246u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET (248u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET (249u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET (250u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET (251u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET (252u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET (254u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET (256u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET (258u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET (259u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET (260u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET (261u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE (1u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET (262u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET (264u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET (266u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_SIZE (2u) + +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET (268u) +#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_SIZE (2u) + +#endif + + +#endif /* CYCFG_CAPSENSE_TUNER_REGMAP_H */ + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c new file mode 100644 index 0000000000..365ae6e7b4 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,60 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ +#include + +#include "cycfg_clocks.h" + +#if defined (CY_USING_HAL) +const cyhal_resource_inst_t CLK_PWM_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = CLK_PWM_HW, + .channel_num = CLK_PWM_NUM, +}; +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) +const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_CSD_CLK_DIV_HW, + .channel_num = CYBSP_CSD_CLK_DIV_NUM, +}; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h new file mode 100644 index 0000000000..53b6c0d3c5 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,66 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CLK_PWM_ENABLED 1U +#define CLK_PWM_HW CY_SYSCLK_DIV_16_BIT +#define CLK_PWM_NUM 0U + +#define CYBSP_CSD_CLK_DIV_ENABLED 1U +#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED +#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_CS_CLK_DIV_HW CYBSP_CSD_CLK_DIV_HW +#define CYBSP_CSD_CLK_DIV_NUM 0U +#define CYBSP_CS_CLK_DIV_NUM CYBSP_CSD_CLK_DIV_NUM + +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; + #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj +#endif //defined (CY_USING_HAL) + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c new file mode 100644 index 0000000000..e066817ddd --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c @@ -0,0 +1,31 @@ +/******************************************************************************* +* File Name: cycfg_connectivity_bt.c +* +* Description: +* Connectivity BT configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_connectivity_bt.h" + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h new file mode 100644 index 0000000000..0665704cf2 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h @@ -0,0 +1,55 @@ +/******************************************************************************* +* File Name: cycfg_connectivity_bt.h +* +* Description: +* Connectivity BT configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_BT_H) +#define CYCFG_CONNECTIVITY_BT_H + +#include "cycfg_notices.h" +#include "cycfg_pins.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define bt_0_power_0_ENABLED 1U +#define CYCFG_BT_LP_ENABLED (1u) +#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0) +#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1) +#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE +#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW +#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE +#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CONNECTIVITY_BT_H */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c new file mode 100644 index 0000000000..b40c169795 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c @@ -0,0 +1,181 @@ +/******************************************************************************* +* File Name: cycfg_dmas.c +* +* Description: +* DMA configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.14850 +* personalities 6.0.0.0 +* udd 3.0.0.2024 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_dmas.h" + +const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_4CYC, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_ENABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD, + .descriptorType = CY_DMA_SINGLE_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 1, + .dstXincrement = 0, + .xCount = 1, + .srcYincrement = 1, + .dstYincrement = 1, + .yCount = 1, + .nextDescriptor = NULL, +}; +cy_stc_dma_descriptor_t TxDma_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t TxDma_channelConfig = +{ + .descriptor = &TxDma_Descriptor_0, + .preemptable = false, + .priority = 3, + .enable = false, + .bufferable = false, +}; +const cy_stc_dma_crc_config_t TxDma_crcConfig = +{ + .dataReverse = false, + .dataXor = 0, + .reminderReverse = false, + .reminderXor = 0, + .polynomial = 79764919, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t TxDma_obj = + { + .type = CYHAL_RSC_DMA, + .block_num = 0U, + .channel_num = TxDma_CHANNEL, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_4CYC, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_ENABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_SINGLE_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0, + .dstXincrement = 1, + .xCount = 1, + .srcYincrement = 1, + .dstYincrement = 1, + .yCount = 1, + .nextDescriptor = &RxDma_Descriptor_1, +}; +const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config = +{ + .retrigger = CY_DMA_RETRIG_4CYC, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_ENABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_SINGLE_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0, + .dstXincrement = 1, + .xCount = 1, + .srcYincrement = 1, + .dstYincrement = 1, + .yCount = 1, + .nextDescriptor = &RxDma_Descriptor_0, +}; +cy_stc_dma_descriptor_t RxDma_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +cy_stc_dma_descriptor_t RxDma_Descriptor_1 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t RxDma_channelConfig = +{ + .descriptor = &RxDma_Descriptor_0, + .preemptable = false, + .priority = 3, + .enable = false, + .bufferable = false, +}; +const cy_stc_dma_crc_config_t RxDma_crcConfig = +{ + .dataReverse = false, + .dataXor = 0, + .reminderReverse = false, + .reminderXor = 0, + .polynomial = 79764919, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t RxDma_obj = + { + .type = CYHAL_RSC_DMA, + .block_num = 0U, + .channel_num = RxDma_CHANNEL, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_dmas(void) +{ +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&TxDma_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&RxDma_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h new file mode 100644 index 0000000000..eb65d3b411 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h @@ -0,0 +1,76 @@ +/******************************************************************************* +* File Name: cycfg_dmas.h +* +* Description: +* DMA configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.14850 +* personalities 6.0.0.0 +* udd 3.0.0.2024 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_DMAS_H) +#define CYCFG_DMAS_H + +#include "cycfg_notices.h" +#include "cy_dma.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) + +#if defined(__cplusplus) +extern "C" { +#endif + +#define TxDma_ENABLED 1U +#define TxDma_HW DW0 +#define TxDma_CHANNEL 26U +#define TxDma_IRQ cpuss_interrupts_dw0_26_IRQn +#define RxDma_ENABLED 1U +#define RxDma_HW DW0 +#define RxDma_CHANNEL 27U +#define RxDma_IRQ cpuss_interrupts_dw0_27_IRQn + +extern const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config; +extern cy_stc_dma_descriptor_t TxDma_Descriptor_0; +extern const cy_stc_dma_channel_config_t TxDma_channelConfig; +extern const cy_stc_dma_crc_config_t TxDma_crcConfig; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t TxDma_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config; +extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config; +extern cy_stc_dma_descriptor_t RxDma_Descriptor_0; +extern cy_stc_dma_descriptor_t RxDma_Descriptor_1; +extern const cy_stc_dma_channel_config_t RxDma_channelConfig; +extern const cy_stc_dma_crc_config_t RxDma_crcConfig; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t RxDma_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_dmas(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_DMAS_H */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h new file mode 100644 index 0000000000..f9a67a4b0f --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + +#ifdef CY_SUPPORTS_DEVICE_VALIDATION +#ifndef CY8C624ABZI_S2D44 + #error "Unexpected target MCU; expected CY8C624ABZI-S2D44. There may be an inconsistency between the *.modus file and the makefile target configuration device sets." +#endif +#endif + + +#endif /* CYCFG_NOTICES_H */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 0000000000..1f24e6c1b2 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,66 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ +#include + +#include "cycfg_peripherals.h" + +cy_stc_csd_context_t cy_csd_0_context = +{ + .lockKey = CY_CSD_NONE_KEY, +}; + +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); + +#ifdef BSP_USING_UART0 + /* UART0 Device Clock*/ + Cy_SysClk_PeriphAssignDivider(PCLK_SCB0_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); +#endif +#ifdef BSP_USING_UART1 + /* UART1 Device Clock*/ + Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); +#endif +#ifdef BSP_USING_UART2 + /* UART2 Device Clock*/ + Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); +#endif +#if defined(BSP_USING_UART3) || defined(BSP_USING_HW_I2C3) + /* UART3 Device Clock*/ + Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); +#endif +#ifdef BSP_USING_UART4 + /* UART4 Device Clock*/ + Cy_SysClk_PeriphAssignDivider(PCLK_SCB4_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); +#endif +#ifdef BSP_USING_UART5 + /* UART5 Device Clock*/ + Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); +#endif +} diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 0000000000..e0221c3c63 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,87 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_csd.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_CSD_ENABLED 1U +#define CY_CAPSENSE_CORE 4u +#define CY_CAPSENSE_CPU_CLK 100000000u +#define CY_CAPSENSE_PERI_CLK 100000000u +#define CY_CAPSENSE_VDDA_MV 3300u +#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define CY_CAPSENSE_PERI_DIV_INDEX 0u +#define Cmod_PORT GPIO_PRT7 +#define CintA_PORT GPIO_PRT7 +#define CintB_PORT GPIO_PRT7 +#define Button0_Rx0_PORT GPIO_PRT1 +#define Button0_Tx_PORT GPIO_PRT8 +#define Button1_Rx0_PORT GPIO_PRT1 +#define Button1_Tx_PORT GPIO_PRT8 +#define LinearSlider0_Sns0_PORT GPIO_PRT8 +#define LinearSlider0_Sns1_PORT GPIO_PRT8 +#define LinearSlider0_Sns2_PORT GPIO_PRT8 +#define LinearSlider0_Sns3_PORT GPIO_PRT8 +#define LinearSlider0_Sns4_PORT GPIO_PRT8 +#define Cmod_PIN 7u +#define CintA_PIN 1u +#define CintB_PIN 2u +#define Button0_Rx0_PIN 0u +#define Button0_Tx_PIN 1u +#define Button1_Rx0_PIN 0u +#define Button1_Tx_PIN 2u +#define LinearSlider0_Sns0_PIN 3u +#define LinearSlider0_Sns1_PIN 4u +#define LinearSlider0_Sns2_PIN 5u +#define LinearSlider0_Sns3_PIN 6u +#define LinearSlider0_Sns4_PIN 7u +#define Cmod_PORT_NUM 7u +#define CintA_PORT_NUM 7u +#define CintB_PORT_NUM 7u +#define CYBSP_CSD_HW CSD0 +#define CYBSP_CSD_IRQ csd_interrupt_IRQn + +extern cy_stc_csd_context_t cy_csd_0_context; + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c new file mode 100644 index 0000000000..eddda04023 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -0,0 +1,581 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +#define CYBSP_SDHC_IO1_PORT GPIO_PRT13 +#define CYBSP_SDHC_IO1_PORT_NUM 13U +#define CYBSP_SDHC_IO1_PIN 1U + +#ifndef ioss_0_port_13_pin_1_HSIOM + #define ioss_0_port_13_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SDHC_IO1_HSIOM ioss_0_port_13_pin_1_HSIOM + +#define CYBSP_SDHC_IO2_PORT GPIO_PRT13 +#define CYBSP_SDHC_IO2_PORT_NUM 13U +#define CYBSP_SDHC_IO2_PIN 2U + +#ifndef ioss_0_port_13_pin_2_HSIOM + #define ioss_0_port_13_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SDHC_IO2_HSIOM ioss_0_port_13_pin_2_HSIOM + +const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_SDHC_IO1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SDHC_IO1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SDHC_IO1_PORT_NUM, + .channel_num = CYBSP_SDHC_IO1_PIN, + }; +#endif //defined (CY_USING_HAL) + +const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_SDHC_IO2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SDHC_IO2_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SDHC_IO2_PORT_NUM, + .channel_num = CYBSP_SDHC_IO2_PIN, + }; +#endif //defined (CY_USING_HAL) + +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_WCO_IN_PORT_NUM, + .channel_num = CYBSP_WCO_IN_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_WCO_OUT_PORT_NUM, + .channel_num = CYBSP_WCO_OUT_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_RX_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_RX_PORT_NUM, + .channel_num = CYBSP_CSD_RX_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWO_PORT_NUM, + .channel_num = CYBSP_SWO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDIO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDIO_PORT_NUM, + .channel_num = CYBSP_SWDIO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = CYBSP_SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDCK_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDCK_PORT_NUM, + .channel_num = CYBSP_SWDCK_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CINA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CINA_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CINA_PORT_NUM, + .channel_num = CYBSP_CINA_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CINB_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CINB_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CINB_PORT_NUM, + .channel_num = CYBSP_CINB_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CMOD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CMOD_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CMOD_PORT_NUM, + .channel_num = CYBSP_CMOD_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_BTN0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_BTN0_PORT_NUM, + .channel_num = CYBSP_CSD_BTN0_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_BTN1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_BTN1_PORT_NUM, + .channel_num = CYBSP_CSD_BTN1_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD0_PORT_NUM, + .channel_num = CYBSP_CSD_SLD0_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD1_PORT_NUM, + .channel_num = CYBSP_CSD_SLD1_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD2_PORT_NUM, + .channel_num = CYBSP_CSD_SLD2_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD3_PORT_NUM, + .channel_num = CYBSP_CSD_SLD3_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD4_PORT_NUM, + .channel_num = CYBSP_CSD_SLD4_PIN, + }; +#endif //defined (CY_USING_HAL) + +const cy_stc_gpio_pin_config_t SMART_IO_OUTPUT_PIN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = P9_1_TCPWM1_LINE_COMPL20, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t SMART_IO_OUTPUT_PIN_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = 9U, + .channel_num = 1U, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CINA_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CINB_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h new file mode 100644 index 0000000000..cf60c8dcb0 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -0,0 +1,936 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.14850 +* personalities 6.0.0.0 +* udd 3.0.0.2024 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) +#include "cycfg_routing.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_WCO_IN_ENABLED 1U +#define CYBSP_WCO_IN_PORT GPIO_PRT0 +#define CYBSP_WCO_IN_PORT_NUM 0U +#define CYBSP_WCO_IN_PIN 0U +#define CYBSP_WCO_IN_NUM 0U +#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN P0_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_WCO_OUT_ENABLED 1U +#define CYBSP_WCO_OUT_PORT GPIO_PRT0 +#define CYBSP_WCO_OUT_PORT_NUM 0U +#define CYBSP_WCO_OUT_PIN 1U +#define CYBSP_WCO_OUT_NUM 1U +#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT P0_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SW2 (P0_4) + #define CYBSP_USER_BTN1 CYBSP_SW2 + #define CYBSP_USER_BTN CYBSP_SW2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED_RGB_GREEN (P0_5) + #define CYBSP_USER_LED4 CYBSP_LED_RGB_GREEN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A0 (P10_0) + #define CYBSP_J2_1 CYBSP_A0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A1 (P10_1) + #define CYBSP_J2_3 CYBSP_A1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A2 (P10_2) + #define CYBSP_J2_5 CYBSP_A2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A3 (P10_3) + #define CYBSP_J2_7 CYBSP_A3 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A4 (P10_4) + #define CYBSP_J2_9 CYBSP_A4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A5 (P10_5) + #define CYBSP_J2_11 CYBSP_A5 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A6 (P10_6) + #define CYBSP_J2_13 CYBSP_A6 + #define CYBSP_POT CYBSP_A6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A7 (P10_7) + #define CYBSP_J2_15 CYBSP_A7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_FRAM_SSEL (P11_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED9 (P11_1) + #define CYBSP_USER_LED2 CYBSP_LED9 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS (P11_2) + #define CYBSP_QSPI_FLASH_SSEL CYBSP_QSPI_SS +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3 (P11_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2 (P11_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1 (P11_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0 (P11_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK (P11_7) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SPI_MOSI (P12_0) + #define CYBSP_D11 CYBSP_SPI_MOSI +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SPI_MISO (P12_1) + #define CYBSP_D12 CYBSP_SPI_MISO +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SPI_CLK (P12_2) + #define CYBSP_D13 CYBSP_SPI_CLK +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SPI_CS (P12_3) + #define CYBSP_D10 CYBSP_SPI_CS +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_CMD (P12_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_CLK (P12_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_IO0 (P13_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_IO1 (P13_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_IO2 (P13_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_IO3 (P13_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_DETECT (P13_5) +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_RX_ENABLED 1U +#define CYBSP_CS_RX_ENABLED CYBSP_CSD_RX_ENABLED +#define CYBSP_CS_TX_RX_ENABLED CYBSP_CSD_RX_ENABLED +#define CYBSP_CSD_RX_PORT GPIO_PRT1 +#define CYBSP_CS_RX_PORT CYBSP_CSD_RX_PORT +#define CYBSP_CS_TX_RX_PORT CYBSP_CSD_RX_PORT +#define CYBSP_CSD_RX_PORT_NUM 1U +#define CYBSP_CS_RX_PORT_NUM CYBSP_CSD_RX_PORT_NUM +#define CYBSP_CS_TX_RX_PORT_NUM CYBSP_CSD_RX_PORT_NUM +#define CYBSP_CSD_RX_PIN 0U +#define CYBSP_CS_RX_PIN CYBSP_CSD_RX_PIN +#define CYBSP_CS_TX_RX_PIN CYBSP_CSD_RX_PIN +#define CYBSP_CSD_RX_NUM 0U +#define CYBSP_CS_RX_NUM CYBSP_CSD_RX_NUM +#define CYBSP_CS_TX_RX_NUM CYBSP_CSD_RX_NUM +#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_RX_DRIVEMODE CYBSP_CSD_RX_DRIVEMODE +#define CYBSP_CS_TX_RX_DRIVEMODE CYBSP_CSD_RX_DRIVEMODE +#define CYBSP_CSD_RX_INIT_DRIVESTATE 1 +#define CYBSP_CS_RX_INIT_DRIVESTATE CYBSP_CSD_RX_INIT_DRIVESTATE +#define CYBSP_CS_TX_RX_INIT_DRIVESTATE CYBSP_CSD_RX_INIT_DRIVESTATE +#ifndef ioss_0_port_1_pin_0_HSIOM + #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CYBSP_CS_RX_HSIOM CYBSP_CSD_RX_HSIOM +#define CYBSP_CS_TX_RX_HSIOM CYBSP_CSD_RX_HSIOM +#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_CS_RX_IRQ CYBSP_CSD_RX_IRQ +#define CYBSP_CS_TX_RX_IRQ CYBSP_CSD_RX_IRQ +#if defined (CY_USING_HAL) + #define CYBSP_CSD_RX_HAL_PORT_PIN P1_0 + #define CYBSP_CS_RX_HAL_PORT_PIN CYBSP_CSD_RX_HAL_PORT_PIN + #define CYBSP_CS_TX_RX_HAL_PORT_PIN CYBSP_CSD_RX_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_RX P1_0 + #define CYBSP_CS_RX CYBSP_CSD_RX + #define CYBSP_CS_TX_RX CYBSP_CSD_RX +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_RX_HAL_IRQ CYBSP_CSD_RX_HAL_IRQ + #define CYBSP_CS_TX_RX_HAL_IRQ CYBSP_CSD_RX_HAL_IRQ +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_RX_HAL_DIR CYBSP_CSD_RX_HAL_DIR + #define CYBSP_CS_TX_RX_HAL_DIR CYBSP_CSD_RX_HAL_DIR +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_RX_HAL_DRIVEMODE CYBSP_CSD_RX_HAL_DRIVEMODE + #define CYBSP_CS_TX_RX_HAL_DRIVEMODE CYBSP_CSD_RX_HAL_DRIVEMODE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED_RGB_RED (P1_1) + #define CYBSP_USER_LED3 CYBSP_LED_RGB_RED +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SW4 (P1_4) + #define CYBSP_USER_BTN2 CYBSP_SW4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED4 (P13_7) + #define CYBSP_USER_LED1 CYBSP_LED4 + #define CYBSP_USER_LED CYBSP_LED4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_D0 (P2_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_D1 (P2_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_D2 (P2_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_D3 (P2_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_CMD (P2_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_CLK (P2_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_WL_REG_ON (P2_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RX (P3_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_TX (P3_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RTS (P3_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_CTS (P3_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_POWER (P3_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_DEVICE_WAKE (P3_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_HOST_WAKE (P4_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_HOST_WAKE (P4_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_RX (P5_0) + #define CYBSP_D0 CYBSP_DEBUG_UART_RX +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_TX (P5_1) + #define CYBSP_D1 CYBSP_DEBUG_UART_TX + #define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5 + #define CYBSP_DEBUG_UART_TX_PIN 1U +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_RTS (P5_2) + #define CYBSP_D2 CYBSP_DEBUG_UART_RTS +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_CTS (P5_3) + #define CYBSP_D3 CYBSP_DEBUG_UART_CTS +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_D4 (P5_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_D5 (P5_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_D6 (P5_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_D7 (P5_7) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL (P6_0) + #define CYBSP_D15 CYBSP_I2C_SCL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA (P6_1) + #define CYBSP_D14 CYBSP_I2C_SDA +#endif //defined (CY_USING_HAL) +#define CYBSP_SWO_ENABLED 1U +#define CYBSP_SWO_PORT GPIO_PRT6 +#define CYBSP_SWO_PORT_NUM 6U +#define CYBSP_SWO_PIN 4U +#define CYBSP_SWO_NUM 4U +#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_PORT_PIN P6_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO P6_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_SWDIO_ENABLED 1U +#define CYBSP_SWDIO_PORT GPIO_PRT6 +#define CYBSP_SWDIO_PORT_NUM 6U +#define CYBSP_SWDIO_PIN 6U +#define CYBSP_SWDIO_NUM 6U +#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO P6_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP +#endif //defined (CY_USING_HAL) +#define CYBSP_SWDCK_ENABLED 1U +#define CYBSP_SWDCK_PORT GPIO_PRT6 +#define CYBSP_SWDCK_PORT_NUM 6U +#define CYBSP_SWDCK_PIN 7U +#define CYBSP_SWDCK_NUM 7U +#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define CYBSP_SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK P6_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN +#endif //defined (CY_USING_HAL) +#define CYBSP_CINA_ENABLED 1U +#define CYBSP_CINA_PORT GPIO_PRT7 +#define CYBSP_CINA_PORT_NUM 7U +#define CYBSP_CINA_PIN 1U +#define CYBSP_CINA_NUM 1U +#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CINA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_1_HSIOM + #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM +#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CINA_HAL_PORT_PIN P7_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINA P7_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CINB_ENABLED 1U +#define CYBSP_CINB_PORT GPIO_PRT7 +#define CYBSP_CINB_PORT_NUM 7U +#define CYBSP_CINB_PIN 2U +#define CYBSP_CINB_NUM 2U +#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CINB_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_2_HSIOM + #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM +#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CINB_HAL_PORT_PIN P7_2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINB P7_2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED_RGB_BLUE (P7_3) + #define CYBSP_USER_LED5 CYBSP_LED_RGB_BLUE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_D8 (P7_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_D9 (P7_6) +#endif //defined (CY_USING_HAL) +#define CYBSP_CMOD_ENABLED 1U +#define CYBSP_CMOD_PORT GPIO_PRT7 +#define CYBSP_CMOD_PORT_NUM 7U +#define CYBSP_CMOD_PIN 7U +#define CYBSP_CMOD_NUM 7U +#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CMOD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_7_HSIOM + #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM +#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CMOD_HAL_PORT_PIN P7_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CMOD P7_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_BTN0_ENABLED 1U +#define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED +#define CYBSP_CSD_BTN0_PORT GPIO_PRT8 +#define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT +#define CYBSP_CSD_BTN0_PORT_NUM 8U +#define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM +#define CYBSP_CSD_BTN0_PIN 1U +#define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN +#define CYBSP_CSD_BTN0_NUM 1U +#define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM +#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE +#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1 +#define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE +#ifndef ioss_0_port_8_pin_1_HSIOM + #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM +#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1 + #define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0 P8_1 + #define CYBSP_CS_BTN0 CYBSP_CSD_BTN0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_BTN1_ENABLED 1U +#define CYBSP_CS_BTN1_ENABLED CYBSP_CSD_BTN1_ENABLED +#define CYBSP_CSD_BTN1_PORT GPIO_PRT8 +#define CYBSP_CS_BTN1_PORT CYBSP_CSD_BTN1_PORT +#define CYBSP_CSD_BTN1_PORT_NUM 8U +#define CYBSP_CS_BTN1_PORT_NUM CYBSP_CSD_BTN1_PORT_NUM +#define CYBSP_CSD_BTN1_PIN 2U +#define CYBSP_CS_BTN1_PIN CYBSP_CSD_BTN1_PIN +#define CYBSP_CSD_BTN1_NUM 2U +#define CYBSP_CS_BTN1_NUM CYBSP_CSD_BTN1_NUM +#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_BTN1_DRIVEMODE CYBSP_CSD_BTN1_DRIVEMODE +#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1 +#define CYBSP_CS_BTN1_INIT_DRIVESTATE CYBSP_CSD_BTN1_INIT_DRIVESTATE +#ifndef ioss_0_port_8_pin_2_HSIOM + #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CYBSP_CS_BTN1_HSIOM CYBSP_CSD_BTN1_HSIOM +#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_BTN1_IRQ CYBSP_CSD_BTN1_IRQ +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2 + #define CYBSP_CS_BTN1_HAL_PORT_PIN CYBSP_CSD_BTN1_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1 P8_2 + #define CYBSP_CS_BTN1 CYBSP_CSD_BTN1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_BTN1_HAL_IRQ CYBSP_CSD_BTN1_HAL_IRQ +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_BTN1_HAL_DIR CYBSP_CSD_BTN1_HAL_DIR +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_BTN1_HAL_DRIVEMODE CYBSP_CSD_BTN1_HAL_DRIVEMODE +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD0_ENABLED 1U +#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED +#define CYBSP_CSD_SLD0_PORT GPIO_PRT8 +#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT +#define CYBSP_CSD_SLD0_PORT_NUM 8U +#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM +#define CYBSP_CSD_SLD0_PIN 3U +#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN +#define CYBSP_CSD_SLD0_NUM 3U +#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM +#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE +#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE +#ifndef ioss_0_port_8_pin_3_HSIOM + #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM +#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3 + #define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0 P8_3 + #define CYBSP_CS_SLD0 CYBSP_CSD_SLD0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD1_ENABLED 1U +#define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED +#define CYBSP_CSD_SLD1_PORT GPIO_PRT8 +#define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT +#define CYBSP_CSD_SLD1_PORT_NUM 8U +#define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM +#define CYBSP_CSD_SLD1_PIN 4U +#define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN +#define CYBSP_CSD_SLD1_NUM 4U +#define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM +#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE +#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE +#ifndef ioss_0_port_8_pin_4_HSIOM + #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM +#define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM +#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4 + #define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1 P8_4 + #define CYBSP_CS_SLD1 CYBSP_CSD_SLD1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD2_ENABLED 1U +#define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED +#define CYBSP_CSD_SLD2_PORT GPIO_PRT8 +#define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT +#define CYBSP_CSD_SLD2_PORT_NUM 8U +#define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM +#define CYBSP_CSD_SLD2_PIN 5U +#define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN +#define CYBSP_CSD_SLD2_NUM 5U +#define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM +#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE +#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE +#ifndef ioss_0_port_8_pin_5_HSIOM + #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM +#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5 + #define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2 P8_5 + #define CYBSP_CS_SLD2 CYBSP_CSD_SLD2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD3_ENABLED 1U +#define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED +#define CYBSP_CSD_SLD3_PORT GPIO_PRT8 +#define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT +#define CYBSP_CSD_SLD3_PORT_NUM 8U +#define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM +#define CYBSP_CSD_SLD3_PIN 6U +#define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN +#define CYBSP_CSD_SLD3_NUM 6U +#define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM +#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE +#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE +#ifndef ioss_0_port_8_pin_6_HSIOM + #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM +#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6 + #define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3 P8_6 + #define CYBSP_CS_SLD3 CYBSP_CSD_SLD3 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD4_ENABLED 1U +#define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED +#define CYBSP_CSD_SLD4_PORT GPIO_PRT8 +#define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT +#define CYBSP_CSD_SLD4_PORT_NUM 8U +#define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM +#define CYBSP_CSD_SLD4_PIN 7U +#define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN +#define CYBSP_CSD_SLD4_NUM 7U +#define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM +#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE +#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE +#ifndef ioss_0_port_8_pin_7_HSIOM + #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM +#define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM +#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7 + #define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4 P8_7 + #define CYBSP_CS_SLD4 CYBSP_CSD_SLD4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A8 (P9_0) + #define CYBSP_J2_2 CYBSP_A8 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A9 (P9_1) + #define CYBSP_J2_4 CYBSP_A9 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A10 (P9_2) + #define CYBSP_J2_6 CYBSP_A10 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A11 (P9_3) + #define CYBSP_J2_8 CYBSP_A11 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A12 (P9_4) + #define CYBSP_J2_10 CYBSP_A12 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A13 (P9_5) + #define CYBSP_J2_12 CYBSP_A13 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A14 (P9_6) + #define CYBSP_J2_14 CYBSP_A14 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_A15 (P9_7) + #define CYBSP_J2_16 CYBSP_A15 +#endif //defined (CY_USING_HAL) + +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config; +#define CYBSP_CS_RX_config CYBSP_CSD_RX_config +#define CYBSP_CS_TX_RX_config CYBSP_CSD_RX_config +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj; + #define CYBSP_CS_RX_obj CYBSP_CSD_RX_obj + #define CYBSP_CS_TX_RX_obj CYBSP_CSD_RX_obj +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWO_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CINA_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CINB_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CMOD_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config; +#define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj; + #define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config; +#define CYBSP_CS_BTN1_config CYBSP_CSD_BTN1_config +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj; + #define CYBSP_CS_BTN1_obj CYBSP_CSD_BTN1_obj +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config; +#define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj; + #define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config; +#define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj; + #define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config; +#define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj; + #define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config; +#define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj; + #define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config; +#define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj; + #define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj +#endif //defined (CY_USING_HAL) + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c new file mode 100644 index 0000000000..e92520d238 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -0,0 +1,271 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.c +* +* Description: +* Provides definitions of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* QSPI Configurator 2.20.0.2857 +* +******************************************************************************** +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_qspi_memslot.h" + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xECU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_QUAD, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0x01U, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 4U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x06U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x04U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xDCU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x60U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x34U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x35U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x05U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x01U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 = +{ + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x04U, + /* The size of the memory. */ + .memSize = 0x04000000U, + /* Specifies the Read command. */ + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd, + /* Specifies the Erase command. */ + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x00040000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd, + /* Specifies the Program command. */ + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd, + /* Specifies the page size for programming. */ + .programSize = 0x00000200U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x01U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x02U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 2600U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 460000U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 1300U, +#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50) + /* Points to NULL or to structure with info about sectors for hybrid memory. */ + .hybridRegionCount = 0U, + .hybridRegionInfo = NULL +#endif +}; + +const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 = +{ + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_0, + /* Flags. */ + .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN, + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave is mapped to in the PSoC memory map. + Valid when the memory-mapped mode is enabled. */ + .baseAddress = 0x18000000U, + /* The size allocated in the PSoC memory map, for the memory slave device. + The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ + .memMappedSize = 0x4000000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + Valid when the memory mapped mode is enabled. */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0 +}; + +const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { + &S25FL512S_SlaveSlot_0 +}; + +const cy_stc_smif_block_config_t smifBlockConfig = +{ + /* The number of SMIF memories defined. */ + .memCount = CY_SMIF_DEVICE_NUM, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR +}; + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h new file mode 100644 index 0000000000..021bccf157 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -0,0 +1,65 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.h +* +* Description: +* Provides declarations of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* QSPI Configurator 2.20.0.2857 +* +******************************************************************************** +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#ifndef CYCFG_QSPI_MEMSLOT_H +#define CYCFG_QSPI_MEMSLOT_H +#include "cy_smif_memslot.h" + +#define CY_SMIF_CFG_TOOL_VERSION (220) + +/* Supported QSPI Driver version */ +#define CY_SMIF_DRV_VERSION_REQUIRED (100) + +#if !defined(CY_SMIF_DRV_VERSION) + #define CY_SMIF_DRV_VERSION (100) +#endif + +/* Check the used Driver version */ +#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION) + #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project. +#endif + +#define CY_SMIF_DEVICE_NUM 1 + +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; + +extern const cy_stc_smif_block_config_t smifBlockConfig; + + +#endif /*CYCFG_QSPI_MEMSLOT_H*/ + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c new file mode 100644 index 0000000000..2a8d923a29 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: cycfg_routing.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_routing.h" + +#include "cy_device_headers.h" + +void init_cycfg_routing(void) +{ + HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; + HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; +} diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h new file mode 100644 index 0000000000..665dffa162 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* File Name: cycfg_routing.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() +#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN +#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_ROUTING_H */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c new file mode 100644 index 0000000000..e137a92baf --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -0,0 +1,1212 @@ +/******************************************************************************* +* File Name: cycfg_system.c +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.14850 +* personalities 6.0.0.0 +* udd 3.0.0.2024 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_system.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_LF +#define CY_CFG_SYSCLK_CLKALTSYSTICK_INTERVAL 0 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_FREQUENCY 32768 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS ((0)/1000000.0)*32768 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_MULT 500U +#define CY_CFG_SYSCLK_FLL_REFDIV 20U +#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4 +#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true +#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U +#define CY_CFG_SYSCLK_FLL_IGAIN 9U +#define CY_CFG_SYSCLK_FLL_PGAIN 5U +#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U +#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT +#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U +#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_ILO_HIBERNATE true +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 30 +#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1 +#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 5 +#define CY_CFG_SYSCLK_PLL0_LF_MODE false +#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 48000000 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0 +#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 +#define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO +#define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0 +#define CY_CFG_SYSCLK_WCO_IN_PIN 0U +#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0 +#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U +#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_INIT 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP +#define CY_CFG_PWR_USING_ULP 0 +#define CY_CFG_PWR_REGULATOR_MODE_MIN false +#define CY_CFG_PWR_BKP_ERROR 6 + +#if defined (CY_DEVICE_SECURE) + static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig; +#endif //defined (CY_DEVICE_SECURE) +#if (!defined(CY_DEVICE_SECURE)) + static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = + { + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 10U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, + }; +#endif //(!defined(CY_DEVICE_SECURE)) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 1U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 2U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 3U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 4U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 5U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if (!defined(CY_DEVICE_SECURE)) + static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = + { + .feedbackDiv = 30, + .referenceDiv = 1, + .outputDiv = 5, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + }; +#endif //(!defined(CY_DEVICE_SECURE)) + +__WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +#if defined (CY_DEVICE_SECURE) + void init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config) + { + #ifdef CY_CFG_PWR_ENABLED + secure_config->powerEnable = CY_CFG_PWR_ENABLED; + #endif /* CY_CFG_PWR_ENABLED */ + + #ifdef CY_CFG_PWR_USING_LDO + secure_config->ldoEnable = CY_CFG_PWR_USING_LDO; + #endif /* CY_CFG_PWR_USING_LDO */ + + #ifdef CY_CFG_PWR_USING_PMIC + secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC; + #endif /* CY_CFG_PWR_USING_PMIC */ + + #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD + secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD; + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + + #ifdef CY_CFG_PWR_USING_ULP + secure_config->ulpEnable = CY_CFG_PWR_USING_ULP; + #endif /* CY_CFG_PWR_USING_ULP */ + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED; + #endif /* CY_CFG_SYSCLK_ECO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED; + #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED; + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED; + #endif /* CY_CFG_SYSCLK_WCO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED; + #endif /* CY_CFG_SYSCLK_FLL_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED + secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices. + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED; + #endif /* CY_CFG_SYSCLK_PILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED; + #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */ + + #ifdef CY_CFG_PWR_LDO_VOLTAGE + secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE; + #endif /* CY_CFG_PWR_LDO_VOLTAGE */ + + #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN + secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN; + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ + + #ifdef CY_CFG_PWR_BUCK_VOLTAGE + secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE; + #endif /* CY_CFG_PWR_BUCK_VOLTAGE */ + + #ifdef CY_CFG_SYSCLK_ECO_FREQ + secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ECO_CLOAD + secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ECO_ESR + secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR; + #endif /* CY_CFG_SYSCLK_ECO_ESR */ + + #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL + secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL; + #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT + secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT + secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN + secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN + secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ; + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT + secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN + secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM + secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */ + + #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE + secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE; + #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */ + + #ifdef CY_CFG_SYSCLK_WCO_BYPASS + secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS; + #endif /* CY_CFG_SYSCLK_WCO_BYPASS */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PRT + secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT; + #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT + secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PIN + secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN; + #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN + secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ + secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_FLL_MULT + secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT; + #endif /* CY_CFG_SYSCLK_FLL_MULT */ + + #ifdef CY_CFG_SYSCLK_FLL_REFDIV + secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV; + #endif /* CY_CFG_SYSCLK_FLL_REFDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE + secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE; + #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV + secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV; + #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE + secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE; + #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */ + + #ifdef CY_CFG_SYSCLK_FLL_IGAIN + secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN; + #endif /* CY_CFG_SYSCLK_FLL_IGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_PGAIN + secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN; + #endif /* CY_CFG_SYSCLK_FLL_PGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT + secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT; + #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */ + + #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE + secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ + secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV + secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV + secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV + secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE + secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE + secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ + secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV + secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV + secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV + secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE + secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE + secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ + secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE + secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE + secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE + secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE + secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE + secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE + secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER + secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER + secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER + secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH + secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER + secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ + secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH + secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER + secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ + secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH + secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER + secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ + secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH + secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER + secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ + secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH + secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER + secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ + secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH + secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER + secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ + secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE + secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER + secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE + secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE + secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE + secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER + secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE + secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD + secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME + secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ + secure_config->altHFclkFreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV + secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR + secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */ + } +#endif //defined (CY_DEVICE_SECURE) +__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() +{ + Cy_SysTick_Init(CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE, CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS); +} +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkBakInit() + { + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkFastInit() + { + Cy_SysClk_ClkFastSetDivider(0U); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_FllInit() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkHf0Init() + { + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_IloInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkLfInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkPath0Init() + { + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkPath1Init() + { + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkPath2Init() + { + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkPath3Init() + { + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkPath4Init() + { + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkPath5Init() + { + Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkPeriInit() + { + Cy_SysClk_ClkPeriSetDivider(0U); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_Pll0Init() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkSlowInit() + { + Cy_SysClk_ClkSlowSetDivider(0U); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_ClkTimerInit() + { + Cy_SysClk_ClkTimerDisable(); + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); + Cy_SysClk_ClkTimerSetDivider(0U); + Cy_SysClk_ClkTimerEnable(); + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void Cy_SysClk_WcoInit() + { + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } + } +#endif //(!defined(CY_DEVICE_SECURE)) +#if (!defined(CY_DEVICE_SECURE)) + __STATIC_INLINE void init_cycfg_power(void) + { + /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + #if CY_CFG_SYSCLK_WCO_ENABLED + uint32_t wcoTrim = Cy_SysLib_GetWcoTrim(); + if (CY_SYSLIB_SUCCESS != Cy_SysLib_ResetBackupDomain()) + { + Cy_SysLib_DelayUs(1U); + if (CY_SYSLIB_SUCCESS != Cy_SysLib_GetResetStatus()) + { + cycfg_ClockStartupError(CY_CFG_PWR_BKP_ERROR); + } + } + Cy_SysLib_SetWcoTrim(wcoTrim); + #else /* CY_CFG_SYSCLK_WCO_ENABLED */ + (void) Cy_SysLib_ResetBackupDomain(); + #endif /* CY_CFG_SYSCLK_WCO_ENABLED */ + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + /* Configure core regulator */ + #if !(defined(CY_DEVICE_SECURE)) + #if defined (CY_IP_M4CPUSS) + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); + #else + Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); + #endif /* CY_CFG_PWR_USING_LDO */ + #endif /* defined (CY_IP_M4CPUSS) */ + #if CY_CFG_PWR_REGULATOR_MODE_MIN + Cy_SysPm_SystemSetMinRegulatorCurrent(); + #else + Cy_SysPm_SystemSetNormalRegulatorCurrent(); + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ + #endif /* !(defined(CY_DEVICE_SECURE)) */ + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif /* CY_CFG_PWR_USING_PMIC */ + } +#endif //(!defined(CY_DEVICE_SECURE)) + + +void init_cycfg_system(void) +{ + #if defined(CY_DEVICE_SECURE) + cy_en_pra_status_t configStatus; + init_cycfg_secure_struct(&srss_0_clock_0_secureConfig); + #if (((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0UL)) + #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0. + #endif + #if (((CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 1UL)) + #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0. + #endif + #if (((CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 2UL)) + #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0. + #endif + #if (((CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 3UL)) + #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0. + #endif + #if (((CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 4UL)) + #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0. + #endif + #if (((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL)) + #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0. + #endif + + configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC, + CY_PRA_FUNC_INIT_CYCFG_DEVICE, + &srss_0_clock_0_secureConfig); + if ( configStatus != CY_PRA_STATUS_SUCCESS ) + { + cycfg_ClockStartupError(configStatus); + } + + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ); + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + #else /* defined(CY_DEVICE_SECURE) */ + + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #if (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED) + + Cy_SysClk_AltHfInit(); + #endif /* (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED */ + + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + #ifndef CY_CFG_SYSCLK_CLKHF0_ENABLED + #error the CLKHF0 must be enabled for proper chip operation + #endif + + #endif /* defined(CY_DEVICE_SECURE) */ + + #ifdef CY_CFG_SYSCLK_MFO_ENABLED + Cy_SysClk_MfoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED + Cy_SysClk_ClkMfInit(); + #endif + + #if (!defined(CY_DEVICE_SECURE)) + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); + #ifndef CY_CFG_SYSCLK_ILO_ENABLED + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */ + Cy_SysLib_DelayUs(200U); + #endif + Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); + #endif + + #endif /* (!defined(CY_DEVICE_SECURE)) */ + + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h new file mode 100644 index 0000000000..91cc759b5e --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -0,0 +1,116 @@ +/******************************************************************************* +* File Name: cycfg_system.h +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.4.0.5972 +* mtb-pdl-cat1 2.4.0.13881 +* personalities 6.0.0.0 +* udd 3.0.0.1974 +* +******************************************************************************** +* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_SYSTEM_H) +#define CYCFG_SYSTEM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_pra.h" +#include "cy_pra_cfg.h" +#include "cy_systick.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define cpuss_0_dap_0_ENABLED 1U +#define srss_0_clock_0_ENABLED 1U +#define srss_0_clock_0_altsystickclk_0_ENABLED 1U +#define srss_0_clock_0_bakclk_0_ENABLED 1U +#define srss_0_clock_0_fastclk_0_ENABLED 1U +#define srss_0_clock_0_fll_0_ENABLED 1U +#define srss_0_clock_0_hfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF0 0UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL +#define srss_0_clock_0_ilo_0_ENABLED 1U +#define srss_0_clock_0_imo_0_ENABLED 1U +#define srss_0_clock_0_lfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO +#define srss_0_clock_0_pathmux_0_ENABLED 1U +#define srss_0_clock_0_pathmux_1_ENABLED 1U +#define srss_0_clock_0_pathmux_2_ENABLED 1U +#define srss_0_clock_0_pathmux_3_ENABLED 1U +#define srss_0_clock_0_pathmux_4_ENABLED 1U +#define srss_0_clock_0_pathmux_5_ENABLED 1U +#define srss_0_clock_0_periclk_0_ENABLED 1U +#define srss_0_clock_0_pll_0_ENABLED 1U +#define srss_0_clock_0_slowclk_0_ENABLED 1U +#define srss_0_clock_0_timerclk_0_ENABLED 1U +#define srss_0_clock_0_wco_0_ENABLED 1U +#define srss_0_power_0_ENABLED 1U +#define CY_CFG_PWR_MODE_LP 0x01UL +#define CY_CFG_PWR_MODE_ULP 0x02UL +#define CY_CFG_PWR_MODE_ACTIVE 0x04UL +#define CY_CFG_PWR_MODE_SLEEP 0x08UL +#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL +#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP +#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP +#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL +#define CY_CFG_PWR_USING_LDO 1 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VBACKUP_MV 3300 +#define CY_CFG_PWR_VDD_NS_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 + +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_system(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_SYSTEM_H */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg new file mode 100644 index 0000000000..d6436810a4 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -0,0 +1,29 @@ +################################################################################ +# File Name: qspi_config.cfg +# +# Description: +# This file contains a SMIF Bank layout for use with OpenOCD. +# This file was automatically generated and should not be modified. +# QSPI Configurator: 2.20.0.2857 +# +################################################################################ +# Copyright 2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +set SMIF_BANKS { + 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} +} + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list new file mode 100644 index 0000000000..9b7f1671f0 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -0,0 +1,20 @@ +[Device=CY8C624ABZI-S2D44] + +[Blocks] +# WIFI +# CYBSP_WIFI_SDIO +sdhc[0] +# CYBSP_WIFI_SDIO_D0 +ioss[0].port[2].pin[0] +# CYBSP_WIFI_SDIO_D1 +ioss[0].port[2].pin[1] +# CYBSP_WIFI_SDIO_D2 +ioss[0].port[2].pin[2] +# CYBSP_WIFI_SDIO_D3 +ioss[0].port[2].pin[3] +# CYBSP_WIFI_SDIO_CMD +ioss[0].port[2].pin[4] +# CYBSP_WIFI_SDIO_CLK +ioss[0].port[2].pin[5] +# CYBSP_WIFI_WL_REG_ON +ioss[0].port[2].pin[6] \ No newline at end of file diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense new file mode 100644 index 0000000000..c4327623d5 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -0,0 +1,415 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi new file mode 100644 index 0000000000..4d0dfe410b --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -0,0 +1,63 @@ + + + + PSoC 6.xml + + + 0 + S25FL512S-4byteaddr + true + None + 0x18000000 + 0x4000000 + 0x1BFFFFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL512S-4byteaddr + true + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.modus b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.modus new file mode 100644 index 0000000000..9e0667d6c9 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -0,0 +1,727 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct new file mode 100644 index 0000000000..a7264c63ac --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -0,0 +1,272 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm0plus.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Public RAM +; This is an unprotected public RAM region, with the placed .cy_sharedmem section. +; This region is used to place objects that require full access from both cores. +; Uncomment the following lines, define the region size and uncomment placement of +; .cy_sharedmem section below. +; #define PUBLIC_RAM_SIZE %REGION_SIZE% +; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. + ;RW_IRAM2 PUBLIC_RAM_START UNINIT + ;{ + ; * (.cy_sharedmem) + ;} + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s new file mode 100644 index 0000000000..332737ec48 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s @@ -0,0 +1,223 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S new file mode 100644 index 0000000000..edde48c67a --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S @@ -0,0 +1,254 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + + .section __STACK, __stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + nop +.L_API_call: + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld new file mode 100644 index 0000000000..07518669f4 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -0,0 +1,441 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm0plus.ld +* \version 2.91 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 + + + /* This is an unprotected public RAM region, with the placed .cy_sharedmem. + * This region is used to place objects that require full access from both cores. + * Uncomment the following line, define the region origin and length, and uncomment the placement of + * the .cy_sharedmem section below. + */ + /* public_ram (rw) : ORIGIN = %REGION_START_ADDRESS%, LENGTH = %REGION_SIZE% */ + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : + { + . = ALIGN(4); + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram AT>flash + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/ + /* + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + __public_ram_start__ = .; + KEEP(*(.cy_sharedmem)) + . = ALIGN(4); + __public_ram_end__ = .; + } > public_ram + */ + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S new file mode 100644 index 0000000000..9bdf9c3e26 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S @@ -0,0 +1,372 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 +.L_API_call: + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf new file mode 100644 index 0000000000..7480a10906 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -0,0 +1,253 @@ +/******************************************************************************* +* \file cy8c6xxa_cm0plus.icf +* \version 2.91 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +/* Public RAM + * This is an unprotected public RAM region, with the placed .cy_sharedmem section. + * This region is used to place objects that require full access from both cores. + * Uncomment the following lines, define region size, and uncomment the placement of + * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ + * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. + */ +/* +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +*/ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM + *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. + */ +/* +place at start of IRAM2_region { section .cy_sharedmem }; +*/ + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s new file mode 100644 index 0000000000..3fa2e866e7 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s @@ -0,0 +1,331 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c new file mode 100644 index 0000000000..3a6d54df04 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -0,0 +1,536 @@ +/***************************************************************************//** +* \file system_psoc6_cm0plus.c +* \version 2.91 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) + + +/** +* Holds the system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1M_THRESHOLD (1000000u) + +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + + +/******************************************************************************* +* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() +*******************************************************************************/ +#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) +#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system on CAT1A: +* - Restores FLL registers to the default state. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref Cy_PRA_Init() for PSoC 64 devices. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + CY_SECTION_SHAREDMEM + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 + }; + + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + #if defined(CY_DEVICE_SECURE) + /* Initialize Protected Regsiter Access driver. */ + Cy_PRA_Init(); + #endif /* defined(CY_DEVICE_SECURE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); + + if (0UL != locHf0Clock) + { + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; + } +} + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysGetCM4Status +****************************************************************************//** +* +* Returns the Cortex-M4 core power mode. +* +* \return \ref group_system_config_cm4_status_macro +* +*******************************************************************************/ +uint32_t Cy_SysGetCM4Status(void) +{ + uint32_t regValue; + + /* Get current power mode */ + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; + + return (regValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysEnableCM4 +****************************************************************************//** +* +* Sets vector table base address and enables the Cortex-M4 core. +* +* \note If the CPU is already enabled, it is reset and then enabled. +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +void Cy_SysEnableCM4(uint32_t vectorTableOffset) +{ + uint32_t regValue; + uint32_t interruptState; + uint32_t cpuState; + + CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); + + interruptState = Cy_SysLib_EnterCriticalSection(); + + cpuState = Cy_SysGetCM4Status(); + if (CY_SYS_CM4_STATUS_ENABLED == cpuState) + { + Cy_SysResetCM4(); + } + + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_ENABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysDisableCM4 +****************************************************************************//** +* +* Disables the Cortex-M4 core and waits for the mode to take the effect. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the +* CPU. +* +*******************************************************************************/ +void Cy_SysDisableCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_DISABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysRetainCM4 +****************************************************************************//** +* +* Retains the Cortex-M4 core and exists without waiting for the mode to take +* effect. +* +* \note The retained mode can be entered only from the enabled mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysRetainCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RETAINED; + CPUSS->CM4_PWR_CTL = regValue; + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysResetCM4 +****************************************************************************//** +* +* Resets the Cortex-M4 core and waits for the mode to take the effect. +* +* \note The reset mode can not be entered from the retained mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysResetCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RESET; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} +#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm0 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm0(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct new file mode 100644 index 0000000000..edd6046930 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -0,0 +1,277 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.91 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x000FD800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00200000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s new file mode 100644 index 0000000000..4d54e8bed1 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s @@ -0,0 +1,708 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT scb_9_interrupt_IRQHandler [WEAK] + EXPORT scb_10_interrupt_IRQHandler [WEAK] + EXPORT scb_11_interrupt_IRQHandler [WEAK] + EXPORT scb_12_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK] + EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +scb_9_interrupt_IRQHandler +scb_10_interrupt_IRQHandler +scb_11_interrupt_IRQHandler +scb_12_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dmac_2_IRQHandler +cpuss_interrupts_dmac_3_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_0_interrupt_i2s_IRQHandler +audioss_0_interrupt_pdm_IRQHandler +audioss_1_interrupt_i2s_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +sdhc_0_interrupt_wakeup_IRQHandler +sdhc_0_interrupt_general_IRQHandler +sdhc_1_interrupt_wakeup_IRQHandler +sdhc_1_interrupt_general_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..cd00f1e9f1 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S @@ -0,0 +1,565 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + .section __STACK , __stack + .align 3 + +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl _Cy_SystemInitFpuEnable + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + nop +.L_API_call: + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .end + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld new file mode 100644 index 0000000000..844ae9ff59 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -0,0 +1,465 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4_dual.ld +* \version 2.91 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0xFD800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x200000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + /* setction information for finsh shell begin */ + FSymTab : + { + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + } > flash + VSymTab : + { + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + } > flash + rti_fn : + { + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > flash + /* setction information for finsh shell end */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : + { + . = ALIGN(4); + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram AT>flash + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..c9be49b2b4 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* OS-specific low-level initialization */ + .weak cy_toolchain_init + .func cy_toolchain_init, cy_toolchain_init + .type cy_toolchain_init, %function + +cy_toolchain_init: + bx lr + .size cy_toolchain_init, . - cy_toolchain_init + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + /* OS-specific low-level initialization */ + bl cy_toolchain_init + + /* Call C/C++ static constructors */ + bl __libc_init_array + + /* Execute main application */ + bl entry + + /* Call C/C++ static destructors */ + bl __libc_fini_array + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 +.L_API_call: + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .end + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf new file mode 100644 index 0000000000..14ea8bcbac --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -0,0 +1,247 @@ +/******************************************************************************* +* \file cy8c6xxa_cm4_dual.icf +* \version 2.91 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +"cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s new file mode 100644 index 0000000000..8f1e4a57e5 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s @@ -0,0 +1,1280 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for OS-specific customization +;; + PUBWEAK cy_toolchain_init + SECTION .text:CODE:REORDER:NOROOT(2) +cy_toolchain_init + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK scb_9_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_9_interrupt_IRQHandler + B scb_9_interrupt_IRQHandler + + PUBWEAK scb_10_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_10_interrupt_IRQHandler + B scb_10_interrupt_IRQHandler + + PUBWEAK scb_11_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_11_interrupt_IRQHandler + B scb_11_interrupt_IRQHandler + + PUBWEAK scb_12_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_12_interrupt_IRQHandler + B scb_12_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_2_IRQHandler + B cpuss_interrupts_dmac_2_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_3_IRQHandler + B cpuss_interrupts_dmac_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_0_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_i2s_IRQHandler + B audioss_0_interrupt_i2s_IRQHandler + + PUBWEAK audioss_0_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_pdm_IRQHandler + B audioss_0_interrupt_pdm_IRQHandler + + PUBWEAK audioss_1_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_1_interrupt_i2s_IRQHandler + B audioss_1_interrupt_i2s_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_wakeup_IRQHandler + B sdhc_0_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_0_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_general_IRQHandler + B sdhc_0_interrupt_general_IRQHandler + + PUBWEAK sdhc_1_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_wakeup_IRQHandler + B sdhc_1_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_1_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_general_IRQHandler + B sdhc_1_interrupt_general_IRQHandler + + + END + + +; [] END OF FILE diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c new file mode 100644 index 0000000000..4da98ccdbc --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c @@ -0,0 +1,400 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.91 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default FastClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + + +/** +* Holds the system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (28u) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1M_THRESHOLD (1000000u) + +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system on CAT1A: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref Cy_PRA_Init() for PSoC 64 devices. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + /* Initialize Protected Register Access driver */ + Cy_PRA_Init(); +#endif /* defined(CY_DEVICE_SECURE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); + + if (0UL != locHf0Clock) + { + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; + } +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/EULA b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/EULA new file mode 100644 index 0000000000..f10c742b10 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/EULA @@ -0,0 +1,55 @@ +CYPRESS END USER LICENSE AGREEMENT + +PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING DOCUMENTATION. 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Limitation of Liability. + +In no event and under no legal theory, whether in tort (including negligence), +contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be +liable to You for damages, including any direct, indirect, special, incidental, +or consequential damages of any character arising as a result of this License or +out of the use or inability to use the Work (including but not limited to +damages for loss of goodwill, work stoppage, computer failure or malfunction, or +any and all other commercial damages or losses), even if such Contributor has +been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to +offer, and charge a fee for, acceptance of support, warranty, indemnity, or +other liability obligations and/or rights consistent with this License. However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/README.md b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/README.md new file mode 100644 index 0000000000..5043d4b062 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/README.md @@ -0,0 +1,76 @@ +# CY8CKIT-062S2-43012 BSP + +## Overview + +The CY8CKIT-062S2-43012 PSoC™ 6S2 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC™ 6 MCUs. It comes with a Murata 1LV Module (CYW43012 Wi-Fi + Bluetooth Combo Chip), industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface. + +![](docs/html/board.png) + +To use code from the BSP, simply include a reference to `cybsp.h`. + +## Features + +### Kit Features: + +* Support of up to 2MB Flash and 1MB SRAM +* Dedicated SDHC to interface with WICED wireless devices. +* Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm Cortex-M0+ as the secondary processor for low-power operations. +* Supports Full-Speed USB, capacitive-sensing with CAPSENSE, a PDM-PCM digital microphone interface, a Quad-SPI interface, 13 serial communication blocks, 7 programmable analog blocks, and 56 programmable digital blocks. + +### Kit Contents: + +* PSoC™ 6S2 Wi-Fi BT Pioneer Board +* USB Type-A to Micro-B cable +* Quick Start Guide +* Four jumper wires (4 inches each) +* Two jumper wires (5 inches each) + +## BSP Configuration + +The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CKIT-062S2-43012.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile. + +Components: +* Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board. +* BSP_DESIGN_MODUS - This component, enabled by default, causes the Configurator generated code for this specific BSP to be included. This should not be used at the same time as the CUSTOM_DESIGN_MODUS component. +* CUSTOM_DESIGN_MODUS - This component, disabled by default, causes the Configurator generated code from the application to be included. This assumes that the application provides configurator generated code. This should not be used at the same time as the BSP_DESIGN_MODUS component. + +Defines: +* CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one. +* CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers. +* CYBSP_CUSTOM_SYSCLK_PM_CALLBACK - This define, disabled by default, causes the BSP to skip registering its default SysClk Power Management callback, if any, and instead to invoke the application-defined function `cybsp_register_custom_sysclk_pm_callback` to register an application-specific callback. + +### Clock Configuration + +| Clock | Source | Output Frequency | +|----------|-----------|------------------| +| FLL | IMO | 100.0 MHz | +| PLL | IMO | 48.0 MHz | +| CLK_HF0 | CLK_PATH0 | 100 MHz | + +### Power Configuration + +* System Active Power Mode: LP +* System Idle Power Mode: Deep Sleep +* VDDA Voltage: 3300 mV +* VDDD Voltage: 3300 mV + +See the [BSP Setttings][settings] for additional board specific configuration settings. + +## API Reference Manual + +The CY8CKIT-062S2-43012 Board Support Package provides a set of APIs to configure, initialize and use the board resources. + +See the [BSP API Reference Manual][api] for the complete list of the provided interfaces. + +## More information +* [CY8CKIT-062S2-43012 BSP API Reference Manual][api] +* [CY8CKIT-062S2-43012 Documentation](http://www.cypress.com/CY8CKIT-062S2-43012) +* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com) +* [Infineon GitHub](https://github.com/infineon) +* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment) + +[api]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/modules.html +[settings]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/md_bsp_settings.html + +--- +© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2021. \ No newline at end of file diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/RELEASE.md b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/RELEASE.md new file mode 100644 index 0000000000..6f64a5a143 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/RELEASE.md @@ -0,0 +1,92 @@ +# CY8CKIT-062S2-43012 BSP Release Notes +The CY8CKIT-062S2-43012 PSoC™ 6S2 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC™ 6 MCUs. It comes with a Murata 1LV Module (CYW43012 Wi-Fi + Bluetooth Combo Chip), industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface. + +NOTE: BSPs are versioned by family. This means that version 1.2.0 of any BSP in a family (eg: PSoC™ 6) will have the same software maturity level. However, not all updates are necessarily applicable for each BSP in the family so not all version numbers will exist for each board. Additionally, new BSPs may not start at version 1.0.0. In the event of adding a common feature across all BSPs, the libraries are assigned the same version number. For example if BSP_A is at v1.3.0 and BSP_B is at v1.2.0, the event will trigger a version update to v1.4.0 for both BSP_A and BSP_B. This allows the common feature to be tracked in a consistent way. + +### What's Included? +The CY8CKIT-062S2-43012 library includes the following: +* BSP specific makefile to configure the build process for the board +* cybsp.c/h files to initialize the board and any system peripherals +* cybsp_types.h file describing basic board setup +* CM4 Linker script & startup code for GCC, IAR, and ARM toolchains +* CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains +* Configurator design files (and generated code) to setup board specific peripherals +* .lib file references for all dependent libraries +* API documentation + +### What Changed? +#### v3.1.0 +* Added optional macro CYBSP_CUSTOM_SYSCLK_PM_CALLBACK to allow overriding default clock power management behavior. +* Enable AIROC BLE stack for MCUs with an integrated BLE radio +#### v3.0.0 +* Updated to HAL dependency to v2.0.0 +* Updated CAPSENSE™ dependency to v3.0.0 +* Regenerated code with Configurators from ModusToolbox™ v2.4.0 +#### v2.3.0 +* Add new connectivity components for easier board customization +* Simplify BT configuration settings for boards that support it +* Minor branding updates +#### v2.2.0 +* Updated PSoC™ 64 linker sections to match secure policy settings +* Minor documentation updates +#### v2.1.0 +* Added component CAT1 to all boards +* Added new components for connectivity chips +* Added BT configuration settings for boards that support it +* Minor documentation updates +#### v2.0.1 +* Minor update to better handle when to include the SCL library in the build +#### v2.0.0 +* Updated design files and GeneratedSource with ModusToolbox™ 2.2 release +* Migrated pin definitions into design.modus file +* Updated clock frequencies to 100 MHz (fast) / 50 MHz (slow) +* Updated MPNs on some boards to non-obsolete parts +* Switched psoc6pdl dependency to new mtb-pdl +* Switched psoc6hal dependency to new mtb-hal +* Switched psoc6make dependency to new core-make & recipe-make-cat1a +NOTE: This version requires ModusToolbox™ tools 2.2 or later. This version is not backwards compatible with 1.X versions. Additional manual steps must be taken to successfully update a design using a 1.x version of the BSP to this version. +#### v1.3.0 +* Minor update for documentation & branding +* Updated design files to use latest personality files +* Initialize VDDA voltage if set in configurator +NOTE: This requires psoc6hal 1.3.0 or later +#### v1.2.1 +* Added 43012/4343W/43438 component to appropriate BSPs +* Added multi-image policy for secure (064) BSPs +#### v1.2.0 +* Standardize version numbering for all boards in a family +* Moved UDB SDIO implementation into its own library udb-sdio-whd library +* Added call to setup HAL SysPM driver (requires HAL 1.2.0 or later) +* Updated documentation +NOTE: This requires psoc6hal 1.2.0 or later +#### v1.1.0 +* Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core specific directories. +* Minor updates to avoid potential warnings on some toolchains +#### v1.0.1 +* Added pin references for the board's J2 Header (for appropriate boards) +#### v1.0.0 +* Initial release + +### Supported Software and Tools +This version of the CY8CKIT-062S2-43012 BSP was validated for compatibility with the following Software and Tools: + +| Software and Tools | Version | +| :--- | :----: | +| ModusToolbox™ Software Environment | 2.4.0 | +| GCC Compiler | 10.3.1 | +| IAR Compiler | 8.4 | +| ARM Compiler | 6.11 | + +Minimum required ModusToolbox™ Software Environment: v2.4.0 + +### More information +* [CY8CKIT-062S2-43012 BSP API Reference Manual][api] +* [CY8CKIT-062S2-43012 Documentation](http://www.cypress.com/CY8CKIT-062S2-43012) +* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com) +* [Infineon GitHub](https://github.com/infineon) +* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment) + +[api]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/modules.html + +--- +© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2021. \ No newline at end of file diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.c new file mode 100644 index 0000000000..e16fc38da6 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.c @@ -0,0 +1,92 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2020-2022 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) + +#include "cybsp_bt_config.h" +#include "cycfg_connectivity_bt.h" +#include "wiced_bt_dev.h" + +// Not all boards use all of these pins. Any that arn't defined we will fallback on No Connects. +#if !defined(CYBSP_BT_POWER) + #define CYBSP_BT_POWER (NC) +#endif +#if !defined(CYCFG_BT_DEV_WAKE_GPIO) + #define CYCFG_BT_DEV_WAKE_GPIO (NC) +#endif +#if !defined(CYCFG_BT_HOST_WAKE_GPIO) + #define CYCFG_BT_HOST_WAKE_GPIO (NC) +#endif +#if !defined(CYBSP_BT_UART_TX) + #define CYBSP_BT_UART_TX (NC) +#endif +#if !defined(CYBSP_BT_UART_RX) + #define CYBSP_BT_UART_RX (NC) +#endif +#if !defined(CYBSP_BT_UART_RTS) + #define CYBSP_BT_UART_RTS (NC) +#endif +#if !defined(CYBSP_BT_UART_CTS) + #define CYBSP_BT_UART_CTS (NC) +#endif + +const cybt_platform_config_t cybsp_bt_platform_cfg = +{ + .hci_config = + { + .hci_transport = CYBT_HCI_UART, + + .hci = + { + .hci_uart = + { + .uart_tx_pin = CYBSP_BT_UART_TX, + .uart_rx_pin = CYBSP_BT_UART_RX, + .uart_rts_pin = CYBSP_BT_UART_RTS, + .uart_cts_pin = CYBSP_BT_UART_CTS, + + .baud_rate_for_fw_download = CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD, + .baud_rate_for_feature = CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE, + + .data_bits = CYBSP_BT_PLATFORM_CFG_BITS_DATA, + .stop_bits = CYBSP_BT_PLATFORM_CFG_BITS_STOP, + .parity = CYHAL_UART_PARITY_NONE, + .flow_control = true + } + } + }, + + .controller_config = + { + .bt_power_pin = CYBSP_BT_POWER, + .sleep_mode = + { + .sleep_mode_enabled = CYCFG_BT_LP_ENABLED, + .device_wakeup_pin = CYCFG_BT_DEV_WAKE_GPIO, + .host_wakeup_pin = CYCFG_BT_HOST_WAKE_GPIO, + .device_wake_polarity = CYCFG_BT_DEV_WAKE_POLARITY, + .host_wake_polarity = CYCFG_BT_HOST_WAKE_IRQ_EVENT + } + }, + + .task_mem_pool_size = CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES +}; + +#endif /* defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.h new file mode 100644 index 0000000000..1912f3bc51 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/bluetooth/cybsp_bt_config.h @@ -0,0 +1,71 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2020-2021 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +/** + * \addtogroup group_bsp_bt Bluetooth Configuration Structure + * \{ + * Basic configuration structure for the Bluetooth interface on this board. + */ +#pragma once + +#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) + +#include "cybt_platform_config.h" +#include "cycfg_pins.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD) +/** If not already defined, the baud rate to download data at. */ +#define CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD (115200) +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE) +/** If not already defined, the baud rate for general operation. */ +#define CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE (115200) +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_BITS_DATA) +/** If not already defined, the number of data bits to transmit. */ +#define CYBSP_BT_PLATFORM_CFG_BITS_DATA (8) +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_BITS_STOP) +/** If not already defined, the number of stop bits to transmit. */ +#define CYBSP_BT_PLATFORM_CFG_BITS_STOP (1) +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES) +/** If not already defined, the number of bytes to allocated for the task memory pool. */ +#define CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES (2048) +#endif + +/** Bluetooth platform configuration settings for the board. */ +extern const cybt_platform_config_t cybsp_bt_platform_cfg; + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif /* defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) */ + +/** \} group_bsp_bt */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp.c b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp.c new file mode 100644 index 0000000000..1ceaf6e5a8 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp.c @@ -0,0 +1,161 @@ +/***************************************************************************//** +* \file cybsp.c +* +* Description: +* Provides initialization code for starting up the hardware contained on the +* Infineon board. +* +******************************************************************************** +* \copyright +* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cy_syspm.h" +#include "cy_sysclk.h" +#include "cybsp.h" +#if defined(CY_USING_HAL) +#include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +// The sysclk deep sleep callback is recommended to be the last callback that is executed before +// entry into deep sleep mode and the first one upon exit the deep sleep mode. +// Doing so minimizes the time spent on low power mode entry and exit. +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +static cyhal_sdio_t sdio_obj; + +//-------------------------------------------------------------------------------------------------- +// cybsp_get_wifi_sdio_obj +//-------------------------------------------------------------------------------------------------- +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} + + +#endif // if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) + +#if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) +//-------------------------------------------------------------------------------------------------- +// cybsp_register_sysclk_pm_callback +// +// Registers a power management callback that prepares the clock system for entering deep sleep mode +// and restore the clocks upon wakeup from deep sleep. +// NOTE: This is called automatically as part of \ref cybsp_init +//-------------------------------------------------------------------------------------------------- +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL }; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = + { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + + +#endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) + + +//-------------------------------------------------------------------------------------------------- +// cybsp_init +//-------------------------------------------------------------------------------------------------- +cy_rslt_t cybsp_init(void) +{ + // Setup hardware manager to track resource usage then initialize all system (clock/power) board + // configuration + #if defined(CY_USING_HAL) + cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } + + #ifdef CY_CFG_PWR_VDDA_MV + if (CY_RSLT_SUCCESS == result) + { + cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV); + } + #endif + + #else // if defined(CY_USING_HAL) + cy_rslt_t result = CY_RSLT_SUCCESS; + #endif // if defined(CY_USING_HAL) + + #if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) + init_cycfg_all(); + #endif + + if (CY_RSLT_SUCCESS == result) + { + #if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) + result = cybsp_register_custom_sysclk_pm_callback(); + #else + result = cybsp_register_sysclk_pm_callback(); + #endif + } + + #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) + // Initialize SDIO interface. This must be done before other HAL API calls as some SDIO + // implementations require specific peripheral instances. + // NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). + // This is typically done when starting up WiFi. + if (CY_RSLT_SUCCESS == result) + { + // Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, + // CYBSP_WIFI_SDIO_D3, CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); + } + #endif // defined(CYBSP_WIFI_CAPABLE) + + // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was + // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP + // reservation list (cyreservedresources.list) to make sure no resources are reserved by both. + return result; +} + + +#if defined(__cplusplus) +} +#endif diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp.h new file mode 100644 index 0000000000..4961cea9ce --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp.h @@ -0,0 +1,97 @@ +/***********************************************************************************************//** + * \file cybsp.h + * + * \brief + * Basic API for setting up boards containing a Cypress MCU. + * + *************************************************************************************************** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cybsp_types.h" +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +#include "cyhal_sdio.h" +#endif +#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) +#include "cybsp_bt_config.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * \addtogroup group_bsp_errors Error Codes + * \{ + * Error codes specific to the board. + */ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK \ + (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_errors */ + +/** + * \addtogroup group_bsp_functions Functions + * \{ + * All functions exposed by the board. + */ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) + +#define CYBSP_WIFI_INTERFACE_TYPE CYBSP_SDIO_INTERFACE + +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif // defined(CYBSP_WIFI_CAPABLE) + +#if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) +//-------------------------------------------------------------------------------------------------- +// cybsp_register_custom_sysclk_pm_callback +// +// Registers a power management callback that prepares the clock system for entering deep sleep mode +// and restore the clocks upon wakeup from deep sleep. The application should implement this +// function and define `CYBSP_CUSTOM_SYSCLK_PM_CALLBACK` if it needs to replace the default SysClk +// DeepSleep callback behavior with application specific logic. +// NOTE: This is called automatically as part of \ref cybsp_init +//-------------------------------------------------------------------------------------------------- +cy_rslt_t cybsp_register_custom_sysclk_pm_callback(void); +#endif // defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif // __cplusplus diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h new file mode 100644 index 0000000000..676746fce7 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h @@ -0,0 +1,844 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#pragma once + +#if defined(CY_USING_HAL) +#include "cyhal_pin_package.h" +#endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +/** test */ +#include "cycfg.h" +#elif defined(COMPONENT_CAT4) /* CAT4 does not have configurators so the BSP defines pins in a + * non-generated header */ +#include "cybsp_pins.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * \addtogroup group_bsp_pins Pin Mappings + * \{ + * Macro definitions for common peripheral pins on the board. + */ + +#if defined(CYBSP_USER_LED) +/** + * \addtogroup group_bsp_pins_led LED Pins + * \{ + * Pins connected to user LEDs on the board. + */ + +#ifdef CYBSP_LED_RGB_RED +/** RGB LED - Red \def CYBSP_LED_RGB_RED + */ +#endif +#ifdef CYBSP_LED_RGB_GREEN +/** RGB LED - Green \def CYBSP_LED_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED_RGB_BLUE +/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE + */ +#endif +#ifdef CYBSP_USER_LED +/** User LED \def CYBSP_USER_LED + */ +#endif +#ifdef CYBSP_USER_LED1 +/** User LED1 \def CYBSP_USER_LED1 + */ +#endif +#ifdef CYBSP_USER_LED2 +/** User LED2 \def CYBSP_USER_LED2 + */ +#endif +#ifdef CYBSP_USER_LED3 +/** User LED3 \def CYBSP_USER_LED3 + */ +#endif +#ifdef CYBSP_USER_LED4 +/** User LED 4 \def CYBSP_USER_LED4 + */ +#endif +#ifdef CYBSP_USER_LED5 +/** User LED 5 \def CYBSP_USER_LED5 + */ +#endif +#ifdef CYBSP_USER_LED6 +/** User LED 6 \def CYBSP_USER_LED6 + */ +#endif +#ifdef CYBSP_USER_LED7 +/** User LED 7 \def CYBSP_USER_LED7 + */ +#endif +#ifdef CYBSP_USER_LED8 +/** User LED 8 \def CYBSP_USER_LED8 + */ +#endif +#ifdef CYBSP_USER_LED9 +/** User LED 9 \def CYBSP_USER_LED9 + */ +#endif +#ifdef CYBSP_USER_LED10 +/** User LED 10 \def CYBSP_USER_LED10 + */ +#endif +#ifdef CYBSP_LED1 +/** LED 1 \def CYBSP_LED1 + */ +#endif +#ifdef CYBSP_LED2 +/** LED 2 \def CYBSP_LED2 + */ +#endif +#ifdef CYBSP_LED3 +/** LED 3 \def CYBSP_LED3 + */ +#endif +#ifdef CYBSP_LED3_RGB_RED +/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED + */ +#endif +#ifdef CYBSP_LED3_RGB_GREEN +/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED3_RGB_BLUE +/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE + */ +#endif +#ifdef CYBSP_LED4 +/** LED 4 \def CYBSP_LED4 + */ +#endif +#ifdef CYBSP_LED5 +/** LED 5 \def CYBSP_LED5 + */ +#endif +#ifdef CYBSP_LED6 +/** LED 6 \def CYBSP_LED6 + */ +#endif +#ifdef CYBSP_LED7 +/** LED 7 \def CYBSP_LED7 + */ +#endif +#ifdef CYBSP_LED8 +/** LED 8 \def CYBSP_LED8 + */ +#endif +#ifdef CYBSP_LED9 +/** LED 9 \def CYBSP_LED9 + */ +#endif +#ifdef CYBSP_LED10 +/** LED 10 \def CYBSP_LED10 + */ +#endif +#ifdef CYBSP_LED11 +/** LED 11 \def CYBSP_LED11 + */ +#endif +#ifdef CYBSP_LED12 +/** LED 12 \def CYBSP_LED12 + */ +#endif +#ifdef CYBSP_LED13 +/** LED 13 \def CYBSP_LED13 + */ +#endif +#ifdef CYBSP_LED_SLD0 +/** Slider LED 0 \def CYBSP_LED_SLD0 + */ +#endif +#ifdef CYBSP_LED_SLD1 +/** Slider LED 1 \def CYBSP_LED_SLD1 + */ +#endif +#ifdef CYBSP_LED_SLD2 +/** Slider LED 2 \def CYBSP_LED_SLD2 + */ +#endif +#ifdef CYBSP_LED_SLD3 +/** Slider LED 3 \def CYBSP_LED_SLD3 + */ +#endif +#ifdef CYBSP_LED_SLD4 +/** Slider LED 4 \def CYBSP_LED_SLD4 + */ +#endif +#ifdef CYBSP_LED_SLD5 +/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5 + */ +#endif +#ifdef CYBSP_LED_BTN0 +/** Button LED 0 \def CYBSP_LED_BTN0 + */ +#endif +#ifdef CYBSP_LED_BTN1 +/** Button LED 1 \def CYBSP_LED_BTN1 + */ +#endif +#ifdef CYBSP_LED_BTN2 +/** Button LED 2 \def CYBSP_LED_BTN2 + */ +#endif + +/** \} group_bsp_pins_led */ +#endif // defined(CYBSP_USER_LED) + +#if defined(CYBSP_USER_BTN) +/** + * \addtogroup group_bsp_pins_btn Button Pins + * \{ + * Pins connected to user buttons on the board. + */ + +#ifdef CYBSP_SW1 +/** Switch 1 \def CYBSP_SW1 + */ +#endif +#ifdef CYBSP_SW2 +/** Switch 2 \def CYBSP_SW2 + */ +#endif +#ifdef CYBSP_SW3 +/** Switch 3 \def CYBSP_SW3 + */ +#endif +#ifdef CYBSP_SW4 +/** Switch 4 \def CYBSP_SW4 + */ +#endif +#ifdef CYBSP_USER_BTN +/** User Button 1 \def CYBSP_USER_BTN + */ +#endif +#ifdef CYBSP_USER_BTN1 +/** User Button 1 \def CYBSP_USER_BTN1 + */ +#endif +#ifdef CYBSP_USER_BTN2 +/** User Button 2 \def CYBSP_USER_BTN2 + */ +#endif +#ifdef CYBSP_POTENTIOMETER_INPUT +/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT + */ +#endif + +/** \} group_bsp_pins_btn */ +#endif // defined(CYBSP_USER_BTN) + +#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) +/** + * \addtogroup group_bsp_pins_comm Communication Pins + * \{ + * Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...) + */ + +#ifdef CYBSP_DEBUG_UART_RX +/** Pin: UART RX \def CYBSP_DEBUG_UART_RX + */ +#endif +#ifdef CYBSP_DEBUG_UART_TX +/** Pin: UART TX \def CYBSP_DEBUG_UART_TX + */ +#endif +#ifdef CYBSP_I2C_SCL +/** Pin: I2C SCL \def CYBSP_I2C_SCL + */ +#endif +#ifdef CYBSP_I2C_SDA +/** Pin: I2C SDA \def CYBSP_I2C_SDA + */ +#endif +#ifdef CYBSP_SWDIO +/** Pin: SWDIO \def CYBSP_SWDIO + */ +#endif +#ifdef CYBSP_SWDCK +/** Pin: SWDCK \def CYBSP_SWDCK + */ +#endif +#ifdef CYBSP_SPI_MOSI +/** Pin: SPI MOSI \def CYBSP_SPI_MOSI + */ +#endif +#ifdef CYBSP_SPI_MISO +/** Pin: SPI MISO \def CYBSP_SPI_MISO + */ +#endif +#ifdef CYBSP_SPI_CLK +/** Pin: SPI CLK \def CYBSP_SPI_CLK + */ +#endif +#ifdef CYBSP_SPI_CS +/** Pin: SPI CS \def CYBSP_SPI_CS + */ +#endif +#ifdef CYBSP_SWO +/** Pin: SWO \def CYBSP_SWO + */ +#endif +#ifdef CYBSP_QSPI_SS +/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS + */ +#endif +#ifdef CYBSP_QSPI_D3 +/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3 + */ +#endif +#ifdef CYBSP_QSPI_D2 +/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2 + */ +#endif +#ifdef CYBSP_QSPI_D1 +/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1 + */ +#endif +#ifdef CYBSP_QSPI_D0 +/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0 + */ +#endif +#ifdef CYBSP_QSPI_SCK +/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D0 +/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D1 +/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D2 +/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D3 +/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CMD +/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CLK +/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK + */ +#endif +#ifdef CYBSP_WIFI_WL_REG_ON +/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON + */ +#endif +#ifdef CYBSP_WIFI_HOST_WAKE +/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE + */ + +/** WiFi host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +/** WiFi host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) +#endif +#ifdef CYBSP_BT_UART_RX +/** Pin: BT UART RX \def CYBSP_BT_UART_RX + */ +#endif +#ifdef CYBSP_BT_UART_TX +/** Pin: BT UART TX \def CYBSP_BT_UART_TX + */ +#endif +#ifdef CYBSP_BT_UART_RTS +/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS + */ +#endif +#ifdef CYBSP_BT_UART_CTS +/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS + */ +#endif +#ifdef CYBSP_BT_POWER +/** Pin: BT Power \def CYBSP_BT_POWER + */ +#endif +#ifdef CYBSP_BT_HOST_WAKE +/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE + */ +/** BT host-wake GPIO drive mode */ +#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE) +/** BT host wake IRQ event */ +#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL) +#endif +#ifdef CYBSP_BT_DEVICE_WAKE +/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE + */ +/** BT device wakeup GPIO drive mode */ +#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG) +/** BT device wakeup polarity */ +#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u) +#endif +#ifdef CYBSP_PDM_CLK +/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK + */ +#endif +#ifdef CYBSP_PDM_DATA +/** Pin PDM PCM DATA \def CYBSP_PDM_DATA + */ +#endif +#ifdef CYBSP_I2S_MCLK +/** Pin: I2S MCLK \def CYBSP_I2S_MCLK + */ +#endif +#ifdef CYBSP_I2S_TX_SCK +/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK + */ +#endif +#ifdef CYBSP_I2S_TX_WS +/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS + */ +#endif +#ifdef CYBSP_I2S_TX_DATA +/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA + */ +#endif +#ifdef CYBSP_I2S_RX_SCK +/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK + */ +#endif +#ifdef CYBSP_I2S_RX_WS +/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS + */ +#endif +#ifdef CYBSP_I2S_RX_DATA +/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA + */ +#endif +#ifdef CYBSP_DEBUG_UART_RTS +/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS + */ +#endif +#ifdef CYBSP_DEBUG_UART_CTS +/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS + */ +#endif +#ifdef CYBSP_UART_RX +/** Pin: UART RX \def CYBSP_UART_RX + */ +#endif +#ifdef CYBSP_UART_TX +/** Pin: UART TX \def CYBSP_UART_TX + */ +#endif +#ifdef CYBSP_TDO_SWO +/** Pin: \def CYBSP_TDO_SWO + */ +#endif +#ifdef CYBSP_TMS_SWDIO +/** Pin: \def CYBSP_TMS_SWDIO + */ +#endif +#ifdef CYBSP_SWCLK +/** Pin: \def CYBSP_SWCLK + */ +#endif + +/** \} group_bsp_pins_comm */ +#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) + +#if defined(CYBSP_A0) +/** + * \addtogroup group_bsp_pins_arduino Arduino Header Pins + * \{ + * Pins mapped to the Arduino header on the board. + */ + +#ifdef CYBSP_A0 +/** Arduino A0 \def CYBSP_A0 + */ +#endif +#ifdef CYBSP_A1 +/** Arduino A1 \def CYBSP_A1 + */ +#endif +#ifdef CYBSP_A2 +/** Arduino A2 \def CYBSP_A2 + */ +#endif +#ifdef CYBSP_A3 +/** Arduino A3 \def CYBSP_A3 + */ +#endif +#ifdef CYBSP_A4 +/** Arduino A4 \def CYBSP_A4 + */ +#endif +#ifdef CYBSP_A5 +/** Arduino A5 \def CYBSP_A5 + */ +#endif +#ifdef CYBSP_D0 +/** Arduino D0 \def CYBSP_D0 + */ +#endif +#ifdef CYBSP_D1 +/** Arduino D1 \def CYBSP_D1 + */ +#endif +#ifdef CYBSP_D2 +/** Arduino D2 \def CYBSP_D2 + */ +#endif +#ifdef CYBSP_D3 +/** Arduino D3 \def CYBSP_D3 + */ +#endif +#ifdef CYBSP_D4 +/** Arduino D4 \def CYBSP_D4 + */ +#endif +#ifdef CYBSP_D5 +/** Arduino D5 \def CYBSP_D5 + */ +#endif +#ifdef CYBSP_D6 +/** Arduino D6 \def CYBSP_D6 + */ +#endif +#ifdef CYBSP_D7 +/** Arduino D7 \def CYBSP_D7 + */ +#endif +#ifdef CYBSP_D8 +/** Arduino D8 \def CYBSP_D8 + */ +#endif +#ifdef CYBSP_D9 +/** Arduino D9 \def CYBSP_D9 + */ +#endif +#ifdef CYBSP_D10 +/** Arduino D10 \def CYBSP_D10 + */ +#endif +#ifdef CYBSP_D11 +/** Arduino D11 \def CYBSP_D11 + */ +#endif +#ifdef CYBSP_D12 +/** Arduino D12 \def CYBSP_D12 + */ +#endif +#ifdef CYBSP_D13 +/** Arduino D13 \def CYBSP_D13 + */ +#endif +#ifdef CYBSP_D14 +/** Arduino D14 \def CYBSP_D14 + */ +#endif +#ifdef CYBSP_D15 +/** Arduino D15 \def CYBSP_D15 + */ +#endif + +/** \} group_bsp_pins_arduino */ +#endif // defined(CYBSP_A0) + +#if defined(CYBSP_J2_1) +/** + * \addtogroup group_bsp_pins_j2 J2 Header Pins + * \{ + * Pins mapped to the J2 header on the board. + */ + +#ifdef CYBSP_J2_1 +/** Infineon J2 Header pin 1 \def CYBSP_J2_1 + */ +#endif +#ifdef CYBSP_J2_2 +/** Infineon J2 Header pin 2 \def CYBSP_J2_2 + */ +#endif +#ifdef CYBSP_J2_3 +/** Infineon J2 Header pin 3 \def CYBSP_J2_3 + */ +#endif +#ifdef CYBSP_J2_4 +/** Infineon J2 Header pin 4 \def CYBSP_J2_4 + */ +#endif +#ifdef CYBSP_J2_5 +/** Infineon J2 Header pin 5 \def CYBSP_J2_5 + */ +#endif +#ifdef CYBSP_J2_7 +/** Infineon J2 Header pin 7 \def CYBSP_J2_7 + */ +#endif +#ifdef CYBSP_J2_8 +/** Infineon J2 Header pin 8 \def CYBSP_J2_8 + */ +#endif +#ifdef CYBSP_J2_9 +/** Infineon J2 Header pin 9 \def CYBSP_J2_9 + */ +#endif +#ifdef CYBSP_J2_10 +/** Infineon J2 Header pin 10 \def CYBSP_J2_10 + */ +#endif +#ifdef CYBSP_J2_11 +/** Infineon J2 Header pin 11 \def CYBSP_J2_11 + */ +#endif +#ifdef CYBSP_J2_12 +/** Infineon J2 Header pin 12 \def CYBSP_J2_12 + */ +#endif +#ifdef CYBSP_J2_13 +/** Infineon J2 Header pin 13 \def CYBSP_J2_13 + */ +#endif +#ifdef CYBSP_J2_15 +/** Infineon J2 Header pin 15 \def CYBSP_J2_15 + */ +#endif +#ifdef CYBSP_J2_16 +/** Infineon J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_16 +/** Infineon J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_6 +/** Infineon J2 Header pin 6 \def CYBSP_J2_6 + */ +#endif +#ifdef CYBSP_J2_17 +/** Infineon J2 Header pin 17 \def CYBSP_J2_17 + */ +#endif +#ifdef CYBSP_J2_18 +/** Infineon J2 Header pin 18 \def CYBSP_J2_18 + */ +#endif +#ifdef CYBSP_J2_19 +/** Infineon J2 Header pin 19 \def CYBSP_J2_19 + */ +#endif +#ifdef CYBSP_J2_20 +/** Infineon J2 Header pin 20 \def CYBSP_J2_20 + */ +#endif +#ifdef CYBSP_J2_14 +/** Infineon J2 Header pin 14 \def CYBSP_J2_14 + */ +#endif + +/** \} group_bsp_pins_j2 */ +#endif // defined(CYBSP_J2_1) + +#if defined(CYBSP_J6_1) +/** + * \addtogroup group_bsp_pins_j6 J6 Header Pins + * \{ + * Pins mapped to the J6 header on the board. + */ + +#ifdef CYBSP_J6_1 +/** Infineon J6 Header pin 1 \def CYBSP_J6_1 + */ +#endif +#ifdef CYBSP_J6_2 +/** Infineon J6 Header pin 2 \def CYBSP_J6_2 + */ +#endif +#ifdef CYBSP_J6_3 +/** Infineon J6 Header pin 3 \def CYBSP_J6_3 + */ +#endif +#ifdef CYBSP_J6_4 +/** Infineon J6 Header pin 4 \def CYBSP_J6_4 + */ +#endif +#ifdef CYBSP_J6_5 +/** Infineon J6 Header pin 5 \def CYBSP_J6_5 + */ +#endif +#ifdef CYBSP_J6_6 +/** Infineon J6 Header pin 6 \def CYBSP_J6_6 + */ +#endif +#ifdef CYBSP_J6_7 +/** Infineon J6 Header pin 7 \def CYBSP_J6_7 + */ +#endif +#ifdef CYBSP_J6_8 +/** Infineon J6 Header pin 8 \def CYBSP_J6_8 + */ +#endif +#ifdef CYBSP_J6_9 +/** Infineon J6 Header pin 9 \def CYBSP_J6_9 + */ +#endif +#ifdef CYBSP_J6_10 +/** Infineon J6 Header pin 10 \def CYBSP_J6_10 + */ +#endif +#ifdef CYBSP_J6_11 +/** Infineon J6 Header pin 11 \def CYBSP_J6_11 + */ +#endif +#ifdef CYBSP_J6_12 +/** Infineon J6 Header pin 12 \def CYBSP_J6_12 + */ +#endif +#ifdef CYBSP_J6_13 +/** Infineon J6 Header pin 13 \def CYBSP_J6_13 + */ +#endif +#ifdef CYBSP_J6_14 +/** Infineon J6 Header pin 14 \def CYBSP_J6_14 + */ +#endif +#ifdef CYBSP_J6_15 +/** Infineon J6 Header pin 15 \def CYBSP_J6_15 + */ +#endif +#ifdef CYBSP_J6_16 +/** Infineon J6 Header pin 16 \def CYBSP_J6_16 + */ +#endif + +/** \} group_bsp_pins_j6 */ +#endif // defined(CYBSP_J6_1) + +#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) +/** + * \addtogroup group_bsp_pins_capsense Capsense + * \{ + * Pins connected to CAPSENSEâ„¢ sensors on the board. + */ + +#ifdef CYBSP_CSD_TX +/** Pin: CapSesnse TX \def CYBSP_CSD_TX + */ +#endif +#ifdef CYBSP_CINA +/** Pin: CapSesnse CINA \def CYBSP_CINA + */ +#endif +#ifdef CYBSP_CINTA +/** Pin: CapSesnse CINTA \def CYBSP_CINTA + */ +#endif +#ifdef CYBSP_CINB +/** Pin: CapSesnse CINB \def CYBSP_CINB + */ +#endif +#ifdef CYBSP_CINTB +/** Pin: CapSesnse CINTB \def CYBSP_CINTB + */ +#endif +#ifdef CYBSP_CMOD +/** Pin: CapSesnse CMOD \def CYBSP_CMOD + */ +#endif +#ifdef CYBSP_CSD_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0 + */ +#endif +#ifdef CYBSP_CSD_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1 + */ +#endif +#ifdef CYBSP_CSD_SLD0 +/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0 + */ +#endif +#ifdef CYBSP_CSD_SLD1 +/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1 + */ +#endif +#ifdef CYBSP_CSD_SLD2 +/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2 + */ +#endif +#ifdef CYBSP_CSD_SLD3 +/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3 + */ +#endif +#ifdef CYBSP_CSD_SLD4 +/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4 + */ +#endif +#ifdef CYBSP_CSD_SLD5 +/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5 + */ +#endif +#ifdef CYBSP_CSX_BTN_TX +/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX + */ +#endif +#ifdef CYBSP_CSX_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0 + */ +#endif +#ifdef CYBSP_CSX_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1 + */ +#endif +#ifdef CYBSP_CSX_BTN2 +/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2 + */ +#endif + +/** \} group_bsp_pins_capsense */ +#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) + +#if defined(CYBSP_WCO_IN) +/** + * \addtogroup group_bsp_pins_wco WCO + * \{ + * Pins connected to the WCO on the board. + */ +#ifdef CYBSP_WCO_IN +/** Pin: WCO input \def CYBSP_WCO_IN + */ +#endif +#ifdef CYBSP_WCO_OUT +/** Pin: WCO output \def CYBSP_WCO_OUT + */ +#endif + +/** \} group_bsp_pins_wco */ +#endif // defined(CYBSP_WCO_IN) + +/** \} group_bsp_pins */ + +#if defined(__cplusplus) +} +#endif diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp_types.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp_types.h new file mode 100644 index 0000000000..41de9c7906 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/cybsp_types.h @@ -0,0 +1,63 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#pragma once + +#include "cybsp_doc.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * \cond INTERNAL + */ +/* WIFI interface types */ +#define CYBSP_SDIO_INTERFACE (0) +#define CYBSP_SPI_INTERFACE (1) +#define CYBSP_M2M_INTERFACE (2) +/** \endcond */ + +/** + * \addtogroup group_bsp_pin_state Pin States + * \{ + * Macros to abstract out whether the LEDs & Buttons are wired high or active low. + */ +/** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON +#define CYBSP_LED_STATE_ON (0U) +#endif +/** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF +#define CYBSP_LED_STATE_OFF (1U) +#endif +/** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED +#define CYBSP_BTN_PRESSED (0U) +#endif +/** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF +#define CYBSP_BTN_OFF (1U) +#endif +/** \} group_bsp_pin_state */ + +#if defined(__cplusplus) +} +#endif diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt new file mode 100644 index 0000000000..80bb73b4ec --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt @@ -0,0 +1,7 @@ +capsense +core-lib +core-make +mtb-hal-cat1 +mtb-pdl-cat1 +psoc6cm0p +recipe-make-cat1a diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt new file mode 100644 index 0000000000..80bb73b4ec --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt @@ -0,0 +1,7 @@ +capsense +core-lib +core-make +mtb-hal-cat1 +mtb-pdl-cat1 +psoc6cm0p +recipe-make-cat1a diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt new file mode 100644 index 0000000000..80bb73b4ec --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt @@ -0,0 +1,7 @@ +capsense +core-lib +core-make +mtb-hal-cat1 +mtb-pdl-cat1 +psoc6cm0p +recipe-make-cat1a diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/system_psoc6.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/system_psoc6.h new file mode 100644 index 0000000000..a864f14cea --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/system_psoc6.h @@ -0,0 +1,734 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.91 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode +* +* ARM Compiler\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.sct', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00002000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00002000 +* \endcode +* - 'xx_cm4_dual.sct', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode +* +* \note Correct operation of malloc and related functions depends on the working +* implementation of the 'sbrk' function. Newlib-nano (default C runtime library +* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that +* doesn't check for heap and stack collisions during excessive memory allocations. +* To ensure the heap always remains within the range defined by __HeapBase and +* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: +* \snippet startup/snippet/main.c snippet_sbrk +* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include +* clib-support library that provides newlib-compatible implementations of +* 'sbrk', '__malloc_lock' and '__malloc_unlock': +*
+* https://github.com/cypresssemiconductorco/clib-support. +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler +* - Editing source code files\n +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.91Updated memory configuration for PSoC 64 devices.Flash and RAM memory allocation updated.
Added cys06xxa_cm4 linker scripts.New device support.
2.90.1Updated \ref group_system_config_heap_stack_config_gcc section with the note +* on the dynamic memory allocation for ARM GCC.Documentation update.
Updated system_psoc6.h to include custom CY_SYSTEM_PSOC6_CONFIG passed as compiler macro.Improve configuration flexibility.
Updated attribute usage for the linker section placement in CM0+ startup codeEnhancement based on usability feedback.
Renamed the '.cy_xip' linker script region as 'cy_xip'Enable access to the XIP region start/end addresses from the C code.
2.90Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.Flash allocation adjustment.
2.80Updated linker scripts for PSoC 64 Secure MCU devices.Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates +* in accordance with the PSoC 64 Secure Boot SDK policies.
Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.Provided support for SysPM driver updates.
Updated the linker scripts.Reserved FLASH area for the MCU boot headers.
Added System Pipe initialization for all devices. Improved PDL usability according to user experience.
Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. Defect fixing.
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +/* + * Include optional application-specific configuration header. + * + * For example, custom system_psoc6_config.h can be included here + * by adding the below macro definition to the build system: + * DEFINES+=CY_SYSTEM_PSOC6_CONFIG='"system_psoc6_config.h"' + */ +#if defined(CY_SYSTEM_PSOC6_CONFIG) +#include CY_SYSTEM_PSOC6_CONFIG +#endif + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +#if defined(__ARMCC_VERSION) + extern void SystemInit(void) __attribute__((constructor)); +#else + extern void SystemInit(void); +#endif /* (__ARMCC_VERSION) */ + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macros. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/version.xml b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/version.xml new file mode 100644 index 0000000000..d518882cd3 --- /dev/null +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/version.xml @@ -0,0 +1 @@ +3.1.0.27308 diff --git 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+ libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_connectivity_bt.c + cycfg_connectivity_bt.c + 0 + 0 + + + 10 + 97 + 1 + 0 + 0 + 0 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_system.c + cycfg_system.c + 0 + 0 + + + 10 + 98 + 1 + 0 + 0 + 0 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c + system_psoc6_cm4.c + 0 + 0 + + + 10 + 99 + 1 + 0 + 0 + 0 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg.c + cycfg.c + 0 + 0 + + + 10 + 100 + 1 + 0 + 0 + 0 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_peripherals.c + cycfg_peripherals.c + 0 + 0 + + + 10 + 101 + 1 + 0 + 0 + 0 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_capsense.c + cycfg_capsense.c + 0 + 0 + + + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx index 863895e5c7..6303c1c1fc 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +

### uVision Project, (C) Keil Software
+ rtthread @@ -16,28 +19,28 @@ Cypress.PSoC6_DFP.1.2.0 https://github.com/cypresssemiconductorco/cmsis-packs/raw/master/PSoC6_DFP/ IRAM(0x08000000,0x100000) IROM(0x10000000,0x200000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD08026400 -FC8000 -FN5 -FF0CY8C6xxA_SFLASH_TOC2 -FS016007C00 -FL0400 -FF1CY8C6xxA_SFLASH_PKEY -FS116005A00 -FL1C00 -FF2CY8C6xxA_SFLASH_USER -FS216000800 -FL2800 -FF3CY8C6xxA_WFLASH -FS314000000 -FL38000 -FF4CY8C6xxA_sect256KB -FS410000000 -FL4200000 -FP0($$Device:CY8C624ABZI-S2D44$Flash\CY8C6xxA_SFLASH_TOC2.FLM) -FP1($$Device:CY8C624ABZI-S2D44$Flash\CY8C6xxA_SFLASH_PKEY.FLM) -FP2($$Device:CY8C624ABZI-S2D44$Flash\CY8C6xxA_SFLASH_USER.FLM) -FP3($$Device:CY8C624ABZI-S2D44$Flash\CY8C6xxA_WFLASH.FLM) -FP4($$Device:CY8C624ABZI-S2D44$Flash\CY8C6xxA_sect256KB.FLM)) 0 - - - - - - - - - - + + + + + + + + + + $$Device:CY8C624ABZI-S2D44$SVD\psoc6_02.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -101,8 +104,8 @@ 0 0 3 - - + + 1 @@ -136,10 +139,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -306,7 +309,7 @@ 0x0 - + 1 @@ -333,10 +336,10 @@ 0 0 - - CY_USING_HAL, __STDC_LIMIT_MACROS, COMPONENT_CAT1A, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARM_LIBC, IFX_PSOC6_43012, __RTTHREAD__, COMPONENT_CAT1, COMPONENT_BSP_DESIGN_MODUS, CY8C624ABZI_S2D44 - - applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\IFX_PSOC6_HAL\capsense;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;..\libraries\IFX_PSOC6_HAL\retarget-io;..\libraries\IFX_PSOC6_HAL\core-lib\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\serial-flash;..\libraries\IFX_PSOC6_HAL\mtb_shared\usbdev;..\libraries\IFX_PSOC6_HAL\mtb_shared\csdidac;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012;..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc + + CY_USING_HAL, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, COMPONENT_CAT1A, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, COMPONENT_BSP_DESIGN_MODUS, IFX_PSOC6_43012, __RTTHREAD__, COMPONENT_CAT1, CY8C624ABZI_S2D44 + + ..\..\..\components\finsh;board\ports;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;..\..\..\components\utilities\libadt;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers;libs\TARGET_CY8CKIT-062S2-43012;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;..\..\..\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\..\..\components\libc\posix\io\poll;..\libraries\IFX_PSOC6_HAL\core-lib\include;libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\libraries\IFX_PSOC6_HAL\capsense;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;..\..\..\libcpu\arm\common;board;..\libraries\IFX_PSOC6_HAL\retarget-io;..\..\..\components\libc\posix\io\stdio;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\libraries\IFX_PSOC6_HAL\mtb_shared\serial-flash;..\libraries\HAL_Drivers\config;..\libraries\IFX_PSOC6_HAL\mtb_shared\usbdev;.;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\csdidac;applications;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include @@ -351,10 +354,10 @@ 0 3 - - - - + + + + @@ -366,17 +369,27 @@ 0 0x10000000 0x08000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + + + ADT + + + avl.c + 1 + ..\..\..\components\utilities\libadt\avl.c + + + Applications @@ -395,50 +408,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdio.c 1 ..\..\..\components\libc\compilers\common\cstdio.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cwchar.c 1 @@ -454,29 +453,21 @@ 1 ..\..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - - cpuport.c 1 @@ -492,57 +483,46 @@ 1 ..\..\..\components\drivers\ipc\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c - - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - + + rt_drv_pwm.c + 1 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + serial.c 1 @@ -552,42 +532,32 @@ Drivers - - - startup_psoc6_02_cm4.S - 2 - ..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S - - cy_syslib_mdk.S 2 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\TOOLCHAIN_ARM\cy_syslib_mdk.S - - board.c 1 board\board.c - - drv_common.c 1 ..\libraries\HAL_Drivers\drv_common.c - - drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c - - + + drv_pwm.c + 1 + ..\libraries\HAL_Drivers\drv_pwm.c + drv_uart.c 1 @@ -603,22 +573,16 @@ 1 ..\..\..\components\finsh\shell.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - cmd.c 1 @@ -634,85 +598,61 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - device.c 1 ..\..\..\src\device.c - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - mempool.c 1 ..\..\..\src\mempool.c - - object.c 1 ..\..\..\src\object.c - - scheduler.c 1 ..\..\..\src\scheduler.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -722,321 +662,287 @@ Libraries - - - psoc6_03_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - - cy_sysint.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c - - cyhal_triggers_psoc6_02.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\source\triggers\cyhal_triggers_psoc6_02.c - - cy_retarget_io.c 1 ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c - - cy_scb_i2c.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_i2c.c - - cy_gpio.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_gpio.c - - cyhal_scb_common.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_scb_common.c - - - - system_psoc6_cm4.c - 1 - ..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c - - - cyhal_clock.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_clock.c - - - - cy_scb_uart.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c - - - cyhal_psoc6_02_124_bga.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\source\pin_packages\cyhal_psoc6_02_124_bga.c - - - cybsp.c + cy_scb_uart.c 1 - ..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\cybsp.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c - - cy_scb_common.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_common.c - - cy_prot.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_prot.c - - cyhal_gpio.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_gpio.c - - cyhal_system.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_system.c - - cy_ipc_sema.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c - - + + psoc6_01_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c + cyhal_utils_psoc.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils_psoc.c - - + + psoc6_03_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + cyhal_utils.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c - - + + cy_tcpwm_counter.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_tcpwm_counter.c + + + cyhal_pwm.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_pwm.c + cy_ipc_drv.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c - - cyhal_hwmgr.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_hwmgr.c - - cy_syslib.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c - - - - cycfg_system.c - 1 - ..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_system.c - - - - - cycfg_peripherals.c - 1 - ..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_peripherals.c - - - - - cy_syspm.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c - - - - - cyhal_lptimer.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c - - - - - cyhal_irq_psoc.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_irq_psoc.c - - - - - cy_mcwdt.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_mcwdt.c - - - - - cy_sysclk.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysclk.c - - - - - cyhal_syspm.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c - - - - - psoc6_04_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - - - - - cycfg_pins.c - 1 - ..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c - - - - - cyhal_uart.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_uart.c - - - - - cy_systick.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c - - - - - cycfg.c - 1 - ..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg.c - - - - - cyhal_interconnect.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_interconnect.c - - - - - cy_trigmux.c - 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_trigmux.c - - - psoc6_02_cm0p_sleep.c 1 ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c - - + + cy_syspm.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c + + + cyhal_lptimer.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c + + + cy_tcpwm_pwm.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_tcpwm_pwm.c + + + cyhal_irq_psoc.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_irq_psoc.c + + + cy_mcwdt.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_mcwdt.c + + + cy_sysclk.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysclk.c + + + psoc6_04_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + + + cyhal_syspm.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c + + + cyhal_uart.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_uart.c + + + cyhal_timer.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_timer.c + + + cy_systick.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c + + + cyhal_interconnect.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_interconnect.c + + + cy_trigmux.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_trigmux.c + cy_device.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c - - - - cycfg_routing.c - 1 - ..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c - - - - - lib_cy_capsense.lib - 4 - ..\libraries\IFX_PSOC6_HAL\lib\cy_capsense.lib - - - - - cycfg_clocks.c - 1 - ..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c - - - cy_ipc_pipe.c 1 ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_pipe.c + + cyhal_tcpwm_common.c + 1 + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_tcpwm_common.c + + + + libs - psoc6_01_cm0p_sleep.c + cycfg_dmas.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_dmas.c + + + cycfg_routing.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c + + + cybsp.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\cybsp.c + + + cycfg_qspi_memslot.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_qspi_memslot.c + + + cycfg_pins.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c + + + cycfg_clocks.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c + + + startup_psoc6_02_cm4.S + 2 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S + + + cycfg_connectivity_bt.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_connectivity_bt.c + + + cycfg_system.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_system.c + + + system_psoc6_cm4.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c + + + cycfg.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg.c + + + cycfg_peripherals.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_peripherals.c + + + cycfg_capsense.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_capsense.c + - - - + + + + diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig.h b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig.h index f708915474..c073228c56 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig.h +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig.h @@ -36,6 +36,7 @@ /* Memory Management */ +#define RT_PAGE_MAX_ORDER 11 #define RT_USING_MEMPOOL #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP @@ -47,9 +48,9 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart5" -#define RT_VER_NUM 0x40101 -#define ARCH_ARM +#define RT_VER_NUM 0x50000 #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 @@ -76,6 +77,7 @@ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA @@ -181,20 +183,26 @@ /* entertainment: terminal games and other interesting software packages */ -/* Privated Packages of RealThread */ +/* Arduino libraries */ -/* Network Utilities */ +/* Sensor libraries */ -/* RT-Thread Smart */ +/* Display libraries */ + + +/* Timing libraries */ + + +/* Project libraries */ #define SOC_FAMILY_IFX -#define SOC_SERIES_IFX_PSOC6 +#define SOC_SERIES_IFX_PSOC62 /* Hardware Drivers Config */ -#define SOC_IFX_PSOC6_43012 +#define SOC_CY8C624ABZI_S2D44 /* Onboard Peripheral Drivers */ diff --git a/bsp/renesas/ra6m3-ek/.settings/standalone.prefs b/bsp/renesas/ra6m3-ek/.settings/standalone.prefs index c3d6bc3dc2..6d8f324b22 100644 --- a/bsp/renesas/ra6m3-ek/.settings/standalone.prefs +++ b/bsp/renesas/ra6m3-ek/.settings/standalone.prefs @@ -1,19 +1,21 @@ -#Fri Nov 18 18:05:07 CST 2022 +#Wed Jan 11 18:29:06 CST 2023 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/libraries= com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/all=3427620923,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|143358381,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|2743353138,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|546480625,ra/fsp/inc/fsp_common_api.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|1728953905,ra/fsp/inc/fsp_features.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2425160085,ra/fsp/inc/api/bsp_api.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2208590403,ra/fsp/inc/instances/r_ioport.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3297195641,ra/fsp/inc/fsp_version.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_phy\#\#\#\#3.5.0/all=180607401,ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c|809828733,ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c|1059783364,ra/fsp/inc/instances/r_ether_phy.h|2050444946,ra/fsp/inc/api/r_ether_phy_api.h|451576276,ra/fsp/src/r_ether_phy/r_ether_phy.c|4014538643,ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/all=143358381,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|2743353138,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h|3427620923,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_phy\#\#\#\#3.5.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2425160085,ra/fsp/inc/api/bsp_api.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1728953905,ra/fsp/inc/fsp_features.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|546480625,ra/fsp/inc/fsp_common_api.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2208590403,ra/fsp/inc/instances/r_ioport.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3297195641,ra/fsp/inc/fsp_version.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries= -com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=PinConfiguration -com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h +com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/all= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFC\#\#3.5.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=3254285722,ra/fsp/src/r_ioport/r_ioport.c|2208590403,ra/fsp/inc/instances/r_ioport.h|1939984091,ra/fsp/inc/api/r_ioport_api.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|3916852077,ra/fsp/inc/api/r_uart_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|3916852077,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.136564520=false com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries= diff --git a/bsp/renesas/ra6m3-ek/configuration.xml b/bsp/renesas/ra6m3-ek/configuration.xml index 02c41c61b6..2e272e626c 100644 --- a/bsp/renesas/ra6m3-ek/configuration.xml +++ b/bsp/renesas/ra6m3-ek/configuration.xml @@ -165,6 +165,10 @@ SCI UART Renesas.RA.3.5.0.pack + + Ethernet PHY + Renesas.RA.3.5.0.pack + @@ -203,13 +207,28 @@ + + + + + + + + + + + + + + + @@ -224,6 +243,18 @@ + + + + + + + + + + + + @@ -232,13 +263,43 @@ - + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + diff --git a/bsp/renesas/ra6m3-ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/bsp/renesas/ra6m3-ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index c098985d51..48c4b5099e 100644 --- a/bsp/renesas/ra6m3-ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/bsp/renesas/ra6m3-ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -20,7 +20,7 @@ #endif #define BSP_CFG_MCU_VCC_MV (3300) #define BSP_CFG_STACK_MAIN_BYTES (0x400) - #define BSP_CFG_HEAP_BYTES (0x2000) + #define BSP_CFG_HEAP_BYTES (0) #define BSP_CFG_PARAM_CHECKING_ENABLE (0) #define BSP_CFG_ASSERT (0) #define BSP_CFG_ERROR_LOG (0) diff --git a/bsp/renesas/ra6m3-ek/ra_gen/hal_data.c b/bsp/renesas/ra6m3-ek/ra_gen/hal_data.c index 80213f8e49..566df6f202 100644 --- a/bsp/renesas/ra6m3-ek/ra_gen/hal_data.c +++ b/bsp/renesas/ra6m3-ek/ra_gen/hal_data.c @@ -1,5 +1,27 @@ /* generated HAL source file - do not edit */ #include "hal_data.h" +ether_phy_instance_ctrl_t g_ether_phy0_ctrl; + +const ether_phy_cfg_t g_ether_phy0_cfg = +{ + + .channel = 0, + .phy_lsi_address = 0, + .phy_reset_wait_time = 0x00020000, + .mii_bit_access_wait_time = 8, + .flow_control = ETHER_PHY_FLOW_CONTROL_DISABLE, + .mii_type = ETHER_PHY_MII_TYPE_RMII, + .p_context = NULL, + .p_extend = NULL, + +}; +/* Instance structure to use this module. */ +const ether_phy_instance_t g_ether_phy0 = +{ + .p_ctrl = &g_ether_phy0_ctrl, + .p_cfg = &g_ether_phy0_cfg, + .p_api = &g_ether_phy_on_ether_phy +}; sci_uart_instance_ctrl_t g_uart7_ctrl; baud_setting_t g_uart7_baud_setting = diff --git a/bsp/renesas/ra6m3-ek/ra_gen/hal_data.h b/bsp/renesas/ra6m3-ek/ra_gen/hal_data.h index 317acda1c4..e1e94ea2ce 100644 --- a/bsp/renesas/ra6m3-ek/ra_gen/hal_data.h +++ b/bsp/renesas/ra6m3-ek/ra_gen/hal_data.h @@ -4,9 +4,17 @@ #include #include "bsp_api.h" #include "common_data.h" +#include "r_ether_phy.h" +#include "r_ether_phy_api.h" #include "r_sci_uart.h" #include "r_uart_api.h" FSP_HEADER +/** ether_phy on ether_phy Instance. */ +extern const ether_phy_instance_t g_ether_phy0; + +/** Access the Ethernet PHY instance using these structures when calling API functions directly (::p_api is not used). */ +extern ether_phy_instance_ctrl_t g_ether_phy0_ctrl; +extern const ether_phy_cfg_t g_ether_phy0_cfg; /** UART on SCI Instance. */ extern const uart_instance_t g_uart7; diff --git a/bsp/renesas/ra6m3-ek/ra_gen/pin_data.c b/bsp/renesas/ra6m3-ek/ra_gen/pin_data.c index 9986dea419..2233b756ff 100644 --- a/bsp/renesas/ra6m3-ek/ra_gen/pin_data.c +++ b/bsp/renesas/ra6m3-ek/ra_gen/pin_data.c @@ -22,12 +22,52 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { }, { .pin = BSP_IO_PORT_04_PIN_01, - .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_06_PIN_13, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { + .pin = BSP_IO_PORT_06_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_07_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, }; const ioport_cfg_t g_bsp_pin_cfg = {