From 7a853ccd0df479578af22bfa8972d5b39fa4c5d0 Mon Sep 17 00:00:00 2001 From: liminghui12 <2923282118@qq.com> Date: Thu, 28 Nov 2024 13:22:48 +0800 Subject: [PATCH] =?UTF-8?q?renesas=20R9A07G0=20PWM=E6=A1=86=E6=9E=B6=20GPT?= =?UTF-8?q?=E6=97=B6=E9=92=9F=E4=BF=AE=E6=94=B9=E4=B8=BA=20FSP=5FPRIV=5FCL?= =?UTF-8?q?OCK=5FPCLKGPTL?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/renesas/libraries/HAL_Drivers/drv_pwm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_pwm.c b/bsp/renesas/libraries/HAL_Drivers/drv_pwm.c index 60f91a0ca9..5c2fd8a36c 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_pwm.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_pwm.c @@ -53,11 +53,16 @@ static struct ra_pwm ra6m4_pwm_obj[BSP_PWMS_NUM] = #endif }; +#ifdef SOC_SERIES_R9A07G0 + #define FSP_PRIV_CLOCK FSP_PRIV_CLOCK_PCLKGPTL +#else + #define FSP_PRIV_CLOCK FSP_PRIV_CLOCK_PCLKD +#endif /* Convert the raw PWM period counts into ns */ static rt_uint32_t _convert_counts_ns(uint32_t source_div, uint32_t raw) { - uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div; + uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK) >> source_div; uint32_t ns = (uint32_t)(((uint64_t)raw * 1000000000ULL) / pclkd_freq_hz); return ns; } @@ -65,7 +70,7 @@ static rt_uint32_t _convert_counts_ns(uint32_t source_div, uint32_t raw) /* Convert ns into raw PWM period counts */ static rt_uint32_t _convert_ns_counts(uint32_t source_div, uint32_t raw) { - uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div; + uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK) >> source_div; uint32_t counts = (uint32_t)(((uint64_t)raw * (uint64_t)pclkd_freq_hz) / 1000000000ULL); return counts; }