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renesas R9A07G0 PWM框架 GPT时钟修改为 FSP_PRIV_CLOCK_PCLKGPTL

This commit is contained in:
liminghui12 2024-11-28 13:22:48 +08:00
parent e5bc2dbdc6
commit 7a853ccd0d
1 changed files with 7 additions and 2 deletions
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9
bsp/renesas/libraries/HAL_Drivers/drv_pwm.c
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@ -53,11 +53,16 @@ static struct ra_pwm ra6m4_pwm_obj[BSP_PWMS_NUM] =
#endif
};
#ifdef SOC_SERIES_R9A07G0
#define FSP_PRIV_CLOCK FSP_PRIV_CLOCK_PCLKGPTL
#else
#define FSP_PRIV_CLOCK FSP_PRIV_CLOCK_PCLKD
#endif
/* Convert the raw PWM period counts into ns */
static rt_uint32_t _convert_counts_ns(uint32_t source_div, uint32_t raw)
{
uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK) >> source_div;
uint32_t ns = (uint32_t)(((uint64_t)raw * 1000000000ULL) / pclkd_freq_hz);
return ns;
}
@ -65,7 +70,7 @@ static rt_uint32_t _convert_counts_ns(uint32_t source_div, uint32_t raw)
/* Convert ns into raw PWM period counts */
static rt_uint32_t _convert_ns_counts(uint32_t source_div, uint32_t raw)
{
uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK) >> source_div;
uint32_t counts = (uint32_t)(((uint64_t)raw * (uint64_t)pclkd_freq_hz) / 1000000000ULL);
return counts;
}