diff --git a/bsp/renesas/rzn2l_rsk/.cproject b/bsp/renesas/rzn2l_rsk/.cproject new file mode 100644 index 0000000000..e5c18fc2dd --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.cproject @@ -0,0 +1,221 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/rzn2l_rsk/.project b/bsp/renesas/rzn2l_rsk/.project new file mode 100644 index 0000000000..a96db4e220 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.project @@ -0,0 +1,28 @@ + + + hh + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + diff --git a/bsp/renesas/rzn2l_rsk/.settings/hh.JLink.Debug.rttlaunch b/bsp/renesas/rzn2l_rsk/.settings/hh.JLink.Debug.rttlaunch new file mode 100644 index 0000000000..618eadd9b7 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.settings/hh.JLink.Debug.rttlaunch @@ -0,0 +1,94 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/rzn2l_rsk/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs b/bsp/renesas/rzn2l_rsk/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs new file mode 100644 index 0000000000..7dbfc8a7d9 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin diff --git a/bsp/renesas/rzn2l_rsk/.settings/language.settings.xml b/bsp/renesas/rzn2l_rsk/.settings/language.settings.xml new file mode 100644 index 0000000000..67360abb07 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/bsp/renesas/rzn2l_rsk/.settings/local_temp_storage.prefs b/bsp/renesas/rzn2l_rsk/.settings/local_temp_storage.prefs new file mode 100644 index 0000000000..6c3ab86d84 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.settings/local_temp_storage.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +temp.toolchain.exec.path=D\:\\manufacture_apps\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\ARM\\GNU_Tools_for_ARM_Embedded_Processors\\10.2.1/bin diff --git a/bsp/renesas/rzn2l_rsk/.settings/org.eclipse.core.runtime.prefs b/bsp/renesas/rzn2l_rsk/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 0000000000..9f1acfcfba --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/bsp/renesas/rzn2l_rsk/.settings/projcfg.ini b/bsp/renesas/rzn2l_rsk/.settings/projcfg.ini new file mode 100644 index 0000000000..f8e9f80e4a --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.settings/projcfg.ini @@ -0,0 +1,19 @@ +#RT-Thread Studio Project Configuration +#Thu Nov 28 18:09:09 CST 2024 +cfg_version=v3.0 +board_name=rzn2l_rsk +example_name= +hardware_adapter=J-Link +board_base_nano_proj=false +project_type=rt-thread +chip_name=R9A07G084 +selected_rtt_version=latest +bsp_version=1.0.0 +os_branch=master +project_base_rtt_bsp=true +output_project_path=D\:\\manufacture_apps\\RT-ThreadStudio\\repo\\Local\\Board_Support_Packages\\Renesas\\EtherKit\\1.0.0\\projects +is_base_example_project=false +is_use_scons_build=true +project_name=etherkit_blink_led +os_version=latest +bsp_path= diff --git a/bsp/renesas/rzn2l_rsk/.settings/project.JLink.Debug.rttlaunch b/bsp/renesas/rzn2l_rsk/.settings/project.JLink.Debug.rttlaunch new file mode 100644 index 0000000000..db20f2562b --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.settings/project.JLink.Debug.rttlaunch @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/rzn2l_rsk/.settings/standalone.prefs b/bsp/renesas/rzn2l_rsk/.settings/standalone.prefs index 5e6ead989e..1f9ccf199a 100644 --- a/bsp/renesas/rzn2l_rsk/.settings/standalone.prefs +++ b/bsp/renesas/rzn2l_rsk/.settings/standalone.prefs @@ -1,24 +1,26 @@ -#Sat Sep 14 16:03:03 CST 2024 -com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp_xspi0_boot.icf +#Wed Nov 27 16:37:16 CST 2024 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.1.fsp.2.0.0/all=1441545198,rzn/arm/CMSIS_5/LICENSE.txt|4247764709,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h|1135074086,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h|510668081,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h|4245531541,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h|1887099957,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h|3334069041,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/all= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/all=907937621,script/fsp_xspi0_boot.icf|3822962514,rzn/board/rzn2l_rsk/board_leds.c|358444977,rzn/board/rzn2l_rsk/board_init.c|2067006575,rzn/board/rzn2l_rsk/board.h|736691883,rzn/board/rzn2l_rsk/board_ethernet_phy.h|1631979823,rzn/board/rzn2l_rsk/board_leds.h|1430483072,rzn/board/rzn2l_rsk/board_init.h com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.0.0/libraries= com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.86814920=false -com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.0.0/all=908052335,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3563504244,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|870156648,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c|368480523,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c|3243637314,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1280798555,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3352808441,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h|1310386533,rzn/fsp/src/bsp/mcu/all/bsp_io.h|3643995939,rzn/fsp/src/bsp/mcu/all/bsp_cache.h|1033616941,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h|1572168446,rzn/fsp/src/bsp/mcu/all/bsp_io.c|3001342594,rzn/fsp/src/bsp/mcu/all/bsp_common.h|263477342,rzn/fsp/src/bsp/mcu/all/bsp_reset.h|2534029381,rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h|4193244082,rzn/fsp/src/bsp/mcu/all/bsp_irq.h|2136575248,rzn/fsp/src/bsp/mcu/all/bsp_tfu.h|2170977041,rzn/fsp/src/bsp/mcu/all/bsp_delay.c|526389185,rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h|8162287,rzn/fsp/src/bsp/mcu/all/bsp_clocks.h|3045644015,rzn/fsp/src/bsp/mcu/all/bsp_common.c|1908923075,rzn/fsp/src/bsp/mcu/all/bsp_clocks.c|1289851302,rzn/fsp/src/bsp/mcu/all/bsp_irq.c|358242822,rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c|2321472163,rzn/fsp/src/bsp/mcu/all/bsp_cache.c|225356254,rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h|2518644892,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c|392613868,rzn/fsp/src/bsp/mcu/all/bsp_reset.c|2238656401,rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1611830052,rzn/fsp/src/bsp/mcu/all/bsp_delay.h|2060190483,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h|1543064539,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h|3717942516,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c|3396795463,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c|2195931215,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c|1126344352,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h|1926319940,rzn/fsp/inc/fsp_features.h|2508067197,rzn/fsp/inc/fsp_version.h|3571247719,rzn/fsp/inc/fsp_common_api.h|3347087544,rzn/fsp/inc/instances/r_ioport.h|1765016794,rzn/fsp/inc/api/bsp_api.h|250199021,rzn/fsp/inc/api/r_ioport_api.h -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.0.0/libraries= com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=false com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.0.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.0.0/all= com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.1.fsp.2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_rtc\#\#\#\#2.0.0/all=3551601681,rzn/fsp/src/r_rtc/r_rtc.c|3948337697,rzn/fsp/inc/instances/r_rtc.h|3795688877,rzn/fsp/inc/api/r_rtc_api.h +com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp_xspi0_boot.icf +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.1.fsp.2.0.0/all=1441545198,rzn/arm/CMSIS_5/LICENSE.txt|4247764709,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h|1135074086,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h|510668081,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h|4245531541,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h|1887099957,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h|3334069041,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/all= +com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/all=2921827146,rzn/fsp/src/r_sci_uart/r_sci_uart.c|4093801030,rzn/fsp/inc/instances/r_sci_uart.h|1119704027,rzn/fsp/inc/api/r_uart_api.h|3586794436,rzn/fsp/inc/api/r_transfer_api.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.0.0/all=3243637314,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_rtc\#\#\#\#2.0.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.0.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.0.0/all=2989202485,rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c|1967641730,rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h|1508541487,rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h|1088535767,rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c|1458388275,rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h|617637586,rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.0.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.0.0/all=615913359,rzn/fsp/src/r_ioport/r_ioport.c|3347087544,rzn/fsp/inc/instances/r_ioport.h|250199021,rzn/fsp/inc/api/r_ioport_api.h diff --git a/bsp/renesas/rzn2l_rsk/SConscript b/bsp/renesas/rzn2l_rsk/SConscript index 889ba12c85..db0ef9c0cb 100644 --- a/bsp/renesas/rzn2l_rsk/SConscript +++ b/bsp/renesas/rzn2l_rsk/SConscript @@ -17,8 +17,7 @@ elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): if GetOption('target') != 'mdk5': CPPPATH = [cwd] src = Glob('./src/*.c') - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) for d in list: path = os.path.join(cwd, d) diff --git a/bsp/renesas/rzn2l_rsk/board/board.h b/bsp/renesas/rzn2l_rsk/board/board.h index cf53068064..baa0abb1c4 100644 --- a/bsp/renesas/rzn2l_rsk/board/board.h +++ b/bsp/renesas/rzn2l_rsk/board/board.h @@ -19,7 +19,7 @@ extern "C" { #include #include -#define RZ_SRAM_SIZE 512 /* The SRAM size of the chip needs to be modified */ +#define RZ_SRAM_SIZE 1536 /* The SRAM size of the chip needs to be modified */ #define RZ_SRAM_END (0x10000000 + RZ_SRAM_SIZE * 1024 - 1) #ifdef __ARMCC_VERSION @@ -29,7 +29,8 @@ extern int Image$$RAM_END$$ZI$$Base; #pragma section="CSTACK" #define HEAP_BEGIN (__segment_end("CSTACK")) #else -#define HEAP_BEGIN (0x10000000) +extern int __bss_end__; +#define HEAP_BEGIN ((void *)&__bss_end__) #endif #define HEAP_END RZ_SRAM_END @@ -37,7 +38,7 @@ extern int Image$$RAM_END$$ZI$$Base; /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define MAX_HANDLERS (512) +#define MAX_HANDLERS BSP_VECTOR_TABLE_MAX_ENTRIES #define GIC_IRQ_START 0 #define GIC_ACK_INTID_MASK (0x000003FFU) /* number of interrupts on board */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/SConscript b/bsp/renesas/rzn2l_rsk/rzn/SConscript index 41038bee62..4ff6ec8599 100644 --- a/bsp/renesas/rzn2l_rsk/rzn/SConscript +++ b/bsp/renesas/rzn2l_rsk/rzn/SConscript @@ -12,13 +12,12 @@ if rtconfig.PLATFORM in ['iccarm']: Return('group') elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): if GetOption('target') != 'mdk5': - src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c') - src += Glob(cwd + '/fsp/src/bsp/mcu/all/cr/*.c') - src += Glob(cwd + '/fsp/src/bsp/mcu/r*/*.c') - src += Glob(cwd + '/fsp/src/r_*/*.c') - src += Glob(cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/*.c') - src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c'] - src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c'] + src += Glob('./fsp/src/bsp/mcu/all/*.c') + src += Glob('./fsp/src/bsp/mcu/all/cr/*.c') + src += Glob('./fsp/src/bsp/mcu/r*/*.c') + src += Glob('./fsp/src/bsp/cmsis/Device/RENESAS/Source/*.c') + src += Glob('./fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/*.c') + src += Glob('./fsp/src/r_*/*.c') CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core_R/Include', cwd + '/fsp/inc', cwd + '/fsp/inc/api', diff --git a/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.icf b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.icf index 2f14001fa0..03db352850 100644 --- a/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.icf +++ b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.icf @@ -1,684 +1,684 @@ -include "memory_regions.icf"; - -/* The memory information for each device is done in memory regions file. - * The starting address and length of memory not defined in memory regions file are defined as 0. */ - -if (isdefinedsymbol(ATCM_START)) -{ - define symbol ATCM_PRV_START = ATCM_START; -} -else -{ - define symbol ATCM_PRV_START = 0; -} - -if (isdefinedsymbol(ATCM_LENGTH)) -{ - define symbol ATCM_PRV_LENGTH = ATCM_LENGTH; -} -else -{ - define symbol ATCM_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(BTCM_START)) -{ - define symbol BTCM_PRV_START = BTCM_START; -} -else -{ - define symbol BTCM_PRV_START = 0; -} - -if (isdefinedsymbol(BTCM_LENGTH)) -{ - define symbol BTCM_PRV_LENGTH = BTCM_LENGTH; -} -else -{ - define symbol BTCM_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(SYSTEM_RAM_START)) -{ - define symbol SYSTEM_RAM_PRV_START = SYSTEM_RAM_START; -} -else -{ - define symbol SYSTEM_RAM_PRV_START = 0; -} - -if (isdefinedsymbol(SYSTEM_RAM_LENGTH)) -{ - define symbol SYSTEM_RAM_PRV_LENGTH = SYSTEM_RAM_LENGTH; -} -else -{ - define symbol SYSTEM_RAM_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(SYSTEM_RAM_MIRROR_START)) -{ - define symbol SYSTEM_RAM_MIRROR_PRV_START = SYSTEM_RAM_MIRROR_START; -} -else -{ - define symbol SYSTEM_RAM_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(SYSTEM_RAM_MIRROR_LENGTH)) -{ - define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = SYSTEM_RAM_MIRROR_LENGTH; -} -else -{ - define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_START)) -{ - define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = xSPI0_CS0_SPACE_MIRROR_START; -} -else -{ - define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_LENGTH)) -{ - define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS0_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_START)) -{ - define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = xSPI0_CS1_SPACE_MIRROR_START; -} -else -{ - define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_LENGTH)) -{ - define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS1_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_START)) -{ - define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = xSPI1_CS0_SPACE_MIRROR_START; -} -else -{ - define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_LENGTH)) -{ - define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS0_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_START)) -{ - define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = xSPI1_CS1_SPACE_MIRROR_START; -} -else -{ - define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_LENGTH)) -{ - define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS1_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS0_SPACE_MIRROR_START)) -{ - define symbol CS0_SPACE_MIRROR_PRV_START = CS0_SPACE_MIRROR_START; -} -else -{ - define symbol CS0_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(CS0_SPACE_MIRROR_LENGTH)) -{ - define symbol CS0_SPACE_MIRROR_PRV_LENGTH = CS0_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol CS0_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS2_SPACE_MIRROR_START)) -{ - define symbol CS2_SPACE_MIRROR_PRV_START = CS2_SPACE_MIRROR_START; -} -else -{ - define symbol CS2_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(CS2_SPACE_MIRROR_LENGTH)) -{ - define symbol CS2_SPACE_MIRROR_PRV_LENGTH = CS2_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol CS2_SPACE_MIRROR_PRV_LENGTH = 0; -} - - -if (isdefinedsymbol(CS3_SPACE_MIRROR_START)) -{ - define symbol CS3_SPACE_MIRROR_PRV_START = CS3_SPACE_MIRROR_START; -} -else -{ - define symbol CS3_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(CS3_SPACE_MIRROR_LENGTH)) -{ - define symbol CS3_SPACE_MIRROR_PRV_LENGTH = CS3_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol CS3_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS5_SPACE_MIRROR_START)) -{ - define symbol CS5_SPACE_MIRROR_PRV_START = CS5_SPACE_MIRROR_START; -} -else -{ - define symbol CS5_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(CS5_SPACE_MIRROR_LENGTH)) -{ - define symbol CS5_SPACE_MIRROR_PRV_LENGTH = CS5_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol CS5_SPACE_MIRROR_PRV_LENGTH = 0; -} - - -if (isdefinedsymbol(xSPI0_CS0_SPACE_START)) -{ - define symbol xSPI0_CS0_SPACE_PRV_START = xSPI0_CS0_SPACE_START; -} -else -{ - define symbol xSPI0_CS0_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI0_CS0_SPACE_LENGTH)) -{ - define symbol xSPI0_CS0_SPACE_PRV_LENGTH = xSPI0_CS0_SPACE_LENGTH; -} -else -{ - define symbol xSPI0_CS0_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI0_CS1_SPACE_START)) -{ - define symbol xSPI0_CS1_SPACE_PRV_START = xSPI0_CS1_SPACE_START; -} -else -{ - define symbol xSPI0_CS1_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI0_CS1_SPACE_LENGTH)) -{ - define symbol xSPI0_CS1_SPACE_PRV_LENGTH = xSPI0_CS1_SPACE_LENGTH; -} -else -{ - define symbol xSPI0_CS1_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI1_CS0_SPACE_START)) -{ - define symbol xSPI1_CS0_SPACE_PRV_START = xSPI1_CS0_SPACE_START; -} -else -{ - define symbol xSPI1_CS0_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI1_CS0_SPACE_LENGTH)) -{ - define symbol xSPI1_CS0_SPACE_PRV_LENGTH = xSPI1_CS0_SPACE_LENGTH; -} -else -{ - define symbol xSPI1_CS0_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI1_CS1_SPACE_START)) -{ - define symbol xSPI1_CS1_SPACE_PRV_START = xSPI1_CS1_SPACE_START; -} -else -{ - define symbol xSPI1_CS1_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI1_CS1_SPACE_LENGTH)) -{ - define symbol xSPI1_CS1_SPACE_PRV_LENGTH = xSPI1_CS1_SPACE_LENGTH; -} -else -{ - define symbol xSPI1_CS1_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS0_SPACE_START)) -{ - define symbol CS0_SPACE_PRV_START = CS0_SPACE_START; -} -else -{ - define symbol CS0_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(CS0_SPACE_LENGTH)) -{ - define symbol CS0_SPACE_PRV_LENGTH = CS0_SPACE_LENGTH; -} -else -{ - define symbol CS0_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS2_SPACE_START)) -{ - define symbol CS2_SPACE_PRV_START = CS2_SPACE_START; -} -else -{ - define symbol CS2_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(CS2_SPACE_LENGTH)) -{ - define symbol CS2_SPACE_PRV_LENGTH = CS2_SPACE_LENGTH; -} -else -{ - define symbol CS2_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS3_SPACE_START)) -{ - define symbol CS3_SPACE_PRV_START = CS3_SPACE_START; -} -else -{ - define symbol CS3_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(CS3_SPACE_LENGTH)) -{ - define symbol CS3_SPACE_PRV_LENGTH = CS3_SPACE_LENGTH; -} -else -{ - define symbol CS3_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS5_SPACE_START)) -{ - define symbol CS5_SPACE_PRV_START = CS5_SPACE_START; -} -else -{ - define symbol CS5_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(CS5_SPACE_LENGTH)) -{ - define symbol CS5_SPACE_PRV_LENGTH = CS5_SPACE_LENGTH; -} -else -{ - define symbol CS5_SPACE_PRV_LENGTH = 0; -} - -define symbol SYSTEM_RAM_END_OFFSET = 0x00048000; -define symbol FLASH_ADDRESS = xSPI0_CS0_SPACE_PRV_START; - -define symbol INTVEC_ADDRESS = ATCM_PRV_START; -define symbol RAM_ADDRESS = (ATCM_PRV_START + 0x100); -define symbol RAM_END_ADDRESS = (ATCM_PRV_START + ATCM_PRV_LENGTH - 1); -define symbol LOADER_STACK_ADDRESS = (BTCM_PRV_START + 0x2000); -define symbol LOADER_STACK_END_ADDRESS = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1); -define symbol DATA_NONCACHE_OFFSET = 0x00048000; -define symbol DATA_NONCACHE_END_OFFSET = 0x00044000; -define symbol DMAC_LINK_MODE_OFFSET = 0x00044000; -define symbol DMAC_LINK_MODE_END_OFFSET = 0x00040000; -define symbol NONCACHE_BUFFER_OFFSET = 0x00020000; -define symbol NONCACHE_BUFFER_END_OFFSET = 0; - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = INTVEC_ADDRESS; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = FLASH_ADDRESS + 0x20100; -define symbol __ICFEDIT_region_ROM_end__ = FLASH_ADDRESS + 0x6FFFF; -define symbol __ICFEDIT_region_RAM_start__ = RAM_ADDRESS; -define symbol __ICFEDIT_region_RAM_end__ = RAM_END_ADDRESS; -/**** End of ICF editor section. ###ICF###*/ - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; - -define symbol __region_D_LOADER_STACK_start__ = LOADER_STACK_ADDRESS; -define symbol __region_D_LOADER_STACK_end__ = LOADER_STACK_END_ADDRESS; - -define symbol __region_DATA_NONCACHE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_OFFSET; -define symbol __region_DATA_NONCACHE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_END_OFFSET - 1; -define symbol __region_DMAC_LINK_MODE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_OFFSET; -define symbol __region_DMAC_LINK_MODE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_END_OFFSET - 1; -define symbol __region_SHARED_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00040000; -define symbol __region_SHARED_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00020000 - 1; -define symbol __region_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_OFFSET; -define symbol __region_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_END_OFFSET - 1; - -define symbol __region_ATCM_start__ = ATCM_PRV_START; -define symbol __region_ATCM_end__ = ATCM_PRV_START + ATCM_PRV_LENGTH - 1; -define symbol __region_BTCM_start__ = BTCM_PRV_START; -define symbol __region_BTCM_end__ = BTCM_PRV_START + BTCM_PRV_LENGTH - 1; -define symbol __region_SYSTEM_RAM_start__ = SYSTEM_RAM_PRV_START; -define symbol __region_SYSTEM_RAM_end__ = SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; -define symbol __region_SYSTEM_RAM_MIRROR_start__ = SYSTEM_RAM_MIRROR_PRV_START; -define symbol __region_SYSTEM_RAM_MIRROR_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; - -define symbol __region_XSPI0_CS0_MIRROR_start__ = xSPI0_CS0_SPACE_MIRROR_PRV_START; -define symbol __region_XSPI0_CS0_MIRROR_end__ = xSPI0_CS0_SPACE_MIRROR_PRV_START + xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_XSPI0_CS1_MIRROR_start__ = xSPI0_CS1_SPACE_MIRROR_PRV_START; -define symbol __region_XSPI0_CS1_MIRROR_end__ = xSPI0_CS1_SPACE_MIRROR_PRV_START + xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_XSPI1_CS0_MIRROR_start__ = xSPI1_CS0_SPACE_MIRROR_PRV_START; -define symbol __region_XSPI1_CS0_MIRROR_end__ = xSPI1_CS0_SPACE_MIRROR_PRV_START + xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_XSPI1_CS1_MIRROR_start__ = xSPI1_CS1_SPACE_MIRROR_PRV_START; -define symbol __region_XSPI1_CS1_MIRROR_end__ = xSPI1_CS1_SPACE_MIRROR_PRV_START + xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_CS0_MIRROR_start__ = CS0_SPACE_MIRROR_PRV_START; -define symbol __region_CS0_MIRROR_end__ = CS0_SPACE_MIRROR_PRV_START + CS0_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_CS2_MIRROR_start__ = CS2_SPACE_MIRROR_PRV_START; -define symbol __region_CS2_MIRROR_end__ = CS2_SPACE_MIRROR_PRV_START + CS2_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_CS3_MIRROR_start__ = CS3_SPACE_MIRROR_PRV_START; -define symbol __region_CS3_MIRROR_end__ = CS3_SPACE_MIRROR_PRV_START + CS3_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_CS5_MIRROR_start__ = CS5_SPACE_MIRROR_PRV_START; -define symbol __region_CS5_MIRROR_end__ = CS5_SPACE_MIRROR_PRV_START + CS5_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_XSPI0_CS0_start__ = xSPI0_CS0_SPACE_PRV_START; -define symbol __region_XSPI0_CS0_end__ = xSPI0_CS0_SPACE_PRV_START + xSPI0_CS0_SPACE_PRV_LENGTH - 1; -define symbol __region_XSPI0_CS1_start__ = xSPI0_CS1_SPACE_PRV_START; -define symbol __region_XSPI0_CS1_end__ = xSPI0_CS1_SPACE_PRV_START + xSPI0_CS1_SPACE_PRV_LENGTH - 1; -define symbol __region_XSPI1_CS0_start__ = xSPI1_CS0_SPACE_PRV_START; -define symbol __region_XSPI1_CS0_end__ = xSPI1_CS0_SPACE_PRV_START + xSPI1_CS0_SPACE_PRV_LENGTH - 1; -define symbol __region_XSPI1_CS1_start__ = xSPI1_CS1_SPACE_PRV_START; -define symbol __region_XSPI1_CS1_end__ = xSPI1_CS1_SPACE_PRV_START + xSPI1_CS1_SPACE_PRV_LENGTH - 1; -define symbol __region_CS0_start__ = CS0_SPACE_PRV_START; -define symbol __region_CS0_end__ = CS0_SPACE_PRV_START + CS0_SPACE_PRV_LENGTH - 1; -define symbol __region_CS2_start__ = CS2_SPACE_PRV_START; -define symbol __region_CS2_end__ = CS2_SPACE_PRV_START + CS2_SPACE_PRV_LENGTH - 1; -define symbol __region_CS3_start__ = CS3_SPACE_PRV_START; -define symbol __region_CS3_end__ = CS3_SPACE_PRV_START + CS3_SPACE_PRV_LENGTH - 1; -define symbol __region_CS5_start__ = CS5_SPACE_PRV_START; -define symbol __region_CS5_end__ = CS5_SPACE_PRV_START + CS5_SPACE_PRV_LENGTH - 1; - -/************** SPI boot mode setting **************/ -define symbol __region_LDR_PARAM_start__ = FLASH_ADDRESS; -define symbol __region_LDR_PARAM_end__ = FLASH_ADDRESS + 0x0000004B; -define symbol __region_S_LOADER_STACK_start__ = FLASH_ADDRESS + 0x0000004C; -define symbol __region_S_LOADER_STACK_end__ = FLASH_ADDRESS + 0x0000804B; - -define symbol __region_S_intvec_start__ = FLASH_ADDRESS + 0x20000; -define symbol __region_S_intvec_end__ = FLASH_ADDRESS + 0x200FF; -define symbol __region_S_RAM_start__ = FLASH_ADDRESS + 0x70000; -define symbol __region_S_RAM_end__ = FLASH_ADDRESS + 0x7FFFF; -/****************************************************/ - -define region D_LOADER_STACK_region = mem:[from __region_D_LOADER_STACK_start__ to __region_D_LOADER_STACK_end__]; - -define region LDR_PARAM_region = mem:[from __region_LDR_PARAM_start__ to __region_LDR_PARAM_end__]; -define region S_LOADER_STACK_region = mem:[from __region_S_LOADER_STACK_start__ to __region_S_LOADER_STACK_end__]; - -define region S_intvec_region = mem:[from __region_S_intvec_start__ to __region_S_intvec_end__]; -define region S_RAM_region = mem:[from __region_S_RAM_start__ to __region_S_RAM_end__]; - -define region DATA_NONCACHE_region = mem:[from __region_DATA_NONCACHE_start__ to __region_DATA_NONCACHE_end__]; -define region DMAC_LINK_MODE_region = mem:[from __region_DMAC_LINK_MODE_start__ to __region_DMAC_LINK_MODE_end__]; -define region SHARED_NONCACHE_BUFFER_region = mem:[from __region_SHARED_NONCACHE_BUFFER_start__ to __region_SHARED_NONCACHE_BUFFER_end__]; -define region NONCACHE_BUFFER_region = mem:[from __region_NONCACHE_BUFFER_start__ to __region_NONCACHE_BUFFER_end__]; - -define region ATCM_region = mem:[from __region_ATCM_start__ to __region_ATCM_end__ ]; -define region BTCM_region = mem:[from __region_BTCM_start__ to __region_BTCM_end__ ]; -define region SYSTEM_RAM_region = mem:[from __region_SYSTEM_RAM_start__ to __region_SYSTEM_RAM_end__ ]; -define region SYSTEM_RAM_MIRROR_region = mem:[from __region_SYSTEM_RAM_MIRROR_start__ to __region_SYSTEM_RAM_MIRROR_end__ ]; -define region XSPI0_CS0_MIRROR_region = mem:[from __region_XSPI0_CS0_MIRROR_start__ to __region_XSPI0_CS0_MIRROR_end__ ]; -define region XSPI0_CS1_MIRROR_region = mem:[from __region_XSPI0_CS1_MIRROR_start__ to __region_XSPI0_CS1_MIRROR_end__ ]; -define region XSPI1_CS0_MIRROR_region = mem:[from __region_XSPI1_CS0_MIRROR_start__ to __region_XSPI1_CS0_MIRROR_end__ ]; -define region XSPI1_CS1_MIRROR_region = mem:[from __region_XSPI1_CS1_MIRROR_start__ to __region_XSPI1_CS1_MIRROR_end__ ]; -define region CS0_MIRROR_region = mem:[from __region_CS0_MIRROR_start__ to __region_CS0_MIRROR_end__ ]; -define region CS2_MIRROR_region = mem:[from __region_CS2_MIRROR_start__ to __region_CS2_MIRROR_end__ ]; -define region CS3_MIRROR_region = mem:[from __region_CS3_MIRROR_start__ to __region_CS3_MIRROR_end__ ]; -define region CS5_MIRROR_region = mem:[from __region_CS5_MIRROR_start__ to __region_CS5_MIRROR_end__ ]; -define region XSPI0_CS0_region = mem:[from __region_XSPI0_CS0_start__ to __region_XSPI0_CS0_end__ ]; -define region XSPI0_CS1_region = mem:[from __region_XSPI0_CS1_start__ to __region_XSPI0_CS1_end__ ]; -define region XSPI1_CS0_region = mem:[from __region_XSPI1_CS0_start__ to __region_XSPI1_CS0_end__ ]; -define region XSPI1_CS1_region = mem:[from __region_XSPI1_CS1_start__ to __region_XSPI1_CS1_end__ ]; -define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__ ]; -define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__ ]; -define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__ ]; -define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__ ]; - -define block LDR_PRG_RBLOCK with fixed order - { ro code section .loader_text_init object startup_core.o, - ro code object startup_core.o, - ro code object system_core.o, - ro code object startup.o, - ro code object system.o, - ro code object bsp_clocks.o, - ro code object bsp_irq_core.o, - ro code object bsp_irq.o, - ro code object bsp_register_protection.o, - ro code object r_ioport.o, - ro code object bsp_cache.o, - ro code section .warm_start_init } - except { ro code section .intvec_init, - ro code section .reset_handler_init }; -define block LDR_PRG_WBLOCK with fixed order - { rw code section .loader_text object startup_core.o, - rw code object startup_core.o, - rw code object system_core.o, - rw code object startup.o, - rw code object system.o, - rw code object bsp_clocks.o, - rw code object bsp_irq_core.o, - rw code object bsp_irq.o, - rw code object bsp_register_protection.o, - rw code object r_ioport.o, - rw code object bsp_cache.o, - rw code section .warm_start } - except { rw code section .intvec, - rw code section .reset_handler }; -define block LDR_DATA_ZBLOCK with alignment = 4 - { section .bss object startup_core.o, - section .bss object system_core.o, - section .bss object startup.o, - section .bss object system.o, - section .bss object bsp_clocks.o, - section .bss object bsp_irq_core.o, - section .bss object bsp_irq.o, - section .bss object bsp_register_protection.o, - section .bss object r_ioport.o, - section .bss object bsp_cache.o, - section .bss object bsp_io.o }; -define block LDR_DATA_RBLOCK with fixed order, alignment = 4 - { section .data_init object startup_core.o, - section .data_init object system_core.o, - section .data_init object startup.o, - section .data_init object system.o, - section .data_init object bsp_clocks.o, - section .data_init object bsp_irq_core.o, - section .data_init object bsp_irq.o, - section .data_init object bsp_register_protection.o, - section .data_init object r_ioport.o, - section .data_init object bsp_cache.o, - section .rodata_init object system_core.o }; -define block LDR_DATA_WBLOCK with fixed order, alignment = 4 - { section .data object startup_core.o, - section .data object system_core.o, - section .data object startup.o, - section .data object system.o, - section .data object bsp_clocks.o, - section .data object bsp_irq_core.o, - section .data object bsp_irq.o, - section .data object bsp_register_protection.o, - section .data object r_ioport.o, - section .data object bsp_cache.o, - section .rodata object system_core.o }; - -define block HEAP_BLOCK with alignment = 8 { rw section HEAP }; -define block THREAD_STACK with alignment = 8 { rw section .stack* }; -define block SYS_STACK with alignment = 8 { rw section .sys_stack }; -define block SVC_STACK with alignment = 8 { rw section .svc_stack }; -define block IRQ_STACK with alignment = 8 { rw section .irq_stack }; -define block FIQ_STACK with alignment = 8 { rw section .fiq_stack }; -define block UND_STACK with alignment = 8 { rw section .und_stack }; -define block ABT_STACK with alignment = 8 { rw section .abt_stack }; - -define block VECTOR_RBLOCK with alignment = 32 { ro code section .intvec_init}; -define block VECTOR_WBLOCK with alignment = 32 { rw code section .intvec}; -define block USER_PRG_RBLOCK with alignment = 4 { ro code }; -define block USER_PRG_WBLOCK with alignment = 4 { rw code }; -define block USER_DATA_ZBLOCK with alignment = 4 { section .bss }; -define block USER_DATA_RBLOCK with fixed order, alignment = 4 - { section .data_init, - section __DLIB_PERTHREAD_init, - section .rodata_init, - section .version_init }; -define block USER_DATA_WBLOCK with fixed order, alignment = 4 - { section .data, - section __DLIB_PERTHREAD, - section .rodata, - section .version }; -define block USER_DATA_NONCACHE_RBLOCK with alignment = 4 { section .data_noncache_init }; -define block USER_DATA_NONCACHE_WBLOCK with alignment = 4 { section .data_noncache }; -define block DMAC_LINK_MODE_ZBLOCK with alignment = 4 { section .dmac_link_mode* }; -define block SHARED_NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .shared_noncache_buffer* }; -define block NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .noncache_buffer* }; - -initialize manually { ro code object startup_core.o, - ro code object system_core.o, - ro code object startup.o, - ro code object system.o, - ro code object bsp_clocks.o, - ro code object bsp_irq_core.o, - ro code object bsp_irq.o, - ro code object bsp_register_protection.o, - ro code object r_ioport.o, - ro code object bsp_cache.o, - ro code section .intvec, - ro code section .reset_handler, - ro code section .warm_start, - ro code, - section .data, - section __DLIB_PERTHREAD, - section .rodata, - section .version, - section .data_noncache }; - -do not initialize { section .noinit, - section .bss, - section .dmac_link_mode*, - section .shared_noncache_buffer*, - section .noncache_buffer*, - rw section HEAP, - rw section .stack*, - rw section .sys_stack, - rw section .svc_stack, - rw section .irq_stack, - rw section .fiq_stack, - rw section .und_stack, - rw section .abt_stack }; - -place at address mem: __ICFEDIT_intvec_start__ { block VECTOR_WBLOCK }; - -place in LDR_PARAM_region { readonly section .loader_param }; -place at start of S_LOADER_STACK_region { block LDR_PRG_RBLOCK }; -place in S_LOADER_STACK_region { section LDR_DATA_RBLOCK, block LDR_DATA_RBLOCK }; -place in S_intvec_region { block VECTOR_RBLOCK }; -place in ROM_region { block USER_PRG_RBLOCK, readonly }; -place in S_RAM_region { block USER_DATA_RBLOCK, block USER_DATA_NONCACHE_RBLOCK }; - -place at start of D_LOADER_STACK_region { block LDR_PRG_WBLOCK }; -place in D_LOADER_STACK_region { section LDR_DATA_WBLOCK, block LDR_DATA_WBLOCK, - section LDR_DATA_ZBLOCK, block LDR_DATA_ZBLOCK }; -place in D_LOADER_STACK_region { section SYS_STACK, block SYS_STACK, - section SVC_STACK, block SVC_STACK, - section IRQ_STACK, block IRQ_STACK, - section FIQ_STACK, block FIQ_STACK, - section UND_STACK, block UND_STACK, - section ABT_STACK, block ABT_STACK }; -place in RAM_region { block USER_PRG_WBLOCK }; -place in RAM_region { readwrite, last block CSTACK }; -place in RAM_region { block USER_DATA_WBLOCK, - block USER_DATA_ZBLOCK }; -place in RAM_region { section HEAP_BLOCK, block HEAP_BLOCK, - section THREAD_STACK, block THREAD_STACK }; - -place in DATA_NONCACHE_region { block USER_DATA_NONCACHE_WBLOCK }; -place in DMAC_LINK_MODE_region { block DMAC_LINK_MODE_ZBLOCK }; -place in SHARED_NONCACHE_BUFFER_region { block SHARED_NONCACHE_BUFFER_ZBLOCK }; -place in NONCACHE_BUFFER_region { block NONCACHE_BUFFER_ZBLOCK }; -place in ATCM_region { }; -place in BTCM_region { }; -place in SYSTEM_RAM_region { }; -place in SYSTEM_RAM_MIRROR_region { }; -place in XSPI0_CS0_MIRROR_region { }; -place in XSPI0_CS1_MIRROR_region { }; -place in XSPI1_CS0_MIRROR_region { }; -place in XSPI1_CS1_MIRROR_region { }; -place in CS0_MIRROR_region { }; -place in CS2_MIRROR_region { }; -place in CS3_MIRROR_region { }; -place in CS5_MIRROR_region { }; -place in XSPI0_CS0_region { }; -place in XSPI0_CS1_region { }; -place in XSPI1_CS0_region { }; -place in XSPI1_CS1_region { }; -place in CS0_region { }; -place in CS2_region { }; -place in CS3_region { }; -place in CS5_region { }; +include "memory_regions.icf"; + +/* The memory information for each device is done in memory regions file. + * The starting address and length of memory not defined in memory regions file are defined as 0. */ + +if (isdefinedsymbol(ATCM_START)) +{ + define symbol ATCM_PRV_START = ATCM_START; +} +else +{ + define symbol ATCM_PRV_START = 0; +} + +if (isdefinedsymbol(ATCM_LENGTH)) +{ + define symbol ATCM_PRV_LENGTH = ATCM_LENGTH; +} +else +{ + define symbol ATCM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(BTCM_START)) +{ + define symbol BTCM_PRV_START = BTCM_START; +} +else +{ + define symbol BTCM_PRV_START = 0; +} + +if (isdefinedsymbol(BTCM_LENGTH)) +{ + define symbol BTCM_PRV_LENGTH = BTCM_LENGTH; +} +else +{ + define symbol BTCM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_START)) +{ + define symbol SYSTEM_RAM_PRV_START = SYSTEM_RAM_START; +} +else +{ + define symbol SYSTEM_RAM_PRV_START = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_LENGTH)) +{ + define symbol SYSTEM_RAM_PRV_LENGTH = SYSTEM_RAM_LENGTH; +} +else +{ + define symbol SYSTEM_RAM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_MIRROR_START)) +{ + define symbol SYSTEM_RAM_MIRROR_PRV_START = SYSTEM_RAM_MIRROR_START; +} +else +{ + define symbol SYSTEM_RAM_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_MIRROR_LENGTH)) +{ + define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = SYSTEM_RAM_MIRROR_LENGTH; +} +else +{ + define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_START)) +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = xSPI0_CS0_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_START)) +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = xSPI0_CS1_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS1_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_START)) +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = xSPI1_CS0_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_START)) +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = xSPI1_CS1_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS1_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS0_SPACE_MIRROR_START)) +{ + define symbol CS0_SPACE_MIRROR_PRV_START = CS0_SPACE_MIRROR_START; +} +else +{ + define symbol CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol CS0_SPACE_MIRROR_PRV_LENGTH = CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS2_SPACE_MIRROR_START)) +{ + define symbol CS2_SPACE_MIRROR_PRV_START = CS2_SPACE_MIRROR_START; +} +else +{ + define symbol CS2_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS2_SPACE_MIRROR_LENGTH)) +{ + define symbol CS2_SPACE_MIRROR_PRV_LENGTH = CS2_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS2_SPACE_MIRROR_PRV_LENGTH = 0; +} + + +if (isdefinedsymbol(CS3_SPACE_MIRROR_START)) +{ + define symbol CS3_SPACE_MIRROR_PRV_START = CS3_SPACE_MIRROR_START; +} +else +{ + define symbol CS3_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS3_SPACE_MIRROR_LENGTH)) +{ + define symbol CS3_SPACE_MIRROR_PRV_LENGTH = CS3_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS3_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS5_SPACE_MIRROR_START)) +{ + define symbol CS5_SPACE_MIRROR_PRV_START = CS5_SPACE_MIRROR_START; +} +else +{ + define symbol CS5_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS5_SPACE_MIRROR_LENGTH)) +{ + define symbol CS5_SPACE_MIRROR_PRV_LENGTH = CS5_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS5_SPACE_MIRROR_PRV_LENGTH = 0; +} + + +if (isdefinedsymbol(xSPI0_CS0_SPACE_START)) +{ + define symbol xSPI0_CS0_SPACE_PRV_START = xSPI0_CS0_SPACE_START; +} +else +{ + define symbol xSPI0_CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_LENGTH)) +{ + define symbol xSPI0_CS0_SPACE_PRV_LENGTH = xSPI0_CS0_SPACE_LENGTH; +} +else +{ + define symbol xSPI0_CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_START)) +{ + define symbol xSPI0_CS1_SPACE_PRV_START = xSPI0_CS1_SPACE_START; +} +else +{ + define symbol xSPI0_CS1_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_LENGTH)) +{ + define symbol xSPI0_CS1_SPACE_PRV_LENGTH = xSPI0_CS1_SPACE_LENGTH; +} +else +{ + define symbol xSPI0_CS1_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_START)) +{ + define symbol xSPI1_CS0_SPACE_PRV_START = xSPI1_CS0_SPACE_START; +} +else +{ + define symbol xSPI1_CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_LENGTH)) +{ + define symbol xSPI1_CS0_SPACE_PRV_LENGTH = xSPI1_CS0_SPACE_LENGTH; +} +else +{ + define symbol xSPI1_CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_START)) +{ + define symbol xSPI1_CS1_SPACE_PRV_START = xSPI1_CS1_SPACE_START; +} +else +{ + define symbol xSPI1_CS1_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_LENGTH)) +{ + define symbol xSPI1_CS1_SPACE_PRV_LENGTH = xSPI1_CS1_SPACE_LENGTH; +} +else +{ + define symbol xSPI1_CS1_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS0_SPACE_START)) +{ + define symbol CS0_SPACE_PRV_START = CS0_SPACE_START; +} +else +{ + define symbol CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS0_SPACE_LENGTH)) +{ + define symbol CS0_SPACE_PRV_LENGTH = CS0_SPACE_LENGTH; +} +else +{ + define symbol CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS2_SPACE_START)) +{ + define symbol CS2_SPACE_PRV_START = CS2_SPACE_START; +} +else +{ + define symbol CS2_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS2_SPACE_LENGTH)) +{ + define symbol CS2_SPACE_PRV_LENGTH = CS2_SPACE_LENGTH; +} +else +{ + define symbol CS2_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS3_SPACE_START)) +{ + define symbol CS3_SPACE_PRV_START = CS3_SPACE_START; +} +else +{ + define symbol CS3_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS3_SPACE_LENGTH)) +{ + define symbol CS3_SPACE_PRV_LENGTH = CS3_SPACE_LENGTH; +} +else +{ + define symbol CS3_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS5_SPACE_START)) +{ + define symbol CS5_SPACE_PRV_START = CS5_SPACE_START; +} +else +{ + define symbol CS5_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS5_SPACE_LENGTH)) +{ + define symbol CS5_SPACE_PRV_LENGTH = CS5_SPACE_LENGTH; +} +else +{ + define symbol CS5_SPACE_PRV_LENGTH = 0; +} + +define symbol SYSTEM_RAM_END_OFFSET = 0x00048000; +define symbol FLASH_ADDRESS = xSPI0_CS0_SPACE_PRV_START; + +define symbol INTVEC_ADDRESS = ATCM_PRV_START; +define symbol RAM_ADDRESS = (ATCM_PRV_START + 0x100); +define symbol RAM_END_ADDRESS = (ATCM_PRV_START + ATCM_PRV_LENGTH - 1); +define symbol LOADER_STACK_ADDRESS = (BTCM_PRV_START + 0x2000); +define symbol LOADER_STACK_END_ADDRESS = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1); +define symbol DATA_NONCACHE_OFFSET = 0x00048000; +define symbol DATA_NONCACHE_END_OFFSET = 0x00044000; +define symbol DMAC_LINK_MODE_OFFSET = 0x00044000; +define symbol DMAC_LINK_MODE_END_OFFSET = 0x00040000; +define symbol NONCACHE_BUFFER_OFFSET = 0x00020000; +define symbol NONCACHE_BUFFER_END_OFFSET = 0; + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = INTVEC_ADDRESS; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = FLASH_ADDRESS + 0x20100; +define symbol __ICFEDIT_region_ROM_end__ = FLASH_ADDRESS + 0x6FFFF; +define symbol __ICFEDIT_region_RAM_start__ = RAM_ADDRESS; +define symbol __ICFEDIT_region_RAM_end__ = RAM_END_ADDRESS; +/**** End of ICF editor section. ###ICF###*/ + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +define symbol __region_D_LOADER_STACK_start__ = LOADER_STACK_ADDRESS; +define symbol __region_D_LOADER_STACK_end__ = LOADER_STACK_END_ADDRESS; + +define symbol __region_DATA_NONCACHE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_OFFSET; +define symbol __region_DATA_NONCACHE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_END_OFFSET - 1; +define symbol __region_DMAC_LINK_MODE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_OFFSET; +define symbol __region_DMAC_LINK_MODE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_END_OFFSET - 1; +define symbol __region_SHARED_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00040000; +define symbol __region_SHARED_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00020000 - 1; +define symbol __region_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_OFFSET; +define symbol __region_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_END_OFFSET - 1; + +define symbol __region_ATCM_start__ = ATCM_PRV_START; +define symbol __region_ATCM_end__ = ATCM_PRV_START + ATCM_PRV_LENGTH - 1; +define symbol __region_BTCM_start__ = BTCM_PRV_START; +define symbol __region_BTCM_end__ = BTCM_PRV_START + BTCM_PRV_LENGTH - 1; +define symbol __region_SYSTEM_RAM_start__ = SYSTEM_RAM_PRV_START; +define symbol __region_SYSTEM_RAM_end__ = SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; +define symbol __region_SYSTEM_RAM_MIRROR_start__ = SYSTEM_RAM_MIRROR_PRV_START; +define symbol __region_SYSTEM_RAM_MIRROR_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; + +define symbol __region_XSPI0_CS0_MIRROR_start__ = xSPI0_CS0_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI0_CS0_MIRROR_end__ = xSPI0_CS0_SPACE_MIRROR_PRV_START + xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS1_MIRROR_start__ = xSPI0_CS1_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI0_CS1_MIRROR_end__ = xSPI0_CS1_SPACE_MIRROR_PRV_START + xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS0_MIRROR_start__ = xSPI1_CS0_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI1_CS0_MIRROR_end__ = xSPI1_CS0_SPACE_MIRROR_PRV_START + xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS1_MIRROR_start__ = xSPI1_CS1_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI1_CS1_MIRROR_end__ = xSPI1_CS1_SPACE_MIRROR_PRV_START + xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS0_MIRROR_start__ = CS0_SPACE_MIRROR_PRV_START; +define symbol __region_CS0_MIRROR_end__ = CS0_SPACE_MIRROR_PRV_START + CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS2_MIRROR_start__ = CS2_SPACE_MIRROR_PRV_START; +define symbol __region_CS2_MIRROR_end__ = CS2_SPACE_MIRROR_PRV_START + CS2_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS3_MIRROR_start__ = CS3_SPACE_MIRROR_PRV_START; +define symbol __region_CS3_MIRROR_end__ = CS3_SPACE_MIRROR_PRV_START + CS3_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS5_MIRROR_start__ = CS5_SPACE_MIRROR_PRV_START; +define symbol __region_CS5_MIRROR_end__ = CS5_SPACE_MIRROR_PRV_START + CS5_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS0_start__ = xSPI0_CS0_SPACE_PRV_START; +define symbol __region_XSPI0_CS0_end__ = xSPI0_CS0_SPACE_PRV_START + xSPI0_CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS1_start__ = xSPI0_CS1_SPACE_PRV_START; +define symbol __region_XSPI0_CS1_end__ = xSPI0_CS1_SPACE_PRV_START + xSPI0_CS1_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS0_start__ = xSPI1_CS0_SPACE_PRV_START; +define symbol __region_XSPI1_CS0_end__ = xSPI1_CS0_SPACE_PRV_START + xSPI1_CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS1_start__ = xSPI1_CS1_SPACE_PRV_START; +define symbol __region_XSPI1_CS1_end__ = xSPI1_CS1_SPACE_PRV_START + xSPI1_CS1_SPACE_PRV_LENGTH - 1; +define symbol __region_CS0_start__ = CS0_SPACE_PRV_START; +define symbol __region_CS0_end__ = CS0_SPACE_PRV_START + CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_CS2_start__ = CS2_SPACE_PRV_START; +define symbol __region_CS2_end__ = CS2_SPACE_PRV_START + CS2_SPACE_PRV_LENGTH - 1; +define symbol __region_CS3_start__ = CS3_SPACE_PRV_START; +define symbol __region_CS3_end__ = CS3_SPACE_PRV_START + CS3_SPACE_PRV_LENGTH - 1; +define symbol __region_CS5_start__ = CS5_SPACE_PRV_START; +define symbol __region_CS5_end__ = CS5_SPACE_PRV_START + CS5_SPACE_PRV_LENGTH - 1; + +/************** SPI boot mode setting **************/ +define symbol __region_LDR_PARAM_start__ = FLASH_ADDRESS; +define symbol __region_LDR_PARAM_end__ = FLASH_ADDRESS + 0x0000004B; +define symbol __region_S_LOADER_STACK_start__ = FLASH_ADDRESS + 0x0000004C; +define symbol __region_S_LOADER_STACK_end__ = FLASH_ADDRESS + 0x0000804B; + +define symbol __region_S_intvec_start__ = FLASH_ADDRESS + 0x20000; +define symbol __region_S_intvec_end__ = FLASH_ADDRESS + 0x200FF; +define symbol __region_S_RAM_start__ = FLASH_ADDRESS + 0x70000; +define symbol __region_S_RAM_end__ = FLASH_ADDRESS + 0x7FFFF; +/****************************************************/ + +define region D_LOADER_STACK_region = mem:[from __region_D_LOADER_STACK_start__ to __region_D_LOADER_STACK_end__]; + +define region LDR_PARAM_region = mem:[from __region_LDR_PARAM_start__ to __region_LDR_PARAM_end__]; +define region S_LOADER_STACK_region = mem:[from __region_S_LOADER_STACK_start__ to __region_S_LOADER_STACK_end__]; + +define region S_intvec_region = mem:[from __region_S_intvec_start__ to __region_S_intvec_end__]; +define region S_RAM_region = mem:[from __region_S_RAM_start__ to __region_S_RAM_end__]; + +define region DATA_NONCACHE_region = mem:[from __region_DATA_NONCACHE_start__ to __region_DATA_NONCACHE_end__]; +define region DMAC_LINK_MODE_region = mem:[from __region_DMAC_LINK_MODE_start__ to __region_DMAC_LINK_MODE_end__]; +define region SHARED_NONCACHE_BUFFER_region = mem:[from __region_SHARED_NONCACHE_BUFFER_start__ to __region_SHARED_NONCACHE_BUFFER_end__]; +define region NONCACHE_BUFFER_region = mem:[from __region_NONCACHE_BUFFER_start__ to __region_NONCACHE_BUFFER_end__]; + +define region ATCM_region = mem:[from __region_ATCM_start__ to __region_ATCM_end__ ]; +define region BTCM_region = mem:[from __region_BTCM_start__ to __region_BTCM_end__ ]; +define region SYSTEM_RAM_region = mem:[from __region_SYSTEM_RAM_start__ to __region_SYSTEM_RAM_end__ ]; +define region SYSTEM_RAM_MIRROR_region = mem:[from __region_SYSTEM_RAM_MIRROR_start__ to __region_SYSTEM_RAM_MIRROR_end__ ]; +define region XSPI0_CS0_MIRROR_region = mem:[from __region_XSPI0_CS0_MIRROR_start__ to __region_XSPI0_CS0_MIRROR_end__ ]; +define region XSPI0_CS1_MIRROR_region = mem:[from __region_XSPI0_CS1_MIRROR_start__ to __region_XSPI0_CS1_MIRROR_end__ ]; +define region XSPI1_CS0_MIRROR_region = mem:[from __region_XSPI1_CS0_MIRROR_start__ to __region_XSPI1_CS0_MIRROR_end__ ]; +define region XSPI1_CS1_MIRROR_region = mem:[from __region_XSPI1_CS1_MIRROR_start__ to __region_XSPI1_CS1_MIRROR_end__ ]; +define region CS0_MIRROR_region = mem:[from __region_CS0_MIRROR_start__ to __region_CS0_MIRROR_end__ ]; +define region CS2_MIRROR_region = mem:[from __region_CS2_MIRROR_start__ to __region_CS2_MIRROR_end__ ]; +define region CS3_MIRROR_region = mem:[from __region_CS3_MIRROR_start__ to __region_CS3_MIRROR_end__ ]; +define region CS5_MIRROR_region = mem:[from __region_CS5_MIRROR_start__ to __region_CS5_MIRROR_end__ ]; +define region XSPI0_CS0_region = mem:[from __region_XSPI0_CS0_start__ to __region_XSPI0_CS0_end__ ]; +define region XSPI0_CS1_region = mem:[from __region_XSPI0_CS1_start__ to __region_XSPI0_CS1_end__ ]; +define region XSPI1_CS0_region = mem:[from __region_XSPI1_CS0_start__ to __region_XSPI1_CS0_end__ ]; +define region XSPI1_CS1_region = mem:[from __region_XSPI1_CS1_start__ to __region_XSPI1_CS1_end__ ]; +define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__ ]; +define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__ ]; +define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__ ]; +define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__ ]; + +define block LDR_PRG_RBLOCK with fixed order + { ro code section .loader_text_init object startup_core.o, + ro code object startup_core.o, + ro code object system_core.o, + ro code object startup.o, + ro code object system.o, + ro code object bsp_clocks.o, + ro code object bsp_irq_core.o, + ro code object bsp_irq.o, + ro code object bsp_register_protection.o, + ro code object r_ioport.o, + ro code object bsp_cache.o, + ro code section .warm_start_init } + except { ro code section .intvec_init, + ro code section .reset_handler_init }; +define block LDR_PRG_WBLOCK with fixed order + { rw code section .loader_text object startup_core.o, + rw code object startup_core.o, + rw code object system_core.o, + rw code object startup.o, + rw code object system.o, + rw code object bsp_clocks.o, + rw code object bsp_irq_core.o, + rw code object bsp_irq.o, + rw code object bsp_register_protection.o, + rw code object r_ioport.o, + rw code object bsp_cache.o, + rw code section .warm_start } + except { rw code section .intvec, + rw code section .reset_handler }; +define block LDR_DATA_ZBLOCK with alignment = 4 + { section .bss object startup_core.o, + section .bss object system_core.o, + section .bss object startup.o, + section .bss object system.o, + section .bss object bsp_clocks.o, + section .bss object bsp_irq_core.o, + section .bss object bsp_irq.o, + section .bss object bsp_register_protection.o, + section .bss object r_ioport.o, + section .bss object bsp_cache.o, + section .bss object bsp_io.o }; +define block LDR_DATA_RBLOCK with fixed order, alignment = 4 + { section .data_init object startup_core.o, + section .data_init object system_core.o, + section .data_init object startup.o, + section .data_init object system.o, + section .data_init object bsp_clocks.o, + section .data_init object bsp_irq_core.o, + section .data_init object bsp_irq.o, + section .data_init object bsp_register_protection.o, + section .data_init object r_ioport.o, + section .data_init object bsp_cache.o, + section .rodata_init object system_core.o }; +define block LDR_DATA_WBLOCK with fixed order, alignment = 4 + { section .data object startup_core.o, + section .data object system_core.o, + section .data object startup.o, + section .data object system.o, + section .data object bsp_clocks.o, + section .data object bsp_irq_core.o, + section .data object bsp_irq.o, + section .data object bsp_register_protection.o, + section .data object r_ioport.o, + section .data object bsp_cache.o, + section .rodata object system_core.o }; + +define block HEAP_BLOCK with alignment = 8 { rw section HEAP }; +define block THREAD_STACK with alignment = 8 { rw section .stack* }; +define block SYS_STACK with alignment = 8 { rw section .sys_stack }; +define block SVC_STACK with alignment = 8 { rw section .svc_stack }; +define block IRQ_STACK with alignment = 8 { rw section .irq_stack }; +define block FIQ_STACK with alignment = 8 { rw section .fiq_stack }; +define block UND_STACK with alignment = 8 { rw section .und_stack }; +define block ABT_STACK with alignment = 8 { rw section .abt_stack }; + +define block VECTOR_RBLOCK with alignment = 32 { ro code section .intvec_init}; +define block VECTOR_WBLOCK with alignment = 32 { rw code section .intvec}; +define block USER_PRG_RBLOCK with alignment = 4 { ro code }; +define block USER_PRG_WBLOCK with alignment = 4 { rw code }; +define block USER_DATA_ZBLOCK with alignment = 4 { section .bss }; +define block USER_DATA_RBLOCK with fixed order, alignment = 4 + { section .data_init, + section __DLIB_PERTHREAD_init, + section .rodata_init, + section .version_init }; +define block USER_DATA_WBLOCK with fixed order, alignment = 4 + { section .data, + section __DLIB_PERTHREAD, + section .rodata, + section .version }; +define block USER_DATA_NONCACHE_RBLOCK with alignment = 4 { section .data_noncache_init }; +define block USER_DATA_NONCACHE_WBLOCK with alignment = 4 { section .data_noncache }; +define block DMAC_LINK_MODE_ZBLOCK with alignment = 4 { section .dmac_link_mode* }; +define block SHARED_NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .shared_noncache_buffer* }; +define block NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .noncache_buffer* }; + +initialize manually { ro code object startup_core.o, + ro code object system_core.o, + ro code object startup.o, + ro code object system.o, + ro code object bsp_clocks.o, + ro code object bsp_irq_core.o, + ro code object bsp_irq.o, + ro code object bsp_register_protection.o, + ro code object r_ioport.o, + ro code object bsp_cache.o, + ro code section .intvec, + ro code section .reset_handler, + ro code section .warm_start, + ro code, + section .data, + section __DLIB_PERTHREAD, + section .rodata, + section .version, + section .data_noncache }; + +do not initialize { section .noinit, + section .bss, + section .dmac_link_mode*, + section .shared_noncache_buffer*, + section .noncache_buffer*, + rw section HEAP, + rw section .stack*, + rw section .sys_stack, + rw section .svc_stack, + rw section .irq_stack, + rw section .fiq_stack, + rw section .und_stack, + rw section .abt_stack }; + +place at address mem: __ICFEDIT_intvec_start__ { block VECTOR_WBLOCK }; + +place in LDR_PARAM_region { readonly section .loader_param }; +place at start of S_LOADER_STACK_region { block LDR_PRG_RBLOCK }; +place in S_LOADER_STACK_region { section LDR_DATA_RBLOCK, block LDR_DATA_RBLOCK }; +place in S_intvec_region { block VECTOR_RBLOCK }; +place in ROM_region { block USER_PRG_RBLOCK, readonly }; +place in S_RAM_region { block USER_DATA_RBLOCK, block USER_DATA_NONCACHE_RBLOCK }; + +place at start of D_LOADER_STACK_region { block LDR_PRG_WBLOCK }; +place in D_LOADER_STACK_region { section LDR_DATA_WBLOCK, block LDR_DATA_WBLOCK, + section LDR_DATA_ZBLOCK, block LDR_DATA_ZBLOCK }; +place in D_LOADER_STACK_region { section SYS_STACK, block SYS_STACK, + section SVC_STACK, block SVC_STACK, + section IRQ_STACK, block IRQ_STACK, + section FIQ_STACK, block FIQ_STACK, + section UND_STACK, block UND_STACK, + section ABT_STACK, block ABT_STACK }; +place in RAM_region { block USER_PRG_WBLOCK }; +place in RAM_region { readwrite, last block CSTACK }; +place in RAM_region { block USER_DATA_WBLOCK, + block USER_DATA_ZBLOCK }; +place in RAM_region { section HEAP_BLOCK, block HEAP_BLOCK, + section THREAD_STACK, block THREAD_STACK }; + +place in DATA_NONCACHE_region { block USER_DATA_NONCACHE_WBLOCK }; +place in DMAC_LINK_MODE_region { block DMAC_LINK_MODE_ZBLOCK }; +place in SHARED_NONCACHE_BUFFER_region { block SHARED_NONCACHE_BUFFER_ZBLOCK }; +place in NONCACHE_BUFFER_region { block NONCACHE_BUFFER_ZBLOCK }; +place in ATCM_region { }; +place in BTCM_region { }; +place in SYSTEM_RAM_region { }; +place in SYSTEM_RAM_MIRROR_region { }; +place in XSPI0_CS0_MIRROR_region { }; +place in XSPI0_CS1_MIRROR_region { }; +place in XSPI1_CS0_MIRROR_region { }; +place in XSPI1_CS1_MIRROR_region { }; +place in CS0_MIRROR_region { }; +place in CS2_MIRROR_region { }; +place in CS3_MIRROR_region { }; +place in CS5_MIRROR_region { }; +place in XSPI0_CS0_region { }; +place in XSPI0_CS1_region { }; +place in XSPI1_CS0_region { }; +place in XSPI1_CS1_region { }; +place in CS0_region { }; +place in CS2_region { }; +place in CS3_region { }; +place in CS5_region { }; diff --git a/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.ld b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.ld index d0ee38a658..ef2a35fc4c 100644 --- a/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.ld +++ b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.ld @@ -1,12 +1,47 @@ /* Linker File for Renesas RZ/N2L FSP */ - -INCLUDE memory_regions.ld - /* The memory information for each device is done in memory regions file. * The starting address and length of memory not defined in memory regions file are defined as 0. */ +/* generated memory regions file - do not edit */ +ATCM_START = 0x00000000; +ATCM_LENGTH = 0x20000; +BTCM_START = 0x00100000; +BTCM_LENGTH = 0x20000; +SYSTEM_RAM_START = 0x10000000; +SYSTEM_RAM_LENGTH = 0x180000; +SYSTEM_RAM_MIRROR_START = 0x30000000; +SYSTEM_RAM_MIRROR_LENGTH = 0x180000; +xSPI0_CS0_SPACE_MIRROR_START = 0x40000000; +xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000; +xSPI0_CS1_SPACE_MIRROR_START = 0x44000000; +xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000; +xSPI1_CS0_SPACE_MIRROR_START = 0x48000000; +xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000; +CS0_SPACE_MIRROR_START = 0x50000000; +CS0_SPACE_MIRROR_LENGTH = 0x4000000; +CS2_SPACE_MIRROR_START = 0x54000000; +CS2_SPACE_MIRROR_LENGTH = 0x4000000; +CS3_SPACE_MIRROR_START = 0x58000000; +CS3_SPACE_MIRROR_LENGTH = 0x4000000; +CS5_SPACE_MIRROR_START = 0x5C000000; +CS5_SPACE_MIRROR_LENGTH = 0x4000000; +xSPI0_CS0_SPACE_START = 0x60000000; +xSPI0_CS0_SPACE_LENGTH = 0x4000000; +xSPI0_CS1_SPACE_START = 0x64000000; +xSPI0_CS1_SPACE_LENGTH = 0x4000000; +xSPI1_CS0_SPACE_START = 0x68000000; +xSPI1_CS0_SPACE_LENGTH = 0x4000000; +CS0_SPACE_START = 0x70000000; +CS0_SPACE_LENGTH = 0x4000000; +CS2_SPACE_START = 0x74000000; +CS2_SPACE_LENGTH = 0x4000000; +CS3_SPACE_START = 0x78000000; +CS3_SPACE_LENGTH = 0x4000000; +CS5_SPACE_START = 0x7C000000; +CS5_SPACE_LENGTH = 0x4000000; + ATCM_PRV_START = DEFINED(ATCM_START) ? ATCM_START : 0; ATCM_PRV_LENGTH = DEFINED(ATCM_LENGTH) ? ATCM_LENGTH : 0; BTCM_PRV_START = DEFINED(BTCM_START) ? BTCM_START : 0; @@ -51,13 +86,13 @@ CS5_SPACE_PRV_LENGTH = DEFINED(CS5_SPACE_LENGTH) ? CS5_SPACE_LENGTH : 0; LOADER_PARAM_ADDRESS = xSPI0_CS0_SPACE_PRV_START; FLASH_CONTENTS_ADDRESS = LOADER_PARAM_ADDRESS + 0x0000004C; LOADER_TEXT_ADDRESS = 0x00102000; -INTVEC_ADDRESS = 0x00000000; -TEXT_ADDRESS = 0x00000100; +INTVEC_ADDRESS = 0x10000000; +TEXT_ADDRESS = 0x10020000; NONCACHE_BUFFER_OFFSET = 0x00020000; DMAC_LINK_MODE_OFFSET = 0x00044000; DATA_NONCACHE_OFFSET = 0x00048000; -RAM_START = ATCM_PRV_START; -RAM_LENGTH = ATCM_PRV_LENGTH; +RAM_START = SYSTEM_RAM_PRV_START; +RAM_LENGTH = SYSTEM_RAM_PRV_LENGTH; LOADER_START = BTCM_PRV_START; LOADER_LENGTH = BTCM_PRV_LENGTH; @@ -205,22 +240,37 @@ SECTIONS *(.dtors) _dtor_end = .; + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - - - . = ALIGN(4); - KEEP(*(FalPartTable)) + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + /* new GCC version uses .init_array */ + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + KEEP(*(FalPartTable)) KEEP(*(.eh_frame*)) } > RAM @@ -310,7 +360,7 @@ SECTIONS /* Place the STD heap here. */ KEEP(*(.heap)) __HeapLimit = .; - } > ATCM + } > RAM .thread_stack (NOLOAD): { . = ALIGN(8); diff --git a/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot_systemRAM.icf b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot_systemRAM.icf deleted file mode 100644 index 0e3f984c5f..0000000000 --- a/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot_systemRAM.icf +++ /dev/null @@ -1,699 +0,0 @@ -include "memory_regions.icf"; - -/* The memory information for each device is done in memory regions file. - * The starting address and length of memory not defined in memory regions file are defined as 0. */ - -if (isdefinedsymbol(ATCM_START)) -{ - define symbol ATCM_PRV_START = ATCM_START; -} -else -{ - define symbol ATCM_PRV_START = 0; -} - -if (isdefinedsymbol(ATCM_LENGTH)) -{ - define symbol ATCM_PRV_LENGTH = ATCM_LENGTH; -} -else -{ - define symbol ATCM_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(BTCM_START)) -{ - define symbol BTCM_PRV_START = BTCM_START; -} -else -{ - define symbol BTCM_PRV_START = 0; -} - -if (isdefinedsymbol(BTCM_LENGTH)) -{ - define symbol BTCM_PRV_LENGTH = BTCM_LENGTH; -} -else -{ - define symbol BTCM_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(SYSTEM_RAM_START)) -{ - define symbol SYSTEM_RAM_PRV_START = SYSTEM_RAM_START; -} -else -{ - define symbol SYSTEM_RAM_PRV_START = 0; -} - -if (isdefinedsymbol(SYSTEM_RAM_LENGTH)) -{ - define symbol SYSTEM_RAM_PRV_LENGTH = SYSTEM_RAM_LENGTH; -} -else -{ - define symbol SYSTEM_RAM_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(SYSTEM_RAM_MIRROR_START)) -{ - define symbol SYSTEM_RAM_MIRROR_PRV_START = SYSTEM_RAM_MIRROR_START; -} -else -{ - define symbol SYSTEM_RAM_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(SYSTEM_RAM_MIRROR_LENGTH)) -{ - define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = SYSTEM_RAM_MIRROR_LENGTH; -} -else -{ - define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_START)) -{ - define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = xSPI0_CS0_SPACE_MIRROR_START; -} -else -{ - define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_LENGTH)) -{ - define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS0_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_START)) -{ - define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = xSPI0_CS1_SPACE_MIRROR_START; -} -else -{ - define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_LENGTH)) -{ - define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS1_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_START)) -{ - define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = xSPI1_CS0_SPACE_MIRROR_START; -} -else -{ - define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_LENGTH)) -{ - define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS0_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_START)) -{ - define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = xSPI1_CS1_SPACE_MIRROR_START; -} -else -{ - define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_LENGTH)) -{ - define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS1_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS0_SPACE_MIRROR_START)) -{ - define symbol CS0_SPACE_MIRROR_PRV_START = CS0_SPACE_MIRROR_START; -} -else -{ - define symbol CS0_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(CS0_SPACE_MIRROR_LENGTH)) -{ - define symbol CS0_SPACE_MIRROR_PRV_LENGTH = CS0_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol CS0_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS2_SPACE_MIRROR_START)) -{ - define symbol CS2_SPACE_MIRROR_PRV_START = CS2_SPACE_MIRROR_START; -} -else -{ - define symbol CS2_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(CS2_SPACE_MIRROR_LENGTH)) -{ - define symbol CS2_SPACE_MIRROR_PRV_LENGTH = CS2_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol CS2_SPACE_MIRROR_PRV_LENGTH = 0; -} - - -if (isdefinedsymbol(CS3_SPACE_MIRROR_START)) -{ - define symbol CS3_SPACE_MIRROR_PRV_START = CS3_SPACE_MIRROR_START; -} -else -{ - define symbol CS3_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(CS3_SPACE_MIRROR_LENGTH)) -{ - define symbol CS3_SPACE_MIRROR_PRV_LENGTH = CS3_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol CS3_SPACE_MIRROR_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS5_SPACE_MIRROR_START)) -{ - define symbol CS5_SPACE_MIRROR_PRV_START = CS5_SPACE_MIRROR_START; -} -else -{ - define symbol CS5_SPACE_MIRROR_PRV_START = 0; -} - -if (isdefinedsymbol(CS5_SPACE_MIRROR_LENGTH)) -{ - define symbol CS5_SPACE_MIRROR_PRV_LENGTH = CS5_SPACE_MIRROR_LENGTH; -} -else -{ - define symbol CS5_SPACE_MIRROR_PRV_LENGTH = 0; -} - - -if (isdefinedsymbol(xSPI0_CS0_SPACE_START)) -{ - define symbol xSPI0_CS0_SPACE_PRV_START = xSPI0_CS0_SPACE_START; -} -else -{ - define symbol xSPI0_CS0_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI0_CS0_SPACE_LENGTH)) -{ - define symbol xSPI0_CS0_SPACE_PRV_LENGTH = xSPI0_CS0_SPACE_LENGTH; -} -else -{ - define symbol xSPI0_CS0_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI0_CS1_SPACE_START)) -{ - define symbol xSPI0_CS1_SPACE_PRV_START = xSPI0_CS1_SPACE_START; -} -else -{ - define symbol xSPI0_CS1_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI0_CS1_SPACE_LENGTH)) -{ - define symbol xSPI0_CS1_SPACE_PRV_LENGTH = xSPI0_CS1_SPACE_LENGTH; -} -else -{ - define symbol xSPI0_CS1_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI1_CS0_SPACE_START)) -{ - define symbol xSPI1_CS0_SPACE_PRV_START = xSPI1_CS0_SPACE_START; -} -else -{ - define symbol xSPI1_CS0_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI1_CS0_SPACE_LENGTH)) -{ - define symbol xSPI1_CS0_SPACE_PRV_LENGTH = xSPI1_CS0_SPACE_LENGTH; -} -else -{ - define symbol xSPI1_CS0_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(xSPI1_CS1_SPACE_START)) -{ - define symbol xSPI1_CS1_SPACE_PRV_START = xSPI1_CS1_SPACE_START; -} -else -{ - define symbol xSPI1_CS1_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(xSPI1_CS1_SPACE_LENGTH)) -{ - define symbol xSPI1_CS1_SPACE_PRV_LENGTH = xSPI1_CS1_SPACE_LENGTH; -} -else -{ - define symbol xSPI1_CS1_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS0_SPACE_START)) -{ - define symbol CS0_SPACE_PRV_START = CS0_SPACE_START; -} -else -{ - define symbol CS0_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(CS0_SPACE_LENGTH)) -{ - define symbol CS0_SPACE_PRV_LENGTH = CS0_SPACE_LENGTH; -} -else -{ - define symbol CS0_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS2_SPACE_START)) -{ - define symbol CS2_SPACE_PRV_START = CS2_SPACE_START; -} -else -{ - define symbol CS2_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(CS2_SPACE_LENGTH)) -{ - define symbol CS2_SPACE_PRV_LENGTH = CS2_SPACE_LENGTH; -} -else -{ - define symbol CS2_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS3_SPACE_START)) -{ - define symbol CS3_SPACE_PRV_START = CS3_SPACE_START; -} -else -{ - define symbol CS3_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(CS3_SPACE_LENGTH)) -{ - define symbol CS3_SPACE_PRV_LENGTH = CS3_SPACE_LENGTH; -} -else -{ - define symbol CS3_SPACE_PRV_LENGTH = 0; -} - -if (isdefinedsymbol(CS5_SPACE_START)) -{ - define symbol CS5_SPACE_PRV_START = CS5_SPACE_START; -} -else -{ - define symbol CS5_SPACE_PRV_START = 0; -} - -if (isdefinedsymbol(CS5_SPACE_LENGTH)) -{ - define symbol CS5_SPACE_PRV_LENGTH = CS5_SPACE_LENGTH; -} -else -{ - define symbol CS5_SPACE_PRV_LENGTH = 0; -} - -define symbol SYSTEM_RAM_END_OFFSET = 0x00048000; -define symbol FLASH_ADDRESS = xSPI0_CS0_SPACE_PRV_START; - -/* -define symbol INTVEC_ADDRESS = ATCM_PRV_START; -define symbol RAM_ADDRESS = (ATCM_PRV_START + 0x100); -define symbol RAM_END_ADDRESS = (ATCM_PRV_START + ATCM_PRV_LENGTH - 1); -define symbol LOADER_STACK_ADDRESS = (BTCM_PRV_START + 0x2000); -define symbol LOADER_STACK_END_ADDRESS = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1); -define symbol DATA_NONCACHE_OFFSET = 0x00048000; -define symbol DATA_NONCACHE_END_OFFSET = 0x00044000; -define symbol DMAC_LINK_MODE_OFFSET = 0x00044000; -define symbol DMAC_LINK_MODE_END_OFFSET = 0x00040000; -define symbol NONCACHE_BUFFER_OFFSET = 0x00020000; -define symbol NONCACHE_BUFFER_END_OFFSET = 0; -*/ -/************* Override define symbol to place EtherCAT protocol into SystemRAM ************/ -define symbol INTVEC_ADDRESS = SYSTEM_RAM_PRV_START; -define symbol RAM_ADDRESS = (SYSTEM_RAM_PRV_START + 0x100); -define symbol RAM_END_ADDRESS = (SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - 1); -define symbol LOADER_STACK_ADDRESS = (BTCM_PRV_START + 0x2000); -define symbol LOADER_STACK_END_ADDRESS = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1); -define symbol DATA_NONCACHE_OFFSET = 0x00048000; -define symbol DATA_NONCACHE_END_OFFSET = 0x00044000; -define symbol DMAC_LINK_MODE_OFFSET = 0x00044000; -define symbol DMAC_LINK_MODE_END_OFFSET = 0x00040000; -define symbol NONCACHE_BUFFER_OFFSET = 0x00020000; -define symbol NONCACHE_BUFFER_END_OFFSET = 0; -/*********************************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = INTVEC_ADDRESS; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = FLASH_ADDRESS + 0x20100; -define symbol __ICFEDIT_region_ROM_end__ = FLASH_ADDRESS + 0x6FFFF; -define symbol __ICFEDIT_region_RAM_start__ = RAM_ADDRESS; -define symbol __ICFEDIT_region_RAM_end__ = RAM_END_ADDRESS; -/**** End of ICF editor section. ###ICF###*/ - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; - -define symbol __region_D_LOADER_STACK_start__ = LOADER_STACK_ADDRESS; -define symbol __region_D_LOADER_STACK_end__ = LOADER_STACK_END_ADDRESS; - -define symbol __region_DATA_NONCACHE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_OFFSET; -define symbol __region_DATA_NONCACHE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_END_OFFSET - 1; -define symbol __region_DMAC_LINK_MODE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_OFFSET; -define symbol __region_DMAC_LINK_MODE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_END_OFFSET - 1; -define symbol __region_SHARED_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00040000; -define symbol __region_SHARED_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00020000 - 1; -define symbol __region_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_OFFSET; -define symbol __region_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_END_OFFSET - 1; - -define symbol __region_ATCM_start__ = ATCM_PRV_START; -define symbol __region_ATCM_end__ = ATCM_PRV_START + ATCM_PRV_LENGTH - 1; -define symbol __region_BTCM_start__ = BTCM_PRV_START; -define symbol __region_BTCM_end__ = BTCM_PRV_START + BTCM_PRV_LENGTH - 1; -define symbol __region_SYSTEM_RAM_start__ = SYSTEM_RAM_PRV_START; -define symbol __region_SYSTEM_RAM_end__ = SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; -define symbol __region_SYSTEM_RAM_MIRROR_start__ = SYSTEM_RAM_MIRROR_PRV_START; -define symbol __region_SYSTEM_RAM_MIRROR_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; - -define symbol __region_XSPI0_CS0_MIRROR_start__ = xSPI0_CS0_SPACE_MIRROR_PRV_START; -define symbol __region_XSPI0_CS0_MIRROR_end__ = xSPI0_CS0_SPACE_MIRROR_PRV_START + xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_XSPI0_CS1_MIRROR_start__ = xSPI0_CS1_SPACE_MIRROR_PRV_START; -define symbol __region_XSPI0_CS1_MIRROR_end__ = xSPI0_CS1_SPACE_MIRROR_PRV_START + xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_XSPI1_CS0_MIRROR_start__ = xSPI1_CS0_SPACE_MIRROR_PRV_START; -define symbol __region_XSPI1_CS0_MIRROR_end__ = xSPI1_CS0_SPACE_MIRROR_PRV_START + xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_XSPI1_CS1_MIRROR_start__ = xSPI1_CS1_SPACE_MIRROR_PRV_START; -define symbol __region_XSPI1_CS1_MIRROR_end__ = xSPI1_CS1_SPACE_MIRROR_PRV_START + xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_CS0_MIRROR_start__ = CS0_SPACE_MIRROR_PRV_START; -define symbol __region_CS0_MIRROR_end__ = CS0_SPACE_MIRROR_PRV_START + CS0_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_CS2_MIRROR_start__ = CS2_SPACE_MIRROR_PRV_START; -define symbol __region_CS2_MIRROR_end__ = CS2_SPACE_MIRROR_PRV_START + CS2_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_CS3_MIRROR_start__ = CS3_SPACE_MIRROR_PRV_START; -define symbol __region_CS3_MIRROR_end__ = CS3_SPACE_MIRROR_PRV_START + CS3_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_CS5_MIRROR_start__ = CS5_SPACE_MIRROR_PRV_START; -define symbol __region_CS5_MIRROR_end__ = CS5_SPACE_MIRROR_PRV_START + CS5_SPACE_MIRROR_PRV_LENGTH - 1; -define symbol __region_XSPI0_CS0_start__ = xSPI0_CS0_SPACE_PRV_START; -define symbol __region_XSPI0_CS0_end__ = xSPI0_CS0_SPACE_PRV_START + xSPI0_CS0_SPACE_PRV_LENGTH - 1; -define symbol __region_XSPI0_CS1_start__ = xSPI0_CS1_SPACE_PRV_START; -define symbol __region_XSPI0_CS1_end__ = xSPI0_CS1_SPACE_PRV_START + xSPI0_CS1_SPACE_PRV_LENGTH - 1; -define symbol __region_XSPI1_CS0_start__ = xSPI1_CS0_SPACE_PRV_START; -define symbol __region_XSPI1_CS0_end__ = xSPI1_CS0_SPACE_PRV_START + xSPI1_CS0_SPACE_PRV_LENGTH - 1; -define symbol __region_XSPI1_CS1_start__ = xSPI1_CS1_SPACE_PRV_START; -define symbol __region_XSPI1_CS1_end__ = xSPI1_CS1_SPACE_PRV_START + xSPI1_CS1_SPACE_PRV_LENGTH - 1; -define symbol __region_CS0_start__ = CS0_SPACE_PRV_START; -define symbol __region_CS0_end__ = CS0_SPACE_PRV_START + CS0_SPACE_PRV_LENGTH - 1; -define symbol __region_CS2_start__ = CS2_SPACE_PRV_START; -define symbol __region_CS2_end__ = CS2_SPACE_PRV_START + CS2_SPACE_PRV_LENGTH - 1; -define symbol __region_CS3_start__ = CS3_SPACE_PRV_START; -define symbol __region_CS3_end__ = CS3_SPACE_PRV_START + CS3_SPACE_PRV_LENGTH - 1; -define symbol __region_CS5_start__ = CS5_SPACE_PRV_START; -define symbol __region_CS5_end__ = CS5_SPACE_PRV_START + CS5_SPACE_PRV_LENGTH - 1; - -/************** SPI boot mode setting **************/ -define symbol __region_LDR_PARAM_start__ = FLASH_ADDRESS; -define symbol __region_LDR_PARAM_end__ = FLASH_ADDRESS + 0x0000004B; -define symbol __region_S_LOADER_STACK_start__ = FLASH_ADDRESS + 0x0000004C; -define symbol __region_S_LOADER_STACK_end__ = FLASH_ADDRESS + 0x0000804B; - -define symbol __region_S_intvec_start__ = FLASH_ADDRESS + 0x20000; -define symbol __region_S_intvec_end__ = FLASH_ADDRESS + 0x200FF; -define symbol __region_S_RAM_start__ = FLASH_ADDRESS + 0x70000; -define symbol __region_S_RAM_end__ = FLASH_ADDRESS + 0x7FFFF; -/****************************************************/ - -define region D_LOADER_STACK_region = mem:[from __region_D_LOADER_STACK_start__ to __region_D_LOADER_STACK_end__]; - -define region LDR_PARAM_region = mem:[from __region_LDR_PARAM_start__ to __region_LDR_PARAM_end__]; -define region S_LOADER_STACK_region = mem:[from __region_S_LOADER_STACK_start__ to __region_S_LOADER_STACK_end__]; - -define region S_intvec_region = mem:[from __region_S_intvec_start__ to __region_S_intvec_end__]; -define region S_RAM_region = mem:[from __region_S_RAM_start__ to __region_S_RAM_end__]; - -define region DATA_NONCACHE_region = mem:[from __region_DATA_NONCACHE_start__ to __region_DATA_NONCACHE_end__]; -define region DMAC_LINK_MODE_region = mem:[from __region_DMAC_LINK_MODE_start__ to __region_DMAC_LINK_MODE_end__]; -define region SHARED_NONCACHE_BUFFER_region = mem:[from __region_SHARED_NONCACHE_BUFFER_start__ to __region_SHARED_NONCACHE_BUFFER_end__]; -define region NONCACHE_BUFFER_region = mem:[from __region_NONCACHE_BUFFER_start__ to __region_NONCACHE_BUFFER_end__]; - -define region ATCM_region = mem:[from __region_ATCM_start__ to __region_ATCM_end__ ]; -define region BTCM_region = mem:[from __region_BTCM_start__ to __region_BTCM_end__ ]; -define region SYSTEM_RAM_region = mem:[from __region_SYSTEM_RAM_start__ to __region_SYSTEM_RAM_end__ ]; -define region SYSTEM_RAM_MIRROR_region = mem:[from __region_SYSTEM_RAM_MIRROR_start__ to __region_SYSTEM_RAM_MIRROR_end__ ]; -define region XSPI0_CS0_MIRROR_region = mem:[from __region_XSPI0_CS0_MIRROR_start__ to __region_XSPI0_CS0_MIRROR_end__ ]; -define region XSPI0_CS1_MIRROR_region = mem:[from __region_XSPI0_CS1_MIRROR_start__ to __region_XSPI0_CS1_MIRROR_end__ ]; -define region XSPI1_CS0_MIRROR_region = mem:[from __region_XSPI1_CS0_MIRROR_start__ to __region_XSPI1_CS0_MIRROR_end__ ]; -define region XSPI1_CS1_MIRROR_region = mem:[from __region_XSPI1_CS1_MIRROR_start__ to __region_XSPI1_CS1_MIRROR_end__ ]; -define region CS0_MIRROR_region = mem:[from __region_CS0_MIRROR_start__ to __region_CS0_MIRROR_end__ ]; -define region CS2_MIRROR_region = mem:[from __region_CS2_MIRROR_start__ to __region_CS2_MIRROR_end__ ]; -define region CS3_MIRROR_region = mem:[from __region_CS3_MIRROR_start__ to __region_CS3_MIRROR_end__ ]; -define region CS5_MIRROR_region = mem:[from __region_CS5_MIRROR_start__ to __region_CS5_MIRROR_end__ ]; -define region XSPI0_CS0_region = mem:[from __region_XSPI0_CS0_start__ to __region_XSPI0_CS0_end__ ]; -define region XSPI0_CS1_region = mem:[from __region_XSPI0_CS1_start__ to __region_XSPI0_CS1_end__ ]; -define region XSPI1_CS0_region = mem:[from __region_XSPI1_CS0_start__ to __region_XSPI1_CS0_end__ ]; -define region XSPI1_CS1_region = mem:[from __region_XSPI1_CS1_start__ to __region_XSPI1_CS1_end__ ]; -define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__ ]; -define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__ ]; -define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__ ]; -define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__ ]; - -define block LDR_PRG_RBLOCK with fixed order - { ro code section .loader_text_init object startup_core.o, - ro code object startup_core.o, - ro code object system_core.o, - ro code object startup.o, - ro code object system.o, - ro code object bsp_clocks.o, - ro code object bsp_irq_core.o, - ro code object bsp_irq.o, - ro code object bsp_register_protection.o, - ro code object r_ioport.o, - ro code object bsp_cache.o, - ro code section .warm_start_init } - except { ro code section .intvec_init, - ro code section .reset_handler_init }; -define block LDR_PRG_WBLOCK with fixed order - { rw code section .loader_text object startup_core.o, - rw code object startup_core.o, - rw code object system_core.o, - rw code object startup.o, - rw code object system.o, - rw code object bsp_clocks.o, - rw code object bsp_irq_core.o, - rw code object bsp_irq.o, - rw code object bsp_register_protection.o, - rw code object r_ioport.o, - rw code object bsp_cache.o, - rw code section .warm_start } - except { rw code section .intvec, - rw code section .reset_handler }; -define block LDR_DATA_ZBLOCK with alignment = 4 - { section .bss object startup_core.o, - section .bss object system_core.o, - section .bss object startup.o, - section .bss object system.o, - section .bss object bsp_clocks.o, - section .bss object bsp_irq_core.o, - section .bss object bsp_irq.o, - section .bss object bsp_register_protection.o, - section .bss object r_ioport.o, - section .bss object bsp_cache.o, - section .bss object bsp_io.o }; -define block LDR_DATA_RBLOCK with fixed order, alignment = 4 - { section .data_init object startup_core.o, - section .data_init object system_core.o, - section .data_init object startup.o, - section .data_init object system.o, - section .data_init object bsp_clocks.o, - section .data_init object bsp_irq_core.o, - section .data_init object bsp_irq.o, - section .data_init object bsp_register_protection.o, - section .data_init object r_ioport.o, - section .data_init object bsp_cache.o, - section .rodata_init object system_core.o }; -define block LDR_DATA_WBLOCK with fixed order, alignment = 4 - { section .data object startup_core.o, - section .data object system_core.o, - section .data object startup.o, - section .data object system.o, - section .data object bsp_clocks.o, - section .data object bsp_irq_core.o, - section .data object bsp_irq.o, - section .data object bsp_register_protection.o, - section .data object r_ioport.o, - section .data object bsp_cache.o, - section .rodata object system_core.o }; - -define block HEAP_BLOCK with alignment = 8 { rw section HEAP }; -define block THREAD_STACK with alignment = 8 { rw section .stack* }; -define block SYS_STACK with alignment = 8 { rw section .sys_stack }; -define block SVC_STACK with alignment = 8 { rw section .svc_stack }; -define block IRQ_STACK with alignment = 8 { rw section .irq_stack }; -define block FIQ_STACK with alignment = 8 { rw section .fiq_stack }; -define block UND_STACK with alignment = 8 { rw section .und_stack }; -define block ABT_STACK with alignment = 8 { rw section .abt_stack }; - -define block VECTOR_RBLOCK with alignment = 32 { ro code section .intvec_init}; -define block VECTOR_WBLOCK with alignment = 32 { rw code section .intvec}; -define block USER_PRG_RBLOCK with alignment = 4 { ro code }; -define block USER_PRG_WBLOCK with alignment = 4 { rw code }; -define block USER_DATA_ZBLOCK with alignment = 4 { section .bss }; -define block USER_DATA_RBLOCK with fixed order, alignment = 4 - { section .data_init, - section __DLIB_PERTHREAD_init, - section .rodata_init, - section .version_init }; -define block USER_DATA_WBLOCK with fixed order, alignment = 4 - { section .data, - section __DLIB_PERTHREAD, - section .rodata, - section .version }; -define block USER_DATA_NONCACHE_RBLOCK with alignment = 4 { section .data_noncache_init }; -define block USER_DATA_NONCACHE_WBLOCK with alignment = 4 { section .data_noncache }; -define block DMAC_LINK_MODE_ZBLOCK with alignment = 4 { section .dmac_link_mode* }; -define block SHARED_NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .shared_noncache_buffer* }; -define block NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .noncache_buffer* }; - -initialize manually { ro code object startup_core.o, - ro code object system_core.o, - ro code object startup.o, - ro code object system.o, - ro code object bsp_clocks.o, - ro code object bsp_irq_core.o, - ro code object bsp_irq.o, - ro code object bsp_register_protection.o, - ro code object r_ioport.o, - ro code object bsp_cache.o, - ro code section .intvec, - ro code section .reset_handler, - ro code section .warm_start, - ro code, - section .data, - section __DLIB_PERTHREAD, - section .rodata, - section .version, - section .data_noncache }; - -do not initialize { section .noinit, - section .bss, - section .dmac_link_mode*, - section .shared_noncache_buffer*, - section .noncache_buffer*, - rw section HEAP, - rw section .stack*, - rw section .sys_stack, - rw section .svc_stack, - rw section .irq_stack, - rw section .fiq_stack, - rw section .und_stack, - rw section .abt_stack }; - -place at address mem: __ICFEDIT_intvec_start__ { block VECTOR_WBLOCK }; - -place in LDR_PARAM_region { readonly section .loader_param }; -place at start of S_LOADER_STACK_region { block LDR_PRG_RBLOCK }; -place in S_LOADER_STACK_region { section LDR_DATA_RBLOCK, block LDR_DATA_RBLOCK }; -place in S_intvec_region { block VECTOR_RBLOCK }; -place in ROM_region { block USER_PRG_RBLOCK, readonly }; -place in S_RAM_region { block USER_DATA_RBLOCK, block USER_DATA_NONCACHE_RBLOCK }; - -place at start of D_LOADER_STACK_region { block LDR_PRG_WBLOCK }; -place in D_LOADER_STACK_region { section LDR_DATA_WBLOCK, block LDR_DATA_WBLOCK, - section LDR_DATA_ZBLOCK, block LDR_DATA_ZBLOCK }; -place in D_LOADER_STACK_region { section SYS_STACK, block SYS_STACK, - section SVC_STACK, block SVC_STACK, - section IRQ_STACK, block IRQ_STACK, - section FIQ_STACK, block FIQ_STACK, - section UND_STACK, block UND_STACK, - section ABT_STACK, block ABT_STACK }; -place in RAM_region { block USER_PRG_WBLOCK }; -place in RAM_region { readwrite, last block CSTACK }; -place in RAM_region { block USER_DATA_WBLOCK, - block USER_DATA_ZBLOCK }; -place in RAM_region { section HEAP_BLOCK, block HEAP_BLOCK, - section THREAD_STACK, block THREAD_STACK }; - -place in DATA_NONCACHE_region { block USER_DATA_NONCACHE_WBLOCK }; -place in DMAC_LINK_MODE_region { block DMAC_LINK_MODE_ZBLOCK }; -place in SHARED_NONCACHE_BUFFER_region { block SHARED_NONCACHE_BUFFER_ZBLOCK }; -place in NONCACHE_BUFFER_region { block NONCACHE_BUFFER_ZBLOCK }; -place in ATCM_region { }; -place in BTCM_region { }; -place in SYSTEM_RAM_region { }; -place in SYSTEM_RAM_MIRROR_region { }; -place in XSPI0_CS0_MIRROR_region { }; -place in XSPI0_CS1_MIRROR_region { }; -place in XSPI1_CS0_MIRROR_region { }; -place in XSPI1_CS1_MIRROR_region { }; -place in CS0_MIRROR_region { }; -place in CS2_MIRROR_region { }; -place in CS3_MIRROR_region { }; -place in CS5_MIRROR_region { }; -place in XSPI0_CS0_region { }; -place in XSPI0_CS1_region { }; -place in XSPI1_CS0_region { }; -place in XSPI1_CS1_region { }; -place in CS0_region { }; -place in CS2_region { }; -place in CS3_region { }; -place in CS5_region { }; diff --git a/bsp/renesas/rzn2l_rsk/script/memory_regions.ld b/bsp/renesas/rzn2l_rsk/script/memory_regions.ld deleted file mode 100644 index 227ab3ebb1..0000000000 --- a/bsp/renesas/rzn2l_rsk/script/memory_regions.ld +++ /dev/null @@ -1,38 +0,0 @@ - - /* generated memory regions file - do not edit */ - ATCM_START = 0x00000000; - ATCM_LENGTH = 0x20000; - BTCM_START = 0x00100000; - BTCM_LENGTH = 0x20000; - SYSTEM_RAM_START = 0x10000000; - SYSTEM_RAM_LENGTH = 0x180000; - SYSTEM_RAM_MIRROR_START = 0x30000000; - SYSTEM_RAM_MIRROR_LENGTH = 0x180000; - xSPI0_CS0_SPACE_MIRROR_START = 0x40000000; - xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000; - xSPI0_CS1_SPACE_MIRROR_START = 0x44000000; - xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000; - xSPI1_CS0_SPACE_MIRROR_START = 0x48000000; - xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000; - CS0_SPACE_MIRROR_START = 0x50000000; - CS0_SPACE_MIRROR_LENGTH = 0x4000000; - CS2_SPACE_MIRROR_START = 0x54000000; - CS2_SPACE_MIRROR_LENGTH = 0x4000000; - CS3_SPACE_MIRROR_START = 0x58000000; - CS3_SPACE_MIRROR_LENGTH = 0x4000000; - CS5_SPACE_MIRROR_START = 0x5C000000; - CS5_SPACE_MIRROR_LENGTH = 0x4000000; - xSPI0_CS0_SPACE_START = 0x60000000; - xSPI0_CS0_SPACE_LENGTH = 0x4000000; - xSPI0_CS1_SPACE_START = 0x64000000; - xSPI0_CS1_SPACE_LENGTH = 0x4000000; - xSPI1_CS0_SPACE_START = 0x68000000; - xSPI1_CS0_SPACE_LENGTH = 0x4000000; - CS0_SPACE_START = 0x70000000; - CS0_SPACE_LENGTH = 0x4000000; - CS2_SPACE_START = 0x74000000; - CS2_SPACE_LENGTH = 0x4000000; - CS3_SPACE_START = 0x78000000; - CS3_SPACE_LENGTH = 0x4000000; - CS5_SPACE_START = 0x7C000000; - CS5_SPACE_LENGTH = 0x4000000; diff --git a/libcpu/arm/cortex-r52/context_gcc.S b/libcpu/arm/cortex-r52/context_gcc.S index e95c631eef..1bd581e9ee 100644 --- a/libcpu/arm/cortex-r52/context_gcc.S +++ b/libcpu/arm/cortex-r52/context_gcc.S @@ -8,7 +8,6 @@ * 2024-03-01 Wangyuqiang first version */ -#include "rtconfig.h" .syntax unified .text