[bsp][hc32]优化can驱动和pwm驱动 (#8217)
**为什么提交这份PR (why to submit this PR)** 1. hc32驱动函数和rtt函数声明之间的参数类型不一致,在mdk编译时产生警告。 2. hc32的can设备,在注册时就把can中断使能了。导致can设备在打开前,就会产生中断。 3. hc32的pwm驱动,不支持PWM_CMD_SET_PERIOD和PWM_CMD_SET_PULSE指令,导致rt_pwm_set_pulse()函数返回失败。 **你的解决方案是什么 (what is your solution)** 1. 修改hc32驱动函数参数类型和声明一致。 2. 注册can设备时主动禁止can中断,因为打开设备时会主动打开中断。 3. 修改pwm驱动,增加PWM_CMD_SET_PERIOD和PWM_CMD_SET_PULSE指令支持。
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@ -151,14 +151,14 @@ static void _adc_internal_trigger1_set(adc_device *p_adc_dev)
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AOS_SetTriggerEventSrc(u32TriggerSel, p_adc_dev->init.internal_trig1_sel);
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}
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static rt_err_t _adc_enable(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
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static rt_err_t _adc_enable(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
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{
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adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc);
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ADC_ChCmd(p_adc_dev->instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled);
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return 0;
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}
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static rt_err_t _adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
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static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
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{
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rt_err_t rt_ret = -RT_ERROR;
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@ -362,7 +362,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
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return RT_EOK;
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}
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static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
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static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
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{
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struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
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stc_can_tx_frame_t stc_tx_frame = {0};
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@ -398,7 +398,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t
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return RT_EOK;
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}
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static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
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static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
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{
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int32_t ll_ret;
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struct rt_can_msg *pmsg;
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@ -655,6 +655,7 @@ int rt_hw_can_init(void)
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/* register CAN device */
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rt_hw_board_can_init(g_can_dev_array[i].instance);
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CAN_IntCmd(g_can_dev_array[i].instance, CAN_INT_ALL, DISABLE);
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rt_hw_can_register(&g_can_dev_array[i].rt_can,
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g_can_dev_array[i].init.name,
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&_can_ops,
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@ -160,13 +160,12 @@ static rt_err_t drv_pwm_set(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration
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rt_uint32_t u32clkFreq;
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rt_uint64_t u64clk_ns;
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rt_uint64_t u64val;
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//
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u32clkFreq = get_tmra_clk_freq(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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u64val = (rt_uint64_t)configuration->period / u64clk_ns;
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if ((configuration->period <= u64clk_ns) || (u64val > 0xFFFF))
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{
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// clk not match, need change div
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/* clk not match, need change div */
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uint32_t div_bit;
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u32clkFreq = get_tmra_clk_freq_not_div(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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@ -177,7 +176,6 @@ static rt_err_t drv_pwm_set(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration
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u64val /= 2;
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}
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if (div_bit > 10) return -RT_ERROR;
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//
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TMRA_SetClockDiv(TMRAx, div_bit << TMRA_BCSTR_CKDIV_POS);
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u32clkFreq = get_tmra_clk_freq(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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@ -187,13 +185,51 @@ static rt_err_t drv_pwm_set(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set_period(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration)
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{
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rt_uint32_t u32clkFreq;
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rt_uint64_t u64clk_ns;
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rt_uint64_t u64val;
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u32clkFreq = get_tmra_clk_freq(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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u64val = (rt_uint64_t)configuration->period / u64clk_ns;
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if ((configuration->period <= u64clk_ns) || (u64val > 0xFFFF))
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{
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/* clk not match, need change div */
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uint32_t div_bit;
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u32clkFreq = get_tmra_clk_freq_not_div(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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u64val = (rt_uint64_t)configuration->period / u64clk_ns;
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for (div_bit=0; div_bit<= 10; div_bit++)
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{
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if (u64val < 0xFFFF) break;
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u64val /= 2;
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}
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if (div_bit > 10) return -RT_ERROR;
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TMRA_SetClockDiv(TMRAx, div_bit << TMRA_BCSTR_CKDIV_POS);
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u32clkFreq = get_tmra_clk_freq(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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}
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TMRA_SetPeriodValue(TMRAx, configuration->period / u64clk_ns);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set_pulse(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration)
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{
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rt_uint32_t u32clkFreq;
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rt_uint64_t u64clk_ns;
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u32clkFreq = get_tmra_clk_freq(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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TMRA_SetCompareValue(TMRAx, configuration->channel, configuration->pulse / u64clk_ns);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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struct hc32_pwm_tmra *pwm;
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pwm = rt_container_of(device, struct hc32_pwm_tmra, pwm_device);
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CM_TMRA_TypeDef *TMRAx = pwm->instance;
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switch (cmd)
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{
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case PWMN_CMD_ENABLE:
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@ -208,6 +244,10 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
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return drv_pwm_set(TMRAx, configuration);
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case PWM_CMD_GET:
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return drv_pwm_get(TMRAx, configuration);
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case PWM_CMD_SET_PERIOD:
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return drv_pwm_set_period(TMRAx, configuration);
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case PWM_CMD_SET_PULSE:
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return drv_pwm_set_pulse(TMRAx, configuration);
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default:
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return -RT_EINVAL;
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}
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@ -217,7 +257,6 @@ static rt_err_t _pwm_tmra_init(struct hc32_pwm_tmra *device)
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{
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CM_TMRA_TypeDef *TMRAx;
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uint32_t i;
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//
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RT_ASSERT(device != RT_NULL);
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TMRAx = device->instance;
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TMRA_Init(TMRAx, &device->stcTmraInit);
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@ -392,7 +392,7 @@ static void hc32_spi_enable(CM_SPI_TypeDef *SPIx)
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}
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}
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static rt_uint32_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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int32_t state;
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rt_size_t message_length, already_send_length;
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@ -450,7 +450,6 @@ static rt_uint32_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mes
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{
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recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length;
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}
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if (message->send_buf && message->recv_buf)
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{
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if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX))
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