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[qemu] format codes

This commit is contained in:
Meco Man 2021-12-15 01:49:09 -05:00
parent 5f6729e1b8
commit 79e3d7f48e
23 changed files with 88 additions and 88 deletions
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2
bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

56
bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -12,33 +12,33 @@
#define __DRV_AC97_H__
/* Register offsets */
#define AC97_RESET 0x00
#define AC97_MASTER 0x02
#define AC97_HEADPHONE 0x04
#define AC97_MASTER_MONO 0x06
#define AC97_MASTER_TONE 0x08
#define AC97_PC_BEEP 0x0A //mixer volume
#define AC97_PHONE 0x0C
#define AC97_MIC 0x0E //qwert db
#define AC97_LINE 0x10
#define AC97_CD 0x12
#define AC97_VIDEO 0x14
#define AC97_AUX 0x16
#define AC97_PCM 0x18
#define AC97_REC_SEL 0x1A //0 represent mic
#define AC97_REC_GAIN 0x1C
#define AC97_REC_GAIN_MIC 0x1E
#define AC97_GENERAL_PURPOSE 0x20
#define AC97_3D_CONTROL 0x22
#define AC97_INT_PAGING 0x24 //qwert
#define AC97_POWERDOWN 0x26
#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */
#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */
#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */
#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */
#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */
#define AC97_DAC_SLOT_MAP 0x6C
#define AC97_ADC_SLOT_MAP 0x6E
#define AC97_RESET 0x00
#define AC97_MASTER 0x02
#define AC97_HEADPHONE 0x04
#define AC97_MASTER_MONO 0x06
#define AC97_MASTER_TONE 0x08
#define AC97_PC_BEEP 0x0A //mixer volume
#define AC97_PHONE 0x0C
#define AC97_MIC 0x0E //qwert db
#define AC97_LINE 0x10
#define AC97_CD 0x12
#define AC97_VIDEO 0x14
#define AC97_AUX 0x16
#define AC97_PCM 0x18
#define AC97_REC_SEL 0x1A //0 represent mic
#define AC97_REC_GAIN 0x1C
#define AC97_REC_GAIN_MIC 0x1E
#define AC97_GENERAL_PURPOSE 0x20
#define AC97_3D_CONTROL 0x22
#define AC97_INT_PAGING 0x24 //qwert
#define AC97_POWERDOWN 0x26
#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */
#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */
#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */
#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */
#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */
#define AC97_DAC_SLOT_MAP 0x6C
#define AC97_ADC_SLOT_MAP 0x6E
void ac97_reset(void);
rt_err_t ac97_set_vol(int vol);

2
bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

52
bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -14,11 +14,11 @@
#define PL041_BASE_ADDR (0x10004000)
/* offsets in CTRL_CH */
#define AACI_RXCR 0x00 /* 29 bits Control Rx FIFO */
#define AACI_TXCR 0x04 /* 17 bits Control Tx FIFO */
#define AACI_SR 0x08 /* 12 bits Status */
#define AACI_ISR 0x0C /* 7 bits Int Status */
#define AACI_IE 0x10 /* 7 bits Int Enable */
#define AACI_RXCR 0x00 /* 29 bits Control Rx FIFO */
#define AACI_TXCR 0x04 /* 17 bits Control Tx FIFO */
#define AACI_SR 0x08 /* 12 bits Status */
#define AACI_ISR 0x0C /* 7 bits Int Status */
#define AACI_IE 0x10 /* 7 bits Int Enable */
/* both for AACI_RXCR and AACI_TXCR */
#define AACI_CR_FEN (1 << 16) /* fifo enable */
@ -39,7 +39,7 @@
#define AACI_CR_SL3 (1 << 3)
#define AACI_CR_SL2 (1 << 2)
#define AACI_CR_SL1 (1 << 1)
#define AACI_CR_EN (1 << 0) /* receive enable */
#define AACI_CR_EN (1 << 0) /* receive enable */
/* status register bits */
#define AACI_SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
@ -66,29 +66,29 @@
/* interrupt enable */
#define AACI_IE_RXTOIE (1 << 6) /*rx timeout interrupt enable*/
#define AACI_IE_URIE (1 << 5) /*Transmit underrun interrupt enable*/
#define AACI_IE_ORIE (1 << 4) /*Overrun receive interrupt enable*/
#define AACI_IE_ORIE (1 << 4) /*Overrun receive interrupt enable*/
#define AACI_IE_RXIE (1 << 3) /*Receive interrupt enable*/
#define AACI_IE_TXIE (1 << 2) /*Transmit interrupt enable*/
#define AACI_IE_RXTIE (1 << 1) /*Receive timeout interrupt enable*/
#define AACI_IE_TXCIE (1 << 0) /*Transmit complete interrupt enable*/
#define AACI_IE_TXCIE (1 << 0) /*Transmit complete interrupt enable*/
/* interrupt status */
#define AACI_ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
#define AACI_ISR_UR (1 << 5) /* tx fifo underrun */
#define AACI_ISR_OR (1 << 4) /* rx fifo overrun */
#define AACI_ISR_RX (1 << 3) /* rx interrupt status */
#define AACI_ISR_TX (1 << 2) /* tx interrupt status */
#define AACI_ISR_RXTO (1 << 1) /* rx timeout */
#define AACI_ISR_TXC (1 << 0) /* tx complete */
#define AACI_ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
#define AACI_ISR_UR (1 << 5) /* tx fifo underrun */
#define AACI_ISR_OR (1 << 4) /* rx fifo overrun */
#define AACI_ISR_RX (1 << 3) /* rx interrupt status */
#define AACI_ISR_TX (1 << 2) /* tx interrupt status */
#define AACI_ISR_RXTO (1 << 1) /* rx timeout */
#define AACI_ISR_TXC (1 << 0) /* tx complete */
/* interrupt enable */
#define AACI_IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
#define AACI_IE_UR (1 << 5) /* tx fifo underrun */
#define AACI_IE_OR (1 << 4) /* rx fifo overrun */
#define AACI_IE_RX (1 << 3) /* rx interrupt status */
#define AACI_IE_TX (1 << 2) /* tx interrupt status */
#define AACI_IE_RXTO (1 << 1) /* rx timeout */
#define AACI_IE_TXC (1 << 0) /* tx complete */
#define AACI_IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
#define AACI_IE_UR (1 << 5) /* tx fifo underrun */
#define AACI_IE_OR (1 << 4) /* rx fifo overrun */
#define AACI_IE_RX (1 << 3) /* rx interrupt status */
#define AACI_IE_TX (1 << 2) /* tx interrupt status */
#define AACI_IE_RXTO (1 << 1) /* rx timeout */
#define AACI_IE_TXC (1 << 0) /* tx complete */
/* slot flag register bits */
#define AACI_SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
@ -120,7 +120,7 @@
#define AACI_ICLR_RXOEC2 (1 << 2) /* Receive overrun error clear */
#define AACI_ICLR_RXOEC1 (1 << 1) /* Receive overrun error clear */
#define AACI_ICLR_WISC (1 << 0) /* Wake-up interrupt status clear */
/* Main control register bits AACI_MAINCR */
#define AACI_MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */
#define AACI_MAINCR_DMAEN (1 << 9) /* dma enable */
@ -141,8 +141,8 @@
#define SYNC_FORCE (1 << 0)
/* Main flag register bits. P66 */
#define MAINFR_TXB (1 << 1) /* transmit busy */
#define MAINFR_RXB (1 << 0) /* receive busy */
#define MAINFR_TXB (1 << 1) /* transmit busy */
#define MAINFR_RXB (1 << 0) /* receive busy */
#define PL041_CHANNEL_LEFT_DAC (0x1 << 3)
#define PL041_CHANNEL_RIGHT_DAC (0x1 << 3)

4
bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes

4
bsp/qemu-vexpress-a9/drivers/audio/drv_sound.h
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes

2
bsp/qemu-vexpress-a9/drivers/board.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/qemu-vexpress-a9/drivers/board.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/qemu-vexpress-a9/drivers/drv_clcd.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -88,7 +88,7 @@ static rt_err_t drv_clcd_control(struct rt_device *device, int cmd, void *args)
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops clcd_ops =
const static struct rt_device_ops clcd_ops =
{
drv_clcd_init,
RT_NULL,

2
bsp/qemu-vexpress-a9/drivers/drv_clcd.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/qemu-vexpress-a9/drivers/drv_keyboard.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -141,7 +141,7 @@ static const struct keymap map[] = {
{0x74, RTGUIK_RIGHT, 0, "RIGHT" },
{0x0d, RTGUIK_TAB, 0, "TAB" },
{0x76, RTGUIK_ESCAPE, 0, "ESC" },
{0x37, RTGUIK_POWER, 0, "POWER" },
{0x37, RTGUIK_POWER, 0, "POWER" },
{0x5a, RTGUIK_KP_ENTER, 0, "ENTER"},
{0x66, RTGUIK_BACKSPACE, 0, "BACKSPACE"},
};
@ -433,12 +433,12 @@ int rt_hw_keyboard_init(void)
struct keyboard_pl050_pdata_t *pdat;
virtual_addr_t virt = (virtual_addr_t)KEYBOARD_ADDRESS;
int irq = KEYBOARD_IRQ_NUM;
id = (((read32(virt + 0xfec) & 0xff) << 24) |
((read32(virt + 0xfe8) & 0xff) << 16) |
((read32(virt + 0xfe4) & 0xff) << 8) |
((read32(virt + 0xfe0) & 0xff) << 0));
if(((id >> 12) & 0xff) != 0x41 || (id & 0xfff) != 0x050)
{
LOG_E("read id fail id:0x%08x", id);

2
bsp/qemu-vexpress-a9/drivers/drv_keyboard.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/qemu-vexpress-a9/drivers/drv_mouse.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/qemu-vexpress-a9/drivers/drv_mouse.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -12,4 +12,4 @@
int rt_hw_mouse_init(void);
#endif
#endif

6
bsp/qemu-vexpress-a9/drivers/drv_sdio.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -295,7 +295,7 @@ static rt_err_t sdhci_pl180_setclock(struct sdhci_t * sdhci, rt_uint32_t clock)
if(clock)
{
temp = read32(pdat->virt + PL180_CLOCK) | (0x1<<8);
temp = temp; // skip warning
temp = temp; // skip warning
write32(pdat->virt + PL180_CLOCK, 0x100);
}
else
@ -388,7 +388,7 @@ static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io
LOG_D("clock:%d bus_width:%d", io_cfg->clock, io_cfg->bus_width);
}
static const struct rt_mmcsd_host_ops ops =
static const struct rt_mmcsd_host_ops ops =
{
mmc_request_send,
mmc_set_iocfg,

2
bsp/qemu-vexpress-a9/drivers/drv_sdio.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

10
bsp/qemu-vexpress-a9/drivers/drv_timer.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -89,7 +89,7 @@ void timer_init(int timer, unsigned int preload)
{
uint32_t val;
if (timer == 0)
if (timer == 0)
{
/* Setup Timer0 for generating irq */
val = TIMER_CTRL(TIMER01_HW_BASE);
@ -101,8 +101,8 @@ void timer_init(int timer, unsigned int preload)
/* enable timer */
TIMER_CTRL(TIMER01_HW_BASE) |= TIMER_CTRL_ENABLE;
}
else
}
else
{
/* Setup Timer1 for generating irq */
val = TIMER_CTRL(TIMER23_HW_BASE);
@ -122,7 +122,7 @@ void timer_clear_pending(int timer)
if (timer == 0)
{
TIMER_INTCLR(TIMER01_HW_BASE) = 0x01;
}
}
else
{
TIMER_INTCLR(TIMER23_HW_BASE) = 0x01;

2
bsp/qemu-vexpress-a9/drivers/drv_timer.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/qemu-vexpress-a9/drivers/realview.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/qemu-vexpress-a9/drivers/secondary_cpu.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/qemu-vexpress-a9/drivers/serial.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/qemu-vexpress-a9/drivers/serial.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/qemu-vexpress-a9/drivers/vexpress_a9.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*