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Merge pull request #44 from RT-Thread/master 

update
This commit is contained in:
Meco Jianting Man 2021-04-22 12:27:28 +08:00 committed by GitHub
parent 09f04bee8f ed84d02eb3
commit 7935f892d2
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GPG Key ID: 4AEE18F83AFDEB23
12 changed files with 1033 additions and 1221 deletions
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192
bsp/qemu-vexpress-a9/drivers/drv_smc911x.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -46,12 +46,12 @@ int mdelay(int value)
#if defined (CONFIG_SMC911X_32_BIT)
rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
{
return *(volatile uint32_t*)(dev->iobase + offset);
return *(volatile uint32_t *)(dev->iobase + offset);
}
rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
{
*(volatile uint32_t*)(dev->iobase + offset) = val;
*(volatile uint32_t *)(dev->iobase + offset) = val;
}
#elif defined (CONFIG_SMC911X_16_BIT)
@ -78,47 +78,47 @@ struct chip_id
static const struct chip_id chip_ids[] =
{
{ CHIP_89218,"LAN89218" },
{ CHIP_9115, "LAN9115" },
{ CHIP_9116, "LAN9116" },
{ CHIP_9117, "LAN9117" },
{ CHIP_9118, "LAN9118" },
{ CHIP_9211, "LAN9211" },
{ CHIP_9215, "LAN9215" },
{ CHIP_9216, "LAN9216" },
{ CHIP_9217, "LAN9217" },
{ CHIP_9218, "LAN9218" },
{ CHIP_9220, "LAN9220" },
{ CHIP_9221, "LAN9221" },
{ LAN9118_ID_89218, "LAN89218" },
{ LAN9118_ID_9115, "LAN9115" },
{ LAN9118_ID_9116, "LAN9116" },
{ LAN9118_ID_9117, "LAN9117" },
{ LAN9118_ID_9118, "LAN9118" },
{ LAN9210_ID_9211, "LAN9211" },
{ LAN9218_ID_9215, "LAN9215" },
{ LAN9218_ID_9216, "LAN9216" },
{ LAN9218_ID_9217, "LAN9217" },
{ LAN9218_ID_9218, "LAN9218" },
{ LAN9220_ID_9220, "LAN9220" },
{ LAN9220_ID_9221, "LAN9221" },
{ 0, RT_NULL },
};
static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
{
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | LAN9118_MAC_CSR_CMD_R | reg);
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
return smc911x_reg_read(dev, MAC_CSR_DATA);
return smc911x_reg_read(dev, LAN9118_MAC_CSR_DATA);
}
static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
{
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
smc911x_reg_write(dev, MAC_CSR_DATA, data);
smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
smc911x_reg_write(dev, LAN9118_MAC_CSR_DATA, data);
smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | reg);
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
}
static int smc911x_detect_chip(struct eth_device_smc911x *dev)
{
unsigned long val, i;
val = smc911x_reg_read(dev, BYTE_TEST);
val = smc911x_reg_read(dev, LAN9118_BYTE_TEST);
if (val == 0xffffffff)
{
/* Special case -- no chip present */
@ -130,7 +130,7 @@ static int smc911x_detect_chip(struct eth_device_smc911x *dev)
return -1;
}
val = smc911x_reg_read(dev, ID_REV) >> 16;
val = smc911x_reg_read(dev, LAN9118_ID_REV) >> 16;
for (i = 0; chip_ids[i].id != 0; i++)
{
if (chip_ids[i].id == val) break;
@ -151,16 +151,16 @@ static void smc911x_reset(struct eth_device_smc911x *dev)
/*
* Take out of PM setting first
* Device is already wake up if PMT_CTRL_READY bit is set
* Device is already wake up if LAN9118_PMT_CTRL_READY bit is set
*/
if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0)
if ((smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY) == 0)
{
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(dev, BYTE_TEST, 0x0);
smc911x_reg_write(dev, LAN9118_BYTE_TEST, 0x0);
timeout = 10;
while (timeout-- && !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
while (timeout-- && !(smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY))
udelay(10);
if (timeout < 0)
@ -172,11 +172,11 @@ static void smc911x_reset(struct eth_device_smc911x *dev)
}
/* Disable interrupts */
smc911x_reg_write(dev, INT_EN, 0);
smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
smc911x_reg_write(dev, LAN9118_INT_EN, 0);
smc911x_reg_write(dev, LAN9118_HW_CFG, LAN9118_HW_CFG_SRST);
timeout = 1000;
while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
while (timeout-- && smc911x_reg_read(dev, LAN9118_E2P_CMD) & LAN9118_E2P_CMD)
udelay(10);
if (timeout < 0)
@ -186,11 +186,11 @@ static void smc911x_reset(struct eth_device_smc911x *dev)
}
/* Reset the FIFO level and flow control settings */
smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
smc911x_set_mac_csr(dev, LAN9118_FLOW, LAN9118_FLOW_FCPT(0xffff) | LAN9118_FLOW_FCEN);
smc911x_reg_write(dev, LAN9118_AFC_CFG, 0x0050287F);
/* Set to LED outputs */
smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
smc911x_reg_write(dev, LAN9118_GPIO_CFG, 0x70070000);
}
static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
@ -201,20 +201,20 @@ static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
addrh = m[4] | (m[5] << 8);
smc911x_set_mac_csr(dev, ADDRL, addrl);
smc911x_set_mac_csr(dev, ADDRH, addrh);
smc911x_set_mac_csr(dev, LAN9118_ADDRL, addrl);
smc911x_set_mac_csr(dev, LAN9118_ADDRH, addrh);
}
static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
uint8_t phy, uint8_t reg, uint16_t *val)
{
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
smc911x_set_mac_csr(dev, LAN9118_MII_ACC, phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY);
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
*val = smc911x_get_mac_csr(dev, MII_DATA);
*val = smc911x_get_mac_csr(dev, LAN9118_MII_DATA);
return 0;
}
@ -222,14 +222,14 @@ static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
uint8_t phy, uint8_t reg, uint16_t val)
{
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
;
smc911x_set_mac_csr(dev, MII_DATA, val);
smc911x_set_mac_csr(dev, MII_ACC,
phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
smc911x_set_mac_csr(dev, LAN9118_MII_DATA, val);
smc911x_set_mac_csr(dev, LAN9118_MII_ACC,
phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY | LAN9118_MII_ACC_MIIWNR);
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
;
return 0;
}
@ -238,10 +238,10 @@ static int smc911x_phy_reset(struct eth_device_smc911x *dev)
{
uint32_t reg;
reg = smc911x_reg_read(dev, PMT_CTRL);
reg = smc911x_reg_read(dev, LAN9118_PMT_CTRL);
reg &= ~0xfffff030;
reg |= PMT_CTRL_PHY_RST;
smc911x_reg_write(dev, PMT_CTRL, reg);
reg |= LAN9118_PMT_CTRL_PHY_RST;
smc911x_reg_write(dev, LAN9118_PMT_CTRL, reg);
mdelay(100);
@ -255,10 +255,10 @@ static void smc911x_phy_configure(struct eth_device_smc911x *dev)
smc911x_phy_reset(dev);
smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_RESET);
mdelay(1);
smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1);
smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
smc911x_eth_phy_write(dev, 1, LAN9118_MII_ADVERTISE, 0x01e1);
smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_ANENABLE | LAN9118_BMCR_ANRESTART);
timeout = 5000;
do
@ -267,10 +267,10 @@ static void smc911x_phy_configure(struct eth_device_smc911x *dev)
if ((timeout--) == 0)
goto err_out;
if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0)
if (smc911x_eth_phy_read(dev, 1, LAN9118_MII_BMSR, &status) != 0)
goto err_out;
}
while (!(status & BMSR_LSTATUS));
while (!(status & LAN9118_BMSR_LSTATUS));
return;
@ -281,17 +281,17 @@ err_out:
static void smc911x_enable(struct eth_device_smc911x *dev)
{
/* Enable TX */
smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
smc911x_reg_write(dev, LAN9118_HW_CFG, 8 << 16 | LAN9118_HW_CFG_SF);
smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
smc911x_reg_write(dev, LAN9118_GPT_CFG, LAN9118_GPT_CFG_TIMER_EN | 10000);
smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
smc911x_reg_write(dev, LAN9118_TX_CFG, LAN9118_TX_CFG_TX_ON);
/* no padding to start of packets */
smc911x_reg_write(dev, RX_CFG, 0);
smc911x_reg_write(dev, LAN9118_RX_CFG, 0);
smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
MAC_CR_HBDIS);
smc911x_set_mac_csr(dev, LAN9118_MAC_CR, LAN9118_MAC_CR_TXEN | LAN9118_MAC_CR_RXEN |
LAN9118_MAC_CR_HBDIS);
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
@ -329,13 +329,13 @@ static void smc911x_isr(int vector, void *param)
emac = SMC911X_EMAC_DEVICE(param);
status = smc911x_reg_read(emac, INT_STS);
if (status & INT_STS_RSFL)
status = smc911x_reg_read(emac, LAN9118_INT_STS);
if (status & LAN9118_INT_STS_RSFL)
{
eth_device_ready(&emac->parent);
}
smc911x_reg_write(emac, INT_STS, status);
smc911x_reg_write(emac, LAN9118_INT_STS, status);
return ;
}
@ -359,18 +359,18 @@ static rt_err_t smc911x_emac_init(rt_device_t dev)
#if 1
/* Interrupt on every received packet */
smc911x_reg_write(emac, FIFO_INT, 0x01 << 8);
smc911x_reg_write(emac, INT_EN, INT_EN_RDFL_EN | INT_EN_RSFL_EN);
smc911x_reg_write(emac, LAN9118_FIFO_INT, 0x01 << 8);
smc911x_reg_write(emac, LAN9118_INT_EN, LAN9118_INT_EN_RDFL_EN | LAN9118_INT_RSFL);
/* enable interrupt */
smc911x_reg_write(emac, INT_CFG, INT_CFG_IRQ_EN | INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
smc911x_reg_write(emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_EN | LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
#else
/* disable interrupt */
smc911x_reg_write(emac, INT_EN, 0);
value = smc911x_reg_read(emac, INT_CFG);
value &= ~INT_CFG_IRQ_EN;
smc911x_reg_write(emac, INT_CFG, value);
smc911x_reg_write(emac, LAN9118_INT_EN, 0);
value = smc911x_reg_read(emac, LAN9118_IRQ_CFG);
value &= ~LAN9118_IRQ_CFG_IRQ_EN;
smc911x_reg_write(emac, LAN9118_IRQ_CFG, value);
#endif
rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
@ -386,11 +386,11 @@ static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
emac = SMC911X_EMAC_DEVICE(dev);
RT_ASSERT(emac != RT_NULL);
switch(cmd)
switch (cmd)
{
case NIOCTL_GADDR:
/* get MAC address */
if(args) rt_memcpy(args, emac->enetaddr, 6);
if (args) rt_memcpy(args, emac->enetaddr, 6);
else return -RT_ERROR;
break;
default :
@ -402,7 +402,7 @@ static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
/* Ethernet device interface */
/* transmit packet. */
static uint8_t tx_buf[2048];
rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf *p)
{
struct eth_device_smc911x *emac;
@ -418,36 +418,36 @@ rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
/* send it out */
data = (uint32_t*)tx_buf;
data = (uint32_t *)tx_buf;
length = p->tot_len;
smc911x_reg_write(emac, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
smc911x_reg_write(emac, TX_DATA_FIFO, length);
smc911x_reg_write(emac, LAN9118_TXDFIFOP, LAN9118_TXC_A_FS | LAN9118_TXC_A_LS | length);
smc911x_reg_write(emac, LAN9118_TXDFIFOP, length);
tmplen = (length + 3) / 4;
while (tmplen--)
{
smc911x_reg_write(emac, TX_DATA_FIFO, *data++);
smc911x_reg_write(emac, LAN9118_TXDFIFOP, *data++);
}
/* wait for transmission */
while (!((smc911x_reg_read(emac, TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
while (!(LAN9118_TX_FIFO_INF_TXSUSED(smc911x_reg_read(emac, LAN9118_TX_FIFO_INF))));
/* get status. Ignore 'no carrier' error, it has no meaning for
* full duplex operation
*/
status = smc911x_reg_read(emac, TX_STATUS_FIFO) &
(TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
status = smc911x_reg_read(emac, LAN9118_TXSFIFOP) &
(LAN9118_TXS_LOC | LAN9118_TXS_LCOL | LAN9118_TXS_ECOL |
LAN9118_TXS_ED | LAN9118_TX_STS_UNDERRUN);
if (!status) return 0;
rt_kprintf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
status & TX_STS_LOC ? "TX_STS_LOC " : "",
status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
status & LAN9118_TXS_LOC ? "LAN9118_TXS_LOC " : "",
status & LAN9118_TXS_LCOL ? "LAN9118_TXS_LCOL " : "",
status & LAN9118_TXS_ECOL ? "LAN9118_TXS_ECOL " : "",
status & LAN9118_TXS_ED ? "LAN9118_TXS_ED " : "",
status & LAN9118_TX_STS_UNDERRUN ? "LAN9118_TX_STS_UNDERRUN" : "");
return -RT_EIO;
}
@ -455,24 +455,24 @@ rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
/* reception packet. */
struct pbuf *smc911x_emac_rx(rt_device_t dev)
{
struct pbuf* p = RT_NULL;
struct pbuf *p = RT_NULL;
struct eth_device_smc911x *emac;
emac = SMC911X_EMAC_DEVICE(dev);
RT_ASSERT(emac != RT_NULL);
/* take the emac buffer to the pbuf */
if ((smc911x_reg_read(emac, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16)
if (LAN9118_RX_FIFO_INF_RXSUSED(smc911x_reg_read(emac, LAN9118_RX_FIFO_INF)))
{
uint32_t status;
uint32_t pktlen, tmplen;
status = smc911x_reg_read(emac, RX_STATUS_FIFO);
status = smc911x_reg_read(emac, LAN9118_RXSFIFOP);
/* get frame length */
pktlen = (status & RX_STS_PKT_LEN) >> 16;
pktlen = (status & LAN9118_RX_STS_PKT_LEN) >> 16;
smc911x_reg_write(emac, RX_CFG, 0);
smc911x_reg_write(emac, LAN9118_RX_CFG, 0);
tmplen = (pktlen + 3) / 4;
@ -483,11 +483,11 @@ struct pbuf *smc911x_emac_rx(rt_device_t dev)
uint32_t *data = (uint32_t *)p->payload;
while (tmplen--)
{
*data++ = smc911x_reg_read(emac, RX_DATA_FIFO);
*data++ = smc911x_reg_read(emac, LAN9118_RXDFIFOP);
}
}
if (status & RX_STS_ES)
if (status & LAN9118_RXS_ES)
{
rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
}
@ -497,7 +497,7 @@ struct pbuf *smc911x_emac_rx(rt_device_t dev)
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops smc911x_emac_ops =
const static struct rt_device_ops smc911x_emac_ops =
{
smc911x_emac_init,
RT_NULL,
@ -520,7 +520,7 @@ int smc911x_emac_hw_init(void)
}
/* set INT CFG */
smc911x_reg_write(&_emac, INT_CFG, INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
smc911x_reg_write(&_emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
/* test MAC address */
_emac.enetaddr[0] = AUTOMAC0;

704
bsp/qemu-vexpress-a9/drivers/drv_smc911x.h
View File

@ -1,402 +1,342 @@
/*
* SMSC LAN9[12]1[567] Network driver
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
* SPDX-License-Identifier: Apache-2.0
*
* SPDX-License-Identifier: GPL-2.0+
* Change Logs:
* Date Author Notes
* 2021-04-21
*/
#ifndef _SMC911X_H_
#define _SMC911X_H_
#include <stdint.h>
/* $NetBSD: lan9118reg.h,v 1.3 2010/09/27 12:29:03 kiyohara Exp $ */
/*
* Copyright (c) 2008 KIYOHARA Takashi
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LAN9118REG_H_
#define _LAN9118REG_H_
#define CONFIG_SMC911X_32_BIT
/* Below are the register offsets and bit definitions
* of the Lan911x memory space
*/
#define RX_DATA_FIFO 0x00
#define LAN9118_IOSIZE 0x100
#define TX_DATA_FIFO 0x20
#define TX_CMD_A_INT_ON_COMP 0x80000000
#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
#define TX_CMD_A_INT_FIRST_SEG 0x00002000
#define TX_CMD_A_INT_LAST_SEG 0x00001000
#define TX_CMD_A_BUF_SIZE 0x000007FF
#define TX_CMD_B_PKT_TAG 0xFFFF0000
#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
#define TX_CMD_B_DISABLE_PADDING 0x00001000
#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
#define LAN9118_ID_89218 0x218a
#define LAN9118_ID_9115 0x0115
#define LAN9118_ID_9116 0x0116
#define LAN9118_ID_9117 0x0117
#define LAN9118_ID_9118 0x0118
#define LAN9218_ID_9215 0x115a
#define LAN9218_ID_9216 0x116a
#define LAN9218_ID_9217 0x117a
#define LAN9218_ID_9218 0x118a
#define RX_STATUS_FIFO 0x40
#define RX_STS_PKT_LEN 0x3FFF0000
#define RX_STS_ES 0x00008000
#define RX_STS_BCST 0x00002000
#define RX_STS_LEN_ERR 0x00001000
#define RX_STS_RUNT_ERR 0x00000800
#define RX_STS_MCAST 0x00000400
#define RX_STS_TOO_LONG 0x00000080
#define RX_STS_COLL 0x00000040
#define RX_STS_ETH_TYPE 0x00000020
#define RX_STS_WDOG_TMT 0x00000010
#define RX_STS_MII_ERR 0x00000008
#define RX_STS_DRIBBLING 0x00000004
#define RX_STS_CRC_ERR 0x00000002
#define RX_STATUS_FIFO_PEEK 0x44
#define TX_STATUS_FIFO 0x48
#define TX_STS_TAG 0xFFFF0000
#define TX_STS_ES 0x00008000
#define TX_STS_LOC 0x00000800
#define TX_STS_NO_CARR 0x00000400
#define TX_STS_LATE_COLL 0x00000200
#define TX_STS_MANY_COLL 0x00000100
#define TX_STS_COLL_CNT 0x00000078
#define TX_STS_MANY_DEFER 0x00000004
#define TX_STS_UNDERRUN 0x00000002
#define TX_STS_DEFERRED 0x00000001
#define TX_STATUS_FIFO_PEEK 0x4C
#define ID_REV 0x50
#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
#define ID_REV_REV_ID 0x0000FFFF /* RO */
#define LAN9210_ID_9210 0x9210
#define LAN9210_ID_9211 0x9211
#define LAN9220_ID_9220 0x9220
#define LAN9220_ID_9221 0x9221
#define INT_CFG 0x54
#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
#define INT_CFG_INT_DEAS_CLR 0x00004000
#define INT_CFG_INT_DEAS_STS 0x00002000
#define INT_CFG_IRQ_INT 0x00001000 /* RO */
#define INT_CFG_IRQ_EN 0x00000100 /* R/W */
/* R/W Not Affected by SW Reset */
#define INT_CFG_IRQ_POL 0x00000010
/* R/W Not Affected by SW Reset */
#define INT_CFG_IRQ_TYPE 0x00000001
#define IS_LAN9118(id) ((id) >= LAN9118_ID_9115 && (id) <= LAN9118_ID_9118)
#define IS_LAN9218(id) ((id) >= LAN9218_ID_9215 && (id) <= LAN9218_ID_9218)
#define INT_STS 0x58
#define INT_STS_SW_INT 0x80000000 /* R/WC */
#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
#define INT_STS_RXDF_INT 0x00400000 /* R/WC */
#define INT_STS_TX_IOC 0x00200000 /* R/WC */
#define INT_STS_RXD_INT 0x00100000 /* R/WC */
#define INT_STS_GPT_INT 0x00080000 /* R/WC */
#define INT_STS_PHY_INT 0x00040000 /* RO */
#define INT_STS_PME_INT 0x00020000 /* R/WC */
#define INT_STS_TXSO 0x00010000 /* R/WC */
#define INT_STS_RWT 0x00008000 /* R/WC */
#define INT_STS_RXE 0x00004000 /* R/WC */
#define INT_STS_TXE 0x00002000 /* R/WC */
/*#define INT_STS_ERX 0x00001000*/ /* R/WC */
#define INT_STS_TDFU 0x00000800 /* R/WC */
#define INT_STS_TDFO 0x00000400 /* R/WC */
#define INT_STS_TDFA 0x00000200 /* R/WC */
#define INT_STS_TSFF 0x00000100 /* R/WC */
#define INT_STS_TSFL 0x00000080 /* R/WC */
/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */
#define INT_STS_RDFO 0x00000040 /* R/WC */
#define INT_STS_RDFL 0x00000020 /* R/WC */
#define INT_STS_RSFF 0x00000010 /* R/WC */
#define INT_STS_RSFL 0x00000008 /* R/WC */
#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
#define INT_EN 0x5C
#define INT_EN_SW_INT_EN 0x80000000 /* R/W */
#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
#define INT_EN_PME_INT_EN 0x00020000 /* R/W */
#define INT_EN_TXSO_EN 0x00010000 /* R/W */
#define INT_EN_RWT_EN 0x00008000 /* R/W */
#define INT_EN_RXE_EN 0x00004000 /* R/W */
#define INT_EN_TXE_EN 0x00002000 /* R/W */
/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */
#define INT_EN_TDFU_EN 0x00000800 /* R/W */
#define INT_EN_TDFO_EN 0x00000400 /* R/W */
#define INT_EN_TDFA_EN 0x00000200 /* R/W */
#define INT_EN_TSFF_EN 0x00000100 /* R/W */
#define INT_EN_TSFL_EN 0x00000080 /* R/W */
/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */
#define INT_EN_RDFO_EN 0x00000040 /* R/W */
#define INT_EN_RDFL_EN 0x00000020 /* R/W */
#define INT_EN_RSFF_EN 0x00000010 /* R/W */
#define INT_EN_RSFL_EN 0x00000008 /* R/W */
#define INT_EN_GPIO2_INT 0x00000004 /* R/W */
#define INT_EN_GPIO1_INT 0x00000002 /* R/W */
#define INT_EN_GPIO0_INT 0x00000001 /* R/W */
#define BYTE_TEST 0x64
#define FIFO_INT 0x68
#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
#define RX_CFG 0x6C
#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
#define RX_CFG_RX_DUMP 0x00008000 /* R/W */
#define RX_CFG_RXDOFF 0x00001F00 /* R/W */
/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
#define TX_CFG 0x70
/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
/* R/W Self Clearing */
/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/
#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
#define TX_CFG_TXSAO 0x00000004 /* R/W */
#define TX_CFG_TX_ON 0x00000002 /* R/W */
#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
#define HW_CFG 0x74
#define HW_CFG_TTM 0x00200000 /* R/W */
#define HW_CFG_SF 0x00100000 /* R/W */
#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
#define HW_CFG_TR 0x00003000 /* R/W */
#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
#define HW_CFG_SMI_SEL 0x00000010 /* R/W */
#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
#define HW_CFG_SRST_TO 0x00000002 /* RO */
#define HW_CFG_SRST 0x00000001 /* Self Clearing */
#define RX_DP_CTRL 0x78
#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
#define RX_FIFO_INF 0x7C
#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
#define TX_FIFO_INF 0x80
#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
#define PMT_CTRL 0x84
#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
#define PMT_CTRL_ED_EN 0x00000100 /* R/W */
/* R/W Not Affected by SW Reset */
#define PMT_CTRL_PME_TYPE 0x00000040
#define PMT_CTRL_WUPS 0x00000030 /* R/WC */
#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
#define PMT_CTRL_PME_IND 0x00000008 /* R/W */
#define PMT_CTRL_PME_POL 0x00000004 /* R/W */
/* R/W Not Affected by SW Reset */
#define PMT_CTRL_PME_EN 0x00000002
#define PMT_CTRL_READY 0x00000001 /* RO */
#define GPIO_CFG 0x88
#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
#define GPT_CFG 0x8C
#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
#define GPT_CNT 0x90
#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
#define ENDIAN 0x98
#define FREE_RUN 0x9C
#define RX_DROP 0xA0
#define MAC_CSR_CMD 0xA4
#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
#define MAC_CSR_DATA 0xA8
#define AFC_CFG 0xAC
#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
#define AFC_CFG_FCMULT 0x00000008 /* R/W */
#define AFC_CFG_FCBRD 0x00000004 /* R/W */
#define AFC_CFG_FCADD 0x00000002 /* R/W */
#define AFC_CFG_FCANY 0x00000001 /* R/W */
#define E2P_CMD 0xB0
#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
#define E2P_DATA 0xB4
#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
/* end of LAN register offsets and bit definitions */
/* MAC Control and Status registers */
#define MAC_CR 0x01 /* R/W */
/* MAC_CR - MAC Control Register */
#define MAC_CR_RXALL 0x80000000
/* TODO: delete this bit? It is not described in the data sheet. */
#define MAC_CR_HBDIS 0x10000000
#define MAC_CR_RCVOWN 0x00800000
#define MAC_CR_LOOPBK 0x00200000
#define MAC_CR_FDPX 0x00100000
#define MAC_CR_MCPAS 0x00080000
#define MAC_CR_PRMS 0x00040000
#define MAC_CR_INVFILT 0x00020000
#define MAC_CR_PASSBAD 0x00010000
#define MAC_CR_HFILT 0x00008000
#define MAC_CR_HPFILT 0x00002000
#define MAC_CR_LCOLL 0x00001000
#define MAC_CR_BCAST 0x00000800
#define MAC_CR_DISRTY 0x00000400
#define MAC_CR_PADSTR 0x00000100
#define MAC_CR_BOLMT_MASK 0x000000C0
#define MAC_CR_DFCHK 0x00000020
#define MAC_CR_TXEN 0x00000008
#define MAC_CR_RXEN 0x00000004
#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
#define HASHH 0x04 /* R/W */
#define HASHL 0x05 /* R/W */
#define MII_ACC 0x06 /* R/W */
#define MII_ACC_PHY_ADDR 0x0000F800
#define MII_ACC_MIIRINDA 0x000007C0
#define MII_ACC_MII_WRITE 0x00000002
#define MII_ACC_MII_BUSY 0x00000001
#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
#define FLOW 0x08 /* R/W */
#define FLOW_FCPT 0xFFFF0000
#define FLOW_FCPASS 0x00000004
#define FLOW_FCEN 0x00000002
#define FLOW_FCBSY 0x00000001
#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
#define VLAN1_VTI1 0x0000ffff
#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
#define VLAN2_VTI2 0x0000ffff
#define WUFF 0x0B /* WO */
#define WUCSR 0x0C /* R/W */
#define WUCSR_GUE 0x00000200
#define WUCSR_WUFR 0x00000040
#define WUCSR_MPR 0x00000020
#define WUCSR_WAKE_EN 0x00000004
#define WUCSR_MPEN 0x00000002
/* Chip ID values */
#define CHIP_89218 0x218a
#define CHIP_9115 0x115
#define CHIP_9116 0x116
#define CHIP_9117 0x117
#define CHIP_9118 0x118
#define CHIP_9211 0x9211
#define CHIP_9215 0x115a
#define CHIP_9216 0x116a
#define CHIP_9217 0x117a
#define CHIP_9218 0x118a
#define CHIP_9220 0x9220
#define CHIP_9221 0x9221
#define LAN9118_IPHY_ADDR 0x01 /* Internal PHY Address */
/* Generic MII registers. */
#define LAN9118_RXDFIFOP 0x00 /* RX Data FIFO Port */
#define LAN9118_RXDFIFOAP 0x04 /* RX Data FIFO Alias Ports */
#define LAN9118_TXDFIFOP 0x20 /* TX Data FIFO Port */
#define LAN9118_TXDFIFOAP 0x24 /* TX Data FIFO Alias Ports */
#define LAN9118_RXSFIFOP 0x40 /* RX Status FIFO Port */
#define LAN9118_RXSFIFOPEEK 0x44 /* RX Status FIFO PEEK */
#define LAN9118_TXSFIFOP 0x48 /* TX Status FIFO Port */
#define LAN9118_TXSFIFOPEEK 0x4c /* TX Status FIFO PEEK */
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
#define MII_LPA 0x05 /* Link partner ability reg */
#define MII_EXPANSION 0x06 /* Expansion register */
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
#define MII_STAT1000 0x0a /* 1000BASE-T status */
#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
#define MII_SREVISION 0x16 /* Silicon revision */
#define MII_RESV1 0x17 /* Reserved... */
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
#define MII_PHYADDR 0x19 /* PHY address */
#define MII_RESV2 0x1a /* Reserved... */
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
#define MII_NCONFIG 0x1c /* Network interface config */
/* System Control and Status Registers */
#define LAN9118_ID_REV 0x50 /* Chip ID and Revision */
#define LAN9118_ID_REV_ID(x) (((x) >> 16) & 0xffff)
#define LAN9118_ID_REV_REV(x) ((x) & 0xffff)
#define LAN9118_IRQ_CFG 0x54 /* Main Interrupt Configuration */
#define LAN9118_IRQ_CFG_INT_DEAS(t) ((t) << 24) /* Intr Deassert Interval */
#define LAN9118_IRQ_CFG_INT_DEAS_CLR (1 << 14) /* Intr Deass Intrval clr */
#define LAN9118_IRQ_CFG_INT_DEAS_STS (1 << 13) /* Intr Deassert Status */
#define LAN9118_IRQ_CFG_IRQ_INT (1 << 12) /* Master Interrupt */
#define LAN9118_IRQ_CFG_IRQ_EN (1 << 8) /* IRQ Enable */
#define LAN9118_IRQ_CFG_IRQ_POL (1 << 4) /* IRQ Polarity */
#define LAN9118_IRQ_CFG_IRQ_TYPE (1 << 0) /* IRQ Buffer Type */
#define LAN9118_INT_STS 0x58 /* Interrupt Status */
#define LAN9118_INT_EN 0x5c /* Interrupt Enable Register */
#define LAN9118_INT_SW_INT (1 << 31) /* Software Interrupt */
#define LAN9118_INT_TXSTOP_INT (1 << 25) /* TX Stopped */
#define LAN9118_INT_RXSTOP_INT (1 << 24) /* RX Stopped */
#define LAN9118_INT_RXDFH_INT (1 << 23) /* RX Drppd Frm Cnt Halfway */
#define LAN9118_INT_TX_IOC (1 << 21) /* TX IOC Interrupt */
#define LAN9118_INT_RXD_INT (1 << 20) /* RX DMA Interrupt */
#define LAN9118_INT_GPT_INT (1 << 19) /* GP Timer */
#define LAN9118_INT_PHY_INT (1 << 18) /* PHY */
#define LAN9118_INT_PME_INT (1 << 17) /* Power Management Event */
#define LAN9118_INT_TXSO (1 << 16) /* TX Status FIFO Overflow */
#define LAN9118_INT_RWT (1 << 15) /* Rcv Watchdog Time-out */
#define LAN9118_INT_RXE (1 << 14) /* Receive Error */
#define LAN9118_INT_TXE (1 << 13) /* Transmitter Error */
#define LAN9118_INT_TDFO (1 << 10) /* TX Data FIFO Overrun */
#define LAN9118_INT_TDFA (1 << 9) /* TX Data FIFO Available */
#define LAN9118_INT_TSFF (1 << 8) /* TX Status FIFO Full */
#define LAN9118_INT_TSFL (1 << 7) /* TX Status FIFO Level */
#define LAN9118_INT_RXDF_INT (1 << 6) /* RX Dropped Frame Intr */
#define LAN9118_INT_RSFF (1 << 4) /* RX Status FIFO Full */
#define LAN9118_INT_RSFL (1 << 3) /* RX Status FIFO Level */
#define LAN9118_INT_GPIOX_INT(x) (1 << (x)) /* GPIO[2:0] */
/* 0x60 Reserved for future use */
#define LAN9118_BYTE_TEST 0x64 /* Read-only byte order testing reg */
#define LAN9118_BYTE_TEST_VALUE 0x87654321
#define LAN9118_FIFO_INT 0x68 /* FIFO Level Interrupt */
#define LAN9118_FIFO_INT_TXDAL(x) ((x) << 24) /* TX Data Available Lvl */
#define LAN9118_FIFO_INT_TXSL(x) ((x) << 16) /* TX Status Level */
#define LAN9118_FIFO_INT_RXSL(x) ((x) << 0) /* RX Status Level */
#define LAN9118_RX_CFG 0x6c /* Receive Configuration */
#define LAN9118_RX_CFG_RXEA_4B (0 << 30) /* RX End Alignment: 4 Byte */
#define LAN9118_RX_CFG_RXEA_16B (1 << 30) /* 16 Byte */
#define LAN9118_RX_CFG_RXEA_32B (2 << 30) /* 32 Byte */
#define LAN9118_RX_CFG_RX_DMA_CNT(x) ((x) << 16) /* RX DMA Count */
#define LAN9118_RX_CFG_RX_DUMP (1 << 15) /* Force RX Discard */
#define LAN9118_RX_CFG_RXDOFF(x) ((x) << 8) /* RX Data Offset */
#define LAN9118_TX_CFG 0x70 /* Transmit Configuration */
#define LAN9118_TX_CFG_TXS_DUMP (1 << 15) /* Force TX Status Discard */
#define LAN9118_TX_CFG_TXD_DUMP (1 << 14) /* Force TX Data Discard */
#define LAN9118_TX_CFG_TXSAO (1 << 2) /* TX Status Allow Overrun */
#define LAN9118_TX_CFG_TX_ON (1 << 1) /* Transmitter Enable */
#define LAN9118_TX_CFG_STOP_TX (1 << 0) /* Stop Transmitter */
#define LAN9118_HW_CFG 0x74 /* Hardware Configuration */
#define LAN9118_HW_CFG_MBO (1 << 20)/* Must Be One */
#define LAN9118_HW_CFG_TX_FIF_MASK (0xf << 16) /* TX FIFO Size */
#define LAN9118_HW_CFG_TX_FIF_SZ(sz) ((sz) << 16)
#define LAN9118_HW_CFG_PHY_CLK_SEL_MASK (3 << 5) /* PHY Clock Select */
#define LAN9118_HW_CFG_PHY_CLK_SEL_IPHY (0 << 5) /* Internal PHY */
#define LAN9118_HW_CFG_PHY_CLK_SEL_EMII (1 << 5) /* External MII Port */
#define LAN9118_HW_CFG_PHY_CLK_SEL_CD (2 << 5) /* Clock Disabled */
#define LAN9118_HW_CFG_SMI_SEL (1 << 4) /* Serial Mgmt Interface Sel */
#define LAN9118_HW_CFG_EXT_PHY_DET (1 << 3) /* External PHY Detect */
#define LAN9118_HW_CFG_EXT_PHY_EN (1 << 2) /* External PHY Enable */
#define LAN9118_HW_CFG_SRST_TO (1 << 1) /* Soft Reset Timeout */
#define LAN9118_HW_CFG_SRST (1 << 0) /* Soft Reset */
#define LAN9118_RX_DP_CTL 0x78 /* RX Datapath Control */
#define LAN9118_RX_DP_CTL_RX_FFWD (1 << 31)/* RX Data FIFO Fast Forward */
#define LAN9118_RX_FIFO_INF 0x7c /* Receive FIFO Information */
#define LAN9118_RX_FIFO_INF_RXSUSED(x) (((x) >> 16) & 0xff) /*Sts Used Space*/
#define LAN9118_RX_FIFO_INF_RXDUSED(x) ((x) & 0xffff) /*Data FIFO Used Space*/
#define LAN9118_TX_FIFO_INF 0x80 /* Transmit FIFO Information */
#define LAN9118_TX_FIFO_INF_TXSUSED(x) (((x) >> 16) & 0xff) /*Sts Used Space*/
#define LAN9118_TX_FIFO_INF_TDFREE(x) ((x) & 0xffff) /*Data FIFO Free Space*/
#define LAN9118_PMT_CTRL 0x84 /* Power Management Control */
#define LAN9118_PMT_CTRL_PM_MODE_MASK (3 << 12)
#define LAN9118_PMT_CTRL_PM_MODE_D0 (0 << 12)
#define LAN9118_PMT_CTRL_PM_MODE_D1 (1 << 12)
#define LAN9118_PMT_CTRL_PM_MODE_D2 (2 << 12)
#define LAN9118_PMT_CTRL_PHY_RST (1 << 10) /* PHY Reset */
#define LAN9118_PMT_CTRL_WOL_EN (1 << 9) /* Wake-On-LAN Enable */
#define LAN9118_PMT_CTRL_ED_EN (1 << 8) /* Energy-Detect Enable */
#define LAN9118_PMT_CTRL_PME_TYPE (1 << 6) /* PME Buffer Type */
#define LAN9118_PMT_CTRL_WUPS_NWUED (0 << 4) /* WAKE-UP Status: No Event */
#define LAN9118_PMT_CTRL_WUPS_ED (1 << 4) /* WAKE-UP Status: Energy */
#define LAN9118_PMT_CTRL_WUPS_WUD (2 << 4) /* WAKE-UP Status: Wake-up */
#define LAN9118_PMT_CTRL_PME_IND (1 << 3) /* PME indication */
#define LAN9118_PMT_CTRL_PME_POL (1 << 2) /* PME Polarity */
#define LAN9118_PMT_CTRL_PME_EN (1 << 1) /* PME Enable */
#define LAN9118_PMT_CTRL_READY (1 << 0) /* Device Ready */
#define LAN9118_GPIO_CFG 0x88 /* General Purpose IO Configuration */
#define LAN9118_GPIO_CFG_LEDX_EN(x) (1 << ((x) + 28)) /* LED[3:1] enable */
#define LAN9118_GPIO_CFG_GPIO_INT_POL(p) (1 << ((p) + 24)) /* Intr Polarity */
#define LAN9118_GPIO_CFG_EEPR_EN (7 << 20) /* EEPROM Enable */
#define LAN9118_GPIO_CFG_GPIOBUFN(n) (1 << ((n) + 16)) /* Buffer Type */
#define LAN9118_GPIO_CFG_GPDIRN(n) (1 << ((n) + 8)) /* Direction */
#define LAN9118_GPIO_CFG_GPODN(n) (1 << (n)) /* GPIO Data (3,4 is WO) */
#define LAN9118_GPT_CFG 0x8c /* General Purpose Timer Config */
#define LAN9118_GPT_CNT 0x90 /* General Purpose Timer Count */
/* 0x94 Reserved for future use */
#define LAN9118_WORD_SWAP 0x98 /* WORD SWAP Register */
#define LAN9118_FREE_RUN 0x9c /* Free Run Counter */
#define LAN9118_RX_DROP 0xa0 /* RX Drop Frame Counter */
#define LAN9118_MAC_CSR_CMD 0xa4 /* MAC CSR Synchronizer Command */
#define LAN9118_MAC_CSR_CMD_BUSY (1 << 31)
#define LAN9118_MAC_CSR_CMD_W (0 << 30)
#define LAN9118_MAC_CSR_CMD_R (1 << 30)
#define LAN9118_MAC_CSR_CMD_ADDRESS(a) ((a) & 0xff)
#define LAN9118_MAC_CSR_DATA 0xa8 /* MAC CSR Synchronizer Data */
#define LAN9118_AFC_CFG 0xac /* Automatic Flow Control Config */
#define LAN9118_AFC_CFG_AFC_HI(x) ((x) << 16)
#define LAN9118_AFC_CFG_AFC_LO(x) ((x) << 8)
#define LAN9118_AFC_CFG_BACK_DUR(x) ((x) << 4)
#define LAN9118_AFC_CFG_FCMULT (1 << 3) /* Flow Control on Multicast */
#define LAN9118_AFC_CFG_FCBRD (1 << 2) /* Flow Control on Broadcast */
#define LAN9118_AFC_CFG_FCADD (1 << 1) /* Flow Control on Addr Dec */
#define LAN9118_AFC_CFG_FCANY (1 << 0) /* Flow Control on Any Frame */
#define LAN9118_E2P_CMD 0xb0 /* EEPROM command */
#define LAN9118_E2P_CMD_EPCB (1 << 31) /* EPC Busy */
#define LAN9118_E2P_CMD_EPCC_READ (0 << 28) /* EPC Command: READ */
#define LAN9118_E2P_CMD_EPCC_EWDS (1 << 28) /* EWDS */
#define LAN9118_E2P_CMD_EPCC_EWEN (2 << 28) /* EWEN */
#define LAN9118_E2P_CMD_EPCC_WRITE (3 << 28) /* WRITE */
#define LAN9118_E2P_CMD_EPCC_WRAL (4 << 28) /* WRAL */
#define LAN9118_E2P_CMD_EPCC_ERASE (5 << 28) /* ERASE */
#define LAN9118_E2P_CMD_EPCC_ERAL (6 << 28) /* ERAL */
#define LAN9118_E2P_CMD_EPCC_RELOAD (7 << 28) /* Reload */
#define LAN9118_E2P_CMD_EPCTO (1 << 9) /* EPC Time-out */
#define LAN9118_E2P_CMD_MACAL (1 << 8) /* MAC Address Loaded */
#define LAN9118_E2P_CMD_EPCA(a) ((a) & 0xff) /* EPC Address */
#define LAN9118_E2P_DATA 0xb4 /* EEPROM Data */
/* 0xb8 - 0xfc Reserved for future use */
/* MAC Control and Status Registers */
#define LAN9118_MAC_CR 0x1 /* MAC Control Register */
#define LAN9118_MAC_CR_RXALL (1 << 31) /* Receive All Mode */
#define LAN9118_MAC_CR_RCVOWN (1 << 23) /* Disable Receive Own */
#define LAN9118_MAC_CR_LOOPBK (1 << 21) /* Loopback operation Mode */
#define LAN9118_MAC_CR_FDPX (1 << 20) /* Full Duplex Mode */
#define LAN9118_MAC_CR_MCPAS (1 << 19) /* Pass All Multicast */
#define LAN9118_MAC_CR_PRMS (1 << 18) /* Promiscuous Mode */
#define LAN9118_MAC_CR_INVFILT (1 << 17) /* Inverse filtering */
#define LAN9118_MAC_CR_PASSBAD (1 << 16) /* Pass Bad Frames */
#define LAN9118_MAC_CR_HO (1 << 15) /* Hash Only Filtering mode */
#define LAN9118_MAC_CR_HPFILT (1 << 13) /* Hash/Perfect Flt Mode */
#define LAN9118_MAC_CR_LCOLL (1 << 12) /* Late Collision Control */
#define LAN9118_MAC_CR_BCAST (1 << 11) /* Disable Broardcast Frms */
#define LAN9118_MAC_CR_DISRTY (1 << 10) /* Disable Retry */
#define LAN9118_MAC_CR_PADSTR (1 << 8) /* Automatic Pad String */
#define LAN9118_MAC_CR_BOLMT (1 << 7) /* BackOff Limit */
#define LAN9118_MAC_CR_DFCHK (1 << 5) /* Deferral Check */
#define LAN9118_MAC_CR_TXEN (1 << 3) /* Transmitter enable */
#define LAN9118_MAC_CR_RXEN (1 << 2) /* Receiver enable */
#define LAN9118_ADDRH 0x2 /* MAC Address High */
#define LAN9118_ADDRL 0x3 /* MAC Address Low */
#define LAN9118_HASHH 0x4 /* Multicast Hash Table High */
#define LAN9118_HASHL 0x5 /* Multicast Hash Table Low */
#define LAN9118_MII_ACC 0x6 /* MII Access */
#define LAN9118_MII_ACC_PHYA(a) ((a) << 11) /* PHY Address */
#define LAN9118_MII_ACC_MIIRINDA(i) ((i) << 6) /* MII Register Index */
#define LAN9118_MII_ACC_MIIWNR (1 << 1) /* MII Write */
#define LAN9118_MII_ACC_MIIBZY (1 << 0) /* MII Busy */
#define LAN9118_MII_DATA 0x7 /* MII Data */
#define LAN9118_FLOW 0x8 /* Flow Control */
#define LAN9118_FLOW_FCPT(t) ((t) << 16) /* Pause Time */
#define LAN9118_FLOW_FCPASS (1 << 2) /* Pass Control Frame */
#define LAN9118_FLOW_FCEN (1 << 1) /* Flow Control Enable */
#define LAN9118_FLOW_FCBUSY (1 << 0) /* Flow Control Busy */
#define LAN9118_VLAN1 0x9 /* VLAN1 Tag */
#define LAN9118_VLAN2 0xa /* VLAN2 Tag */
#define LAN9118_WUFF 0xb /* Wake-up Frame Filter */
#define LAN9118_WUCSR 0xc /* Wake-up Control and Status */
/* PHY Registers */
#define LAN9118_MCSR 0x11 /* Mode Control/Status Register */
#define LAN9118_MCSR_EDPWRDOWN (1 << 13) /* Energy Detect Power Down */
#define LAN9118_MCSR_ENERGYON (1 << 1)
#define LAN9118_SMR 0x12 /* Special Modes Register */
#define LAN9118_SMR_PHYAD (0x01)
#define LAN9118_SCSI 0x1b /* Special Control/Status Indications */
#define LAN9118_SCSI_VCOOFF_LP (1 << 10)
#define LAN9118_SCSI_XPOL (1 << 4) /* Polarity state */
#define LAN9118_ISR 0x1d /* Interrupt Source Register */
#define LAN9118_IMR 0x1e /* Interrupt Mask Register */
#define LAN9118_I_ENERGYON (1 << 7)
#define LAN9118_I_AUTONEGOCOMPL (1 << 6)
#define LAN9118_I_REMOTEFAULT (1 << 5)
#define LAN9118_I_LINKDOWN (1 << 4)
#define LAN9118_I_AUTONEGOLPACK (1 << 3) /* AutoNego LP Acknowledge */
#define LAN9118_I_PDF (1 << 2) /* Parallel Detection Fault */
#define LAN9118_I_AUTONEGOPR (1 << 1) /* AutoNego Page Received */
#define LAN9118_PHYSCSR 0x1f /* PHY Special Control/Status Reg */
#define LAN9118_PHYSCSR_AUTODONE (1 << 12) /* AutoNego done indication */
#define LAN9118_PHYSCSR_SI_10 (1 << 2) /* Speed Indication */
#define LAN9118_PHYSCSR_SI_100 (2 << 2)
#define LAN9118_PHYSCSR_SI_FDX (4 << 2)
/* TX Command 'A' Format */
#define LAN9118_TXC_A_IC (1 << 31) /* Interrupt on Completion */
#define LAN9118_TXC_A_BEA_4B (0 << 24) /* Buffer End Alignment: 4B */
#define LAN9118_TXC_A_BEA_16B (1 << 24) /* 16B */
#define LAN9118_TXC_A_BEA_32B (2 << 24) /* 32B */
#define LAN9118_TXC_A_DSO(x) ((x) << 16) /*Data Start Offset: bytes*/
#define LAN9118_TXC_A_FS (1 << 13) /* First Segment */
#define LAN9118_TXC_A_LS (1 << 12) /* Last Segment */
#define LAN9118_TXC_A_BS(x) ((x) << 0) /* Buffer Size */
/* TX Command 'B' Format */
#define LAN9118_TXC_B_PT(x) ((x) << 16) /* Packet Tag */
#define LAN9118_TXC_B_ACRCD (1 << 13) /* Add CRC Disable */
#define LAN9118_TXC_B_DEFP (1 << 12) /* Dis Ether Frame Padding */
#define LAN9118_TXC_B_PL(x) ((x) << 0) /* Packet Length */
/* TX Status Format */
#define LAN9118_TXS_PKTTAG(x) (((x) >> 16) & 0xff) /* Packet Tag */
#define LAN9118_TXS_ES (1 << 15) /* Error Status */
#define LAN9118_TXS_LOC (1 << 11) /* Loss Of Carrier */
#define LAN9118_TXS_NC (1 << 10) /* No Carrier */
#define LAN9118_TXS_LCOL (1 << 9) /* Late Collision */
#define LAN9118_TXS_ECOL (1 << 8) /* Excessive Collision*/
#define LAN9118_TXS_COLCNT(x) (((x) >> 3) & 0xf) /* Collision Count */
#define LAN9118_TXS_ED (1 << 2) /* Excessive Deferral */
#define LAN9118_TXS_DEFERRED (1 << 0) /* Deferred */
/* RX Status Format */
#define LAN9118_RXS_FILTFAIL (1 << 30) /* Filtering Fail */
#define LAN9118_RXS_PKTLEN(x) (((x) >> 16) & 0x3fff) /* Packet Len */
#define LAN9118_RXS_ES (1 << 15) /* Error Status */
#define LAN9118_RXS_BCF (1 << 13) /* Broadcast Frame */
#define LAN9118_RXS_LENERR (1 << 12) /* Length Error */
#define LAN9118_RXS_RUNTF (1 << 11) /* Runt Frame */
#define LAN9118_RXS_MCF (1 << 10) /* Multicast Frame */
#define LAN9118_RXS_FTL (1 << 7) /* Frame Too Long */
#define LAN9118_RXS_COLS (1 << 6) /* Collision Seen */
#define LAN9118_RXS_FT (1 << 5) /* Frame Type */
#define LAN9118_RXS_RWTO (1 << 4) /* Rcv Watchdog time-out */
#define LAN9118_RXS_MIIERR (1 << 3) /* MII Error */
#define LAN9118_RXS_DBIT (1 << 2) /* Drabbling Bit */
#define LAN9118_RXS_CRCERR (1 << 1) /* CRC Error */
/* Basic mode control register. */
#define BMCR_RESV 0x003f /* Unused... */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
#define LAN9118_BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
#define LAN9118_BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
#define LAN9118_BMCR_RESET 0x8000 /* Reset the DP83840 */
#define LAN9118_BMSR_LSTATUS 0x0004 /* Link status */
/* Basic mode status register. */
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
#define BMSR_JCD 0x0002 /* Jabber detected */
#define BMSR_LSTATUS 0x0004 /* Link status */
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x00c0 /* Unused... */
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
/* Generic MII registers. */
#define LAN9118_MII_BMCR 0x00 /* Basic mode control register */
#define LAN9118_MII_BMSR 0x01 /* Basic mode status register */
#define LAN9118_MII_ADVERTISE 0x04 /* Advertisement control register */
#endif
#define LAN9118_GPT_CFG_TIMER_EN 0x20000000 /* R/W */
#define LAN9118_RX_STS_PKT_LEN 0x3FFF0000
#define LAN9118_TX_STS_UNDERRUN 0x00000002
#define LAN9118_HW_CFG_SF 0x00100000 /* R/W */
#define LAN9118_INT_STS_RSFL 0x00000008 /* R/WC */
#define LAN9118_INT_EN_RDFL_EN 0x00000020 /* R/W */
#define LAN9118_MAC_CR_HBDIS 0x10000000
#endif /* _LAN9118REG_H_ */

2
bsp/stm32/libraries/HAL_Drivers/drv_wdt.c
View File

@ -109,7 +109,7 @@ int rt_wdt_init(void)
stm32_wdt.hiwdg.Init.Reload = 0x00000FFF;
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) \
|| defined(SOC_SERIES_STM32H7)
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L0)
stm32_wdt.hiwdg.Init.Window = 0x00000FFF;
#endif
stm32_wdt.is_start = 0;

7
bsp/stm32/stm32l475-atk-pandora/board/Kconfig
View File

@ -15,6 +15,13 @@ menu "Onboard Peripheral Drivers"
select BSP_USING_UART1
default y
config BSP_USING_KEY
bool "Enable onboard keys"
select RT_USING_PIN
select RT_USING_TIMER_SOFT
select PKG_USING_MULTIBUTTON
default n
config BSP_USING_QSPI_FLASH
bool "Enable QSPI FLASH (W25Q128 qspi1)"
select BSP_USING_QSPI

5
bsp/stm32/stm32l475-atk-pandora/board/SConscript
View File

@ -12,6 +12,9 @@ board.c
CubeMX_Config/Src/stm32l4xx_hal_msp.c
''')
if GetDepend('BSP_USING_KEY'):
src = src + ['ports/drv_key.c']
if GetDepend(['BSP_USING_QSPI_FLASH']):
src += Glob('ports/drv_qspi_flash.c')
@ -19,7 +22,7 @@ if GetDepend('BSP_USING_SPI_LCD'):
src = src + ['ports/drv_lcd.c']
if GetDepend(['BSP_USING_SDCARD']):
src += Glob('ports/sdcard_port.c')
src += Glob('ports/drv_sdcard.c')
if GetDepend(['BSP_USING_ICM20608']) or GetDepend(['BSP_USING_AHT10']):
src += Glob('ports/sensor_port.c')

122
bsp/stm32/stm32l475-atk-pandora/board/ports/drv_key.c Normal file
View File

@ -0,0 +1,122 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-04-17 Meco Man first version
*/
#include <rtthread.h>
#ifdef BSP_USING_KEY
#define DBG_TAG "KEY"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include <rtdevice.h>
#include <drv_gpio.h>
#include <multi_button.h>
#define KEY0_PIN GET_PIN(D, 10)
#define KEY1_PIN GET_PIN(D, 9)
#define KEY2_PIN GET_PIN(D, 8)
#define KEY_WKUP_PIN GET_PIN(C, 13)
static struct rt_timer key_timer;
static struct button key0;
static struct button key1;
static struct button key2;
static struct button key_wkup;
/*---- user codes area begin ----*/
/*users can modify according to needs*/
static void key0_BtnCallback(void* state)
{
rt_kprintf("key0!\n");
}
static void key1_BtnCallback(void* state)
{
rt_kprintf("key1!\n");
}
static void key2_BtnCallback(void* state)
{
rt_kprintf("key2!\n");
}
static void key_wkup_BtnCallback(void* state)
{
rt_kprintf("key wkup!\n");
}
/*---- user codes area end ----*/
static void _cb_key_timer(void *parameter)
{
button_ticks();
}
static uint8_t _cb_key0_pin_level(void)
{
return rt_pin_read(KEY0_PIN);
}
static uint8_t _cb_key1_pin_level(void)
{
return rt_pin_read(KEY1_PIN);
}
static uint8_t _cb_key2_pin_level(void)
{
return rt_pin_read(KEY2_PIN);
}
static uint8_t _cb_key_wkup_pin_level(void)
{
return rt_pin_read(KEY_WKUP_PIN);
}
static int onboard_key_init(void)
{
rt_timer_init(&key_timer,
"key timer",
_cb_key_timer,
RT_NULL,
rt_tick_from_millisecond(TICKS_INTERVAL),
RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER);
if(rt_timer_start(&key_timer) < 0)
{
LOG_E("drv_key timer initialization failed");
return -1;
}
rt_pin_mode(KEY0_PIN, PIN_MODE_INPUT);
rt_pin_mode(KEY1_PIN, PIN_MODE_INPUT);
rt_pin_mode(KEY2_PIN, PIN_MODE_INPUT);
rt_pin_mode(KEY_WKUP_PIN, PIN_MODE_INPUT);
button_init(&key0, _cb_key0_pin_level, PIN_LOW);
button_init(&key1, _cb_key1_pin_level, PIN_LOW);
button_init(&key2, _cb_key2_pin_level, PIN_LOW);
button_init(&key_wkup, _cb_key_wkup_pin_level, PIN_HIGH);
/*---- user codes area begin ----*/
/*users can modify according to needs*/
button_attach(&key0, PRESS_DOWN, key0_BtnCallback);
button_attach(&key1, PRESS_DOWN, key1_BtnCallback);
button_attach(&key2, PRESS_DOWN, key2_BtnCallback);
button_attach(&key_wkup, PRESS_UP, key_wkup_BtnCallback);
/*---- user codes area end ----*/
button_start(&key0);
button_start(&key1);
button_start(&key2);
button_start(&key_wkup);
return 0;
}
INIT_APP_EXPORT(onboard_key_init);
#endif

6
bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c → bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdcard.c
View File

@ -23,7 +23,7 @@
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
void sd_mount(void *parameter)
static void sd_mount(void *parameter)
{
while (1)
{
@ -43,7 +43,7 @@ void sd_mount(void *parameter)
}
}
int stm32_sdcard_mount(void)
static int onboard_sdcard_mount(void)
{
rt_thread_t tid;
@ -67,7 +67,7 @@ int stm32_sdcard_mount(void)
return RT_EOK;
}
INIT_APP_EXPORT(stm32_sdcard_mount);
INIT_APP_EXPORT(onboard_sdcard_mount);
static int rt_hw_spi1_tfcard(void)
{

6
components/drivers/misc/pin.c
View File

@ -47,7 +47,7 @@ static rt_size_t _pin_write(rt_device_t dev, rt_off_t pos, const void *buffer, r
return size;
}
static rt_err_t _pin_control(rt_device_t dev, int cmd, void *args)
static rt_err_t _pin_control(rt_device_t dev, int cmd, void *args)
{
struct rt_device_pin_mode *mode;
struct rt_device_pin *pin = (struct rt_device_pin *)dev;
@ -111,6 +111,7 @@ rt_err_t rt_pin_attach_irq(rt_int32_t pin, rt_uint32_t mode,
}
return -RT_ENOSYS;
}
rt_err_t rt_pin_detach_irq(rt_int32_t pin)
{
RT_ASSERT(_hw_pin.ops != RT_NULL);
@ -146,7 +147,7 @@ void rt_pin_write(rt_base_t pin, rt_base_t value)
}
FINSH_FUNCTION_EXPORT_ALIAS(rt_pin_write, pinWrite, write value to hardware pin);
int rt_pin_read(rt_base_t pin)
int rt_pin_read(rt_base_t pin)
{
RT_ASSERT(_hw_pin.ops != RT_NULL);
return _hw_pin.ops->pin_read(&_hw_pin.parent, pin);
@ -166,4 +167,3 @@ rt_base_t rt_pin_get(const char *name)
return _hw_pin.ops->pin_get(name);
}
FINSH_FUNCTION_EXPORT_ALIAS(rt_pin_get, pinGet, get pin number from hardware pin);

676
components/drivers/usb/usbdevice/class/audio.h
View File

@ -1,676 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* <linux/usb/audio.h> -- USB Audio definitions.
*
* Copyright (C) 2006 Thumtronics Pty Ltd.
* Developed for Thumtronics by Grey Innovation
* Ben Williamson <ben.williamson@greyinnovation.com>
*
* This software is distributed under the terms of the GNU General Public
* License ("GPL") version 2, as published by the Free Software Foundation.
*
* This file holds USB constants and structures defined
* by the USB Device Class Definition for Audio Devices.
* Comments below reference relevant sections of that document:
*
* http://www.usb.org/developers/devclass_docs/audio10.pdf
*
* Types and defines in this file are either specific to version 1.0 of
* this standard or common for newer versions.
*/
#ifndef _UAPI__LINUX_USB_AUDIO_H
#define _UAPI__LINUX_USB_AUDIO_H
//#include <linux/types.h>
#include <rtthread.h>
typedef int8_t __s8;
typedef uint8_t __u8;
typedef int16_t __s16;
typedef uint16_t __u16;
typedef int32_t __s32;
typedef uint32_t __u32;
typedef int64_t __s64;
typedef uint64_t __u64;
#define UAC_USE_FEATURE_UNIT 0 /* Feature unit does not support */
/*
* Below are truly Linux-specific types that should never collide with
* any application/library that wants linux/types.h.
*/
#ifdef __CHECKER__
#define __bitwise__ __attribute__((bitwise))
#else
#define __bitwise__
#endif
#ifdef __CHECK_ENDIAN__
#define __bitwise __bitwise__
#else
#define __bitwise
#endif
typedef __u16 __bitwise __le16;
typedef __u16 __bitwise __be16;
typedef __u32 __bitwise __le32;
typedef __u32 __bitwise __be32;
typedef __u64 __bitwise __le64;
typedef __u64 __bitwise __be64;
typedef __u16 __bitwise __sum16;
typedef __u32 __bitwise __wsum;
/* bInterfaceProtocol values to denote the version of the standard used */
#define UAC_VERSION_1 0x00
#define UAC_VERSION_2 0x20
#define UAC_VERSION_3 0x30
/* A.2 Audio Interface Subclass Codes */
#define USB_SUBCLASS_AUDIOCONTROL 0x01
#define USB_SUBCLASS_AUDIOSTREAMING 0x02
#define USB_SUBCLASS_MIDISTREAMING 0x03
/* A.5 Audio Class-Specific AC Interface Descriptor Subtypes */
#define UAC_HEADER 0x01
#define UAC_INPUT_TERMINAL 0x02
#define UAC_OUTPUT_TERMINAL 0x03
#define UAC_MIXER_UNIT 0x04
#define UAC_SELECTOR_UNIT 0x05
#define UAC_FEATURE_UNIT 0x06
#define UAC1_PROCESSING_UNIT 0x07
#define UAC1_EXTENSION_UNIT 0x08
/* A.6 Audio Class-Specific AS Interface Descriptor Subtypes */
#define UAC_AS_GENERAL 0x01
#define UAC_FORMAT_TYPE 0x02
#define UAC_FORMAT_SPECIFIC 0x03
/* A.7 Processing Unit Process Types */
#define UAC_PROCESS_UNDEFINED 0x00
#define UAC_PROCESS_UP_DOWNMIX 0x01
#define UAC_PROCESS_DOLBY_PROLOGIC 0x02
#define UAC_PROCESS_STEREO_EXTENDER 0x03
#define UAC_PROCESS_REVERB 0x04
#define UAC_PROCESS_CHORUS 0x05
#define UAC_PROCESS_DYN_RANGE_COMP 0x06
/* A.8 Audio Class-Specific Endpoint Descriptor Subtypes */
#define UAC_EP_GENERAL 0x01
/* A.9 Audio Class-Specific Request Codes */
#define UAC_SET_ 0x00
#define UAC_GET_ 0x80
#define UAC__CUR 0x1
#define UAC__MIN 0x2
#define UAC__MAX 0x3
#define UAC__RES 0x4
#define UAC__MEM 0x5
#define UAC_SET_CUR (UAC_SET_ | UAC__CUR)
#define UAC_GET_CUR (UAC_GET_ | UAC__CUR)
#define UAC_SET_MIN (UAC_SET_ | UAC__MIN)
#define UAC_GET_MIN (UAC_GET_ | UAC__MIN)
#define UAC_SET_MAX (UAC_SET_ | UAC__MAX)
#define UAC_GET_MAX (UAC_GET_ | UAC__MAX)
#define UAC_SET_RES (UAC_SET_ | UAC__RES)
#define UAC_GET_RES (UAC_GET_ | UAC__RES)
#define UAC_SET_MEM (UAC_SET_ | UAC__MEM)
#define UAC_GET_MEM (UAC_GET_ | UAC__MEM)
#define UAC_GET_STAT 0xff
/* A.10 Control Selector Codes */
/* A.10.1 Terminal Control Selectors */
#define UAC_TERM_COPY_PROTECT 0x01
/* A.10.2 Feature Unit Control Selectors */
#define UAC_FU_MUTE 0x01
#define UAC_FU_VOLUME 0x02
#define UAC_FU_BASS 0x03
#define UAC_FU_MID 0x04
#define UAC_FU_TREBLE 0x05
#define UAC_FU_GRAPHIC_EQUALIZER 0x06
#define UAC_FU_AUTOMATIC_GAIN 0x07
#define UAC_FU_DELAY 0x08
#define UAC_FU_BASS_BOOST 0x09
#define UAC_FU_LOUDNESS 0x0a
#define UAC_CONTROL_BIT(CS) (1 << ((CS) - 1))
/* A.10.3.1 Up/Down-mix Processing Unit Controls Selectors */
#define UAC_UD_ENABLE 0x01
#define UAC_UD_MODE_SELECT 0x02
/* A.10.3.2 Dolby Prologic (tm) Processing Unit Controls Selectors */
#define UAC_DP_ENABLE 0x01
#define UAC_DP_MODE_SELECT 0x02
/* A.10.3.3 3D Stereo Extender Processing Unit Control Selectors */
#define UAC_3D_ENABLE 0x01
#define UAC_3D_SPACE 0x02
/* A.10.3.4 Reverberation Processing Unit Control Selectors */
#define UAC_REVERB_ENABLE 0x01
#define UAC_REVERB_LEVEL 0x02
#define UAC_REVERB_TIME 0x03
#define UAC_REVERB_FEEDBACK 0x04
/* A.10.3.5 Chorus Processing Unit Control Selectors */
#define UAC_CHORUS_ENABLE 0x01
#define UAC_CHORUS_LEVEL 0x02
#define UAC_CHORUS_RATE 0x03
#define UAC_CHORUS_DEPTH 0x04
/* A.10.3.6 Dynamic Range Compressor Unit Control Selectors */
#define UAC_DCR_ENABLE 0x01
#define UAC_DCR_RATE 0x02
#define UAC_DCR_MAXAMPL 0x03
#define UAC_DCR_THRESHOLD 0x04
#define UAC_DCR_ATTACK_TIME 0x05
#define UAC_DCR_RELEASE_TIME 0x06
/* A.10.4 Extension Unit Control Selectors */
#define UAC_XU_ENABLE 0x01
/* MIDI - A.1 MS Class-Specific Interface Descriptor Subtypes */
#define UAC_MS_HEADER 0x01
#define UAC_MIDI_IN_JACK 0x02
#define UAC_MIDI_OUT_JACK 0x03
/* MIDI - A.1 MS Class-Specific Endpoint Descriptor Subtypes */
#define UAC_MS_GENERAL 0x01
/* Terminals - 2.1 USB Terminal Types */
#define UAC_TERMINAL_UNDEFINED 0x100
#define UAC_TERMINAL_STREAMING 0x101
#define UAC_TERMINAL_VENDOR_SPEC 0x1FF
/* Terminal Control Selectors */
/* 4.3.2 Class-Specific AC Interface Descriptor */
struct uac1_ac_header_descriptor {
__u8 bLength; /* 8 + n */
__u8 bDescriptorType; /* USB_DT_CS_INTERFACE */
__u8 bDescriptorSubtype; /* UAC_MS_HEADER */
__le16 bcdADC; /* 0x0100 */
__le16 wTotalLength; /* includes Unit and Terminal desc. */
__u8 bInCollection; /* n */
__u8 baInterfaceNr[]; /* [n] */
} __attribute__ ((packed));
#define UAC_DT_AC_HEADER_SIZE(n) (8 + (n))
/* As above, but more useful for defining your own descriptors: */
#define DECLARE_UAC_AC_HEADER_DESCRIPTOR(n) \
struct uac1_ac_header_descriptor_##n { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubtype; \
__le16 bcdADC; \
__le16 wTotalLength; \
__u8 bInCollection; \
__u8 baInterfaceNr[n]; \
} __attribute__ ((packed))
/* 4.3.2.1 Input Terminal Descriptor */
struct uac_input_terminal_descriptor {
__u8 bLength; /* in bytes: 12 */
__u8 bDescriptorType; /* CS_INTERFACE descriptor type */
__u8 bDescriptorSubtype; /* INPUT_TERMINAL descriptor subtype */
__u8 bTerminalID; /* Constant uniquely terminal ID */
__le16 wTerminalType; /* USB Audio Terminal Types */
__u8 bAssocTerminal; /* ID of the Output Terminal associated */
__u8 bNrChannels; /* Number of logical output channels */
__le16 wChannelConfig;
__u8 iChannelNames;
__u8 iTerminal;
} __attribute__ ((packed));
#define UAC_DT_INPUT_TERMINAL_SIZE 12
/* Terminals - 2.2 Input Terminal Types */
#define UAC_INPUT_TERMINAL_UNDEFINED 0x200
#define UAC_INPUT_TERMINAL_MICROPHONE 0x201
#define UAC_INPUT_TERMINAL_DESKTOP_MICROPHONE 0x202
#define UAC_INPUT_TERMINAL_PERSONAL_MICROPHONE 0x203
#define UAC_INPUT_TERMINAL_OMNI_DIR_MICROPHONE 0x204
#define UAC_INPUT_TERMINAL_MICROPHONE_ARRAY 0x205
#define UAC_INPUT_TERMINAL_PROC_MICROPHONE_ARRAY 0x206
/* Terminals - control selectors */
#define UAC_TERMINAL_CS_COPY_PROTECT_CONTROL 0x01
/* 4.3.2.2 Output Terminal Descriptor */
struct uac1_output_terminal_descriptor {
__u8 bLength; /* in bytes: 9 */
__u8 bDescriptorType; /* CS_INTERFACE descriptor type */
__u8 bDescriptorSubtype; /* OUTPUT_TERMINAL descriptor subtype */
__u8 bTerminalID; /* Constant uniquely terminal ID */
__le16 wTerminalType; /* USB Audio Terminal Types */
__u8 bAssocTerminal; /* ID of the Input Terminal associated */
__u8 bSourceID; /* ID of the connected Unit or Terminal*/
__u8 iTerminal;
} __attribute__ ((packed));
#define UAC_DT_OUTPUT_TERMINAL_SIZE 9
/* Terminals - 2.3 Output Terminal Types */
#define UAC_OUTPUT_TERMINAL_UNDEFINED 0x300
#define UAC_OUTPUT_TERMINAL_SPEAKER 0x301
#define UAC_OUTPUT_TERMINAL_HEADPHONES 0x302
#define UAC_OUTPUT_TERMINAL_HEAD_MOUNTED_DISPLAY_AUDIO 0x303
#define UAC_OUTPUT_TERMINAL_DESKTOP_SPEAKER 0x304
#define UAC_OUTPUT_TERMINAL_ROOM_SPEAKER 0x305
#define UAC_OUTPUT_TERMINAL_COMMUNICATION_SPEAKER 0x306
#define UAC_OUTPUT_TERMINAL_LOW_FREQ_EFFECTS_SPEAKER 0x307
/* Terminals - 2.4 Bi-directional Terminal Types */
#define UAC_BIDIR_TERMINAL_UNDEFINED 0x400
#define UAC_BIDIR_TERMINAL_HANDSET 0x401
#define UAC_BIDIR_TERMINAL_HEADSET 0x402
#define UAC_BIDIR_TERMINAL_SPEAKER_PHONE 0x403
#define UAC_BIDIR_TERMINAL_ECHO_SUPPRESSING 0x404
#define UAC_BIDIR_TERMINAL_ECHO_CANCELING 0x405
/* Set bControlSize = 2 as default setting */
#define UAC_DT_FEATURE_UNIT_SIZE(ch) (7 + ((ch) + 1) * 2)
/* As above, but more useful for defining your own descriptors: */
#define DECLARE_UAC_FEATURE_UNIT_DESCRIPTOR(ch) \
struct uac_feature_unit_descriptor_##ch { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubtype; \
__u8 bUnitID; \
__u8 bSourceID; \
__u8 bControlSize; \
__le16 bmaControls[ch + 1]; \
__u8 iFeature; \
} __attribute__ ((packed))
/* 4.3.2.3 Mixer Unit Descriptor */
struct uac_mixer_unit_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubtype;
__u8 bUnitID;
__u8 bNrInPins;
__u8 baSourceID[];
} __attribute__ ((packed));
static inline __u8 uac_mixer_unit_bNrChannels(struct uac_mixer_unit_descriptor *desc)
{
return desc->baSourceID[desc->bNrInPins];
}
static inline __u32 uac_mixer_unit_wChannelConfig(struct uac_mixer_unit_descriptor *desc,
int protocol)
{
if (protocol == UAC_VERSION_1)
return (desc->baSourceID[desc->bNrInPins + 2] << 8) |
desc->baSourceID[desc->bNrInPins + 1];
else
return (desc->baSourceID[desc->bNrInPins + 4] << 24) |
(desc->baSourceID[desc->bNrInPins + 3] << 16) |
(desc->baSourceID[desc->bNrInPins + 2] << 8) |
(desc->baSourceID[desc->bNrInPins + 1]);
}
static inline __u8 uac_mixer_unit_iChannelNames(struct uac_mixer_unit_descriptor *desc,
int protocol)
{
return (protocol == UAC_VERSION_1) ?
desc->baSourceID[desc->bNrInPins + 3] :
desc->baSourceID[desc->bNrInPins + 5];
}
static inline __u8 *uac_mixer_unit_bmControls(struct uac_mixer_unit_descriptor *desc,
int protocol)
{
switch (protocol) {
case UAC_VERSION_1:
return &desc->baSourceID[desc->bNrInPins + 4];
case UAC_VERSION_2:
return &desc->baSourceID[desc->bNrInPins + 6];
case UAC_VERSION_3:
return &desc->baSourceID[desc->bNrInPins + 2];
default:
return NULL;
}
}
static inline __u16 uac3_mixer_unit_wClusterDescrID(struct uac_mixer_unit_descriptor *desc)
{
return (desc->baSourceID[desc->bNrInPins + 1] << 8) |
desc->baSourceID[desc->bNrInPins];
}
static inline __u8 uac_mixer_unit_iMixer(struct uac_mixer_unit_descriptor *desc)
{
__u8 *raw = (__u8 *) desc;
return raw[desc->bLength - 1];
}
/* 4.3.2.4 Selector Unit Descriptor */
struct uac_selector_unit_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubtype;
__u8 bUintID;
__u8 bNrInPins;
__u8 baSourceID[];
} __attribute__ ((packed));
static inline __u8 uac_selector_unit_iSelector(struct uac_selector_unit_descriptor *desc)
{
__u8 *raw = (__u8 *) desc;
return raw[desc->bLength - 1];
}
#if UAC_USE_FEATURE_UNIT
/* 4.3.2.5 Feature Unit Descriptor */
struct uac_feature_unit_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubtype;
__u8 bUnitID;
__u8 bSourceID;
__u8 bControlSize;
__u8 bmaControls[0]; /* variable length */
} __attribute__((packed));
static inline __u8 uac_feature_unit_iFeature(struct uac_feature_unit_descriptor *desc)
{
__u8 *raw = (__u8 *) desc;
return raw[desc->bLength - 1];
}
#endif
/* 4.3.2.6 Processing Unit Descriptors */
struct uac_processing_unit_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubtype;
__u8 bUnitID;
__le16 wProcessType;
__u8 bNrInPins;
__u8 baSourceID[];
} __attribute__ ((packed));
static inline __u8 uac_processing_unit_bNrChannels(struct uac_processing_unit_descriptor *desc)
{
return desc->baSourceID[desc->bNrInPins];
}
static inline __u32 uac_processing_unit_wChannelConfig(struct uac_processing_unit_descriptor *desc,
int protocol)
{
if (protocol == UAC_VERSION_1)
return (desc->baSourceID[desc->bNrInPins + 2] << 8) |
desc->baSourceID[desc->bNrInPins + 1];
else
return (desc->baSourceID[desc->bNrInPins + 4] << 24) |
(desc->baSourceID[desc->bNrInPins + 3] << 16) |
(desc->baSourceID[desc->bNrInPins + 2] << 8) |
(desc->baSourceID[desc->bNrInPins + 1]);
}
static inline __u8 uac_processing_unit_iChannelNames(struct uac_processing_unit_descriptor *desc,
int protocol)
{
return (protocol == UAC_VERSION_1) ?
desc->baSourceID[desc->bNrInPins + 3] :
desc->baSourceID[desc->bNrInPins + 5];
}
static inline __u8 uac_processing_unit_bControlSize(struct uac_processing_unit_descriptor *desc,
int protocol)
{
switch (protocol) {
case UAC_VERSION_1:
return desc->baSourceID[desc->bNrInPins + 4];
case UAC_VERSION_2:
return 2; /* in UAC2, this value is constant */
case UAC_VERSION_3:
return 4; /* in UAC3, this value is constant */
default:
return 1;
}
}
static inline __u8 *uac_processing_unit_bmControls(struct uac_processing_unit_descriptor *desc,
int protocol)
{
switch (protocol) {
case UAC_VERSION_1:
return &desc->baSourceID[desc->bNrInPins + 5];
case UAC_VERSION_2:
return &desc->baSourceID[desc->bNrInPins + 6];
case UAC_VERSION_3:
return &desc->baSourceID[desc->bNrInPins + 2];
default:
return NULL;
}
}
static inline __u8 uac_processing_unit_iProcessing(struct uac_processing_unit_descriptor *desc,
int protocol)
{
__u8 control_size = uac_processing_unit_bControlSize(desc, protocol);
switch (protocol) {
case UAC_VERSION_1:
case UAC_VERSION_2:
default:
return *(uac_processing_unit_bmControls(desc, protocol)
+ control_size);
case UAC_VERSION_3:
return 0; /* UAC3 does not have this field */
}
}
static inline __u8 *uac_processing_unit_specific(struct uac_processing_unit_descriptor *desc,
int protocol)
{
__u8 control_size = uac_processing_unit_bControlSize(desc, protocol);
switch (protocol) {
case UAC_VERSION_1:
case UAC_VERSION_2:
default:
return uac_processing_unit_bmControls(desc, protocol)
+ control_size + 1;
case UAC_VERSION_3:
return uac_processing_unit_bmControls(desc, protocol)
+ control_size;
}
}
/*
* Extension Unit (XU) has almost compatible layout with Processing Unit, but
* on UAC2, it has a different bmControls size (bControlSize); it's 1 byte for
* XU while 2 bytes for PU. The last iExtension field is a one-byte index as
* well as iProcessing field of PU.
*/
static inline __u8 uac_extension_unit_bControlSize(struct uac_processing_unit_descriptor *desc,
int protocol)
{
switch (protocol) {
case UAC_VERSION_1:
return desc->baSourceID[desc->bNrInPins + 4];
case UAC_VERSION_2:
return 1; /* in UAC2, this value is constant */
case UAC_VERSION_3:
return 4; /* in UAC3, this value is constant */
default:
return 1;
}
}
static inline __u8 uac_extension_unit_iExtension(struct uac_processing_unit_descriptor *desc,
int protocol)
{
__u8 control_size = uac_extension_unit_bControlSize(desc, protocol);
switch (protocol) {
case UAC_VERSION_1:
case UAC_VERSION_2:
default:
return *(uac_processing_unit_bmControls(desc, protocol)
+ control_size);
case UAC_VERSION_3:
return 0; /* UAC3 does not have this field */
}
}
/* 4.5.2 Class-Specific AS Interface Descriptor */
struct uac1_as_header_descriptor {
__u8 bLength; /* in bytes: 7 */
__u8 bDescriptorType; /* USB_DT_CS_INTERFACE */
__u8 bDescriptorSubtype; /* AS_GENERAL */
__u8 bTerminalLink; /* Terminal ID of connected Terminal */
__u8 bDelay; /* Delay introduced by the data path */
__le16 wFormatTag; /* The Audio Data Format */
} __attribute__ ((packed));
#define UAC_DT_AS_HEADER_SIZE 7
/* Formats - A.1.1 Audio Data Format Type I Codes */
#define UAC_FORMAT_TYPE_I_UNDEFINED 0x0
#define UAC_FORMAT_TYPE_I_PCM 0x1
#define UAC_FORMAT_TYPE_I_PCM8 0x2
#define UAC_FORMAT_TYPE_I_IEEE_FLOAT 0x3
#define UAC_FORMAT_TYPE_I_ALAW 0x4
#define UAC_FORMAT_TYPE_I_MULAW 0x5
struct uac_format_type_i_continuous_descriptor {
__u8 bLength; /* in bytes: 8 + (ns * 3) */
__u8 bDescriptorType; /* USB_DT_CS_INTERFACE */
__u8 bDescriptorSubtype; /* FORMAT_TYPE */
__u8 bFormatType; /* FORMAT_TYPE_1 */
__u8 bNrChannels; /* physical channels in the stream */
__u8 bSubframeSize; /* */
__u8 bBitResolution;
__u8 bSamFreqType;
__u8 tLowerSamFreq[3];
__u8 tUpperSamFreq[3];
} __attribute__ ((packed));
#define UAC_FORMAT_TYPE_I_CONTINUOUS_DESC_SIZE 14
struct uac_format_type_i_discrete_descriptor {
__u8 bLength; /* in bytes: 8 + (ns * 3) */
__u8 bDescriptorType; /* USB_DT_CS_INTERFACE */
__u8 bDescriptorSubtype; /* FORMAT_TYPE */
__u8 bFormatType; /* FORMAT_TYPE_1 */
__u8 bNrChannels; /* physical channels in the stream */
__u8 bSubframeSize; /* */
__u8 bBitResolution;
__u8 bSamFreqType;
__u8 tSamFreq[][3];
} __attribute__ ((packed));
#define DECLARE_UAC_FORMAT_TYPE_I_DISCRETE_DESC(n) \
struct uac_format_type_i_discrete_descriptor_##n { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubtype; \
__u8 bFormatType; \
__u8 bNrChannels; \
__u8 bSubframeSize; \
__u8 bBitResolution; \
__u8 bSamFreqType; \
__u8 tSamFreq[n][3]; \
} __attribute__ ((packed))
#define UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(n) (8 + (n * 3))
struct uac_format_type_i_ext_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubtype;
__u8 bFormatType;
__u8 bSubslotSize;
__u8 bBitResolution;
__u8 bHeaderLength;
__u8 bControlSize;
__u8 bSideBandProtocol;
} __attribute__((packed));
/* Formats - Audio Data Format Type I Codes */
#define UAC_FORMAT_TYPE_II_MPEG 0x1001
#define UAC_FORMAT_TYPE_II_AC3 0x1002
struct uac_format_type_ii_discrete_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubtype;
__u8 bFormatType;
__le16 wMaxBitRate;
__le16 wSamplesPerFrame;
__u8 bSamFreqType;
__u8 tSamFreq[][3];
} __attribute__((packed));
struct uac_format_type_ii_ext_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubtype;
__u8 bFormatType;
__le16 wMaxBitRate;
__le16 wSamplesPerFrame;
__u8 bHeaderLength;
__u8 bSideBandProtocol;
} __attribute__((packed));
/* type III */
#define UAC_FORMAT_TYPE_III_IEC1937_AC3 0x2001
#define UAC_FORMAT_TYPE_III_IEC1937_MPEG1_LAYER1 0x2002
#define UAC_FORMAT_TYPE_III_IEC1937_MPEG2_NOEXT 0x2003
#define UAC_FORMAT_TYPE_III_IEC1937_MPEG2_EXT 0x2004
#define UAC_FORMAT_TYPE_III_IEC1937_MPEG2_LAYER1_LS 0x2005
#define UAC_FORMAT_TYPE_III_IEC1937_MPEG2_LAYER23_LS 0x2006
/* Formats - A.2 Format Type Codes */
#define UAC_FORMAT_TYPE_UNDEFINED 0x0
#define UAC_FORMAT_TYPE_I 0x1
#define UAC_FORMAT_TYPE_II 0x2
#define UAC_FORMAT_TYPE_III 0x3
#define UAC_EXT_FORMAT_TYPE_I 0x81
#define UAC_EXT_FORMAT_TYPE_II 0x82
#define UAC_EXT_FORMAT_TYPE_III 0x83
struct uac_iso_endpoint_descriptor {
__u8 bLength; /* in bytes: 7 */
__u8 bDescriptorType; /* USB_DT_CS_ENDPOINT */
__u8 bDescriptorSubtype; /* EP_GENERAL */
__u8 bmAttributes;
__u8 bLockDelayUnits;
__le16 wLockDelay;
} __attribute__((packed));
#define UAC_ISO_ENDPOINT_DESC_SIZE 7
#define UAC_EP_CS_ATTR_SAMPLE_RATE 0x01
#define UAC_EP_CS_ATTR_PITCH_CONTROL 0x02
#define UAC_EP_CS_ATTR_FILL_MAX 0x80
/* status word format (3.7.1.1) */
#define UAC1_STATUS_TYPE_ORIG_MASK 0x0f
#define UAC1_STATUS_TYPE_ORIG_AUDIO_CONTROL_IF 0x0
#define UAC1_STATUS_TYPE_ORIG_AUDIO_STREAM_IF 0x1
#define UAC1_STATUS_TYPE_ORIG_AUDIO_STREAM_EP 0x2
#define UAC1_STATUS_TYPE_IRQ_PENDING (1 << 7)
#define UAC1_STATUS_TYPE_MEM_CHANGED (1 << 6)
struct uac1_status_word {
__u8 bStatusType;
__u8 bOriginator;
} __attribute__((packed));
#endif /* _UAPI__LINUX_USB_AUDIO_H */

61
components/drivers/usb/usbdevice/class/audio_mic.c
View File

@ -11,7 +11,8 @@
#include <rthw.h>
#include <rtdevice.h>
#include "drivers/usb_device.h"
#include "audio.h"
#include "uaudioreg.h"
#define DBG_TAG "usbd.audio.mic"
#define DBG_LVL DBG_INFO
@ -46,9 +47,6 @@
#define UAC_MAX_PACKET_SIZE 64
#define UAC_EP_MAX_PACKET_SIZE 32
#define UAC_CHANNEL_NUM RECORD_CHANNEL
#define UAC_INTR_NUM 1
#define UAC_CH_NUM 1
#define UAC_FORMAT_NUM 1
struct uac_ac_descriptor
{
@ -56,21 +54,21 @@ struct uac_ac_descriptor
struct uiad_descriptor iad_desc;
#endif
struct uinterface_descriptor intf_desc;
DECLARE_UAC_AC_HEADER_DESCRIPTOR(UAC_INTR_NUM) hdr_desc;
struct uac_input_terminal_descriptor it_desc;
struct uac1_output_terminal_descriptor ot_desc;
struct usb_audio_control_descriptor hdr_desc;
struct usb_audio_input_terminal it_desc;
struct usb_audio_output_terminal ot_desc;
#if UAC_USE_FEATURE_UNIT
DECLARE_UAC_FEATURE_UNIT_DESCRIPTOR(UAC_CH_NUM) feature_unit_desc;
struct usb_audio_feature_unit feature_unit_desc;
#endif
};
struct uac_as_descriptor
{
struct uinterface_descriptor intf_desc;
struct uac1_as_header_descriptor hdr_desc;
DECLARE_UAC_FORMAT_TYPE_I_DISCRETE_DESC(UAC_FORMAT_NUM) format_type_desc;
struct usb_audio_streaming_interface_descriptor hdr_desc;
struct usb_audio_streaming_type1_descriptor format_type_desc;
struct uendpoint_descriptor ep_desc;
struct uac_iso_endpoint_descriptor as_ep_desc;
struct usb_audio_streaming_endpoint_descriptor as_ep_desc;
};
/*
@ -169,9 +167,9 @@ static struct uac_ac_descriptor ac_desc =
},
/* Header Descriptor */
{
UAC_DT_AC_HEADER_SIZE(UAC_INTR_NUM),
sizeof(struct usb_audio_control_descriptor),
UAC_CS_INTERFACE,
UAC_HEADER,
UDESCSUB_AC_HEADER,
0x0100, /* Version: 1.00 */
0x001E, /* Total length: 30 */
0x01, /* Total number of interfaces: 1 */
@ -179,9 +177,9 @@ static struct uac_ac_descriptor ac_desc =
},
/* Input Terminal Descriptor */
{
UAC_DT_INPUT_TERMINAL_SIZE,
sizeof(struct usb_audio_input_terminal),
UAC_CS_INTERFACE,
UAC_INPUT_TERMINAL,
UDESCSUB_AC_INPUT,
0x01, /* Terminal ID: 1 */
0x0201, /* Terminal Type: Microphone (0x0201) */
0x00, /* Assoc Terminal: 0 */
@ -192,9 +190,9 @@ static struct uac_ac_descriptor ac_desc =
},
/* Output Terminal Descriptor */
{
UAC_DT_OUTPUT_TERMINAL_SIZE,
sizeof(struct usb_audio_output_terminal),
UAC_CS_INTERFACE,
UAC_OUTPUT_TERMINAL,
UDESCSUB_AC_OUTPUT,
0x02, /* Terminal ID: 2 */
0x0101, /* Terminal Type: USB Streaming (0x0101) */
0x00, /* Assoc Terminal: 0 */
@ -204,11 +202,12 @@ static struct uac_ac_descriptor ac_desc =
#if UAC_USE_FEATURE_UNIT
/* Feature unit Descriptor */
{
UAC_DT_FEATURE_UNIT_SIZE(UAC_CH_NUM),
sizeof(struct usb_audio_feature_unit),
UAC_CS_INTERFACE,
UAC_FEATURE_UNIT,
UDESCSUB_AC_FEATURE,
0x02,
0x0101,
0x01,
0x01,
0x00,
0x01,
},
@ -246,19 +245,19 @@ static struct uac_as_descriptor as_desc =
},
/* General AS Descriptor */
{
UAC_DT_AS_HEADER_SIZE,
sizeof(struct usb_audio_streaming_interface_descriptor),
UAC_CS_INTERFACE,
UAC_AS_GENERAL,
AS_GENERAL,
0x02, /* Terminal ID: 2 */
0x01, /* Interface delay in frames: 1 */
UAC_FORMAT_TYPE_I_PCM,
UA_FMT_PCM,
},
/* Format type i Descriptor */
{
UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(UAC_FORMAT_NUM),
sizeof(struct usb_audio_streaming_type1_descriptor),
UAC_CS_INTERFACE,
UAC_FORMAT_TYPE,
UAC_FORMAT_TYPE_I,
FORMAT_TYPE,
FORMAT_TYPE_I,
UAC_CHANNEL_NUM,
2, /* Subframe Size: 2 */
RESOLUTION_BITS,
@ -276,9 +275,9 @@ static struct uac_as_descriptor as_desc =
},
/* AS Endpoint Descriptor */
{
UAC_ISO_ENDPOINT_DESC_SIZE,
sizeof(struct usb_audio_streaming_endpoint_descriptor),
UAC_CS_ENDPOINT,
UAC_MS_GENERAL,
AS_GENERAL,
},
};
@ -476,9 +475,9 @@ static rt_err_t _uac_descriptor_config(struct uac_ac_descriptor *ac,
static rt_err_t _uac_samplerate_config(struct uac_as_descriptor *as, rt_uint32_t samplerate)
{
as->format_type_desc.tSamFreq[0][2] = samplerate >> 16 & 0xff;
as->format_type_desc.tSamFreq[0][1] = samplerate >> 8 & 0xff;
as->format_type_desc.tSamFreq[0][0] = samplerate & 0xff;
as->format_type_desc.tSamFreq[0 * 3 + 2] = samplerate >> 16 & 0xff;
as->format_type_desc.tSamFreq[0 * 3 + 1] = samplerate >> 8 & 0xff;
as->format_type_desc.tSamFreq[0 * 3 + 0] = samplerate & 0xff;
return RT_EOK;
}

55
components/drivers/usb/usbdevice/class/audio_speaker.c
View File

@ -11,7 +11,9 @@
#include <rthw.h>
#include <rtdevice.h>
#include "drivers/usb_device.h"
#include "audio.h"
#define AUFMT_MAX_FREQUENCIES 1
#include "uaudioreg.h"
#define DBG_TAG "usbd.audio.speaker"
#define DBG_LVL DBG_INFO
@ -46,9 +48,6 @@
#define UAC_MAX_PACKET_SIZE 64
#define UAC_EP_MAX_PACKET_SIZE 32
#define UAC_CHANNEL_NUM AUDIO_CHANNEL
#define UAC_INTR_NUM 1
#define UAC_CH_NUM 1
#define UAC_FORMAT_NUM 1
struct uac_ac_descriptor
{
@ -56,21 +55,21 @@ struct uac_ac_descriptor
struct uiad_descriptor iad_desc;
#endif
struct uinterface_descriptor intf_desc;
DECLARE_UAC_AC_HEADER_DESCRIPTOR(UAC_INTR_NUM) hdr_desc;
struct uac_input_terminal_descriptor it_desc;
struct uac1_output_terminal_descriptor ot_desc;
struct usb_audio_control_descriptor hdr_desc;
struct usb_audio_input_terminal it_desc;
struct usb_audio_output_terminal ot_desc;
#if UAC_USE_FEATURE_UNIT
DECLARE_UAC_FEATURE_UNIT_DESCRIPTOR(UAC_CH_NUM) feature_unit_desc;
struct usb_audio_feature_unit feature_unit_desc;
#endif
};
struct uac_as_descriptor
{
struct uinterface_descriptor intf_desc;
struct uac1_as_header_descriptor hdr_desc;
DECLARE_UAC_FORMAT_TYPE_I_DISCRETE_DESC(UAC_FORMAT_NUM) format_type_desc;
struct usb_audio_streaming_interface_descriptor hdr_desc;
struct usb_audio_streaming_type1_descriptor format_type_desc;
struct uendpoint_descriptor ep_desc;
struct uac_iso_endpoint_descriptor as_ep_desc;
struct usb_audio_streaming_endpoint_descriptor as_ep_desc;
};
/*
@ -169,9 +168,9 @@ static struct uac_ac_descriptor ac_desc =
},
/* Header Descriptor */
{
UAC_DT_AC_HEADER_SIZE(UAC_INTR_NUM),
sizeof(struct usb_audio_control_descriptor),
UAC_CS_INTERFACE,
UAC_HEADER,
UDESCSUB_AC_HEADER,
0x0100, /* Version: 1.00 */
0x0027, /* Total length: 39 */
0x01, /* Total number of interfaces: 1 */
@ -179,9 +178,9 @@ static struct uac_ac_descriptor ac_desc =
},
/* Input Terminal Descriptor */
{
UAC_DT_INPUT_TERMINAL_SIZE,
sizeof(struct usb_audio_input_terminal),
UAC_CS_INTERFACE,
UAC_INPUT_TERMINAL,
UDESCSUB_AC_INPUT,
0x01, /* Terminal ID: 1 */
0x0101, /* Terminal Type: USB Streaming (0x0101) */
0x00, /* Assoc Terminal: 0 */
@ -192,9 +191,9 @@ static struct uac_ac_descriptor ac_desc =
},
/* Output Terminal Descriptor */
{
UAC_DT_OUTPUT_TERMINAL_SIZE,
sizeof(struct usb_audio_output_terminal),
UAC_CS_INTERFACE,
UAC_OUTPUT_TERMINAL,
UDESCSUB_AC_OUTPUT,
0x02, /* Terminal ID: 2 */
0x0302, /* Terminal Type: Headphones (0x0302) */
0x00, /* Assoc Terminal: 0 */
@ -246,19 +245,19 @@ static struct uac_as_descriptor as_desc =
},
/* General AS Descriptor */
{
UAC_DT_AS_HEADER_SIZE,
sizeof(struct usb_audio_streaming_interface_descriptor),
UAC_CS_INTERFACE,
UAC_AS_GENERAL,
AS_GENERAL,
0x01, /* Terminal ID: 1 */
0x01, /* Interface delay in frames: 1 */
UAC_FORMAT_TYPE_I_PCM,
UA_FMT_PCM,
},
/* Format type i Descriptor */
{
UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(UAC_FORMAT_NUM),
sizeof(struct usb_audio_streaming_type1_descriptor),
UAC_CS_INTERFACE,
UAC_FORMAT_TYPE,
UAC_FORMAT_TYPE_I,
FORMAT_TYPE,
FORMAT_TYPE_I,
UAC_CHANNEL_NUM,
2, /* Subframe Size: 2 */
RESOLUTION_BITS,
@ -276,9 +275,9 @@ static struct uac_as_descriptor as_desc =
},
/* AS Endpoint Descriptor */
{
UAC_ISO_ENDPOINT_DESC_SIZE,
sizeof(struct usb_audio_streaming_endpoint_descriptor),
UAC_CS_ENDPOINT,
UAC_MS_GENERAL,
AS_GENERAL,
},
};
@ -477,9 +476,9 @@ static rt_err_t _uac_descriptor_config(struct uac_ac_descriptor *ac,
static rt_err_t _uac_samplerate_config(struct uac_as_descriptor *as, rt_uint32_t samplerate)
{
as->format_type_desc.tSamFreq[0][2] = samplerate >> 16 & 0xff;
as->format_type_desc.tSamFreq[0][1] = samplerate >> 8 & 0xff;
as->format_type_desc.tSamFreq[0][0] = samplerate & 0xff;
as->format_type_desc.tSamFreq[0 * 3 + 2] = samplerate >> 16 & 0xff;
as->format_type_desc.tSamFreq[0 * 3 + 1] = samplerate >> 8 & 0xff;
as->format_type_desc.tSamFreq[0 * 3 + 0] = samplerate & 0xff;
return RT_EOK;
}

418
components/drivers/usb/usbdevice/class/uaudioreg.h Normal file
View File

@ -0,0 +1,418 @@
/* $NetBSD: uaudioreg.h,v 1.15.38.1 2012/06/02 11:09:29 mrg Exp $ */
/*
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Lennart Augustsson (lennart@augustsson.net) at
* Carlstedt Research & Technology.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <rtdef.h>
typedef uint8_t uByte;
typedef uint16_t uWord;
#define UPACKED __attribute__ ((packed))
#define UAUDIO_VERSION 0x100
#define USB_SUBCLASS_AUDIOCONTROL 1
#define USB_SUBCLASS_AUDIOSTREAMING 2
#define USB_SUBCLASS_AUDIOMIDISTREAM 3
#define UDESC_CS_CONFIG 0x22
#define UDESC_CS_STRING 0x23
#define UDESC_CS_INTERFACE 0x24
#define UDESC_CS_ENDPOINT 0x25
#define UDESCSUB_AC_HEADER 1
#define UDESCSUB_AC_INPUT 2
#define UDESCSUB_AC_OUTPUT 3
#define UDESCSUB_AC_MIXER 4
#define UDESCSUB_AC_SELECTOR 5
#define UDESCSUB_AC_FEATURE 6
#define UDESCSUB_AC_PROCESSING 7
#define UDESCSUB_AC_EXTENSION 8
#ifndef AUFMT_MAX_FREQUENCIES
#define AUFMT_MAX_FREQUENCIES 1
#endif
/* The first fields are identical to usb_endpoint_descriptor_t */
typedef struct {
uByte bLength;
uByte bDescriptorType;
uByte bEndpointAddress;
uByte bmAttributes;
uWord wMaxPacketSize;
uByte bInterval;
/*
* The following two entries are only used by the Audio Class.
* And according to the specs the Audio Class is the only one
* allowed to extend the endpoint descriptor.
* Who knows what goes on in the minds of the people in the USB
* standardization? :-(
*/
uByte bRefresh;
uByte bSynchAddress;
} UPACKED usb_endpoint_descriptor_audio_t;
/* generic, for iteration */
typedef struct {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
} UPACKED uaudio_cs_descriptor_t;
struct usb_audio_control_descriptor {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uWord bcdADC;
uWord wTotalLength;
uByte bInCollection;
uByte baInterfaceNr[1];
} UPACKED;
struct usb_audio_streaming_interface_descriptor {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bTerminalLink;
uByte bDelay;
uWord wFormatTag;
} UPACKED;
struct usb_audio_streaming_endpoint_descriptor {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bmAttributes;
#define UA_SED_FREQ_CONTROL 0x01
#define UA_SED_PITCH_CONTROL 0x02
#define UA_SED_MAXPACKETSONLY 0x80
uByte bLockDelayUnits;
uWord wLockDelay;
} UPACKED;
struct usb_audio_streaming_type1_descriptor {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bFormatType;
uByte bNrChannels;
uByte bSubFrameSize;
uByte bBitResolution;
uByte bSamFreqType;
#define UA_SAMP_CONTNUOUS 0
uByte tSamFreq[3*AUFMT_MAX_FREQUENCIES];
#define UA_GETSAMP(p, n) ((p)->tSamFreq[(n)*3+0] | ((p)->tSamFreq[(n)*3+1] << 8) | ((p)->tSamFreq[(n)*3+2] << 16))
#define UA_SAMP_LO(p) UA_GETSAMP(p, 0)
#define UA_SAMP_HI(p) UA_GETSAMP(p, 1)
} UPACKED;
struct usb_audio_cluster {
uByte bNrChannels;
uWord wChannelConfig;
#define UA_CHANNEL_LEFT 0x0001
#define UA_CHANNEL_RIGHT 0x0002
#define UA_CHANNEL_CENTER 0x0004
#define UA_CHANNEL_LFE 0x0008
#define UA_CHANNEL_L_SURROUND 0x0010
#define UA_CHANNEL_R_SURROUND 0x0020
#define UA_CHANNEL_L_CENTER 0x0040
#define UA_CHANNEL_R_CENTER 0x0080
#define UA_CHANNEL_SURROUND 0x0100
#define UA_CHANNEL_L_SIDE 0x0200
#define UA_CHANNEL_R_SIDE 0x0400
#define UA_CHANNEL_TOP 0x0800
uByte iChannelNames;
} UPACKED;
/* Shared by all units and terminals */
struct usb_audio_unit {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bUnitId;
};
/* UDESCSUB_AC_INPUT */
struct usb_audio_input_terminal {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bTerminalId;
uWord wTerminalType;
uByte bAssocTerminal;
uByte bNrChannels;
uWord wChannelConfig;
uByte iChannelNames;
uByte iTerminal;
} UPACKED;
/* UDESCSUB_AC_OUTPUT */
struct usb_audio_output_terminal {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bTerminalId;
uWord wTerminalType;
uByte bAssocTerminal;
uByte bSourceId;
uByte iTerminal;
} UPACKED;
/* UDESCSUB_AC_MIXER */
struct usb_audio_mixer_unit {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bUnitId;
uByte bNrInPins;
uByte baSourceId[255]; /* [bNrInPins] */
/* struct usb_audio_mixer_unit_1 */
} UPACKED;
struct usb_audio_mixer_unit_1 {
uByte bNrChannels;
uWord wChannelConfig;
uByte iChannelNames;
uByte bmControls[255]; /* [bNrChannels] */
/*uByte iMixer;*/
} UPACKED;
/* UDESCSUB_AC_SELECTOR */
struct usb_audio_selector_unit {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bUnitId;
uByte bNrInPins;
uByte baSourceId[255]; /* [bNrInPins] */
/* uByte iSelector; */
} UPACKED;
/* UDESCSUB_AC_FEATURE */
struct usb_audio_feature_unit {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bUnitId;
uByte bSourceId;
uByte bControlSize;
uByte bmaControls[2]; /* size for more than enough */
/* uByte iFeature; */
} UPACKED;
/* UDESCSUB_AC_PROCESSING */
struct usb_audio_processing_unit {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bUnitId;
uWord wProcessType;
uByte bNrInPins;
uByte baSourceId[255]; /* [bNrInPins] */
/* struct usb_audio_processing_unit_1 */
} UPACKED;
struct usb_audio_processing_unit_1{
uByte bNrChannels;
uWord wChannelConfig;
uByte iChannelNames;
uByte bControlSize;
uByte bmControls[255]; /* [bControlSize] */
#define UA_PROC_ENABLE_MASK 1
} UPACKED;
struct usb_audio_processing_unit_updown {
uByte iProcessing;
uByte bNrModes;
uWord waModes[255]; /* [bNrModes] */
} UPACKED;
/* UDESCSUB_AC_EXTENSION */
struct usb_audio_extension_unit {
uByte bLength;
uByte bDescriptorType;
uByte bDescriptorSubtype;
uByte bUnitId;
uWord wExtensionCode;
uByte bNrInPins;
uByte baSourceId[255]; /* [bNrInPins] */
/* struct usb_audio_extension_unit_1 */
} UPACKED;
struct usb_audio_extension_unit_1 {
uByte bNrChannels;
uWord wChannelConfig;
uByte iChannelNames;
uByte bControlSize;
uByte bmControls[255]; /* [bControlSize] */
#define UA_EXT_ENABLE_MASK 1
#define UA_EXT_ENABLE 1
/*uByte iExtension;*/
} UPACKED;
/* USB terminal types */
#define UAT_UNDEFINED 0x0100
#define UAT_STREAM 0x0101
#define UAT_VENDOR 0x01ff
/* input terminal types */
#define UATI_UNDEFINED 0x0200
#define UATI_MICROPHONE 0x0201
#define UATI_DESKMICROPHONE 0x0202
#define UATI_PERSONALMICROPHONE 0x0203
#define UATI_OMNIMICROPHONE 0x0204
#define UATI_MICROPHONEARRAY 0x0205
#define UATI_PROCMICROPHONEARR 0x0206
/* output terminal types */
#define UATO_UNDEFINED 0x0300
#define UATO_SPEAKER 0x0301
#define UATO_HEADPHONES 0x0302
#define UATO_DISPLAYAUDIO 0x0303
#define UATO_DESKTOPSPEAKER 0x0304
#define UATO_ROOMSPEAKER 0x0305
#define UATO_COMMSPEAKER 0x0306
#define UATO_SUBWOOFER 0x0307
/* bidir terminal types */
#define UATB_UNDEFINED 0x0400
#define UATB_HANDSET 0x0401
#define UATB_HEADSET 0x0402
#define UATB_SPEAKERPHONE 0x0403
#define UATB_SPEAKERPHONEESUP 0x0404
#define UATB_SPEAKERPHONEECANC 0x0405
/* telephony terminal types */
#define UATT_UNDEFINED 0x0500
#define UATT_PHONELINE 0x0501
#define UATT_TELEPHONE 0x0502
#define UATT_DOWNLINEPHONE 0x0503
/* external terminal types */
#define UATE_UNDEFINED 0x0600
#define UATE_ANALOGCONN 0x0601
#define UATE_DIGITALAUIFC 0x0602
#define UATE_LINECONN 0x0603
#define UATE_LEGACYCONN 0x0604
#define UATE_SPDIF 0x0605
#define UATE_1394DA 0x0606
#define UATE_1394DV 0x0607
/* embedded function terminal types */
#define UATF_UNDEFINED 0x0700
#define UATF_CALIBNOISE 0x0701
#define UATF_EQUNOISE 0x0702
#define UATF_CDPLAYER 0x0703
#define UATF_DAT 0x0704
#define UATF_DCC 0x0705
#define UATF_MINIDISK 0x0706
#define UATF_ANALOGTAPE 0x0707
#define UATF_PHONOGRAPH 0x0708
#define UATF_VCRAUDIO 0x0709
#define UATF_VIDEODISCAUDIO 0x070a
#define UATF_DVDAUDIO 0x070b
#define UATF_TVTUNERAUDIO 0x070c
#define UATF_SATELLITE 0x070d
#define UATF_CABLETUNER 0x070e
#define UATF_DSS 0x070f
#define UATF_RADIORECV 0x0710
#define UATF_RADIOXMIT 0x0711
#define UATF_MULTITRACK 0x0712
#define UATF_SYNTHESIZER 0x0713
#define SET_CUR 0x01
#define GET_CUR 0x81
#define SET_MIN 0x02
#define GET_MIN 0x82
#define SET_MAX 0x03
#define GET_MAX 0x83
#define SET_RES 0x04
#define GET_RES 0x84
#define SET_MEM 0x05
#define GET_MEM 0x85
#define GET_STAT 0xff
#define MUTE_CONTROL 0x01
#define VOLUME_CONTROL 0x02
#define BASS_CONTROL 0x03
#define MID_CONTROL 0x04
#define TREBLE_CONTROL 0x05
#define GRAPHIC_EQUALIZER_CONTROL 0x06
#define AGC_CONTROL 0x07
#define DELAY_CONTROL 0x08
#define BASS_BOOST_CONTROL 0x09
#define LOUDNESS_CONTROL 0x0a
#define FU_MASK(u) (1 << ((u)-1))
#define MASTER_CHAN 0
#define AS_GENERAL 1
#define FORMAT_TYPE 2
#define FORMAT_SPECIFIC 3
#define UA_FMT_PCM 1
#define UA_FMT_PCM8 2
#define UA_FMT_IEEE_FLOAT 3
#define UA_FMT_ALAW 4
#define UA_FMT_MULAW 5
#define UA_FMT_MPEG 0x1001
#define UA_FMT_AC3 0x1002
#define SAMPLING_FREQ_CONTROL 0x01
#define PITCH_CONTROL 0x02
#define FORMAT_TYPE_UNDEFINED 0
#define FORMAT_TYPE_I 1
#define FORMAT_TYPE_II 2
#define FORMAT_TYPE_III 3
#define UA_PROC_MASK(n) (1<< ((n)-1))
#define PROCESS_UNDEFINED 0
#define XX_ENABLE_CONTROL 1
#define UPDOWNMIX_PROCESS 1
#define UD_ENABLE_CONTROL 1
#define UD_MODE_SELECT_CONTROL 2
#define DOLBY_PROLOGIC_PROCESS 2
#define DP_ENABLE_CONTROL 1
#define DP_MODE_SELECT_CONTROL 2
#define P3D_STEREO_EXTENDER_PROCESS 3
#define P3D_ENABLE_CONTROL 1
#define P3D_SPACIOUSNESS_CONTROL 2
#define REVERBATION_PROCESS 4
#define RV_ENABLE_CONTROL 1
#define RV_LEVEL_CONTROL 2
#define RV_TIME_CONTROL 3
#define RV_FEEDBACK_CONTROL 4
#define CHORUS_PROCESS 5
#define CH_ENABLE_CONTROL 1
#define CH_LEVEL_CONTROL 2
#define CH_RATE_CONTROL 3
#define CH_DEPTH_CONTROL 4
#define DYN_RANGE_COMP_PROCESS 6
#define DR_ENABLE_CONTROL 1
#define DR_COMPRESSION_RATE_CONTROL 2
#define DR_MAXAMPL_CONTROL 3
#define DR_THRESHOLD_CONTROL 4
#define DR_ATTACK_TIME_CONTROL 5
#define DR_RELEASE_TIME_CONTROL 6