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[BSP][airm2m] 同步lib修改,包括sram加锁、修复获取rtc频率错误等 (#7718)

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Dozingfiretruck 2023-06-27 10:41:59 +08:00 committed by GitHub
parent ce4a9c324d
commit 78dcc3d2c8
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6 changed files with 498 additions and 90 deletions
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2
bsp/airm2m/air32f103/README.md
View File

@ -14,7 +14,7 @@
## 开发板介绍
Air32F103为系列芯片，首发型号为Air32F103CBT6，其外设和硬件设计兼容市场上一些主流F103型号，主频最高可达216M，32K RAM+128K Flash，每个IO都可设置独立的内部上下拉电阻。
Air32F103为系列芯片，首发型号为Air32F103CBT6，其外设和硬件设计兼容市场上一些主流F103型号，主频最高可达216M，96K RAM+128K Flash，每个IO都可设置独立的内部上下拉电阻。
开发板外观如下图所示：

30
bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/air32f10x_flash.c
View File

@ -296,7 +296,7 @@ void FLASH_Unlock(void)
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/* Authorize the FPEC of Bank2 Access */
FLASH->KEYR2 = FLASH_KEY1;
FLASH->KEYR2 = FLASH_KEY2;
@ -318,7 +318,7 @@ void FLASH_UnlockBank1(void)
FLASH->KEYR = FLASH_KEY2;
}
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/**
* @brief Unlocks the FLASH Bank2 Program Erase Controller.
* @note This function can be used only for AIR32F10X_XL density devices.
@ -348,7 +348,7 @@ void FLASH_Lock(void)
/* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
FLASH->CR |= CR_LOCK_Set;
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
FLASH->CR2 |= CR_LOCK_Set;
#endif /* AIR32F10X_XL */
@ -369,7 +369,7 @@ void FLASH_LockBank1(void)
FLASH->CR |= CR_LOCK_Set;
}
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/**
* @brief Locks the FLASH Bank2 Program Erase Controller.
* @note This function can be used only for AIR32F10X_XL density devices.
@ -396,7 +396,7 @@ FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Page_Address));
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
if(Page_Address < FLASH_BANK1_END_ADDRESS)
{
/* Wait for last operation to be completed */
@ -467,7 +467,7 @@ FLASH_Status FLASH_EraseAllPages(void)
{
FLASH_Status status = FLASH_COMPLETE;
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
@ -548,7 +548,7 @@ FLASH_Status FLASH_EraseAllBank1Pages(void)
return status;
}
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/**
* @brief Erases all Bank2 FLASH pages.
* @note This function can be used only for AIR32F103_XL density devices.
@ -754,7 +754,7 @@ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
if(Address < FLASH_BANK1_END_ADDRESS - 2)
{
/* Wait for last operation to be completed */
@ -929,7 +929,7 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
@ -1222,7 +1222,7 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint
return status;
}
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/**
* @brief Configures to boot from Bank1 or Bank2.
* @note This function can be used only for AIR32F103_XL density devices.
@ -1361,7 +1361,7 @@ FlagStatus FLASH_GetPrefetchBufferStatus(void)
*/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
{
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/* Check the parameters */
assert_param(IS_FLASH_IT(FLASH_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
@ -1430,7 +1430,7 @@ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
{
FlagStatus bitstatus = RESET;
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/* Check the parameters */
assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
if(FLASH_FLAG == FLASH_FLAG_OPTERR)
@ -1514,7 +1514,7 @@ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
*/
void FLASH_ClearFlag(uint32_t FLASH_FLAG)
{
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/* Check the parameters */
assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
@ -1614,7 +1614,7 @@ FLASH_Status FLASH_GetBank1Status(void)
return flashstatus;
}
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/**
* @brief Returns the FLASH Bank2 Status.
* @note This function can be used for AIR32F103_XL density devices.
@ -1712,7 +1712,7 @@ FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
return status;
}
#ifdef AIR32F10X_XL
#if defined(AIR32F10X_XL) || defined(AIR32F10X_MD_1024K)
/**
* @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
* @note This function can be used only for AIR32F103_XL density devices.

6
bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/air32f10x_rcc.c
View File

@ -89,7 +89,7 @@
#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0x9FFF3FFF)
#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x6000C000)
/* CSR register bit mask */
#define CSR_RMVF_Set ((uint32_t)0x01000000)
@ -126,7 +126,7 @@
*/
static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
static __I uint8_t ADCPrescTable[16] = {2, 4, 6, 8, 16, 32, 36, 48, 64, 72, 96, 120, 144, 168, 192 ,216};
/**
* @}
@ -682,7 +682,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
/* Get ADCCLK prescaler */
tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
tmp = tmp >> 14;
tmp = ((tmp >> 27) | (tmp >> 14)) & 0x0F;
presc = ADCPrescTable[tmp];
/* ADCCLK clock frequency */
RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;

391
bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/system_air32f10x.c
View File

@ -1,3 +1,55 @@
/**
******************************************************************************
* @file GPIO/IOToggle/system_air32f10x.c
* @author MCD Application Team
* @version V3.5.0
* @date 08-April-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* factors, AHB/APBx prescalers and Flash settings).
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_air32f10x_xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_air32f10x_xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
* the product used), refer to "HSE_VALUE" define in "air32f10x.h" file.
* When HSE is used as system clock source, directly or through PLL, and you
* are using different crystal you have to adapt the HSE value to your own
* configuration.
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
@ -6,15 +58,69 @@
* @{
*/
/** @addtogroup air32f10x_System_Private_Includes
* @{
*/
#include "air32f10x.h"
//#define SYSCLK_FREQ_HSE HSE_VALUE
//#define SYSCLK_FREQ_24MHz 24000000
//#define SYSCLK_FREQ_36MHz 36000000
//#define SYSCLK_FREQ_48MHz 48000000
//#define SYSCLK_FREQ_56MHz 56000000
/**
* @}
*/
/** @addtogroup air32f10x_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup air32f10x_System_Private_Defines
* @{
*/
/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
frequency (after reset the HSI is used as SYSCLK source)
IMPORTANT NOTE:
==============
1. After each device reset the HSI is used as System clock source.
2. Please make sure that the selected System clock doesn't exceed your device's
maximum frequency.
3. If none of the define below is enabled, the HSI is used as System clock
source.
4. The System clock configuration functions provided within this file assume that:
- For Low, Medium and High density Value line devices an external 8MHz
crystal is used to drive the System clock.
- For Low, Medium and High density devices an external 8MHz crystal is
used to drive the System clock.
- For Connectivity line devices an external 25MHz crystal is used to drive
the System clock.
If you are using different crystal you have to adapt those functions accordingly.
*/
#if defined (air32f10x_LD_VL) || (defined air32f10x_MD_VL) || (defined air32f10x_HD_VL)
/* #define SYSCLK_FREQ_HSE HSE_VALUE */
#define SYSCLK_FREQ_24MHz 24000000
#else
/* #define SYSCLK_FREQ_HSE HSE_VALUE */
/* #define SYSCLK_FREQ_24MHz 24000000 */
/* #define SYSCLK_FREQ_36MHz 36000000 */
/* #define SYSCLK_FREQ_48MHz 48000000 */
/* #define SYSCLK_FREQ_56MHz 56000000 */
#define SYSCLK_FREQ_72MHz 72000000
#endif
/*!< Uncomment the following line if you need to use external SRAM mounted
on air3210E-EVAL board (air32 High density and XL-density devices) or on
air32100E-EVAL board (air32 High-density value line devices) as data memory */
#if defined (air32f10x_HD) || (defined air32f10x_XL) || (defined air32f10x_HD_VL)
/* #define DATA_IN_ExtSRAM */
#endif
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@ -110,7 +216,11 @@ void SystemInit (void)
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef air32f10x_CL
RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* air32f10x_CL */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
@ -121,9 +231,32 @@ void SystemInit (void)
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
#ifdef air32f10x_CL
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined (air32f10x_LD_VL) || defined (air32f10x_MD_VL) || (defined air32f10x_HD_VL)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* air32f10x_CL */
#if defined (air32f10x_HD) || (defined air32f10x_XL) || (defined air32f10x_HD_VL)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();
@ -174,6 +307,14 @@ void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0;
#ifdef air32f10x_CL
uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
#endif /* air32f10x_CL */
#if defined (air32f10x_LD_VL) || defined (air32f10x_MD_VL) || (defined air32f10x_HD_VL)
uint32_t prediv1factor = 0;
#endif /* air32f10x_LD_VL or air32f10x_MD_VL or air32f10x_HD_VL */
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
@ -191,6 +332,7 @@ void SystemCoreClockUpdate (void)
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#ifndef air32f10x_CL
pllmull = ( pllmull >> 18) + 2;
if (pllsource == 0x00)
@ -200,6 +342,11 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (air32f10x_LD_VL) || defined (air32f10x_MD_VL) || (defined air32f10x_HD_VL)
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */
@ -209,8 +356,47 @@ void SystemCoreClockUpdate (void)
{
SystemCoreClock = HSE_VALUE * pllmull;
}
#endif
}
#else
pllmull = pllmull >> 18;
if (pllmull != 0x0D)
{
pllmull += 2;
}
else
{ /* PLL multiplication factor = PLL input clock * 6.5 */
pllmull = 13 / 2;
}
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{/* PREDIV1 selected as PLL clock entry */
/* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
if (prediv1source == 0)
{
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
}
else
{/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
#endif /* air32f10x_CL */
break;
default:
@ -250,6 +436,59 @@ static void SetSysClock(void)
source (default after reset) */
}
/**
* @brief Setup the external memory controller. Called in startup_air32f10x.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_air32f10x_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on air3210E-EVAL
* board (air32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*!< FSMC Bank1 NOR/SRAM3 is used for the air3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */
/* Enable FSMC clock */
RCC->AHBENR = 0x00000114;
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0;
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
GPIOD->CRL = 0x44BB44BB;
GPIOD->CRH = 0xBBBBBBBB;
GPIOE->CRL = 0xB44444BB;
GPIOE->CRH = 0xBBBBBBBB;
GPIOF->CRL = 0x44BBBBBB;
GPIOF->CRH = 0xBBBB4444;
GPIOG->CRL = 0x44BBBBBB;
GPIOG->CRH = 0x44444B44;
/*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
FSMC_Bank1->BTCR[4] = 0x00001011;
FSMC_Bank1->BTCR[5] = 0x00000200;
}
#endif /* DATA_IN_ExtSRAM */
#ifdef SYSCLK_FREQ_HSE
/**
* @brief Selects HSE as System clock source and configure HCLK, PCLK2
@ -284,13 +523,27 @@ static void SetSysClockToHSE(void)
if (HSEStatus == (uint32_t)0x01)
{
#if !defined air32f10x_LD_VL && !defined air32f10x_MD_VL && !defined air32f10x_HD_VL
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
#ifndef air32f10x_CL
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#else
if (HSE_VALUE <= 24000000)
{
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
}
else
{
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
}
#endif /* air32f10x_CL */
#endif
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
@ -349,12 +602,14 @@ static void SetSysClockTo24(void)
if (HSEStatus == (uint32_t)0x01)
{
#if !defined air32f10x_LD_VL && !defined air32f10x_MD_VL && !defined air32f10x_HD_VL
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
@ -365,9 +620,35 @@ static void SetSysClockTo24(void)
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
#ifdef air32f10x_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL6);
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
#elif defined (air32f10x_LD_VL) || defined (air32f10x_MD_VL) || defined (air32f10x_HD_VL)
/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
#else
/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
#endif /* air32f10x_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
@ -441,9 +722,34 @@ static void SetSysClockTo36(void)
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
#ifdef air32f10x_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL9);
/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
#else
/* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
#endif /* air32f10x_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
@ -517,9 +823,33 @@ static void SetSysClockTo48(void)
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef air32f10x_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL6);
#else
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
#endif /* air32f10x_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
@ -594,10 +924,35 @@ static void SetSysClockTo56(void)
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef air32f10x_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL7);
#else
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
#endif /* air32f10x_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
@ -672,10 +1027,34 @@ static void SetSysClockTo72(void)
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef air32f10x_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL9);
#else
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* air32f10x_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;

142
bsp/airm2m/air32f103/libraries/Startup/arm/startup_air32f10x.s
View File

@ -118,70 +118,70 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SYMC_IRQHandler
DCD RNG_IRQHandler
DCD SENSOR_IRQHandler
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
;DCD 0X20005000
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
;DCD 0X20005000
;DCD BOOT_RAM
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -189,7 +189,7 @@ __Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;
BOOT_RAM PROC
BOOT_RAM PROC
EXPORT BOOT_RAM [WEAK]
IMPORT __main
IMPORT SystemInit
@ -198,14 +198,14 @@ BOOT_RAM PROC
LDR R0, =__main
BX R0
ENDP
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
LDR R0,=0x400210F0
LDR R0,=0x400210F0
MOV R1,#0x00000001
STR R1,[R0]
LDR R2,=0x40016C00
LDR R2,=0x40016C00
LDR R3,=0xa7d93a86
STR R3,[R2]
LDR R3,=0xab12dfcd
@ -217,6 +217,20 @@ Reset_Handler PROC
LDR R4,=0x4002228c
LDR R5,=0xa5a5a5a5
STR R5,[R4]
;lock
LDR R2,=0x400210F0
LDR R3,=0x00000000
STR R3,[R2]
LDR R2,=0x40016C00
LDR R3,=0x5826c579
STR R3,[R2]
LDR R3,=0x54ed2032
STR R3,[R2]
LDR R3,=0x3212cad9
STR R3,[R2]
LDR R2,=0x4002228c
LDR R3,=0x5a5a5a5a
STR R3,[R2]
MOV R1,#0x00000000
IMPORT __main
IMPORT SystemInit

17
bsp/airm2m/air32f103/libraries/Startup/gcc/startup_air32f10x.s
View File

@ -65,7 +65,7 @@ FillZerobss:
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/*unlock*/
ldr r0,=0x400210F0
mov r1,#0x00000001
str r1,[r0]
@ -81,6 +81,21 @@ LoopFillZerobss:
ldr r4,=0x4002228c
ldr r5,=0xa5a5a5a5
str r5,[r4]
/*lock*/
ldr r2,=0x400210f0
ldr r3,=0x00000000
str r3,[r2]
ldr r2,=0x40016c00
ldr r3,=0x5826c579
str r3,[r2]
ldr r3,=0x54ed2032
str r3,[r2]
ldr r3,=0x3212cad9
str r3,[r2]
ldr r2,=0x4002228c
ldr r3,=0x5a5a5a5a
str r3,[r2]
mov r1,#0x00000000
/* Call the clock system intitialization function.*/