[bsp/n32g452xx] Unified header file definition. "GPIO_H__" to "DRV_GPIO_H". "USART_H" to "DRV_USART_H"
[bsp/n32g452xx] In drv_pwm.c, variable meaning is different with RT-Thread interface definition. Fixed and tested. [bsp/n32g452xx] Add support for UART4/UART5. [bsp/n32g452xx] In drv_gpio.c Modify "N32F10X_PIN_NUMBERS" to "N32G45X_PIN_NUMBERS".
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09f439bcc2
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@ -15,7 +15,7 @@ src += ['drv_clk.c']
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if GetDepend(['BSP_USING_GPIO']):
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src += ['drv_gpio.c']
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if GetDepend(['BSP_USING_UART']):
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if GetDepend(['RT_USING_WDT']):
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src += ['drv_wdt.c']
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if GetDepend(['BSP_USING_UART']):
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@ -15,7 +15,7 @@
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#ifdef RT_USING_PIN
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#define N32F10X_PIN_NUMBERS 64 //[48, 64, 100, 144 ]
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#define N32G45X_PIN_NUMBERS 64 //[48, 64, 100, 144 ]
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#define __N32_PIN(index, rcc, gpio, gpio_index) \
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{ \
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@ -37,7 +37,7 @@ struct pin_index
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static const struct pin_index pins[] =
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{
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#if (N32F10X_PIN_NUMBERS == 48)
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#if (N32G45X_PIN_NUMBERS == 48)
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__N32_PIN_DEFAULT,
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__N32_PIN_DEFAULT,
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__N32_PIN(2, APB2, C, 13),
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@ -89,7 +89,7 @@ static const struct pin_index pins[] =
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__N32_PIN_DEFAULT,
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#endif
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#if (N32F10X_PIN_NUMBERS == 64)
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#if (N32G45X_PIN_NUMBERS == 64)
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__N32_PIN_DEFAULT,
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__N32_PIN_DEFAULT,
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__N32_PIN(2, APB2, C, 13),
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@ -156,7 +156,7 @@ static const struct pin_index pins[] =
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__N32_PIN_DEFAULT,
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__N32_PIN_DEFAULT,
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#endif
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#if (N32F10X_PIN_NUMBERS == 100)
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#if (N32G45X_PIN_NUMBERS == 100)
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__N32_PIN_DEFAULT,
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__N32_PIN(1, APB2, E, 2),
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__N32_PIN(2, APB2, E, 3),
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@ -259,7 +259,7 @@ static const struct pin_index pins[] =
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__N32_PIN_DEFAULT,
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__N32_PIN_DEFAULT,
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#endif
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#if (N32F10X_PIN_NUMBERS == 144)
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#if (N32G45X_PIN_NUMBERS == 144)
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__N32_PIN_DEFAULT,
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__N32_PIN(1, APB2, E, 2),
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__N32_PIN(2, APB2, E, 3),
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@ -7,9 +7,10 @@
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* Date Author Notes
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* 2015-01-05 Bernard the first version
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*/
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#ifndef GPIO_H__
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#define GPIO_H__
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#ifndef __DRV_GPIO_H__
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#define __DRV_GPIO_H__
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int n32_hw_pin_init(void);
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#endif
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#endif /* __DRV_GPIO_H__ */
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@ -29,6 +29,7 @@
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#endif /* RT_USING_PWM */
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#define MAX_PERIOD 65535
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#define MIN_PERIOD 3
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#ifdef BSP_USING_PWM
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@ -207,6 +208,9 @@ static rt_err_t drv_pwm_set(struct n32_pwm *pwm_dev, struct rt_pwm_configuration
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{
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TIM_Module *TIMx = pwm_dev->tim_handle;
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rt_uint32_t channel = configuration->channel;
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rt_uint32_t period;
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rt_uint64_t psc;
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rt_uint32_t pulse;
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/* Init timer pin and enable clock */
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void n32_msp_tim_init(void *Instance);
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@ -228,25 +232,33 @@ static rt_err_t drv_pwm_set(struct n32_pwm *pwm_dev, struct rt_pwm_configuration
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input_clock = RCC_Clock.Pclk1Freq * 2;
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}
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input_clock /= 1000000UL;
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/* Convert nanosecond to frequency and duty cycle. */
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rt_uint32_t period = (unsigned long long)configuration->period ;
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rt_uint64_t psc = period / MAX_PERIOD + 1;
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period = (unsigned long long)configuration->period * input_clock / 1000ULL;
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psc = period / MAX_PERIOD + 1;
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period = period / psc;
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psc = psc * (input_clock / 1000000);
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if (period < MIN_PERIOD)
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{
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period = MIN_PERIOD;
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}
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if ((pwm_dev->period != period) || (pwm_dev->psc != psc))
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{
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/* TIMe base configuration */
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/* Tim base configuration */
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TIM_TimeBaseInitType TIM_TIMeBaseStructure;
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TIM_InitTimBaseStruct(&TIM_TIMeBaseStructure);
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TIM_TIMeBaseStructure.Period = period;
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TIM_TIMeBaseStructure.Period = period - 1;
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TIM_TIMeBaseStructure.Prescaler = psc - 1;
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TIM_TIMeBaseStructure.ClkDiv = 0;
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TIM_TIMeBaseStructure.CntMode = TIM_CNT_MODE_UP;
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TIM_InitTimeBase(TIMx, &TIM_TIMeBaseStructure);
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}
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rt_uint32_t pulse = (unsigned long long)configuration->pulse;
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pulse = (unsigned long long)configuration->pulse * input_clock / psc / 1000ULL;
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if (pulse > period)
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{
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pulse = period;
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}
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/* PWM1 Mode configuration: Channel1 */
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OCInitType TIM_OCInitStructure;
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TIM_InitOcStruct(&TIM_OCInitStructure);
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@ -437,12 +437,46 @@ void DMA2_Channel3_IRQHandler(void)
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rt_interrupt_enter();
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dma_rx_done_isr(&serial4);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif /* BSP_USING_UART4 */
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#if defined(BSP_USING_UART5)
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/* UART5 device driver structure */
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struct n32_uart uart5 =
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{
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UART5,
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UART5_IRQn,
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{
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DMA1_CH8,
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DMA1,
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DMA1_FLAG_GL8,
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DMA1_Channel8_IRQn,
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0,
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},
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};
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struct rt_serial_device serial5;
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void UART5_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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uart_isr(&serial5);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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void DMA1_Channel8_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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dma_rx_done_isr(&serial5);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif /* BSP_USING_UART5 */
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static void NVIC_Configuration(struct n32_uart *uart)
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{
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NVIC_InitType NVIC_InitStructure;
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@ -552,6 +586,31 @@ int rt_hw_usart_init(void)
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uart);
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#endif /* BSP_USING_UART3 */
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#if defined(BSP_USING_UART4)
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uart = &uart4;
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config.baud_rate = BAUD_RATE_115200;
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serial4.ops = &n32_uart_ops;
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serial4.config = config;
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NVIC_Configuration(uart);
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/* register UART3 device */
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rt_hw_serial_register(&serial4, "uart4",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
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RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
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uart);
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#endif /* BSP_USING_UART4 */
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#if defined(BSP_USING_UART5)
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uart = &uart5;
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config.baud_rate = BAUD_RATE_115200;
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serial5.ops = &n32_uart_ops;
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serial5.config = config;
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NVIC_Configuration(uart);
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/* register UART3 device */
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rt_hw_serial_register(&serial5, "uart5",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
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RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
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uart);
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#endif /* BSP_USING_UART5 */
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return RT_EOK;
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}
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@ -8,9 +8,9 @@
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* 2009-01-05 Bernard the first version
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*/
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#ifndef __USART_H__
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#define __USART_H__
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#ifndef __DRV_USART_H__
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#define __DRV_USART_H__
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int rt_hw_usart_init(void);
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#endif
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#endif /* __DRV_USART_H__ */
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@ -49,6 +49,15 @@ menu "On-chip Peripheral Drivers"
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config BSP_USING_UART3
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bool "Enable UART3"
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default n
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config BSP_USING_UART4
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bool "Enable UART4"
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default n
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config BSP_USING_UART5
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bool "Enable UART5"
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default n
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endif
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menuconfig BSP_USING_PWM
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