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rt-thread-official
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Merge pull request #1080 from TanekLiang/imxrt 

[bsp] update i.mx rt bsp
This commit is contained in:
Bernard Xiong 2017-12-07 18:32:55 +08:00 committed by GitHub
parent d3ddf3b0a7 5fe9bcd176
commit 749fa2b73a
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
28 changed files with 1179 additions and 3924 deletions
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70
bsp/imxrt1052-evk/.config
View File

@ -8,12 +8,15 @@
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_DEBUG=y
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_DEBUG_INIT=0
# CONFIG_RT_DEBUG_THREAD is not set
CONFIG_RT_DEBUG_THREAD=0
CONFIG_RT_USING_HOOK=y
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
@ -32,15 +35,18 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_HEAP=y
CONFIG_RT_USING_SMALL_MEM=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
@ -78,8 +84,13 @@ CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=4
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
CONFIG_RT_DFS_ELM_USE_LFN_0=y
@ -94,6 +105,9 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_NET is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
@ -111,6 +125,11 @@ CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SDIO=y
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
@ -118,10 +137,8 @@ CONFIG_RT_USING_SDIO=y
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_POSIX is not set
#
# Network stack
@ -141,6 +158,13 @@ CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
# CONFIG_LWIP_USING_DHCPD is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
# CONFIG_RT_LWIP_RAW is not set
@ -178,6 +202,17 @@ CONFIG_LWIP_SO_RCVBUF=1
#
# CONFIG_RT_USING_GUIENGINE is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
#
# RT-Thread online packages
#
@ -187,24 +222,30 @@ CONFIG_LWIP_SO_RCVBUF=1
#
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
#
# IoT - internet of things
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEB_TERMINAL is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
#
# language packages
#
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
@ -214,15 +255,18 @@ CONFIG_LWIP_SO_RCVBUF=1
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_ELOG is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
#
# BSP_SPECIAL CONFIG
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
CONFIG_RT_USING_UART=y
CONFIG_RT_USING_UART1=y

25
bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf
View File

@ -45,20 +45,20 @@
** ###################################################################
*/
#define m_interrupts_start 0x60002000
#define m_interrupts_size 0x00000400
#define m_text_start 0x60002400
#define m_text_size 0x1F7FDC00
#define m_text_start 0x60002000
#define m_text_size 0x1F7FE000
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#define Stack_Size 0x1000
#endif
#if (defined(__heap_size__))
@ -69,23 +69,22 @@
LR_m_text m_text_start m_text_size { ; load region size_region
ER_m_text m_text_start m_text_size { ; load address = execution address
* (RESET,+FIRST)
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
ARM_LIB_STACK +0 EMPTY Stack_Size { ; Stack region growing down
}
}
LR_m_interrupts m_interrupts_start m_interrupts_size {
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
}

45
bsp/imxrt1052-evk/Libraries/arm/evkmimxrt1050_flexspi_nor.ini Normal file
View File

@ -0,0 +1,45 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void Setup (void) {
SP = _RDWORD(0x60002000); // Setup Stack Pointer
PC = _RDWORD(0x60002004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

66
bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld
View File

@ -53,14 +53,33 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
/* Specify the memory areas */
MEMORY
{
m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00000400
m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00000400
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000
m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000
m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
}
/* Define output sections */
SECTIONS
{
.boot_data :
{
KEEP(*(.bootdata))
} > m_boot_data
.image_vertor_table :
{
KEEP(*(.ivt))
} > m_image_vertor_table
/* The startup code goes first into internal RAM */
.interrupts :
{
@ -87,6 +106,23 @@ SECTIONS
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
} > m_text
.ARM.extab :
@ -173,7 +209,7 @@ SECTIONS
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
} > m_dtcm
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
.ncache.init : AT(__NDATA_ROM)
@ -182,14 +218,14 @@ SECTIONS
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_data
} > m_dtcm
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
} > m_dtcm
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
@ -209,32 +245,22 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
} > m_dtcm
.stack :
{
. = ALIGN(8);
stack_start = .;
. += STACK_SIZE;
} > m_data
stack_end = .;
heap_start = .;
} > m_dtcm
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
__StackTop = stack_end;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

56
bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_ram.ld
View File

@ -54,8 +54,14 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x00020000
/* m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 */
m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
/* m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 */
/* m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 */
/* m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 */
}
/* Define output sections */
@ -87,6 +93,23 @@ SECTIONS
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
} > m_text
.ARM.extab :
@ -173,7 +196,7 @@ SECTIONS
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
} > m_dtcm
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
.ncache.init : AT(__NDATA_ROM)
@ -182,14 +205,14 @@ SECTIONS
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_data
} > m_dtcm
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
} > m_dtcm
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
@ -209,32 +232,21 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
} > m_dtcm
.stack :
{
. = ALIGN(8);
stack_start = .;
. += STACK_SIZE;
} > m_data
stack_end = .;
heap_start = .;
} > m_dtcm
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
__StackTop = stack_end;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

4
bsp/imxrt1052-evk/Libraries/gcc/startup_MIMXRT1052.S
View File

@ -36,6 +36,10 @@
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
#define __STARTUP_INITIALIZE_NONCACHEDATA
#define __STARTUP_CLEAR_BSS
.syntax unified
.arch armv7-m

47
bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_flexspi_nor.icf
View File

@ -47,14 +47,23 @@
define symbol m_interrupts_start = 0x60002000;
define symbol m_interrupts_end = 0x600023FF;
define symbol m_text_start = 0x60002400;
define symbol m_text_end = 0x7F7FFFFF;
define symbol m_itcm_start = 0x00000000;
define symbol m_itcm_end = 0x0001FFFF;
define symbol m_data_start = 0x20000000;
define symbol m_data_end = 0x2001FFFF;
define symbol m_spiflash_start = 0x60002400;
define symbol m_spiflash_end = 0x7F7FFFFF;
define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x2023FFFF;
define symbol m_dtcm_start = 0x20000000;
define symbol m_dtcm_end = 0x2001FFFF;
define symbol m_ocram_start = 0x20200000;
define symbol m_ocram_end = 0x2023FFFF;
define symbol m_sdram_start = 0x80000000;
define symbol m_sdram_end = 0x81DFFFFF;
define symbol m_ncache_start = 0x81E00000;
define symbol m_ncache_end = 0x81FFFFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
@ -75,11 +84,13 @@ define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
| mem:[from m_spiflash_start to m_spiflash_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define region ITCM_region = mem:[from m_itcm_start to m_itcm_end];
define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end];
define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end];
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
@ -92,10 +103,14 @@ do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in DATA_region { block NCACHE_VAR };
place in CSTACK_region { block CSTACK };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place in TEXT_region { readonly };
place in DTCM_region { block RW };
place in DTCM_region { block ZI };
place in DTCM_region { last block HEAP };
place in DTCM_region { block CSTACK };
place in NCACHE_region { block NCACHE_VAR };

2
bsp/imxrt1052-evk/Libraries/system_MIMXRT1052.c
View File

@ -116,6 +116,8 @@ void SystemInit (void) {
SCB_EnableDCache();
#endif
extern void rt_lowlevel_init(void);
rt_lowlevel_init();
}
/* ----------------------------------------------------------------------------

137
bsp/imxrt1052-evk/applications/main.c
View File

@ -30,63 +30,116 @@
#include <dfs_file.h>
#endif
#ifdef RT_USING_DEVICE
#include <rtdevice.h>
#endif
#include <board.h>
RT_USED MPU_Type *mpu = MPU;
RT_USED IOMUXC_GPR_Type *iomuxc_gpr = IOMUXC_GPR;
static void dump_clock(void)
void dump_clock(void)
{
rt_kprintf("CPU clock: %d\n", CLOCK_GetFreq(kCLOCK_CpuClk));
rt_kprintf("AHB clock : %d\n", CLOCK_GetFreq(kCLOCK_AhbClk));
rt_kprintf("SEMC clock : %d\n", CLOCK_GetFreq(kCLOCK_SemcClk));
rt_kprintf("IPG clock : %d\n", CLOCK_GetFreq(kCLOCK_IpgClk));
rt_kprintf("OSC clock selected : %d\n", CLOCK_GetFreq(kCLOCK_OscClk));
rt_kprintf("RTC clock: %d\n", CLOCK_GetFreq(kCLOCK_RtcClk));
rt_kprintf("ARMPLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_ArmPllClk));
rt_kprintf("USB1PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk));
rt_kprintf("USB1PLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));
rt_kprintf("USB1PLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk));
rt_kprintf("USB1PLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk));
rt_kprintf("USB1PLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk));
rt_kprintf("USB2PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk));
rt_kprintf("SYSPLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllClk));
rt_kprintf("SYSPLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk));
rt_kprintf("SYSPLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk));
rt_kprintf("SYSPLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk));
rt_kprintf("SYSPLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk));
rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk));
rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk));
rt_kprintf("Enet PLLCLK ref_enetpll2 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll2Clk));
rt_kprintf("Audio PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_AudioPllClk));
rt_kprintf("Video PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_VideoPllClk));
rt_kprintf("IPG clock : %d\n", CLOCK_GetFreq(kCLOCK_IpgClk));
rt_kprintf("OSC clock selected : %d\n", CLOCK_GetFreq(kCLOCK_OscClk));
rt_kprintf("RTC clock: %d\n", CLOCK_GetFreq(kCLOCK_RtcClk));
rt_kprintf("ARMPLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_ArmPllClk));
rt_kprintf("USB1PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk));
rt_kprintf("USB1PLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));
rt_kprintf("USB1PLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk));
rt_kprintf("USB1PLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk));
rt_kprintf("USB1PLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk));
rt_kprintf("USB2PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk));
rt_kprintf("SYSPLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllClk));
rt_kprintf("SYSPLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk));
rt_kprintf("SYSPLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk));
rt_kprintf("SYSPLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk));
rt_kprintf("SYSPLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk));
rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk));
rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk));
rt_kprintf("Enet PLLCLK ref_enetpll2 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll2Clk));
rt_kprintf("Audio PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_AudioPllClk));
rt_kprintf("Video PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_VideoPllClk));
}
void dump_tcm(void)
void dump_cc_info(void)
{
#define DUMP_REG(__REG) \
rt_kprintf("%s(%08p): %08x\n", #__REG, &(__REG), __REG)
DUMP_REG(IOMUXC_GPR->GPR14);
DUMP_REG(IOMUXC_GPR->GPR16);
DUMP_REG(IOMUXC_GPR->GPR17);
#if defined(__CC_ARM)
rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION);
#elif defined(__ICCARM__)
rt_kprintf("using iccarm, version: %d\n", __VER__);
#elif defined(__GNUC__)
rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__);
#endif
}
void dump_link_info(void)
{
#if defined(__CC_ARM)
#elif defined(__ICCARM__)
#elif defined(__GNUC__)
#define DUMP_SYMBOL(__SYM) \
extern int __SYM; \
rt_kprintf("%s: %p\n", #__SYM, &__SYM)
DUMP_SYMBOL(__fsymtab_start);
DUMP_SYMBOL(__fsymtab_end);
DUMP_SYMBOL(__vsymtab_start);
DUMP_SYMBOL(__vsymtab_end);
DUMP_SYMBOL(__rt_init_start);
DUMP_SYMBOL(__rt_init_end);
DUMP_SYMBOL(__exidx_start);
DUMP_SYMBOL(__exidx_end);
DUMP_SYMBOL(__etext);
DUMP_SYMBOL(__data_start__);
DUMP_SYMBOL(__data_end__);
DUMP_SYMBOL(__noncachedata_start__);
DUMP_SYMBOL(__noncachedata_init_end__);
DUMP_SYMBOL(__noncachedata_end__);
DUMP_SYMBOL(__bss_start__);
DUMP_SYMBOL(__bss_end__);
DUMP_SYMBOL(stack_start);
DUMP_SYMBOL(stack_end);
DUMP_SYMBOL(heap_start);
#endif
}
int main(void)
{
rt_uint32_t result;
//dump_clock();
//dump_tcm();
rt_thread_delay(RT_TICK_PER_SECOND * 2);
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
rt_kprintf("File System initialized!\n");
dump_cc_info();
dump_link_info();
rt_kprintf("build time: %s %s\n", __DATE__, __TIME__);
#if defined(RT_USING_DFS) && defined(RT_USING_SDIO)
result = mmcsd_wait_cd_changed(RT_TICK_PER_SECOND);
if (result == MMCSD_HOST_PLUGED)
{
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
rt_kprintf("File System initialized!\n");
else
rt_kprintf("File System init failed!\n");
}
else
rt_kprintf("File System init failed!\n");
{
rt_kprintf("sdcard init fail or timeout: %d!\n", result);
}
#endif
while (1)
{
rt_thread_delay(RT_TICK_PER_SECOND);

50
bsp/imxrt1052-evk/applications/mem_dump.c Normal file
View File

@ -0,0 +1,50 @@
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-12-05 Tanek first version
*/
#include <rtthread.h>
static void mem_dump(uint32_t buffer, uint32_t length)
{
uint32_t *buf = (uint32_t *)buffer;
int i;
for (i = 0; i < length / 4; i++)
{
rt_kprintf("0x%08X,", buf[i]);
if (i % 8 == 7)
{
rt_kprintf("\n");
}
else
{
rt_kprintf(" ");
}
}
}
#ifdef RT_USING_FINSH
#include <finsh.h>
FINSH_FUNCTION_EXPORT(mem_dump, dump memory);
#endif

95
bsp/imxrt1052-evk/bsp/imxrt/imxrt1052_sdram.icf
View File

@ -1,95 +0,0 @@
/*
** ###################################################################
** Processor: MIMXRT1052DVL6A
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: i.MX 6RT for ROM
** Version: rev. 0.1, 2017-01-10
** Build: b170608
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol m_interrupts_start = 0x00000000;
define symbol m_interrupts_end = 0x000003FF;
define symbol m_text_start = 0x00000400;
define symbol m_text_end = 0x0001FFFF;
define symbol m_data_start = 0x80020000;
define symbol m_data_end = 0x800FFFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly, block RTT_INIT_FUNC };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in CSTACK_region { block CSTACK };

2
bsp/imxrt1052-evk/drivers/SConscript
View File

@ -8,6 +8,8 @@ cwd = os.path.join(str(Dir('#')), 'drivers')
src = Split("""
board.c
usart.c
hyper_flash_boot.c
drv_sdram.c
""")
CPPPATH = [cwd]

94
bsp/imxrt1052-evk/drivers/board.c
View File

@ -18,6 +18,8 @@
#include "board.h"
#include "usart.h"
static struct rt_memheap system_heap;
/* ARM PLL configuration for RUN mode */
const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U };
@ -29,14 +31,14 @@ const clock_usb_pll_config_t usb1PllConfig = { .loopDivider = 0U };
static void BOARD_BootClockGate(void)
{
/* Disable all unused peripheral clock */
CCM->CCGR0 = 0x00C0000FU;
CCM->CCGR1 = 0x30000000U;
CCM->CCGR2 = 0x003F0030U;
CCM->CCGR3 = 0xF0000330U;
CCM->CCGR4 = 0x0000FF3CU;
CCM->CCGR5 = 0xF000330FU;
CCM->CCGR6 = 0x00FC0300U;
// /* Disable all unused peripheral clock */
// CCM->CCGR0 = 0x00C0000FU;
// CCM->CCGR1 = 0x30000000U;
// CCM->CCGR2 = 0x003F0030U;
// CCM->CCGR3 = 0xF0000330U;
// CCM->CCGR4 = 0x0000FF3CU;
// CCM->CCGR5 = 0xF000330FU;
// CCM->CCGR6 = 0x00FC0300U;
}
static void BOARD_BootClockRUN(void)
@ -83,6 +85,64 @@ static void BOARD_BootClockRUN(void)
}
/* MPU configuration. */
static void BOARD_ConfigMPU(void)
{
/* Disable I cache and D cache */
SCB_DisableICache();
SCB_DisableDCache();
/* Disable MPU */
ARM_MPU_Disable();
/* Region 0 setting */
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 1 setting */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 2 setting */
// spi flash: normal type, cacheable, no bufferable, no shareable
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 3 setting */
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 4 setting */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 5 setting */
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 6 setting */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
#if defined(SDRAM_MPU_INIT)
/* Region 7 setting */
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
/* Region 8 setting */
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
#endif
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
/* Enable I cache and D cache */
SCB_EnableDCache();
SCB_EnableICache();
}
/**
* This is the timer interrupt service routine.
*
@ -98,17 +158,23 @@ void SysTick_Handler(void)
rt_interrupt_leave();
}
void rt_lowlevel_init(void)
{
BOARD_ConfigMPU();
extern int imxrt_sdram_init(void);
imxrt_sdram_init();
}
/**
* This function will initial LPC8XX board.
*/
void rt_hw_board_init()
{
BOARD_BootClockRUN();
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
extern int imxrt_hw_usart_init(void);
imxrt_hw_usart_init();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
@ -119,7 +185,11 @@ void rt_hw_board_init()
#endif
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END);
rt_system_heap_init((void*)SDRAM_BEGIN, (void*)SDRAM_END);
rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
rt_memheap_init(&system_heap, "system", (void *)HEAP_BEGIN, HEAP_SIZE);
#endif
}

22
bsp/imxrt1052-evk/drivers/board.h
View File

@ -21,18 +21,26 @@
#include <fsl_iomuxc.h>
#ifdef __CC_ARM
extern int Image$$RW_m_data$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_m_data$$ZI$$Limit)
extern int Image$$ARM_LIB_STACK$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$ARM_LIB_STACK$$ZI$$Limit)
#define HEAP_END (0x2001FFFFu)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#define HEAP_BEGIN (__segment_end("HEAP"))
#define HEAP_END (0x2001FFFFu)
#else
extern int __data_end__;
#define HEAP_BEGIN (&__data_end__)
extern int heap_start;
#define HEAP_BEGIN (&heap_start)
#define HEAP_END (0x2001FFFFu)
#endif
#define HEAP_END 0x81DFFFFF
//#define HEAP_END 0x2001FFFF
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
#define SDRAM_MPU_INIT
#define SDRAM_BEGIN (0x80000000u)
#define SDRAM_END (0x81E00000u)
void rt_hw_board_init(void);

163
bsp/imxrt1052-evk/drivers/drv_eth.c
View File

@ -28,7 +28,7 @@
#include <netif/ethernetif.h>
#include "lwipopts.h"
#define ENET_RXBD_NUM (4)
#define ENET_TXBD_NUM (4)
#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
@ -36,16 +36,17 @@
#define PHY_ADDRESS 0x02u
/* debug option */
//#define DEBUG
//#define ETH_RX_DUMP
//#define ETH_TX_DUMP
#ifdef DEBUG
#define ETH_PRINTF rt_kprintf
#else
#define ETH_PRINTF(...)
#endif
#define DBG_ENABLE
#define DBG_SECTION_NAME "[ETH]"
#define DBG_COLOR
#define DBG_LEVEL DBG_INFO
#include <rtdbg.h>
#define MAX_ADDR_LEN 6
@ -54,12 +55,12 @@ struct rt_imxrt_eth
{
/* inherit from ethernet device */
struct eth_device parent;
enet_handle_t enet_handle;
ENET_Type *enet_base;
enet_data_error_stats_t error_statistic;
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
rt_bool_t tx_is_waiting;
struct rt_semaphore tx_wait;
};
@ -75,9 +76,9 @@ static struct rt_imxrt_eth imxrt_eth_device;
void _enet_rx_callback(struct rt_imxrt_eth * eth)
{
rt_err_t result;
ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt);
result = eth_device_ready(&(eth->parent));
if( result != RT_EOK )
rt_kprintf("RX err =%d\n", result );
@ -97,30 +98,30 @@ void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event,
switch(event)
{
case kENET_RxEvent:
_enet_rx_callback((struct rt_imxrt_eth *)userData);
break;
case kENET_TxEvent:
_enet_tx_callback((struct rt_imxrt_eth *)userData);
break;
case kENET_ErrEvent:
//rt_kprintf("kENET_ErrEvent\n");
break;
case kENET_WakeUpEvent:
//rt_kprintf("kENET_WakeUpEvent\n");
break;
case kENET_TimeStampEvent:
//rt_kprintf("kENET_TimeStampEvent\n");
break;
case kENET_TimeStampAvailEvent:
//rt_kprintf("kENET_TimeStampAvailEvent \n");
break;
default:
//rt_kprintf("unknow error\n");
break;
@ -314,21 +315,21 @@ static void _enet_io_init(void)
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
}
static void _enet_clk_init(void)
{
const clock_enet_pll_config_t config = {true, false, false, 1, 1};
CLOCK_InitEnetPll(&config);
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
}
static void _delay(void)
{
volatile int i = 1000000;
while (i--)
i = i;
}
@ -336,7 +337,7 @@ static void _delay(void)
static void _enet_phy_reset_by_gpio(void)
{
gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
GPIO_PinInit(GPIO1, 9, &gpio_config);
GPIO_PinInit(GPIO1, 10, &gpio_config);
/* pull up the ENET_INT before RESET. */
@ -354,7 +355,7 @@ static void _enet_config(void)
phy_speed_t speed;
phy_duplex_t duplex;
bool link = false;
/* prepare the buffer configuration. */
enet_buffer_config_t buffConfig = {
ENET_RXBD_NUM,
@ -366,7 +367,7 @@ static void _enet_config(void)
&g_rxDataBuff[0][0],
&g_txDataBuff[0][0],
};
/* Get default configuration. */
/*
* config.miiMode = kENET_RmiiMode;
@ -377,26 +378,36 @@ static void _enet_config(void)
ENET_GetDefaultConfig(&config);
config.interrupt = kENET_TxFrameInterrupt | kENET_RxFrameInterrupt;
//config.interrupt = 0xFFFFFFFF;
/* Set SMI to get PHY link status. */
sysClock = CLOCK_GetFreq(kCLOCK_AhbClk);
status = PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, sysClock);
while (status != kStatus_Success)
if (status == kStatus_Success)
{
ETH_PRINTF("\r\nPHY Auto-negotiation failed. Please check the cable connection and link partner setting.\r\n");
status = PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, sysClock);
PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &link);
if (link)
{
/* Get the actual PHY link speed. */
PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, PHY_ADDRESS, &speed, &duplex);
/* Change the MII speed and duplex for actual link status. */
config.miiSpeed = (enet_mii_speed_t)speed;
config.miiDuplex = (enet_mii_duplex_t)duplex;
}
dbg_log(DBG_LOG, "PHY Auto-negotiation success.\n");
eth_device_linkchange(&imxrt_eth_device.parent, RT_TRUE);
}
PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &link);
if (link)
else
{
/* Get the actual PHY link speed. */
PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, PHY_ADDRESS, &speed, &duplex);
/* Change the MII speed and duplex for actual link status. */
config.miiSpeed = (enet_mii_speed_t)speed;
config.miiDuplex = (enet_mii_duplex_t)duplex;
}
config.miiSpeed = kENET_MiiSpeed10M;
config.miiDuplex = kENET_MiiHalfDuplex;
dbg_log(DBG_WARNING, "PHY Auto-negotiation failed. Please check the cable connection and link partner setting.\n");
eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE);
}
ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock);
ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device);
ENET_ActiveRead(imxrt_eth_device.enet_base);
@ -408,7 +419,7 @@ static rt_err_t rt_imxrt_eth_init(rt_device_t dev)
_enet_io_init();
_enet_clk_init();
_enet_phy_reset_by_gpio();
_enet_config();
return RT_EOK;
@ -416,33 +427,33 @@ static rt_err_t rt_imxrt_eth_init(rt_device_t dev)
static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
ETH_PRINTF("rt_imxrt_eth_open...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_open...\n");
return RT_EOK;
}
static rt_err_t rt_imxrt_eth_close(rt_device_t dev)
{
ETH_PRINTF("rt_imxrt_eth_close...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_close...\n");
return RT_EOK;
}
static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
ETH_PRINTF("rt_imxrt_eth_read...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_read...\n");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_imxrt_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
ETH_PRINTF("rt_imxrt_eth_write...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_write...\n");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args)
{
ETH_PRINTF("rt_imxrt_eth_control...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_control...\n");
switch(cmd)
{
case NIOCTL_GADDR:
@ -468,7 +479,7 @@ rt_err_t rt_imxrt_eth_tx( rt_device_t dev, struct pbuf* p)
RT_ASSERT(p != NULL);
RT_ASSERT(enet_handle != RT_NULL);
ETH_PRINTF("rt_imxrt_eth_tx: %d\n", p->len);
dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len);
#ifdef ETH_TX_DUMP
{
@ -477,11 +488,11 @@ rt_err_t rt_imxrt_eth_tx( rt_device_t dev, struct pbuf* p)
buf = (uint8_t *)p->payload;
for (i = 0; i < p->len; i++)
{
ETH_PRINTF("%02X ", buf[i]);
dbg_log(DBG_LOG, "%02X ", buf[i]);
if (i % 16 == 15)
ETH_PRINTF("\n");
dbg_log(DBG_LOG, "\n");
}
ETH_PRINTF("\n");
dbg_log(DBG_LOG, "\n");
}
#endif
@ -504,12 +515,12 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
{
uint32_t length = 0;
status_t status;
struct pbuf* p = RT_NULL;
enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle;
ENET_Type *enet_base = imxrt_eth_device.enet_base;
enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic;
/* Get the Frame size */
status = ENET_GetRxFrameSize(enet_handle, &length);
@ -518,7 +529,7 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
{
/* Received valid frame. Deliver the rx buffer with the size equal to length. */
p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
if (p != NULL)
{
status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length);
@ -532,28 +543,28 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
buf = (uint8_t *)p->payload;
for (i = 0; i < p->len; i++)
{
ETH_PRINTF("%02X ", buf[i]);
dbg_log(DBG_LOG, "%02X ", buf[i]);
if (i % 16 == 15)
ETH_PRINTF("\n");
dbg_log(DBG_LOG, "\n");
}
ETH_PRINTF("\n");
dbg_log(DBG_LOG, "\n");
#endif
return p;
}
else
{
ETH_PRINTF(" A frame read failed\n");
dbg_log(DBG_LOG, " A frame read failed\n");
pbuf_free(p);
}
}
else
{
ETH_PRINTF(" pbuf_alloc faild\n");
dbg_log(DBG_LOG, " pbuf_alloc faild\n");
}
}
else if (status == kStatus_ENET_RxFrameError)
{
ETH_PRINTF("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
/* Update the received buffer when error happened. */
/* Get the error information of the received g_frame. */
ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic);
@ -577,7 +588,7 @@ static int rt_hw_imxrt_eth_init(void)
imxrt_eth_device.dev_addr[3] = 0x12;
imxrt_eth_device.dev_addr[4] = 0x34;
imxrt_eth_device.dev_addr[5] = 0x56;
imxrt_eth_device.enet_base = ENET;
imxrt_eth_device.parent.parent.init = rt_imxrt_eth_init;
@ -591,20 +602,20 @@ static int rt_hw_imxrt_eth_init(void)
imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx;
imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx;
ETH_PRINTF("sem init: tx_wait\r\n");
dbg_log(DBG_LOG, "sem init: tx_wait\r\n");
/* init tx semaphore */
rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO);
/* register eth device */
ETH_PRINTF("eth_device_init start\r\n");
dbg_log(DBG_LOG, "eth_device_init start\r\n");
state = eth_device_init(&(imxrt_eth_device.parent), "e0");
if (RT_EOK == state)
{
ETH_PRINTF("eth_device_init success\r\n");
dbg_log(DBG_LOG, "eth_device_init success\r\n");
}
else
{
ETH_PRINTF("eth_device_init faild: %d\r\n", state);
dbg_log(DBG_LOG, "eth_device_init faild: %d\r\n", state);
}
return state;
}
@ -618,7 +629,7 @@ void phy_read(uint32_t phyReg)
{
uint32_t data;
status_t status;
status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data);
if (kStatus_Success == status)
{
@ -633,7 +644,7 @@ void phy_read(uint32_t phyReg)
void phy_write(uint32_t phyReg, uint32_t data)
{
status_t status;
status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data);
if (kStatus_Success == status)
{
@ -649,7 +660,7 @@ void phy_dump(void)
{
uint32_t data;
status_t status;
int i;
for (i = 0; i < 32; i++)
{
@ -659,7 +670,7 @@ void phy_dump(void)
rt_kprintf("phy_dump: %02X --> faild", i);
break;
}
if (i % 8 == 7)
{
rt_kprintf("%02X --> %08X ", i, data);
@ -668,17 +679,17 @@ void phy_dump(void)
{
rt_kprintf("%02X --> %08X\n", i, data);
}
}
}
void enet_reg_dump(void)
{
ENET_Type *enet_base = imxrt_eth_device.enet_base;
#define DUMP_REG(__REG) \
rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG)
DUMP_REG(EIR);
DUMP_REG(EIMR);
DUMP_REG(RDAR);
@ -785,16 +796,16 @@ void enet_nvic_tog(void)
void enet_rx_stat(void)
{
enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic;
#define DUMP_STAT(__VAR) \
rt_kprintf("%-25s: %08X\n", #__VAR, error_statistic->__VAR);
DUMP_STAT(statsRxLenGreaterErr);
DUMP_STAT(statsRxAlignErr);
DUMP_STAT(statsRxFcsErr);
DUMP_STAT(statsRxOverRunErr);
DUMP_STAT(statsRxTruncateErr);
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
DUMP_STAT(statsRxProtocolChecksumErr);
DUMP_STAT(statsRxIpHeadChecksumErr);
@ -808,8 +819,8 @@ void enet_rx_stat(void)
DUMP_STAT(statsTxExcessCollisionErr);
DUMP_STAT(statsTxUnderFlowErr);
DUMP_STAT(statsTxTsErr);
#endif
#endif
}
void enet_buf_info(void)
@ -818,7 +829,7 @@ void enet_buf_info(void)
int i = 0;
for (i = 0; i < ENET_RXBD_NUM; i++)
{
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
i,
g_rxBuffDescrip[i].length,
g_rxBuffDescrip[i].control,
@ -827,7 +838,7 @@ void enet_buf_info(void)
for (i = 0; i < ENET_TXBD_NUM; i++)
{
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
i,
g_txBuffDescrip[i].length,
g_txBuffDescrip[i].control,

195
bsp/imxrt1052-evk/drivers/drv_sdram.c Normal file
View File

@ -0,0 +1,195 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2017-12-04 Tanek first implementation
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
static uint32_t _RDWORD(uint32_t address)
{
return *((uint32_t *)address);
}
static void _WDWORD(uint32_t address, uint32_t value)
{
*((uint32_t *)address) = value;
}
static void SDRAM_WaitIpCmdDone(void)
{
unsigned long reg;
do
{
reg = _RDWORD(0x402F003C);
}while((reg & 0x3) == 0);
}
static void _clock_init(void)
{
// Enable all clocks
_WDWORD(0x400FC068,0xffffffff);
_WDWORD(0x400FC06C,0xffffffff);
_WDWORD(0x400FC070,0xffffffff);
_WDWORD(0x400FC074,0xffffffff);
_WDWORD(0x400FC078,0xffffffff);
_WDWORD(0x400FC07C,0xffffffff);
_WDWORD(0x400FC080,0xffffffff);
_WDWORD(0x400D8030,0x00002001);
_WDWORD(0x400D8100,0x001d0000);
_WDWORD(0x400FC014,0x00010D40);
}
static void _sdr_Init(void)
{
// Config IOMUX
_WDWORD(0x401F8014, 0x00000000);
_WDWORD(0x401F8018, 0x00000000);
_WDWORD(0x401F801C, 0x00000000);
_WDWORD(0x401F8020, 0x00000000);
_WDWORD(0x401F8024, 0x00000000);
_WDWORD(0x401F8028, 0x00000000);
_WDWORD(0x401F802C, 0x00000000);
_WDWORD(0x401F8030, 0x00000000);
_WDWORD(0x401F8034, 0x00000000);
_WDWORD(0x401F8038, 0x00000000);
_WDWORD(0x401F803C, 0x00000000);
_WDWORD(0x401F8040, 0x00000000);
_WDWORD(0x401F8044, 0x00000000);
_WDWORD(0x401F8048, 0x00000000);
_WDWORD(0x401F804C, 0x00000000);
_WDWORD(0x401F8050, 0x00000000);
_WDWORD(0x401F8054, 0x00000000);
_WDWORD(0x401F8058, 0x00000000);
_WDWORD(0x401F805C, 0x00000000);
_WDWORD(0x401F8060, 0x00000000);
_WDWORD(0x401F8064, 0x00000000);
_WDWORD(0x401F8068, 0x00000000);
_WDWORD(0x401F806C, 0x00000000);
_WDWORD(0x401F8070, 0x00000000);
_WDWORD(0x401F8074, 0x00000000);
_WDWORD(0x401F8078, 0x00000000);
_WDWORD(0x401F807C, 0x00000000);
_WDWORD(0x401F8080, 0x00000000);
_WDWORD(0x401F8084, 0x00000000);
_WDWORD(0x401F8088, 0x00000000);
_WDWORD(0x401F808C, 0x00000000);
_WDWORD(0x401F8090, 0x00000000);
_WDWORD(0x401F8094, 0x00000000);
_WDWORD(0x401F8098, 0x00000000);
_WDWORD(0x401F809C, 0x00000000);
_WDWORD(0x401F80A0, 0x00000000);
_WDWORD(0x401F80A4, 0x00000000);
_WDWORD(0x401F80A8, 0x00000000);
_WDWORD(0x401F80AC, 0x00000000);
_WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION
_WDWORD(0x401F80B4, 0x00000000);
_WDWORD(0x401F80B8, 0x00000000);
// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
_WDWORD(0x401F8204, 0x000110F9);
_WDWORD(0x401F8208, 0x000110F9);
_WDWORD(0x401F820C, 0x000110F9);
_WDWORD(0x401F8210, 0x000110F9);
_WDWORD(0x401F8214, 0x000110F9);
_WDWORD(0x401F8218, 0x000110F9);
_WDWORD(0x401F821C, 0x000110F9);
_WDWORD(0x401F8220, 0x000110F9);
_WDWORD(0x401F8224, 0x000110F9);
_WDWORD(0x401F8228, 0x000110F9);
_WDWORD(0x401F822C, 0x000110F9);
_WDWORD(0x401F8230, 0x000110F9);
_WDWORD(0x401F8234, 0x000110F9);
_WDWORD(0x401F8238, 0x000110F9);
_WDWORD(0x401F823C, 0x000110F9);
_WDWORD(0x401F8240, 0x000110F9);
_WDWORD(0x401F8244, 0x000110F9);
_WDWORD(0x401F8248, 0x000110F9);
_WDWORD(0x401F824C, 0x000110F9);
_WDWORD(0x401F8250, 0x000110F9);
_WDWORD(0x401F8254, 0x000110F9);
_WDWORD(0x401F8258, 0x000110F9);
_WDWORD(0x401F825C, 0x000110F9);
_WDWORD(0x401F8260, 0x000110F9);
_WDWORD(0x401F8264, 0x000110F9);
_WDWORD(0x401F8268, 0x000110F9);
_WDWORD(0x401F826C, 0x000110F9);
_WDWORD(0x401F8270, 0x000110F9);
_WDWORD(0x401F8274, 0x000110F9);
_WDWORD(0x401F8278, 0x000110F9);
_WDWORD(0x401F827C, 0x000110F9);
_WDWORD(0x401F8280, 0x000110F9);
_WDWORD(0x401F8284, 0x000110F9);
_WDWORD(0x401F8288, 0x000110F9);
_WDWORD(0x401F828C, 0x000110F9);
_WDWORD(0x401F8290, 0x000110F9);
_WDWORD(0x401F8294, 0x000110F9);
_WDWORD(0x401F8298, 0x000110F9);
_WDWORD(0x401F829C, 0x000110F9);
_WDWORD(0x401F82A0, 0x000110F9);
_WDWORD(0x401F82A4, 0x000110F9);
_WDWORD(0x401F82A8, 0x000110F9);
// Config SDR Controller Registers/
_WDWORD(0x402F0000,0x10000004); // MCR
_WDWORD(0x402F0008,0x00030524); // BMCR0
_WDWORD(0x402F000C,0x06030524); // BMCR1
_WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
_WDWORD(0x402F0014,0x8200001B); // BR1, 32MB
_WDWORD(0x402F0018,0x8400001B); // BR2, 32MB
_WDWORD(0x402F001C,0x8600001B); // BR3, 32MB
_WDWORD(0x402F0020,0x90000021); // BR4,
_WDWORD(0x402F0024,0xA0000019); // BR5,
_WDWORD(0x402F0028,0xA8000017); // BR6,
_WDWORD(0x402F002C,0xA900001B); // BR7,
_WDWORD(0x402F0030,0x00000021); // BR8,
_WDWORD(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.
// _WDWORD(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
_WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
_WDWORD(0x402F0044,0x00652922); // SDRAMCR1
_WDWORD(0x402F0048,0x00010920); // SDRAMCR2
_WDWORD(0x402F004C,0x50210A08); // SDRAMCR3
_WDWORD(0x402F0080,0x00000021); // DBICR0
_WDWORD(0x402F0084,0x00888888); // DBICR1
_WDWORD(0x402F0094,0x00000002); // IPCR1
_WDWORD(0x402F0098,0x00000000); // IPCR2
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F00A0,0x00000033); // IPTXDAT
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.
}
int imxrt_sdram_init(void)
{
_clock_init();
_sdr_Init();
return 0;
}
/*@}*/

10
bsp/imxrt1052-evk/drivers/fsl_phy.c
View File

@ -29,12 +29,13 @@
*/
#include "fsl_phy.h"
#include <rtthread.h>
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
#define PHY_TIMEOUT_COUNT 0xFFFFU
/*******************************************************************************
* Prototypes
@ -83,14 +84,14 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
counter --;
}
if (!counter)
{
return kStatus_Fail;
}
/* Reset PHY. */
counter = PHY_TIMEOUT_COUNT;
counter = 6;
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
if (result == kStatus_Success)
{
@ -136,6 +137,9 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
break;
}
}
rt_kprintf("[PHY] wait autonegotiation complete...\n");
rt_thread_delay(RT_TICK_PER_SECOND);
if (!counter)
{

66
bsp/imxrt1052-evk/drivers/hyper_flash_boot.c Normal file
View File

@ -0,0 +1,66 @@
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-12-05 Tanek first version
*/
#include <rtthread.h>
// enter serial download mode, and run command:
// finsh /> mem_dump(0x60000000, 512)
#if defined (__ICCARM__ )
RT_USED static const uint32_t boot_data[] @(0x60000000u) =
#elif defined ( __GNUC__ )
RT_USED static const uint32_t boot_data[] __attribute__((section (".bootdata"))) =
#elif defined ( __CC_ARM )
RT_USED static const uint32_t boot_data[] __attribute__((at(0x60000000u))) =
#endif
{
0x42464346, 0x56010400, 0x00000000, 0x03030303, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000059, 0x01080800, 0x00000000, 0x00000000, 0x04000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000F, 0x0001000F,
0x8B1887A0, 0xA7048F10, 0x00000000, 0x00000000, 0x87008700, 0x87AA8700, 0x87058700, 0x87708700,
0x8B1887A0, 0xB70B8F10, 0x0000A704, 0x00000000, 0x87008700, 0x87AA8700, 0x87058700, 0x87AA8700,
0x87008700, 0x87558700, 0x87028700, 0x87558700, 0x87008700, 0x87AA8700, 0x87058700, 0x87808700,
0x87008700, 0x87AA8700, 0x87058700, 0x87AA8700, 0x87008700, 0x87558700, 0x87028700, 0x87558700,
0x8B188700, 0x87008F10, 0x00008730, 0x00000000, 0x87008700, 0x87AA8700, 0x87058700, 0x87A08700,
0x8B188700, 0xA3808F10, 0x00000000, 0x00000000, 0x87008700, 0x87AA8700, 0x87058700, 0x87808700,
0x87008700, 0x87AA8700, 0x87058700, 0x87AA8700, 0x87008700, 0x87558700, 0x87028700, 0x87558700,
0x87008700, 0x87AA8700, 0x87058700, 0x87108700, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000102, 0x00000302, 0x00000504, 0x00000902, 0x00000B04, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000200, 0x00040000, 0x00000008, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
// finsh /> mem_dump(0x60001000, 16)
#if defined (__ICCARM__ )
RT_USED static const uint32_t image_vector_table[] @(0x60001000u) =
#elif defined ( __GNUC__ )
RT_USED static const uint32_t image_vector_table[] __attribute__((section (".ivt"))) =
#elif defined ( __CC_ARM )
RT_USED static const uint32_t image_vector_table[] __attribute__((at(0x60001000u))) =
#endif
{
0x412000D1, 0x60002000, 0x00000000, 0x00000000, 0x60001020, 0x60001000, 0x00000000, 0x00000000,
0x60000000, 0x00800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};

25
bsp/imxrt1052-evk/drivers/usart.c
View File

@ -27,7 +27,7 @@
#error "Please define at least one UARTx"
#endif
#include <rtdevice.h>
/* imxrt uart driver */
@ -130,7 +130,7 @@ static const struct imxrt_uart uarts[] = {
"uart1",
},
#endif
};
/* Get debug console frequency. */
@ -210,9 +210,9 @@ static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_c
RT_ASSERT(cfg != RT_NULL);
uart = (struct imxrt_uart *)serial->parent.user_data;
imxrt_uart_gpio_init(uart);
LPUART_GetDefaultConfig(&config);
config.baudRate_Bps = cfg->baud_rate;
@ -249,13 +249,13 @@ static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_c
config.parityMode = kLPUART_ParityDisabled;
break;
}
config.enableTx = true;
config.enableRx = true;
LPUART_Init(uart->uart_base, &config, BOARD_DebugConsoleSrcFreq());
return RT_EOK;
}
@ -273,7 +273,7 @@ static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *ar
LPUART_DisableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
/* disable rx irq */
DisableIRQ(uart->irqn);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable interrupt */
@ -295,7 +295,7 @@ static int imxrt_putc(struct rt_serial_device *serial, char ch)
LPUART_WriteByte(uart->uart_base, ch);
while(!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
return 1;
}
@ -323,7 +323,7 @@ static void uart_isr(struct rt_serial_device *serial)
struct imxrt_uart *uart = (struct imxrt_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
/* enter interrupt */
rt_interrupt_enter();
@ -332,7 +332,7 @@ static void uart_isr(struct rt_serial_device *serial)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
/* leave interrupt */
rt_interrupt_leave();
}
@ -350,7 +350,6 @@ int imxrt_hw_usart_init(void)
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
int i;
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{
uarts[i].serial->ops = &imxrt_uart_ops;

259
bsp/imxrt1052-evk/imxrt1052_sdram.ld
View File

@ -1,259 +0,0 @@
/*
** ###################################################################
** Processors: MIMXRT1052CVL5A
** MIMXRT1052DVL6A
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
/* Specify the memory areas */
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x80000400
m_text (RX) : ORIGIN = 0x80000400, LENGTH = 0x8007FC00
m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01600000
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal RAM */
.interrupts :
{
__VECTOR_TABLE = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
__VECTOR_RAM = __VECTOR_TABLE;
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
/* The program code and other data goes into internal RAM */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(m_usb_dma_init_data)
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
.ncache.init : AT(__NDATA_ROM)
{
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_ncache
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_ncache
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(m_usb_dma_noninit_data)
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
.stack :
{
. = ALIGN(8);
. += STACK_SIZE;
} > m_data
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

58
bsp/imxrt1052-evk/project.ewd
View File

@ -11,7 +11,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>28</version>
<version>29</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -48,7 +48,7 @@
</option>
<option>
<name>RunToEnable</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>RunToName</name>
@ -76,7 +76,7 @@
</option>
<option>
<name>OCDownloadVerifyAll</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>OCProductVersion</name>
@ -84,15 +84,15 @@
</option>
<option>
<name>OCDynDriverList</name>
<state>ARMSIM_ID</state>
<state>JLINK_ID</state>
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>8.11.2.13604</state>
<state>8.20.1.14181</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>CLowLevel</name>
@ -112,7 +112,7 @@
</option>
<option>
<name>FlashLoadersV3</name>
<state>$TOOLKIT_DIR$\config\flashloader\</state>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1050_EVK_FlexSPI.board</state>
</option>
<option>
<name>OCImagesSuppressCheck1</name>
@ -210,6 +210,10 @@
<name>OCAttachSlave</name>
<state>0</state>
</option>
<option>
<name>MassEraseBeforeFlashing</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -288,7 +292,7 @@
<option>
<name>CMSISDAPResetList</name>
<version>1</version>
<state>10</state>
<state>4</state>
</option>
<option>
<name>CMSISDAPHWResetDuration</name>
@ -308,7 +312,7 @@
</option>
<option>
<name>CMSISDAPInterfaceRadio</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>CMSISDAPInterfaceCmdLine</name>
@ -373,31 +377,31 @@
</option>
<option>
<name>CatchMMERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchNOCPERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchCHKERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchSTATERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchBUSERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchINTERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchHARDERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchDummy</name>
@ -425,7 +429,7 @@
</option>
<option>
<name>CMSISDAPSelectedCPUBehaviour</name>
<state>0</state>
<state></state>
</option>
<option>
<name>ICpuName</name>
@ -721,7 +725,7 @@
<debug>1</debug>
<option>
<name>CCCatchSFERR</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>JLinkSpeed</name>
@ -822,12 +826,12 @@
</option>
<option>
<name>CCJLinkInterfaceRadio</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>CCJLinkResetList</name>
<version>6</version>
<state>5</state>
<state>8</state>
</option>
<option>
<name>CCJLinkInterfaceCmdLine</name>
@ -1402,6 +1406,10 @@
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
@ -1418,7 +1426,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>28</version>
<version>29</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1617,6 +1625,10 @@
<name>OCAttachSlave</name>
<state>0</state>
</option>
<option>
<name>MassEraseBeforeFlashing</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -2809,6 +2821,10 @@
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
<loadFlag>0</loadFlag>

219
bsp/imxrt1052-evk/project.ewp
View File

@ -171,7 +171,6 @@
<state>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</state>
<state>RT_USING_DLIBC</state>
<state>_DLIB_FILE_DESCRIPTOR</state>
<state>_DLIB_THREAD_SUPPORT</state>
</option>
<option>
<name>CCPreprocFile</name>
@ -301,31 +300,27 @@
<option>
<name>CCIncludePath2</name>
<state />
<state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
<state>$PROJ_DIR$\Libraries</state>
<state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\netif</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net</state>
<state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\Libraries\drivers</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
<state>$PROJ_DIR$\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net\socket</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src</state>
<state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include\netif</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
<state>$PROJ_DIR$\Libraries\utilities</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\Libraries</state>
<state>$PROJ_DIR$\applications</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net\select</state>
<state>$PROJ_DIR$\..\..\components\finsh</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include\ipv4</state>
<state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
<state>$PROJ_DIR$\..\..\components\libc\pthreads</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\arch\include</state>
<state>$PROJ_DIR$\..\..\components\finsh</state>
<state>$PROJ_DIR$\Libraries\drivers</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
</option>
<option>
<name>CCStdIncCheck</name>
@ -722,7 +717,7 @@
</option>
<option>
<name>IlinkIcfFile</name>
<state>$PROJ_DIR$\imxrt1052_sdram.icf</state>
<state>$PROJ_DIR$\Libraries\iar\MIMXRT1052xxxxx_flexspi_nor.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
@ -1245,31 +1240,27 @@
<option>
<name>CCIncludePath2</name>
<state />
<state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
<state>$PROJ_DIR$\Libraries</state>
<state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\netif</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net</state>
<state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\Libraries\drivers</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
<state>$PROJ_DIR$\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net\socket</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src</state>
<state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include\netif</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
<state>$PROJ_DIR$\Libraries\utilities</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\Libraries</state>
<state>$PROJ_DIR$\applications</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net\select</state>
<state>$PROJ_DIR$\..\..\components\finsh</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include\ipv4</state>
<state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
<state>$PROJ_DIR$\..\..\components\libc\pthreads</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\arch\include</state>
<state>$PROJ_DIR$\..\..\components\finsh</state>
<state>$PROJ_DIR$\Libraries\drivers</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
</option>
<option>
<name>CCStdIncCheck</name>
@ -1892,6 +1883,9 @@
<file>
<name>$PROJ_DIR$\applications\main.c</name>
</file>
<file>
<name>$PROJ_DIR$\applications\mem_dump.c</name>
</file>
<file>
<name>$PROJ_DIR$\applications\mem_test.c</name>
</file>
@ -1907,6 +1901,12 @@
<file>
<name>$PROJ_DIR$\drivers\usart.c</name>
</file>
<file>
<name>$PROJ_DIR$\drivers\hyper_flash_boot.c</name>
</file>
<file>
<name>$PROJ_DIR$\drivers\drv_sdram.c</name>
</file>
<file>
<name>$PROJ_DIR$\drivers\drv_eth.c</name>
</file>
@ -2127,7 +2127,7 @@
<name>$PROJ_DIR$\..\..\src\kservice.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\src\mem.c</name>
<name>$PROJ_DIR$\..\..\src\memheap.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\src\object.c</name>
@ -2177,12 +2177,6 @@
<file>
<name>$PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\src\poll.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\src\select.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs\devfs.c</name>
</file>
@ -2192,15 +2186,6 @@
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\net\dfs_net.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\net\net_netdb.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\net\net_sockets.c</name>
</file>
</group>
<group>
<name>DeviceDrivers</name>
@ -2329,153 +2314,111 @@
</file>
</group>
<group>
<name>pthreads</name>
<name>LwIP</name>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\clock_time.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\api_lib.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\mqueue.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\api_msg.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\pthread.c</name>
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</project>

2910
bsp/imxrt1052-evk/project.ewt
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File diff suppressed because it is too large Load Diff

366
bsp/imxrt1052-evk/project.uvprojx
View File

@ -10,13 +10,14 @@
<TargetName>RT-Thread IMXRT1052</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>MIMXRT1052:M7</Device>
<Vendor>NXP</Vendor>
<PackID>NXP.iMXRT_DFP.1.0.1</PackID>
<PackID>NXP.iMXRT_DFP.1.0.2</PackID>
<PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
<Cpu>IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -48,12 +49,12 @@
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>rtthread-lpc</OutputName>
<OutputName>rtthread-imxrt</OutputName>
<CreateExecutable>1</CreateExecutable>
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<HexFormatSelection>1</HexFormatSelection>
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@ -79,9 +80,9 @@
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
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<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg1Name>fromelf --bin !L --output rtthread-mdk.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
@ -332,10 +333,10 @@
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186</MiscControls>
<MiscControls>--library_interface=armcc --library_type=standardlib --diag_suppress=66</MiscControls>
<Define>SKIP_SYSCLK_INIT, CPU_MIMXRT1052DVL6A, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, EVK_MCIMXRM, FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE, RT_USING_ARM_LIBC</Define>
<Undefine></Undefine>
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<IncludePath>applications;.;drivers;Libraries;Libraries\drivers;Libraries\utilities;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m7;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-1.4.1\src;..\..\components\net\lwip-1.4.1\src\include;..\..\components\net\lwip-1.4.1\src\include\ipv4;..\..\components\net\lwip-1.4.1\src\arch\include;..\..\components\net\lwip-1.4.1\src\include\netif</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -366,10 +367,10 @@
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x10000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\imxrt1052_sdram.sct</ScatterFile>
<ScatterFile>.\Libraries\arm\MIMXRT1052xxxxx_flexspi_nor.scf</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc> --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) </Misc>
<Misc>--keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
@ -389,6 +390,11 @@
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@ -414,6 +420,16 @@
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@ -780,9 +796,9 @@
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<FileName>stats.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\stats.c</FilePath>
</File>
<File>
<FileName>sys.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\sys.c</FilePath>
</File>
<File>
<FileName>tcp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\tcp.c</FilePath>
</File>
<File>
<FileName>tcp_in.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\tcp_in.c</FilePath>
</File>
<File>
<FileName>tcp_out.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\tcp_out.c</FilePath>
</File>
<File>
<FileName>timeouts.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\timeouts.c</FilePath>
</File>
<File>
<FileName>udp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\udp.c</FilePath>
</File>
<File>
<FileName>ethernet.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\netif\ethernet.c</FilePath>
</File>
<File>
<FileName>ethernetif.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c</FilePath>
</File>
<File>
<FileName>lowpan6.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c</FilePath>
</File>
<File>
<FileName>autoip.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\def.c</FilePath>
</File>
<File>
<FileName>dhcp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\dhcp.c</FilePath>
</File>
<File>
<FileName>etharp.c</FileName>
<FileName>dns.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\dns.c</FilePath>
</File>
<File>
<FileName>init.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\init.c</FilePath>
</File>
<File>
<FileName>memp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\memp.c</FilePath>
</File>
<File>
<FileName>netif.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\netif.c</FilePath>
</File>
<File>
<FileName>pbuf.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\pbuf.c</FilePath>
</File>
<File>
<FileName>raw.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\raw.c</FilePath>
</File>
<File>
<FileName>stats.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\stats.c</FilePath>
</File>
<File>
<FileName>sys.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\sys.c</FilePath>
</File>
<File>
<FileName>tcp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\tcp.c</FilePath>
</File>
<File>
<FileName>tcp_in.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\tcp_in.c</FilePath>
</File>
<File>
<FileName>tcp_out.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\tcp_out.c</FilePath>
</File>
<File>
<FileName>timers.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\timers.c</FilePath>
</File>
<File>
<FileName>udp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\udp.c</FilePath>
</File>
<File>
<FileName>autoip.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\autoip.c</FilePath>
</File>
<File>
<FileName>icmp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\icmp.c</FilePath>
</File>
<File>
<FileName>igmp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\igmp.c</FilePath>
</File>
<File>
<FileName>ip4.c</FileName>
<FileName>inet.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\inet.c</FilePath>
</File>
<File>
<FileName>ip4_addr.c</FileName>
<FileName>inet_chksum.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\inet_chksum.c</FilePath>
</File>
<File>
<FileName>ip4_frag.c</FileName>
<FileName>ip.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\ip.c</FilePath>
</File>
<File>
<FileName>ip_addr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\ip_addr.c</FilePath>
</File>
<File>
<FileName>ip_frag.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\ip_frag.c</FilePath>
</File>
<File>
<FileName>etharp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\netif\etharp.c</FilePath>
</File>
<File>
<FileName>ethernetif.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\netif\ethernetif.c</FilePath>
</File>
<File>
<FileName>slipif.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\netif\slipif.c</FilePath>
</File>
</Files>
</Group>

92
bsp/imxrt1052-evk/rtconfig.h
View File

@ -8,12 +8,15 @@
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
/* RT_THREAD_PRIORITY_8 is not set */
#define RT_THREAD_PRIORITY_32
/* RT_THREAD_PRIORITY_256 is not set */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_DEBUG
#define RT_USING_OVERFLOW_CHECK
#define RT_DEBUG_INIT 1
/* RT_DEBUG_THREAD is not set */
#define RT_DEBUG_INIT 0
#define RT_DEBUG_THREAD 0
#define RT_USING_HOOK
#define IDLE_THREAD_STACK_SIZE 256
/* RT_USING_TIMER_SOFT is not set */
@ -30,14 +33,17 @@
/* Memory Management */
/* RT_USING_MEMPOOL is not set */
/* RT_USING_MEMHEAP is not set */
#define RT_USING_HEAP
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
/* RT_USING_NOHEAP is not set */
/* RT_USING_SMALL_MEM is not set */
/* RT_USING_SLAB is not set */
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
/* RT_USING_INTERRUPT_INFO is not set */
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
@ -63,16 +69,20 @@
#define FINSH_CMD_SIZE 80
/* FINSH_USING_AUTH is not set */
#define FINSH_USING_MSH
//#define FINSH_USING_MSH_DEFAULT
//#define FINSH_USING_MSH_ONLY
#define FINSH_USING_MSH_DEFAULT
/* FINSH_USING_MSH_ONLY is not set */
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_0
@ -86,7 +96,10 @@
/* RT_DFS_ELM_USE_ERASE is not set */
#define RT_DFS_ELM_REENTRANT
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_NET
/* RT_USING_DFS_NET is not set */
/* RT_USING_DFS_ROMFS is not set */
/* RT_USING_DFS_RAMFS is not set */
/* RT_USING_DFS_UFFS is not set */
/* RT_USING_DFS_NFS is not set */
/* Device Drivers */
@ -101,27 +114,27 @@
/* RT_USING_MTD_NAND is not set */
/* RT_USING_RTC is not set */
#define RT_USING_SDIO
//#define RT_MMCSD_DBG
/* RT_USING_SPI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_WIFI is not set */
/* Using USB */
/* RT_USING_USB_HOST is not set */
/* RT_USING_USB_DEVICE is not set */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
#define RT_USING_POSIX
/* RT_USING_POSIX_MMAP is not set */
/* RT_USING_POSIX_TERMIOS is not set */
/* RT_USING_PTHREADS is not set */
/* RT_USING_POSIX is not set */
/* Network stack */
/* light weight TCP/IP stack */
#define RT_USING_LWIP
#define RT_USING_LWIP202
//#define RT_LWIP_DEBUG
#define RT_USING_LWIP141
/* RT_USING_LWIP202 is not set */
/* RT_LWIP_IGMP is not set */
#define RT_LWIP_ICMP
@ -131,6 +144,12 @@
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* LWIP_USING_DHCPD is not set */
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
/* RT_LWIP_RAW is not set */
@ -156,18 +175,6 @@
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 10
#define RT_LWIP_IPADDR3 30
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 10
#define RT_LWIP_GWADDR3 1
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* Modbus master and slave stack */
@ -178,40 +185,59 @@
/* RT_USING_GUIENGINE is not set */
/* VBUS(Virtual Software BUS) */
/* RT_USING_VBUS is not set */
/* Utilities */
/* RT_USING_LOGTRACE is not set */
/* RT_USING_RYM is not set */
/* RT-Thread online packages */
/* system packages */
/* PKG_USING_PARTITION is not set */
/* PKG_USING_SQLITE is not set */
/* PKG_USING_RTI is not set */
/* IoT - internet of things */
/* PKG_USING_CJSON is not set */
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEB_TERMINAL is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* PKG_USING_CJSON is not set */
/* PKG_USING_EZXML is not set */
/* PKG_USING_NANOPB is not set */
/* security packages */
/* PKG_USING_MBEDTLS is not set */
/* PKG_USING_libsodium is not set */
/* language packages */
/* PKG_USING_JERRYSCRIPT is not set */
/* PKG_USING_MICROPYTHON is not set */
/* multimedia packages */
/* tools packages */
/* PKG_USING_CMBACKTRACE is not set */
/* PKG_USING_ELOG is not set */
/* PKG_USING_EASYLOGGER is not set */
/* PKG_USING_SYSTEMVIEW is not set */
/* miscellaneous packages */
/* PKG_USING_FASTLZ is not set */
/* PKG_USING_MINILZO is not set */
/* example package: hello */
/* PKG_USING_HELLO is not set */
/* BSP_SPECIAL CONFIG */
#define RT_USING_UART
#define RT_USING_UART1

10
bsp/imxrt1052-evk/rtconfig.py
View File

@ -41,16 +41,18 @@ if PLATFORM == 'gcc':
STRIP = PREFIX + 'strip'
DEVICE = ' -std=c99 -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -g -Wall -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_USED -eentry'
CFLAGS = DEVICE + ' -g -Wall -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_PRESENT -eentry'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=imxrt1052_sdram.map,-cref,-u,Reset_Handler -T imxrt1052_sdram.ld'
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=imxrt1052_sdram.map,-cref,-u,Reset_Handler -T ./Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld'
CPATH = ''
LPATH = ''
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0'
else:
CFLAGS += ' -O2 -Os'

2
bsp/imxrt1052-evk/template.ewp
View File

@ -690,7 +690,7 @@
</option>
<option>
<name>IlinkIcfFile</name>
<state>$PROJ_DIR$\imxrt1052_sdram.icf</state>
<state>$PROJ_DIR$\Libraries\iar\MIMXRT1052xxxxx_flexspi_nor.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>

13
bsp/imxrt1052-evk/template.uvprojx
View File

@ -16,7 +16,8 @@
<TargetCommonOption>
<Device>MIMXRT1052:M7</Device>
<Vendor>NXP</Vendor>
<PackID>NXP.iMXRT_DFP.1.0.1</PackID>
<PackID>NXP.iMXRT_DFP.1.0.2</PackID>
<PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
<Cpu>IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -48,12 +49,12 @@
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>rtthread-lpc</OutputName>
<OutputName>rtthread-imxrt</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\build\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
@ -79,9 +80,9 @@
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg1Name>fromelf --bin !L --output rtthread-mdk.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
@ -366,7 +367,7 @@
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x10000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\imxrt1052_sdram.sct</ScatterFile>
<ScatterFile>.\Libraries\arm\MIMXRT1052xxxxx_flexspi_nor.scf</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>