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This commit is contained in:
Meco Man 2021-03-21 02:55:53 +08:00
parent b21d59b3dc
commit 70b1c0e92f
19 changed files with 1954 additions and 1954 deletions
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182
bsp/stm32f20x/Drivers/24LCxx.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -16,171 +16,171 @@
#define EE24LC024H #define EE24LC024H
/* /*
Note: If eeprom size lager then EE_MEM_SIZE byte, you must define EE_ADDR_SIZE == I2C_MEM_2Bytes Note: If eeprom size lager then EE_MEM_SIZE byte, you must define EE_ADDR_SIZE == I2C_MEM_2Bytes
*/ */
#ifdef EE24LC024H #ifdef EE24LC024H
#define EE_ADDR_SIZE I2C_MEM_1Byte #define EE_ADDR_SIZE I2C_MEM_1Byte
#define EE_MEM_SIZE 256 #define EE_MEM_SIZE 256
#define EE_PageSize 16 #define EE_PageSize 16
#endif #endif
static struct rt_device ee_dev; static struct rt_device ee_dev;
uint32_t EE_ReadBuffer(void *pBuffer, rt_off_t ReadAddr, rt_size_t NumByteToRead) uint32_t EE_ReadBuffer(void *pBuffer, rt_off_t ReadAddr, rt_size_t NumByteToRead)
{ {
return I2C_IORW(I2C1, (uint8_t *)pBuffer, (uint16_t)NumByteToRead, (uint16_t)ReadAddr, EE_Address | 0x01, I2C_MEM_1Byte ); return I2C_IORW(I2C1, (uint8_t *)pBuffer, (uint16_t)NumByteToRead, (uint16_t)ReadAddr, EE_Address | 0x01, I2C_MEM_1Byte );
} }
uint32_t EE_WritePage(void *pBuffer, uint16_t WriteAddr) uint32_t EE_WritePage(void *pBuffer, uint16_t WriteAddr)
{ {
I2C_IORW(I2C1, (uint8_t *)pBuffer, EE_PageSize , WriteAddr, EE_Address , EE_ADDR_SIZE ); I2C_IORW(I2C1, (uint8_t *)pBuffer, EE_PageSize , WriteAddr, EE_Address , EE_ADDR_SIZE );
/*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error ) /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error )
rt_kprintf("EE ACK failed\n");*/ rt_kprintf("EE ACK failed\n");*/
rt_thread_delay(50); rt_thread_delay(50);
return 0; return 0;
} }
uint32_t EE_WriteByte(void *pBuffer, uint16_t WriteAddr) uint32_t EE_WriteByte(void *pBuffer, uint16_t WriteAddr)
{ {
I2C_IORW(I2C1, (uint8_t *)pBuffer, 1 , WriteAddr, EE_Address, EE_ADDR_SIZE ); I2C_IORW(I2C1, (uint8_t *)pBuffer, 1 , WriteAddr, EE_Address, EE_ADDR_SIZE );
/*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error ) /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error )
rt_kprintf("EE ACK failed\n");*/ rt_kprintf("EE ACK failed\n");*/
rt_thread_delay(50); rt_thread_delay(50);
return 0; return 0;
} }
Status EE_WriteBuffer(const void *pBuffer, rt_off_t WriteAddr, rt_size_t NumByteToWrite) Status EE_WriteBuffer(const void *pBuffer, rt_off_t WriteAddr, rt_size_t NumByteToWrite)
{ {
uint8_t NumOfPage = 0, NumOfSingle = 0; uint8_t NumOfPage = 0, NumOfSingle = 0;
uint16_t Addr = 0,count = 0; uint16_t Addr = 0,count = 0;
uint8_t *ptr = (uint8_t *)pBuffer; uint8_t *ptr = (uint8_t *)pBuffer;
Addr = (uint16_t)(WriteAddr&0xFFFF); Addr = (uint16_t)(WriteAddr&0xFFFF);
count = (uint16_t)(NumByteToWrite&0xFFFF); count = (uint16_t)(NumByteToWrite&0xFFFF);
if ((WriteAddr + NumByteToWrite) > EE_MEM_SIZE) if ((WriteAddr + NumByteToWrite) > EE_MEM_SIZE)
return Error; return Error;
while (count >= EE_PageSize) while (count >= EE_PageSize)
{ {
EE_WritePage(ptr, Addr); EE_WritePage(ptr, Addr);
Addr += EE_PageSize; Addr += EE_PageSize;
count -= EE_PageSize; count -= EE_PageSize;
ptr += EE_PageSize; ptr += EE_PageSize;
} }
while (count) while (count)
{ {
EE_WriteByte(ptr++, Addr++); EE_WriteByte(ptr++, Addr++);
count--; count--;
} }
return Success; return Success;
} }
static rt_err_t ee24LCxx_init(rt_device_t dev) static rt_err_t ee24LCxx_init(rt_device_t dev)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_size_t ee24LCxx_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size) static rt_size_t ee24LCxx_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size)
{ {
if (EE_ReadBuffer(buf, pos, size) == Success) if (EE_ReadBuffer(buf, pos, size) == Success)
return size; return size;
else else
return -1; return -1;
} }
static rt_size_t ee24LCxx_write(rt_device_t dev, rt_off_t pos, const void *buf, rt_size_t size) static rt_size_t ee24LCxx_write(rt_device_t dev, rt_off_t pos, const void *buf, rt_size_t size)
{ {
if (EE_WriteBuffer(buf, pos, size) == Success) if (EE_WriteBuffer(buf, pos, size) == Success)
return size; return size;
else else
return -1; return -1;
} }
static rt_err_t ee24LCxx_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t ee24LCxx_open(rt_device_t dev, rt_uint16_t oflag)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_err_t ee24LCxx_close(rt_device_t dev) static rt_err_t ee24LCxx_close(rt_device_t dev)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_err_t ee24LCxx_control(rt_device_t dev, int cmd, void *args) static rt_err_t ee24LCxx_control(rt_device_t dev, int cmd, void *args)
{ {
return RT_EOK; return RT_EOK;
} }
void ee24LCxx_hw_init(void) void ee24LCxx_hw_init(void)
{ {
uint32_t delay, i; uint32_t delay, i;
I2C1_INIT(); I2C1_INIT();
for (i =0; i < 4; i++) for (i =0; i < 4; i++)
{ {
delay = 0xFFFFF; delay = 0xFFFFF;
while (delay--); while (delay--);
} }
ee_dev.init = ee24LCxx_init; ee_dev.init = ee24LCxx_init;
ee_dev.open = ee24LCxx_open; ee_dev.open = ee24LCxx_open;
ee_dev.close = ee24LCxx_close; ee_dev.close = ee24LCxx_close;
ee_dev.read = ee24LCxx_read; ee_dev.read = ee24LCxx_read;
ee_dev.write = ee24LCxx_write; ee_dev.write = ee24LCxx_write;
ee_dev.control = ee24LCxx_control; ee_dev.control = ee24LCxx_control;
ee_dev.type = RT_Device_Class_Unknown; ee_dev.type = RT_Device_Class_Unknown;
rt_device_register(&ee_dev, "eeprom", RT_DEVICE_FLAG_RDWR); rt_device_register(&ee_dev, "eeprom", RT_DEVICE_FLAG_RDWR);
} }
void dump_ee(void) void dump_ee(void)
{ {
rt_device_t dev; rt_device_t dev;
char buf[EE_MEM_SIZE]; char buf[EE_MEM_SIZE];
int i, j; int i, j;
dev = rt_device_find("eeprom"); dev = rt_device_find("eeprom");
rt_device_read(dev, 0, buf, EE_MEM_SIZE ); rt_device_read(dev, 0, buf, EE_MEM_SIZE );
for (i = 0; i < 16; i++) for (i = 0; i < 16; i++)
{ {
for (j = 0; j < 16; j++) for (j = 0; j < 16; j++)
{ {
rt_kprintf("0x%02X ", buf[ i*16+ j]); rt_kprintf("0x%02X ", buf[ i*16+ j]);
} }
rt_kprintf("\n"); rt_kprintf("\n");
} }
} }
void ee_reset(void) void ee_reset(void)
{ {
char buf[EE_MEM_SIZE], read[EE_MEM_SIZE]; char buf[EE_MEM_SIZE], read[EE_MEM_SIZE];
int i; int i;
rt_device_t dev = rt_device_find("eeprom"); rt_device_t dev = rt_device_find("eeprom");
for (i = 0; i < EE_MEM_SIZE; i++) for (i = 0; i < EE_MEM_SIZE; i++)
{ {
buf[i] = 0xFF; buf[i] = 0xFF;
read[i] = 0; read[i] = 0;
} }
if (rt_device_write(dev, 0, buf, EE_MEM_SIZE ) == EE_MEM_SIZE) if (rt_device_write(dev, 0, buf, EE_MEM_SIZE ) == EE_MEM_SIZE)
rt_kprintf("Write Success\n"); rt_kprintf("Write Success\n");
rt_device_read(dev, 0, read, EE_MEM_SIZE ); rt_device_read(dev, 0, read, EE_MEM_SIZE );
for (i = 0; i < EE_MEM_SIZE; i++) for (i = 0; i < EE_MEM_SIZE; i++)
{ {
if (buf[i] != read[i]) if (buf[i] != read[i])
rt_kprintf("EE Failed %X != %X at %d\n", buf[i], read[i], i); rt_kprintf("EE Failed %X != %X at %d\n", buf[i], read[i], i);
} }
} }
#ifdef RT_USING_FINSH #ifdef RT_USING_FINSH

212
bsp/stm32f20x/Drivers/FM25Lx.c
View File

@ -26,7 +26,7 @@ void rt_hw_spi2_baud_rate(uint16_t SPI_BaudRatePrescaler)
/* FM25L256 using SPI2 */ /* FM25L256 using SPI2 */
void fm25_spi_cfg() void fm25_spi_cfg()
{ {
GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitTypeDef GPIO_InitStructure;
SPI_InitTypeDef SPI_InitStructure; SPI_InitTypeDef SPI_InitStructure;
/* Enable SPI Periph clock */ /* Enable SPI Periph clock */
@ -36,24 +36,24 @@ void fm25_spi_cfg()
//Setup GPIO //Setup GPIO
GPIO_InitStructure.GPIO_Pin = FM25_SPI_SCK | FM25_SPI_MISO | FM25_SPI_MOSI; GPIO_InitStructure.GPIO_Pin = FM25_SPI_SCK | FM25_SPI_MISO | FM25_SPI_MOSI;
/*Connect Pin to AF*/ /*Connect Pin to AF*/
GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource3, GPIO_AF_SPI3); GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource3, GPIO_AF_SPI3);
GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource4, GPIO_AF_SPI3); GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource4, GPIO_AF_SPI3);
GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource5, GPIO_AF_SPI3); GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource5, GPIO_AF_SPI3);
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(FM25_SPI_GPIO, &GPIO_InitStructure); GPIO_Init(FM25_SPI_GPIO, &GPIO_InitStructure);
/* CS pin: PB12 */ /* CS pin: PB12 */
GPIO_InitStructure.GPIO_Pin = FM25_SPI_NSS_PIN; GPIO_InitStructure.GPIO_Pin = FM25_SPI_NSS_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(FM25_SPI_NSS_GPIO, &GPIO_InitStructure); GPIO_Init(FM25_SPI_NSS_GPIO, &GPIO_InitStructure);
CS_HIGH(); CS_HIGH();
SPI_Cmd(FM25_SPI, DISABLE); SPI_Cmd(FM25_SPI, DISABLE);
/*------------------------ SPI configuration ------------------------*/ /*------------------------ SPI configuration ------------------------*/
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx; SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master; SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
@ -72,23 +72,23 @@ void fm25_spi_cfg()
SPI_Cmd(FM25_SPI, ENABLE); SPI_Cmd(FM25_SPI, ENABLE);
//SPI_CalculateCRC(FM25_SPI, DISABLE); //SPI_CalculateCRC(FM25_SPI, DISABLE);
fram_lock = rt_sem_create("framlock", 1, RT_IPC_FLAG_FIFO); fram_lock = rt_sem_create("framlock", 1, RT_IPC_FLAG_FIFO);
} }
static uint8_t spi_readwrite(uint8_t data) static uint8_t spi_readwrite(uint8_t data)
{ {
int32_t timeout = 0xFFFFF; int32_t timeout = 0xFFFFF;
//rt_kprintf("State 0x%X\n", SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE)); //rt_kprintf("State 0x%X\n", SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE));
//Wait until the transmit buffer is empty //Wait until the transmit buffer is empty
while (SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE) == RESET && --timeout >0); while (SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE) == RESET && --timeout >0);
if( timeout <= 0 ){ spi_timeout_cnt++; return 0;} if( timeout <= 0 ){ spi_timeout_cnt++; return 0;}
// Send the byte // Send the byte
SPI_I2S_SendData(FM25_SPI, data); SPI_I2S_SendData(FM25_SPI, data);
timeout = 0xFFFFF; timeout = 0xFFFFF;
//Wait until a data is received //Wait until a data is received
while (SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_RXNE) == RESET && --timeout >0); while (SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_RXNE) == RESET && --timeout >0);
if( timeout <= 0 ){ spi_timeout_cnt++; return 0;} if( timeout <= 0 ){ spi_timeout_cnt++; return 0;}
// Get the received data // Get the received data
data = SPI_I2S_ReceiveData(FM25_SPI); data = SPI_I2S_ReceiveData(FM25_SPI);
@ -110,29 +110,29 @@ rt_size_t fm25_read(rt_device_t dev, rt_off_t offset, void * buf, rt_size_t size
{ {
uint32_t index; uint32_t index;
uint8_t *buffer = (uint8_t*) buf; uint8_t *buffer = (uint8_t*) buf;
fram_lock(); fram_lock();
//spi_config(); //spi_config();
//rt_kprintf("READ: %d, size=%d\n", offset, size); //rt_kprintf("READ: %d, size=%d\n", offset, size);
CS_LOW(); CS_LOW();
spi_readwrite( FM25_READ); spi_readwrite( FM25_READ);
spi_readwrite( (offset >> 8)&0xFF ); spi_readwrite( (offset >> 8)&0xFF );
spi_readwrite( offset & 0xFF ); spi_readwrite( offset & 0xFF );
for(index=0; index<size; index++) for(index=0; index<size; index++)
{ {
*buffer++ = spi_readwrite(0xFF); *buffer++ = spi_readwrite(0xFF);
if( spi_timeout_cnt > 0 ) if( spi_timeout_cnt > 0 )
{ {
fram_unlock(); fram_unlock();
spi_timeout_cnt = 0; spi_timeout_cnt = 0;
rt_kprintf("Read time out\n"); rt_kprintf("Read time out\n");
return -1; return -1;
} }
offset++; offset++;
} }
CS_HIGH(); CS_HIGH();
@ -145,33 +145,33 @@ rt_size_t fm25_write(rt_device_t dev, rt_off_t offset, const void * buf, rt_size
{ {
uint32_t index = size; uint32_t index = size;
uint8_t *buffer = (uint8_t*) buf; uint8_t *buffer = (uint8_t*) buf;
fram_lock(); fram_lock();
//spi_config(); //spi_config();
//rt_kprintf("WRITE: %d, size=%d\n", offset, size); //rt_kprintf("WRITE: %d, size=%d\n", offset, size);
CS_LOW(); CS_LOW();
spi_readwrite( FM25_WREN ); spi_readwrite( FM25_WREN );
CS_HIGH();
CS_LOW();
spi_readwrite( FM25_WRITE);
spi_readwrite( (offset >> 8)&0xFF );
spi_readwrite( offset & 0xFF );
while( index > 0 )
{
spi_readwrite( *buffer++ );
if( spi_timeout_cnt > 0 )
{
fram_unlock();
rt_kprintf("Write time out\n");
spi_timeout_cnt = 0;
return -1;
}
index--;
offset++;
}
CS_HIGH(); CS_HIGH();
//rt_thread_delay(100); CS_LOW();
spi_readwrite( FM25_WRITE);
spi_readwrite( (offset >> 8)&0xFF );
spi_readwrite( offset & 0xFF );
while( index > 0 )
{
spi_readwrite( *buffer++ );
if( spi_timeout_cnt > 0 )
{
fram_unlock();
rt_kprintf("Write time out\n");
spi_timeout_cnt = 0;
return -1;
}
index--;
offset++;
}
CS_HIGH();
//rt_thread_delay(100);
fram_unlock(); fram_unlock();
@ -179,36 +179,36 @@ rt_size_t fm25_write(rt_device_t dev, rt_off_t offset, const void * buf, rt_size
} }
static rt_err_t fm25_init(rt_device_t dev) static rt_err_t fm25_init(rt_device_t dev)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_err_t fm25_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t fm25_open(rt_device_t dev, rt_uint16_t oflag)
{ {
char i; char i;
SPI_Cmd(FM25_SPI, ENABLE); SPI_Cmd(FM25_SPI, ENABLE);
if( oflag != RT_DEVICE_FLAG_RDONLY ) if( oflag != RT_DEVICE_FLAG_RDONLY )
{ {
CS_LOW(); CS_LOW();
spi_readwrite( FM25_WRSR ); spi_readwrite( FM25_WRSR );
spi_readwrite( FM25_WPEN ); spi_readwrite( FM25_WPEN );
CS_HIGH(); CS_HIGH();
//rt_kprintf("RDSR=0x%X\n", fm25_read_status()); //rt_kprintf("RDSR=0x%X\n", fm25_read_status());
} }
return RT_EOK; return RT_EOK;
} }
static rt_err_t fm25_close(rt_device_t dev) static rt_err_t fm25_close(rt_device_t dev)
{ {
CS_LOW(); CS_LOW();
spi_readwrite( FM25_WRDI ); spi_readwrite( FM25_WRDI );
CS_HIGH(); CS_HIGH();
SPI_Cmd(FM25_SPI, DISABLE); SPI_Cmd(FM25_SPI, DISABLE);
return RT_EOK; return RT_EOK;
} }
static rt_err_t fm25_control(rt_device_t dev, int cmd, void *args) static rt_err_t fm25_control(rt_device_t dev, int cmd, void *args)
{ {
RT_ASSERT(dev != RT_NULL); RT_ASSERT(dev != RT_NULL);
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{ {
@ -219,30 +219,30 @@ static rt_err_t fm25_control(rt_device_t dev, int cmd, void *args)
geometry->bytes_per_sector = 1; geometry->bytes_per_sector = 1;
geometry->block_size = 1; geometry->block_size = 1;
geometry->sector_count = 8192; geometry->sector_count = 8192;
} }
return RT_EOK; return RT_EOK;
} }
static struct rt_device spi_flash_device; static struct rt_device spi_flash_device;
void fm25_hw_init() void fm25_hw_init()
{ {
int i = 0xFFFFF; int i = 0xFFFFF;
fm25_spi_cfg(); fm25_spi_cfg();
while(i--); while(i--);
//spi_config(); //spi_config();
CS_LOW(); CS_LOW();
spi_readwrite( FM25_WRDI ); spi_readwrite( FM25_WRDI );
CS_HIGH(); CS_HIGH();
spi_flash_device.type = RT_Device_Class_Block; spi_flash_device.type = RT_Device_Class_Block;
spi_flash_device.init = fm25_init; spi_flash_device.init = fm25_init;
spi_flash_device.open = fm25_open; spi_flash_device.open = fm25_open;
spi_flash_device.close = fm25_close; spi_flash_device.close = fm25_close;
spi_flash_device.read = fm25_read; spi_flash_device.read = fm25_read;
spi_flash_device.write = fm25_write; spi_flash_device.write = fm25_write;
spi_flash_device.control = fm25_control; spi_flash_device.control = fm25_control;
/* no private */ /* no private */
@ -255,17 +255,17 @@ void fm25_hw_init()
int fram_test(int x) int fram_test(int x)
{ {
//rt_kprintf("SR=0x%X\nCR1=0x%X\nCR2=0x%X\n", FM25_SPI->SR, FM25_SPI->CR1,FM25_SPI->CR2); //rt_kprintf("SR=0x%X\nCR1=0x%X\nCR2=0x%X\n", FM25_SPI->SR, FM25_SPI->CR1,FM25_SPI->CR2);
rt_device_t device = RT_NULL; rt_device_t device = RT_NULL;
char buf[256]; char buf[256];
char read[256]; char read[256];
int i, j; int i, j;
for(i =0; i< 256; i++ ) for(i =0; i< 256; i++ )
{ {
buf[i] = i; buf[i] = i;
read[i] = 0; read[i] = 0;
} }
// step 1:find device // step 1:find device
device = rt_device_find("fram0"); device = rt_device_find("fram0");
if( device == RT_NULL) if( device == RT_NULL)
@ -273,22 +273,22 @@ int fram_test(int x)
rt_kprintf("device %s: not found!\r\n"); rt_kprintf("device %s: not found!\r\n");
return RT_ERROR; return RT_ERROR;
} }
device->open(device,RT_DEVICE_FLAG_RDWR); device->open(device,RT_DEVICE_FLAG_RDWR);
for( j = 0; j < FM25_MAXSIZE; j+= 256 ) for( j = 0; j < FM25_MAXSIZE; j+= 256 )
//j = 256*x; //j = 256*x;
{ {
//rt_kprintf("RDSR=0x%X\n", fm25_read_status()); //rt_kprintf("RDSR=0x%X\n", fm25_read_status());
device->write(device,j, buf,256); device->write(device,j, buf,256);
device->read(device,j, read,256); device->read(device,j, read,256);
for(i =0; i< 256; i++ ) for(i =0; i< 256; i++ )
{ {
if( buf[i] != read[i] ) if( buf[i] != read[i] )
rt_kprintf("error at %d: %d!=%d\n", i, buf[i], read[i]); rt_kprintf("error at %d: %d!=%d\n", i, buf[i], read[i]);
} }
} }
device->close(device); device->close(device);
rt_kprintf("Finsh test\n"); rt_kprintf("Finsh test\n");
} }
#ifdef RT_USING_FINSH #ifdef RT_USING_FINSH
#include <finsh.h> #include <finsh.h>

50
bsp/stm32f20x/Drivers/FM25Lx.h
View File

@ -1,14 +1,14 @@
#ifndef FM25LX_H #ifndef FM25LX_H
#define FM25LX_H #define FM25LX_H
#define FM25_WREN 0x06 #define FM25_WREN 0x06
#define FM25_WRDI 0x04 #define FM25_WRDI 0x04
#define FM25_RDSR 0x05 #define FM25_RDSR 0x05
#define FM25_WRSR 0x01 #define FM25_WRSR 0x01
#define FM25_READ 0x03 #define FM25_READ 0x03
#define FM25_WRITE 0x02 #define FM25_WRITE 0x02
#define FM25_WEL 0x02 #define FM25_WEL 0x02
#define FM25_WPEN 0x80 #define FM25_WPEN 0x80
#define FM25CL64B #define FM25CL64B
//#define FM25LC256 //#define FM25LC256
@ -19,25 +19,25 @@
#define FM25_MAXSIZE 32768 #define FM25_MAXSIZE 32768
#endif #endif
#define FM25_SPI SPI3 #define FM25_SPI SPI3
#define FM25_SPI_GPIO GPIOB #define FM25_SPI_GPIO GPIOB
#define FM25_SPI_MOSI GPIO_Pin_5 #define FM25_SPI_MOSI GPIO_Pin_5
#define FM25_SPI_MISO GPIO_Pin_4 #define FM25_SPI_MISO GPIO_Pin_4
#define FM25_SPI_SCK GPIO_Pin_3 #define FM25_SPI_SCK GPIO_Pin_3
#define FM25_SPI_NSS_GPIO GPIOD #define FM25_SPI_NSS_GPIO GPIOD
#define FM25_SPI_NSS_PIN GPIO_Pin_10 #define FM25_SPI_NSS_PIN GPIO_Pin_10
#define FM25_SPI_CLK RCC_APB1Periph_SPI3 #define FM25_SPI_CLK RCC_APB1Periph_SPI3
#define FM25_SPI_GPIO_CLK RCC_AHB1Periph_GPIOB #define FM25_SPI_GPIO_CLK RCC_AHB1Periph_GPIOB
#define FM25_SPI_NSS_GPIO_CLK RCC_AHB1Periph_GPIOD #define FM25_SPI_NSS_GPIO_CLK RCC_AHB1Periph_GPIOD
#define FM25_SPI_DMA_CLK RCC_AHB1Periph_DMA1 #define FM25_SPI_DMA_CLK RCC_AHB1Periph_DMA1
#define FM25_SPI_DMA_Channel DMA_Channel_0 #define FM25_SPI_DMA_Channel DMA_Channel_0
#define FM25_SPI_RX_DMA_Stream DMA1_Stream0 #define FM25_SPI_RX_DMA_Stream DMA1_Stream0
#define FM25_SPI_RX_DMA_IRQ DMA1_Stream0_IRQn #define FM25_SPI_RX_DMA_IRQ DMA1_Stream0_IRQn
#define FM25_SPI_RX_DMA_FLAG DMA_IT_TCIF0 #define FM25_SPI_RX_DMA_FLAG DMA_IT_TCIF0
#define FM25_SPI_TX_DMA_Stream DMA1_Stream5 #define FM25_SPI_TX_DMA_Stream DMA1_Stream5
#define FM25_SPI_TX_DMA_IRQ DMA1_Stream5_IRQn #define FM25_SPI_TX_DMA_IRQ DMA1_Stream5_IRQn
#define FM25_SPI_TX_DMA_FLAG DMA_IT_TCIF5 #define FM25_SPI_TX_DMA_FLAG DMA_IT_TCIF5
#define FM25_SPI_DR_Base 0x4003C00C #define FM25_SPI_DR_Base 0x4003C00C
#endif #endif

44
bsp/stm32f20x/Drivers/board.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -219,11 +219,11 @@ uint32_t SD_DMAEndOfTransferStatus(void)
void NVIC_Configuration(void) void NVIC_Configuration(void)
{ {
#ifdef VECT_TAB_RAM #ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x20000000 */ /* Set the Vector Table base location at 0x20000000 */
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else /* VECT_TAB_FLASH */ #else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x08000000 */ /* Set the Vector Table base location at 0x08000000 */
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif #endif
} }
@ -236,15 +236,15 @@ void NVIC_Configuration(void)
*******************************************************************************/ *******************************************************************************/
void SysTick_Configuration(void) void SysTick_Configuration(void)
{ {
RCC_ClocksTypeDef rcc_clocks; RCC_ClocksTypeDef rcc_clocks;
rt_uint32_t cnts; rt_uint32_t cnts;
RCC_GetClocksFreq(&rcc_clocks); RCC_GetClocksFreq(&rcc_clocks);
cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND; cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
SysTick_Config(cnts); SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
} }
/** /**
@ -253,13 +253,13 @@ void SysTick_Configuration(void)
*/ */
void SysTick_Handler(void) void SysTick_Handler(void)
{ {
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
rt_tick_increase(); rt_tick_increase();
/* leave interrupt */ /* leave interrupt */
rt_interrupt_leave(); rt_interrupt_leave();
} }
/** /**
@ -267,15 +267,15 @@ void SysTick_Handler(void)
*/ */
void rt_hw_board_init() void rt_hw_board_init()
{ {
/* NVIC Configuration */ /* NVIC Configuration */
NVIC_Configuration(); NVIC_Configuration();
/* Configure the SysTick */ /* Configure the SysTick */
SysTick_Configuration(); SysTick_Configuration();
rt_hw_usart_init(); rt_hw_usart_init();
#ifdef RT_USING_CONSOLE #ifdef RT_USING_CONSOLE
rt_console_set_device(CONSOLE_DEVICE); rt_console_set_device(CONSOLE_DEVICE);
#endif #endif
} }

26
bsp/stm32f20x/Drivers/board.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -16,32 +16,32 @@
/* board configuration */ /* board configuration */
// <o> SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card // <o> SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card
// <i>Default: 1 // <i>Default: 1
#define STM32_USE_SDIO 1 #define STM32_USE_SDIO 1
/* whether use board external SRAM memory */ /* whether use board external SRAM memory */
// <e>Use external SRAM memory on the board // <e>Use external SRAM memory on the board
// <i>Enable External SRAM memory // <i>Enable External SRAM memory
#define STM32_EXT_SRAM 0 #define STM32_EXT_SRAM 0
// <o>Begin Address of External SRAM // <o>Begin Address of External SRAM
// <i>Default: 0x68000000 // <i>Default: 0x68000000
#define STM32_EXT_SRAM_BEGIN 0x68000000 /* the begining address of external SRAM */ #define STM32_EXT_SRAM_BEGIN 0x68000000 /* the begining address of external SRAM */
// <o>End Address of External SRAM // <o>End Address of External SRAM
// <i>Default: 0x68080000 // <i>Default: 0x68080000
#define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */ #define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */
// </e> // </e>
// <o> Internal SRAM memory size[Kbytes] <8-128> // <o> Internal SRAM memory size[Kbytes] <8-128>
// <i>Default: 64 // <i>Default: 64
#define STM32_SRAM_SIZE 128 #define STM32_SRAM_SIZE 128
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3 // <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
// <i>Default: 1 // <i>Default: 1
#define STM32_CONSOLE_USART 1 #define STM32_CONSOLE_USART 1
// <o> Ethernet Interface: <0=> Microchip ENC28J60 // <o> Ethernet Interface: <0=> Microchip ENC28J60
#define STM32_ETH_IF 0 #define STM32_ETH_IF 0
void rt_hw_board_led_on(int n); void rt_hw_board_led_on(int n);
void rt_hw_board_led_off(int n); void rt_hw_board_led_off(int n);
@ -78,7 +78,7 @@ void rt_hw_board_init(void);
#define SD_SDIO_DMA DMA2 #define SD_SDIO_DMA DMA2
#define SD_SDIO_DMA_CLK RCC_AHB1Periph_DMA2 #define SD_SDIO_DMA_CLK RCC_AHB1Periph_DMA2
#define SD_SDIO_DMA_STREAM3 3 #define SD_SDIO_DMA_STREAM3 3
//#define SD_SDIO_DMA_STREAM6 6 //#define SD_SDIO_DMA_STREAM6 6
#ifdef SD_SDIO_DMA_STREAM3 #ifdef SD_SDIO_DMA_STREAM3

170
bsp/stm32f20x/Drivers/drv_rtc.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -43,20 +43,20 @@ static struct rt_device rtc;
static time_t rt_mktime(struct tm *tm) static time_t rt_mktime(struct tm *tm)
{ {
long res; long res;
int year; int year;
year = tm->tm_year - 70; year = tm->tm_year - 70;
res = YEAR * year + DAY * ((year + 1) / 4); res = YEAR * year + DAY * ((year + 1) / 4);
res += month[tm->tm_mon]; res += month[tm->tm_mon];
if (tm->tm_mon > 1 && ((year + 2) % 4)) if (tm->tm_mon > 1 && ((year + 2) % 4))
res -= DAY; res -= DAY;
res += DAY * (tm->tm_mday - 1); res += DAY * (tm->tm_mday - 1);
res += HOUR * tm->tm_hour; res += HOUR * tm->tm_hour;
res += MINUTE * tm->tm_min; res += MINUTE * tm->tm_min;
res += tm->tm_sec; res += tm->tm_sec;
return res; return res;
} }
static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag)
{ {
@ -76,7 +76,7 @@ static rt_size_t rt_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_siz
static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
{ {
time_t *time; time_t *time;
struct tm ti,*to; struct tm ti,*to;
RT_ASSERT(dev != RT_NULL); RT_ASSERT(dev != RT_NULL);
switch (cmd) switch (cmd)
@ -84,17 +84,17 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
case RT_DEVICE_CTRL_RTC_GET_TIME: case RT_DEVICE_CTRL_RTC_GET_TIME:
time = (time_t *)args; time = (time_t *)args;
/* read device */ /* read device */
//RTC_GetTimeStamp(RTC_Format_BIN, &RTC_TimeStructure, &RTC_DateStructure); //RTC_GetTimeStamp(RTC_Format_BIN, &RTC_TimeStructure, &RTC_DateStructure);
RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure); RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure);
RTC_GetDate(RTC_Format_BIN, &RTC_DateStructure); RTC_GetDate(RTC_Format_BIN, &RTC_DateStructure);
ti.tm_sec = RTC_TimeStructure.RTC_Seconds; ti.tm_sec = RTC_TimeStructure.RTC_Seconds;
ti.tm_min = RTC_TimeStructure.RTC_Minutes; ti.tm_min = RTC_TimeStructure.RTC_Minutes;
ti.tm_hour = RTC_TimeStructure.RTC_Hours; ti.tm_hour = RTC_TimeStructure.RTC_Hours;
//ti.tm_wday = (RTC_DateStructure.RTC_WeekDay==7)?0:RTC_DateStructure.RTC_WeekDay; //ti.tm_wday = (RTC_DateStructure.RTC_WeekDay==7)?0:RTC_DateStructure.RTC_WeekDay;
ti.tm_mon = RTC_DateStructure.RTC_Month -1; ti.tm_mon = RTC_DateStructure.RTC_Month -1;
ti.tm_mday = RTC_DateStructure.RTC_Date; ti.tm_mday = RTC_DateStructure.RTC_Date;
ti.tm_year = RTC_DateStructure.RTC_Year + 70; ti.tm_year = RTC_DateStructure.RTC_Year + 70;
*time = rt_mktime(&ti); *time = rt_mktime(&ti);
//*time = RTC_GetCounter(); //*time = RTC_GetCounter();
break; break;
@ -104,10 +104,10 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
time = (time_t *)args; time = (time_t *)args;
/* Enable the PWR clock */ /* Enable the PWR clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
/* Allow access to RTC */ /* Allow access to RTC */
PWR_BackupAccessCmd(ENABLE); PWR_BackupAccessCmd(ENABLE);
/* Wait until last write operation on RTC registers has finished */ /* Wait until last write operation on RTC registers has finished */
//RTC_WaitForLastTask(); //RTC_WaitForLastTask();
@ -115,22 +115,22 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
/* Change the current time */ /* Change the current time */
//RTC_SetCounter(*time); //RTC_SetCounter(*time);
to = gmtime(time); to = gmtime(time);
RTC_TimeStructure.RTC_Seconds = to->tm_sec; RTC_TimeStructure.RTC_Seconds = to->tm_sec;
RTC_TimeStructure.RTC_Minutes = to->tm_min; RTC_TimeStructure.RTC_Minutes = to->tm_min;
RTC_TimeStructure.RTC_Hours = to->tm_hour; RTC_TimeStructure.RTC_Hours = to->tm_hour;
//RTC_DateStructure.RTC_WeekDay =(ti->tm_wday==0)?7:ti->tm_wday; //RTC_DateStructure.RTC_WeekDay =(ti->tm_wday==0)?7:ti->tm_wday;
RTC_DateStructure.RTC_Month = to->tm_mon + 1; RTC_DateStructure.RTC_Month = to->tm_mon + 1;
RTC_DateStructure.RTC_Date = to->tm_mday; RTC_DateStructure.RTC_Date = to->tm_mday;
RTC_DateStructure.RTC_Year = to->tm_year - 70; RTC_DateStructure.RTC_Year = to->tm_year - 70;
RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure); RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure);
RTC_SetDate(RTC_Format_BIN, &RTC_DateStructure); RTC_SetDate(RTC_Format_BIN, &RTC_DateStructure);
/* Wait until last write operation on RTC registers has finished */ /* Wait until last write operation on RTC registers has finished */
//RTC_WaitForLastTask(); //RTC_WaitForLastTask();
RTC_WriteBackupRegister(RTC_BKP_DR1, 0xA5A5); RTC_WriteBackupRegister(RTC_BKP_DR1, 0xA5A5);
//BKP_WriteBackupRegister(BKP_DR1, 0xA5A5); //BKP_WriteBackupRegister(BKP_DR1, 0xA5A5);
} }
break; break;
} }
@ -147,75 +147,75 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
*******************************************************************************/ *******************************************************************************/
int RTC_Config(void) int RTC_Config(void)
{ {
u32 count=0x200000; u32 count=0x200000;
/* Enable the PWR clock */ /* Enable the PWR clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
/* Allow access to RTC */ /* Allow access to RTC */
PWR_BackupAccessCmd(ENABLE); PWR_BackupAccessCmd(ENABLE);
RCC_LSEConfig(RCC_LSE_ON); RCC_LSEConfig(RCC_LSE_ON);
/* Wait till LSE is ready */ /* Wait till LSE is ready */
while ( (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--count) ); while ( (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--count) );
if ( count == 0 ) if ( count == 0 )
{ {
return -1; return -1;
} }
/* Select the RTC Clock Source */ /* Select the RTC Clock Source */
RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
SynchPrediv = 0xFF; SynchPrediv = 0xFF;
AsynchPrediv = 0x7F; AsynchPrediv = 0x7F;
/* Enable the RTC Clock */ /* Enable the RTC Clock */
RCC_RTCCLKCmd(ENABLE); RCC_RTCCLKCmd(ENABLE);
/* Wait for RTC APB registers synchronisation */ /* Wait for RTC APB registers synchronisation */
RTC_WaitForSynchro(); RTC_WaitForSynchro();
/* Enable The TimeStamp */ /* Enable The TimeStamp */
//RTC_TimeStampCmd(RTC_TimeStampEdge_Falling, ENABLE); //RTC_TimeStampCmd(RTC_TimeStampEdge_Falling, ENABLE);
return 0; return 0;
} }
int RTC_Configuration(void) int RTC_Configuration(void)
{ {
if(RTC_Config() < 0 ) if(RTC_Config() < 0 )
return -1; return -1;
/* Set the Time */ /* Set the Time */
RTC_TimeStructure.RTC_Hours = 0; RTC_TimeStructure.RTC_Hours = 0;
RTC_TimeStructure.RTC_Minutes = 0; RTC_TimeStructure.RTC_Minutes = 0;
RTC_TimeStructure.RTC_Seconds = 0; RTC_TimeStructure.RTC_Seconds = 0;
/* Set the Date */ /* Set the Date */
RTC_DateStructure.RTC_Month = 1; RTC_DateStructure.RTC_Month = 1;
RTC_DateStructure.RTC_Date = 1; RTC_DateStructure.RTC_Date = 1;
RTC_DateStructure.RTC_Year = 0; RTC_DateStructure.RTC_Year = 0;
RTC_DateStructure.RTC_WeekDay = 4; RTC_DateStructure.RTC_WeekDay = 4;
/* Calendar Configuration */ /* Calendar Configuration */
RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv; RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv;
RTC_InitStructure.RTC_SynchPrediv = SynchPrediv; RTC_InitStructure.RTC_SynchPrediv = SynchPrediv;
RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24;
RTC_Init(&RTC_InitStructure); RTC_Init(&RTC_InitStructure);
/* Set Current Time and Date */ /* Set Current Time and Date */
RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure); RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure);
RTC_SetDate(RTC_Format_BCD, &RTC_DateStructure); RTC_SetDate(RTC_Format_BCD, &RTC_DateStructure);
if (RTC_Init(&RTC_InitStructure) == ERROR) if (RTC_Init(&RTC_InitStructure) == ERROR)
return -1; return -1;
return 0; return 0;
} }
void rt_hw_rtc_init(void) void rt_hw_rtc_init(void)
{ {
rtc.type = RT_Device_Class_RTC; rtc.type = RT_Device_Class_RTC;
if (RTC_ReadBackupRegister(RTC_BKP_DR1) != 0xA5A5) if (RTC_ReadBackupRegister(RTC_BKP_DR1) != 0xA5A5)
{ {
@ -234,11 +234,11 @@ void rt_hw_rtc_init(void)
} }
/* register rtc device */ /* register rtc device */
rtc.init = RT_NULL; rtc.init = RT_NULL;
rtc.open = rt_rtc_open; rtc.open = rt_rtc_open;
rtc.close = RT_NULL; rtc.close = RT_NULL;
rtc.read = rt_rtc_read; rtc.read = rt_rtc_read;
rtc.write = RT_NULL; rtc.write = RT_NULL;
rtc.control = rt_rtc_control; rtc.control = rt_rtc_control;
/* no private */ /* no private */

2
bsp/stm32f20x/Drivers/drv_rtc.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

886
bsp/stm32f20x/Drivers/i2c.c
View File

File diff suppressed because it is too large Load Diff

32
bsp/stm32f20x/Drivers/i2c.h
View File

@ -5,17 +5,17 @@
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
#define SR1_AF_Set ((uint16_t)0x0400) #define SR1_AF_Set ((uint16_t)0x0400)
#define SR1_ARLO_Set ((uint16_t)0x0200) #define SR1_ARLO_Set ((uint16_t)0x0200)
#define SR1_BERR_Set ((uint16_t)0x0100) #define SR1_BERR_Set ((uint16_t)0x0100)
#define SR1_ADDR_Set ((uint16_t)0x0002) #define SR1_ADDR_Set ((uint16_t)0x0002)
#define SR1_SB_Set ((uint16_t)0x0001) #define SR1_SB_Set ((uint16_t)0x0001)
#define SR2_BUSY ((uint16_t)0x0002) #define SR2_BUSY ((uint16_t)0x0002)
#define SR2_MSL ((uint16_t)0x0001) #define SR2_MSL ((uint16_t)0x0001)
#define CR1_SWRST_Set ((uint16_t)0x8000) #define CR1_SWRST_Set ((uint16_t)0x8000)
/* I2C SPE mask */ /* I2C SPE mask */
#define CR1_PE_Set ((uint16_t)0x0001) #define CR1_PE_Set ((uint16_t)0x0001)
#define CR1_PE_Reset ((uint16_t)0xFFFE) #define CR1_PE_Reset ((uint16_t)0xFFFE)
@ -97,12 +97,12 @@
#define I2C1_DMA_CHANNEL_TX DMA1_Stream6 #define I2C1_DMA_CHANNEL_TX DMA1_Stream6
#define I2C1_DMA_CHANNEL_RX DMA1_Stream0 #define I2C1_DMA_CHANNEL_RX DMA1_Stream0
#define I2C1_DMA_TX_IRQn DMA1_Stream6_IRQn #define I2C1_DMA_TX_IRQn DMA1_Stream6_IRQn
#define I2C1_DMA_RX_IRQn DMA1_Stream0_IRQn #define I2C1_DMA_RX_IRQn DMA1_Stream0_IRQn
#define I2C2_DMA_CHANNEL_TX DMA1_Stream2 #define I2C2_DMA_CHANNEL_TX DMA1_Stream2
#define I2C2_DMA_CHANNEL_RX DMA1_Stream7 #define I2C2_DMA_CHANNEL_RX DMA1_Stream7
#define I2C2_DMA_TX_IRQn DMA1_Stream2_IRQn #define I2C2_DMA_TX_IRQn DMA1_Stream2_IRQn
#define I2C2_DMA_RX_IRQn DMA1_Stream7_IRQn #define I2C2_DMA_RX_IRQn DMA1_Stream7_IRQn
#define I2C1_DR_Address 0x40005410 #define I2C1_DR_Address 0x40005410
@ -112,20 +112,20 @@
#define I2C1_SCL_PIN GPIO_Pin_6 #define I2C1_SCL_PIN GPIO_Pin_6
#define I2C1_SDA_SOURCE GPIO_PinSource7 #define I2C1_SDA_SOURCE GPIO_PinSource7
#define I2C1_SCL_SOURCE GPIO_PinSource6 #define I2C1_SCL_SOURCE GPIO_PinSource6
#define I2C1_GPIO_PORT GPIOB #define I2C1_GPIO_PORT GPIOB
#define I2C1_GPIO_CLK RCC_AHB1Periph_GPIOB #define I2C1_GPIO_CLK RCC_AHB1Periph_GPIOB
#define I2C1_CLK RCC_APB1Periph_I2C1 #define I2C1_CLK RCC_APB1Periph_I2C1
#define I2C2_SDA_PIN GPIO_Pin_11 #define I2C2_SDA_PIN GPIO_Pin_11
#define I2C2_SCL_PIN GPIO_Pin_10 #define I2C2_SCL_PIN GPIO_Pin_10
#define I2C2_SDA_SOURCE GPIO_PinSource11 #define I2C2_SDA_SOURCE GPIO_PinSource11
#define I2C2_SCL_SOURCE GPIO_PinSource10 #define I2C2_SCL_SOURCE GPIO_PinSource10
#define I2C2_GPIO_PORT GPIOB #define I2C2_GPIO_PORT GPIOB
#define I2C2_GPIO_CLK RCC_AHB1Periph_GPIOB #define I2C2_GPIO_CLK RCC_AHB1Periph_GPIOB
#define I2C2_CLK RCC_APB1Periph_I2C1 #define I2C2_CLK RCC_APB1Periph_I2C1
#define I2C_MEM_1Byte 1 #define I2C_MEM_1Byte 1
#define I2C_MEM_2Bytes 2 #define I2C_MEM_2Bytes 2
typedef enum typedef enum
{ {

246
bsp/stm32f20x/Drivers/sdio_sd.c
View File

@ -484,7 +484,7 @@ uint8_t SD_Detect(void)
/*if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET) /*if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET)
{ {
status = SD_NOT_PRESENT; status = SD_NOT_PRESENT;
} */ } */
return status; return status;
} }
@ -2506,7 +2506,7 @@ uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes)
#include <dfs_fs.h> #include <dfs_fs.h>
/* set sector size to 512 */ /* set sector size to 512 */
#define SECTOR_SIZE 512 #define SECTOR_SIZE 512
static struct rt_device sdcard_device; static struct rt_device sdcard_device;
//static SD_CardInfo SDCardInfo; //static SD_CardInfo SDCardInfo;
@ -2516,44 +2516,44 @@ static rt_uint8_t _sdcard_buffer[SECTOR_SIZE];
/* RT-Thread Device Driver Interface */ /* RT-Thread Device Driver Interface */
static rt_err_t rt_sdcard_init(rt_device_t dev) static rt_err_t rt_sdcard_init(rt_device_t dev)
{ {
/* NVIC_InitTypeDef NVIC_InitStructure; /* NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure); */ NVIC_Init(&NVIC_InitStructure); */
if (rt_sem_init(&sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK) if (rt_sem_init(&sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
{ {
rt_kprintf("init sd lock semaphore failed\n"); rt_kprintf("init sd lock semaphore failed\n");
} }
else else
rt_kprintf("SD Card init OK\n"); rt_kprintf("SD Card init OK\n");
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_sdcard_close(rt_device_t dev) static rt_err_t rt_sdcard_close(rt_device_t dev)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{ {
SD_Error status; SD_Error status;
rt_uint32_t retry; rt_uint32_t retry;
rt_uint32_t factor; rt_uint32_t factor;
if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1; if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1;
else factor = SECTOR_SIZE; else factor = SECTOR_SIZE;
//rt_kprintf("sd: read 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer ,pos, size); //rt_kprintf("sd: read 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer ,pos, size);
rt_sem_take(&sd_lock, RT_WAITING_FOREVER); rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
retry = 3; retry = 3;
while(retry) while(retry)
@ -2571,8 +2571,8 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_
(uint8_t*)_sdcard_buffer, SECTOR_SIZE); (uint8_t*)_sdcard_buffer, SECTOR_SIZE);
status = SD_WaitReadOperation(); status = SD_WaitReadOperation();
while(SD_GetStatus() != SD_TRANSFER_OK); while(SD_GetStatus() != SD_TRANSFER_OK);
if (status != SD_OK) break; if (status != SD_OK) break;
/* copy to the buffer */ /* copy to the buffer */
rt_memcpy(((rt_uint8_t*)buffer + index * SECTOR_SIZE), _sdcard_buffer, SECTOR_SIZE); rt_memcpy(((rt_uint8_t*)buffer + index * SECTOR_SIZE), _sdcard_buffer, SECTOR_SIZE);
@ -2590,49 +2590,49 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_
status = SD_ReadMultiBlocks((part.offset + pos) * factor, status = SD_ReadMultiBlocks((part.offset + pos) * factor,
(uint8_t*)buffer, SECTOR_SIZE, size); (uint8_t*)buffer, SECTOR_SIZE, size);
} }
status = SD_WaitReadOperation(); status = SD_WaitReadOperation();
while(SD_GetStatus() != SD_TRANSFER_OK); while(SD_GetStatus() != SD_TRANSFER_OK);
/*rt_kprintf("===DUMP SECTOR %d===\n",pos); /*rt_kprintf("===DUMP SECTOR %d===\n",pos);
{ {
int i, j; int i, j;
char* tmp = (char*)buffer; char* tmp = (char*)buffer;
for(i =0; i < 32;i++) for(i =0; i < 32;i++)
{ {
rt_kprintf("%2d: ",i); rt_kprintf("%2d: ",i);
for(j= 0; j < 16;j++) for(j= 0; j < 16;j++)
rt_kprintf("%02X ",tmp[i*16+j]); rt_kprintf("%02X ",tmp[i*16+j]);
rt_kprintf("\n"); rt_kprintf("\n");
} }
} */ } */
} }
if (status == SD_OK) break; if (status == SD_OK) break;
retry --; retry --;
} }
rt_sem_release(&sd_lock); rt_sem_release(&sd_lock);
if (status == SD_OK) return size; if (status == SD_OK) return size;
rt_kprintf("read failed: %d, buffer 0x%08x\n", status, buffer); rt_kprintf("read failed: %d, buffer 0x%08x\n", status, buffer);
return 0; return 0;
} }
static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{ {
SD_Error status; SD_Error status;
rt_uint32_t factor; rt_uint32_t factor;
if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1; if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1;
else factor = SECTOR_SIZE; else factor = SECTOR_SIZE;
//rt_kprintf("sd: write 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer , pos, size); //rt_kprintf("sd: write 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer , pos, size);
rt_sem_take(&sd_lock, RT_WAITING_FOREVER); rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
/* read all sectors */ /* read all sectors */
if (((rt_uint32_t)buffer % 4 != 0) || if (((rt_uint32_t)buffer % 4 != 0) ||
((rt_uint32_t)buffer > 0x20080000)) ((rt_uint32_t)buffer > 0x20080000))
{ {
rt_uint32_t index; rt_uint32_t index;
/* which is not alignment with 4 or not chip SRAM */ /* which is not alignment with 4 or not chip SRAM */
for (index = 0; index < size; index ++) for (index = 0; index < size; index ++)
@ -2643,14 +2643,14 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
status = SD_WriteBlock((part.offset + index + pos) * factor, status = SD_WriteBlock((part.offset + index + pos) * factor,
(uint8_t*)_sdcard_buffer, SECTOR_SIZE); (uint8_t*)_sdcard_buffer, SECTOR_SIZE);
status = SD_WaitWriteOperation(); status = SD_WaitWriteOperation();
while(SD_GetStatus() != SD_TRANSFER_OK); while(SD_GetStatus() != SD_TRANSFER_OK);
if (status != SD_OK) break; if (status != SD_OK) break;
} }
} }
else else
{ {
if (size == 1) if (size == 1)
{ {
status = SD_WriteBlock((part.offset + pos) * factor, status = SD_WriteBlock((part.offset + pos) * factor,
@ -2662,15 +2662,15 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
(uint8_t*)buffer, SECTOR_SIZE, size); (uint8_t*)buffer, SECTOR_SIZE, size);
} }
status = SD_WaitWriteOperation(); status = SD_WaitWriteOperation();
while(SD_GetStatus() != SD_TRANSFER_OK); while(SD_GetStatus() != SD_TRANSFER_OK);
} }
rt_sem_release(&sd_lock); rt_sem_release(&sd_lock);
if (status == SD_OK) return size; if (status == SD_OK) return size;
rt_kprintf("write failed: %d, buffer 0x%08x\n", status, buffer); rt_kprintf("write failed: %d, buffer 0x%08x\n", status, buffer);
return 0; return 0;
} }
static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
@ -2686,89 +2686,89 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
geometry->bytes_per_sector = 512; geometry->bytes_per_sector = 512;
geometry->block_size = SDCardInfo.CardBlockSize; geometry->block_size = SDCardInfo.CardBlockSize;
if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
geometry->sector_count = (SDCardInfo.SD_csd.DeviceSize + 1) * 1024; geometry->sector_count = (SDCardInfo.SD_csd.DeviceSize + 1) * 1024;
else else
geometry->sector_count = SDCardInfo.CardCapacity/SDCardInfo.CardBlockSize; geometry->sector_count = SDCardInfo.CardCapacity/SDCardInfo.CardBlockSize;
} }
return RT_EOK; return RT_EOK;
} }
void rt_hw_sdcard_init() void rt_hw_sdcard_init()
{ {
NVIC_InitTypeDef NVIC_InitStructure; NVIC_InitTypeDef NVIC_InitStructure;
if (SD_Init() == SD_OK) if (SD_Init() == SD_OK)
{ {
SD_Error status; SD_Error status;
rt_uint8_t *sector; rt_uint8_t *sector;
/*status = SD_GetCardInfo(&SDCardInfo); /*status = SD_GetCardInfo(&SDCardInfo);
if (status != SD_OK) goto __return; if (status != SD_OK) goto __return;
status = SD_SelectDeselect((u32) (SDCardInfo.RCA << 16)); status = SD_SelectDeselect((u32) (SDCardInfo.RCA << 16));
if (status != SD_OK) goto __return; if (status != SD_OK) goto __return;
SD_EnableWideBusOperation(SDIO_BusWide_4b); SD_EnableWideBusOperation(SDIO_BusWide_4b);
SD_SetDeviceMode(SD_DMA_MODE); */ SD_SetDeviceMode(SD_DMA_MODE); */
// SDIO Interrupt ENABLE // SDIO Interrupt ENABLE
NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure); NVIC_Init(&NVIC_InitStructure);
/* get the first sector to read partition table */ /* get the first sector to read partition table */
sector = (rt_uint8_t*) rt_malloc (512); sector = (rt_uint8_t*) rt_malloc (512);
if (sector == RT_NULL) if (sector == RT_NULL)
{ {
rt_kprintf("allocate partition sector buffer failed\n"); rt_kprintf("allocate partition sector buffer failed\n");
return; return;
} }
status = SD_ReadBlock(0, (uint8_t*)sector, 512); status = SD_ReadBlock(0, (uint8_t*)sector, 512);
status = SD_WaitReadOperation(); status = SD_WaitReadOperation();
while(SD_GetStatus() != SD_TRANSFER_OK); while(SD_GetStatus() != SD_TRANSFER_OK);
if (status == SD_OK) if (status == SD_OK)
{ {
/* get the first partition */ /* get the first partition */
if (dfs_filesystem_get_partition(&part, sector, 0) != 0) if (dfs_filesystem_get_partition(&part, sector, 0) != 0)
{ {
/* there is no partition */ /* there is no partition */
part.offset = 0; part.offset = 0;
part.size = 0; part.size = 0;
} }
} }
else else
{ {
/* there is no partition table */ /* there is no partition table */
part.offset = 0; part.offset = 0;
part.size = 0; part.size = 0;
} }
/* release sector buffer */ /* release sector buffer */
rt_free(sector); rt_free(sector);
/* register sdcard device */ /* register sdcard device */
sdcard_device.type = RT_Device_Class_Block; sdcard_device.type = RT_Device_Class_Block;
sdcard_device.init = rt_sdcard_init; sdcard_device.init = rt_sdcard_init;
sdcard_device.open = rt_sdcard_open; sdcard_device.open = rt_sdcard_open;
sdcard_device.close = rt_sdcard_close; sdcard_device.close = rt_sdcard_close;
sdcard_device.read = rt_sdcard_read; sdcard_device.read = rt_sdcard_read;
sdcard_device.write = rt_sdcard_write; sdcard_device.write = rt_sdcard_write;
sdcard_device.control = rt_sdcard_control; sdcard_device.control = rt_sdcard_control;
/* no private */ /* no private */
sdcard_device.user_data = &SDCardInfo; sdcard_device.user_data = &SDCardInfo;
rt_device_register(&sdcard_device, "sd0", rt_device_register(&sdcard_device, "sd0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
return; return;
} }
__return: __return:
rt_kprintf("sdcard init failed\n"); rt_kprintf("sdcard init failed\n");
} }

566
bsp/stm32f20x/Drivers/serial.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -16,7 +16,7 @@
#include <stm32f2xx_usart.h> #include <stm32f2xx_usart.h>
static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel, static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
rt_uint32_t address, rt_uint32_t size); rt_uint32_t address, rt_uint32_t size);
/** /**
* @addtogroup STM32 * @addtogroup STM32
@ -26,252 +26,252 @@ static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
/* RT-Thread Device Interface */ /* RT-Thread Device Interface */
static rt_err_t rt_serial_init (rt_device_t dev) static rt_err_t rt_serial_init (rt_device_t dev)
{ {
struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data; struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data;
if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
{ {
if (dev->flag & RT_DEVICE_FLAG_INT_RX) if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{ {
rt_memset(uart->int_rx->rx_buffer, 0, rt_memset(uart->int_rx->rx_buffer, 0,
sizeof(uart->int_rx->rx_buffer)); sizeof(uart->int_rx->rx_buffer));
uart->int_rx->read_index = 0; uart->int_rx->read_index = 0;
uart->int_rx->save_index = 0; uart->int_rx->save_index = 0;
} }
if (dev->flag & RT_DEVICE_FLAG_DMA_TX) if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{ {
RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL); RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL);
uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL; uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
/* init data node memory pool */ /* init data node memory pool */
rt_mp_init(&(uart->dma_tx->data_node_mp), "dn", rt_mp_init(&(uart->dma_tx->data_node_mp), "dn",
uart->dma_tx->data_node_mem_pool, uart->dma_tx->data_node_mem_pool,
sizeof(uart->dma_tx->data_node_mem_pool), sizeof(uart->dma_tx->data_node_mem_pool),
sizeof(struct stm32_serial_data_node)); sizeof(struct stm32_serial_data_node));
} }
/* Enable USART */ /* Enable USART */
USART_Cmd(uart->uart_device, ENABLE); USART_Cmd(uart->uart_device, ENABLE);
dev->flag |= RT_DEVICE_FLAG_ACTIVATED; dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
} }
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_serial_close(rt_device_t dev) static rt_err_t rt_serial_close(rt_device_t dev)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{ {
rt_uint8_t* ptr; rt_uint8_t* ptr;
rt_err_t err_code; rt_err_t err_code;
struct stm32_serial_device* uart; struct stm32_serial_device* uart;
ptr = buffer; ptr = buffer;
err_code = RT_EOK; err_code = RT_EOK;
uart = (struct stm32_serial_device*)dev->user_data; uart = (struct stm32_serial_device*)dev->user_data;
if (dev->flag & RT_DEVICE_FLAG_INT_RX) if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{ {
/* interrupt mode Rx */ /* interrupt mode Rx */
while (size) while (size)
{ {
rt_base_t level; rt_base_t level;
/* disable interrupt */ /* disable interrupt */
level = rt_hw_interrupt_disable(); level = rt_hw_interrupt_disable();
if (uart->int_rx->read_index != uart->int_rx->save_index) if (uart->int_rx->read_index != uart->int_rx->save_index)
{ {
/* read a character */ /* read a character */
*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
size--; size--;
/* move to next position */ /* move to next position */
uart->int_rx->read_index ++; uart->int_rx->read_index ++;
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->read_index = 0; uart->int_rx->read_index = 0;
} }
else else
{ {
/* set error code */ /* set error code */
err_code = -RT_EEMPTY; err_code = -RT_EEMPTY;
/* enable interrupt */ /* enable interrupt */
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
break; break;
} }
/* enable interrupt */ /* enable interrupt */
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
} }
} }
else else
{ {
/* polling mode */ /* polling mode */
while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
{ {
while (uart->uart_device->SR & USART_FLAG_RXNE) while (uart->uart_device->SR & USART_FLAG_RXNE)
{ {
*ptr = uart->uart_device->DR & 0xff; *ptr = uart->uart_device->DR & 0xff;
ptr ++; ptr ++;
} }
} }
} }
/* set error code */ /* set error code */
rt_set_errno(err_code); rt_set_errno(err_code);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer; return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
} }
static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel, static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
rt_uint32_t address, rt_uint32_t size) rt_uint32_t address, rt_uint32_t size)
{ {
RT_ASSERT(dma_channel != RT_NULL); RT_ASSERT(dma_channel != RT_NULL);
/* disable DMA */ /* disable DMA */
DMA_Cmd(dma_channel, DISABLE); DMA_Cmd(dma_channel, DISABLE);
/* set buffer address */ /* set buffer address */
dma_channel->M0AR = address; dma_channel->M0AR = address;
/* set size */ /* set size */
dma_channel->NDTR = size; dma_channel->NDTR = size;
/* enable DMA */ /* enable DMA */
DMA_Cmd(dma_channel, ENABLE); DMA_Cmd(dma_channel, ENABLE);
} }
static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{ {
rt_uint8_t* ptr; rt_uint8_t* ptr;
rt_err_t err_code; rt_err_t err_code;
struct stm32_serial_device* uart; struct stm32_serial_device* uart;
err_code = RT_EOK; err_code = RT_EOK;
ptr = (rt_uint8_t*)buffer; ptr = (rt_uint8_t*)buffer;
uart = (struct stm32_serial_device*)dev->user_data; uart = (struct stm32_serial_device*)dev->user_data;
if (dev->flag & RT_DEVICE_FLAG_INT_TX) if (dev->flag & RT_DEVICE_FLAG_INT_TX)
{ {
/* interrupt mode Tx, does not support */ /* interrupt mode Tx, does not support */
RT_ASSERT(0); RT_ASSERT(0);
} }
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{ {
/* DMA mode Tx */ /* DMA mode Tx */
/* allocate a data node */ /* allocate a data node */
struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*) struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*)
rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER); rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER);
if (data_node == RT_NULL) if (data_node == RT_NULL)
{ {
/* set error code */ /* set error code */
err_code = -RT_ENOMEM; err_code = -RT_ENOMEM;
} }
else else
{ {
rt_uint32_t level; rt_uint32_t level;
/* fill data node */ /* fill data node */
data_node->data_ptr = ptr; data_node->data_ptr = ptr;
data_node->data_size = size; data_node->data_size = size;
/* insert to data link */ /* insert to data link */
data_node->next = RT_NULL; data_node->next = RT_NULL;
/* disable interrupt */ /* disable interrupt */
level = rt_hw_interrupt_disable(); level = rt_hw_interrupt_disable();
data_node->prev = uart->dma_tx->list_tail; data_node->prev = uart->dma_tx->list_tail;
if (uart->dma_tx->list_tail != RT_NULL) if (uart->dma_tx->list_tail != RT_NULL)
uart->dma_tx->list_tail->next = data_node; uart->dma_tx->list_tail->next = data_node;
uart->dma_tx->list_tail = data_node; uart->dma_tx->list_tail = data_node;
if (uart->dma_tx->list_head == RT_NULL) if (uart->dma_tx->list_head == RT_NULL)
{ {
/* start DMA to transmit data */ /* start DMA to transmit data */
uart->dma_tx->list_head = data_node; uart->dma_tx->list_head = data_node;
/* Enable DMA Channel */ /* Enable DMA Channel */
rt_serial_enable_dma(uart->dma_tx->dma_channel, rt_serial_enable_dma(uart->dma_tx->dma_channel,
(rt_uint32_t)uart->dma_tx->list_head->data_ptr, (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
uart->dma_tx->list_head->data_size); uart->dma_tx->list_head->data_size);
} }
/* enable interrupt */ /* enable interrupt */
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
} }
} }
else else
{ {
/* polling mode */ /* polling mode */
if (dev->flag & RT_DEVICE_FLAG_STREAM) if (dev->flag & RT_DEVICE_FLAG_STREAM)
{ {
/* stream mode */ /* stream mode */
while (size) while (size)
{ {
if (*ptr == '\n') if (*ptr == '\n')
{ {
while (!(uart->uart_device->SR & USART_FLAG_TXE)); while (!(uart->uart_device->SR & USART_FLAG_TXE));
uart->uart_device->DR = '\r'; uart->uart_device->DR = '\r';
} }
while (!(uart->uart_device->SR & USART_FLAG_TXE)); while (!(uart->uart_device->SR & USART_FLAG_TXE));
uart->uart_device->DR = (*ptr & 0x1FF); uart->uart_device->DR = (*ptr & 0x1FF);
++ptr; --size; ++ptr; --size;
} }
} }
else else
{ {
/* write data directly */ /* write data directly */
while (size) while (size)
{ {
while (!(uart->uart_device->SR & USART_FLAG_TXE)); while (!(uart->uart_device->SR & USART_FLAG_TXE));
uart->uart_device->DR = (*ptr & 0x1FF); uart->uart_device->DR = (*ptr & 0x1FF);
++ptr; --size; ++ptr; --size;
} }
} }
} }
/* set error code */ /* set error code */
rt_set_errno(err_code); rt_set_errno(err_code);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer; return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
} }
static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
{ {
struct stm32_serial_device* uart; struct stm32_serial_device* uart;
RT_ASSERT(dev != RT_NULL); RT_ASSERT(dev != RT_NULL);
uart = (struct stm32_serial_device*)dev->user_data; uart = (struct stm32_serial_device*)dev->user_data;
switch (cmd) switch (cmd)
{ {
case RT_DEVICE_CTRL_SUSPEND: case RT_DEVICE_CTRL_SUSPEND:
/* suspend device */ /* suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED; dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
USART_Cmd(uart->uart_device, DISABLE); USART_Cmd(uart->uart_device, DISABLE);
break; break;
case RT_DEVICE_CTRL_RESUME: case RT_DEVICE_CTRL_RESUME:
/* resume device */ /* resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
USART_Cmd(uart->uart_device, ENABLE); USART_Cmd(uart->uart_device, ENABLE);
break; break;
} }
return RT_EOK; return RT_EOK;
} }
/* /*
@ -280,87 +280,87 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
*/ */
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial) rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
{ {
RT_ASSERT(device != RT_NULL); RT_ASSERT(device != RT_NULL);
if ((flag & RT_DEVICE_FLAG_DMA_RX) || if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
(flag & RT_DEVICE_FLAG_INT_TX)) (flag & RT_DEVICE_FLAG_INT_TX))
{ {
RT_ASSERT(0); RT_ASSERT(0);
} }
device->type = RT_Device_Class_Char; device->type = RT_Device_Class_Char;
device->rx_indicate = RT_NULL; device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL; device->tx_complete = RT_NULL;
device->init = rt_serial_init; device->init = rt_serial_init;
device->open = rt_serial_open; device->open = rt_serial_open;
device->close = rt_serial_close; device->close = rt_serial_close;
device->read = rt_serial_read; device->read = rt_serial_read;
device->write = rt_serial_write; device->write = rt_serial_write;
device->control = rt_serial_control; device->control = rt_serial_control;
device->user_data = serial; device->user_data = serial;
/* register a character device */ /* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
} }
/* ISR for serial interrupt */ /* ISR for serial interrupt */
void rt_hw_serial_isr(rt_device_t device) void rt_hw_serial_isr(rt_device_t device)
{ {
struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data; struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
{ {
/* interrupt mode receive */ /* interrupt mode receive */
RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
/* save on rx buffer */ /* save on rx buffer */
while (uart->uart_device->SR & USART_FLAG_RXNE) while (uart->uart_device->SR & USART_FLAG_RXNE)
{ {
rt_base_t level; rt_base_t level;
/* disable interrupt */ /* disable interrupt */
level = rt_hw_interrupt_disable(); level = rt_hw_interrupt_disable();
/* save character */ /* save character */
uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff; uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff;
uart->int_rx->save_index ++; uart->int_rx->save_index ++;
if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->save_index = 0; uart->int_rx->save_index = 0;
/* if the next position is read index, discard this 'read char' */ /* if the next position is read index, discard this 'read char' */
if (uart->int_rx->save_index == uart->int_rx->read_index) if (uart->int_rx->save_index == uart->int_rx->read_index)
{ {
uart->int_rx->read_index ++; uart->int_rx->read_index ++;
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->read_index = 0; uart->int_rx->read_index = 0;
} }
/* enable interrupt */ /* enable interrupt */
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
} }
/* clear interrupt */ /* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
/* invoke callback */ /* invoke callback */
if (device->rx_indicate != RT_NULL) if (device->rx_indicate != RT_NULL)
{ {
rt_size_t rx_length; rt_size_t rx_length;
/* get rx length */ /* get rx length */
rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
uart->int_rx->save_index - uart->int_rx->read_index; uart->int_rx->save_index - uart->int_rx->read_index;
device->rx_indicate(device, rx_length); device->rx_indicate(device, rx_length);
} }
} }
if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
{ {
/* clear interrupt */ /* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
} }
} }
/* /*
@ -368,47 +368,47 @@ void rt_hw_serial_isr(rt_device_t device)
*/ */
void rt_hw_serial_dma_tx_isr(rt_device_t device) void rt_hw_serial_dma_tx_isr(rt_device_t device)
{ {
rt_uint32_t level; rt_uint32_t level;
struct stm32_serial_data_node* data_node; struct stm32_serial_data_node* data_node;
struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data; struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
/* DMA mode receive */ /* DMA mode receive */
RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX); RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
/* get the first data node */ /* get the first data node */
data_node = uart->dma_tx->list_head; data_node = uart->dma_tx->list_head;
RT_ASSERT(data_node != RT_NULL); RT_ASSERT(data_node != RT_NULL);
/* invoke call to notify tx complete */ /* invoke call to notify tx complete */
if (device->tx_complete != RT_NULL) if (device->tx_complete != RT_NULL)
device->tx_complete(device, data_node->data_ptr); device->tx_complete(device, data_node->data_ptr);
/* disable interrupt */ /* disable interrupt */
level = rt_hw_interrupt_disable(); level = rt_hw_interrupt_disable();
/* remove list head */ /* remove list head */
uart->dma_tx->list_head = data_node->next; uart->dma_tx->list_head = data_node->next;
if (uart->dma_tx->list_head == RT_NULL) /* data link empty */ if (uart->dma_tx->list_head == RT_NULL) /* data link empty */
uart->dma_tx->list_tail = RT_NULL; uart->dma_tx->list_tail = RT_NULL;
/* enable interrupt */ /* enable interrupt */
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
/* release data node memory */ /* release data node memory */
rt_mp_free(data_node); rt_mp_free(data_node);
if (uart->dma_tx->list_head != RT_NULL) if (uart->dma_tx->list_head != RT_NULL)
{ {
/* transmit next data node */ /* transmit next data node */
rt_serial_enable_dma(uart->dma_tx->dma_channel, rt_serial_enable_dma(uart->dma_tx->dma_channel,
(rt_uint32_t)uart->dma_tx->list_head->data_ptr, (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
uart->dma_tx->list_head->data_size); uart->dma_tx->list_head->data_size);
} }
else else
{ {
/* no data to be transmitted, disable DMA */ /* no data to be transmitted, disable DMA */
DMA_Cmd(uart->dma_tx->dma_channel, DISABLE); DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
} }
} }
/*@}*/ /*@}*/

42
bsp/stm32f20x/Drivers/serial.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -17,45 +17,45 @@
/* STM32F10x library definitions */ /* STM32F10x library definitions */
#include <stm32f2xx.h> #include <stm32f2xx.h>
#define UART_RX_BUFFER_SIZE 64 #define UART_RX_BUFFER_SIZE 64
#define UART_TX_DMA_NODE_SIZE 4 #define UART_TX_DMA_NODE_SIZE 4
/* data node for Tx Mode */ /* data node for Tx Mode */
struct stm32_serial_data_node struct stm32_serial_data_node
{ {
rt_uint8_t *data_ptr; rt_uint8_t *data_ptr;
rt_size_t data_size; rt_size_t data_size;
struct stm32_serial_data_node *next, *prev; struct stm32_serial_data_node *next, *prev;
}; };
struct stm32_serial_dma_tx struct stm32_serial_dma_tx
{ {
/* DMA Channel */ /* DMA Channel */
DMA_Stream_TypeDef* dma_channel; DMA_Stream_TypeDef* dma_channel;
/* data list head and tail */ /* data list head and tail */
struct stm32_serial_data_node *list_head, *list_tail; struct stm32_serial_data_node *list_head, *list_tail;
/* data node memory pool */ /* data node memory pool */
struct rt_mempool data_node_mp; struct rt_mempool data_node_mp;
rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE * rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE *
(sizeof(struct stm32_serial_data_node) + sizeof(void*))]; (sizeof(struct stm32_serial_data_node) + sizeof(void*))];
}; };
struct stm32_serial_int_rx struct stm32_serial_int_rx
{ {
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index; rt_uint32_t read_index, save_index;
}; };
struct stm32_serial_device struct stm32_serial_device
{ {
USART_TypeDef* uart_device; USART_TypeDef* uart_device;
/* rx structure */ /* rx structure */
struct stm32_serial_int_rx* int_rx; struct stm32_serial_int_rx* int_rx;
/* tx structure */ /* tx structure */
struct stm32_serial_dma_tx* dma_tx; struct stm32_serial_dma_tx* dma_tx;
}; };
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial); rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial);

476
bsp/stm32f20x/Drivers/stm32f2_eth.c
View File

@ -10,7 +10,7 @@
#include "stm32f2x7_eth.h" #include "stm32f2x7_eth.h"
#include "stm32f2x7_eth_conf.h" #include "stm32f2x7_eth_conf.h"
#define STM32_ETH_DEBUG 0 #define STM32_ETH_DEBUG 0
//#define CHECKSUM_BY_HARDWARE /* don't ues hardware checksum. */ //#define CHECKSUM_BY_HARDWARE /* don't ues hardware checksum. */
/* MII and RMII mode selection, for STM322xG-EVAL Board(MB786) RevB ***********/ /* MII and RMII mode selection, for STM322xG-EVAL Board(MB786) RevB ***********/
@ -42,11 +42,11 @@ extern ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos;
#define MAX_ADDR_LEN 6 #define MAX_ADDR_LEN 6
struct rt_stm32_eth struct rt_stm32_eth
{ {
/* inherit from ethernet device */ /* inherit from ethernet device */
struct eth_device parent; struct eth_device parent;
/* interface address info. */ /* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
}; };
static struct rt_stm32_eth stm32_eth_device; static struct rt_stm32_eth stm32_eth_device;
static struct rt_semaphore tx_wait; static struct rt_semaphore tx_wait;
@ -61,28 +61,28 @@ void ETH_IRQHandler(void)
{ {
rt_uint32_t status; rt_uint32_t status;
status = ETH->DMASR; status = ETH->DMASR;
/* Frame received */ /* Frame received */
if ( ETH_GetDMAFlagStatus(ETH_DMA_FLAG_R) == SET) if ( ETH_GetDMAFlagStatus(ETH_DMA_FLAG_R) == SET)
{ {
rt_err_t result; rt_err_t result;
//rt_kprintf("Frame comming\n"); //rt_kprintf("Frame comming\n");
/* Clear the interrupt flags. */ /* Clear the interrupt flags. */
/* Clear the Eth DMA Rx IT pending bits */ /* Clear the Eth DMA Rx IT pending bits */
ETH_DMAClearITPendingBit(ETH_DMA_IT_R); ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
/* a frame has been received */ /* a frame has been received */
result = eth_device_ready(&(stm32_eth_device.parent)); result = eth_device_ready(&(stm32_eth_device.parent));
if( result != RT_EOK ) rt_kprintf("RX err =%d\n", result ); if( result != RT_EOK ) rt_kprintf("RX err =%d\n", result );
//RT_ASSERT(result == RT_EOK); //RT_ASSERT(result == RT_EOK);
} }
if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */ if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */
{ {
ETH_DMAClearITPendingBit(ETH_DMA_IT_T); ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
} }
ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS); ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
// //
} }
@ -91,244 +91,244 @@ void ETH_IRQHandler(void)
/* initialize the interface */ /* initialize the interface */
static rt_err_t rt_stm32_eth_init(rt_device_t dev) static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{ {
int i; int i;
/* MAC address configuration */ /* MAC address configuration */
ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]); ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);
/* Initialize Tx Descriptors list: Chain Mode */ /* Initialize Tx Descriptors list: Chain Mode */
ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
/* Initialize Rx Descriptors list: Chain Mode */ /* Initialize Rx Descriptors list: Chain Mode */
ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
/* Enable Ethernet Rx interrrupt */ /* Enable Ethernet Rx interrrupt */
{ {
for(i=0; i<ETH_RXBUFNB; i++) for(i=0; i<ETH_RXBUFNB; i++)
{ {
ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE); ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE);
} }
} }
#ifdef CHECKSUM_BY_HARDWARE #ifdef CHECKSUM_BY_HARDWARE
/* Enable the checksum insertion for the Tx frames */ /* Enable the checksum insertion for the Tx frames */
{ {
for(i=0; i<ETH_TXBUFNB; i++) for(i=0; i<ETH_TXBUFNB; i++)
{ {
ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull); ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
} }
} }
#endif #endif
{ {
uint16_t tmp, i=10000; uint16_t tmp, i=10000;
tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR); tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);
ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1, BIST_CONT_MODE ); ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1, BIST_CONT_MODE );
ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp | BIST_START );//BIST_START ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp | BIST_START );//BIST_START
while(i--); while(i--);
//tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR); //tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);
if( ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR) & BIST_STATUS == BIST_STATUS ) if( ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR) & BIST_STATUS == BIST_STATUS )
{ {
rt_kprintf("BIST pass\n"); rt_kprintf("BIST pass\n");
} }
else else
{ {
uint16_t ctrl; uint16_t ctrl;
ctrl = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1); ctrl = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1);
rt_kprintf("BIST faild count =%d\n", BIST_ERROR_COUNT(ctrl) ); rt_kprintf("BIST faild count =%d\n", BIST_ERROR_COUNT(ctrl) );
} }
tmp &= ~BIST_START; //Stop BIST tmp &= ~BIST_START; //Stop BIST
ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp); ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp);
} }
/* Enable MAC and DMA transmission and reception */ /* Enable MAC and DMA transmission and reception */
ETH_Start(); ETH_Start();
//rt_kprintf("DMASR = 0x%X\n", ETH->DMASR ); //rt_kprintf("DMASR = 0x%X\n", ETH->DMASR );
// rt_kprintf("ETH Init\n"); // rt_kprintf("ETH Init\n");
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_stm32_eth_close(rt_device_t dev) static rt_err_t rt_stm32_eth_close(rt_device_t dev)
{ {
return RT_EOK; return RT_EOK;
} }
static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{ {
rt_set_errno(-RT_ENOSYS); rt_set_errno(-RT_ENOSYS);
return 0; return 0;
} }
static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{ {
rt_set_errno(-RT_ENOSYS); rt_set_errno(-RT_ENOSYS);
return 0; return 0;
} }
static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args) static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
{ {
switch(cmd) switch(cmd)
{ {
case NIOCTL_GADDR: case NIOCTL_GADDR:
/* get mac address */ /* get mac address */
if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6); if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
else return -RT_ERROR; else return -RT_ERROR;
break; break;
default : default :
break; break;
} }
return RT_EOK; return RT_EOK;
} }
void show_frame(struct pbuf *q) void show_frame(struct pbuf *q)
{ {
int i = 0; int i = 0;
int j = 0; int j = 0;
char *ptr = q->payload; char *ptr = q->payload;
for( i = 0; i < q->len; i++ ) for( i = 0; i < q->len; i++ )
rt_kprintf("0x%02X ", *(ptr++)); rt_kprintf("0x%02X ", *(ptr++));
rt_kprintf("\n"); rt_kprintf("\n");
} }
/* ethernet device interface */ /* ethernet device interface */
/* transmit packet. */ /* transmit packet. */
rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
{ {
rt_err_t ret; rt_err_t ret;
struct pbuf *q; struct pbuf *q;
uint32_t l = 0; uint32_t l = 0;
u8 *buffer ; u8 *buffer ;
if (( ret = rt_sem_take(&tx_wait, netifGUARD_BLOCK_TIME) ) == RT_EOK) if (( ret = rt_sem_take(&tx_wait, netifGUARD_BLOCK_TIME) ) == RT_EOK)
{ {
buffer = (u8 *)(DMATxDescToSet->Buffer1Addr); buffer = (u8 *)(DMATxDescToSet->Buffer1Addr);
for(q = p; q != NULL; q = q->next) for(q = p; q != NULL; q = q->next)
{ {
//show_frame(q); //show_frame(q);
rt_memcpy((u8_t*)&buffer[l], q->payload, q->len); rt_memcpy((u8_t*)&buffer[l], q->payload, q->len);
l = l + q->len; l = l + q->len;
} }
if( ETH_Prepare_Transmit_Descriptors(l) == ETH_ERROR ) if( ETH_Prepare_Transmit_Descriptors(l) == ETH_ERROR )
rt_kprintf("Tx Error\n"); rt_kprintf("Tx Error\n");
//rt_sem_release(xTxSemaphore); //rt_sem_release(xTxSemaphore);
rt_sem_release(&tx_wait); rt_sem_release(&tx_wait);
//rt_kprintf("Tx packet, len = %d\n", l); //rt_kprintf("Tx packet, len = %d\n", l);
} }
else else
{ {
rt_kprintf("Tx Timeout\n"); rt_kprintf("Tx Timeout\n");
return ret; return ret;
} }
/* Return SUCCESS */ /* Return SUCCESS */
return RT_EOK; return RT_EOK;
} }
/* reception packet. */ /* reception packet. */
struct pbuf *rt_stm32_eth_rx(rt_device_t dev) struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
{ {
struct pbuf *p, *q; struct pbuf *p, *q;
u16_t len; u16_t len;
uint32_t l=0,i =0; uint32_t l=0,i =0;
FrameTypeDef frame; FrameTypeDef frame;
static framecnt = 1; static framecnt = 1;
u8 *buffer; u8 *buffer;
__IO ETH_DMADESCTypeDef *DMARxNextDesc; __IO ETH_DMADESCTypeDef *DMARxNextDesc;
p = RT_NULL; p = RT_NULL;
// rt_kprintf("ETH rx\n"); // rt_kprintf("ETH rx\n");
/* Get received frame */ /* Get received frame */
frame = ETH_Get_Received_Frame_interrupt(); frame = ETH_Get_Received_Frame_interrupt();
if( frame.length > 0 ) if( frame.length > 0 )
{ {
/* check that frame has no error */ /* check that frame has no error */
if ((frame.descriptor->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) if ((frame.descriptor->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET)
{ {
//rt_kprintf("Get a frame %d buf = 0x%X, len= %d\n", framecnt++, frame.buffer, frame.length); //rt_kprintf("Get a frame %d buf = 0x%X, len= %d\n", framecnt++, frame.buffer, frame.length);
/* Obtain the size of the packet and put it into the "len" variable. */ /* Obtain the size of the packet and put it into the "len" variable. */
len = frame.length; len = frame.length;
buffer = (u8 *)frame.buffer; buffer = (u8 *)frame.buffer;
/* We allocate a pbuf chain of pbufs from the pool. */ /* We allocate a pbuf chain of pbufs from the pool. */
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
//p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); //p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
/* Copy received frame from ethernet driver buffer to stack buffer */ /* Copy received frame from ethernet driver buffer to stack buffer */
if (p != NULL) if (p != NULL)
{ {
for (q = p; q != NULL; q = q->next) for (q = p; q != NULL; q = q->next)
{ {
rt_memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len); rt_memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len);
l = l + q->len; l = l + q->len;
} }
} }
} }
/* Release descriptors to DMA */ /* Release descriptors to DMA */
/* Check if received frame with multiple DMA buffer segments */ /* Check if received frame with multiple DMA buffer segments */
if (DMA_RX_FRAME_infos->Seg_Count > 1) if (DMA_RX_FRAME_infos->Seg_Count > 1)
{ {
DMARxNextDesc = DMA_RX_FRAME_infos->FS_Rx_Desc; DMARxNextDesc = DMA_RX_FRAME_infos->FS_Rx_Desc;
} }
else else
{ {
DMARxNextDesc = frame.descriptor; DMARxNextDesc = frame.descriptor;
} }
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */ /* Set Own bit in Rx descriptors: gives the buffers back to DMA */
for (i=0; i<DMA_RX_FRAME_infos->Seg_Count; i++) for (i=0; i<DMA_RX_FRAME_infos->Seg_Count; i++)
{ {
DMARxNextDesc->Status = ETH_DMARxDesc_OWN; DMARxNextDesc->Status = ETH_DMARxDesc_OWN;
DMARxNextDesc = (ETH_DMADESCTypeDef *)(DMARxNextDesc->Buffer2NextDescAddr); DMARxNextDesc = (ETH_DMADESCTypeDef *)(DMARxNextDesc->Buffer2NextDescAddr);
} }
/* Clear Segment_Count */ /* Clear Segment_Count */
DMA_RX_FRAME_infos->Seg_Count =0; DMA_RX_FRAME_infos->Seg_Count =0;
/* When Rx Buffer unavailable flag is set: clear it and resume reception */ /* When Rx Buffer unavailable flag is set: clear it and resume reception */
if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET) if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
{ {
/* Clear RBUS ETHERNET DMA flag */ /* Clear RBUS ETHERNET DMA flag */
ETH->DMASR = ETH_DMASR_RBUS; ETH->DMASR = ETH_DMASR_RBUS;
/* Resume DMA reception */ /* Resume DMA reception */
ETH->DMARPDR = 0; ETH->DMARPDR = 0;
} }
} }
return p; return p;
} }
static void NVIC_Configuration(void) static void NVIC_Configuration(void)
{ {
NVIC_InitTypeDef NVIC_InitStructure; NVIC_InitTypeDef NVIC_InitStructure;
/* 2 bit for pre-emption priority, 2 bits for subpriority */ /* 2 bit for pre-emption priority, 2 bits for subpriority */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
/* Enable the Ethernet global Interrupt */ /* Enable the Ethernet global Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn; NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure); NVIC_Init(&NVIC_InitStructure);
} }
/* /*
@ -383,15 +383,15 @@ static void GPIO_Configuration(void)
ETH_MII_TXD0/ETH_RMII_TXD0 -------> PB12 ETH_MII_TXD0/ETH_RMII_TXD0 -------> PB12
ETH_MII_TXD1/ETH_RMII_TXD1 -------> PB13 ETH_MII_TXD1/ETH_RMII_TXD1 -------> PB13
**** Just for MII Mode **** **** Just for MII Mode ****
ETH_MII_CRS ----------------------> PA0 ETH_MII_CRS ----------------------> PA0
ETH_MII_COL ----------------------> PA3 ETH_MII_COL ----------------------> PA3
ETH_MII_TX_CLK -------------------> PC3 ETH_MII_TX_CLK -------------------> PC3
ETH_MII_RX_ER --------------------> PB10 ETH_MII_RX_ER --------------------> PB10
ETH_MII_RXD2 ---------------------> PB0 ETH_MII_RXD2 ---------------------> PB0
ETH_MII_RXD3 ---------------------> PB1 ETH_MII_RXD3 ---------------------> PB1
ETH_MII_TXD2 ---------------------> PC2 ETH_MII_TXD2 ---------------------> PC2
ETH_MII_TXD3 ---------------------> PB8 ETH_MII_TXD3 ---------------------> PB8
*/ */
/* Configure PC1, PC4 and PC5 */ /* Configure PC1, PC4 and PC5 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 |GPIO_Pin_4 | GPIO_Pin_5; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 |GPIO_Pin_4 | GPIO_Pin_5;
@ -504,7 +504,7 @@ static void ETH_MACDMA_Config(void)
/* Configure Ethernet */ /* Configure Ethernet */
if( ETH_Init(&ETH_InitStructure, DP83848_PHY_ADDRESS) == ETH_ERROR ) if( ETH_Init(&ETH_InitStructure, DP83848_PHY_ADDRESS) == ETH_ERROR )
rt_kprintf("ETH init error, may be no link\n"); rt_kprintf("ETH init error, may be no link\n");
/* Enable the Ethernet Rx Interrupt */ /* Enable the Ethernet Rx Interrupt */
ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R , ENABLE); ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R , ENABLE);
@ -515,64 +515,64 @@ static void ETH_MACDMA_Config(void)
#define DevID_SNo2 (*((rt_uint32_t *)0x1FFF7A10+64)); #define DevID_SNo2 (*((rt_uint32_t *)0x1FFF7A10+64));
void rt_hw_stm32_eth_init(void) void rt_hw_stm32_eth_init(void)
{ {
GPIO_Configuration(); GPIO_Configuration();
NVIC_Configuration(); NVIC_Configuration();
ETH_MACDMA_Config(); ETH_MACDMA_Config();
stm32_eth_device.dev_addr[0] = 0x00; stm32_eth_device.dev_addr[0] = 0x00;
stm32_eth_device.dev_addr[1] = 0x60; stm32_eth_device.dev_addr[1] = 0x60;
stm32_eth_device.dev_addr[2] = 0x6e; stm32_eth_device.dev_addr[2] = 0x6e;
{ {
uint32_t cpu_id[3] = {0}; uint32_t cpu_id[3] = {0};
cpu_id[2] = DevID_SNo2; cpu_id[1] = DevID_SNo1; cpu_id[0] = DevID_SNo0; cpu_id[2] = DevID_SNo2; cpu_id[1] = DevID_SNo1; cpu_id[0] = DevID_SNo0;
// generate MAC addr from 96bit unique ID (only for test) // generate MAC addr from 96bit unique ID (only for test)
stm32_eth_device.dev_addr[3] = (uint8_t)((cpu_id[0]>>16)&0xFF); stm32_eth_device.dev_addr[3] = (uint8_t)((cpu_id[0]>>16)&0xFF);
stm32_eth_device.dev_addr[4] = (uint8_t)((cpu_id[0]>>8)&0xFF); stm32_eth_device.dev_addr[4] = (uint8_t)((cpu_id[0]>>8)&0xFF);
stm32_eth_device.dev_addr[5] = (uint8_t)(cpu_id[0]&0xFF); stm32_eth_device.dev_addr[5] = (uint8_t)(cpu_id[0]&0xFF);
// stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7); // stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7);
// stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8); // stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8);
// stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9); // stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9);
} }
stm32_eth_device.parent.parent.init = rt_stm32_eth_init; stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
stm32_eth_device.parent.parent.open = rt_stm32_eth_open; stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
stm32_eth_device.parent.parent.close = rt_stm32_eth_close; stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
stm32_eth_device.parent.parent.read = rt_stm32_eth_read; stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
stm32_eth_device.parent.parent.write = rt_stm32_eth_write; stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
stm32_eth_device.parent.parent.control = rt_stm32_eth_control; stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
stm32_eth_device.parent.parent.user_data = RT_NULL; stm32_eth_device.parent.parent.user_data = RT_NULL;
stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
/* init tx semaphore */ /* init tx semaphore */
rt_sem_init(&tx_wait, "tx_wait", 1, RT_IPC_FLAG_FIFO); rt_sem_init(&tx_wait, "tx_wait", 1, RT_IPC_FLAG_FIFO);
/* register eth device */ /* register eth device */
eth_device_init(&(stm32_eth_device.parent), "e0"); eth_device_init(&(stm32_eth_device.parent), "e0");
} }
static char led = 0; static char led = 0;
void dp83483() void dp83483()
{ {
uint16_t bsr,sts, bcr, phycr; uint16_t bsr,sts, bcr, phycr;
bsr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR); bsr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR);
sts = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR); sts = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR);
bcr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BCR); bcr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BCR);
phycr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR); phycr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);
rt_kprintf("BCR = 0x%X\tBSR = 0x%X\tPHY_STS = 0x%X\tPHY_CR = 0x%X\n", bcr,bsr,sts, phycr); rt_kprintf("BCR = 0x%X\tBSR = 0x%X\tPHY_STS = 0x%X\tPHY_CR = 0x%X\n", bcr,bsr,sts, phycr);
rt_kprintf("PHY_FCSCR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_FCSCR ) ); rt_kprintf("PHY_FCSCR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_FCSCR ) );
rt_kprintf("PHY_MISR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_MISR ) ); rt_kprintf("PHY_MISR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_MISR ) );
rt_kprintf("DMASR = 0x%X\n", ETH->DMASR ); rt_kprintf("DMASR = 0x%X\n", ETH->DMASR );
//ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_LEDCR, (uint16_t)(0x38 | led)); //ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_LEDCR, (uint16_t)(0x38 | led));
led = (led==7)?0:7; led = (led==7)?0:7;
} }
#ifdef RT_USING_FINSH #ifdef RT_USING_FINSH

2
bsp/stm32f20x/Drivers/stm32f2xx_it.c
View File

@ -145,7 +145,7 @@ void SDIO_IRQHandler(void)
/* Process All SDIO Interrupt Sources */ /* Process All SDIO Interrupt Sources */
if( SD_ProcessIRQSrc() == 2) if( SD_ProcessIRQSrc() == 2)
rt_kprintf("SD Error\n"); rt_kprintf("SD Error\n");
/* leave interrupt */ /* leave interrupt */
rt_interrupt_leave(); rt_interrupt_leave();

234
bsp/stm32f20x/Drivers/usart.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -34,9 +34,9 @@
struct stm32_serial_int_rx uart1_int_rx; struct stm32_serial_int_rx uart1_int_rx;
struct stm32_serial_device uart1 = struct stm32_serial_device uart1 =
{ {
USART1, USART1,
&uart1_int_rx, &uart1_int_rx,
RT_NULL RT_NULL
}; };
struct rt_device uart1_device; struct rt_device uart1_device;
#endif #endif
@ -45,9 +45,9 @@ struct rt_device uart1_device;
struct stm32_serial_int_rx uart6_int_rx; struct stm32_serial_int_rx uart6_int_rx;
struct stm32_serial_device uart6 = struct stm32_serial_device uart6 =
{ {
USART6, USART6,
&uart6_int_rx, &uart6_int_rx,
RT_NULL RT_NULL
}; };
struct rt_device uart6_device; struct rt_device uart6_device;
#endif #endif
@ -56,9 +56,9 @@ struct rt_device uart6_device;
struct stm32_serial_int_rx uart2_int_rx; struct stm32_serial_int_rx uart2_int_rx;
struct stm32_serial_device uart2 = struct stm32_serial_device uart2 =
{ {
USART2, USART2,
&uart2_int_rx, &uart2_int_rx,
RT_NULL RT_NULL
}; };
struct rt_device uart2_device; struct rt_device uart2_device;
#endif #endif
@ -68,9 +68,9 @@ struct stm32_serial_int_rx uart3_int_rx;
struct stm32_serial_dma_tx uart3_dma_tx; struct stm32_serial_dma_tx uart3_dma_tx;
struct stm32_serial_device uart3 = struct stm32_serial_device uart3 =
{ {
USART3, USART3,
&uart3_int_rx, &uart3_int_rx,
&uart3_dma_tx &uart3_dma_tx
}; };
struct rt_device uart3_device; struct rt_device uart3_device;
#endif #endif
@ -80,110 +80,110 @@ struct rt_device uart3_device;
#define USART3_DR_Base 0x40004804 #define USART3_DR_Base 0x40004804
/* USART1_REMAP = 0 */ /* USART1_REMAP = 0 */
#define UART1_GPIO_TX GPIO_Pin_9 #define UART1_GPIO_TX GPIO_Pin_9
#define UART1_GPIO_RX GPIO_Pin_10 #define UART1_GPIO_RX GPIO_Pin_10
#define UART1_GPIO GPIOA #define UART1_GPIO GPIOA
#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1 #define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
#define UART1_TX_DMA DMA1_Channel4 #define UART1_TX_DMA DMA1_Channel4
#define UART1_RX_DMA DMA1_Channel5 #define UART1_RX_DMA DMA1_Channel5
#if defined(STM32F10X_LD) || defined(STM32F10X_MD) || defined(STM32F10X_CL) #if defined(STM32F10X_LD) || defined(STM32F10X_MD) || defined(STM32F10X_CL)
#define UART2_GPIO_TX GPIO_Pin_5 #define UART2_GPIO_TX GPIO_Pin_5
#define UART2_GPIO_RX GPIO_Pin_6 #define UART2_GPIO_RX GPIO_Pin_6
#define UART2_GPIO GPIOD #define UART2_GPIO GPIOD
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2 #define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
#else /* for STM32F10X_HD */ #else /* for STM32F10X_HD */
/* USART2_REMAP = 0 */ /* USART2_REMAP = 0 */
#define UART2_GPIO_TX GPIO_Pin_2 #define UART2_GPIO_TX GPIO_Pin_2
#define UART2_GPIO_RX GPIO_Pin_3 #define UART2_GPIO_RX GPIO_Pin_3
#define UART2_GPIO GPIOA #define UART2_GPIO GPIOA
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2 #define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
#define UART2_TX_DMA DMA1_Channel7 #define UART2_TX_DMA DMA1_Channel7
#define UART2_RX_DMA DMA1_Channel6 #define UART2_RX_DMA DMA1_Channel6
#endif #endif
/* USART3_REMAP[1:0] = 00 */ /* USART3_REMAP[1:0] = 00 */
#define UART3_GPIO_RX GPIO_Pin_11 #define UART3_GPIO_RX GPIO_Pin_11
#define UART3_GPIO_TX GPIO_Pin_10 #define UART3_GPIO_TX GPIO_Pin_10
#define UART3_GPIO GPIOB #define UART3_GPIO GPIOB
#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3 #define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
#define UART3_TX_DMA DMA1_Channel2 #define UART3_TX_DMA DMA1_Channel2
#define UART3_RX_DMA DMA1_Channel3 #define UART3_RX_DMA DMA1_Channel3
/* USART6_REMAP = 0 */ /* USART6_REMAP = 0 */
#define UART6_GPIO_TX GPIO_Pin_6 #define UART6_GPIO_TX GPIO_Pin_6
#define UART6_GPIO_RX GPIO_Pin_7 #define UART6_GPIO_RX GPIO_Pin_7
#define UART6_GPIO GPIOC #define UART6_GPIO GPIOC
#define RCC_APBPeriph_UART6 RCC_APB2Periph_USART6 #define RCC_APBPeriph_UART6 RCC_APB2Periph_USART6
//#define UART1_TX_DMA DMA1_Channel? //#define UART1_TX_DMA DMA1_Channel?
//#define UART1_RX_DMA DMA1_Channel? //#define UART1_RX_DMA DMA1_Channel?
static void RCC_Configuration(void) static void RCC_Configuration(void)
{ {
#ifdef RT_USING_UART1 #ifdef RT_USING_UART1
/* Enable USART1 and GPIOA clocks */ /* Enable USART1 and GPIOA clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
#endif #endif
#ifdef RT_USING_UART6 #ifdef RT_USING_UART6
/* Enable USART6 and GPIOC clocks */ /* Enable USART6 and GPIOC clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
#endif #endif
} }
static void GPIO_Configuration(void) static void GPIO_Configuration(void)
{ {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
#ifdef RT_USING_UART1 #ifdef RT_USING_UART1
GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF; GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz; GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
GPIO_InitStruct.GPIO_OType=GPIO_OType_PP; GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP; GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
GPIO_InitStruct.GPIO_Pin=GPIO_Pin_9|GPIO_Pin_10; GPIO_InitStruct.GPIO_Pin=GPIO_Pin_9|GPIO_Pin_10;
GPIO_Init(GPIOA,&GPIO_InitStruct); GPIO_Init(GPIOA,&GPIO_InitStruct);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1); GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1); GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);
#endif #endif
#ifdef RT_USING_UART6 #ifdef RT_USING_UART6
GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF; GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz; GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
GPIO_InitStruct.GPIO_OType=GPIO_OType_PP; GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP; GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
GPIO_InitStruct.GPIO_Pin=UART6_GPIO_TX|UART6_GPIO_RX; GPIO_InitStruct.GPIO_Pin=UART6_GPIO_TX|UART6_GPIO_RX;
GPIO_Init(UART6_GPIO,&GPIO_InitStruct); GPIO_Init(UART6_GPIO,&GPIO_InitStruct);
GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource6, GPIO_AF_USART6); GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource6, GPIO_AF_USART6);
GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource7, GPIO_AF_USART6); GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource7, GPIO_AF_USART6);
#endif #endif
} }
static void NVIC_Configuration(void) static void NVIC_Configuration(void)
{ {
NVIC_InitTypeDef NVIC_InitStructure; NVIC_InitTypeDef NVIC_InitStructure;
#ifdef RT_USING_UART1 #ifdef RT_USING_UART1
/* Enable the USART1 Interrupt */ /* Enable the USART1 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure); NVIC_Init(&NVIC_InitStructure);
#endif #endif
#ifdef RT_USING_UART6 #ifdef RT_USING_UART6
/* Enable the USART1 Interrupt */ /* Enable the USART1 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn; NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure); NVIC_Init(&NVIC_InitStructure);
#endif #endif
} }
@ -193,60 +193,60 @@ static void NVIC_Configuration(void)
*/ */
void rt_hw_usart_init() void rt_hw_usart_init()
{ {
USART_InitTypeDef USART_InitStructure; USART_InitTypeDef USART_InitStructure;
RCC_Configuration(); RCC_Configuration();
GPIO_Configuration(); GPIO_Configuration();
NVIC_Configuration(); NVIC_Configuration();
/* uart init */ /* uart init */
#ifdef RT_USING_UART1 #ifdef RT_USING_UART1
USART_DeInit(USART1); USART_DeInit(USART1);
USART_InitStructure.USART_BaudRate = 115200; USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b; USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1; USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No ; USART_InitStructure.USART_Parity = USART_Parity_No ;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USART1, &USART_InitStructure); USART_Init(USART1, &USART_InitStructure);
/* register uart1 */ /* register uart1 */
rt_hw_serial_register(&uart1_device, "uart1", rt_hw_serial_register(&uart1_device, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart1); &uart1);
/* enable interrupt */ /* enable interrupt */
USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
/* Enable USART1 */ /* Enable USART1 */
USART_Cmd(USART1, ENABLE); USART_Cmd(USART1, ENABLE);
USART_ClearFlag(USART1,USART_FLAG_TXE); USART_ClearFlag(USART1,USART_FLAG_TXE);
#endif #endif
/* uart init */ /* uart init */
#ifdef RT_USING_UART6 #ifdef RT_USING_UART6
USART_DeInit(USART6); USART_DeInit(USART6);
USART_InitStructure.USART_BaudRate = 115200; USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b; USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1; USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No ; USART_InitStructure.USART_Parity = USART_Parity_No ;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USART6, &USART_InitStructure); USART_Init(USART6, &USART_InitStructure);
/* register uart1 */ /* register uart1 */
rt_hw_serial_register(&uart6_device, "uart6", rt_hw_serial_register(&uart6_device, "uart6",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart6); &uart6);
/* enable interrupt */ /* enable interrupt */
USART_ITConfig(USART6, USART_IT_RXNE, ENABLE); USART_ITConfig(USART6, USART_IT_RXNE, ENABLE);
/* Enable USART6 */ /* Enable USART6 */
USART_Cmd(USART6, ENABLE); USART_Cmd(USART6, ENABLE);
USART_ClearFlag(USART6,USART_FLAG_TXE); USART_ClearFlag(USART6,USART_FLAG_TXE);
#endif #endif
} }

2
bsp/stm32f20x/Drivers/usart.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/stm32f20x/applications/application.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

70
bsp/stm32f20x/applications/startup.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -42,11 +42,11 @@ extern int __bss_end;
*******************************************************************************/ *******************************************************************************/
void assert_failed(u8* file, u32 line) void assert_failed(u8* file, u32 line)
{ {
rt_kprintf("\n\r Wrong parameter value detected on\r\n"); rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file); rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line); rt_kprintf(" line %d\r\n", line);
while (1) ; while (1) ;
} }
#endif #endif
@ -55,58 +55,58 @@ void assert_failed(u8* file, u32 line)
*/ */
void rtthread_startup(void) void rtthread_startup(void)
{ {
/* init board */ /* init board */
rt_hw_board_init(); rt_hw_board_init();
/* show version */ /* show version */
rt_show_version(); rt_show_version();
/* init timer system */ /* init timer system */
rt_system_timer_init(); rt_system_timer_init();
#ifdef RT_USING_HEAP #ifdef RT_USING_HEAP
#if STM32_EXT_SRAM #if STM32_EXT_SRAM
rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END); rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END);
#else #else
#if defined(__CC_ARM) || defined(__CLANG_ARM) #if defined(__CC_ARM) || defined(__CLANG_ARM)
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END); rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END);
#elif __ICCARM__ #elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END); rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END);
#else #else
/* init memory system */ /* init memory system */
rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END); rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END);
#endif #endif
#endif #endif
#endif #endif
/* init scheduler system */ /* init scheduler system */
rt_system_scheduler_init(); rt_system_scheduler_init();
/* init application */ /* init application */
rt_application_init(); rt_application_init();
/* init timer thread */ /* init timer thread */
rt_system_timer_thread_init(); rt_system_timer_thread_init();
/* init idle thread */ /* init idle thread */
rt_thread_idle_init(); rt_thread_idle_init();
/* start scheduler */ /* start scheduler */
rt_system_scheduler_start(); rt_system_scheduler_start();
/* never reach here */ /* never reach here */
return ; return ;
} }
int main(void) int main(void)
{ {
/* disable interrupt first */ /* disable interrupt first */
rt_hw_interrupt_disable(); rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */ /* startup RT-Thread RTOS */
rtthread_startup(); rtthread_startup();
return 0; return 0;
} }
/*@}*/ /*@}*/