for rt-thread 1.1.0
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2372 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
parent
2cdbbf8b05
commit
6fe2afed8c
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@ -11,7 +11,7 @@
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* Date Author Notes
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* Date Author Notes
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* 2006-08-23 Bernard first implementation
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* 2006-08-23 Bernard first implementation
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*
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*
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* 2011-12-17 nl1031 for MicroBlaze
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* 2011-12-17 nl1031 for MacroBlaze
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*
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*
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*/
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*/
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@ -48,6 +48,9 @@ XGpio gpio_output; /* The driver instance for GPIO Device configured as O/P */
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XUartLite uart_lite; /* Instance of the UartLite device */
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XUartLite uart_lite; /* Instance of the UartLite device */
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XIntc int_ctl; /* The instance of the Interrupt Controller */
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XIntc int_ctl; /* The instance of the Interrupt Controller */
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static rt_uint32_t led_data;
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static rt_uint32_t led_data;
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static int cnt;
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static void rt_hw_board_led_init(void);
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static void rt_hw_board_led_init(void);
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@ -58,6 +61,7 @@ static void rt_hw_board_led_init()
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{
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{
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rt_uint32_t status;
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rt_uint32_t status;
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led_data = 0;
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led_data = 0;
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cnt = 0;
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status = XGpio_Initialize(&gpio_output, LEDS_DEVICE_ID);
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status = XGpio_Initialize(&gpio_output, LEDS_DEVICE_ID);
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if (status != XST_SUCCESS)
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if (status != XST_SUCCESS)
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{
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{
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@ -96,9 +100,10 @@ void rt_hw_board_led_off(rt_uint32_t led)
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XGpio_DiscreteWrite(&gpio_output, 1, led_data);
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XGpio_DiscreteWrite(&gpio_output, 1, led_data);
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}
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}
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void rt_hw_led_flash(void)
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void rt_hw_led_flash(void)
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{
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{
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rt_uint32_t i;
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volatile rt_uint32_t i;
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rt_hw_board_led_off(1);
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rt_hw_board_led_off(1);
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for (i = 0; i < 20000; i ++);
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for (i = 0; i < 20000; i ++);
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@ -107,6 +112,7 @@ void rt_hw_led_flash(void)
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for (i = 0; i < 20000; i ++);
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for (i = 0; i < 20000; i ++);
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}
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}
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#ifdef RT_USING_CONSOLE
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#ifdef RT_USING_CONSOLE
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/*
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/*
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@ -124,6 +130,7 @@ void rt_hw_console_output(const char* str)
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{
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{
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/* Transmit Character */
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/* Transmit Character */
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XUartLite_SendByte(STDOUT_BASEADDRESS, *str);
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XUartLite_SendByte(STDOUT_BASEADDRESS, *str);
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if (*str == '\n')
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if (*str == '\n')
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XUartLite_SendByte(STDOUT_BASEADDRESS, '\r');
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XUartLite_SendByte(STDOUT_BASEADDRESS, '\r');
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@ -147,6 +154,7 @@ static void rt_hw_console_init()
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}
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}
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#endif
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#endif
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void rt_hw_timer_handler(void)
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void rt_hw_timer_handler(void)
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{
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{
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rt_uint32_t csr;
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rt_uint32_t csr;
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@ -157,12 +165,12 @@ void rt_hw_timer_handler(void)
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if (csr & XTC_CSR_INT_OCCURED_MASK)
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if (csr & XTC_CSR_INT_OCCURED_MASK)
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{
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{
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rt_tick_increase();
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rt_tick_increase();
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, csr | XTC_CSR_INT_OCCURED_MASK);
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, csr | XTC_CSR_INT_OCCURED_MASK);
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}
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}
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}
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}
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/*
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/*
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*********************************************************************************************************
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*********************************************************************************************************
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* rt_intc_init()
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* rt_intc_init()
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@ -186,31 +194,33 @@ void rt_intc_init(void)
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/* install interrupt handler */
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/* install interrupt handler */
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rt_hw_interrupt_install(XPAR_INTC_0_TMRCTR_0_VEC_ID, (rt_isr_handler_t)rt_hw_timer_handler, RT_NULL);
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rt_hw_interrupt_install(XPAR_INTC_0_TMRCTR_0_VEC_ID, (rt_isr_handler_t)rt_hw_timer_handler, RT_NULL);
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rt_hw_interrupt_umask(XPAR_INTC_0_TMRCTR_0_VEC_ID);
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rt_hw_interrupt_umask(XPAR_INTC_0_TMRCTR_0_VEC_ID);
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XIntc_Start(&int_ctl, XIN_REAL_MODE);
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XIntc_Start(&int_ctl, XIN_REAL_MODE);
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}
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}
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void rt_tmr_init (void)
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void rt_tmr_init (void)
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{
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{
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rt_uint32_t ctl;
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rt_uint32_t ctl;
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XStatus status;
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XStatus status;
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status = XTmrCtr_Initialize(&timer,XPAR_AXI_TIMER_0_DEVICE_ID);
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status = XTmrCtr_Initialize(&timer,XPAR_AXI_TIMER_0_DEVICE_ID);
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TLR_OFFSET, PIV);
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TLR_OFFSET, PIV);
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ctl = XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK;
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ctl = XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK;
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, ctl);
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, ctl);
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}
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}
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/**
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/**
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* This function will initial SPARTAN 6 LX9 board.
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* This function will initial SPARTAN 6 LX9 board.
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*/
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*/
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void rt_hw_board_init()
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void rt_hw_board_init()
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{
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{
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microblaze_disable_icache();
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microblaze_disable_dcache();
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/* init hardware console */
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/* init hardware console */
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rt_hw_console_init();
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rt_hw_console_init();
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/* timer init */
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/* timer init */
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rt_tmr_init();
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rt_tmr_init();
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}
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}
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#define __BOARD_H__
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#define __BOARD_H__
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#define MCK 50000000
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void rt_hw_board_led_on(rt_uint32_t);
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void rt_hw_board_led_on(rt_uint32_t);
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void rt_hw_board_led_off(rt_uint32_t);
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void rt_hw_board_led_off(rt_uint32_t);
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@ -16,6 +16,7 @@
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/* Tick per Second*/
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/* Tick per Second*/
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#define RT_TICK_PER_SECOND 100
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#define RT_TICK_PER_SECOND 100
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/* SECTION: RT_DEBUG */
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/* SECTION: RT_DEBUG */
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/* Thread Debug*/
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/* Thread Debug*/
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/* #define RT_THREAD_DEBUG */
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/* #define RT_THREAD_DEBUG */
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@ -88,6 +89,7 @@
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#define FINSH_THREAD_STACK_SIZE 8192
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#define FINSH_THREAD_STACK_SIZE 8192
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#define RT_USING_TC
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#define RT_USING_TC
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/* SECTION: a runtime libc library */
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/* SECTION: a runtime libc library */
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/* a runtime libc library*/
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/* a runtime libc library*/
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/* #define RT_USING_NEWLIB */
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/* #define RT_USING_NEWLIB */
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@ -25,6 +25,7 @@ extern void finsh_system_init(void);
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extern void rt_hw_led_flash(void);
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extern void rt_hw_led_flash(void);
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/*@{*/
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/*@{*/
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#ifdef __CC_ARM
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#ifdef __CC_ARM
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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@ -70,6 +71,7 @@ void rtthread_startup(void)
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rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
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rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
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#else
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#else
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rt_system_heap_init((void*)&__bss_end, (void*)(&__bss_end+0x4000));
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rt_system_heap_init((void*)&__bss_end, (void*)(&__bss_end+0x4000));
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#endif
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#endif
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#endif
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#endif
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@ -131,7 +131,7 @@ int _tc_thread_delete()
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tc_cleanup(_tc_cleanup);
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tc_cleanup(_tc_cleanup);
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thread_delete_init();
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thread_delete_init();
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return 25;
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return 27;
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}
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}
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FINSH_FUNCTION_EXPORT(_tc_thread_delete, a thread delete example);
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FINSH_FUNCTION_EXPORT(_tc_thread_delete, a thread delete example);
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#else
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#else
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static char thread1_stack[THREAD_STACK_SIZE];
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static char thread1_stack[THREAD_STACK_SIZE];
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static char thread2_stack[THREAD_STACK_SIZE];
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static char thread2_stack[THREAD_STACK_SIZE];
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static rt_uint32_t t1_count = 0;
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volatile static rt_uint32_t t1_count = 0;
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static rt_uint32_t t2_count = 0;
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volatile static rt_uint32_t t2_count = 0;
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static void thread1_entry(void* parameter)
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static void thread1_entry(void* parameter)
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{
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{
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while (1)
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while (1)
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/* unlock scheduler */
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/* unlock scheduler */
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rt_exit_critical();
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rt_exit_critical();
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rt_kprintf("t1_count=%d t2_count=%d\n",t1_count,t2_count);
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if (t1_count / t2_count != 2)
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if (t1_count / t2_count != 2)
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tc_stat(TC_STAT_END | TC_STAT_FAILED);
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tc_stat(TC_STAT_END | TC_STAT_FAILED);
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else
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tc_done(TC_STAT_PASSED);
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}
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}
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int _tc_thread_same_priority()
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int _tc_thread_same_priority()
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@ -44,7 +44,6 @@ rt_hw_interrupt_disable:
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RTSD r15, 8
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RTSD r15, 8
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AND r0, r0, r0
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AND r0, r0, r0
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.end rt_hw_interrupt_disable
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.end rt_hw_interrupt_disable
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/*
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/*
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rt_hw_interrupt_enable:
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rt_hw_interrupt_enable:
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RTSD r15, 8
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RTSD r15, 8
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MTS rMSR, r5 /* Move the saved status from r5 into rMSR */
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MTS rMSR, r5 /* Move the saved status from r5 into rMSR */
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.end rt_hw_interrupt_enable
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.end rt_hw_interrupt_enable
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/*
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/*
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ADDIK r1, r1, STACK_SIZE
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ADDIK r1, r1, STACK_SIZE
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RTID r14, 0 /* IE bit will be set automatically */
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RTID r14, 0 /* IE bit will be set automatically */
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AND r0, r0, r0
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AND r0, r0, r0
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.end rt_hw_context_switch
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.end rt_hw_context_switch
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/*
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/*
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SWI r6, r3, 0 /* rt_interrupt_to_thread = to */
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SWI r6, r3, 0 /* rt_interrupt_to_thread = to */
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RTSD r15, 8
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RTSD r15, 8
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AND r0, r0, r0
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AND r0, r0, r0
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.end rt_hw_context_switch_interrupt
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.end rt_hw_context_switch_interrupt
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.globl _interrupt_handler
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.globl _interrupt_handler
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.section .text
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.align 2
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.align 2
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.ent _interrupt_handler
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.ent _interrupt_handler
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.type _interrupt_handler, @function
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.type _interrupt_handler, @function
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@ -99,7 +99,8 @@ static rt_err_t rt_serial_init(rt_device_t dev)
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RT_ASSERT(serial != RT_NULL);
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RT_ASSERT(serial != RT_NULL);
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RT_ASSERT(serial->peripheral_id != XPAR_INTC_0_UARTLITE_1_VEC_ID);
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RT_ASSERT(serial->peripheral_id != XPAR_UARTLITE_1_DEVICE_ID);
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/* reset rx index */
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/* reset rx index */
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serial->save_index = 0;
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serial->save_index = 0;
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@ -168,7 +169,8 @@ static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_
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serial->read_index ++;
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serial->read_index ++;
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if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
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if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
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serial->read_index = 0;
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serial->read_index = 0;
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} else
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}
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else
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{
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{
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/* no data in rx buffer */
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/* no data in rx buffer */
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@ -180,23 +182,23 @@ static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_
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/* enable interrupt */
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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rt_hw_interrupt_enable(level);
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ptr++;
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ptr ++; size --;
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size--;
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}
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}
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return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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} else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
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}
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else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
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{
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{
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/* not support right now */
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/* not support right now */
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RT_ASSERT(0);
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RT_ASSERT(0);
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} else
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}
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else
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{
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{
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/* poll mode */
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/* poll mode */
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while (size)
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while (size)
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{
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{
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/* Wait for Full Rx Buffer */
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/* Wait for Full Rx Buffer */
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while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA))
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while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA));
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;
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/* Read Character */
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/* Read Character */
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*ptr = serial->hw_base->Rx_FIFO;
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*ptr = serial->hw_base->Rx_FIFO;
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@ -227,8 +229,7 @@ static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buff
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/* stream mode */
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/* stream mode */
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if (*ptr == '\n')
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if (*ptr == '\n')
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{
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{
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while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY))
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while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
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;
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serial->hw_base->Tx_FIFO = '\r';
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serial->hw_base->Tx_FIFO = '\r';
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}
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}
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@ -237,8 +238,11 @@ static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buff
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/* Transmit Character */
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/* Transmit Character */
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serial->hw_base->Tx_FIFO = *ptr;
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serial->hw_base->Tx_FIFO = *ptr;
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ptr++;
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if (*ptr & 1)
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size--;
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rt_hw_board_led_on(2);
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else
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rt_hw_board_led_off(2);
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ptr ++; size --;
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}
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}
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}
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}
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else
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else
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@ -246,13 +250,15 @@ static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buff
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while (size)
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while (size)
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{
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{
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/* Wait for Empty Tx Buffer */
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/* Wait for Empty Tx Buffer */
|
||||||
while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY))
|
while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
|
||||||
;
|
|
||||||
|
|
||||||
/* Transmit Character */
|
/* Transmit Character */
|
||||||
serial->hw_base->Tx_FIFO = *ptr;
|
serial->hw_base->Tx_FIFO = *ptr;
|
||||||
ptr++;
|
if (*ptr & 1)
|
||||||
size--;
|
rt_hw_board_led_on(2);
|
||||||
|
else
|
||||||
|
rt_hw_board_led_off(2);
|
||||||
|
ptr ++; size --;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -288,8 +294,8 @@ rt_err_t rt_hw_serial_init()
|
||||||
|
|
||||||
/* init serial device private data */
|
/* init serial device private data */
|
||||||
serial1.hw_base = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR;
|
serial1.hw_base = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR;
|
||||||
serial1.peripheral_id = XPAR_INTC_0_UARTLITE_1_VEC_ID;
|
serial1.peripheral_id = XPAR_UARTLITE_1_DEVICE_ID;
|
||||||
serial1.baudrate = 9600;
|
serial1.baudrate = 115200;
|
||||||
|
|
||||||
/* set device virtual interface */
|
/* set device virtual interface */
|
||||||
device->init = rt_serial_init;
|
device->init = rt_serial_init;
|
||||||
|
@ -303,6 +309,8 @@ rt_err_t rt_hw_serial_init()
|
||||||
rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
|
rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
return RT_EOK;
|
return RT_EOK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -16,6 +16,8 @@
|
||||||
extern void *_SDA_BASE_;
|
extern void *_SDA_BASE_;
|
||||||
extern void *_SDA2_BASE_;
|
extern void *_SDA2_BASE_;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* This function will initialize thread stack
|
* This function will initialize thread stack
|
||||||
*
|
*
|
||||||
|
@ -26,7 +28,8 @@ extern void *_SDA2_BASE_;
|
||||||
*
|
*
|
||||||
* @return stack address
|
* @return stack address
|
||||||
*/
|
*/
|
||||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
|
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||||
|
rt_uint8_t *stack_addr, void *texit)
|
||||||
{
|
{
|
||||||
unsigned long *stk;
|
unsigned long *stk;
|
||||||
|
|
||||||
|
|
|
@ -20,14 +20,17 @@
|
||||||
#include "xintc_i.h"
|
#include "xintc_i.h"
|
||||||
#include "xintc_l.h"
|
#include "xintc_l.h"
|
||||||
|
|
||||||
|
|
||||||
#define MAX_HANDLERS XPAR_INTC_MAX_NUM_INTR_INPUTS
|
#define MAX_HANDLERS XPAR_INTC_MAX_NUM_INTR_INPUTS
|
||||||
extern XIntc int_ctl; /* The instance of the Interrupt Controller */
|
extern XIntc int_ctl; /* The instance of the Interrupt Controller */
|
||||||
|
|
||||||
|
|
||||||
extern rt_uint32_t rt_interrupt_nest;
|
extern rt_uint32_t rt_interrupt_nest;
|
||||||
|
|
||||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||||
|
|
||||||
|
|
||||||
void rt_hw_interrupt_handler(int vector)
|
void rt_hw_interrupt_handler(int vector)
|
||||||
{
|
{
|
||||||
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
||||||
|
@ -42,8 +45,10 @@ void rt_hw_interrupt_init()
|
||||||
|
|
||||||
XIntc_Config *CfgPtr;
|
XIntc_Config *CfgPtr;
|
||||||
|
|
||||||
|
|
||||||
CfgPtr = &XIntc_ConfigTable[0];
|
CfgPtr = &XIntc_ConfigTable[0];
|
||||||
|
|
||||||
|
|
||||||
for (index = 0; index < MAX_HANDLERS; index ++)
|
for (index = 0; index < MAX_HANDLERS; index ++)
|
||||||
{
|
{
|
||||||
CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler;
|
CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler;
|
||||||
|
@ -89,10 +94,8 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha
|
||||||
|
|
||||||
if(vector >= 0 && vector < MAX_HANDLERS)
|
if(vector >= 0 && vector < MAX_HANDLERS)
|
||||||
{
|
{
|
||||||
if (*old_handler != RT_NULL)
|
if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler;
|
||||||
*old_handler = (rt_isr_handler_t) CfgPtr->HandlerTable[vector].Handler;
|
if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler;
|
||||||
if (new_handler != RT_NULL)
|
|
||||||
CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler) new_handler;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -125,6 +128,7 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha
|
||||||
*
|
*
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
void rt_hw_trap_irq(void )
|
void rt_hw_trap_irq(void )
|
||||||
{
|
{
|
||||||
u32 intr_status;
|
u32 intr_status;
|
||||||
|
@ -133,6 +137,7 @@ void rt_hw_trap_irq(void)
|
||||||
volatile u32 reg; /* used as bit bucket */
|
volatile u32 reg; /* used as bit bucket */
|
||||||
XIntc_Config *cfg_ptr;
|
XIntc_Config *cfg_ptr;
|
||||||
|
|
||||||
|
|
||||||
/* Get the configuration data using the device ID */
|
/* Get the configuration data using the device ID */
|
||||||
cfg_ptr = &XIntc_ConfigTable[0];
|
cfg_ptr = &XIntc_ConfigTable[0];
|
||||||
|
|
||||||
|
@ -203,3 +208,4 @@ void rt_hw_trap_irq(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue